# mcause.rs - source
Source of the Rust file `/home/runner/.cargo/git/checkouts/riscv-ab2abd16c438337b/11d43cf/src/register/mcause.rs`.
Keywords: rust, rustlang, rust-lang

    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    69
    70
    71
    72
    73
    74
    75
    76
    77
    78
    79
    80
    81
    82
    83
    84
    85
    86
    87
    88
    89
    90
    91
    92
    93
    94
    95
    96
    97
    98
    99
    100
    101
    102
    103
    104
    105
    106
    107
    108
    109
    110
    111
    112
    113
    114
    115
    116
    117
    118
    119
    120
    121
    122
    123
    124
    125
    126
    127
    128
    129
    130
    131
    132
    133
    134
    135
    136
    137
    138

    //! mcause register

    /// mcause register
    #[derive(Clone, Copy, Debug)]
    pub struct Mcause {
        bits: usize,
    }

    /// Trap Cause
    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
    pub enum Trap {
        Interrupt(Interrupt),
        Exception(Exception),
    }

    /// Interrupt
    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
    pub enum Interrupt {
        UserSoft,
        SupervisorSoft,
        MachineSoft,
        UserTimer,
        SupervisorTimer,
        MachineTimer,
        UserExternal,
        SupervisorExternal,
        MachineExternal,
        Unknown,
    }

    /// Exception
    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
    pub enum Exception {
        InstructionMisaligned,
        InstructionFault,
        IllegalInstruction,
        Breakpoint,
        LoadMisaligned,
        LoadFault,
        StoreMisaligned,
        StoreFault,
        UserEnvCall,
        SupervisorEnvCall,
        MachineEnvCall,
        InstructionPageFault,
        LoadPageFault,
        StorePageFault,
        Unknown,
    }

    impl Interrupt {
        pub fn from(nr: usize) -> Self {
            match nr {
                0 => Interrupt::UserSoft,
                1 => Interrupt::SupervisorSoft,
                3 => Interrupt::MachineSoft,
                4 => Interrupt::UserTimer,
                5 => Interrupt::SupervisorTimer,
                7 => Interrupt::MachineTimer,
                8 => Interrupt::UserExternal,
                9 => Interrupt::SupervisorExternal,
                11 => Interrupt::MachineExternal,
                _ => Interrupt::Unknown,
            }
        }
    }

    impl Exception {
        pub fn from(nr: usize) -> Self {
            match nr {
                0 => Exception::InstructionMisaligned,
                1 => Exception::InstructionFault,
                2 => Exception::IllegalInstruction,
                3 => Exception::Breakpoint,
                4 => Exception::LoadMisaligned,
                5 => Exception::LoadFault,
                6 => Exception::StoreMisaligned,
                7 => Exception::StoreFault,
                8 => Exception::UserEnvCall,
                9 => Exception::SupervisorEnvCall,
                11 => Exception::MachineEnvCall,
                12 => Exception::InstructionPageFault,
                13 => Exception::LoadPageFault,
                15 => Exception::StorePageFault,
                _ => Exception::Unknown,
            }
        }
    }
    impl Mcause {
        /// Returns the contents of the register as raw bits
        #[inline]
        pub fn bits(&self) -> usize {
            self.bits
        }

        /// Returns the code field
        pub fn code(&self) -> usize {
            match () {
                #[cfg(target_pointer_width = "32")]
                () => self.bits & !(1 << 31),
                #[cfg(target_pointer_width = "64")]
                () => self.bits & !(1 << 63),
                #[cfg(target_pointer_width = "128")]
                () => self.bits & !(1 << 127),
            }
        }

        /// Trap Cause
        #[inline]
        pub fn cause(&self) -> Trap {
            if self.is_interrupt() {
                Trap::Interrupt(Interrupt::from(self.code()))
            } else {
                Trap::Exception(Exception::from(self.code()))
            }
        }

        /// Is trap cause an interrupt.
        #[inline]
        pub fn is_interrupt(&self) -> bool {
            match () {
                #[cfg(target_pointer_width = "32")]
                () => self.bits & (1 << 31) == 1 << 31,
                #[cfg(target_pointer_width = "64")]
                () => self.bits & (1 << 63) == 1 << 63,
                #[cfg(target_pointer_width = "128")]
                () => self.bits & (1 << 127) == 1 << 127,
            }
        }

        /// Is trap cause an exception.
        #[inline]
        pub fn is_exception(&self) -> bool {
            !self.is_interrupt()
        }
    }

    read_csr_as!(Mcause, 0x342, __read_mcause);