# k210_pac::sysctl::clk_th0 - Rust
Clock threshold controller 0
Keywords: rust, rustlang, rust-lang, clk_th0

# Module k210_pac::sysctl::clk_th0

source · [−]
Expand description

Clock threshold controller 0

## Structs

AI_GCLK_W

Write proxy for field `ai_gclk`

DVP_GCLK_W

Write proxy for field `dvp_gclk`

ROM_GCLK_W

Write proxy for field `rom_gclk`

SRAM0_GCLK_W

Write proxy for field `sram0_gclk`

SRAM1_GCLK_W

Write proxy for field `sram1_gclk`

## Type Definitions

AI_GCLK_R

Reader of field `ai_gclk`

DVP_GCLK_R

Reader of field `dvp_gclk`

R

Reader of register clk_th0

ROM_GCLK_R

Reader of field `rom_gclk`

SRAM0_GCLK_R

Reader of field `sram0_gclk`

SRAM1_GCLK_R

Reader of field `sram1_gclk`

W

Writer for register clk_th0