# CLK_SEL0 in k210_pac::sysctl - Rust
Clock select controller 0
Keywords: rust, rustlang, rust-lang, CLK_SEL0

# Type Definition k210_pac::sysctl::CLK_SEL0

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    pub type CLK_SEL0 = Reg<u32, _CLK_SEL0>;

Expand description

Clock select controller 0

This register you can `read`, `reset`, `write`, `write_with_zero`, `modify`. See API.

For information about available fields see clk_sel0 module

## Trait Implementations

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### impl ResetValue for CLK_SEL0

Register clk_sel0 `reset()`’s with value 0

#### type Type = u32

Raw register type (`u8`, `u16`, `u32`, …).

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#### fn reset_value() -> Self::Type

Reset value of the register.

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### impl Readable for CLK_SEL0

`read()` method returns clk_sel0::R reader structure

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### impl Writable for CLK_SEL0

`write(|w| ..)` method takes clk_sel0::W writer structure