initSidebarItems({"struct":[["AES_CLK_EN_W","Write proxy for field `aes_clk_en`"],["AI_CLK_EN_W","Write proxy for field `ai_clk_en`"],["DMA_CLK_EN_W","Write proxy for field `dma_clk_en`"],["DVP_CLK_EN_W","Write proxy for field `dvp_clk_en`"],["FFT_CLK_EN_W","Write proxy for field `fft_clk_en`"],["FPIOA_CLK_EN_W","Write proxy for field `fpioa_clk_en`"],["GPIO_CLK_EN_W","Write proxy for field `gpio_clk_en`"],["I2C0_CLK_EN_W","Write proxy for field `i2c0_clk_en`"],["I2C1_CLK_EN_W","Write proxy for field `i2c1_clk_en`"],["I2C2_CLK_EN_W","Write proxy for field `i2c2_clk_en`"],["I2S0_CLK_EN_W","Write proxy for field `i2s0_clk_en`"],["I2S1_CLK_EN_W","Write proxy for field `i2s1_clk_en`"],["I2S2_CLK_EN_W","Write proxy for field `i2s2_clk_en`"],["OTP_CLK_EN_W","Write proxy for field `otp_clk_en`"],["ROM_CLK_EN_W","Write proxy for field `rom_clk_en`"],["RTC_CLK_EN_W","Write proxy for field `rtc_clk_en`"],["SHA_CLK_EN_W","Write proxy for field `sha_clk_en`"],["SPI0_CLK_EN_W","Write proxy for field `spi0_clk_en`"],["SPI1_CLK_EN_W","Write proxy for field `spi1_clk_en`"],["SPI2_CLK_EN_W","Write proxy for field `spi2_clk_en`"],["SPI3_CLK_EN_W","Write proxy for field `spi3_clk_en`"],["TIMER0_CLK_EN_W","Write proxy for field `timer0_clk_en`"],["TIMER1_CLK_EN_W","Write proxy for field `timer1_clk_en`"],["TIMER2_CLK_EN_W","Write proxy for field `timer2_clk_en`"],["UART1_CLK_EN_W","Write proxy for field `uart1_clk_en`"],["UART2_CLK_EN_W","Write proxy for field `uart2_clk_en`"],["UART3_CLK_EN_W","Write proxy for field `uart3_clk_en`"],["WDT0_CLK_EN_W","Write proxy for field `wdt0_clk_en`"],["WDT1_CLK_EN_W","Write proxy for field `wdt1_clk_en`"]],"type":[["AES_CLK_EN_R","Reader of field `aes_clk_en`"],["AI_CLK_EN_R","Reader of field `ai_clk_en`"],["DMA_CLK_EN_R","Reader of field `dma_clk_en`"],["DVP_CLK_EN_R","Reader of field `dvp_clk_en`"],["FFT_CLK_EN_R","Reader of field `fft_clk_en`"],["FPIOA_CLK_EN_R","Reader of field `fpioa_clk_en`"],["GPIO_CLK_EN_R","Reader of field `gpio_clk_en`"],["I2C0_CLK_EN_R","Reader of field `i2c0_clk_en`"],["I2C1_CLK_EN_R","Reader of field `i2c1_clk_en`"],["I2C2_CLK_EN_R","Reader of field `i2c2_clk_en`"],["I2S0_CLK_EN_R","Reader of field `i2s0_clk_en`"],["I2S1_CLK_EN_R","Reader of field `i2s1_clk_en`"],["I2S2_CLK_EN_R","Reader of field `i2s2_clk_en`"],["OTP_CLK_EN_R","Reader of field `otp_clk_en`"],["R","Reader of register clk_en_peri"],["ROM_CLK_EN_R","Reader of field `rom_clk_en`"],["RTC_CLK_EN_R","Reader of field `rtc_clk_en`"],["SHA_CLK_EN_R","Reader of field `sha_clk_en`"],["SPI0_CLK_EN_R","Reader of field `spi0_clk_en`"],["SPI1_CLK_EN_R","Reader of field `spi1_clk_en`"],["SPI2_CLK_EN_R","Reader of field `spi2_clk_en`"],["SPI3_CLK_EN_R","Reader of field `spi3_clk_en`"],["TIMER0_CLK_EN_R","Reader of field `timer0_clk_en`"],["TIMER1_CLK_EN_R","Reader of field `timer1_clk_en`"],["TIMER2_CLK_EN_R","Reader of field `timer2_clk_en`"],["UART1_CLK_EN_R","Reader of field `uart1_clk_en`"],["UART2_CLK_EN_R","Reader of field `uart2_clk_en`"],["UART3_CLK_EN_R","Reader of field `uart3_clk_en`"],["W","Writer for register clk_en_peri"],["WDT0_CLK_EN_R","Reader of field `wdt0_clk_en`"],["WDT1_CLK_EN_R","Reader of field `wdt1_clk_en`"]]});