initSidebarItems({"mod":[["baudr","Baud Rate Select"],["ctrlr0","Control Register 0"],["ctrlr1","Control Register 1"],["dmacr","DMA Control Register"],["dmardlr","DMA Receive Data Level"],["dmatdlr","DMA Transmit Data Level"],["dr","Data Register"],["endian","ENDIAN"],["icr","Interrupt Clear Register"],["idr","Identification Register"],["imr","Interrupt Mask Register"],["isr","Interrupt Status Register"],["msticr","Multi-Master Interrupt Clear Register"],["mwcr","Microwire Control Register"],["risr","Raw Interrupt Status Register"],["rx_sample_delay","RX Sample Delay Register"],["rxflr","Receive FIFO Level Register"],["rxftlr","Receive FIFO Threshold Level"],["rxoicr","Receive FIFO Overflow Interrupt Clear Register"],["rxuicr","Receive FIFO Underflow Interrupt Clear Register"],["ser","Slave Enable Register"],["spi_ctrlr0","SPI Control Register"],["sr","Status Register"],["ssic_version_id","DWC_ssi component version"],["ssienr","Enable Register"],["txflr","Transmit FIFO Level Register"],["txftlr","Transmit FIFO Threshold Level"],["txoicr","Transmit FIFO Overflow Interrupt Clear Register"],["xip_cnt_time_out","XIP time out register for continuous transfers"],["xip_ctrl","XIP Control Register"],["xip_incr_inst","XIP INCR transfer opcode"],["xip_mode_bits","XIP Mode bits"],["xip_ser","XIP Slave Enable Register"],["xip_wrap_inst","XIP WRAP transfer opcode"],["xrxoicr","XIP Receive FIFO Overflow Interrupt Clear Register"]],"struct":[["RegisterBlock","Register block"]],"type":[["BAUDR","Baud Rate Select"],["CTRLR0","Control Register 0"],["CTRLR1","Control Register 1"],["DMACR","DMA Control Register"],["DMARDLR","DMA Receive Data Level"],["DMATDLR","DMA Transmit Data Level"],["DR","Data Register"],["ENDIAN","ENDIAN"],["ICR","Interrupt Clear Register"],["IDR","Identification Register"],["IMR","Interrupt Mask Register"],["ISR","Interrupt Status Register"],["MSTICR","Multi-Master Interrupt Clear Register"],["MWCR","Microwire Control Register"],["RISR","Raw Interrupt Status Register"],["RXFLR","Receive FIFO Level Register"],["RXFTLR","Receive FIFO Threshold Level"],["RXOICR","Receive FIFO Overflow Interrupt Clear Register"],["RXUICR","Receive FIFO Underflow Interrupt Clear Register"],["RX_SAMPLE_DELAY","RX Sample Delay Register"],["SER","Slave Enable Register"],["SPI_CTRLR0","SPI Control Register"],["SR","Status Register"],["SSIC_VERSION_ID","DWC_ssi component version"],["SSIENR","Enable Register"],["TXFLR","Transmit FIFO Level Register"],["TXFTLR","Transmit FIFO Threshold Level"],["TXOICR","Transmit FIFO Overflow Interrupt Clear Register"],["XIP_CNT_TIME_OUT","XIP time out register for continuous transfers"],["XIP_CTRL","XIP Control Register"],["XIP_INCR_INST","XIP INCR transfer opcode"],["XIP_MODE_BITS","XIP Mode bits"],["XIP_SER","XIP Slave Enable Register"],["XIP_WRAP_INST","XIP WRAP transfer opcode"],["XRXOICR","XIP Receive FIFO Overflow Interrupt Clear Register"]]});