# k210_pac::sysctl::clk_sel0 - Rust
Clock select controller 0
Keywords: rust, rustlang, rust-lang, clk_sel0

# Module k210_pac::sysctl::clk_sel0

source · [−]
Expand description

Clock select controller 0

## Structs

ACLK_DIVIDER_SEL_W

Write proxy for field `aclk_divider_sel`

ACLK_SEL_W

Write proxy for field `aclk_sel`

APB0_CLK_SEL_W

Write proxy for field `apb0_clk_sel`

APB1_CLK_SEL_W

Write proxy for field `apb1_clk_sel`

APB2_CLK_SEL_W

Write proxy for field `apb2_clk_sel`

SPI3_CLK_SEL_W

Write proxy for field `spi3_clk_sel`

TIMER0_CLK_SEL_W

Write proxy for field `timer0_clk_sel`

TIMER1_CLK_SEL_W

Write proxy for field `timer1_clk_sel`

TIMER2_CLK_SEL_W

Write proxy for field `timer2_clk_sel`

## Type Definitions

ACLK_DIVIDER_SEL_R

Reader of field `aclk_divider_sel`

ACLK_SEL_R

Reader of field `aclk_sel`

APB0_CLK_SEL_R

Reader of field `apb0_clk_sel`

APB1_CLK_SEL_R

Reader of field `apb1_clk_sel`

APB2_CLK_SEL_R

Reader of field `apb2_clk_sel`

R

Reader of register clk_sel0

SPI3_CLK_SEL_R

Reader of field `spi3_clk_sel`

TIMER0_CLK_SEL_R

Reader of field `timer0_clk_sel`

TIMER1_CLK_SEL_R

Reader of field `timer1_clk_sel`

TIMER2_CLK_SEL_R

Reader of field `timer2_clk_sel`

W

Writer for register clk_sel0