initSidebarItems({"struct":[["AES_RESET_W","Write proxy for field `aes_reset`"],["AI_RESET_W","Write proxy for field `ai_reset`"],["DMA_RESET_W","Write proxy for field `dma_reset`"],["DVP_RESET_W","Write proxy for field `dvp_reset`"],["FFT_RESET_W","Write proxy for field `fft_reset`"],["FPIOA_RESET_W","Write proxy for field `fpioa_reset`"],["GPIO_RESET_W","Write proxy for field `gpio_reset`"],["I2C0_RESET_W","Write proxy for field `i2c0_reset`"],["I2C1_RESET_W","Write proxy for field `i2c1_reset`"],["I2C2_RESET_W","Write proxy for field `i2c2_reset`"],["I2S0_RESET_W","Write proxy for field `i2s0_reset`"],["I2S1_RESET_W","Write proxy for field `i2s1_reset`"],["I2S2_RESET_W","Write proxy for field `i2s2_reset`"],["ROM_RESET_W","Write proxy for field `rom_reset`"],["RTC_RESET_W","Write proxy for field `rtc_reset`"],["SHA_RESET_W","Write proxy for field `sha_reset`"],["SPI0_RESET_W","Write proxy for field `spi0_reset`"],["SPI1_RESET_W","Write proxy for field `spi1_reset`"],["SPI2_RESET_W","Write proxy for field `spi2_reset`"],["SPI3_RESET_W","Write proxy for field `spi3_reset`"],["TIMER0_RESET_W","Write proxy for field `timer0_reset`"],["TIMER1_RESET_W","Write proxy for field `timer1_reset`"],["TIMER2_RESET_W","Write proxy for field `timer2_reset`"],["UART1_RESET_W","Write proxy for field `uart1_reset`"],["UART2_RESET_W","Write proxy for field `uart2_reset`"],["UART3_RESET_W","Write proxy for field `uart3_reset`"],["WDT0_RESET_W","Write proxy for field `wdt0_reset`"],["WDT1_RESET_W","Write proxy for field `wdt1_reset`"]],"type":[["AES_RESET_R","Reader of field `aes_reset`"],["AI_RESET_R","Reader of field `ai_reset`"],["DMA_RESET_R","Reader of field `dma_reset`"],["DVP_RESET_R","Reader of field `dvp_reset`"],["FFT_RESET_R","Reader of field `fft_reset`"],["FPIOA_RESET_R","Reader of field `fpioa_reset`"],["GPIO_RESET_R","Reader of field `gpio_reset`"],["I2C0_RESET_R","Reader of field `i2c0_reset`"],["I2C1_RESET_R","Reader of field `i2c1_reset`"],["I2C2_RESET_R","Reader of field `i2c2_reset`"],["I2S0_RESET_R","Reader of field `i2s0_reset`"],["I2S1_RESET_R","Reader of field `i2s1_reset`"],["I2S2_RESET_R","Reader of field `i2s2_reset`"],["R","Reader of register peri_reset"],["ROM_RESET_R","Reader of field `rom_reset`"],["RTC_RESET_R","Reader of field `rtc_reset`"],["SHA_RESET_R","Reader of field `sha_reset`"],["SPI0_RESET_R","Reader of field `spi0_reset`"],["SPI1_RESET_R","Reader of field `spi1_reset`"],["SPI2_RESET_R","Reader of field `spi2_reset`"],["SPI3_RESET_R","Reader of field `spi3_reset`"],["TIMER0_RESET_R","Reader of field `timer0_reset`"],["TIMER1_RESET_R","Reader of field `timer1_reset`"],["TIMER2_RESET_R","Reader of field `timer2_reset`"],["UART1_RESET_R","Reader of field `uart1_reset`"],["UART2_RESET_R","Reader of field `uart2_reset`"],["UART3_RESET_R","Reader of field `uart3_reset`"],["W","Writer for register peri_reset"],["WDT0_RESET_R","Reader of field `wdt0_reset`"],["WDT1_RESET_R","Reader of field `wdt1_reset`"]]});