diff --git a/os/Cargo.toml b/os/Cargo.toml index 5652cd26..462349ad 100644 --- a/os/Cargo.toml +++ b/os/Cargo.toml @@ -7,16 +7,17 @@ edition = "2018" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] } lazy_static = { version = "1.4.0", features = ["spin_no_std"] } buddy_system_allocator = "0.6" bitflags = "1.2.1" xmas-elf = "0.7.0" -virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers" } -k210-pac = { git = "https://github.com/wyfcyx/k210-pac" } -k210-hal = { git = "https://github.com/wyfcyx/k210-hal" } -k210-soc = { git = "https://github.com/wyfcyx/k210-soc" } + easy-fs = { path = "../easy-fs" } +riscv = { path = "../third-party/riscv", features = ["inline-asm"] } +virtio-drivers = { path = "../third-party/virtio-drivers" } +k210-pac = { path = "../third-party/k210-pac" } +k210-hal = { path = "../third-party/k210-hal" } +k210-soc = { path = "../third-party/k210-soc" } [features] board_qemu = [] diff --git a/third-party/k210-hal/.github/workflows/clippy-check.yml b/third-party/k210-hal/.github/workflows/clippy-check.yml new file mode 100644 index 00000000..40cdbb79 --- /dev/null +++ b/third-party/k210-hal/.github/workflows/clippy-check.yml @@ -0,0 +1,16 @@ +on: [push, pull_request] +name: Clippy Check + +jobs: + clippy_check: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + toolchain: nightly + components: clippy + override: true + - uses: actions-rs/clippy-check@v1 + with: + token: ${{ secrets.GITHUB_TOKEN }} diff --git a/third-party/k210-hal/.github/workflows/cross-compile.yml b/third-party/k210-hal/.github/workflows/cross-compile.yml new file mode 100644 index 00000000..8bc14561 --- /dev/null +++ b/third-party/k210-hal/.github/workflows/cross-compile.yml @@ -0,0 +1,19 @@ +on: [push, pull_request] +name: Cross Compile + +jobs: + build: + name: Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + toolchain: stable + target: riscv64gc-unknown-none-elf + override: true + - uses: actions-rs/cargo@v1 + with: + use-cross: true + command: build + args: --target riscv64gc-unknown-none-elf diff --git a/third-party/k210-hal/.github/workflows/security-audit.yml b/third-party/k210-hal/.github/workflows/security-audit.yml new file mode 100644 index 00000000..fa5006a5 --- /dev/null +++ b/third-party/k210-hal/.github/workflows/security-audit.yml @@ -0,0 +1,12 @@ +name: Security Audit +on: + schedule: + - cron: '0 0 * * *' +jobs: + audit: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v1 + - uses: actions-rs/audit-check@v1 + with: + token: ${{ secrets.GITHUB_TOKEN }} diff --git a/third-party/k210-hal/.gitignore b/third-party/k210-hal/.gitignore new file mode 100644 index 00000000..2f88dbac --- /dev/null +++ b/third-party/k210-hal/.gitignore @@ -0,0 +1,3 @@ +/target +**/*.rs.bk +Cargo.lock \ No newline at end of file diff --git a/third-party/k210-hal/CODE_OF_CONDUCT.md b/third-party/k210-hal/CODE_OF_CONDUCT.md new file mode 100644 index 00000000..fccadf9a --- /dev/null +++ b/third-party/k210-hal/CODE_OF_CONDUCT.md @@ -0,0 +1,37 @@ +# The Rust Code of Conduct + +## Conduct + +**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team) + +* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic. +* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all. +* Please be kind and courteous. There's no need to be mean or rude. +* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer. +* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works. +* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups. +* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back. +* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome. + +## Moderation + +These are the policies for upholding our community's standards of conduct. + +1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.) +2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed. +3. Moderators will first respond to such remarks with a warning. +4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off. +5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded. +6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology. +7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed. +8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others. + +In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely. + +And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust. + +The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org). + +*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).* + +[team]: https://github.com/rust-embedded/wg#the-riscv-team diff --git a/third-party/k210-hal/Cargo.toml b/third-party/k210-hal/Cargo.toml new file mode 100644 index 00000000..e41adf1e --- /dev/null +++ b/third-party/k210-hal/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "k210-hal" +version = "0.2.0" +authors = ["The RISC-V Team "] +categories = ["embedded", "hardware-support", "no-std"] +description = "Hardware Abstract Layer (HAL) support for K210, dual-core RV64GC SoC" +repository = "https://github.com/riscv-rust/k210-hal" +keywords = ["riscv", "k210", "hal"] +license = "ISC" +edition = "2018" + +[package.metadata.docs.rs] +targets = ["riscv64gc-unknown-none-elf"] + +[dependencies] +embedded-hal = "=1.0.0-alpha.1" +nb = "0.1.1" +k210-pac = { path = "../k210-pac" } +bitflags = "1.2.1" diff --git a/third-party/k210-hal/README.md b/third-party/k210-hal/README.md new file mode 100644 index 00000000..a56269f3 --- /dev/null +++ b/third-party/k210-hal/README.md @@ -0,0 +1,37 @@ +[![crates.io](https://img.shields.io/crates/d/k210-hal.svg)](https://crates.io/crates/k210-hal) +[![crates.io](https://img.shields.io/crates/v/k210-hal.svg)](https://crates.io/crates/k210-hal) +[![Build Status](https://travis-ci.org/riscv-rust/k210-hal.svg?branch=master)](https://travis-ci.org/riscv-rust/k210-hal) + +# `k210-hal` + +> Hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware +> accelerated AI peripherals. + +This project is developed and maintained by the [RISC-V team][team]. + +## [Documentation](https://docs.rs/k210-hal) + +## License + +Copyright 2019 [RISC-V team][team] + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +## Code of Conduct + +Contribution to this crate is organized under the terms of the [Rust Code of +Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises +to intervene to uphold that code of conduct. + +[CoC]: CODE_OF_CONDUCT.md +[team]: https://github.com/rust-embedded/wg#the-risc-v-team diff --git a/third-party/k210-hal/src/aes.rs b/third-party/k210-hal/src/aes.rs new file mode 100644 index 00000000..f5c8f6f7 --- /dev/null +++ b/third-party/k210-hal/src/aes.rs @@ -0,0 +1,79 @@ +//! (TODO) Hardware AES calculator (AES) +use core::marker::PhantomData; +use crate::pac::AES; + +pub struct Aes { + aes: AES, + _mode: PhantomData, + _klen: PhantomData, +} + +pub struct Ecb; + +pub struct Cbc; + +pub struct Gcm; + +pub struct K128; + +pub struct K192; + +pub struct K256; + +#[allow(unused)] // todo: remove +impl Aes { + pub fn ecb128(aes: AES) -> Aes { + todo!() + } + + pub fn ecb192(aes: AES) -> Aes { + todo!() + } + + pub fn ecb256(aes: AES) -> Aes { + todo!() + } + + pub fn cbc128(aes: AES) -> Aes { + todo!() + } + + pub fn cbc192(aes: AES) -> Aes { + todo!() + } + + pub fn cbc256(aes: AES) -> Aes { + todo!() + } + + pub fn gcm128(aes: AES) -> Aes { + todo!() + } + + pub fn gcm192(aes: AES) -> Aes { + todo!() + } + + pub fn gcm256(aes: AES) -> Aes { + todo!() + } +} + +impl Aes { + // todo: clock + pub fn free(self) -> AES { + self.aes + } +} + +#[allow(unused)] // todo: remove +impl Aes { + // entrypt block in-place + pub fn encrypt_block(&self, block: &mut [u8], key: &[u8]) { + todo!() + } + // decrypt block in-place + pub fn decrypt_block(&self, block: &mut [u8], key: &[u8]) { + todo!() + } +} diff --git a/third-party/k210-hal/src/apu.rs b/third-party/k210-hal/src/apu.rs new file mode 100644 index 00000000..8f20054f --- /dev/null +++ b/third-party/k210-hal/src/apu.rs @@ -0,0 +1 @@ +//! (TODO) Audio Processor Unit (APU) diff --git a/third-party/k210-hal/src/cache.rs b/third-party/k210-hal/src/cache.rs new file mode 100644 index 00000000..aad82183 --- /dev/null +++ b/third-party/k210-hal/src/cache.rs @@ -0,0 +1,117 @@ +//! (TODO) Bypass cache +//! +//! Todo: verify this module! + +use core::slice; +use core::str; + +/// Convert a buffer or a pointer into ones with uncached address. +/// +/// Section 3.4.1, Kendryte K210 Datasheet +pub fn uncached(buf: T) -> T { + buf.uncache() +} + +/// Uncacheable buffer or pointer. +pub trait Uncache { + /// Convert this buffer or pointer to uncached addressed ones + fn uncache(self) -> Self; +} + +impl Uncache for &T { + #[inline] + fn uncache(self) -> Self { + let addr = self as *const T as usize; + assert_addr_cached(addr); + // note(unsafe): safe for source address is safe + unsafe { &*((addr - 0x4000_0000) as *const T) } + } +} + +impl Uncache for &mut T { + #[inline] + fn uncache(self) -> Self { + let addr = self as *mut T as usize; + assert_addr_cached(addr); + // note(unsafe): safe for source address is safe + unsafe { &mut *((addr - 0x4000_0000) as *mut T) } + } +} + +impl Uncache for &[T] { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *const T; + // note(unsafe): source address is safe; passing ownership + unsafe { slice::from_raw_parts(new_ptr, self.len()) } + } +} + +impl Uncache for &mut [T] { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *mut T; + // note(unsafe): source address is safe; passing ownership + unsafe { slice::from_raw_parts_mut(new_ptr, self.len()) } + } +} + +impl Uncache for &str { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *const u8; + // note(unsafe): source address is safe; passing ownership + let slice = unsafe { slice::from_raw_parts(new_ptr, self.len()) }; + // note(unsafe): source slice is guaranteed valid in UTF-8 + unsafe { str::from_utf8_unchecked(slice) } + } +} + +impl Uncache for &mut str { + #[inline] + fn uncache(self) -> Self { + let addr = self.as_ptr() as usize; + assert_addr_cached(addr); + let new_ptr = (addr - 0x4000_0000) as *mut u8; + // note(unsafe): source address is safe; passing ownership + let slice = unsafe { slice::from_raw_parts_mut(new_ptr, self.len()) }; + // note(unsafe): source slice is guaranteed valid in UTF-8 + unsafe { str::from_utf8_unchecked_mut(slice) } + } +} + +impl Uncache for *const T { + #[inline] + fn uncache(self) -> Self { + assert_addr_cached(self as usize); + (self as usize - 0x4000_0000) as *const T + } +} + +impl Uncache for *mut T { + #[inline] + fn uncache(self) -> Self { + assert_addr_cached(self as usize); + (self as usize - 0x4000_0000) as *mut T + } +} + +#[inline] +fn assert_addr_cached(addr: usize) { + /* + SRAM memory: 0x8000_0000 to 0x805F_FFFF + AI memory: 0x8060_0000 to 0x807F_FFFF + SRAM memory includes two parts: MEM0 and MEM1 + MEM0 memory: 0x8000_0000 to 0x803F_FFFF + MEM1 memory: 0x8040_0000 to 0x805F_FFFF + */ + // assure that memory is within SRAM or AI + // todo: should we exclude AI? + assert!(addr <= 0x807F_FFFF && addr >= 0x8000_0000); +} diff --git a/third-party/k210-hal/src/clint.rs b/third-party/k210-hal/src/clint.rs new file mode 100644 index 00000000..6f4bbec4 --- /dev/null +++ b/third-party/k210-hal/src/clint.rs @@ -0,0 +1,49 @@ +//! Core Local Interruptor (CLINT) +//! +//! TODO: Should this module designed in a somehow IP-core peripheral create? + +/// mtime register +pub mod mtime { + use crate::pac; + /// Read mtime register. + pub fn read() -> u64 { + unsafe { (*pac::CLINT::ptr()).mtime.read().bits() } + } +} + +/// msip register +pub mod msip { + use crate::pac; + + /// set IPI interrupt flag for one given hart + pub fn set_ipi(hart_id: usize) { + unsafe { + (*pac::CLINT::ptr()).msip[hart_id].write(|w| + w.bits(1)) + } + } + /// clear IPI interrupt flag for one given hart + pub fn clear_ipi(hart_id: usize) { + unsafe { + (*pac::CLINT::ptr()).msip[hart_id].write(|w| + w.bits(0)) + } + } +} + +/// mtimecmp register +pub mod mtimecmp { + use crate::pac; + + /// Read 64-bit mtimecmp register for certain hart id + pub fn read(hart_id: usize) -> u64 { + unsafe { (*pac::CLINT::ptr()).mtimecmp[hart_id].read().bits() } + } + + /// Write 64-bit mtimecmp register for certain hart id + pub fn write(hart_id: usize, bits: u64) { + // Volume II: RISC-V Privileged Architectures V1.10 p.31, figure 3.15 + unsafe { (*pac::CLINT::ptr()).mtimecmp[hart_id].write(|w| + w.bits(bits)) }; + } +} diff --git a/third-party/k210-hal/src/clock.rs b/third-party/k210-hal/src/clock.rs new file mode 100644 index 00000000..2798756e --- /dev/null +++ b/third-party/k210-hal/src/clock.rs @@ -0,0 +1,42 @@ +//! Clock configuration +//use crate::pac::PRCI; +use crate::time::Hertz; + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no +/// longer be changed. +#[derive(Clone, Copy)] +pub struct Clocks { + cpu: Hertz, + apb0: Hertz, +} + +impl Clocks { + #[doc(hidden)] + pub fn new() -> Self { +/* + [MAIXPY]Pll0:freq:806000000 + [MAIXPY]Pll1:freq:398666666 + [MAIXPY]Pll2:freq:45066666 + [MAIXPY]cpu:freq:403000000 + [MAIXPY]kpu:freq:398666666 + in freq: 26000000 + cpu_freq: 390000000 +*/ + Self { + cpu: Hertz(403_000_000), + apb0: Hertz(195_000_000), + } + } + + /// Returns CPU frequency + pub fn cpu(&self) -> Hertz { + Hertz(self.cpu.0) + } + + /// Returns APB0 frequency + pub fn apb0(&self) -> Hertz { + self.apb0 + } +} diff --git a/third-party/k210-hal/src/dmac.rs b/third-party/k210-hal/src/dmac.rs new file mode 100644 index 00000000..12811beb --- /dev/null +++ b/third-party/k210-hal/src/dmac.rs @@ -0,0 +1,34 @@ +//! (TODO) Direct Memory Access Controller (DMAC) +use crate::{pac, sysctl}; + +pub fn dmac_id() -> u64 { + unsafe { (*pac::DMAC::ptr()).id.read().bits() } +} + +pub fn dmac_version() -> u64 { + unsafe { (*pac::DMAC::ptr()).compver.read().bits() } +} + +pub trait DmacExt { + fn configure(self, /* sysctl ACLK clock */) -> Dmac; +} + +impl DmacExt for pac::DMAC { + fn configure(self, /* sysctl ACLK clock */) -> Dmac { + // enable + sysctl::clk_en_peri().modify(|_, w| w.dma_clk_en().set_bit()); + // todo: reset + Dmac {} // todo + } +} + +pub struct Dmac { + +} + +// pub struct C0 { +// // todo +// pub async fn poll() { + +// } +// } diff --git a/third-party/k210-hal/src/fft.rs b/third-party/k210-hal/src/fft.rs new file mode 100644 index 00000000..daa1d0de --- /dev/null +++ b/third-party/k210-hal/src/fft.rs @@ -0,0 +1 @@ +//! (TODO) Fast Fourier Transform (FFT) diff --git a/third-party/k210-hal/src/fpioa.rs b/third-party/k210-hal/src/fpioa.rs new file mode 100644 index 00000000..e1819442 --- /dev/null +++ b/third-party/k210-hal/src/fpioa.rs @@ -0,0 +1,486 @@ +//! Field Programmable IO Array (FPIOA) + +/* + new design: Split FPIOA into several IO pins (IO0, IO1, .., IO47) + with ownership of IOx struct we may change their functions. + For GPIOs and GPIOHS's we should split them into another GpioXx structs. + + note: other modules do not need to require for ownership of certain IOx struct + for that pins and peripherals are considered separate modules. + If this design results in inconvenience or violent of Rust's ownership role + please fire an issue to tell us. +*/ + +use crate::pac::FPIOA; +use crate::sysctl::{self, APB0}; +use core::marker::PhantomData; + +/// FPIOA function +pub trait Function { + const INDEX: u8; +} + +/// Pull direction +#[derive(Copy, Clone)] +pub enum Pull { + /// No pulls + None, + /// Pull down + Down, + /// Pull up + Up, +} + +/// FPIOA I/O Pin +pub trait IoPin { + const INDEX: u8; + + fn set_io_pull(&mut self, pull: Pull) { + unsafe { + let fpioa = &*FPIOA::ptr(); + fpioa.io[Self::INDEX as usize].modify(|_, w| match pull { + Pull::None => w.pu().bit(false).pd().bit(false), + Pull::Down => w.pu().bit(false).pd().bit(true), + Pull::Up => w.pu().bit(true).pd().bit(false), + }); + } + } +} + +/// Marker trait for I/O pin function detection +pub trait Mode {} + +/// Extension trait to split a FPIOA peripheral in independent pins and registers +pub trait FpioaExt { + /// Splits the FPIOA block into independent pins and registers + /// + /// todo: split sysctl into two apb's, then use the APB0 to split Fpioa + fn split(self, apb0: &mut APB0) -> Parts; +} + +/// All I/O pins +macro_rules! def_io_pin { + ($($IoX: ident: ($id: expr, $iox: ident, $func: ident);)+) => { +impl FpioaExt for FPIOA { + fn split(self, apb0: &mut APB0) -> Parts { + // enable APB0 bus + apb0.enable(); + // enable sysctl peripheral + sysctl::clk_en_peri().modify(|_r, w| w.fpioa_clk_en().set_bit()); + // return ownership + Parts { + $( $iox: $IoX { _function: PhantomData }, )+ + } + } +} +/// FPIOA Parts +pub struct Parts { + $( + /// Programmable I/O pin + pub $iox: $IoX<$func>, + )+ + // todo: tie controller Tie (force set high or low as input) +} +pub use io_pins::*; +/// All I/O pins +pub mod io_pins { + use core::marker::PhantomData; + use super::{Function, IoPin, Mode, FUNCTION_DEFAULTS}; + use crate::pac::FPIOA; + +$( + /// Programmable I/O pin + pub struct $IoX { + pub(crate) _function: PhantomData + } + + impl $IoX { + /// Change the programmable I/O pin into given function + /// + /// You may refer to module [functions] for all functions. + /// + /// [functions]: ../functions/index.html + pub fn into_function(self, func: F) -> $IoX { + let _ = func; // note(discard): Zero-sized typestate value + unsafe { &(*FPIOA::ptr()).io[$id].write(|w| + w.bits(FUNCTION_DEFAULTS[F::INDEX as usize]) + ) }; + $IoX { _function: PhantomData } + } + } + impl IoPin for $IoX { + const INDEX: u8 = $id; + } + impl Mode for $IoX {} +)+ +} + }; +} + +def_io_pin! { + Io0: (0, io0, JTAG_TCLK); + Io1: (1, io1, JTAG_TDI); + Io2: (2, io2, JTAG_TMS); + Io3: (3, io3, JTAG_TDO); + Io4: (4, io4, UARTHS_RX); + Io5: (5, io5, UARTHS_TX); + Io6: (6, io6, RESV0); // (FLOAT*): no default function + Io7: (7, io7, RESV0); // (FLOAT*): no default function + Io8: (8, io8, GPIO0); + Io9: (9, io9, GPIO1); + Io10: (10, io10, GPIO2); + Io11: (11, io11, GPIO3); + Io12: (12, io12, GPIO4); + Io13: (13, io13, GPIO5); + Io14: (14, io14, GPIO6); + Io15: (15, io15, GPIO7); + Io16: (16, io16, GPIOHS0); + Io17: (17, io17, GPIOHS1); + Io18: (18, io18, GPIOHS2); + Io19: (19, io19, GPIOHS3); + Io20: (20, io20, GPIOHS4); + Io21: (21, io21, GPIOHS5); + Io22: (22, io22, GPIOHS6); + Io23: (23, io23, GPIOHS7); + Io24: (24, io24, GPIOHS8); + Io25: (25, io25, GPIOHS9); + Io26: (26, io26, GPIOHS10); + Io27: (27, io27, GPIOHS11); + Io28: (28, io28, GPIOHS12); + Io29: (29, io29, GPIOHS13); + Io30: (30, io30, GPIOHS14); + Io31: (31, io31, GPIOHS15); + Io32: (32, io32, GPIOHS16); + Io33: (33, io33, GPIOHS17); + Io34: (34, io34, GPIOHS18); + Io35: (35, io35, GPIOHS19); + Io36: (36, io36, GPIOHS20); + Io37: (37, io37, GPIOHS21); + Io38: (38, io38, GPIOHS22); + Io39: (39, io39, GPIOHS23); + Io40: (40, io40, GPIOHS24); + Io41: (41, io41, GPIOHS25); + Io42: (42, io42, GPIOHS26); + Io43: (43, io43, GPIOHS27); + Io44: (44, io44, GPIOHS28); + Io45: (45, io45, GPIOHS29); + Io46: (46, io46, GPIOHS30); + Io47: (47, io47, GPIOHS31); +} + +/** Defaults per function (from Kendryte fpioa.c) */ +#[rustfmt::skip] +static FUNCTION_DEFAULTS: &[u32] = &[ + 0x00900000, 0x00900001, 0x00900002, 0x00001f03, 0x00b03f04, 0x00b03f05, 0x00b03f06, 0x00b03f07, + 0x00b03f08, 0x00b03f09, 0x00b03f0a, 0x00b03f0b, 0x00001f0c, 0x00001f0d, 0x00001f0e, 0x00001f0f, + 0x03900010, 0x00001f11, 0x00900012, 0x00001f13, 0x00900014, 0x00900015, 0x00001f16, 0x00001f17, + 0x00901f18, 0x00901f19, 0x00901f1a, 0x00901f1b, 0x00901f1c, 0x00901f1d, 0x00901f1e, 0x00901f1f, + 0x00901f20, 0x00901f21, 0x00901f22, 0x00901f23, 0x00901f24, 0x00901f25, 0x00901f26, 0x00901f27, + 0x00901f28, 0x00901f29, 0x00901f2a, 0x00901f2b, 0x00901f2c, 0x00901f2d, 0x00901f2e, 0x00901f2f, + 0x00901f30, 0x00901f31, 0x00901f32, 0x00901f33, 0x00901f34, 0x00901f35, 0x00901f36, 0x00901f37, + 0x00901f38, 0x00901f39, 0x00901f3a, 0x00901f3b, 0x00901f3c, 0x00901f3d, 0x00901f3e, 0x00901f3f, + 0x00900040, 0x00001f41, 0x00900042, 0x00001f43, 0x00900044, 0x00001f45, 0x00b03f46, 0x00b03f47, + 0x00b03f48, 0x00b03f49, 0x00b03f4a, 0x00b03f4b, 0x00b03f4c, 0x00b03f4d, 0x00001f4e, 0x00001f4f, + 0x00001f50, 0x00001f51, 0x03900052, 0x00001f53, 0x00b03f54, 0x00900055, 0x00900056, 0x00001f57, + 0x00001f58, 0x00001f59, 0x0090005a, 0x0090005b, 0x0090005c, 0x0090005d, 0x00001f5e, 0x00001f5f, + 0x00001f60, 0x00001f61, 0x00001f62, 0x00001f63, 0x00001f64, 0x00900065, 0x00900066, 0x00900067, + 0x00900068, 0x00001f69, 0x00001f6a, 0x00001f6b, 0x00001f6c, 0x00001f6d, 0x00001f6e, 0x00001f6f, + 0x00900070, 0x00900071, 0x00900072, 0x00900073, 0x00001f74, 0x00001f75, 0x00001f76, 0x00001f77, + 0x00000078, 0x00000079, 0x0000007a, 0x0000007b, 0x0000007c, 0x0000007d, 0x0099107e, 0x0099107f, + 0x00991080, 0x00991081, 0x00991082, 0x00991083, 0x00001f84, 0x00001f85, 0x00001f86, 0x00900087, + 0x00900088, 0x00900089, 0x0090008a, 0x0090008b, 0x0090008c, 0x0090008d, 0x0090008e, 0x0090008f, + 0x00900090, 0x00900091, 0x00993092, 0x00993093, 0x00900094, 0x00900095, 0x00900096, 0x00900097, + 0x00900098, 0x00001f99, 0x00001f9a, 0x00001f9b, 0x00001f9c, 0x00001f9d, 0x00001f9e, 0x00001f9f, + 0x00001fa0, 0x00001fa1, 0x009000a2, 0x009000a3, 0x009000a4, 0x009000a5, 0x009000a6, 0x00001fa7, + 0x00001fa8, 0x00001fa9, 0x00001faa, 0x00001fab, 0x00001fac, 0x00001fad, 0x00001fae, 0x00001faf, + 0x009000b0, 0x009000b1, 0x009000b2, 0x009000b3, 0x009000b4, 0x00001fb5, 0x00001fb6, 0x00001fb7, + 0x00001fb8, 0x00001fb9, 0x00001fba, 0x00001fbb, 0x00001fbc, 0x00001fbd, 0x00001fbe, 0x00001fbf, + 0x00001fc0, 0x00001fc1, 0x00001fc2, 0x00001fc3, 0x00001fc4, 0x00001fc5, 0x00001fc6, 0x00001fc7, + 0x00001fc8, 0x00001fc9, 0x00001fca, 0x00001fcb, 0x00001fcc, 0x00001fcd, 0x00001fce, 0x00001fcf, + 0x00001fd0, 0x00001fd1, 0x00001fd2, 0x00001fd3, 0x00001fd4, 0x009000d5, 0x009000d6, 0x009000d7, + 0x009000d8, 0x009100d9, 0x00991fda, 0x009000db, 0x009000dc, 0x009000dd, 0x000000de, 0x009000df, + 0x00001fe0, 0x00001fe1, 0x00001fe2, 0x00001fe3, 0x00001fe4, 0x00001fe5, 0x00001fe6, 0x00001fe7, + 0x00001fe8, 0x00001fe9, 0x00001fea, 0x00001feb, 0x00001fec, 0x00001fed, 0x00001fee, 0x00001fef, + 0x00001ff0, 0x00001ff1, 0x00001ff2, 0x00001ff3, 0x00001ff4, 0x00001ff5, 0x00001ff6, 0x00001ff7, + 0x00001ff8, 0x00001ff9, 0x00001ffa, 0x00001ffb, 0x00001ffc, 0x00001ffd, 0x00001ffe, 0x00001fff, +]; + +pub use functions::*; + +/// All programmable functions +pub mod functions { + use super::Function; + + macro_rules! def_function { + ($($name: ident: ($index: expr, $doc: expr);)+) => { + $( + #[doc = $doc] + #[allow(non_camel_case_types)] + pub struct $name; + + impl Function for $name { + const INDEX: u8 = $index; + } + )+ + }; + } + + def_function! { + JTAG_TCLK: (0, "JTAG Test Clock"); + JTAG_TDI: (1, "JTAG Test Data In"); + JTAG_TMS: (2, "JTAG Test Mode Select"); + JTAG_TDO: (3, "JTAG Test Data Out"); + SPI0_D0: (4, "SPI0 Data 0"); + SPI0_D1: (5, "SPI0 Data 1"); + SPI0_D2: (6, "SPI0 Data 2"); + SPI0_D3: (7, "SPI0 Data 3"); + SPI0_D4: (8, "SPI0 Data 4"); + SPI0_D5: (9, "SPI0 Data 5"); + SPI0_D6: (10, "SPI0 Data 6"); + SPI0_D7: (11, "SPI0 Data 7"); + SPI0_SS0: (12, "SPI0 Chip Select 0"); + SPI0_SS1: (13, "SPI0 Chip Select 1"); + SPI0_SS2: (14, "SPI0 Chip Select 2"); + SPI0_SS3: (15, "SPI0 Chip Select 3"); + SPI0_ARB: (16, "SPI0 Arbitration"); + SPI0_SCLK: (17, "SPI0 Serial Clock"); + UARTHS_RX: (18, "UART High speed Receiver"); + UARTHS_TX: (19, "UART High speed Transmitter"); + RESV6: (20, "Reserved function"); + RESV7: (21, "Reserved function"); + CLK_SPI1: (22, "Clock SPI1"); + CLK_I2C1: (23, "Clock I2C1"); + GPIOHS0: (24, "GPIO High speed 0"); + GPIOHS1: (25, "GPIO High speed 1"); + GPIOHS2: (26, "GPIO High speed 2"); + GPIOHS3: (27, "GPIO High speed 3"); + GPIOHS4: (28, "GPIO High speed 4"); + GPIOHS5: (29, "GPIO High speed 5"); + GPIOHS6: (30, "GPIO High speed 6"); + GPIOHS7: (31, "GPIO High speed 7"); + GPIOHS8: (32, "GPIO High speed 8"); + GPIOHS9: (33, "GPIO High speed 9"); + GPIOHS10: (34, "GPIO High speed 10"); + GPIOHS11: (35, "GPIO High speed 11"); + GPIOHS12: (36, "GPIO High speed 12"); + GPIOHS13: (37, "GPIO High speed 13"); + GPIOHS14: (38, "GPIO High speed 14"); + GPIOHS15: (39, "GPIO High speed 15"); + GPIOHS16: (40, "GPIO High speed 16"); + GPIOHS17: (41, "GPIO High speed 17"); + GPIOHS18: (42, "GPIO High speed 18"); + GPIOHS19: (43, "GPIO High speed 19"); + GPIOHS20: (44, "GPIO High speed 20"); + GPIOHS21: (45, "GPIO High speed 21"); + GPIOHS22: (46, "GPIO High speed 22"); + GPIOHS23: (47, "GPIO High speed 23"); + GPIOHS24: (48, "GPIO High speed 24"); + GPIOHS25: (49, "GPIO High speed 25"); + GPIOHS26: (50, "GPIO High speed 26"); + GPIOHS27: (51, "GPIO High speed 27"); + GPIOHS28: (52, "GPIO High speed 28"); + GPIOHS29: (53, "GPIO High speed 29"); + GPIOHS30: (54, "GPIO High speed 30"); + GPIOHS31: (55, "GPIO High speed 31"); + GPIO0: (56, "GPIO pin 0"); + GPIO1: (57, "GPIO pin 1"); + GPIO2: (58, "GPIO pin 2"); + GPIO3: (59, "GPIO pin 3"); + GPIO4: (60, "GPIO pin 4"); + GPIO5: (61, "GPIO pin 5"); + GPIO6: (62, "GPIO pin 6"); + GPIO7: (63, "GPIO pin 7"); + UART1_RX: (64, "UART1 Receiver"); + UART1_TX: (65, "UART1 Transmitter"); + UART2_RX: (66, "UART2 Receiver"); + UART2_TX: (67, "UART2 Transmitter"); + UART3_RX: (68, "UART3 Receiver"); + UART3_TX: (69, "UART3 Transmitter"); + SPI1_D0: (70, "SPI1 Data 0"); + SPI1_D1: (71, "SPI1 Data 1"); + SPI1_D2: (72, "SPI1 Data 2"); + SPI1_D3: (73, "SPI1 Data 3"); + SPI1_D4: (74, "SPI1 Data 4"); + SPI1_D5: (75, "SPI1 Data 5"); + SPI1_D6: (76, "SPI1 Data 6"); + SPI1_D7: (77, "SPI1 Data 7"); + SPI1_SS0: (78, "SPI1 Chip Select 0"); + SPI1_SS1: (79, "SPI1 Chip Select 1"); + SPI1_SS2: (80, "SPI1 Chip Select 2"); + SPI1_SS3: (81, "SPI1 Chip Select 3"); + SPI1_ARB: (82, "SPI1 Arbitration"); + SPI1_SCLK: (83, "SPI1 Serial Clock"); + SPI_SLAVE_D0: (84, "SPI Slave Data 0"); + SPI_SLAVE_SS: (85, "SPI Slave Select"); + SPI_SLAVE_SCLK: (86, "SPI Slave Serial Clock"); + I2S0_MCLK: (87, "I2S0 Master Clock"); + I2S0_SCLK: (88, "I2S0 Serial Clock(BCLK)"); + I2S0_WS: (89, "I2S0 Word Select(LRCLK)"); + I2S0_IN_D0: (90, "I2S0 Serial Data Input 0"); + I2S0_IN_D1: (91, "I2S0 Serial Data Input 1"); + I2S0_IN_D2: (92, "I2S0 Serial Data Input 2"); + I2S0_IN_D3: (93, "I2S0 Serial Data Input 3"); + I2S0_OUT_D0: (94, "I2S0 Serial Data Output 0"); + I2S0_OUT_D1: (95, "I2S0 Serial Data Output 1"); + I2S0_OUT_D2: (96, "I2S0 Serial Data Output 2"); + I2S0_OUT_D3: (97, "I2S0 Serial Data Output 3"); + I2S1_MCLK: (98, "I2S1 Master Clock"); + I2S1_SCLK: (99, "I2S1 Serial Clock(BCLK)"); + I2S1_WS: (100, "I2S1 Word Select(LRCLK)"); + I2S1_IN_D0: (101, "I2S1 Serial Data Input 0"); + I2S1_IN_D1: (102, "I2S1 Serial Data Input 1"); + I2S1_IN_D2: (103, "I2S1 Serial Data Input 2"); + I2S1_IN_D3: (104, "I2S1 Serial Data Input 3"); + I2S1_OUT_D0: (105, "I2S1 Serial Data Output 0"); + I2S1_OUT_D1: (106, "I2S1 Serial Data Output 1"); + I2S1_OUT_D2: (107, "I2S1 Serial Data Output 2"); + I2S1_OUT_D3: (108, "I2S1 Serial Data Output 3"); + I2S2_MCLK: (109, "I2S2 Master Clock"); + I2S2_SCLK: (110, "I2S2 Serial Clock(BCLK)"); + I2S2_WS: (111, "I2S2 Word Select(LRCLK)"); + I2S2_IN_D0: (112, "I2S2 Serial Data Input 0"); + I2S2_IN_D1: (113, "I2S2 Serial Data Input 1"); + I2S2_IN_D2: (114, "I2S2 Serial Data Input 2"); + I2S2_IN_D3: (115, "I2S2 Serial Data Input 3"); + I2S2_OUT_D0: (116, "I2S2 Serial Data Output 0"); + I2S2_OUT_D1: (117, "I2S2 Serial Data Output 1"); + I2S2_OUT_D2: (118, "I2S2 Serial Data Output 2"); + I2S2_OUT_D3: (119, "I2S2 Serial Data Output 3"); + RESV0: (120, "Reserved function"); + RESV1: (121, "Reserved function"); + RESV2: (122, "Reserved function"); + RESV3: (123, "Reserved function"); + RESV4: (124, "Reserved function"); + RESV5: (125, "Reserved function"); + I2C0_SCLK: (126, "I2C0 Serial Clock"); + I2C0_SDA: (127, "I2C0 Serial Data"); + I2C1_SCLK: (128, "I2C1 Serial Clock"); + I2C1_SDA: (129, "I2C1 Serial Data"); + I2C2_SCLK: (130, "I2C2 Serial Clock"); + I2C2_SDA: (131, "I2C2 Serial Data"); + CMOS_XCLK: (132, "DVP System Clock"); + CMOS_RST: (133, "DVP System Reset"); + CMOS_PWDN: (134, "DVP Power Down Mode"); + CMOS_VSYNC: (135, "DVP Vertical Sync"); + CMOS_HREF: (136, "DVP Horizontal Reference output"); + CMOS_PCLK: (137, "Pixel Clock"); + CMOS_D0: (138, "Data Bit 0"); + CMOS_D1: (139, "Data Bit 1"); + CMOS_D2: (140, "Data Bit 2"); + CMOS_D3: (141, "Data Bit 3"); + CMOS_D4: (142, "Data Bit 4"); + CMOS_D5: (143, "Data Bit 5"); + CMOS_D6: (144, "Data Bit 6"); + CMOS_D7: (145, "Data Bit 7"); + SCCB_SCLK: (146, "SCCB Serial Clock"); + SCCB_SDA: (147, "SCCB Serial Data"); + UART1_CTS: (148, "UART1 Clear To Send"); + UART1_DSR: (149, "UART1 Data Set Ready"); + UART1_DCD: (150, "UART1 Data Carrier Detect"); + UART1_RI: (151, "UART1 Ring Indicator"); + UART1_SIR_IN: (152, "UART1 Serial Infrared Input"); + UART1_DTR: (153, "UART1 Data Terminal Ready"); + UART1_RTS: (154, "UART1 Request To Send"); + UART1_OUT2: (155, "UART1 User-designated Output 2"); + UART1_OUT1: (156, "UART1 User-designated Output 1"); + UART1_SIR_OUT: (157, "UART1 Serial Infrared Output"); + UART1_BAUD: (158, "UART1 Transmit Clock Output"); + UART1_RE: (159, "UART1 Receiver Output Enable"); + UART1_DE: (160, "UART1 Driver Output Enable"); + UART1_RS485_EN: (161, "UART1 RS485 Enable"); + UART2_CTS: (162, "UART2 Clear To Send"); + UART2_DSR: (163, "UART2 Data Set Ready"); + UART2_DCD: (164, "UART2 Data Carrier Detect"); + UART2_RI: (165, "UART2 Ring Indicator"); + UART2_SIR_IN: (166, "UART2 Serial Infrared Input"); + UART2_DTR: (167, "UART2 Data Terminal Ready"); + UART2_RTS: (168, "UART2 Request To Send"); + UART2_OUT2: (169, "UART2 User-designated Output 2"); + UART2_OUT1: (170, "UART2 User-designated Output 1"); + UART2_SIR_OUT: (171, "UART2 Serial Infrared Output"); + UART2_BAUD: (172, "UART2 Transmit Clock Output"); + UART2_RE: (173, "UART2 Receiver Output Enable"); + UART2_DE: (174, "UART2 Driver Output Enable"); + UART2_RS485_EN: (175, "UART2 RS485 Enable"); + UART3_CTS: (176, "UART3 Clear To Send"); + UART3_DSR: (177, "UART3 Data Set Ready"); + UART3_DCD: (178, "UART3 Data Carrier Detect"); + UART3_RI: (179, "UART3 Ring Indicator"); + UART3_SIR_IN: (180, "UART3 Serial Infrared Input"); + UART3_DTR: (181, "UART3 Data Terminal Ready"); + UART3_RTS: (182, "UART3 Request To Send"); + UART3_OUT2: (183, "UART3 User-designated Output 2"); + UART3_OUT1: (184, "UART3 User-designated Output 1"); + UART3_SIR_OUT: (185, "UART3 Serial Infrared Output"); + UART3_BAUD: (186, "UART3 Transmit Clock Output"); + UART3_RE: (187, "UART3 Receiver Output Enable"); + UART3_DE: (188, "UART3 Driver Output Enable"); + UART3_RS485_EN: (189, "UART3 RS485 Enable"); + TIMER0_TOGGLE1: (190, "TIMER0 Toggle Output 1"); + TIMER0_TOGGLE2: (191, "TIMER0 Toggle Output 2"); + TIMER0_TOGGLE3: (192, "TIMER0 Toggle Output 3"); + TIMER0_TOGGLE4: (193, "TIMER0 Toggle Output 4"); + TIMER1_TOGGLE1: (194, "TIMER1 Toggle Output 1"); + TIMER1_TOGGLE2: (195, "TIMER1 Toggle Output 2"); + TIMER1_TOGGLE3: (196, "TIMER1 Toggle Output 3"); + TIMER1_TOGGLE4: (197, "TIMER1 Toggle Output 4"); + TIMER2_TOGGLE1: (198, "TIMER2 Toggle Output 1"); + TIMER2_TOGGLE2: (199, "TIMER2 Toggle Output 2"); + TIMER2_TOGGLE3: (200, "TIMER2 Toggle Output 3"); + TIMER2_TOGGLE4: (201, "TIMER2 Toggle Output 4"); + CLK_SPI2: (202, "Clock SPI2"); + CLK_I2C2: (203, "Clock I2C2"); + INTERNAL0: (204, "Internal function signal 0"); + INTERNAL1: (205, "Internal function signal 1"); + INTERNAL2: (206, "Internal function signal 2"); + INTERNAL3: (207, "Internal function signal 3"); + INTERNAL4: (208, "Internal function signal 4"); + INTERNAL5: (209, "Internal function signal 5"); + INTERNAL6: (210, "Internal function signal 6"); + INTERNAL7: (211, "Internal function signal 7"); + INTERNAL8: (212, "Internal function signal 8"); + INTERNAL9: (213, "Internal function signal 9"); + INTERNAL10: (214, "Internal function signal 10"); + INTERNAL11: (215, "Internal function signal 11"); + INTERNAL12: (216, "Internal function signal 12"); + INTERNAL13: (217, "Internal function signal 13"); + INTERNAL14: (218, "Internal function signal 14"); + INTERNAL15: (219, "Internal function signal 15"); + INTERNAL16: (220, "Internal function signal 16"); + INTERNAL17: (221, "Internal function signal 17"); + CONSTANT: (222, "Constant function"); + INTERNAL18: (223, "Internal function signal 18"); + DEBUG0: (224, "Debug function 0"); + DEBUG1: (225, "Debug function 1"); + DEBUG2: (226, "Debug function 2"); + DEBUG3: (227, "Debug function 3"); + DEBUG4: (228, "Debug function 4"); + DEBUG5: (229, "Debug function 5"); + DEBUG6: (230, "Debug function 6"); + DEBUG7: (231, "Debug function 7"); + DEBUG8: (232, "Debug function 8"); + DEBUG9: (233, "Debug function 9"); + DEBUG10: (234, "Debug function 10"); + DEBUG11: (235, "Debug function 11"); + DEBUG12: (236, "Debug function 12"); + DEBUG13: (237, "Debug function 13"); + DEBUG14: (238, "Debug function 14"); + DEBUG15: (239, "Debug function 15"); + DEBUG16: (240, "Debug function 16"); + DEBUG17: (241, "Debug function 17"); + DEBUG18: (242, "Debug function 18"); + DEBUG19: (243, "Debug function 19"); + DEBUG20: (244, "Debug function 20"); + DEBUG21: (245, "Debug function 21"); + DEBUG22: (246, "Debug function 22"); + DEBUG23: (247, "Debug function 23"); + DEBUG24: (248, "Debug function 24"); + DEBUG25: (249, "Debug function 25"); + DEBUG26: (250, "Debug function 26"); + DEBUG27: (251, "Debug function 27"); + DEBUG28: (252, "Debug function 28"); + DEBUG29: (253, "Debug function 29"); + DEBUG30: (254, "Debug function 30"); + DEBUG31: (255, "Debug function 31"); + } +} diff --git a/third-party/k210-hal/src/gpio.rs b/third-party/k210-hal/src/gpio.rs new file mode 100644 index 00000000..efe0fb93 --- /dev/null +++ b/third-party/k210-hal/src/gpio.rs @@ -0,0 +1,233 @@ +//! General Purpose Input/Output (GPIO) + +use core::marker::PhantomData; +use crate::pac; +use crate::sysctl::{self, APB0}; +use crate::fpioa::{IoPin, Pull, Mode}; +use crate::bit_utils::{u32_set_bit, u32_toggle_bit, u32_bit_is_set, u32_bit_is_clear}; +use embedded_hal::digital::{OutputPin, StatefulOutputPin, InputPin, ToggleableOutputPin}; + +/// Extension trait to split a GPIO peripheral into independent pins +pub trait GpioExt { + /// Split the GPIO peripheral into parts + fn split(self, apb0: &mut APB0) -> Parts; +} + +macro_rules! def_gpio_pins { + ($($GPIOX: ident: ($num: expr, $gpiox: ident, $func: ident);)+) => { + +impl GpioExt for pac::GPIO { + fn split(self, apb0: &mut APB0) -> Parts { + // enable APB0 bus + apb0.enable(); + // enable sysctl peripheral + sysctl::clk_en_peri().modify(|_r, w| w.gpio_clk_en().set_bit()); + // return ownership + Parts { + $( $gpiox: $GPIOX { _ownership: () }, )+ + } + } +} + +/// GPIO peripheral parts +pub struct Parts { + $( + /// GPIO pin + pub $gpiox: $GPIOX, + )+ +} + +pub use gpio_pins::*; + +/// All GPIO pins +pub mod gpio_pins { + use super::GpioIndex; +$( + /// GPIO pin + pub struct $GPIOX { + pub(crate) _ownership: () + } + + impl GpioIndex for $GPIOX { + type FUNC = crate::fpioa::functions::$func; + const INDEX: u8 = $num; + } +)+ +} + }; +} + +def_gpio_pins! { + GPIO0: (0, gpio0, GPIO0); + GPIO1: (1, gpio1, GPIO1); + GPIO2: (2, gpio2, GPIO2); + GPIO3: (3, gpio3, GPIO3); + GPIO4: (4, gpio4, GPIO4); + GPIO5: (5, gpio5, GPIO5); + GPIO6: (6, gpio6, GPIO6); + GPIO7: (7, gpio7, GPIO7); +} + +/// GPIO Index +pub trait GpioIndex { + type FUNC; + const INDEX: u8; +} + +/// Unknown mode (type state) +pub struct Unknown; + +/// Input mode (type state) +pub struct Input(MODE); + +/// Floating input (type state) +pub struct Floating; + +/// Pull down input (type state) +pub struct PullDown; + +/// Pull up input (type state) +pub struct PullUp; + +/// Output mode (type state) +pub struct Output; + +/// Marker trait for active states +pub trait Active {} + +impl Active for Unknown {} + +impl Active for Input {} + +impl Active for Input {} + +impl Active for Input {} + +impl Active for Output {} + +/// GPIO wrapper struct +pub struct Gpio { + gpio: GPIO, + pin: PIN, + _mode: PhantomData, +} + +impl> Gpio { + pub fn new(gpio: GPIO, pin: PIN) -> Gpio { + Gpio { gpio, pin, _mode: PhantomData } + } +} + +impl Gpio { + pub fn free(self) -> (GPIO, PIN) { + (self.gpio, self.pin) + } +} + +impl Gpio { + pub fn into_floating_input(mut self) -> Gpio> { + self.pin.set_io_pull(Pull::None); + self.direction_in(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + pub fn into_pull_up_input(mut self) -> Gpio> { + self.pin.set_io_pull(Pull::Up); + self.direction_in(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + pub fn into_pull_down_input(mut self) -> Gpio> { + self.pin.set_io_pull(Pull::Down); + self.direction_in(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + pub fn into_push_pull_output(mut self) -> Gpio { + self.pin.set_io_pull(Pull::Down); + self.direction_out(); + Gpio { gpio: self.gpio, pin: self.pin, _mode: PhantomData } + } + + #[inline] + fn direction_in(&mut self) { + unsafe { + let p = &(*pac::GPIO::ptr()).direction as *const _ as *mut _; + u32_set_bit(p, false, GPIO::INDEX as usize); + } + } + + #[inline] + fn direction_out(&mut self) { + unsafe { + let p = &(*pac::GPIO::ptr()).direction as *const _ as *mut _; + u32_set_bit(p, true, GPIO::INDEX as usize); + } + } +} + +impl InputPin for Gpio> { + type Error = core::convert::Infallible; + + fn try_is_high(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_input as *const _ as *const _; + u32_bit_is_set(p, GPIO::INDEX as usize) + }) + } + + fn try_is_low(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_input as *const _ as *const _; + u32_bit_is_clear(p, GPIO::INDEX as usize) + }) + } +} + +impl OutputPin for Gpio { + type Error = core::convert::Infallible; + + fn try_set_high(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *mut _; + u32_set_bit(p, true, GPIO::INDEX as usize); + } + Ok(()) + } + + fn try_set_low(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *mut _; + u32_set_bit(p, false, GPIO::INDEX as usize); + } + Ok(()) + } +} + +impl StatefulOutputPin for Gpio { + fn try_is_set_high(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *const _; + u32_bit_is_set(p, GPIO::INDEX as usize) + }) + } + + fn try_is_set_low(&self) -> Result { + Ok(unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *const _; + u32_bit_is_clear(p, GPIO::INDEX as usize) + }) + } +} + +impl ToggleableOutputPin for Gpio { + type Error = core::convert::Infallible; + + fn try_toggle(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*pac::GPIO::ptr()).data_output as *const _ as *mut _; + u32_toggle_bit(p, GPIO::INDEX as usize); + } + Ok(()) + } +} diff --git a/third-party/k210-hal/src/gpiohs.rs b/third-party/k210-hal/src/gpiohs.rs new file mode 100644 index 00000000..9be4195f --- /dev/null +++ b/third-party/k210-hal/src/gpiohs.rs @@ -0,0 +1,346 @@ +//! High-speed GPIO peripheral (GPIOHS) + +use crate::pac::GPIOHS; +use core::marker::PhantomData; +use crate::bit_utils::{u32_set_bit, u32_toggle_bit, u32_bit_is_set, u32_bit_is_clear}; +use embedded_hal::digital::{InputPin, OutputPin}; + +// todo: verify + +/// Floating mode (type state) +pub struct Floating; + +/// PullUp mode (type state) +pub struct PullUp; + +/// Input mode (type state) +pub struct Input(MODE); + +/// Output mode (type state) +pub struct Output(MODE); + +pub trait GpiohsExt { + fn split(self) -> Parts; +} + +impl GpiohsExt for GPIOHS { + fn split(self) -> Parts { + Parts { + gpiohs0: Gpiohs0 { _mode: PhantomData }, + } + } +} + +pub struct Parts { + pub gpiohs0: Gpiohs0>, +} + +pub struct Gpiohs0 { + _mode: PhantomData, +} + +impl Gpiohs0 { + pub fn into_pull_up_input(self) -> Gpiohs0> { + GPIOHS::set_output_en(0, false); + GPIOHS::set_input_en(0, true); + GPIOHS::set_pullup_en(0, true); + Gpiohs0 { _mode: PhantomData } + } + + // todo: all modes +} + +bitflags::bitflags! { + pub struct Edge: u8 { + const RISING = 0b00000001; + const FALLING = 0b00000010; + const HIGH = 0b00000100; + const LOW = 0b00001000; + } +} + +impl Gpiohs0 { + pub fn trigger_on_edge(&mut self, edge: Edge) { + // clear all pending bits + GPIOHS::clear_rise_ip(0); + GPIOHS::clear_fall_ip(0); + GPIOHS::clear_high_ip(0); + GPIOHS::clear_low_ip(0); + // enable interrupts according to flags + GPIOHS::set_rise_ie(0, edge.contains(Edge::RISING)); + GPIOHS::set_fall_ie(0, edge.contains(Edge::FALLING)); + GPIOHS::set_high_ie(0, edge.contains(Edge::HIGH)); + GPIOHS::set_low_ie(0, edge.contains(Edge::LOW)); + } + + pub fn check_edges(&self) -> Edge { + let mut ans = Edge::empty(); + if GPIOHS::has_rise_ip(0) { + ans |= Edge::RISING; + } + if GPIOHS::has_fall_ip(0) { + ans |= Edge::FALLING; + } + if GPIOHS::has_high_ip(0) { + ans |= Edge::HIGH; + } + if GPIOHS::has_low_ip(0) { + ans |= Edge::LOW; + } + ans + } + + pub fn clear_interrupt_pending_bits(&mut self) { + if GPIOHS::has_rise_ie(0) { + GPIOHS::set_rise_ie(0, false); + GPIOHS::clear_rise_ip(0); + GPIOHS::set_rise_ie(0, true); + } + if GPIOHS::has_fall_ie(0) { + GPIOHS::set_fall_ie(0, false); + GPIOHS::clear_fall_ip(0); + GPIOHS::set_fall_ie(0, true); + } + if GPIOHS::has_high_ie(0) { + GPIOHS::set_high_ie(0, false); + GPIOHS::clear_high_ip(0); + GPIOHS::set_high_ie(0, true); + } + if GPIOHS::has_low_ie(0) { + GPIOHS::set_low_ie(0, false); + GPIOHS::clear_low_ip(0); + GPIOHS::set_low_ie(0, true); + } + } +} + +impl InputPin for Gpiohs0> { + type Error = core::convert::Infallible; + + fn try_is_high(&self) -> Result { + Ok(unsafe { + let p = &(*GPIOHS::ptr()).input_val as *const _ as *const _; + u32_bit_is_set(p, 0) + }) + } + + fn try_is_low(&self) -> Result { + Ok(unsafe { + let p = &(*GPIOHS::ptr()).input_val as *const _ as *const _; + u32_bit_is_clear(p, 0) + }) + } +} + +impl OutputPin for Gpiohs0> { + type Error = core::convert::Infallible; + + fn try_set_high(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*GPIOHS::ptr()).output_val as *const _ as *mut _; + u32_set_bit(p, true, 0); + } + Ok(()) + } + + fn try_set_low(&mut self) -> Result<(), Self::Error> { + unsafe { + let p = &(*GPIOHS::ptr()).output_val as *const _ as *mut _; + u32_set_bit(p, false, 0); + } + Ok(()) + } +} + +trait GpiohsAccess { + fn peripheral() -> &'static mut crate::pac::gpiohs::RegisterBlock; + + fn set_drive(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().drive as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn input_value(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().input_val as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn set_input_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().input_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_iof_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().iof_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_iof_sel(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().iof_sel as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_output_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().output_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_output_value(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().output_val as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_output_xor(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().output_xor as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn toggle_pin(index: usize) { + unsafe { + let p = &mut Self::peripheral().output_val as *mut _ as *mut _; + u32_toggle_bit(p, index); + } + } + + fn set_pullup_en(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().pullup_en as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn set_rise_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_rise_ip(index: usize) { + unsafe { + let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn set_fall_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_fall_ip(index: usize) { + unsafe { + let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn set_high_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().high_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_high_ip(index: usize,) { + unsafe { + let p = &mut Self::peripheral().high_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn set_low_ie(index: usize, bit: bool) { + unsafe { + let p = &mut Self::peripheral().low_ie as *mut _ as *mut _; + u32_set_bit(p, bit, index); + } + } + + fn clear_low_ip(index: usize) { + unsafe { + let p = &mut Self::peripheral().low_ip as *mut _ as *mut _; + u32_set_bit(p, true, index); + } + } + + fn has_rise_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_fall_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_high_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().high_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_low_ie(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().low_ie as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_rise_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_fall_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_high_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().high_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + + fn has_low_ip(index: usize) -> bool { + unsafe { + let p = &mut Self::peripheral().low_ip as *mut _ as *mut _; + u32_bit_is_set(p, index) + } + } + +} + +impl GpiohsAccess for GPIOHS { + fn peripheral() -> &'static mut crate::pac::gpiohs::RegisterBlock { + unsafe { &mut *(GPIOHS::ptr() as *mut _) } + } +} diff --git a/third-party/k210-hal/src/lib.rs b/third-party/k210-hal/src/lib.rs new file mode 100644 index 00000000..4309e866 --- /dev/null +++ b/third-party/k210-hal/src/lib.rs @@ -0,0 +1,67 @@ +//! HAL for the K210 SoC +//! +//! This is an implementation of the [`embedded-hal`] traits for the K210 SoC + +// #![deny(missing_docs)] // uncomment for every releases +#![no_std] + +pub use k210_pac as pac; + +pub mod aes; +pub mod apu; +pub mod cache; +pub mod clint; +pub mod clock; +pub mod dmac; +pub mod fft; +pub mod fpioa; +pub mod gpio; +pub mod gpiohs; +pub mod plic; +pub mod serial; +pub mod spi; +pub mod sha256; +pub mod stdout; +pub mod sysctl; +pub mod time; + +/// Prelude +pub mod prelude { + pub use embedded_hal::prelude::*; + pub use crate::serial::SerialExt as _k210_hal_serial_SerialExt; + pub use crate::stdout::Write as _k210_hal_stdout_Write; + pub use crate::time::U32Ext as _k210_hal_time_U32Ext; + pub use crate::fpioa::FpioaExt as _k210_hal_fpioa_FpioaExt; + pub use crate::sysctl::SysctlExt as _k210_hal_sysctl_SysctlExt; + pub use crate::gpio::GpioExt as _k210_hal_gpio_GpioExt; + pub use crate::gpiohs::GpiohsExt as _k210_hal_gpiohs_GpiohsExt; + pub use crate::plic::PlicExt as _k210_hal_plic_PlicExt; +} + +mod bit_utils { + #[inline(always)] + pub(crate) unsafe fn u32_set_bit(p: *mut u32, bit: bool, index: usize) { + let mask = 1 << index; + if bit { + *p |= mask; + } else { + *p &= !mask; + } + } + + #[inline(always)] + pub(crate) unsafe fn u32_toggle_bit(p: *mut u32, index: usize) { + let mask = 1 << index; + *p ^= mask; + } + + #[inline(always)] + pub(crate) unsafe fn u32_bit_is_set(r: *const u32, index: usize) -> bool { + (*r & 1 << index) != 0 + } + + #[inline(always)] + pub(crate) unsafe fn u32_bit_is_clear(r: *const u32, index: usize) -> bool { + (*r & 1 << index) == 0 + } +} diff --git a/third-party/k210-hal/src/plic.rs b/third-party/k210-hal/src/plic.rs new file mode 100644 index 00000000..06635e2e --- /dev/null +++ b/third-party/k210-hal/src/plic.rs @@ -0,0 +1,239 @@ +//! Platform-Level Interrupt Controller (PLIC) + +// I don't know if this part should be implemented in runtime +// keep by now, may be replaced on further designs +// #[doc(hidden)] +// #[link_name = "MachineExternal"] +// pub extern fn machine_external() { + +// } + +use crate::pac::{PLIC, Interrupt}; + +/// Extension trait for PLIC interrupt controller peripheral +pub trait PlicExt { + /// Interrupt wrapper type + type Interrupt: Nr; + /// Is this M-Mode interrupt enabled on given hart? + fn is_enabled(hart_id: usize, interrupt: Self::Interrupt) -> bool; + /// Enable an interrupt for a given hart + unsafe fn unmask(hart_id: usize, interrupt: Self::Interrupt); + /// Disable an interrupt for a given hart + fn mask(hart_id: usize, interrupt: Self::Interrupt); + /// Get global priority for one interrupt + fn get_priority(interrupt: Self::Interrupt) -> Priority; + /// Globally set priority for one interrupt + unsafe fn set_priority(interrupt: Self::Interrupt, prio: Priority); + /// Get priority threshold for a given hart + fn get_threshold(hart_id: usize) -> Priority; + /// Set the priority threshold for a given hart + unsafe fn set_threshold(hart_id: usize, threshold: Priority); + /// Mark that given hart have claimed to handle this interrupt + fn claim(hart_id: usize) -> Option; + /// Mark that given hart have completed handling this interrupt + fn complete(hart_id: usize, interrupt: Self::Interrupt); + /// Is this interrupt claimed and under procceeding? + fn is_pending(interrupt: Self::Interrupt) -> bool; +} + +impl PlicExt for PLIC { + type Interrupt = Interrupt; + fn is_enabled(hart_id: usize, interrupt: Interrupt) -> bool { + let irq_number = interrupt.into_bits() as usize; + unsafe { + (*PLIC::ptr()).target_enables[hart_id].enable[irq_number / 32] + .read().bits() & 1 << (irq_number % 32) != 0 + } + } + unsafe fn unmask(hart_id: usize, interrupt: Interrupt) { + let irq_number = interrupt.into_bits() as usize; + (*PLIC::ptr()).target_enables[hart_id].enable[irq_number / 32] + .modify(|r, w| + w.bits(r.bits() | 1 << (irq_number % 32))); + } + fn mask(hart_id: usize, interrupt: Interrupt) { + let irq_number = interrupt.into_bits() as usize; + unsafe { + (*PLIC::ptr()).target_enables[hart_id].enable[irq_number / 32] + .modify(|r, w| + w.bits(r.bits() & !(1 << (irq_number % 32)))); + } + } + fn get_priority(interrupt: Interrupt) -> Priority { + let irq_number = interrupt.into_bits() as usize; + let bits = unsafe { + (*PLIC::ptr()).priority[irq_number].read().bits() + }; + Priority::from_bits(bits) + } + unsafe fn set_priority(interrupt: Interrupt, prio: Priority) { + let irq_number = interrupt.into_bits() as usize; + (*PLIC::ptr()).priority[irq_number].write( + |w| + w.bits(prio.into_bits())); + } + fn get_threshold(hart_id: usize) -> Priority { + let bits = unsafe { + (*PLIC::ptr()).targets[hart_id].threshold.read().bits() + }; + Priority::from_bits(bits) + } + unsafe fn set_threshold(hart_id: usize, threshold: Priority) { + (*PLIC::ptr()).targets[hart_id].threshold.write( + |w| + w.bits(threshold.into_bits())); + } + fn claim(hart_id: usize) -> Option { + let bits = unsafe { + (*PLIC::ptr()).targets[hart_id].claim.read().bits() + }; + Nr::from_bits(bits) + } + fn complete(hart_id: usize, interrupt: Interrupt) { + unsafe { + (*PLIC::ptr()).targets[hart_id].claim.write( + |w| + w.bits(interrupt.into_bits())); + } + } + fn is_pending(interrupt: Interrupt) -> bool { + let irq_number = interrupt.into_bits() as usize; + unsafe { + (*PLIC::ptr()).pending[irq_number / 32] + .read().bits() & 1 << (irq_number % 32) != 0 + } + } +} + +impl Nr for Interrupt { + fn into_bits(&self) -> u32 { + *self as u8 as u32 + } + fn from_bits(bits: u32) -> Option { + use Interrupt::*; + match bits { + 0 => None, + 1 => Some(SPI0), + 2 => Some(SPI1), + 3 => Some(SPI_SLAVE), + 4 => Some(SPI3), + 5 => Some(I2S0), + 6 => Some(I2S1), + 7 => Some(I2S2), + 8 => Some(I2C0), + 9 => Some(I2C1), + 10 => Some(I2C2), + 11 => Some(UART1), + 12 => Some(UART2), + 13 => Some(UART3), + 14 => Some(TIMER0A), + 15 => Some(TIMER0B), + 16 => Some(TIMER1A), + 17 => Some(TIMER1B), + 18 => Some(TIMER2A), + 19 => Some(TIMER2B), + 20 => Some(RTC), + 21 => Some(WDT0), + 22 => Some(WDT1), + 23 => Some(APB_GPIO), + 24 => Some(DVP), + 25 => Some(KPU), + 26 => Some(FFT), + 27 => Some(DMA0), + 28 => Some(DMA1), + 29 => Some(DMA2), + 30 => Some(DMA3), + 31 => Some(DMA4), + 32 => Some(DMA5), + 33 => Some(UARTHS), + 34 => Some(GPIOHS0), + 35 => Some(GPIOHS1), + 36 => Some(GPIOHS2), + 37 => Some(GPIOHS3), + 38 => Some(GPIOHS4), + 39 => Some(GPIOHS5), + 40 => Some(GPIOHS6), + 41 => Some(GPIOHS7), + 42 => Some(GPIOHS8), + 43 => Some(GPIOHS9), + 44 => Some(GPIOHS10), + 45 => Some(GPIOHS11), + 46 => Some(GPIOHS12), + 47 => Some(GPIOHS13), + 48 => Some(GPIOHS14), + 49 => Some(GPIOHS15), + 50 => Some(GPIOHS16), + 51 => Some(GPIOHS17), + 52 => Some(GPIOHS18), + 53 => Some(GPIOHS19), + 54 => Some(GPIOHS20), + 55 => Some(GPIOHS21), + 56 => Some(GPIOHS22), + 57 => Some(GPIOHS23), + 58 => Some(GPIOHS24), + 59 => Some(GPIOHS25), + 60 => Some(GPIOHS26), + 61 => Some(GPIOHS27), + 62 => Some(GPIOHS28), + 63 => Some(GPIOHS29), + 64 => Some(GPIOHS30), + 65 => Some(GPIOHS31), + _ => panic!("invalid interrupt bits") + } + } +} + +#[doc(hidden)] +pub trait Nr: Sized { + fn into_bits(&self) -> u32; + fn from_bits(bits: u32) -> Option; +} + +/// Priority of an interrupt +#[derive(Clone, Copy, Debug)] +pub enum Priority { + /// Priority 0: Never interrupt + P0, + /// Priority 1: Lowest active priority + P1, + /// Priority 2 + P2, + /// Priority 3 + P3, + /// Priority 4 + P4, + /// Priority 5 + P5, + /// Priority 6 + P6, + /// Priority 7: Highest priority + P7, +} + +impl Priority { + fn into_bits(self) -> u32 { + match self { + Priority::P0 => 0, + Priority::P1 => 1, + Priority::P2 => 2, + Priority::P3 => 3, + Priority::P4 => 4, + Priority::P5 => 5, + Priority::P6 => 6, + Priority::P7 => 7, + } + } + fn from_bits(prio: u32) -> Priority { + match prio { + 0 => Priority::P0, + 1 => Priority::P1, + 2 => Priority::P2, + 3 => Priority::P3, + 4 => Priority::P4, + 5 => Priority::P5, + 6 => Priority::P6, + 7 => Priority::P7, + _ => panic!("Invalid priority"), + } + } +} diff --git a/third-party/k210-hal/src/serial.rs b/third-party/k210-hal/src/serial.rs new file mode 100644 index 00000000..302fbb5c --- /dev/null +++ b/third-party/k210-hal/src/serial.rs @@ -0,0 +1,235 @@ +//! Serial interface +//! +//! You can use the `Serial` interface with these UART instances: +//! * [`UARTHS`](crate::pac::UARTHS) +//! * [`UART1`](crate::pac::UART1) +//! * [`UART2`](crate::pac::UART2) +//! * [`UART3`](crate::pac::UART3) + +use core::mem; +use core::convert::Infallible; + +use embedded_hal::serial; + +use crate::pac::{UARTHS,uart1,UART1,UART2,UART3}; +use crate::clock::Clocks; +use crate::time::Bps; + +/// Extension trait that constrains UART peripherals +pub trait SerialExt: Sized { + /// Configures a UART peripheral to provide serial communication + fn configure(self, baud_rate: Bps, clocks: &Clocks) -> Serial; +} + +/// Serial abstraction +pub struct Serial { + uart: UART, +} + +impl Serial { + /// Splits the `Serial` abstraction into a transmitter and a + /// receiver half + pub fn split(self) -> (Tx, Rx) { + ( + Tx { + uart: self.uart, + }, + Rx { + uart: unsafe { mem::MaybeUninit::uninit().assume_init() }, + } + ) + } + + /// Forms `Serial` abstraction from a transmitter and a + /// receiver half + pub fn join(tx: Tx, rx: Rx) -> Self { + let _ = rx; // note(discard): Zero-sized typestate struct + Serial { uart: tx.uart } + } + + /// Releases the UART peripheral + pub fn free(self) -> UART { + // todo: power down this UART + self.uart + } +} + +/// Serial transmitter +pub struct Tx { + uart: UART, +} + +/// Serial receiver +pub struct Rx { + uart: UART, +} + +impl SerialExt for UARTHS { + fn configure(self, baud_rate: Bps, clocks: &Clocks) -> Serial + { + let uart = self; + + let div = clocks.cpu().0 / baud_rate.0 - 1; + unsafe { + uart.div.write(|w| w.bits(div)); + } + + uart.txctrl.write(|w| w.txen().bit(true)); + uart.rxctrl.write(|w| w.rxen().bit(true)); + + Serial { uart } + } +} + +impl Serial { + /// Starts listening for an interrupt event + pub fn listen(self) -> Self { + self.uart.ie.write(|w| w.txwm().bit(false).rxwm().bit(true)); + self + } + + /// Stops listening for an interrupt event + pub fn unlisten(self) -> Self { + self.uart + .ie + .write(|w| w.txwm().bit(false).rxwm().bit(false)); + self + } +} + +impl serial::Read for Rx { + type Error = Infallible; + + fn try_read(&mut self) -> nb::Result { + let rxdata = self.uart.rxdata.read(); + + if rxdata.empty().bit_is_set() { + Err(nb::Error::WouldBlock) + } else { + Ok(rxdata.data().bits() as u8) + } + } +} + +impl serial::Write for Tx { + type Error = Infallible; + + fn try_write(&mut self, byte: u8) -> nb::Result<(), Infallible> { + let txdata = self.uart.txdata.read(); + + if txdata.full().bit_is_set() { + Err(nb::Error::WouldBlock) + } else { + unsafe { + (*UARTHS::ptr()).txdata.write(|w| w.data().bits(byte)); + } + Ok(()) + } + } + + fn try_flush(&mut self) -> nb::Result<(), Infallible> { + let txdata = self.uart.txdata.read(); + + if txdata.full().bit_is_set() { + Err(nb::Error::WouldBlock) + } else { + Ok(()) + } + } +} + +mod closed_trait { + use core::ops::Deref; + /// Trait to be able to generalize over UART1/UART2/UART3 + pub trait UartX: Deref { + const INDEX: u8; + } +} +use closed_trait::UartX; + +impl UartX for UART1 { const INDEX: u8 = 1; } +impl UartX for UART2 { const INDEX: u8 = 2; } +impl UartX for UART3 { const INDEX: u8 = 3; } + +const UART_RECEIVE_FIFO_1: u32 = 0; +const UART_SEND_FIFO_8: u32 = 3; + +impl SerialExt for UART { + fn configure(self, baud_rate: Bps, clocks: &Clocks) -> Serial { + let uart = self; + + // Hardcode these for now: + let data_width = 8; // 8 data bits + let stopbit_val = 0; // 1 stop bit + let parity_val = 0; // No parity + // Note: need to make sure that UARTx clock is enabled through sysctl before here + let divisor = clocks.apb0().0 / baud_rate.0; + let dlh = ((divisor >> 12) & 0xff) as u8; + let dll = ((divisor >> 4) & 0xff) as u8; + let dlf = (divisor & 0xf) as u8; + unsafe { + // Set Divisor Latch Access Bit (enables DLL DLH) to set baudrate + uart.lcr.write(|w| w.bits(1 << 7)); + uart.dlh_ier.write(|w| w.bits(dlh.into())); + uart.rbr_dll_thr.write(|w| w.bits(dll.into())); + uart.dlf.write(|w| w.bits(dlf.into())); + // Clear Divisor Latch Access Bit after setting baudrate + uart.lcr.write(|w| w.bits((data_width - 5) | (stopbit_val << 2) | (parity_val << 3))); + // Write IER + uart.dlh_ier.write(|w| w.bits(0x80)); /* THRE */ + // Write FCT + uart.fcr_iir.write(|w| w.bits(UART_RECEIVE_FIFO_1 << 6 | UART_SEND_FIFO_8 << 4 | 0x1 << 3 | 0x1)); + } + + Serial { uart } + } +} + +impl Serial { + /// Starts listening for an interrupt event + pub fn listen(self) -> Self { + self + } + + /// Stops listening for an interrupt event + pub fn unlisten(self) -> Self { + self + } +} + +impl serial::Read for Rx { + type Error = Infallible; + + fn try_read(&mut self) -> nb::Result { + let lsr = self.uart.lsr.read(); + + if (lsr.bits() & (1<<0)) == 0 { // Data Ready bit + Err(nb::Error::WouldBlock) + } else { + let rbr = self.uart.rbr_dll_thr.read(); + Ok((rbr.bits() & 0xff) as u8) + } + } +} + +impl serial::Write for Tx { + type Error = Infallible; + + fn try_write(&mut self, byte: u8) -> nb::Result<(), Infallible> { + let lsr = self.uart.lsr.read(); + + if (lsr.bits() & (1<<5)) != 0 { // Transmit Holding Register Empty bit + Err(nb::Error::WouldBlock) + } else { + unsafe { + self.uart.rbr_dll_thr.write(|w| w.bits(byte.into())); + } + Ok(()) + } + } + + fn try_flush(&mut self) -> nb::Result<(), Infallible> { + // TODO + Ok(()) + } +} diff --git a/third-party/k210-hal/src/sha256.rs b/third-party/k210-hal/src/sha256.rs new file mode 100644 index 00000000..e32a62b9 --- /dev/null +++ b/third-party/k210-hal/src/sha256.rs @@ -0,0 +1,52 @@ +//! Secure Hash Algorithm-256 (SHA256) + +use crate::pac::SHA256; +use crate::sysctl::{self, APB0}; + +/// SHA256 module abstraction +pub struct Sha256 { + sha256: SHA256, +} + +impl Sha256 { + pub fn sha256(sha256: SHA256, apb0: &mut APB0) -> Sha256 { + apb0.enable(); + sysctl::clk_en_peri().modify(|_r, w| + w.sha_clk_en().set_bit()); + sysctl::peri_reset().modify(|_r, w| + w.sha_reset().set_bit()); + sysctl::peri_reset().modify(|_r, w| + w.sha_reset().clear_bit()); + Sha256 { sha256 } + } + + pub fn new_digest(self) -> Digest { + todo!() + } + + pub fn release(self) -> SHA256 { + sysctl::clk_en_peri().modify(|_r, w| + w.sha_clk_en().clear_bit()); + self.sha256 + } +} + +pub struct Digest { + sha256: SHA256, +} + +impl Digest { + pub fn write_u32(&mut self, n: u32) { + let _todo = n; + todo!() + } + + pub fn finish(&self, out: &mut [u8; 32]) { + let _todo = out; + todo!() + } + + pub fn free(self) -> Sha256 { + Sha256 { sha256: self.sha256 } + } +} diff --git a/third-party/k210-hal/src/spi.rs b/third-party/k210-hal/src/spi.rs new file mode 100644 index 00000000..89a7f91f --- /dev/null +++ b/third-party/k210-hal/src/spi.rs @@ -0,0 +1,122 @@ +//! (TODO) Serial Peripheral Interface (SPI) + +use crate::pac::SPI0; +use crate::clock::Clocks; +use crate::sysctl::{self, APB0}; +pub use embedded_hal::spi::{Mode, Polarity, Phase}; +use core::convert::Infallible; + +/// +pub struct Spi { + spi: SPI +} + +impl Spi { + pub fn spi0( + spi: SPI0, + mode: Mode, + frame_format: FrameFormat, + endian: Endian, + clock: &Clocks, + apb0: &mut APB0 + ) -> Self { + let work_mode = hal_mode_to_pac(mode); + let frame_format = frame_format_to_pac(frame_format); + let tmod = crate::pac::spi0::ctrlr0::TMOD_A::TRANS_RECV; // todo other modes + let endian = endian as u32; + let data_bit_length = 8; // todo more length + let _ = clock; // todo + unsafe { + // no interrupts for now + spi.imr.write(|w| w.bits(0x00)); + // no dma for now + spi.dmacr.write(|w| w.bits(0x00)); + spi.dmatdlr.write(|w| w.bits(0x10)); + spi.dmardlr.write(|w| w.bits(0x00)); + // no slave access for now + spi.ser.write(|w| w.bits(0x00)); + spi.ssienr.write(|w| w.bits(0x00)); + // set control registers + spi.ctrlr0.write(|w| { + w.work_mode() + .variant(work_mode) + .tmod() + .variant(tmod) + .frame_format() + .variant(frame_format) + .data_length() + .bits(data_bit_length - 1) + }); + spi.spi_ctrlr0.reset(); // standard + spi.endian.write(|w| w.bits(endian)); + } + // enable APB0 bus + apb0.enable(); + // enable peripheral via sysctl + sysctl::clk_en_peri().modify(|_r, w| + w.spi0_clk_en().set_bit()); + Spi { spi } + } + + pub fn release(self) -> SPI0 { + // power off + sysctl::clk_en_peri().modify(|_r, w| + w.spi0_clk_en().clear_bit()); + self.spi + } +} + +impl embedded_hal::spi::FullDuplex for Spi { + /// An enumeration of SPI errors + type Error = Infallible; + + /// Reads the word stored in the shift register + /// + /// **NOTE** A word must be sent to the slave before attempting to call this + /// method. + fn try_read(&mut self) -> nb::Result { + todo!() + } + + /// Sends a word to the slave + fn try_send(&mut self, word: u8) -> nb::Result<(), Self::Error> { + todo!("{}", word) + } +} + +#[derive(Clone, Copy, PartialEq, Eq)] +pub enum FrameFormat { + Standard, + Dual, + Quad, + Octal, +} +#[derive(Clone, Copy, PartialEq, Eq)] +#[repr(u32)] +pub enum Endian { + Little = 0, + Big = 1, +} + +#[inline] +fn hal_mode_to_pac(mode: Mode) -> crate::pac::spi0::ctrlr0::WORK_MODE_A { + use crate::pac::spi0::ctrlr0::WORK_MODE_A; + use {Polarity::*, Phase::*}; + match (mode.polarity, mode.phase) { + (IdleLow, CaptureOnFirstTransition) => WORK_MODE_A::MODE0, + (IdleLow, CaptureOnSecondTransition) => WORK_MODE_A::MODE1, + (IdleHigh, CaptureOnFirstTransition) => WORK_MODE_A::MODE2, + (IdleHigh, CaptureOnSecondTransition) => WORK_MODE_A::MODE3, + } +} + +#[inline] +fn frame_format_to_pac(frame_format: FrameFormat) -> crate::pac::spi0::ctrlr0::FRAME_FORMAT_A { + use crate::pac::spi0::ctrlr0::FRAME_FORMAT_A; + match frame_format { + FrameFormat::Standard => FRAME_FORMAT_A::STANDARD, + FrameFormat::Dual => FRAME_FORMAT_A::DUAL, + FrameFormat::Quad => FRAME_FORMAT_A::QUAD, + FrameFormat::Octal => FRAME_FORMAT_A::OCTAL, + } +} diff --git a/third-party/k210-hal/src/stdout.rs b/third-party/k210-hal/src/stdout.rs new file mode 100644 index 00000000..8483cc40 --- /dev/null +++ b/third-party/k210-hal/src/stdout.rs @@ -0,0 +1,31 @@ +//! Stdout +pub use core::fmt::Write; +use nb::block; + +/// Stdout implements the core::fmt::Write trait for hal::serial::Write +/// implementations. +pub struct Stdout<'p, T>(pub &'p mut T); + +impl<'p, T> Write for Stdout<'p, T> + where + T: embedded_hal::serial::Write, +{ + fn write_str(&mut self, s: &str) -> core::fmt::Result { + for byte in s.as_bytes() { + if *byte == b'\n' { + let res = block!(self.0.try_write(b'\r')); + + if res.is_err() { + return Err(core::fmt::Error); + } + } + + let res = block!(self.0.try_write(*byte)); + + if res.is_err() { + return Err(core::fmt::Error); + } + } + Ok(()) + } +} diff --git a/third-party/k210-hal/src/sysctl.rs b/third-party/k210-hal/src/sysctl.rs new file mode 100644 index 00000000..f2e66495 --- /dev/null +++ b/third-party/k210-hal/src/sysctl.rs @@ -0,0 +1,61 @@ +//! (TODO) System Controller (SYSCTL) + +use crate::pac::{sysctl, SYSCTL}; + +pub(crate) fn sysctl<'a>() -> &'a sysctl::RegisterBlock { + unsafe { &*(SYSCTL::ptr()) } +} + +pub(crate) fn clk_en_cent<'a>() -> &'a sysctl::CLK_EN_CENT { + &sysctl().clk_en_cent +} + +pub(crate) fn clk_en_peri<'a>() -> &'a sysctl::CLK_EN_PERI { + &sysctl().clk_en_peri +} + +pub(crate) fn peri_reset<'a>() -> &'a sysctl::PERI_RESET { + &sysctl().peri_reset +} + +pub trait SysctlExt { + fn constrain(self) -> Parts; +} + +impl SysctlExt for SYSCTL { + fn constrain(self) -> Parts { + Parts { + apb0: APB0 { _ownership: () }, + } + } +} + +// ref: sysctl.c +pub struct Parts { + // todo: PLL0, PLL1, PLL2 + // todo: CPU, SRAM, APB-bus, ROM, DMA, AI + pub apb0: APB0, + // pub apb1: APB1, + // pub apb2: APB2, +} + +pub struct APB0 { + _ownership: () +} + +impl APB0 { + pub(crate) fn enable(&mut self) { + clk_en_cent().modify( + |_r, w| + w.apb0_clk_en().set_bit() + ); + } +} + +// pub struct APB1 { +// _ownership: () +// } + +// pub struct APB2 { +// _ownership: () +// } diff --git a/third-party/k210-hal/src/time.rs b/third-party/k210-hal/src/time.rs new file mode 100644 index 00000000..c21a86fa --- /dev/null +++ b/third-party/k210-hal/src/time.rs @@ -0,0 +1,68 @@ +//! Time units + +/// Bits per second +#[derive(Clone, Copy)] +pub struct Bps(pub u32); + +/// Hertz +#[derive(Clone, Copy)] +pub struct Hertz(pub u32); + +/// KiloHertz +#[derive(Clone, Copy)] +pub struct KiloHertz(pub u32); + +/// MegaHertz +#[derive(Clone, Copy)] +pub struct MegaHertz(pub u32); + +/// Extension trait that adds convenience methods to the `u32` type +pub trait U32Ext { + /// Wrap in `Bps` + fn bps(self) -> Bps; + + /// Wrap in `Hertz` + fn hz(self) -> Hertz; + + /// Wrap in `KiloHertz` + fn khz(self) -> KiloHertz; + + /// Wrap in `MegaHertz` + fn mhz(self) -> MegaHertz; +} + +impl U32Ext for u32 { + fn bps(self) -> Bps { + Bps(self) + } + + fn hz(self) -> Hertz { + Hertz(self) + } + + fn khz(self) -> KiloHertz { + KiloHertz(self) + } + + fn mhz(self) -> MegaHertz { + MegaHertz(self) + } +} + +impl Into for KiloHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> KiloHertz { + KiloHertz(self.0 * 1_000) + } +} diff --git a/third-party/k210-pac/.gitignore b/third-party/k210-pac/.gitignore new file mode 100644 index 00000000..2f88dbac --- /dev/null +++ b/third-party/k210-pac/.gitignore @@ -0,0 +1,3 @@ +/target +**/*.rs.bk +Cargo.lock \ No newline at end of file diff --git a/third-party/k210-pac/.travis.yml b/third-party/k210-pac/.travis.yml new file mode 100644 index 00000000..6fbe7e6b --- /dev/null +++ b/third-party/k210-pac/.travis.yml @@ -0,0 +1,28 @@ +language: rust + +env: + - TARGET=x86_64-unknown-linux-gnu + - TARGET=riscv64gc-unknown-none-elf + +rust: + - nightly + - stable + +if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + + +install: + - ci/install.sh + +script: + - ci/script.sh + +branches: + only: + - master + - staging + - trying + +notifications: + email: + on_success: never diff --git a/third-party/k210-pac/CODE_OF_CONDUCT.md b/third-party/k210-pac/CODE_OF_CONDUCT.md new file mode 100644 index 00000000..fccadf9a --- /dev/null +++ b/third-party/k210-pac/CODE_OF_CONDUCT.md @@ -0,0 +1,37 @@ +# The Rust Code of Conduct + +## Conduct + +**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team) + +* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic. +* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all. +* Please be kind and courteous. There's no need to be mean or rude. +* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer. +* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works. +* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups. +* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back. +* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome. + +## Moderation + +These are the policies for upholding our community's standards of conduct. + +1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.) +2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed. +3. Moderators will first respond to such remarks with a warning. +4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off. +5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded. +6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology. +7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed. +8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others. + +In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely. + +And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust. + +The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org). + +*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).* + +[team]: https://github.com/rust-embedded/wg#the-riscv-team diff --git a/third-party/k210-pac/Cargo.toml b/third-party/k210-pac/Cargo.toml new file mode 100644 index 00000000..66080af2 --- /dev/null +++ b/third-party/k210-pac/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "k210-pac" +version = "0.2.0" +authors = ["The RISC-V Team "] +categories = ["embedded", "hardware-support", "no-std"] +description = "Peripheral access API for K210 SoC" +repository = "https://github.com/riscv-rust/k210-pac" +keywords = ["riscv", "k210", "register", "peripheral"] +license = "ISC" +edition = "2018" + +[dependencies] +bare-metal = "0.2.4" +riscv = "0.6.0" +riscv-rt = { version = "0.8", optional = true } +vcell = "0.1.2" + +[features] +rt = ["riscv-rt"] diff --git a/third-party/k210-pac/README.md b/third-party/k210-pac/README.md new file mode 100644 index 00000000..eccb942f --- /dev/null +++ b/third-party/k210-pac/README.md @@ -0,0 +1,36 @@ +[![crates.io](https://img.shields.io/crates/d/k210-pac.svg)](https://crates.io/crates/k210-pac) +[![crates.io](https://img.shields.io/crates/v/k210-pac.svg)](https://crates.io/crates/k210-pac) +[![Build Status](https://travis-ci.org/riscv-rust/k210-pac.svg?branch=master)](https://travis-ci.org/riscv-rust/k210-pac) + +# `k210-pac` + +> Peripheral access API for K210 SoC + +This project is developed and maintained by the [RISC-V team][team]. + +## [Documentation](https://docs.rs/crate/k210-pac) + +## License + +Copyright 2019 [RISC-V team][team] + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +## Code of Conduct + +Contribution to this crate is organized under the terms of the [Rust Code of +Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises +to intervene to uphold that code of conduct. + +[CoC]: CODE_OF_CONDUCT.md +[team]: https://github.com/rust-embedded/wg#the-risc-v-team diff --git a/third-party/k210-pac/build.rs b/third-party/k210-pac/build.rs new file mode 100644 index 00000000..41ec77f4 --- /dev/null +++ b/third-party/k210-pac/build.rs @@ -0,0 +1,15 @@ +use std::io::Write; +use std::path::PathBuf; +use std::{env, fs}; + +fn main() { + // Put the linker script somewhere the linker can find it + let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); + println!("cargo:rustc-link-search={}", out_dir.display()); + + fs::File::create(out_dir.join("memory-k210.x")) + .unwrap() + .write_all(include_bytes!("memory-k210.x")) + .unwrap(); + println!("cargo:rerun-if-changed=memory-k210.x"); +} diff --git a/third-party/k210-pac/ci/install.sh b/third-party/k210-pac/ci/install.sh new file mode 100755 index 00000000..ce4ea1e9 --- /dev/null +++ b/third-party/k210-pac/ci/install.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +set -euxo pipefail + +rustup target add $TARGET diff --git a/third-party/k210-pac/ci/script.sh b/third-party/k210-pac/ci/script.sh new file mode 100755 index 00000000..70fa0f49 --- /dev/null +++ b/third-party/k210-pac/ci/script.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +set -euxo pipefail + +cargo check --target $TARGET +cargo check --target $TARGET --features rt diff --git a/third-party/k210-pac/k210.svd b/third-party/k210-pac/k210.svd new file mode 100644 index 00000000..c2f99331 --- /dev/null +++ b/third-party/k210-pac/k210.svd @@ -0,0 +1,7718 @@ + + + Canaan Inc. + K210 + 1.0 + Kendryte K210 64-bit RISC-V CPU + + 8 + 64 + 32 + read-write + + + 0x00000000 + 0xFFFFFFFF + + + + + CLINT + Core Local Interruptor + CLINT + 0x02000000 + + + 2 + 0x04 + msip[%s] + Hart software interrupt register + 0x0000 + + + 0 + 1 + + + + + 64 + 2 + 0x08 + mtimecmp[%s] + Hart time comparator register + 0x4000 + + + 64 + mtime + Timer register + 0xBFF8 + + + + + + + + PLIC + Platform-Level Interrupt Controller + PLIC + 0x0C000000 + + + 1024 + 0x04 + priority[%s] + Interrupt Source Priority Register + 0x000000 + + + + + 32 + 0x04 + pending[%s] + Interrupt Pending Register + 0x001000 + + + target_enables[%s] + Target Interrupt Enables + 0x002000 + 4 + 0x80 + + 32 + 0x04 + enable[%s] + Interrupt Enable Register + 0 + + + + targets[%s] + Target Configuration + 0x200000 + 4 + 0x1000 + + threshold + Priority Threshold Register + 0x0 + + + priority + 20 + + Priority + + Never + Never interrupt + 0 + + + P1 + Priority 1 + 1 + + + P2 + Priority 2 + 2 + + + P3 + Priority 3 + 3 + + + P4 + Priority 4 + 4 + + + P5 + Priority 5 + 5 + + + P6 + Priority 6 + 6 + + + P7 + Priority 7 + 7 + + + + + + + claim + Claim/Complete Register + 0x4 + + 0x00000000 + 0xFFFFFFFF + + + + _reserved + Padding to make sure targets is an array + 0xffc + + + + + + + + + UARTHS + High-speed UART + UARTHS + 0x38000000 + + + txdata + Transmit Data Register + 0x00 + + + data + Transmit data + [7:0] + + + full + Transmit FIFO full + [31:31] + + + + + + rxdata + Receive Data Register + 0x04 + + + data + Received data + [7:0] + + + empty + Receive FIFO empty + [31:31] + + + + + + txctrl + Transmit Control Register + 0x08 + + + txen + Transmit enable + [0:0] + + + nstop + Number of stop bits + [1:1] + + + txcnt + Transmit watermark level + [18:16] + + + + + + rxctrl + Receive Control Register + 0x0C + + + rxen + Receive enable + [0:0] + + + rxcnt + Receive watermark level + [18:16] + + + + + + ie + Interrupt Enable Register + 0x10 + + + txwm + Transmit watermark interrupt enable + [0:0] + + + rxwm + Receive watermark interrupt enable + [1:1] + + + + + + ip + Interrupt Pending Register + 0x14 + + + txwm + Transmit watermark interrupt pending + [0:0] + + + rxwm + Receive watermark interrupt pending + [1:1] + + + + + + div + Baud Rate Divisor Register + 0x18 + + + div + Baud rate divisor + [15:0] + + + + + + UARTHS + 33 + + + + + + + GPIOHS + High-speed GPIO + GPIOHS + 0x38001000 + + + input_val + Input Value Register + 0x000 + + + pin%s + 0 + 0 + 32 + 1 + + + + + input_en + Pin Input Enable Register + 0x004 + + + pin%s + 0 + 0 + 32 + 1 + + + + + output_en + Pin Output Enable Register + 0x008 + + + pin%s + 0 + 0 + 32 + 1 + + + + + output_val + Output Value Register + 0x00C + + + pin%s + 0 + 0 + 32 + 1 + + + + + pullup_en + Internal Pull-Up Enable Register + 0x010 + + + pin%s + 0 + 0 + 32 + 1 + + + + + drive + Drive Strength Register + 0x014 + + + pin%s + 0 + 0 + 32 + 1 + + + + + rise_ie + Rise Interrupt Enable Register + 0x018 + + + pin%s + 0 + 0 + 32 + 1 + + + + + rise_ip + Rise Interrupt Pending Register + 0x01C + + + pin%s + 0 + 0 + 32 + 1 + + + + + fall_ie + Fall Interrupt Enable Register + 0x020 + + + pin%s + 0 + 0 + 32 + 1 + + + + + fall_ip + Fall Interrupt Pending Register + 0x024 + + + pin%s + 0 + 0 + 32 + 1 + + + + + high_ie + High Interrupt Enable Register + 0x028 + + + pin%s + 0 + 0 + 32 + 1 + + + + + high_ip + High Interrupt Pending Register + 0x02C + + + pin%s + 0 + 0 + 32 + 1 + + + + + low_ie + Low Interrupt Enable Register + 0x030 + + + pin%s + 0 + 0 + 32 + 1 + + + + + low_ip + Low Interrupt Pending Register + 0x034 + + + pin%s + 0 + 0 + 32 + 1 + + + + + iof_en + HW I/O Function Enable Register + 0x038 + + + pin%s + 0 + 0 + 32 + 1 + + + + + iof_sel + HW I/O Function Select Register + 0x03C + + + pin%s + 0 + 0 + 32 + 1 + + + + + output_xor + Output XOR (invert) Register + 0x040 + + + pin%s + 0 + 0 + 32 + 1 + + + + + + GPIOHS0 + 34 + + + GPIOHS1 + 35 + + + GPIOHS2 + 36 + + + GPIOHS3 + 37 + + + GPIOHS4 + 38 + + + GPIOHS5 + 39 + + + GPIOHS6 + 40 + + + GPIOHS7 + 41 + + + GPIOHS8 + 42 + + + GPIOHS9 + 43 + + + GPIOHS10 + 44 + + + GPIOHS11 + 45 + + + GPIOHS12 + 46 + + + GPIOHS13 + 47 + + + GPIOHS14 + 48 + + + GPIOHS15 + 49 + + + GPIOHS16 + 50 + + + GPIOHS17 + 51 + + + GPIOHS18 + 52 + + + GPIOHS19 + 53 + + + GPIOHS20 + 54 + + + GPIOHS21 + 55 + + + GPIOHS22 + 56 + + + GPIOHS23 + 57 + + + GPIOHS24 + 58 + + + GPIOHS25 + 59 + + + GPIOHS26 + 60 + + + GPIOHS27 + 61 + + + GPIOHS28 + 62 + + + GPIOHS29 + 63 + + + GPIOHS30 + 64 + + + GPIOHS31 + 65 + + + + + + + KPU + Neural Network Accelerator + KPU + 0x40800000 + + + + layer_argument_fifo + Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register + 0x00 + 64 + + + interrupt_status + Interrupt status + 0x08 + 64 + + + calc_done + Interrupt raised when calculation is done + [0:0] + + + layer_cfg_almost_empty + Interrupt raised when layer arguments FIFO almost empty + [1:1] + + + layer_cfg_almost_full + Interrupt raised when layer arguments FIFO almost full + [2:2] + + + + + interrupt_raw + Interrupt raw + 0x10 + 64 + + + interrupt_mask + Interrupt mask: 0 enables the interrupt, 1 masks the interrupt + 0x18 + 64 + + + interrupt_clear + Interrupt clear: write 1 to a bit to clear interrupt + 0x20 + 64 + + + fifo_threshold + FIFO threshold + 0x28 + 64 + + + full_threshold + FIFO full threshold + [3:0] + + + empty_threshold + FIFO empty threshold + [7:4] + + + + + fifo_data_out + FIFO data output + 0x30 + 64 + + + fifo_ctrl + FIFO control + 0x38 + 64 + + + dma_fifo_flush_n + Flush DMA FIFO + [0:0] + + + gs_fifo_flush_n + Flush GS FIFO + [1:1] + + + cfg_fifo_flush_n + Flush configuration FIFO + [2:2] + + + cmd_fifo_flush_n + Flush command FIFO + [3:3] + + + resp_fifo_flush_n + Flush response FIFO + [4:4] + + + + + eight_bit_mode + Eight bit mode + 0x40 + 64 + + + eight_bit_mode + Use 8-bit instead of 16-bit precision if set + [0:0] + + + + + + KPU + 25 + + + + + + + FFT + Fast Fourier Transform Accelerator + FFT + 0x42000000 + + + input_fifo + FFT input data fifo + 0x00 + 64 + + + ctrl + FFT control register + 0x08 + 64 + + + point + FFT calculation data length + [2:0] + + + p512 + 512 point + 0 + + + p256 + 256 point + 1 + + + p128 + 128 point + 2 + + + p64 + 64 point + 3 + + + + + mode + FFT mode + [3:3] + + + fft + FFT mode + 0 + + + ifft + Inverse FFT mode + 1 + + + + + shift + Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ... + [12:4] + + + enable + FFT enable + [13:13] + + + dma_send + FFT DMA enable + [14:14] + + + input_mode + Input data arrangement + [16:15] + + + riri + RIRI (real imaginary interleaved) + 0 + + + rrrr + RRRR (only real part) + 1 + + + rrii + First input the real part and then input the imaginary part + 2 + + + + + data_mode + Effective width of input data + [17:17] + + + width_64 + 64 bit effective + 0 + + + width_128 + 128 bit effective + 1 + + + + + + + + fifo_ctrl + FIFO control + 0x10 + 64 + + + resp_fifo_flush + Response memory initialization flag + [0:0] + + + cmd_fifo_flush + Command memory initialization flag + [1:1] + + + gs_fifo_flush + Output interface memory initialization flag + [2:2] + + + + + + intr_mask + interrupt mask + 0x18 + 64 + + + fft_done + FFT done + [0:0] + + + + + + intr_clear + Interrupt clear + 0x20 + 64 + + + fft_done + FFT done + [0:0] + + + + + + status + FFT status register + 0x28 + 64 + + + fft_done + FFT done + [0:0] + + + + + + status_raw + FFT status raw + 0x30 + 64 + + + fft_done + FFT done + [0:0] + + + fft_work + FFT work + [1:1] + + + + + + output_fifo + FFT output FIFO + 0x38 + 64 + + + + FFT + 26 + + + + + + + DMAC + Direct Memory Access Controller + DMAC + 0x50000000 + + + + id + ID Register + 0x00 + 64 + + + compver + COMPVER Register + 0x08 + 64 + + + cfg + Configure Register + 0x10 + 64 + + + dmac_en + Enable DMAC + [0:0] + + + int_en + Globally enable interrupt generation + [1:1] + + + + + + chen + Channel Enable Register + 0x18 + 64 + + + ch%s_en + Enable channel %s + [0:0] + 6 + 1 + 1-6 + + + + ch%s_en_we + Write enable channel %s + [8:8] + 6 + 1 + 1-6 + + + + ch%s_susp + Suspend request channel %s + [16:16] + 6 + 1 + 1-6 + + + + ch%s_susp_we + Enable write to ch%s_susp bit + [24:24] + 6 + 1 + 1-6 + + + + ch%s_abort + Abort request channel %s + [32:32] + 6 + 1 + 1-6 + + + + ch%s_abort_we + Enable write to ch%s_abort bit + [40:40] + 6 + 1 + 1-6 + + + + + + + intstatus + Interrupt Status Register + 0x30 + 64 + + + ch%s_intstat + Channel %s interrupt bit + [0:0] + 6 + 1 + 1-6 + + + + commonreg_intstat + Common register status bit + [16:16] + + + + + + com_intclear + Common Interrupt Clear Register + 0x38 + 64 + + + slvif_dec_err + Clear slvif_dec_err interrupt in com_intstatus + [0:0] + + + slvif_wr2ro_err + Clear slvif_wr2ro_err interrupt in com_intstatus + [1:1] + + + slvif_rd2wo_err + Clear slvif_rd2wo_err interrupt in com_intstatus + [2:2] + + + slvif_wronhold_err + Clear slvif_wronhold_err interrupt in com_intstatus + [3:3] + + + + slvif_undefinedreg_dec_err + Clear slvif_undefinedreg_dec_err in com_intstatus + [8:8] + + + + + + com_intstatus_en + Common Interrupt Status Enable Register + 0x40 + 64 + + + slvif_dec_err + Slave Interface Common Register Decode Error + [0:0] + + + slvif_wr2ro_err + Slave Interface Common Register Write to Read only Error + [1:1] + + + slvif_rd2wo_err + Slave Interface Common Register Read to Write-only Error + [2:2] + + + slvif_wronhold_err + Slave Interface Common Register Write On Hold Error + [3:3] + + + + slvif_undefinedreg_dec_err + Slave Interface Undefined Register Decode Error + [8:8] + + + + + + com_intsignal_en + Common Interrupt Signal Enable Register + 0x48 + 64 + + + slvif_dec_err + Slave Interface Common Register Decode Error + [0:0] + + + slvif_wr2ro_err + Slave Interface Common Register Write to Read only Error + [1:1] + + + slvif_rd2wo_err + Slave Interface Common Register Read to Write-only Error + [2:2] + + + slvif_wronhold_err + Slave Interface Common Register Write On Hold Error + [3:3] + + + + slvif_undefinedreg_dec_err + Slave Interface Undefined Register Decode Error + [8:8] + + + + + + com_intstatus + Common Interrupt Status + 0x50 + 64 + + + slvif_dec_err + Slave Interface Common Register Decode Error + [0:0] + + + slvif_wr2ro_err + Slave Interface Common Register Write to Read only Error + [1:1] + + + slvif_rd2wo_err + Slave Interface Common Register Read to Write-only Error + [2:2] + + + slvif_wronhold_err + Slave Interface Common Register Write On Hold Error + [3:3] + + + + slvif_undefinedreg_dec_err + Slave Interface Undefined Register Decode Error + [8:8] + + + + + + reset + Reset register + 0x58 + 64 + + + rst + DMAC reset request bit + [0:0] + + + + + + + channel[%s] + Channel configuration + 6 + 0x100 + 0x100 + 64 + + sar + SAR Address Register + 0x00 + + + dar + DAR Address Register + 0x08 + + + block_ts + Block Transfer Size Register + 0x10 + + + block_ts + Block transfer size + [21:0] + + + + + + ctl + Control Register + 0x18 + + + sms + Source master select + [0:0] + + MASTER_SELECT + + axi_master_1 + AXI master 1 + 0 + + + axi_master_2 + AXI master 2 + 1 + + + + + + dms + Destination master select + [2:2] + + + + + sinc + Source address increment + [4:4] + + INCREMENT + + increment + Increment address + 0 + + + nochange + Don't increment address + 1 + + + + + + dinc + Destination address increment + [6:6] + + + + + src_tr_width + Source transfer width + [10:8] + + TRANSFER_WIDTH + + width_8 + 8 bits + 0 + + + width_16 + 16 bits + 1 + + + width_32 + 32 bits + 2 + + + width_64 + 64 bits + 3 + + + width_128 + 128 bits + 4 + + + width_256 + 256 bits + 5 + + + width_512 + 512 bits + 6 + + + + + dst_tr_width + Destination transfer width + [13:11] + + + + src_msize + Source burst transaction length + [17:14] + + BURST_LENGTH + + length_1 + 1 data item + 0 + + + length_4 + 4 data items + 1 + + + length_8 + 8 data items + 2 + + + length_16 + 16 data items + 3 + + + length_32 + 32 data items + 4 + + + length_64 + 64 data items + 5 + + + length_128 + 128 data items + 6 + + + length_256 + 256 data items + 7 + + + length_512 + 512 data items + 8 + + + length_1024 + 1024 data items + 9 + + + + + dst_msize + Destination burst transaction length + [21:18] + + + + + nonposted_lastwrite_en + Non Posted Last Write Enable (posted writes may be used till the end of the block) + [30:30] + + + + arlen_en + Source burst length enable + [38:38] + + + arlen + Source burst length + [46:39] + + + awlen_en + Destination burst length enable + [47:47] + + + awlen + Destination burst length + [55:48] + + + src_stat_en + Source status enable + [56:56] + + + dst_stat_en + Destination status enable + [57:57] + + + ioc_blktfr + Interrupt completion of block transfer + [58:58] + + + + shadowreg_or_lli_last + Last shadow linked list item (indicates shadowreg/LLI content is the last one) + [62:62] + + + shadowreg_or_lli_valid + last shadow linked list item valid (indicate shadowreg/LLI content is valid) + [63:63] + + + + + cfg + Configure Register + 0x20 + + + src_multblk_type + Source multi-block transfer type + [1:0] + + MULTIBLK_TRANSFER_TYPE + + contiguous + Continuous multi-block type + 0 + + + reload + Reload multi-block type + 1 + + + shadow_register + Shadow register based multi-block type + 2 + + + linked_list + Linked list based multi-block type + 3 + + + + + dst_multblk_type + Destination multi-block transfer type + [3:2] + + + + + tt_fc + Transfer type and flow control + [34:32] + + + mem2mem_dma + Transfer memory to memory and flow controller is DMAC + 0 + + + mem2prf_dma + Transfer memory to peripheral and flow controller is DMAC + 1 + + + prf2mem_dma + Transfer peripheral to memory and flow controller is DMAC + 2 + + + prf2prf_dma + Transfer peripheral to peripheral and flow controller is DMAC + 3 + + + prf2mem_prf + Transfer peripheral to memory and flow controller is source peripheral + 4 + + + prf2prf_srcprf + Transfer peripheral to peripheral and flow controller is source peripheral + 5 + + + mem2prf_prf + Transfer memory to peripheral and flow controller is destination peripheral + 6 + + + prf2prf_dstprf + Transfer peripheral to peripheral and flow controller is destination peripheral + 7 + + + + + hs_sel_src + Source software or hardware handshaking select + [35:35] + + HANDSHAKING + + hardware + Hardware handshaking is used + 0 + + + software + Software handshaking is used + 1 + + + + + hs_sel_dst + Destination software or hardware handshaking select + [36:36] + + + + src_hwhs_pol + Source hardware handshaking interface polarity + [37:37] + + POLARITY + + active_high + Active high + 0 + + + active_low + Active low + 1 + + + + + dst_hwhs_pol + Destination hardware handshaking interface polarity + [38:38] + + + + src_per + Assign a hardware handshaking interface to source of channel + [42:39] + + + + dst_per + Assign a hardware handshaking interface to destination of channel + [47:44] + + + + ch_prior + Channel priority (7 is highest, 0 is lowest) + [51:49] + + + lock_ch + Channel lock bit + [52:52] + + + lock_ch_l + Channel lock level + [54:53] + + + dma_transfer + Duration of channel is locked for entire DMA transfer + 0 + + + block_transfer + Duration of channel is locked for current block transfer + 1 + + + transaction + Duration of channel is locked for current transaction + 2 + + + + + src_osr_lmt + Source outstanding request limit + [58:55] + + + dst_osr_lmt + Destination outstanding request limit + [62:59] + + + + + + llp + Linked List Pointer register + 0x28 + + + lms + LLI master select + [0:0] + + + + + loc + Starting address memeory of LLI block + [63:6] + + + + + status + Channel Status Register + 0x30 + + + cmpltd_blk_size + Completed block transfer size + [21:0] + + + + + + swhssrc + Channel Software handshake Source Register + 0x38 + + + req + Software handshake request for channel source + [0:0] + + + req_we + Write enable bit for software handshake request + [1:1] + + + sglreq + Software handshake single request for channel source + [2:2] + + + sglreq_we + Write enable bit for software handshake + [3:3] + + + lst + Software handshake last request for channel source + [4:4] + + + lst_we + Write enable bit for software handshake last request + [5:5] + + + + + + swhsdst + Channel Software handshake Destination Register + 0x40 + + + req + Software handshake request for channel destination + [0:0] + + + req_we + Write enable bit for software handshake request + [1:1] + + + sglreq + Software handshake single request for channel destination + [2:2] + + + sglreq_we + Write enable bit for software handshake + [3:3] + + + lst + Software handshake last request for channel destination + [4:4] + + + lst_we + Write enable bit for software handshake last request + [5:5] + + + + + + blk_tfr + Channel Block Transfer Resume Request Register + 0x48 + + + resumereq + Block transfer resume request + [0:0] + + + + + + axi_id + Channel AXI ID Register + 0x50 + + + axi_qos + AXI QOS Register + 0x58 + + + + intstatus_en + Interrupt Status Enable Register + 0x80 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + intstatus + Channel Interrupt Status Register + 0x88 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + intsignal_en + Interrupt Signal Enable Register + 0x90 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + intclear + Interrupt Clear Register + 0x98 + + + block_tfr_done + Block transfer done + [0:0] + + + tfr_done + Transfer done + [1:1] + + + + src_transcomp + Source transaction complete + [3:3] + + + dst_transcomp + Destination transaction complete + [4:4] + + + src_dec_err + Source Decode Error + [5:5] + + + dst_dec_err + Destination Decode Error + [6:6] + + + src_slv_err + Source Slave Error + [7:7] + + + dst_slv_err + Destination Slave Error + [8:8] + + + lli_rd_dec_err + LLI Read Decode Error Status Enable + [9:9] + + + lli_wr_dec_err + LLI WRITE Decode Error + [10:10] + + + lli_rd_slv_err + LLI Read Slave Error + [11:11] + + + lli_wr_slv_err + LLI WRITE Slave Error + [12:12] + + + + + + + _reserved + Padding to make structure size 256 bytes so that channels[] is an array + 0xf8 + + + + + DMA0 + 27 + + + DMA1 + 28 + + + DMA2 + 29 + + + DMA3 + 30 + + + DMA4 + 31 + + + DMA5 + 32 + + + + + + + GPIO + General Purpose Input/Output Interface + GPIO + 0x50200000 + + + data_output + Data (output) registers + 0x00 + + + pin%s + 0 + 0 + 8 + 1 + + + + + direction + Data direction registers + 0x04 + + + pin%s + 0 + 0 + 8 + 1 + + DIRECTION + + input + Pin is input + 0 + + + output + Pin is output + 1 + + + + + + + source + Data source registers + 0x08 + + + interrupt_enable + Interrupt enable/disable registers + 0x30 + + + interrupt_mask + Interrupt mask registers + 0x34 + + + interrupt_level + Interrupt level registers + 0x38 + + + interrupt_polarity + Interrupt polarity registers + 0x3c + + + interrupt_status + Interrupt status registers + 0x40 + + + interrupt_status_raw + Raw interrupt status registers + 0x44 + + + interrupt_debounce + Interrupt debounce registers + 0x48 + + + interrupt_clear + Registers for clearing interrupts + 0x4c + + + data_input + External port (data input) registers + 0x50 + + + pin%s + 0 + 0 + 8 + 1 + + + + + sync_level + Sync level registers + 0x60 + + + id_code + ID code + 0x64 + + + interrupt_bothedge + Interrupt both edge type + 0x68 + + + + APB_GPIO + 23 + + + + + + + UART1 + Universal Asynchronous Receiver-Transmitter 1 + UART + 0x50210000 + + + rbr_dll_thr + Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W) + 0x00 + + + dlh_ier + Divisor Latch (High) / Interrupt Enable Register + 0x04 + + + fcr_iir + FIFO Control Register / Interrupt Identification Register + 0x08 + + + lcr + Line Control Register + 0x0c + + + mcr + Modem Control Register + 0x10 + + + lsr + Line Status Register + 0x14 + + + msr + Modem Status Register + 0x18 + + + scr + Scratchpad Register + 0x1c + + + lpdll + Low Power Divisor Latch (Low) Register + 0x20 + + + lpdlh + Low Power Divisor Latch (High) Register + 0x24 + + + srbr_sthr[%s] + 16 + 4 + Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W) + 0x30 + + + far + FIFO Access Register + 0x70 + + + tfr + Transmit FIFO Read Register + 0x74 + + + rfw + Receive FIFO Write Register + 0x78 + + + usr + UART Status Register + 0x7c + + + tfl + Transmit FIFO Level + 0x80 + + + rfl + Receive FIFO Level + 0x84 + + + srr + Software Reset Register + 0x88 + + + srts + Shadow Request to Send Register + 0x8c + + + sbcr + Shadow Break Control Register + 0x90 + + + sdmam + Shadow DMA Mode + 0x94 + + + sfe + Shadow FIFO Enable + 0x98 + + + srt + Shadow RCVR Trigger Register + 0x9c + + + stet + Shadow TX Empty Trigger Register + 0xa0 + + + htx + Halt TX Regster + 0xa4 + + + dmasa + DMA Software Acknowledge Register + 0xa8 + + + tcr + Transfer Control Register + 0xac + + + de_en + DE Enable Register + 0xb0 + + + re_en + RE Enable Register + 0xb4 + + + det + DE Assertion Time Register + 0xb8 + + + tat + Turn-Around Time Register + 0xbc + + + dlf + Divisor Latch (Fractional) Register + 0xc0 + + + rar + Receive-Mode Address Register + 0xc4 + + + tar + Transmit-Mode Address Register + 0xc8 + + + lcr_ext + Line Control Register (Extended) + 0xcc + + + cpr + Component Parameter Register + 0xf4 + + + ucv + UART Component Version + 0xf8 + + + ctr + Component Type Register + 0xfc + + + + UART1 + 11 + + + + + + + UART2 + Universal Asynchronous Receiver-Transmitter 2 + 0x50220000 + + UART2 + 12 + + + + + + + UART3 + Universal Asynchronous Receiver-Transmitter 3 + 0x50230000 + + UART3 + 13 + + + + + + + SPI0 + Serial Peripheral Interface 0 (master) + SPI + 0x52000000 + + + + ctrlr0 + Control Register 0 + 0x00 + + + work_mode + WORK_MODE + [7:6] + + + mode0 + MODE_0 + 0 + + + mode1 + MODE_1 + 1 + + + mode2 + MODE_2 + 2 + + + mode3 + MODE_3 + 3 + + + + + tmod + TRANSFER_MODE + [9:8] + + + trans_recv + TRANS_RECV + 0 + + + trans + TRANS + 1 + + + recv + RECV + 2 + + + eerom + EEROM + 3 + + + + + frame_format + FRAME_FORMAT + [22:21] + + + standard + STANDARD + 0 + + + dual + DUAL + 1 + + + quad + QUAD + 2 + + + octal + OCTAL + 3 + + + + + data_length + DATA_BIT_LENGTH + [20:16] + 331 + + + + + + ctrlr1 + Control Register 1 + 0x04 + + + + ssienr + Enable Register + 0x08 + + + + mwcr + Microwire Control Register + 0x0c + + + + ser + Slave Enable Register + 0x10 + + + + baudr + Baud Rate Select + 0x14 + + + + txftlr + Transmit FIFO Threshold Level + 0x18 + + + + rxftlr + Receive FIFO Threshold Level + 0x1c + + + + txflr + Transmit FIFO Level Register + 0x20 + + + + rxflr + Receive FIFO Level Register + 0x24 + + + + sr + Status Register + 0x28 + + + + imr + Interrupt Mask Register + 0x2c + + + + isr + Interrupt Status Register + 0x30 + + + risr + Raw Interrupt Status Register + 0x34 + + + + txoicr + Transmit FIFO Overflow Interrupt Clear Register + 0x38 + + + + rxoicr + Receive FIFO Overflow Interrupt Clear Register + 0x3c + + + + rxuicr + Receive FIFO Underflow Interrupt Clear Register + 0x40 + + + + msticr + Multi-Master Interrupt Clear Register + 0x44 + + + + icr + Interrupt Clear Register + 0x48 + + + + dmacr + DMA Control Register + 0x4c + + + + dmatdlr + DMA Transmit Data Level + 0x50 + + + + dmardlr + DMA Receive Data Level + 0x54 + + + + idr + Identification Register + 0x58 + + + + ssic_version_id + DWC_ssi component version + 0x5c + + + + dr%s + Data Register + 0x60 + 36 + 0-35 + 0x4 + + + + rx_sample_delay + RX Sample Delay Register + 0xf0 + + + + spi_ctrlr0 + SPI Control Register + 0xf4 + + + aitm + instruction_address_trans_mode + [1:0] + + + standard + STANDARD + 0 + + + addr_standard + ADDR_STANDARD + 1 + + + as_frame_format + AS_FRAME_FORMAT + 2 + + + + + addr_length + ADDR_LENGTH + [5:2] + + + inst_length + INSTRUCTION_LENGTH + [9:8] + + + wait_cycles + WAIT_CYCLES + [15:11] + 031 + + + + + + xip_mode_bits + XIP Mode bits + 0xfc + + + xip_incr_inst + XIP INCR transfer opcode + 0x100 + + + + xip_wrap_inst + XIP WRAP transfer opcode + 0x104 + + + xip_ctrl + XIP Control Register + 0x108 + + + + xip_ser + XIP Slave Enable Register + 0x10c + + + + xrxoicr + XIP Receive FIFO Overflow Interrupt Clear Register + 0x110 + + + + xip_cnt_time_out + XIP time out register for continuous transfers + 0x114 + + + + endian + ENDIAN + 0x118 + + + + SPI0 + 1 + + + + + + + SPI1 + Serial Peripheral Interface 1 (master) + 0x53000000 + + SPI1 + 2 + + + + + + + SPI2 + Serial Peripheral Interface 2 (slave) + 0x50240000 + + + + dummy + Dummy register: this peripheral is not implemented yet + 0x00 + + + + SPI_SLAVE + 3 + + + + + + + SPI3 + Serial Peripheral Interface 3 (master) + 0x54000000 + + + + ctrlr0 + Control Register 0 + 0x00 + + + data_length + DATA_BIT_LENGTH + [4:0] + 331 + + + work_mode + WORK_MODE + [9:8] + + + mode0 + MODE_0 + 0 + + + mode1 + MODE_1 + 1 + + + mode2 + MODE_2 + 2 + + + mode3 + MODE_3 + 3 + + + + + tmod + TRANSFER_MODE + [11:10] + + + trans_recv + TRANS_RECV + 0 + + + trans + TRANS + 1 + + + recv + RECV + 2 + + + eerom + EEROM + 3 + + + + + frame_format + FRAME_FORMAT + [23:22] + + + standard + STANDARD + 0 + + + dual + DUAL + 1 + + + quad + QUAD + 2 + + + octal + OCTAL + 3 + + + + + + + + ctrlr1 + Control Register 1 + 0x04 + + + + ssienr + Enable Register + 0x08 + + + + mwcr + Microwire Control Register + 0x0c + + + + ser + Slave Enable Register + 0x10 + + + + baudr + Baud Rate Select + 0x14 + + + + txftlr + Transmit FIFO Threshold Level + 0x18 + + + + rxftlr + Receive FIFO Threshold Level + 0x1c + + + + txflr + Transmit FIFO Level Register + 0x20 + + + + rxflr + Receive FIFO Level Register + 0x24 + + + + sr + Status Register + 0x28 + + + + imr + Interrupt Mask Register + 0x2c + + + + isr + Interrupt Status Register + 0x30 + + + risr + Raw Interrupt Status Register + 0x34 + + + + txoicr + Transmit FIFO Overflow Interrupt Clear Register + 0x38 + + + + rxoicr + Receive FIFO Overflow Interrupt Clear Register + 0x3c + + + + rxuicr + Receive FIFO Underflow Interrupt Clear Register + 0x40 + + + + msticr + Multi-Master Interrupt Clear Register + 0x44 + + + + icr + Interrupt Clear Register + 0x48 + + + + dmacr + DMA Control Register + 0x4c + + + + dmatdlr + DMA Transmit Data Level + 0x50 + + + + dmardlr + DMA Receive Data Level + 0x54 + + + + idr + Identification Register + 0x58 + + + + ssic_version_id + DWC_ssi component version + 0x5c + + + + dr%s + Data Register + 0x60 + 36 + 0-35 + 0x4 + + + + rx_sample_delay + RX Sample Delay Register + 0xf0 + + + + spi_ctrlr0 + SPI Control Register + 0xf4 + + + aitm + instruction_address_trans_mode + [1:0] + + + standard + STANDARD + 0 + + + addr_standard + ADDR_STANDARD + 1 + + + as_frame_format + AS_FRAME_FORMAT + 2 + + + + + addr_length + ADDR_LENGTH + [5:2] + + + inst_length + INSTRUCTION_LENGTH + [9:8] + + + wait_cycles + WAIT_CYCLES + [15:11] + 031 + + + + + + xip_mode_bits + XIP Mode bits + 0xfc + + + xip_incr_inst + XIP INCR transfer opcode + 0x100 + + + + xip_wrap_inst + XIP WRAP transfer opcode + 0x104 + + + xip_ctrl + XIP Control Register + 0x108 + + + + xip_ser + XIP Slave Enable Register + 0x10c + + + + xrxoicr + XIP Receive FIFO Overflow Interrupt Clear Register + 0x110 + + + + xip_cnt_time_out + XIP time out register for continuous transfers + 0x114 + + + + endian + ENDIAN + 0x118 + + + + SPI3 + 4 + + + + + + + I2S0 + Inter-Integrated Sound Interface 0 + I2S + 0x50250000 + + + + ier + Enable Register + 0x00 + + + ien + I2S Enable + [0:0] + + + + + irer + Receiver Block Enable Register + 0x04 + + + rxen + Receiver block enable + [0:0] + + + + + iter + Transmitter Block Enable Register + 0x08 + + + txen + Transmitter block enable + [0:0] + + + + + cer + Clock Generation enable + 0x0c + + + clken + Transmitter block enable + [0:0] + + + + + ccr + Clock Configuration Register + 0x10 + + + clk_gate + Gating of sclk + [2:0] + + + no + Clock gating is disabled + 0 + + + cycles12 + Gating after 12 sclk cycles + 1 + + + cycles16 + Gating after 16 sclk cycles + 2 + + + cycles20 + Gating after 20 sclk cycles + 3 + + + cycles24 + Gating after 24 sclk cycles + 4 + + + + + clk_word_size + The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode + [4:3] + + + cycles16 + 16 sclk cycles + 0 + + + cycles24 + 24 sclk cycles + 1 + + + cycles32 + 32 sclk cycles + 2 + + + + + align_mode + Alignment mode setting + [7:5] + + + standard + Standard I2S format + 1 + + + right + Right aligned format + 2 + + + left + Left aligned format + 4 + + + + + dma_tx_en + DMA transmit enable control + [8:8] + + + dma_rx_en + DMA receive enable control + [9:9] + + + dma_divide_16 + Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en + [10:10] + + + sign_expand_en + SIGN_EXPAND_EN + [11:11] + + + + + rxffr + Receiver Block FIFO Reset Register + 0x14 + + + rxffr + Receiver FIFO reset + [0:0] + + FLUSH + + not_flush + Not flush FIFO + 0 + + + flush + Flush FIFO + 1 + + + + + + + txffr + Transmitter Block FIFO Reset Register + 0x18 + + + rxffr + Transmitter FIFO reset + [0:0] + + + + + + + channel%s + Channel cluster + 0x20 + 4 + 0-3 + 0x40 + + + left_rxtx + Left Receive or Left Transmit Register + 0x00 + + + right_rxtx + + Right Receive or Right Transmit Register + 0x04 + + + rer + Receive Enable Register + 0x08 + + + rxchenx + Receive channel enable/disable + [0:0] + + + + + ter + Transmit Enable Register + 0x0c + + + txchenx + Transmit channel enable/disable + [0:0] + + + + + rcr + Receive Configuration Register + 0x10 + + + wlen + Desired data resolution of receiver + [2:0] + + WLEN + + ignore + Ignore the word length + 0 + + + resolution12 + 12-bit data resolution of the receiver + 1 + + + resolution16 + 16-bit data resolution of the receiver + 2 + + + resolution20 + 20-bit data resolution of the receiver + 3 + + + resolution24 + 24-bit data resolution of the receiver + 4 + + + resolution32 + 32-bit data resolution of the receiver + 5 + + + + + + + tcr + Transmit Configuration Register + 0x14 + + + wlen + Desired data resolution of transmitter + [2:0] + + + + + + + isr + Interrupt Status Register + 0x18 + read-only + + + rxda + Status of receiver data avaliable interrupt + [0:0] + + + rxfo + Status of data overrun interrupt for RX channel + [1:1] + + + txfe + Status of transmit empty triger interrupt + [4:4] + + + txfo + Status of data overrun interrupt for the TX channel + [5:5] + + + + + imr + Interrupt Mask Register + 0x1c + + + rxdam + Mask RX FIFO data avaliable interrupt + [0:0] + + + rxfom + Mask RX FIFO overrun interrupt + [1:1] + + + txfem + Mask TX FIFO empty interrupt + [4:4] + + + txfom + Mask TX FIFO overrun interrupt + [5:5] + + + + + ror + Receive Overrun Register + 0x20 + read-only + + + rxcho + Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun + [0:0] + + + + + tor + Transmit Overrun Register + 0x24 + read-only + + + txcho + Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun + [0:0] + + + + + rfcr + Receive FIFO Configuration Register + 0x28 + + + rxchdt + Trigger level in the RX FIFO at which the receiver data available interrupt generate + [3:0] + + LEVEL + + level1 + Interrupt trigger when FIFO level is 1 + 0 + + + level2 + Interrupt trigger when FIFO level is 2 + 1 + + + level3 + Interrupt trigger when FIFO level is 3 + 2 + + + level4 + Interrupt trigger when FIFO level is 4 + 3 + + + level5 + Interrupt trigger when FIFO level is 5 + 4 + + + level6 + Interrupt trigger when FIFO level is 6 + 5 + + + level7 + Interrupt trigger when FIFO level is 7 + 6 + + + level8 + Interrupt trigger when FIFO level is 8 + 7 + + + level9 + Interrupt trigger when FIFO level is 9 + 8 + + + level10 + Interrupt trigger when FIFO level is 10 + 9 + + + level11 + Interrupt trigger when FIFO level is 11 + 10 + + + level12 + Interrupt trigger when FIFO level is 12 + 11 + + + level13 + Interrupt trigger when FIFO level is 13 + 12 + + + level14 + Interrupt trigger when FIFO level is 14 + 13 + + + level15 + Interrupt trigger when FIFO level is 15 + 14 + + + level16 + Interrupt trigger when FIFO level is 16 + 15 + + + + + + + tfcr + Transmit FIFO Configuration Register + 0x2c + + + txchet + Trigger level in the TX FIFO at which the transmitter data available interrupt generate + [3:0] + + + + + + + rff + Receive FIFO Flush Register + 0x30 + + + rxchfr + Receiver channel FIFO reset + [0:0] + + FLUSH + + not_flush + Not flush an individual FIFO + 0 + + + flush + Flush an indiviadual FIFO + 1 + + + + + + + tff + Transmit FIFO Flush Register + 0x34 + + + rtxchfr + Transmit channel FIFO reset + [0:0] + + + + + + + _reserved%s + _RESERVED0 + 0x38 + 2 + 0-1 + 0x4 + + + + + rxdma + Receiver Block DMA Register + 0x1c0 + + + + rrxdma + Reset Receiver Block DMA Register + 0x1c4 + + + + txdma + Transmitter Block DMA Register + 0x1c8 + + + + rtxdma + Reset Transmitter Block DMA Register + 0x1cc + + + i2s_comp_param_2 + Component Parameter Register 2 + 0x1f0 + + + i2s_comp_param_1 + Component Parameter Register 1 + 0x1f4 + + + i2s_comp_version_1 + Component Version Register + 0x1f8 + + + i2s_comp_type + Component Type Register + 0x1fc + + + + I2S0 + 5 + + + + + + + APU + Audio Processor + APU + 0x50250200 + + + ch_cfg + Channel Config Register + 0x00 + + + sound_ch_en + BF unit sound channel enable control bits + [7:0] + + + target_dir + Target direction select for valid voice output + [11:8] + + + audio_gain + Audio sample gain factor + [22:12] + + + + data_src_mode + Audio data source configure parameter + [24:24] + + + + we_sound_ch_en + Write enable for sound_ch_en parameter + [28:28] + write-only + + + we_target_dir + Write enable for target_dir parameter + [29:29] + write-only + + + we_audio_gain + Write enable for audio_gain parameter + [30:30] + write-only + + + we_data_src_mode + Write enable for data_out_mode parameter + [31:31] + write-only + + + + + ctl + Control Register + 0x04 + + + dir_search_en + Sound direction searching enable bit + [0:0] + + + search_path_reset + Reset all control logic on direction search processing path + [1:1] + + + + stream_gen_en + Valid voice sample stream generation enable bit + [4:4] + + + voice_gen_path_reset + Reset all control logic on voice stream generating path + [5:5] + + + update_voice_dir + Switch to a new voice source direction + [6:6] + + + + we_dir_search_en + Write enable for we_dir_search_en parameter + [8:8] + write-only + + + we_search_path_rst + Write enable for we_search_path_rst parameter + [9:9] + write-only + + + we_stream_gen + Write enable for we_stream_gen parameter + [10:10] + write-only + + + we_voice_gen_path_rst + Write enable for we_voice_gen_path_rst parameter + [11:11] + write-only + + + we_update_voice_dir + Write enable for we_update_voice_dir parameter + [12:12] + write-only + + + + + + dir_bidx[%s] + Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices) + 0x08 + 32 + 0x04 + + + rd_idx%s + rd_idx%s + [5:0] + 4 + 8 + + + + + + pre_fir0_coef[%s] + FIR0 pre-filter coefficients + 0x88 + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + post_fir0_coef[%s] + FIR0 post-filter coefficients + 0xac + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + pre_fir1_coef[%s] + FIR1 pre-filter coeffecients + 0xd0 + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + post_fir1_coef[%s] + FIR1 post-filter coefficients + 0xf4 + 9 + 0x04 + + + tap0 + Tap 0 + [15:0] + + + tap1 + Tap 1 + [31:16] + + + + + dwsz_cfg + Downsize Config Register + 0x118 + + + dir_dwn_siz_rate + Down-sizing ratio used for direction searching + [3:0] + + + voc_dwn_siz_rate + Down-sizing ratio used for voice stream generation + [7:4] + + + smpl_shift_bits + Sample precision reduction when the source sound sample precision is 20/24/32 bits + [12:8] + + + + + + fft_cfg + FFT Config Register + 0x11c + + fft_shift_factor + FFT shift factor + [8:0] + + + + fft_enable + FFT enable + [12:12] + + + + + sobuf_dma_rdata + Read register for DMA to sample-out buffers + 0x120 + + + vobuf_dma_rdata + Read register for DMA to voice-out buffers + 0x124 + + + int_stat + Interrupt Status Register + 0x128 + + + dir_search_data_rdy + Sound direction searching data ready interrupt event + [0:0] + + + voc_buf_data_rdy + Voice output stream buffer data ready interrupt event + [1:1] + + + + + + int_mask + Interrupt Mask Register + 0x12c + + + dir_search_data_rdy + Sound direction searching data ready interrupt event + [0:0] + + + voc_buf_data_rdy + Voice output stream buffer data ready interrupt event + [1:1] + + + + + + sat_counter + Saturation Counter + 0x130 + + + counter + Counter + [15:0] + + + total + Total + [31:16] + + + + + sat_limits + Saturation Limits + 0x134 + + + upper + Upper limit + [15:0] + + + bottom + Bottom limit + [31:16] + + + + + + + + + + I2S1 + Inter-Integrated Sound Interface 1 + 0x50260000 + + I2S1 + 6 + + + + + + + I2S2 + Inter-Integrated Sound Interface 2 + 0x50270000 + + I2S2 + 7 + + + + + + + I2C0 + Inter-Integrated Circuit Bus 0 + I2C + 0x50280000 + + + con + Control Register + 0x00 + + + master_mode + Master Mode + [0:0] + + + speed + Speed + [2:1] + + + standard + STANDARD + 0 + + + fast + FAST + 1 + + + highspeed + HIGHSPEED + 2 + + + + + addr_slave_width + Slave address width + [3:3] + + + b7 + 7-bit address + 0 + + + b10 + 10-bit address + 1 + + + + + restart_en + Enable Restart + [5:5] + + + slave_disable + Disable Slave + [6:6] + + + stop_det + STOP_DET_IFADDRESSED + [7:7] + + + tx_empty + TX_EMPTY_CTRL + [8:8] + + + + + tar + Target Address Register + 0x04 + + + address + Target Address + [9:0] + + + gc + GC_OR_START + [10:10] + + + special + SPECIAL + [11:11] + + + addr_master_width + Master Address + [12:12] + + + b7 + 7-bit address + 0 + + + b10 + 10-bit address + 1 + + + + + + + sar + Slave Address Register + 0x08 + + + address + Slave Address + [9:0] + + + + + data_cmd + Data Buffer and Command Register + 0x10 + + + cmd + CMD + [8:8] + + + data + Data + [7:0] + + + + + ss_scl_hcnt + Standard Speed Clock SCL High Count Register + 0x14 + + + count + COUNT + [15:0] + + + + + ss_scl_lcnt + Standard Speed Clock SCL Low Count Register + 0x18 + + + count + COUNT + [15:0] + + + + + intr_stat + Interrupt Status Register + 0x2c + read-only + + + rx_under + RX_UNDER + [0:0] + + + rx_over + RX_OVER + [1:1] + + + rx_full + RX_FULL + [2:2] + + + tx_over + TX_OVER + [3:3] + + + tx_empty + TX_EMPTY + [4:4] + + + rd_req + RD_REQ + [5:5] + + + tx_abrt + TX_ABRT + [6:6] + + + rx_done + RX_DONE + [7:7] + + + activity + ACTIVITY + [8:8] + + + stop_det + STOP_DET + [9:9] + + + start_det + START_DET + [10:10] + + + gen_call + GEN_CALL + [11:11] + + + + + intr_mask + Interrupt Mask Register + 0x30 + + + rx_under + RX_UNDER + [0:0] + + + rx_over + RX_OVER + [1:1] + + + rx_full + RX_FULL + [2:2] + + + tx_over + TX_OVER + [3:3] + + + tx_empty + TX_EMPTY + [4:4] + + + rd_req + RD_REQ + [5:5] + + + tx_abrt + TX_ABRT + [6:6] + + + rx_done + RX_DONE + [7:7] + + + activity + ACTIVITY + [8:8] + + + stop_det + STOP_DET + [9:9] + + + start_det + START_DET + [10:10] + + + gen_call + GEN_CALL + [11:11] + + + + + raw_intr_stat + Raw Interrupt Status Register + 0x34 + + + rx_under + RX_UNDER + [0:0] + + + rx_over + RX_OVER + [1:1] + + + rx_full + RX_FULL + [2:2] + + + tx_over + TX_OVER + [3:3] + + + tx_empty + TX_EMPTY + [4:4] + + + rd_req + RD_REQ + [5:5] + + + tx_abrt + TX_ABRT + [6:6] + + + rx_done + RX_DONE + [7:7] + + + activity + ACTIVITY + [8:8] + + + stop_det + STOP_DET + [9:9] + + + start_det + START_DET + [10:10] + + + gen_call + GEN_CALL + [11:11] + + + + + rx_tl + Receive FIFO Threshold Register + 0x38 + + + value + VALUE + [2:0] + + + + + tx_tl + Transmit FIFO Threshold Register + 0x3c + + + value + VALUE + [2:0] + + + + + clr_intr + Clear Combined and Individual Interrupt Register + 0x40 + read-only + + + clr + CLR + [0:0] + + + + + clr_rx_under + Clear RX_UNDER Interrupt Register + 0x44 + read-only + + + clr + CLR + [0:0] + + + + + clr_rx_over + Clear RX_OVER Interrupt Register + 0x48 + read-only + + + clr + CLR + [0:0] + + + + + clr_tx_over + Clear TX_OVER Interrupt Register + 0x4c + read-only + + + clr + CLR + [0:0] + + + + + clr_rd_req + Clear RD_REQ Interrupt Register + 0x50 + read-only + + + clr + CLR + [0:0] + + + + + clr_tx_abrt + Clear TX_ABRT Interrupt Register + 0x54 + read-only + + + clr + CLR + [0:0] + + + + + clr_rx_done + Clear RX_DONE Interrupt Register + 0x58 + read-only + + + clr + CLR + [0:0] + + + + + clr_activity + Clear ACTIVITY Interrupt Register + 0x5c + read-only + + + clr + CLR + [0:0] + + + + + clr_stop_det + Clear STOP_DET Interrupt Register + 0x60 + read-only + + + clr + CLR + [0:0] + + + + + clr_start_det + Clear START_DET Interrupt Register + 0x64 + read-only + + + clr + CLR + [0:0] + + + + + clr_gen_call + I2C Clear GEN_CALL Interrupt Register + 0x68 + read-only + + + clr + CLR + [0:0] + + + + + enable + Enable Register + 0x6c + + + enable + ENABLE + [0:0] + + + abort + ABORT + [1:1] + + + tx_cmd_block + TX_CMD_BLOCK + [2:2] + + + + + status + Status Register + 0x70 + read-only + + + activity + ACTIVITY + [0:0] + + + tfnf + TFNF + [1:1] + + + tfe + TFE + [2:2] + + + rfne + RFNE + [3:3] + + + rff + RFF + [4:4] + + + mst_activity + MST_ACTIVITY + [5:5] + + + slv_activity + SLV_ACTIVITY + [6:6] + + + + + txflr + Transmit FIFO Level Register + 0x74 + + + value + VALUE + [2:0] + + + + + rxflr + Receive FIFO Level Register + 0x78 + + + value + VALUE + [2:0] + + + + + sda_hold + SDA Hold Time Length Register + 0x7c + + + tx + TX + [15:0] + + + rx + RX + [23:16] + + + + + tx_abrt_source + Transmit Abort Source Register + 0x80 + + + addr7_noack + 7B_ADDR_NOACK + [0:0] + + + addr1_10_noack + 10B_ADDR1_NOACK + [1:1] + + + addr2_10_noack + 10B_ADDR2_NOACK + [2:2] + + + txdata_noack + TXDATA_NOACK + [3:3] + + + gcall_noack + GCALL_NOACK + [4:4] + + + gcall_read + GCALL_READ + [5:5] + + + hs_ackdet + HS_ACKDET + [6:6] + + + sbyte_ackdet + SBYTE_ACKDET + [7:7] + + + hs_norstrt + HS_NORSTRT + [8:8] + + + sbyte_norstrt + SBYTE_NORSTRT + [9:9] + + + rd_10_norstrt + 10B_RD_NORSTRT + [10:10] + + + master_dis + MASTER_DIS + [11:11] + + + mst_arblost + MST_ARBLOST + [12:12] + + + slvflush_txfifo + SLVFLUSH_TXFIFO + [13:13] + + + slv_arblost + SLV_ARBLOST + [14:14] + + + slvrd_intx + SLVRD_INTX + [15:15] + + + user_abrt + USER_ABRT + [16:16] + + + + + dma_cr + I2C DMA Control Register + 0x88 + + + RDMAE + RDMAE + [0:0] + + + TDMAE + TDMAE + [1:1] + + + + + dma_tdlr + DMA Transmit Data Level Register + 0x8c + + + value + VALUE + [2:0] + + + + + dma_rdlr + DMA Receive Data Level Register + 0x90 + + + value + VALUE + [2:0] + + + + + sda_setup + SDA Setup Register + 0x94 + + + value + VALUE + [7:0] + + + + + general_call + ACK General Call Register + 0x98 + + + call_enable + CALL_ENABLE + [0:0] + + + + + enable_status + Enable Status Register + 0x9c + read-only + + + ic_enable + IC_ENABLE + [0:0] + + + slv_dis_busy + SLV_DIS_BUSY + [1:1] + + + slv_rx_data_lost + SLV_RX_DATA_LOST + [2:2] + + + + + fs_spklen + SS, FS or FM+ spike suppression limit + 0xa0 + + + value + VALUE + [7:0] + + + + + comp_param_1 + Component Parameter Register 1 + 0xf4 + read-only + + + apb_data_width + APB_DATA_WIDTH + [1:0] + + + max_speed_mode + MAX_SPEED_MODE + [3:2] + + + hc_count_values + HC_COUNT_VALUES + [4:4] + + + intr_io + INTR_IO + [5:5] + + + has_dma + HAS_DMA + [6:6] + + + encoded_params + ENCODED_PARAMS + [7:7] + + + rx_buffer_depth + RX_BUFFER_DEPTH + [15:8] + + + tx_buffer_depth + TX_BUFFER_DEPTH + [23:16] + + + + + comp_version + Component Version Register + 0xf8 + read-only + + + value + VALUE + [31:0] + + + + + comp_type + Component Type Register + 0xfc + read-only + + + value + VALUE + [31:0] + + + + + + I2C0 + 8 + + + + + + + I2C1 + Inter-Integrated Circuit Bus 1 + 0x50290000 + + I2C1 + 9 + + + + + + + I2C2 + Inter-Integrated Circuit Bus 2 + 0x502A0000 + + I2C2 + 10 + + + + + + + FPIOA + Field Programmable IO Array + FPIOA + 0x502B0000 + + + 48 + 0x04 + io[%s] + FPIOA GPIO multiplexer io array + 0x00 + + + ch_sel + Channel select from 256 input + [7:0] + + + ds + Driving selector + [11:8] + + + oe_en + Static output enable, will AND with OE_INV + [12:12] + + + oe_inv + Invert output enable + [13:13] + + + do_sel + Data output select: 0 for DO, 1 for OE + [14:14] + + + do_inv + Invert the result of data output select (DO_SEL) + [15:15] + + + pu + Pull up enable. 0 for nothing, 1 for pull up + [16:16] + + + pd + Pull down enable. 0 for nothing, 1 for pull down + [17:17] + + + sl + Slew rate control enable + [19:19] + + + ie_en + Static input enable, will AND with IE_INV + [20:20] + + + ie_inv + Invert input enable + [21:21] + + + di_inv + Invert Data input + [22:22] + + + st + Schmitt trigger + [23:23] + + + pad_di + Read current IO's data input + [31:31] + + + + + 8 + 0x04 + tie_en[%s] + FPIOA GPIO multiplexer tie enable array + 0xC0 + + + 8 + 0x04 + tie_val[%s] + FPIOA GPIO multiplexer tie value array + 0xE0 + + + + + + + + SHA256 + SHA256 Accelerator + SHA256 + 0x502C0000 + + + 8 + 0x4 + result[%s] + Calculated SHA256 return value + 0x00 + + + data_in + SHA256 input data is written to this register + 0x20 + + + num_reg + Counters register + 0x28 + + + data_cnt + The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit + [15:0] + + + data_num + Currently calculated block number. 512bit=1block + [31:16] + + + + + function_reg_0 + Function configuration register 0 + 0x2C + + + en + write:SHA256 enable register. read:Calculation completed flag + [0:0] + + + overflow + SHA256 calculation overflow flag + [8:8] + + + endian + Endian setting + [16:16] + + + le + Little endian + 0 + + + be + Big endian + 1 + + + + + + + function_reg_1 + Function configuration register 1 + 0x34 + + + dma_en + SHA and DMA handshake signals enable. 1:enable; 0:disable + [0:0] + + + fifo_in_full + 1:SHA256 input fifo is full; 0:not full + [8:8] + + + + + + + + + + TIMER0 + Timer 0 + TIMER + 0x502D0000 + + + channel%s + Channel cluster: load_count, current_value, control, eoi and intr_stat registers + 0x0 + 4 + 0-3 + 0x14 + + + load_count + Load Count Register + 0x00 + + + + current_value + Current Value Register + 0x04 + + + control + Control Register + 0x08 + + + enable + ENABLE + [0:0] + + + mode + MODE + [1:1] + + + free + FREE_MODE + 0 + + + user + USER_MODE + 1 + + + + + interrupt + INTERRUPT_MASK + [2:2] + + + pwm_enable + PWM_ENABLE + [3:3] + + + + + + eoi + Interrupt Clear Register + 0x0c + + + + intr_stat + Interrupt Status Register + 0x10 + + + + + intr_stat + Interrupt Status Register + 0xa0 + + + + eoi + Interrupt Clear Register + 0xa4 + + + + raw_intr_stat + Raw Interrupt Status Register + 0xa8 + + + + comp_version + Component Version Register + 0xac + + + + load_count2%s + Load Count2 Register + 0xb0 + 4 + 0-3 + 0x4 + + + + TIMER0A + 14 + TIMER0 channel 0 or 1 interrupt + + + TIMER0B + 15 + TIMER0 channel 2 or 3 interrupt + + + + + + + TIMER1 + Timer 1 + 0x502E0000 + + TIMER1A + 16 + TIMER1 channel 0 or 1 interrupt + + + TIMER1B + 17 + TIMER1 channel 2 or 3 interrupt + + + + + + + TIMER2 + Timer 2 + 0x502F0000 + + TIMER2A + 18 + TIMER2 channel 0 or 1 interrupt + + + TIMER2B + 19 + TIMER2 channel 2 or 3 interrupt + + + + + + + WDT0 + Watchdog Timer 0 + WDT + 0x50400000 + + + cr + Control Register + 0x00 + + + enable + enable + [0:0] + + + rmod + rmod + [1:1] + + + reset + RESET + 0 + + + interrupt + INTERRUPT + 1 + + + + + rpl + rpl + [4:2] + + + + + torr + Timeout Range Register + 0x04 + + + top0 + top (lower half) + [3:0] + + + top1 + top (upper half) + [7:4] + + + + + ccvr + Current Counter Value Register + 0x08 + + + crr + Counter Restart Register + 0x0c + + + stat + Interrupt Status Register + 0x10 + + + stat + stat + [0:0] + + + + + eoi + Interrupt Clear Register + 0x14 + + + eoi + eoi + [0:0] + + + + + + prot_level + Protection level Register + 0x1c + + + prot_level + prot_level + [2:0] + + + + + + comp_param_5 + Component Parameters Register 5 + 0xe4 + + + user_top_max + user_top_max + [31:0] + + + + + comp_param_4 + Component Parameters Register 4 + 0xe8 + + + user_top_init_max + user_top_init_max + [31:0] + + + + + comp_param_3 + Component Parameters Register 3 + 0xec + + + top_rst + top_rst + [31:0] + + + + + comp_param_2 + Component Parameters Register 2 + 0xf0 + + + cnt_rst + cnt_rst + [31:0] + + + + + comp_param_1 + Component Parameters Register 1 + 0xf4 + + + always_en + always_en + [0:0] + + + dflt_rmod + dflt_rmod + [1:1] + + + dual_top + dual_top + [2:2] + + + hc_rmod + hc_rmod + [3:3] + + + hc_rpl + hc_rpl + [4:4] + + + hc_top + hc_top + [5:5] + + + use_fix_top + use_fix_top + [6:6] + + + pause + pause + [7:7] + + + apb_data_width + apb_data_width + [9:8] + + + dflt_rpl + dflt_rpl + [12:10] + + + + dflt_top + dflt_top + [19:16] + + + dflt_top_init + dflt_top_init + [23:20] + + + cnt_width + cnt_width + [28:24] + + + + + + comp_version + Component Version Register + 0xf8 + + + comp_type + Component Type Register + 0xfc + + + + WDT0 + 21 + + + + + + + WDT1 + Watchdog Timer 1 + 0x50410000 + + WDT1 + 22 + + + + + + + OTP + One-Time Programmable Memory Controller + OTP + 0x50420000 + + + + dummy + Dummy register: this peripheral is not implemented yet + 0x00 + + + + + + + + DVP + Digital Video Port + DVP + 0x50430000 + + + + dvp_cfg + Config Register + 0x00 + + + start_int_enable + START_INT_ENABLE + [0:0] + + + finish_int_enable + FINISH_INT_ENABLE + [1:1] + + + ai_output_enable + AI_OUTPUT_ENABLE + [2:2] + + + display_output_enable + DISPLAY_OUTPUT_ENABLE + [3:3] + + + auto_enable + AUTO_ENABLE + [4:4] + + + burst_size_4beats + BURST_SIZE_4BEATS + [8:8] + + + format + FORMAT + [10:9] + + + rgb + RGB_FORMAT + 0 + + + yuv + YUV_FORMAT + 1 + + + y + Y_FORMAT + 3 + + + + + href_burst_num + HREF_BURST_NUM + [19:12] + + + line_num + LINE_NUM + [29:20] + + + + + r_addr + R_ADDR + 0x04 + + + g_addr + G_ADDR + 0x08 + + + b_addr + B_ADDR + 0x0c + + + cmos_cfg + CMOS Config Register + 0x10 + + + clk_div + CLK_DIV + [7:0] + + + clk_enable + CLK_ENABLE + [8:8] + + + reset + RESET + [16:16] + + + power_down + POWER_DOWN + [24:24] + + + + + sccb_cfg + SCCB Config Register + 0x14 + + + byte_num + BYTE_NUM + [1:0] + + + num2 + BYTE_NUM_2 + 1 + + + num3 + BYTE_NUM_3 + 2 + + + num4 + BYTE_NUM_4 + 3 + + + + + scl_lcnt + SCL_LCNT + [15:8] + + + scl_hcnt + SCL_HCNT + [23:16] + + + rdata + RDATA + [31:24] + read-only + + + + + sccb_ctl + SCCB Control Register + 0x18 + + + + device_address + DEVICE_ADDRESS + [7:0] + + + reg_address + REG_ADDRESS + [15:8] + + + wdata_byte0 + WDATA_BYTE0 + [23:16] + + + wdata_byte1 + WDATA_BYTE1 + [31:24] + + + + + axi + AXI Register + 0x1c + + + gm_mlen + GM_MLEN + [7:0] + + + byte1 + GM_MLEN_1BYTE + 0 + + + byte4 + GM_MLEN_4BYTE + 3 + + + + + + + sts + STS Register + 0x20 + + + frame_start + FRAME_START + [0:0] + + + frame_start_we + FRAME_START_WE + [1:1] + + + frame_finish + FRAME_FINISH + [8:8] + + + frame_finish_we + FRAME_FINISH_WE + [9:9] + + + dvp_en + DVP_EN + [16:16] + + + dvp_en_we + DVP_EN_WE + [17:17] + + + sccb_en + SCCB_EN + [24:24] + + + sccb_en_we + SCCB_EN_WE + [25:25] + + + + + reverse + REVERSE + 0x24 + + + rgb_addr + RGB_ADDR + 0x28 + + + + DVP + 24 + + + + + + + SYSCTL + System Controller + SYSCTL + 0x50440000 + + + git_id + Git short commit id + 0x00 + + + clk_freq + System clock base frequency + 0x04 + + + pll0 + PLL0 controller + 0x08 + + + clkr + [3:0] + + + clkf + [9:4] + + + clkod + [13:10] + + + bwadj + [19:14] + + + reset + [20:20] + + + pwrd + [21:21] + + + intfb + [22:22] + + + bypass + [23:23] + + + test + [24:24] + + + out_en + [25:25] + + + test_en + [26:26] + + + + + pll1 + PLL1 controller + 0x0c + + + clkr + [3:0] + + + clkf + [9:4] + + + clkod + [13:10] + + + bwadj + [19:14] + + + reset + [20:20] + + + pwrd + [21:21] + + + intfb + [22:22] + + + bypass + [23:23] + + + test + [24:24] + + + out_en + [25:25] + + + + + pll2 + PLL2 controller + 0x10 + + + clkr + [3:0] + + + clkf + [9:4] + + + clkod + [13:10] + + + bwadj + [19:14] + + + reset + [20:20] + + + pwrd + [21:21] + + + intfb + [22:22] + + + bypass + [23:23] + + + test + [24:24] + + + out_en + [25:25] + + + ckin_sel + [27:26] + + + + + pll_lock + PLL lock tester + 0x18 + + + pll_lock0 + [1:0] + + + pll_slip_clear0 + [2:2] + + + test_clk_out0 + [3:3] + + + pll_lock1 + [9:8] + + + pll_slip_clear1 + [10:10] + + + test_clk_out1 + [11:11] + + + pll_lock2 + [17:16] + + + pll_slip_clear2 + [18:18] + + + test_clk_out2 + [19:19] + + + + + rom_error + AXI ROM detector + 0x1c + + + rom_mul_error + [0:0] + + + rom_one_error + [1:1] + + + + + clk_sel0 + Clock select controller 0 + 0x20 + + + aclk_sel + [0:0] + + + aclk_divider_sel + [2:1] + + + apb0_clk_sel + [5:3] + + + apb1_clk_sel + [8:6] + + + apb2_clk_sel + [11:9] + + + spi3_clk_sel + [12:12] + + + timer0_clk_sel + [13:13] + + + timer1_clk_sel + [14:14] + + + timer2_clk_sel + [15:15] + + + + + clk_sel1 + Clock select controller 1 + 0x24 + + + spi3_sample_clk_sel + [0:0] + + + + + clk_en_cent + Central clock enable + 0x28 + + + cpu_clk_en + [0:0] + + + sram0_clk_en + [1:1] + + + sram1_clk_en + [2:2] + + + apb0_clk_en + [3:3] + + + apb1_clk_en + [4:4] + + + apb2_clk_en + [5:5] + + + + + clk_en_peri + Peripheral clock enable + 0x2c + + + rom_clk_en + [0:0] + + + dma_clk_en + [1:1] + + + ai_clk_en + [2:2] + + + dvp_clk_en + [3:3] + + + fft_clk_en + [4:4] + + + gpio_clk_en + [5:5] + + + spi0_clk_en + [6:6] + + + spi1_clk_en + [7:7] + + + spi2_clk_en + [8:8] + + + spi3_clk_en + [9:9] + + + i2s0_clk_en + [10:10] + + + i2s1_clk_en + [11:11] + + + i2s2_clk_en + [12:12] + + + i2c0_clk_en + [13:13] + + + i2c1_clk_en + [14:14] + + + i2c2_clk_en + [15:15] + + + uart1_clk_en + [16:16] + + + uart2_clk_en + [17:17] + + + uart3_clk_en + [18:18] + + + aes_clk_en + [19:19] + + + fpioa_clk_en + [20:20] + + + timer0_clk_en + [21:21] + + + timer1_clk_en + [22:22] + + + timer2_clk_en + [23:23] + + + wdt0_clk_en + [24:24] + + + wdt1_clk_en + [25:25] + + + sha_clk_en + [26:26] + + + otp_clk_en + [27:27] + + + rtc_clk_en + [29:29] + + + + + soft_reset + Soft reset ctrl + 0x30 + + + soft_reset + [0:0] + + + + + peri_reset + Peripheral reset controller + 0x34 + + + rom_reset + [0:0] + + + dma_reset + [1:1] + + + ai_reset + [2:2] + + + dvp_reset + [3:3] + + + fft_reset + [4:4] + + + gpio_reset + [5:5] + + + spi0_reset + [6:6] + + + spi1_reset + [7:7] + + + spi2_reset + [8:8] + + + spi3_reset + [9:9] + + + i2s0_reset + [10:10] + + + i2s1_reset + [11:11] + + + i2s2_reset + [12:12] + + + i2c0_reset + [13:13] + + + i2c1_reset + [14:14] + + + i2c2_reset + [15:15] + + + uart1_reset + [16:16] + + + uart2_reset + [17:17] + + + uart3_reset + [18:18] + + + aes_reset + [19:19] + + + fpioa_reset + [20:20] + + + timer0_reset + [21:21] + + + timer1_reset + [22:22] + + + timer2_reset + [23:23] + + + wdt0_reset + [24:24] + + + wdt1_reset + [25:25] + + + sha_reset + [26:26] + + + rtc_reset + [29:29] + + + + + clk_th0 + Clock threshold controller 0 + 0x38 + + + sram0_gclk + [3:0] + + + sram1_gclk + [7:4] + + + ai_gclk + [11:8] + + + dvp_gclk + [15:12] + + + rom_gclk + [19:16] + + + + + clk_th1 + Clock threshold controller 1 + 0x3c + + + spi0_clk + [7:0] + + + spi1_clk + [15:8] + + + spi2_clk + [23:16] + + + spi3_clk + [31:24] + + + + + clk_th2 + Clock threshold controller 2 + 0x40 + + + timer0_clk + [7:0] + + + timer1_clk + [15:8] + + + timer2_clk + [23:16] + + + + + clk_th3 + Clock threshold controller 3 + 0x44 + + + i2s0_clk + [15:0] + + + i2s1_clk + [31:16] + + + + + clk_th4 + Clock threshold controller 4 + 0x48 + + + i2s2_clk + [15:0] + + + i2s0_mclk + [23:16] + + + i2s1_mclk + [31:24] + + + + + clk_th5 + Clock threshold controller 5 + 0x4c + + + i2s2_mclk + [7:0] + + + i2c0_clk + [15:8] + + + i2c1_clk + [23:16] + + + i2c2_clk + [31:24] + + + + + clk_th6 + Clock threshold controller 6 + 0x50 + + + wdt0_clk + [7:0] + + + wdt1_clk + [15:8] + + + + + misc + Miscellaneous controller + 0x54 + + + debug_sel + [5:0] + + + spi_dvp_data_enable + [10:10] + + + + + peri + Peripheral controller + 0x58 + + + timer0_pause + [0:0] + + + timer1_pause + [1:1] + + + timer2_pause + [2:2] + + + timer3_pause + [3:3] + + + timer4_pause + [4:4] + + + timer5_pause + [5:5] + + + timer6_pause + [6:6] + + + timer7_pause + [7:7] + + + timer8_pause + [8:8] + + + timer9_pause + [9:9] + + + timer10_pause + [10:10] + + + timer11_pause + [11:11] + + + spi0_xip_en + [12:12] + + + spi1_xip_en + [13:13] + + + spi2_xip_en + [14:14] + + + spi3_xip_en + [15:15] + + + spi0_clk_bypass + [16:16] + + + spi1_clk_bypass + [17:17] + + + spi2_clk_bypass + [18:18] + + + i2s0_clk_bypass + [19:19] + + + i2s1_clk_bypass + [20:20] + + + i2s2_clk_bypass + [21:21] + + + jtag_clk_bypass + [22:22] + + + dvp_clk_bypass + [23:23] + + + debug_clk_bypass + [24:24] + + + + + spi_sleep + SPI sleep controller + 0x5c + + + ssi0_sleep + [0:0] + + + ssi1_sleep + [1:1] + + + ssi2_sleep + [2:2] + + + ssi3_sleep + [3:3] + + + + + reset_status + Reset source status + 0x60 + + + reset_sts_clr + [0:0] + + + pin_reset_sts + [1:1] + + + wdt0_reset_sts + [2:2] + + + wdt1_reset_sts + [3:3] + + + soft_reset_sts + [4:4] + + + + + dma_sel0 + DMA handshake selector + 0x64 + + + dma_sel0 + [5:0] + + DMASELECT + ssi0_rx_req0 + ssi0_tx_req1 + ssi1_rx_req2 + ssi1_tx_req3 + ssi2_rx_req4 + ssi2_tx_req5 + ssi3_rx_req6 + ssi3_tx_req7 + i2c0_rx_req8 + i2c0_tx_req9 + i2c1_rx_req10 + i2c1_tx_req11 + i2c2_rx_req12 + i2c2_tx_req13 + uart1_rx_req14 + uart1_tx_req15 + uart2_rx_req16 + uart2_tx_req17 + uart3_rx_req18 + uart3_tx_req19 + aes_req20 + sha_rx_req21 + ai_rx_req22 + fft_rx_req23 + fft_tx_req24 + i2s0_tx_req25 + i2s0_rx_req26 + i2s1_tx_req27 + i2s1_rx_req28 + i2s2_tx_req29 + i2s2_rx_req30 + i2s0_bf_dir_req31 + i2s0_bf_voice_req32 + + + + dma_sel1 + [11:6] + + + + + dma_sel2 + [17:12] + + + + + dma_sel3 + [23:18] + + + + + dma_sel4 + [29:24] + + + + + + + dma_sel1 + DMA handshake selector + 0x68 + + + dma_sel5 + [5:0] + + + + + + + power_sel + IO Power Mode Select controller + 0x6c + + + power_mode_sel0 + [0:0] + + + power_mode_sel1 + [1:1] + + + power_mode_sel2 + [2:2] + + + power_mode_sel3 + [3:3] + + + power_mode_sel4 + [4:4] + + + power_mode_sel5 + [5:5] + + + power_mode_sel6 + [6:6] + + + power_mode_sel7 + [7:7] + + + + + + + + + + AES + AES Accelerator + AES + 0x50450000 + + + 4 + 0x04 + key[%s] + 1st-4th word of key + 0x00 + + + encrypt_sel + Encryption or decryption select + 0x10 + + + encrypt_sel + Select encryption or decryption mode + [0:0] + + + encryption + Sets encryption mode + 0 + + + decryption + Sets decryption mode + 1 + + + + + + + mode_ctl + AES mode register + 0x14 + + + cipher_mode + Cipher mode + [2:0] + + + ECB + Electronic Codebook + 0 + + + CBC + Cipher Block Chaining + 1 + + + GCM + Galois/Counter Mode + 2 + + + + + key_mode + Key mode + [4:3] + + + AES128 + AES-128 + 0 + + + AES192 + AES-192 + 1 + + + AES256 + AES-256 + 2 + + + + + key_order + Input key order + [5:5] + + ENDIAN + + be + Big Endian + 0 + + + le + Little Endian + 1 + + + + + input_order + Input data order + [7:7] + + + + + output_order + Output data order + [9:9] + + + + + + + 4 + 0x04 + iv[%s] + Initialisation Vector (96 bit for GCM, 128 bit for CBC) + 0x18 + + + endian + Endian control + 0x28 + + + endian + Input data endian + [0:0] + + + + + + + finish + Finished status + 0x2C + + + finish + AES operation finished status + [0:0] + + + not_finished + Operation not finished + 0 + + + finished + Operation finished + 1 + + + + + + + dma_sel + DMA select + 0x30 + + + dma_sel + Output to DMA if set, to CPU otherwise + [0:0] + + + + + aad_num + GCM additional authenticated data count in bytes, minus one + 0x34 + + + pc_num + Plaintext/ciphertext input data count in bytes, minus one + 0x3c + + + text_data + Plaintext/ciphertext input data + 0x40 + + + aad_data + Additional authenticated data + 0x44 + + + tag_chk + Tag check status + 0x48 + + + tag_chk + Tag check status + [1:0] + + + busy + Check not finished + 0 + + + fail + Check failed + 1 + + + success + Check success + 2 + + + + + + + data_in_flag + Data can input flag + 0x4c + + + data_in_flag + Data can be written to text_data or aad_data when this flag is set + [0:0] + + CAN_INPUT + + cannot_input + Cannot input + 0 + + + can_input + Can input + 1 + + + + + + + 4 + 0x04 + gcm_in_tag[%s] + GCM input tag for comparison with the calculated tag + 0x50 + + + out_data + Plaintext/ciphertext output data + 0x60 + + + en + AES module enable + 0x64 + + + en + AES module enable + [0:0] + + + disable + Disable module + 0 + + + enable + Enable module + 1 + + + + + + + data_out_flag + Data can output flag + 0x68 + + + data_out_flag + Data can be read from out_data when this flag is set + [0:0] + + + cannot_output + Data cannot output + 0 + + + can_output + Data can output + 1 + + + + + + + tag_in_flag + Can input tag (when using GCM) + 0x6c + + + tag_in_flag + GCM tag can be written to gcm_in_tag when this flag is set + [0:0] + + + + + + + tag_clear + Tag clear (a write to this register clears the tag_chk status) + 0x70 + + + 4 + 0x04 + gcm_out_tag[%s] + Computed GCM output tag + 0x74 + + + 4 + 0x04 + key_ext[%s] + 5th-8th word of key + 0x84 + + + + + + + + RTC + Real Time Clock + RTC + 0x50460000 + + + date + Timer date information + 0x00 + + + week + Week. Range [0,6]. 0 is Sunday. + [2:0] + 06 + + + day + Day. Range [1,31] or [1,30] or [1,29] or [1,28] + [12:8] + 131 + + + month + Month. Range [1,12] + [19:16] + 112 + + + year + Year. Range [0,99] + [31:20] + 099 + + + + + time + Timer time information + 0x04 + + + second + Second. Range [0,59] + [15:10] + 059 + + + minute + Minute. Range [0,59] + [21:16] + 059 + + + hour + Hour. Range [0,23] + [28:24] + 023 + + + + + alarm_date + Alarm date information + 0x08 + + + week + Week. Range [0,6]. 0 is Sunday. + [2:0] + 06 + + + day + Day. Range [1,31] or [1,30] or [1,29] or [1,28] + [12:8] + 131 + + + month + Month. Range [1,12] + [19:16] + 112 + + + year + Year. Range [0,99] + [31:20] + 099 + + + + + alarm_time + Alarm time information + 0x0c + + + second + Second. Range [0,59] + [15:10] + 059 + + + minute + Minute. Range [0,59] + [21:16] + 059 + + + hour + Hour. Range [0,23] + [28:24] + 023 + + + + + initial_count + Timer counter initial value + 0x10 + + + count + RTC counter initial value + [31:0] + + + + + current_count + Timer counter current value + 0x14 + + + count + RTC counter current value + [31:0] + + + + + interrupt_ctrl + RTC interrupt settings + 0x18 + + + tick_enable + TICK_ENABLE + [0:0] + + + alarm_enable + Alarm interrupt enable + [1:1] + + + tick_int_mode + Tick interrupt enable + [3:2] + + + alarm_compare_mask + Alarm compare mask for interrupt + [31:24] + + + + + register_ctrl + RTC register settings + 0x1c + + + read_enable + RTC timer read enable + [0:0] + + + write_enable + RTC timer write enable + [1:1] + + + timer_mask + RTC timer mask + [20:13] + + + alarm_mask + RTC alarm mask + [28:21] + + + initial_count_mask + RTC counter initial count value mask + [29:29] + + + interrupt_register_mask + RTC interrupt register mask + [30:30] + + + + + extended + Timer extended information + 0x28 + + + century + Century. Range [0,31] + [4:0] + 031 + + + leap_year + Is leap year. 1 is leap year, 0 is not leap year + [5:5] + + + not_leap + 0 is not leap year + 0 + + + leap + 1 is leap year + 1 + + + + + + + + RTC + 20 + + + + + diff --git a/third-party/k210-pac/memory-k210.x b/third-party/k210-pac/memory-k210.x new file mode 100644 index 00000000..2770e46b --- /dev/null +++ b/third-party/k210-pac/memory-k210.x @@ -0,0 +1,9 @@ +_max_hart_id = 1; + +MEMORY +{ + SRAM : ORIGIN = 0x80000000, LENGTH = 6M + AI_SRAM : ORIGIN = 0x80600000, LENGTH = 2M + SRAM_NOCACHE : ORIGIN = 0x40000000, LENGTH = 6M + AI_SRAM_NOCACHE : ORIGIN = 0x40600000, LENGTH = 2M +} diff --git a/third-party/k210-pac/src/lib.rs b/third-party/k210-pac/src/lib.rs new file mode 100644 index 00000000..a2275719 --- /dev/null +++ b/third-party/k210-pac/src/lib.rs @@ -0,0 +1,46130 @@ +#![doc = "Peripheral access API for K210 microcontrollers (generated using svd2rust v0.17.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.17.0/svd2rust/#peripheral-api"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +extern crate bare_metal; +extern crate riscv; +#[cfg(feature = "rt")] +extern crate riscv_rt; +extern crate vcell; +use core::marker::PhantomData; +use core::ops::Deref; +#[doc(hidden)] +pub mod interrupt { + #[doc = r"Enumeration of all the interrupts"] + #[derive(Copy, Clone, Debug)] + #[repr(u8)] + pub enum Interrupt { + #[doc = "1 - SPI0"] + SPI0 = 1, + #[doc = "2 - SPI1"] + SPI1 = 2, + #[doc = "3 - SPI_SLAVE"] + SPI_SLAVE = 3, + #[doc = "4 - SPI3"] + SPI3 = 4, + #[doc = "5 - I2S0"] + I2S0 = 5, + #[doc = "6 - I2S1"] + I2S1 = 6, + #[doc = "7 - I2S2"] + I2S2 = 7, + #[doc = "8 - I2C0"] + I2C0 = 8, + #[doc = "9 - I2C1"] + I2C1 = 9, + #[doc = "10 - I2C2"] + I2C2 = 10, + #[doc = "11 - UART1"] + UART1 = 11, + #[doc = "12 - UART2"] + UART2 = 12, + #[doc = "13 - UART3"] + UART3 = 13, + #[doc = "14 - TIMER0 channel 0 or 1 interrupt"] + TIMER0A = 14, + #[doc = "15 - TIMER0 channel 2 or 3 interrupt"] + TIMER0B = 15, + #[doc = "16 - TIMER1 channel 0 or 1 interrupt"] + TIMER1A = 16, + #[doc = "17 - TIMER1 channel 2 or 3 interrupt"] + TIMER1B = 17, + #[doc = "18 - TIMER2 channel 0 or 1 interrupt"] + TIMER2A = 18, + #[doc = "19 - TIMER2 channel 2 or 3 interrupt"] + TIMER2B = 19, + #[doc = "20 - RTC"] + RTC = 20, + #[doc = "21 - WDT0"] + WDT0 = 21, + #[doc = "22 - WDT1"] + WDT1 = 22, + #[doc = "23 - APB_GPIO"] + APB_GPIO = 23, + #[doc = "24 - DVP"] + DVP = 24, + #[doc = "25 - KPU"] + KPU = 25, + #[doc = "26 - FFT"] + FFT = 26, + #[doc = "27 - DMA0"] + DMA0 = 27, + #[doc = "28 - DMA1"] + DMA1 = 28, + #[doc = "29 - DMA2"] + DMA2 = 29, + #[doc = "30 - DMA3"] + DMA3 = 30, + #[doc = "31 - DMA4"] + DMA4 = 31, + #[doc = "32 - DMA5"] + DMA5 = 32, + #[doc = "33 - UARTHS"] + UARTHS = 33, + #[doc = "34 - GPIOHS0"] + GPIOHS0 = 34, + #[doc = "35 - GPIOHS1"] + GPIOHS1 = 35, + #[doc = "36 - GPIOHS2"] + GPIOHS2 = 36, + #[doc = "37 - GPIOHS3"] + GPIOHS3 = 37, + #[doc = "38 - GPIOHS4"] + GPIOHS4 = 38, + #[doc = "39 - GPIOHS5"] + GPIOHS5 = 39, + #[doc = "40 - GPIOHS6"] + GPIOHS6 = 40, + #[doc = "41 - GPIOHS7"] + GPIOHS7 = 41, + #[doc = "42 - GPIOHS8"] + GPIOHS8 = 42, + #[doc = "43 - GPIOHS9"] + GPIOHS9 = 43, + #[doc = "44 - GPIOHS10"] + GPIOHS10 = 44, + #[doc = "45 - GPIOHS11"] + GPIOHS11 = 45, + #[doc = "46 - GPIOHS12"] + GPIOHS12 = 46, + #[doc = "47 - GPIOHS13"] + GPIOHS13 = 47, + #[doc = "48 - GPIOHS14"] + GPIOHS14 = 48, + #[doc = "49 - GPIOHS15"] + GPIOHS15 = 49, + #[doc = "50 - GPIOHS16"] + GPIOHS16 = 50, + #[doc = "51 - GPIOHS17"] + GPIOHS17 = 51, + #[doc = "52 - GPIOHS18"] + GPIOHS18 = 52, + #[doc = "53 - GPIOHS19"] + GPIOHS19 = 53, + #[doc = "54 - GPIOHS20"] + GPIOHS20 = 54, + #[doc = "55 - GPIOHS21"] + GPIOHS21 = 55, + #[doc = "56 - GPIOHS22"] + GPIOHS22 = 56, + #[doc = "57 - GPIOHS23"] + GPIOHS23 = 57, + #[doc = "58 - GPIOHS24"] + GPIOHS24 = 58, + #[doc = "59 - GPIOHS25"] + GPIOHS25 = 59, + #[doc = "60 - GPIOHS26"] + GPIOHS26 = 60, + #[doc = "61 - GPIOHS27"] + GPIOHS27 = 61, + #[doc = "62 - GPIOHS28"] + GPIOHS28 = 62, + #[doc = "63 - GPIOHS29"] + GPIOHS29 = 63, + #[doc = "64 - GPIOHS30"] + GPIOHS30 = 64, + #[doc = "65 - GPIOHS31"] + GPIOHS31 = 65, + } + unsafe impl bare_metal::Nr for Interrupt { + #[inline(always)] + fn nr(&self) -> u8 { + *self as u8 + } + } + #[derive(Debug, Copy, Clone)] + pub struct TryFromInterruptError(()); + impl Interrupt { + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 1 => Ok(Interrupt::SPI0), + 2 => Ok(Interrupt::SPI1), + 3 => Ok(Interrupt::SPI_SLAVE), + 4 => Ok(Interrupt::SPI3), + 5 => Ok(Interrupt::I2S0), + 6 => Ok(Interrupt::I2S1), + 7 => Ok(Interrupt::I2S2), + 8 => Ok(Interrupt::I2C0), + 9 => Ok(Interrupt::I2C1), + 10 => Ok(Interrupt::I2C2), + 11 => Ok(Interrupt::UART1), + 12 => Ok(Interrupt::UART2), + 13 => Ok(Interrupt::UART3), + 14 => Ok(Interrupt::TIMER0A), + 15 => Ok(Interrupt::TIMER0B), + 16 => Ok(Interrupt::TIMER1A), + 17 => Ok(Interrupt::TIMER1B), + 18 => Ok(Interrupt::TIMER2A), + 19 => Ok(Interrupt::TIMER2B), + 20 => Ok(Interrupt::RTC), + 21 => Ok(Interrupt::WDT0), + 22 => Ok(Interrupt::WDT1), + 23 => Ok(Interrupt::APB_GPIO), + 24 => Ok(Interrupt::DVP), + 25 => Ok(Interrupt::KPU), + 26 => Ok(Interrupt::FFT), + 27 => Ok(Interrupt::DMA0), + 28 => Ok(Interrupt::DMA1), + 29 => Ok(Interrupt::DMA2), + 30 => Ok(Interrupt::DMA3), + 31 => Ok(Interrupt::DMA4), + 32 => Ok(Interrupt::DMA5), + 33 => Ok(Interrupt::UARTHS), + 34 => Ok(Interrupt::GPIOHS0), + 35 => Ok(Interrupt::GPIOHS1), + 36 => Ok(Interrupt::GPIOHS2), + 37 => Ok(Interrupt::GPIOHS3), + 38 => Ok(Interrupt::GPIOHS4), + 39 => Ok(Interrupt::GPIOHS5), + 40 => Ok(Interrupt::GPIOHS6), + 41 => Ok(Interrupt::GPIOHS7), + 42 => Ok(Interrupt::GPIOHS8), + 43 => Ok(Interrupt::GPIOHS9), + 44 => Ok(Interrupt::GPIOHS10), + 45 => Ok(Interrupt::GPIOHS11), + 46 => Ok(Interrupt::GPIOHS12), + 47 => Ok(Interrupt::GPIOHS13), + 48 => Ok(Interrupt::GPIOHS14), + 49 => Ok(Interrupt::GPIOHS15), + 50 => Ok(Interrupt::GPIOHS16), + 51 => Ok(Interrupt::GPIOHS17), + 52 => Ok(Interrupt::GPIOHS18), + 53 => Ok(Interrupt::GPIOHS19), + 54 => Ok(Interrupt::GPIOHS20), + 55 => Ok(Interrupt::GPIOHS21), + 56 => Ok(Interrupt::GPIOHS22), + 57 => Ok(Interrupt::GPIOHS23), + 58 => Ok(Interrupt::GPIOHS24), + 59 => Ok(Interrupt::GPIOHS25), + 60 => Ok(Interrupt::GPIOHS26), + 61 => Ok(Interrupt::GPIOHS27), + 62 => Ok(Interrupt::GPIOHS28), + 63 => Ok(Interrupt::GPIOHS29), + 64 => Ok(Interrupt::GPIOHS30), + 65 => Ok(Interrupt::GPIOHS31), + _ => Err(TryFromInterruptError(())), + } + } + } + #[cfg(feature = "rt")] + #[macro_export] + #[doc = r" Assigns a handler to an interrupt"] + #[doc = r""] + #[doc = r" This macro takes two arguments: the name of an interrupt and the path to the"] + #[doc = r" function that will be used as the handler of that interrupt. That function"] + #[doc = r" must have signature `fn()`."] + #[doc = r""] + #[doc = r" Optionally, a third argument may be used to declare interrupt local data."] + #[doc = r" The handler will have exclusive access to these *local* variables on each"] + #[doc = r" invocation. If the third argument is used then the signature of the handler"] + #[doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"] + #[doc = r" passed to the macro."] + #[doc = r""] + #[doc = r" # Example"] + #[doc = r""] + #[doc = r" ``` ignore"] + #[doc = r" interrupt!(TIM2, periodic);"] + #[doc = r""] + #[doc = r" fn periodic() {"] + #[doc = r#" print!(".");"#] + #[doc = r" }"] + #[doc = r""] + #[doc = r" interrupt!(TIM3, tick, locals: {"] + #[doc = r" tick: bool = false;"] + #[doc = r" });"] + #[doc = r""] + #[doc = r" fn tick(locals: &mut TIM3::Locals) {"] + #[doc = r" locals.tick = !locals.tick;"] + #[doc = r""] + #[doc = r" if locals.tick {"] + #[doc = r#" println!("Tick");"#] + #[doc = r" } else {"] + #[doc = r#" println!("Tock");"#] + #[doc = r" }"] + #[doc = r" }"] + #[doc = r" ```"] + macro_rules ! interrupt { ( $ NAME : ident , $ path : path , locals : { $ ( $ lvar : ident : $ lty : ty = $ lval : expr ; ) * } ) => { # [ allow ( non_snake_case ) ] +mod $ NAME { pub struct Locals { $ ( pub $ lvar : $ lty , ) * } } # [ allow ( non_snake_case ) ] +# [ no_mangle ] +pub extern "C" fn $ NAME ( ) { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ( $ lvar : $ lval , ) * } ; let f : fn ( & mut self :: $ NAME :: Locals ) = $ path ; f ( unsafe { & mut LOCALS } ) ; } } ; ( $ NAME : ident , $ path : path ) => { # [ allow ( non_snake_case ) ] +# [ no_mangle ] +pub extern "C" fn $ NAME ( ) { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn ( ) = $ path ; f ( ) ; } } } +} +pub use self::interrupt::Interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic { + use core::marker; + #[doc = " Trait implemented by readable registers to enable the `read` method."] + #[doc = ""] + #[doc = " Registers marked with `Writable` can be also `modify`'ed."] + pub trait Readable {} + #[doc = " Trait implemented by writeable registers."] + #[doc = ""] + #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] + #[doc = ""] + #[doc = " Registers marked with `Readable` can be also `modify`'ed."] + pub trait Writable {} + #[doc = " Reset value of the register."] + #[doc = ""] + #[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] + #[doc = " register by using the `reset` method."] + pub trait ResetValue { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Type; + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Type; + } + #[doc = " This structure provides volatile access to registers."] + pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, + } + unsafe impl Send for Reg {} + impl Reg + where + Self: Readable, + U: Copy, + { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } + } + impl Reg + where + Self: ResetValue + Writable, + U: Copy, + { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(Self::reset_value()) + } + } + impl Reg + where + Self: ResetValue + Writable, + U: Copy, + { + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: Self::reset_value(), + _reg: marker::PhantomData, + }) + .bits, + ); + } + } + impl Reg + where + Self: Writable, + U: Copy + Default, + { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: U::default(), + _reg: marker::PhantomData, + }) + .bits, + ); + } + } + impl Reg + where + Self: Readable + Writable, + U: Copy, + { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits, + _reg: marker::PhantomData, + }, + ) + .bits, + ); + } + } + #[doc = " Register/field reader."] + #[doc = ""] + #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] + #[doc = " method."] + pub struct R { + pub(crate) bits: U, + _reg: marker::PhantomData, + } + impl R + where + U: Copy, + { + #[doc = " Creates a new instance of the reader."] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from register/field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } + } + impl PartialEq for R + where + U: PartialEq, + FI: Copy + Into, + { + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } + } + impl R { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } + } + #[doc = " Register writer."] + #[doc = ""] + #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] + pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: U, + _reg: marker::PhantomData, + } + impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: U) -> &mut Self { + self.bits = bits; + self + } + } + #[doc = " Used if enumerated values cover not the whole range."] + #[derive(Clone, Copy, PartialEq)] + pub enum Variant { + #[doc = " Expected variant."] + Val(T), + #[doc = " Raw bits."] + Res(U), + } +} +#[doc = "Core Local Interruptor"] +pub struct CLINT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLINT {} +impl CLINT { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clint::RegisterBlock { + 0x0200_0000 as *const _ + } +} +impl Deref for CLINT { + type Target = clint::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*CLINT::ptr() } + } +} +#[doc = "Core Local Interruptor"] +pub mod clint { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Hart software interrupt register"] + pub msip: [MSIP; 2], + _reserved1: [u8; 16376usize], + #[doc = "0x4000 - Hart time comparator register"] + pub mtimecmp: [MTIMECMP; 2], + _reserved2: [u8; 32744usize], + #[doc = "0xbff8 - Timer register"] + pub mtime: MTIME, + } + #[doc = "Hart software interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msip](msip) module"] + pub type MSIP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSIP; + #[doc = "`read()` method returns [msip::R](msip::R) reader structure"] + impl crate::Readable for MSIP {} + #[doc = "`write(|w| ..)` method takes [msip::W](msip::W) writer structure"] + impl crate::Writable for MSIP {} + #[doc = "Hart software interrupt register"] + pub mod msip { + #[doc = "Reader of register msip[%s]"] + pub type R = crate::R; + #[doc = "Writer for register msip[%s]"] + pub type W = crate::W; + #[doc = "Register msip[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::MSIP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Hart time comparator register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mtimecmp](mtimecmp) module"] + pub type MTIMECMP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MTIMECMP; + #[doc = "`read()` method returns [mtimecmp::R](mtimecmp::R) reader structure"] + impl crate::Readable for MTIMECMP {} + #[doc = "`write(|w| ..)` method takes [mtimecmp::W](mtimecmp::W) writer structure"] + impl crate::Writable for MTIMECMP {} + #[doc = "Hart time comparator register"] + pub mod mtimecmp { + #[doc = "Reader of register mtimecmp[%s]"] + pub type R = crate::R; + #[doc = "Writer for register mtimecmp[%s]"] + pub type W = crate::W; + #[doc = "Register mtimecmp[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::MTIMECMP { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Timer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mtime](mtime) module"] + pub type MTIME = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MTIME; + #[doc = "`read()` method returns [mtime::R](mtime::R) reader structure"] + impl crate::Readable for MTIME {} + #[doc = "`write(|w| ..)` method takes [mtime::W](mtime::W) writer structure"] + impl crate::Writable for MTIME {} + #[doc = "Timer register"] + pub mod mtime { + #[doc = "Reader of register mtime"] + pub type R = crate::R; + #[doc = "Writer for register mtime"] + pub type W = crate::W; + #[doc = "Register mtime `reset()`'s with value 0"] + impl crate::ResetValue for super::MTIME { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Platform-Level Interrupt Controller"] +pub struct PLIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLIC {} +impl PLIC { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const plic::RegisterBlock { + 0x0c00_0000 as *const _ + } +} +impl Deref for PLIC { + type Target = plic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*PLIC::ptr() } + } +} +#[doc = "Platform-Level Interrupt Controller"] +pub mod plic { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Source Priority Register"] + pub priority: [PRIORITY; 1024], + #[doc = "0x1000 - Interrupt Pending Register"] + pub pending: [PENDING; 32], + _reserved2: [u8; 3968usize], + #[doc = "0x2000 - Target Interrupt Enables"] + pub target_enables: [TARGET_ENABLES; 4], + _reserved3: [u8; 2088448usize], + #[doc = "0x200000 - Target Configuration"] + pub targets: [TARGETS; 4], + } + #[doc = r"Register block"] + #[repr(C)] + pub struct TARGET_ENABLES { + #[doc = "0x00 - Interrupt Enable Register"] + pub enable: [self::target_enables::ENABLE; 32], + } + #[doc = r"Register block"] + #[doc = "Target Interrupt Enables"] + pub mod target_enables { + #[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](enable) module"] + pub type ENABLE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENABLE; + #[doc = "`read()` method returns [enable::R](enable::R) reader structure"] + impl crate::Readable for ENABLE {} + #[doc = "`write(|w| ..)` method takes [enable::W](enable::W) writer structure"] + impl crate::Writable for ENABLE {} + #[doc = "Interrupt Enable Register"] + pub mod enable { + #[doc = "Reader of register enable[%s]"] + pub type R = crate::R; + #[doc = "Writer for register enable[%s]"] + pub type W = crate::W; + #[doc = "Register enable[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::ENABLE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = r"Register block"] + #[repr(C)] + pub struct TARGETS { + #[doc = "0x00 - Priority Threshold Register"] + pub threshold: self::targets::THRESHOLD, + #[doc = "0x04 - Claim/Complete Register"] + pub claim: self::targets::CLAIM, + _reserved2: [u8; 4084usize], + #[doc = "0xffc - Padding to make sure targets is an array"] + pub _reserved: self::targets::_RESERVED, + } + #[doc = r"Register block"] + #[doc = "Target Configuration"] + pub mod targets { + #[doc = "Priority Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [threshold](threshold) module"] + pub type THRESHOLD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _THRESHOLD; + #[doc = "`read()` method returns [threshold::R](threshold::R) reader structure"] + impl crate::Readable for THRESHOLD {} + #[doc = "`write(|w| ..)` method takes [threshold::W](threshold::W) writer structure"] + impl crate::Writable for THRESHOLD {} + #[doc = "Priority Threshold Register"] + pub mod threshold { + #[doc = "Reader of register threshold"] + pub type R = crate::R; + #[doc = "Writer for register threshold"] + pub type W = crate::W; + #[doc = "Register threshold `reset()`'s with value 0"] + impl crate::ResetValue for super::THRESHOLD { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum PRIORITY_A { + #[doc = "0: Never interrupt"] + NEVER = 0, + #[doc = "1: Priority 1"] + P1 = 1, + #[doc = "2: Priority 2"] + P2 = 2, + #[doc = "3: Priority 3"] + P3 = 3, + #[doc = "4: Priority 4"] + P4 = 4, + #[doc = "5: Priority 5"] + P5 = 5, + #[doc = "6: Priority 6"] + P6 = 6, + #[doc = "7: Priority 7"] + P7 = 7, + } + impl From for u8 { + #[inline(always)] + fn from(variant: PRIORITY_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `priority`"] + pub type PRIORITY_R = crate::R; + impl PRIORITY_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRIORITY_A { + match self.bits { + 0 => PRIORITY_A::NEVER, + 1 => PRIORITY_A::P1, + 2 => PRIORITY_A::P2, + 3 => PRIORITY_A::P3, + 4 => PRIORITY_A::P4, + 5 => PRIORITY_A::P5, + 6 => PRIORITY_A::P6, + 7 => PRIORITY_A::P7, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NEVER`"] + #[inline(always)] + pub fn is_never(&self) -> bool { + *self == PRIORITY_A::NEVER + } + #[doc = "Checks if the value of the field is `P1`"] + #[inline(always)] + pub fn is_p1(&self) -> bool { + *self == PRIORITY_A::P1 + } + #[doc = "Checks if the value of the field is `P2`"] + #[inline(always)] + pub fn is_p2(&self) -> bool { + *self == PRIORITY_A::P2 + } + #[doc = "Checks if the value of the field is `P3`"] + #[inline(always)] + pub fn is_p3(&self) -> bool { + *self == PRIORITY_A::P3 + } + #[doc = "Checks if the value of the field is `P4`"] + #[inline(always)] + pub fn is_p4(&self) -> bool { + *self == PRIORITY_A::P4 + } + #[doc = "Checks if the value of the field is `P5`"] + #[inline(always)] + pub fn is_p5(&self) -> bool { + *self == PRIORITY_A::P5 + } + #[doc = "Checks if the value of the field is `P6`"] + #[inline(always)] + pub fn is_p6(&self) -> bool { + *self == PRIORITY_A::P6 + } + #[doc = "Checks if the value of the field is `P7`"] + #[inline(always)] + pub fn is_p7(&self) -> bool { + *self == PRIORITY_A::P7 + } + } + #[doc = "Write proxy for field `priority`"] + pub struct PRIORITY_W<'a> { + w: &'a mut W, + } + impl<'a> PRIORITY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRIORITY_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Never interrupt"] + #[inline(always)] + pub fn never(self) -> &'a mut W { + self.variant(PRIORITY_A::NEVER) + } + #[doc = "Priority 1"] + #[inline(always)] + pub fn p1(self) -> &'a mut W { + self.variant(PRIORITY_A::P1) + } + #[doc = "Priority 2"] + #[inline(always)] + pub fn p2(self) -> &'a mut W { + self.variant(PRIORITY_A::P2) + } + #[doc = "Priority 3"] + #[inline(always)] + pub fn p3(self) -> &'a mut W { + self.variant(PRIORITY_A::P3) + } + #[doc = "Priority 4"] + #[inline(always)] + pub fn p4(self) -> &'a mut W { + self.variant(PRIORITY_A::P4) + } + #[doc = "Priority 5"] + #[inline(always)] + pub fn p5(self) -> &'a mut W { + self.variant(PRIORITY_A::P5) + } + #[doc = "Priority 6"] + #[inline(always)] + pub fn p6(self) -> &'a mut W { + self.variant(PRIORITY_A::P6) + } + #[doc = "Priority 7"] + #[inline(always)] + pub fn p7(self) -> &'a mut W { + self.variant(PRIORITY_A::P7) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn priority(&self) -> PRIORITY_R { + PRIORITY_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn priority(&mut self) -> PRIORITY_W { + PRIORITY_W { w: self } + } + } + } + #[doc = "Claim/Complete Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claim](claim) module"] + pub type CLAIM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLAIM; + #[doc = "`read()` method returns [claim::R](claim::R) reader structure"] + impl crate::Readable for CLAIM {} + #[doc = "`write(|w| ..)` method takes [claim::W](claim::W) writer structure"] + impl crate::Writable for CLAIM {} + #[doc = "Claim/Complete Register"] + pub mod claim { + #[doc = "Reader of register claim"] + pub type R = crate::R; + #[doc = "Writer for register claim"] + pub type W = crate::W; + #[doc = "Register claim `reset()`'s with value 0"] + impl crate::ResetValue for super::CLAIM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Padding to make sure targets is an array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_reserved](_reserved) module"] + pub type _RESERVED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct __RESERVED; + #[doc = "`read()` method returns [_reserved::R](_reserved::R) reader structure"] + impl crate::Readable for _RESERVED {} + #[doc = "`write(|w| ..)` method takes [_reserved::W](_reserved::W) writer structure"] + impl crate::Writable for _RESERVED {} + #[doc = "Padding to make sure targets is an array"] + pub mod _reserved { + #[doc = "Reader of register _reserved"] + pub type R = crate::R; + #[doc = "Writer for register _reserved"] + pub type W = crate::W; + #[doc = "Register _reserved `reset()`'s with value 0"] + impl crate::ResetValue for super::_RESERVED { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "Interrupt Source Priority Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [priority](priority) module"] + pub type PRIORITY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PRIORITY; + #[doc = "`read()` method returns [priority::R](priority::R) reader structure"] + impl crate::Readable for PRIORITY {} + #[doc = "`write(|w| ..)` method takes [priority::W](priority::W) writer structure"] + impl crate::Writable for PRIORITY {} + #[doc = "Interrupt Source Priority Register"] + pub mod priority { + #[doc = "Reader of register priority[%s]"] + pub type R = crate::R; + #[doc = "Writer for register priority[%s]"] + pub type W = crate::W; + #[doc = "Register priority[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PRIORITY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending](pending) module"] + pub type PENDING = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PENDING; + #[doc = "`read()` method returns [pending::R](pending::R) reader structure"] + impl crate::Readable for PENDING {} + #[doc = "`write(|w| ..)` method takes [pending::W](pending::W) writer structure"] + impl crate::Writable for PENDING {} + #[doc = "Interrupt Pending Register"] + pub mod pending { + #[doc = "Reader of register pending[%s]"] + pub type R = crate::R; + #[doc = "Writer for register pending[%s]"] + pub type W = crate::W; + #[doc = "Register pending[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PENDING { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "High-speed UART"] +pub struct UARTHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UARTHS {} +impl UARTHS { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uarths::RegisterBlock { + 0x3800_0000 as *const _ + } +} +impl Deref for UARTHS { + type Target = uarths::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UARTHS::ptr() } + } +} +#[doc = "High-speed UART"] +pub mod uarths { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Transmit Data Register"] + pub txdata: TXDATA, + #[doc = "0x04 - Receive Data Register"] + pub rxdata: RXDATA, + #[doc = "0x08 - Transmit Control Register"] + pub txctrl: TXCTRL, + #[doc = "0x0c - Receive Control Register"] + pub rxctrl: RXCTRL, + #[doc = "0x10 - Interrupt Enable Register"] + pub ie: IE, + #[doc = "0x14 - Interrupt Pending Register"] + pub ip: IP, + #[doc = "0x18 - Baud Rate Divisor Register"] + pub div: DIV, + } + #[doc = "Transmit Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdata](txdata) module"] + pub type TXDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXDATA; + #[doc = "`read()` method returns [txdata::R](txdata::R) reader structure"] + impl crate::Readable for TXDATA {} + #[doc = "`write(|w| ..)` method takes [txdata::W](txdata::W) writer structure"] + impl crate::Writable for TXDATA {} + #[doc = "Transmit Data Register"] + pub mod txdata { + #[doc = "Reader of register txdata"] + pub type R = crate::R; + #[doc = "Writer for register txdata"] + pub type W = crate::W; + #[doc = "Register txdata `reset()`'s with value 0"] + impl crate::ResetValue for super::TXDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data`"] + pub type DATA_R = crate::R; + #[doc = "Write proxy for field `data`"] + pub struct DATA_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `full`"] + pub type FULL_R = crate::R; + #[doc = "Write proxy for field `full`"] + pub struct FULL_W<'a> { + w: &'a mut W, + } + impl<'a> FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - Transmit data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Transmit FIFO full"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - Transmit data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Bit 31 - Transmit FIFO full"] + #[inline(always)] + pub fn full(&mut self) -> FULL_W { + FULL_W { w: self } + } + } + } + #[doc = "Receive Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdata](rxdata) module"] + pub type RXDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXDATA; + #[doc = "`read()` method returns [rxdata::R](rxdata::R) reader structure"] + impl crate::Readable for RXDATA {} + #[doc = "`write(|w| ..)` method takes [rxdata::W](rxdata::W) writer structure"] + impl crate::Writable for RXDATA {} + #[doc = "Receive Data Register"] + pub mod rxdata { + #[doc = "Reader of register rxdata"] + pub type R = crate::R; + #[doc = "Writer for register rxdata"] + pub type W = crate::W; + #[doc = "Register rxdata `reset()`'s with value 0"] + impl crate::ResetValue for super::RXDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data`"] + pub type DATA_R = crate::R; + #[doc = "Write proxy for field `data`"] + pub struct DATA_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `empty`"] + pub type EMPTY_R = crate::R; + #[doc = "Write proxy for field `empty`"] + pub struct EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - Received data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Receive FIFO empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - Received data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Bit 31 - Receive FIFO empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + } + } + #[doc = "Transmit Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txctrl](txctrl) module"] + pub type TXCTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXCTRL; + #[doc = "`read()` method returns [txctrl::R](txctrl::R) reader structure"] + impl crate::Readable for TXCTRL {} + #[doc = "`write(|w| ..)` method takes [txctrl::W](txctrl::W) writer structure"] + impl crate::Writable for TXCTRL {} + #[doc = "Transmit Control Register"] + pub mod txctrl { + #[doc = "Reader of register txctrl"] + pub type R = crate::R; + #[doc = "Writer for register txctrl"] + pub type W = crate::W; + #[doc = "Register txctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::TXCTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txen`"] + pub type TXEN_R = crate::R; + #[doc = "Write proxy for field `txen`"] + pub struct TXEN_W<'a> { + w: &'a mut W, + } + impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `nstop`"] + pub type NSTOP_R = crate::R; + #[doc = "Write proxy for field `nstop`"] + pub struct NSTOP_W<'a> { + w: &'a mut W, + } + impl<'a> NSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `txcnt`"] + pub type TXCNT_R = crate::R; + #[doc = "Write proxy for field `txcnt`"] + pub struct TXCNT_W<'a> { + w: &'a mut W, + } + impl<'a> TXCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Number of stop bits"] + #[inline(always)] + pub fn nstop(&self) -> NSTOP_R { + NSTOP_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Transmit watermark level"] + #[inline(always)] + pub fn txcnt(&self) -> TXCNT_R { + TXCNT_R::new(((self.bits >> 16) & 0x07) as u8) + } + } + impl W { + #[doc = "Bit 0 - Transmit enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 1 - Number of stop bits"] + #[inline(always)] + pub fn nstop(&mut self) -> NSTOP_W { + NSTOP_W { w: self } + } + #[doc = "Bits 16:18 - Transmit watermark level"] + #[inline(always)] + pub fn txcnt(&mut self) -> TXCNT_W { + TXCNT_W { w: self } + } + } + } + #[doc = "Receive Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxctrl](rxctrl) module"] + pub type RXCTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXCTRL; + #[doc = "`read()` method returns [rxctrl::R](rxctrl::R) reader structure"] + impl crate::Readable for RXCTRL {} + #[doc = "`write(|w| ..)` method takes [rxctrl::W](rxctrl::W) writer structure"] + impl crate::Writable for RXCTRL {} + #[doc = "Receive Control Register"] + pub mod rxctrl { + #[doc = "Reader of register rxctrl"] + pub type R = crate::R; + #[doc = "Writer for register rxctrl"] + pub type W = crate::W; + #[doc = "Register rxctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::RXCTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxen`"] + pub type RXEN_R = crate::R; + #[doc = "Write proxy for field `rxen`"] + pub struct RXEN_W<'a> { + w: &'a mut W, + } + impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxcnt`"] + pub type RXCNT_R = crate::R; + #[doc = "Write proxy for field `rxcnt`"] + pub struct RXCNT_W<'a> { + w: &'a mut W, + } + impl<'a> RXCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receive enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 16:18 - Receive watermark level"] + #[inline(always)] + pub fn rxcnt(&self) -> RXCNT_R { + RXCNT_R::new(((self.bits >> 16) & 0x07) as u8) + } + } + impl W { + #[doc = "Bit 0 - Receive enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 16:18 - Receive watermark level"] + #[inline(always)] + pub fn rxcnt(&mut self) -> RXCNT_W { + RXCNT_W { w: self } + } + } + } + #[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](ie) module"] + pub type IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IE; + #[doc = "`read()` method returns [ie::R](ie::R) reader structure"] + impl crate::Readable for IE {} + #[doc = "`write(|w| ..)` method takes [ie::W](ie::W) writer structure"] + impl crate::Writable for IE {} + #[doc = "Interrupt Enable Register"] + pub mod ie { + #[doc = "Reader of register ie"] + pub type R = crate::R; + #[doc = "Writer for register ie"] + pub type W = crate::W; + #[doc = "Register ie `reset()`'s with value 0"] + impl crate::ResetValue for super::IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txwm`"] + pub type TXWM_R = crate::R; + #[doc = "Write proxy for field `txwm`"] + pub struct TXWM_W<'a> { + w: &'a mut W, + } + impl<'a> TXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxwm`"] + pub type RXWM_R = crate::R; + #[doc = "Write proxy for field `rxwm`"] + pub struct RXWM_W<'a> { + w: &'a mut W, + } + impl<'a> RXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit watermark interrupt enable"] + #[inline(always)] + pub fn txwm(&self) -> TXWM_R { + TXWM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive watermark interrupt enable"] + #[inline(always)] + pub fn rxwm(&self) -> RXWM_R { + RXWM_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit watermark interrupt enable"] + #[inline(always)] + pub fn txwm(&mut self) -> TXWM_W { + TXWM_W { w: self } + } + #[doc = "Bit 1 - Receive watermark interrupt enable"] + #[inline(always)] + pub fn rxwm(&mut self) -> RXWM_W { + RXWM_W { w: self } + } + } + } + #[doc = "Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ip](ip) module"] + pub type IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IP; + #[doc = "`read()` method returns [ip::R](ip::R) reader structure"] + impl crate::Readable for IP {} + #[doc = "`write(|w| ..)` method takes [ip::W](ip::W) writer structure"] + impl crate::Writable for IP {} + #[doc = "Interrupt Pending Register"] + pub mod ip { + #[doc = "Reader of register ip"] + pub type R = crate::R; + #[doc = "Writer for register ip"] + pub type W = crate::W; + #[doc = "Register ip `reset()`'s with value 0"] + impl crate::ResetValue for super::IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txwm`"] + pub type TXWM_R = crate::R; + #[doc = "Write proxy for field `txwm`"] + pub struct TXWM_W<'a> { + w: &'a mut W, + } + impl<'a> TXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxwm`"] + pub type RXWM_R = crate::R; + #[doc = "Write proxy for field `rxwm`"] + pub struct RXWM_W<'a> { + w: &'a mut W, + } + impl<'a> RXWM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit watermark interrupt pending"] + #[inline(always)] + pub fn txwm(&self) -> TXWM_R { + TXWM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive watermark interrupt pending"] + #[inline(always)] + pub fn rxwm(&self) -> RXWM_R { + RXWM_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit watermark interrupt pending"] + #[inline(always)] + pub fn txwm(&mut self) -> TXWM_W { + TXWM_W { w: self } + } + #[doc = "Bit 1 - Receive watermark interrupt pending"] + #[inline(always)] + pub fn rxwm(&mut self) -> RXWM_W { + RXWM_W { w: self } + } + } + } + #[doc = "Baud Rate Divisor Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](div) module"] + pub type DIV = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DIV; + #[doc = "`read()` method returns [div::R](div::R) reader structure"] + impl crate::Readable for DIV {} + #[doc = "`write(|w| ..)` method takes [div::W](div::W) writer structure"] + impl crate::Writable for DIV {} + #[doc = "Baud Rate Divisor Register"] + pub mod div { + #[doc = "Reader of register div"] + pub type R = crate::R; + #[doc = "Writer for register div"] + pub type W = crate::W; + #[doc = "Register div `reset()`'s with value 0"] + impl crate::ResetValue for super::DIV { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `div`"] + pub type DIV_R = crate::R; + #[doc = "Write proxy for field `div`"] + pub struct DIV_W<'a> { + w: &'a mut W, + } + impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Baud rate divisor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Baud rate divisor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + } + } +} +#[doc = "High-speed GPIO"] +pub struct GPIOHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIOHS {} +impl GPIOHS { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpiohs::RegisterBlock { + 0x3800_1000 as *const _ + } +} +impl Deref for GPIOHS { + type Target = gpiohs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*GPIOHS::ptr() } + } +} +#[doc = "High-speed GPIO"] +pub mod gpiohs { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Input Value Register"] + pub input_val: INPUT_VAL, + #[doc = "0x04 - Pin Input Enable Register"] + pub input_en: INPUT_EN, + #[doc = "0x08 - Pin Output Enable Register"] + pub output_en: OUTPUT_EN, + #[doc = "0x0c - Output Value Register"] + pub output_val: OUTPUT_VAL, + #[doc = "0x10 - Internal Pull-Up Enable Register"] + pub pullup_en: PULLUP_EN, + #[doc = "0x14 - Drive Strength Register"] + pub drive: DRIVE, + #[doc = "0x18 - Rise Interrupt Enable Register"] + pub rise_ie: RISE_IE, + #[doc = "0x1c - Rise Interrupt Pending Register"] + pub rise_ip: RISE_IP, + #[doc = "0x20 - Fall Interrupt Enable Register"] + pub fall_ie: FALL_IE, + #[doc = "0x24 - Fall Interrupt Pending Register"] + pub fall_ip: FALL_IP, + #[doc = "0x28 - High Interrupt Enable Register"] + pub high_ie: HIGH_IE, + #[doc = "0x2c - High Interrupt Pending Register"] + pub high_ip: HIGH_IP, + #[doc = "0x30 - Low Interrupt Enable Register"] + pub low_ie: LOW_IE, + #[doc = "0x34 - Low Interrupt Pending Register"] + pub low_ip: LOW_IP, + #[doc = "0x38 - HW I/O Function Enable Register"] + pub iof_en: IOF_EN, + #[doc = "0x3c - HW I/O Function Select Register"] + pub iof_sel: IOF_SEL, + #[doc = "0x40 - Output XOR (invert) Register"] + pub output_xor: OUTPUT_XOR, + } + #[doc = "Input Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [input_val](input_val) module"] + pub type INPUT_VAL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INPUT_VAL; + #[doc = "`read()` method returns [input_val::R](input_val::R) reader structure"] + impl crate::Readable for INPUT_VAL {} + #[doc = "`write(|w| ..)` method takes [input_val::W](input_val::W) writer structure"] + impl crate::Writable for INPUT_VAL {} + #[doc = "Input Value Register"] + pub mod input_val { + #[doc = "Reader of register input_val"] + pub type R = crate::R; + #[doc = "Writer for register input_val"] + pub type W = crate::W; + #[doc = "Register input_val `reset()`'s with value 0"] + impl crate::ResetValue for super::INPUT_VAL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Pin Input Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [input_en](input_en) module"] + pub type INPUT_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INPUT_EN; + #[doc = "`read()` method returns [input_en::R](input_en::R) reader structure"] + impl crate::Readable for INPUT_EN {} + #[doc = "`write(|w| ..)` method takes [input_en::W](input_en::W) writer structure"] + impl crate::Writable for INPUT_EN {} + #[doc = "Pin Input Enable Register"] + pub mod input_en { + #[doc = "Reader of register input_en"] + pub type R = crate::R; + #[doc = "Writer for register input_en"] + pub type W = crate::W; + #[doc = "Register input_en `reset()`'s with value 0"] + impl crate::ResetValue for super::INPUT_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Pin Output Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_en](output_en) module"] + pub type OUTPUT_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_EN; + #[doc = "`read()` method returns [output_en::R](output_en::R) reader structure"] + impl crate::Readable for OUTPUT_EN {} + #[doc = "`write(|w| ..)` method takes [output_en::W](output_en::W) writer structure"] + impl crate::Writable for OUTPUT_EN {} + #[doc = "Pin Output Enable Register"] + pub mod output_en { + #[doc = "Reader of register output_en"] + pub type R = crate::R; + #[doc = "Writer for register output_en"] + pub type W = crate::W; + #[doc = "Register output_en `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Output Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_val](output_val) module"] + pub type OUTPUT_VAL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_VAL; + #[doc = "`read()` method returns [output_val::R](output_val::R) reader structure"] + impl crate::Readable for OUTPUT_VAL {} + #[doc = "`write(|w| ..)` method takes [output_val::W](output_val::W) writer structure"] + impl crate::Writable for OUTPUT_VAL {} + #[doc = "Output Value Register"] + pub mod output_val { + #[doc = "Reader of register output_val"] + pub type R = crate::R; + #[doc = "Writer for register output_val"] + pub type W = crate::W; + #[doc = "Register output_val `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_VAL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Internal Pull-Up Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pullup_en](pullup_en) module"] + pub type PULLUP_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PULLUP_EN; + #[doc = "`read()` method returns [pullup_en::R](pullup_en::R) reader structure"] + impl crate::Readable for PULLUP_EN {} + #[doc = "`write(|w| ..)` method takes [pullup_en::W](pullup_en::W) writer structure"] + impl crate::Writable for PULLUP_EN {} + #[doc = "Internal Pull-Up Enable Register"] + pub mod pullup_en { + #[doc = "Reader of register pullup_en"] + pub type R = crate::R; + #[doc = "Writer for register pullup_en"] + pub type W = crate::W; + #[doc = "Register pullup_en `reset()`'s with value 0"] + impl crate::ResetValue for super::PULLUP_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Drive Strength Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drive](drive) module"] + pub type DRIVE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DRIVE; + #[doc = "`read()` method returns [drive::R](drive::R) reader structure"] + impl crate::Readable for DRIVE {} + #[doc = "`write(|w| ..)` method takes [drive::W](drive::W) writer structure"] + impl crate::Writable for DRIVE {} + #[doc = "Drive Strength Register"] + pub mod drive { + #[doc = "Reader of register drive"] + pub type R = crate::R; + #[doc = "Writer for register drive"] + pub type W = crate::W; + #[doc = "Register drive `reset()`'s with value 0"] + impl crate::ResetValue for super::DRIVE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Rise Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rise_ie](rise_ie) module"] + pub type RISE_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISE_IE; + #[doc = "`read()` method returns [rise_ie::R](rise_ie::R) reader structure"] + impl crate::Readable for RISE_IE {} + #[doc = "`write(|w| ..)` method takes [rise_ie::W](rise_ie::W) writer structure"] + impl crate::Writable for RISE_IE {} + #[doc = "Rise Interrupt Enable Register"] + pub mod rise_ie { + #[doc = "Reader of register rise_ie"] + pub type R = crate::R; + #[doc = "Writer for register rise_ie"] + pub type W = crate::W; + #[doc = "Register rise_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::RISE_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Rise Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rise_ip](rise_ip) module"] + pub type RISE_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISE_IP; + #[doc = "`read()` method returns [rise_ip::R](rise_ip::R) reader structure"] + impl crate::Readable for RISE_IP {} + #[doc = "`write(|w| ..)` method takes [rise_ip::W](rise_ip::W) writer structure"] + impl crate::Writable for RISE_IP {} + #[doc = "Rise Interrupt Pending Register"] + pub mod rise_ip { + #[doc = "Reader of register rise_ip"] + pub type R = crate::R; + #[doc = "Writer for register rise_ip"] + pub type W = crate::W; + #[doc = "Register rise_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::RISE_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Fall Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fall_ie](fall_ie) module"] + pub type FALL_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FALL_IE; + #[doc = "`read()` method returns [fall_ie::R](fall_ie::R) reader structure"] + impl crate::Readable for FALL_IE {} + #[doc = "`write(|w| ..)` method takes [fall_ie::W](fall_ie::W) writer structure"] + impl crate::Writable for FALL_IE {} + #[doc = "Fall Interrupt Enable Register"] + pub mod fall_ie { + #[doc = "Reader of register fall_ie"] + pub type R = crate::R; + #[doc = "Writer for register fall_ie"] + pub type W = crate::W; + #[doc = "Register fall_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::FALL_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Fall Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fall_ip](fall_ip) module"] + pub type FALL_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FALL_IP; + #[doc = "`read()` method returns [fall_ip::R](fall_ip::R) reader structure"] + impl crate::Readable for FALL_IP {} + #[doc = "`write(|w| ..)` method takes [fall_ip::W](fall_ip::W) writer structure"] + impl crate::Writable for FALL_IP {} + #[doc = "Fall Interrupt Pending Register"] + pub mod fall_ip { + #[doc = "Reader of register fall_ip"] + pub type R = crate::R; + #[doc = "Writer for register fall_ip"] + pub type W = crate::W; + #[doc = "Register fall_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::FALL_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "High Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [high_ie](high_ie) module"] + pub type HIGH_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _HIGH_IE; + #[doc = "`read()` method returns [high_ie::R](high_ie::R) reader structure"] + impl crate::Readable for HIGH_IE {} + #[doc = "`write(|w| ..)` method takes [high_ie::W](high_ie::W) writer structure"] + impl crate::Writable for HIGH_IE {} + #[doc = "High Interrupt Enable Register"] + pub mod high_ie { + #[doc = "Reader of register high_ie"] + pub type R = crate::R; + #[doc = "Writer for register high_ie"] + pub type W = crate::W; + #[doc = "Register high_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::HIGH_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "High Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [high_ip](high_ip) module"] + pub type HIGH_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _HIGH_IP; + #[doc = "`read()` method returns [high_ip::R](high_ip::R) reader structure"] + impl crate::Readable for HIGH_IP {} + #[doc = "`write(|w| ..)` method takes [high_ip::W](high_ip::W) writer structure"] + impl crate::Writable for HIGH_IP {} + #[doc = "High Interrupt Pending Register"] + pub mod high_ip { + #[doc = "Reader of register high_ip"] + pub type R = crate::R; + #[doc = "Writer for register high_ip"] + pub type W = crate::W; + #[doc = "Register high_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::HIGH_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Low Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [low_ie](low_ie) module"] + pub type LOW_IE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOW_IE; + #[doc = "`read()` method returns [low_ie::R](low_ie::R) reader structure"] + impl crate::Readable for LOW_IE {} + #[doc = "`write(|w| ..)` method takes [low_ie::W](low_ie::W) writer structure"] + impl crate::Writable for LOW_IE {} + #[doc = "Low Interrupt Enable Register"] + pub mod low_ie { + #[doc = "Reader of register low_ie"] + pub type R = crate::R; + #[doc = "Writer for register low_ie"] + pub type W = crate::W; + #[doc = "Register low_ie `reset()`'s with value 0"] + impl crate::ResetValue for super::LOW_IE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Low Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [low_ip](low_ip) module"] + pub type LOW_IP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOW_IP; + #[doc = "`read()` method returns [low_ip::R](low_ip::R) reader structure"] + impl crate::Readable for LOW_IP {} + #[doc = "`write(|w| ..)` method takes [low_ip::W](low_ip::W) writer structure"] + impl crate::Writable for LOW_IP {} + #[doc = "Low Interrupt Pending Register"] + pub mod low_ip { + #[doc = "Reader of register low_ip"] + pub type R = crate::R; + #[doc = "Writer for register low_ip"] + pub type W = crate::W; + #[doc = "Register low_ip `reset()`'s with value 0"] + impl crate::ResetValue for super::LOW_IP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "HW I/O Function Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iof_en](iof_en) module"] + pub type IOF_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IOF_EN; + #[doc = "`read()` method returns [iof_en::R](iof_en::R) reader structure"] + impl crate::Readable for IOF_EN {} + #[doc = "`write(|w| ..)` method takes [iof_en::W](iof_en::W) writer structure"] + impl crate::Writable for IOF_EN {} + #[doc = "HW I/O Function Enable Register"] + pub mod iof_en { + #[doc = "Reader of register iof_en"] + pub type R = crate::R; + #[doc = "Writer for register iof_en"] + pub type W = crate::W; + #[doc = "Register iof_en `reset()`'s with value 0"] + impl crate::ResetValue for super::IOF_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "HW I/O Function Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iof_sel](iof_sel) module"] + pub type IOF_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IOF_SEL; + #[doc = "`read()` method returns [iof_sel::R](iof_sel::R) reader structure"] + impl crate::Readable for IOF_SEL {} + #[doc = "`write(|w| ..)` method takes [iof_sel::W](iof_sel::W) writer structure"] + impl crate::Writable for IOF_SEL {} + #[doc = "HW I/O Function Select Register"] + pub mod iof_sel { + #[doc = "Reader of register iof_sel"] + pub type R = crate::R; + #[doc = "Writer for register iof_sel"] + pub type W = crate::W; + #[doc = "Register iof_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::IOF_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } + #[doc = "Output XOR (invert) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_xor](output_xor) module"] + pub type OUTPUT_XOR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_XOR; + #[doc = "`read()` method returns [output_xor::R](output_xor::R) reader structure"] + impl crate::Readable for OUTPUT_XOR {} + #[doc = "`write(|w| ..)` method takes [output_xor::W](output_xor::W) writer structure"] + impl crate::Writable for OUTPUT_XOR {} + #[doc = "Output XOR (invert) Register"] + pub mod output_xor { + #[doc = "Reader of register output_xor"] + pub type R = crate::R; + #[doc = "Writer for register output_xor"] + pub type W = crate::W; + #[doc = "Register output_xor `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_XOR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-31)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-31)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&self) -> PIN_R { + PIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&self) -> PIN_R { + PIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&self) -> PIN_R { + PIN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&self) -> PIN_R { + PIN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&self) -> PIN_R { + PIN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&self) -> PIN_R { + PIN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&self) -> PIN_R { + PIN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&self) -> PIN_R { + PIN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&self) -> PIN_R { + PIN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&self) -> PIN_R { + PIN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&self) -> PIN_R { + PIN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&self) -> PIN_R { + PIN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&self) -> PIN_R { + PIN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&self) -> PIN_R { + PIN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&self) -> PIN_R { + PIN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&self) -> PIN_R { + PIN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&self) -> PIN_R { + PIN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&self) -> PIN_R { + PIN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&self) -> PIN_R { + PIN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&self) -> PIN_R { + PIN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&self) -> PIN_R { + PIN_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&self) -> PIN_R { + PIN_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&self) -> PIN_R { + PIN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&self) -> PIN_R { + PIN_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn pin8(&mut self) -> PIN_W { + PIN_W { w: self, offset: 8 } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pin9(&mut self) -> PIN_W { + PIN_W { w: self, offset: 9 } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pin10(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pin11(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pin12(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pin13(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 13, + } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pin14(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 14, + } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pin15(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 15, + } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pin16(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn pin17(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pin18(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn pin19(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn pin20(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pin21(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 21, + } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn pin22(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 22, + } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn pin23(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 23, + } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn pin24(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn pin25(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn pin26(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn pin27(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn pin28(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn pin29(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 29, + } + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn pin30(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 30, + } + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn pin31(&mut self) -> PIN_W { + PIN_W { + w: self, + offset: 31, + } + } + } + } +} +#[doc = "Neural Network Accelerator"] +pub struct KPU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for KPU {} +impl KPU { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const kpu::RegisterBlock { + 0x4080_0000 as *const _ + } +} +impl Deref for KPU { + type Target = kpu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*KPU::ptr() } + } +} +#[doc = "Neural Network Accelerator"] +pub mod kpu { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register"] + pub layer_argument_fifo: LAYER_ARGUMENT_FIFO, + #[doc = "0x08 - Interrupt status"] + pub interrupt_status: INTERRUPT_STATUS, + #[doc = "0x10 - Interrupt raw"] + pub interrupt_raw: INTERRUPT_RAW, + #[doc = "0x18 - Interrupt mask: 0 enables the interrupt, 1 masks the interrupt"] + pub interrupt_mask: INTERRUPT_MASK, + #[doc = "0x20 - Interrupt clear: write 1 to a bit to clear interrupt"] + pub interrupt_clear: INTERRUPT_CLEAR, + #[doc = "0x28 - FIFO threshold"] + pub fifo_threshold: FIFO_THRESHOLD, + #[doc = "0x30 - FIFO data output"] + pub fifo_data_out: FIFO_DATA_OUT, + #[doc = "0x38 - FIFO control"] + pub fifo_ctrl: FIFO_CTRL, + #[doc = "0x40 - Eight bit mode"] + pub eight_bit_mode: EIGHT_BIT_MODE, + } + #[doc = "Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [layer_argument_fifo](layer_argument_fifo) module"] + pub type LAYER_ARGUMENT_FIFO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LAYER_ARGUMENT_FIFO; + #[doc = "`read()` method returns [layer_argument_fifo::R](layer_argument_fifo::R) reader structure"] + impl crate::Readable for LAYER_ARGUMENT_FIFO {} + #[doc = "`write(|w| ..)` method takes [layer_argument_fifo::W](layer_argument_fifo::W) writer structure"] + impl crate::Writable for LAYER_ARGUMENT_FIFO {} + #[doc = "Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register"] + pub mod layer_argument_fifo { + #[doc = "Reader of register layer_argument_fifo"] + pub type R = crate::R; + #[doc = "Writer for register layer_argument_fifo"] + pub type W = crate::W; + #[doc = "Register layer_argument_fifo `reset()`'s with value 0"] + impl crate::ResetValue for super::LAYER_ARGUMENT_FIFO { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_status](interrupt_status) module"] + pub type INTERRUPT_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_STATUS; + #[doc = "`read()` method returns [interrupt_status::R](interrupt_status::R) reader structure"] + impl crate::Readable for INTERRUPT_STATUS {} + #[doc = "`write(|w| ..)` method takes [interrupt_status::W](interrupt_status::W) writer structure"] + impl crate::Writable for INTERRUPT_STATUS {} + #[doc = "Interrupt status"] + pub mod interrupt_status { + #[doc = "Reader of register interrupt_status"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_status"] + pub type W = crate::W; + #[doc = "Register interrupt_status `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_STATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "Interrupt raw\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_raw](interrupt_raw) module"] + pub type INTERRUPT_RAW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_RAW; + #[doc = "`read()` method returns [interrupt_raw::R](interrupt_raw::R) reader structure"] + impl crate::Readable for INTERRUPT_RAW {} + #[doc = "`write(|w| ..)` method takes [interrupt_raw::W](interrupt_raw::W) writer structure"] + impl crate::Writable for INTERRUPT_RAW {} + #[doc = "Interrupt raw"] + pub mod interrupt_raw { + #[doc = "Reader of register interrupt_raw"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_raw"] + pub type W = crate::W; + #[doc = "Register interrupt_raw `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_RAW { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "Interrupt mask: 0 enables the interrupt, 1 masks the interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_mask](interrupt_mask) module"] + pub type INTERRUPT_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_MASK; + #[doc = "`read()` method returns [interrupt_mask::R](interrupt_mask::R) reader structure"] + impl crate::Readable for INTERRUPT_MASK {} + #[doc = "`write(|w| ..)` method takes [interrupt_mask::W](interrupt_mask::W) writer structure"] + impl crate::Writable for INTERRUPT_MASK {} + #[doc = "Interrupt mask: 0 enables the interrupt, 1 masks the interrupt"] + pub mod interrupt_mask { + #[doc = "Reader of register interrupt_mask"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_mask"] + pub type W = crate::W; + #[doc = "Register interrupt_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_MASK { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "Interrupt clear: write 1 to a bit to clear interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_clear](interrupt_clear) module"] + pub type INTERRUPT_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_CLEAR; + #[doc = "`read()` method returns [interrupt_clear::R](interrupt_clear::R) reader structure"] + impl crate::Readable for INTERRUPT_CLEAR {} + #[doc = "`write(|w| ..)` method takes [interrupt_clear::W](interrupt_clear::W) writer structure"] + impl crate::Writable for INTERRUPT_CLEAR {} + #[doc = "Interrupt clear: write 1 to a bit to clear interrupt"] + pub mod interrupt_clear { + #[doc = "Reader of register interrupt_clear"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_clear"] + pub type W = crate::W; + #[doc = "Register interrupt_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_CLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `calc_done`"] + pub type CALC_DONE_R = crate::R; + #[doc = "Write proxy for field `calc_done`"] + pub struct CALC_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> CALC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_empty`"] + pub type LAYER_CFG_ALMOST_EMPTY_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_empty`"] + pub struct LAYER_CFG_ALMOST_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `layer_cfg_almost_full`"] + pub type LAYER_CFG_ALMOST_FULL_R = crate::R; + #[doc = "Write proxy for field `layer_cfg_almost_full`"] + pub struct LAYER_CFG_ALMOST_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> LAYER_CFG_ALMOST_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&self) -> CALC_DONE_R { + CALC_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&self) -> LAYER_CFG_ALMOST_EMPTY_R { + LAYER_CFG_ALMOST_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&self) -> LAYER_CFG_ALMOST_FULL_R { + LAYER_CFG_ALMOST_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Interrupt raised when calculation is done"] + #[inline(always)] + pub fn calc_done(&mut self) -> CALC_DONE_W { + CALC_DONE_W { w: self } + } + #[doc = "Bit 1 - Interrupt raised when layer arguments FIFO almost empty"] + #[inline(always)] + pub fn layer_cfg_almost_empty(&mut self) -> LAYER_CFG_ALMOST_EMPTY_W { + LAYER_CFG_ALMOST_EMPTY_W { w: self } + } + #[doc = "Bit 2 - Interrupt raised when layer arguments FIFO almost full"] + #[inline(always)] + pub fn layer_cfg_almost_full(&mut self) -> LAYER_CFG_ALMOST_FULL_W { + LAYER_CFG_ALMOST_FULL_W { w: self } + } + } + } + #[doc = "FIFO threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_threshold](fifo_threshold) module"] + pub type FIFO_THRESHOLD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_THRESHOLD; + #[doc = "`read()` method returns [fifo_threshold::R](fifo_threshold::R) reader structure"] + impl crate::Readable for FIFO_THRESHOLD {} + #[doc = "`write(|w| ..)` method takes [fifo_threshold::W](fifo_threshold::W) writer structure"] + impl crate::Writable for FIFO_THRESHOLD {} + #[doc = "FIFO threshold"] + pub mod fifo_threshold { + #[doc = "Reader of register fifo_threshold"] + pub type R = crate::R; + #[doc = "Writer for register fifo_threshold"] + pub type W = crate::W; + #[doc = "Register fifo_threshold `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_THRESHOLD { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `full_threshold`"] + pub type FULL_THRESHOLD_R = crate::R; + #[doc = "Write proxy for field `full_threshold`"] + pub struct FULL_THRESHOLD_W<'a> { + w: &'a mut W, + } + impl<'a> FULL_THRESHOLD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u64) & 0x0f); + self.w + } + } + #[doc = "Reader of field `empty_threshold`"] + pub type EMPTY_THRESHOLD_R = crate::R; + #[doc = "Write proxy for field `empty_threshold`"] + pub struct EMPTY_THRESHOLD_W<'a> { + w: &'a mut W, + } + impl<'a> EMPTY_THRESHOLD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u64) & 0x0f) << 4); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - FIFO full threshold"] + #[inline(always)] + pub fn full_threshold(&self) -> FULL_THRESHOLD_R { + FULL_THRESHOLD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - FIFO empty threshold"] + #[inline(always)] + pub fn empty_threshold(&self) -> EMPTY_THRESHOLD_R { + EMPTY_THRESHOLD_R::new(((self.bits >> 4) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - FIFO full threshold"] + #[inline(always)] + pub fn full_threshold(&mut self) -> FULL_THRESHOLD_W { + FULL_THRESHOLD_W { w: self } + } + #[doc = "Bits 4:7 - FIFO empty threshold"] + #[inline(always)] + pub fn empty_threshold(&mut self) -> EMPTY_THRESHOLD_W { + EMPTY_THRESHOLD_W { w: self } + } + } + } + #[doc = "FIFO data output\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_data_out](fifo_data_out) module"] + pub type FIFO_DATA_OUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_DATA_OUT; + #[doc = "`read()` method returns [fifo_data_out::R](fifo_data_out::R) reader structure"] + impl crate::Readable for FIFO_DATA_OUT {} + #[doc = "`write(|w| ..)` method takes [fifo_data_out::W](fifo_data_out::W) writer structure"] + impl crate::Writable for FIFO_DATA_OUT {} + #[doc = "FIFO data output"] + pub mod fifo_data_out { + #[doc = "Reader of register fifo_data_out"] + pub type R = crate::R; + #[doc = "Writer for register fifo_data_out"] + pub type W = crate::W; + #[doc = "Register fifo_data_out `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_DATA_OUT { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FIFO control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_ctrl](fifo_ctrl) module"] + pub type FIFO_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_CTRL; + #[doc = "`read()` method returns [fifo_ctrl::R](fifo_ctrl::R) reader structure"] + impl crate::Readable for FIFO_CTRL {} + #[doc = "`write(|w| ..)` method takes [fifo_ctrl::W](fifo_ctrl::W) writer structure"] + impl crate::Writable for FIFO_CTRL {} + #[doc = "FIFO control"] + pub mod fifo_ctrl { + #[doc = "Reader of register fifo_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register fifo_ctrl"] + pub type W = crate::W; + #[doc = "Register fifo_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_CTRL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dma_fifo_flush_n`"] + pub type DMA_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `dma_fifo_flush_n`"] + pub struct DMA_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `gs_fifo_flush_n`"] + pub type GS_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `gs_fifo_flush_n`"] + pub struct GS_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> GS_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `cfg_fifo_flush_n`"] + pub type CFG_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `cfg_fifo_flush_n`"] + pub struct CFG_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> CFG_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `cmd_fifo_flush_n`"] + pub type CMD_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `cmd_fifo_flush_n`"] + pub struct CMD_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> CMD_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `resp_fifo_flush_n`"] + pub type RESP_FIFO_FLUSH_N_R = crate::R; + #[doc = "Write proxy for field `resp_fifo_flush_n`"] + pub struct RESP_FIFO_FLUSH_N_W<'a> { + w: &'a mut W, + } + impl<'a> RESP_FIFO_FLUSH_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + impl R { + #[doc = "Bit 0 - Flush DMA FIFO"] + #[inline(always)] + pub fn dma_fifo_flush_n(&self) -> DMA_FIFO_FLUSH_N_R { + DMA_FIFO_FLUSH_N_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Flush GS FIFO"] + #[inline(always)] + pub fn gs_fifo_flush_n(&self) -> GS_FIFO_FLUSH_N_R { + GS_FIFO_FLUSH_N_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush configuration FIFO"] + #[inline(always)] + pub fn cfg_fifo_flush_n(&self) -> CFG_FIFO_FLUSH_N_R { + CFG_FIFO_FLUSH_N_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Flush command FIFO"] + #[inline(always)] + pub fn cmd_fifo_flush_n(&self) -> CMD_FIFO_FLUSH_N_R { + CMD_FIFO_FLUSH_N_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Flush response FIFO"] + #[inline(always)] + pub fn resp_fifo_flush_n(&self) -> RESP_FIFO_FLUSH_N_R { + RESP_FIFO_FLUSH_N_R::new(((self.bits >> 4) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Flush DMA FIFO"] + #[inline(always)] + pub fn dma_fifo_flush_n(&mut self) -> DMA_FIFO_FLUSH_N_W { + DMA_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 1 - Flush GS FIFO"] + #[inline(always)] + pub fn gs_fifo_flush_n(&mut self) -> GS_FIFO_FLUSH_N_W { + GS_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 2 - Flush configuration FIFO"] + #[inline(always)] + pub fn cfg_fifo_flush_n(&mut self) -> CFG_FIFO_FLUSH_N_W { + CFG_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 3 - Flush command FIFO"] + #[inline(always)] + pub fn cmd_fifo_flush_n(&mut self) -> CMD_FIFO_FLUSH_N_W { + CMD_FIFO_FLUSH_N_W { w: self } + } + #[doc = "Bit 4 - Flush response FIFO"] + #[inline(always)] + pub fn resp_fifo_flush_n(&mut self) -> RESP_FIFO_FLUSH_N_W { + RESP_FIFO_FLUSH_N_W { w: self } + } + } + } + #[doc = "Eight bit mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eight_bit_mode](eight_bit_mode) module"] + pub type EIGHT_BIT_MODE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EIGHT_BIT_MODE; + #[doc = "`read()` method returns [eight_bit_mode::R](eight_bit_mode::R) reader structure"] + impl crate::Readable for EIGHT_BIT_MODE {} + #[doc = "`write(|w| ..)` method takes [eight_bit_mode::W](eight_bit_mode::W) writer structure"] + impl crate::Writable for EIGHT_BIT_MODE {} + #[doc = "Eight bit mode"] + pub mod eight_bit_mode { + #[doc = "Reader of register eight_bit_mode"] + pub type R = crate::R; + #[doc = "Writer for register eight_bit_mode"] + pub type W = crate::W; + #[doc = "Register eight_bit_mode `reset()`'s with value 0"] + impl crate::ResetValue for super::EIGHT_BIT_MODE { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `eight_bit_mode`"] + pub type EIGHT_BIT_MODE_R = crate::R; + #[doc = "Write proxy for field `eight_bit_mode`"] + pub struct EIGHT_BIT_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> EIGHT_BIT_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Use 8-bit instead of 16-bit precision if set"] + #[inline(always)] + pub fn eight_bit_mode(&self) -> EIGHT_BIT_MODE_R { + EIGHT_BIT_MODE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Use 8-bit instead of 16-bit precision if set"] + #[inline(always)] + pub fn eight_bit_mode(&mut self) -> EIGHT_BIT_MODE_W { + EIGHT_BIT_MODE_W { w: self } + } + } + } +} +#[doc = "Fast Fourier Transform Accelerator"] +pub struct FFT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FFT {} +impl FFT { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fft::RegisterBlock { + 0x4200_0000 as *const _ + } +} +impl Deref for FFT { + type Target = fft::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*FFT::ptr() } + } +} +#[doc = "Fast Fourier Transform Accelerator"] +pub mod fft { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - FFT input data fifo"] + pub input_fifo: INPUT_FIFO, + #[doc = "0x08 - FFT control register"] + pub ctrl: CTRL, + #[doc = "0x10 - FIFO control"] + pub fifo_ctrl: FIFO_CTRL, + #[doc = "0x18 - intr_mask"] + pub interruptmask: INTERRUPTMASK, + #[doc = "0x20 - Interrupt clear"] + pub intr_clear: INTR_CLEAR, + #[doc = "0x28 - FFT status register"] + pub status: STATUS, + #[doc = "0x30 - FFT status raw"] + pub status_raw: STATUS_RAW, + #[doc = "0x38 - FFT output FIFO"] + pub output_fifo: OUTPUT_FIFO, + } + #[doc = "FFT input data fifo\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [input_fifo](input_fifo) module"] + pub type INPUT_FIFO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INPUT_FIFO; + #[doc = "`read()` method returns [input_fifo::R](input_fifo::R) reader structure"] + impl crate::Readable for INPUT_FIFO {} + #[doc = "`write(|w| ..)` method takes [input_fifo::W](input_fifo::W) writer structure"] + impl crate::Writable for INPUT_FIFO {} + #[doc = "FFT input data fifo"] + pub mod input_fifo { + #[doc = "Reader of register input_fifo"] + pub type R = crate::R; + #[doc = "Writer for register input_fifo"] + pub type W = crate::W; + #[doc = "Register input_fifo `reset()`'s with value 0"] + impl crate::ResetValue for super::INPUT_FIFO { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FFT control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](ctrl) module"] + pub type CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRL; + #[doc = "`read()` method returns [ctrl::R](ctrl::R) reader structure"] + impl crate::Readable for CTRL {} + #[doc = "`write(|w| ..)` method takes [ctrl::W](ctrl::W) writer structure"] + impl crate::Writable for CTRL {} + #[doc = "FFT control register"] + pub mod ctrl { + #[doc = "Reader of register ctrl"] + pub type R = crate::R; + #[doc = "Writer for register ctrl"] + pub type W = crate::W; + #[doc = "Register ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "FFT calculation data length\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum POINT_A { + #[doc = "0: 512 point"] + P512 = 0, + #[doc = "1: 256 point"] + P256 = 1, + #[doc = "2: 128 point"] + P128 = 2, + #[doc = "3: 64 point"] + P64 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: POINT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `point`"] + pub type POINT_R = crate::R; + impl POINT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(POINT_A::P512), + 1 => Val(POINT_A::P256), + 2 => Val(POINT_A::P128), + 3 => Val(POINT_A::P64), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `P512`"] + #[inline(always)] + pub fn is_p512(&self) -> bool { + *self == POINT_A::P512 + } + #[doc = "Checks if the value of the field is `P256`"] + #[inline(always)] + pub fn is_p256(&self) -> bool { + *self == POINT_A::P256 + } + #[doc = "Checks if the value of the field is `P128`"] + #[inline(always)] + pub fn is_p128(&self) -> bool { + *self == POINT_A::P128 + } + #[doc = "Checks if the value of the field is `P64`"] + #[inline(always)] + pub fn is_p64(&self) -> bool { + *self == POINT_A::P64 + } + } + #[doc = "Write proxy for field `point`"] + pub struct POINT_W<'a> { + w: &'a mut W, + } + impl<'a> POINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: POINT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "512 point"] + #[inline(always)] + pub fn p512(self) -> &'a mut W { + self.variant(POINT_A::P512) + } + #[doc = "256 point"] + #[inline(always)] + pub fn p256(self) -> &'a mut W { + self.variant(POINT_A::P256) + } + #[doc = "128 point"] + #[inline(always)] + pub fn p128(self) -> &'a mut W { + self.variant(POINT_A::P128) + } + #[doc = "64 point"] + #[inline(always)] + pub fn p64(self) -> &'a mut W { + self.variant(POINT_A::P64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u64) & 0x07); + self.w + } + } + #[doc = "FFT mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum MODE_A { + #[doc = "0: FFT mode"] + FFT = 0, + #[doc = "1: Inverse FFT mode"] + IFFT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `mode`"] + pub type MODE_R = crate::R; + impl MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::FFT, + true => MODE_A::IFFT, + } + } + #[doc = "Checks if the value of the field is `FFT`"] + #[inline(always)] + pub fn is_fft(&self) -> bool { + *self == MODE_A::FFT + } + #[doc = "Checks if the value of the field is `IFFT`"] + #[inline(always)] + pub fn is_ifft(&self) -> bool { + *self == MODE_A::IFFT + } + } + #[doc = "Write proxy for field `mode`"] + pub struct MODE_W<'a> { + w: &'a mut W, + } + impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "FFT mode"] + #[inline(always)] + pub fn fft(self) -> &'a mut W { + self.variant(MODE_A::FFT) + } + #[doc = "Inverse FFT mode"] + #[inline(always)] + pub fn ifft(self) -> &'a mut W { + self.variant(MODE_A::IFFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `shift`"] + pub type SHIFT_R = crate::R; + #[doc = "Write proxy for field `shift`"] + pub struct SHIFT_W<'a> { + w: &'a mut W, + } + impl<'a> SHIFT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 4)) | (((value as u64) & 0x01ff) << 4); + self.w + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u64) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `dma_send`"] + pub type DMA_SEND_R = crate::R; + #[doc = "Write proxy for field `dma_send`"] + pub struct DMA_SEND_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u64) & 0x01) << 14); + self.w + } + } + #[doc = "Input data arrangement\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum INPUT_MODE_A { + #[doc = "0: RIRI (real imaginary interleaved)"] + RIRI = 0, + #[doc = "1: RRRR (only real part)"] + RRRR = 1, + #[doc = "2: First input the real part and then input the imaginary part"] + RRII = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: INPUT_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `input_mode`"] + pub type INPUT_MODE_R = crate::R; + impl INPUT_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(INPUT_MODE_A::RIRI), + 1 => Val(INPUT_MODE_A::RRRR), + 2 => Val(INPUT_MODE_A::RRII), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `RIRI`"] + #[inline(always)] + pub fn is_riri(&self) -> bool { + *self == INPUT_MODE_A::RIRI + } + #[doc = "Checks if the value of the field is `RRRR`"] + #[inline(always)] + pub fn is_rrrr(&self) -> bool { + *self == INPUT_MODE_A::RRRR + } + #[doc = "Checks if the value of the field is `RRII`"] + #[inline(always)] + pub fn is_rrii(&self) -> bool { + *self == INPUT_MODE_A::RRII + } + } + #[doc = "Write proxy for field `input_mode`"] + pub struct INPUT_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> INPUT_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INPUT_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RIRI (real imaginary interleaved)"] + #[inline(always)] + pub fn riri(self) -> &'a mut W { + self.variant(INPUT_MODE_A::RIRI) + } + #[doc = "RRRR (only real part)"] + #[inline(always)] + pub fn rrrr(self) -> &'a mut W { + self.variant(INPUT_MODE_A::RRRR) + } + #[doc = "First input the real part and then input the imaginary part"] + #[inline(always)] + pub fn rrii(self) -> &'a mut W { + self.variant(INPUT_MODE_A::RRII) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 15)) | (((value as u64) & 0x03) << 15); + self.w + } + } + #[doc = "Effective width of input data\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum DATA_MODE_A { + #[doc = "0: 64 bit effective"] + WIDTH_64 = 0, + #[doc = "1: 128 bit effective"] + WIDTH_128 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: DATA_MODE_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `data_mode`"] + pub type DATA_MODE_R = crate::R; + impl DATA_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATA_MODE_A { + match self.bits { + false => DATA_MODE_A::WIDTH_64, + true => DATA_MODE_A::WIDTH_128, + } + } + #[doc = "Checks if the value of the field is `WIDTH_64`"] + #[inline(always)] + pub fn is_width_64(&self) -> bool { + *self == DATA_MODE_A::WIDTH_64 + } + #[doc = "Checks if the value of the field is `WIDTH_128`"] + #[inline(always)] + pub fn is_width_128(&self) -> bool { + *self == DATA_MODE_A::WIDTH_128 + } + } + #[doc = "Write proxy for field `data_mode`"] + pub struct DATA_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATA_MODE_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "64 bit effective"] + #[inline(always)] + pub fn width_64(self) -> &'a mut W { + self.variant(DATA_MODE_A::WIDTH_64) + } + #[doc = "128 bit effective"] + #[inline(always)] + pub fn width_128(self) -> &'a mut W { + self.variant(DATA_MODE_A::WIDTH_128) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u64) & 0x01) << 17); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - FFT calculation data length"] + #[inline(always)] + pub fn point(&self) -> POINT_R { + POINT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - FFT mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:12 - Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ..."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new(((self.bits >> 4) & 0x01ff) as u16) + } + #[doc = "Bit 13 - FFT enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - FFT DMA enable"] + #[inline(always)] + pub fn dma_send(&self) -> DMA_SEND_R { + DMA_SEND_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bits 15:16 - Input data arrangement"] + #[inline(always)] + pub fn input_mode(&self) -> INPUT_MODE_R { + INPUT_MODE_R::new(((self.bits >> 15) & 0x03) as u8) + } + #[doc = "Bit 17 - Effective width of input data"] + #[inline(always)] + pub fn data_mode(&self) -> DATA_MODE_R { + DATA_MODE_R::new(((self.bits >> 17) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:2 - FFT calculation data length"] + #[inline(always)] + pub fn point(&mut self) -> POINT_W { + POINT_W { w: self } + } + #[doc = "Bit 3 - FFT mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:12 - Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ..."] + #[inline(always)] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W { w: self } + } + #[doc = "Bit 13 - FFT enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 14 - FFT DMA enable"] + #[inline(always)] + pub fn dma_send(&mut self) -> DMA_SEND_W { + DMA_SEND_W { w: self } + } + #[doc = "Bits 15:16 - Input data arrangement"] + #[inline(always)] + pub fn input_mode(&mut self) -> INPUT_MODE_W { + INPUT_MODE_W { w: self } + } + #[doc = "Bit 17 - Effective width of input data"] + #[inline(always)] + pub fn data_mode(&mut self) -> DATA_MODE_W { + DATA_MODE_W { w: self } + } + } + } + #[doc = "FIFO control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_ctrl](fifo_ctrl) module"] + pub type FIFO_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FIFO_CTRL; + #[doc = "`read()` method returns [fifo_ctrl::R](fifo_ctrl::R) reader structure"] + impl crate::Readable for FIFO_CTRL {} + #[doc = "`write(|w| ..)` method takes [fifo_ctrl::W](fifo_ctrl::W) writer structure"] + impl crate::Writable for FIFO_CTRL {} + #[doc = "FIFO control"] + pub mod fifo_ctrl { + #[doc = "Reader of register fifo_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register fifo_ctrl"] + pub type W = crate::W; + #[doc = "Register fifo_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::FIFO_CTRL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `resp_fifo_flush`"] + pub type RESP_FIFO_FLUSH_R = crate::R; + #[doc = "Write proxy for field `resp_fifo_flush`"] + pub struct RESP_FIFO_FLUSH_W<'a> { + w: &'a mut W, + } + impl<'a> RESP_FIFO_FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `cmd_fifo_flush`"] + pub type CMD_FIFO_FLUSH_R = crate::R; + #[doc = "Write proxy for field `cmd_fifo_flush`"] + pub struct CMD_FIFO_FLUSH_W<'a> { + w: &'a mut W, + } + impl<'a> CMD_FIFO_FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `gs_fifo_flush`"] + pub type GS_FIFO_FLUSH_R = crate::R; + #[doc = "Write proxy for field `gs_fifo_flush`"] + pub struct GS_FIFO_FLUSH_W<'a> { + w: &'a mut W, + } + impl<'a> GS_FIFO_FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - Response memory initialization flag"] + #[inline(always)] + pub fn resp_fifo_flush(&self) -> RESP_FIFO_FLUSH_R { + RESP_FIFO_FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Command memory initialization flag"] + #[inline(always)] + pub fn cmd_fifo_flush(&self) -> CMD_FIFO_FLUSH_R { + CMD_FIFO_FLUSH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Output interface memory initialization flag"] + #[inline(always)] + pub fn gs_fifo_flush(&self) -> GS_FIFO_FLUSH_R { + GS_FIFO_FLUSH_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Response memory initialization flag"] + #[inline(always)] + pub fn resp_fifo_flush(&mut self) -> RESP_FIFO_FLUSH_W { + RESP_FIFO_FLUSH_W { w: self } + } + #[doc = "Bit 1 - Command memory initialization flag"] + #[inline(always)] + pub fn cmd_fifo_flush(&mut self) -> CMD_FIFO_FLUSH_W { + CMD_FIFO_FLUSH_W { w: self } + } + #[doc = "Bit 2 - Output interface memory initialization flag"] + #[inline(always)] + pub fn gs_fifo_flush(&mut self) -> GS_FIFO_FLUSH_W { + GS_FIFO_FLUSH_W { w: self } + } + } + } + #[doc = "intr_mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interruptmask](interruptmask) module"] + pub type INTERRUPTMASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPTMASK; + #[doc = "`read()` method returns [interruptmask::R](interruptmask::R) reader structure"] + impl crate::Readable for INTERRUPTMASK {} + #[doc = "`write(|w| ..)` method takes [interruptmask::W](interruptmask::W) writer structure"] + impl crate::Writable for INTERRUPTMASK {} + #[doc = "intr_mask"] + pub mod interruptmask { + #[doc = "Reader of register interrupt mask"] + pub type R = crate::R; + #[doc = "Writer for register interrupt mask"] + pub type W = crate::W; + #[doc = "Register interrupt mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPTMASK { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + } + } + #[doc = "Interrupt clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_clear](intr_clear) module"] + pub type INTR_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_CLEAR; + #[doc = "`read()` method returns [intr_clear::R](intr_clear::R) reader structure"] + impl crate::Readable for INTR_CLEAR {} + #[doc = "`write(|w| ..)` method takes [intr_clear::W](intr_clear::W) writer structure"] + impl crate::Writable for INTR_CLEAR {} + #[doc = "Interrupt clear"] + pub mod intr_clear { + #[doc = "Reader of register intr_clear"] + pub type R = crate::R; + #[doc = "Writer for register intr_clear"] + pub type W = crate::W; + #[doc = "Register intr_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_CLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + } + } + #[doc = "FFT status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"] + pub type STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS; + #[doc = "`read()` method returns [status::R](status::R) reader structure"] + impl crate::Readable for STATUS {} + #[doc = "`write(|w| ..)` method takes [status::W](status::W) writer structure"] + impl crate::Writable for STATUS {} + #[doc = "FFT status register"] + pub mod status { + #[doc = "Reader of register status"] + pub type R = crate::R; + #[doc = "Writer for register status"] + pub type W = crate::W; + #[doc = "Register status `reset()`'s with value 0"] + impl crate::ResetValue for super::STATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + } + } + #[doc = "FFT status raw\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status_raw](status_raw) module"] + pub type STATUS_RAW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS_RAW; + #[doc = "`read()` method returns [status_raw::R](status_raw::R) reader structure"] + impl crate::Readable for STATUS_RAW {} + #[doc = "`write(|w| ..)` method takes [status_raw::W](status_raw::W) writer structure"] + impl crate::Writable for STATUS_RAW {} + #[doc = "FFT status raw"] + pub mod status_raw { + #[doc = "Reader of register status_raw"] + pub type R = crate::R; + #[doc = "Writer for register status_raw"] + pub type W = crate::W; + #[doc = "Register status_raw `reset()`'s with value 0"] + impl crate::ResetValue for super::STATUS_RAW { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `fft_done`"] + pub type FFT_DONE_R = crate::R; + #[doc = "Write proxy for field `fft_done`"] + pub struct FFT_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `fft_work`"] + pub type FFT_WORK_R = crate::R; + #[doc = "Write proxy for field `fft_work`"] + pub struct FFT_WORK_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_WORK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&self) -> FFT_DONE_R { + FFT_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - FFT work"] + #[inline(always)] + pub fn fft_work(&self) -> FFT_WORK_R { + FFT_WORK_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FFT done"] + #[inline(always)] + pub fn fft_done(&mut self) -> FFT_DONE_W { + FFT_DONE_W { w: self } + } + #[doc = "Bit 1 - FFT work"] + #[inline(always)] + pub fn fft_work(&mut self) -> FFT_WORK_W { + FFT_WORK_W { w: self } + } + } + } + #[doc = "FFT output FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [output_fifo](output_fifo) module"] + pub type OUTPUT_FIFO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUTPUT_FIFO; + #[doc = "`read()` method returns [output_fifo::R](output_fifo::R) reader structure"] + impl crate::Readable for OUTPUT_FIFO {} + #[doc = "`write(|w| ..)` method takes [output_fifo::W](output_fifo::W) writer structure"] + impl crate::Writable for OUTPUT_FIFO {} + #[doc = "FFT output FIFO"] + pub mod output_fifo { + #[doc = "Reader of register output_fifo"] + pub type R = crate::R; + #[doc = "Writer for register output_fifo"] + pub type W = crate::W; + #[doc = "Register output_fifo `reset()`'s with value 0"] + impl crate::ResetValue for super::OUTPUT_FIFO { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + 0x5000_0000 as *const _ + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*DMAC::ptr() } + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - ID Register"] + pub id: ID, + #[doc = "0x08 - COMPVER Register"] + pub compver: COMPVER, + #[doc = "0x10 - Configure Register"] + pub cfg: CFG, + #[doc = "0x18 - Channel Enable Register"] + pub chen: CHEN, + _reserved4: [u8; 16usize], + #[doc = "0x30 - Interrupt Status Register"] + pub intstatus: INTSTATUS, + #[doc = "0x38 - Common Interrupt Clear Register"] + pub com_intclear: COM_INTCLEAR, + #[doc = "0x40 - Common Interrupt Status Enable Register"] + pub com_intstatus_en: COM_INTSTATUS_EN, + #[doc = "0x48 - Common Interrupt Signal Enable Register"] + pub com_intsignal_en: COM_INTSIGNAL_EN, + #[doc = "0x50 - Common Interrupt Status"] + pub com_intstatus: COM_INTSTATUS, + #[doc = "0x58 - Reset register"] + pub reset: RESET, + _reserved10: [u8; 160usize], + #[doc = "0x100 - Channel configuration"] + pub channel: [CHANNEL; 6], + } + #[doc = r"Register block"] + #[repr(C)] + pub struct CHANNEL { + #[doc = "0x00 - SAR Address Register"] + pub sar: self::channel::SAR, + #[doc = "0x08 - DAR Address Register"] + pub dar: self::channel::DAR, + #[doc = "0x10 - Block Transfer Size Register"] + pub block_ts: self::channel::BLOCK_TS, + #[doc = "0x18 - Control Register"] + pub ctl: self::channel::CTL, + #[doc = "0x20 - Configure Register"] + pub cfg: self::channel::CFG, + #[doc = "0x28 - Linked List Pointer register"] + pub llp: self::channel::LLP, + #[doc = "0x30 - Channel Status Register"] + pub status: self::channel::STATUS, + #[doc = "0x38 - Channel Software handshake Source Register"] + pub swhssrc: self::channel::SWHSSRC, + #[doc = "0x40 - Channel Software handshake Destination Register"] + pub swhsdst: self::channel::SWHSDST, + #[doc = "0x48 - Channel Block Transfer Resume Request Register"] + pub blk_tfr: self::channel::BLK_TFR, + #[doc = "0x50 - Channel AXI ID Register"] + pub axi_id: self::channel::AXI_ID, + #[doc = "0x58 - AXI QOS Register"] + pub axi_qos: self::channel::AXI_QOS, + _reserved12: [u8; 32usize], + #[doc = "0x80 - Interrupt Status Enable Register"] + pub intstatus_en: self::channel::INTSTATUS_EN, + #[doc = "0x88 - Channel Interrupt Status Register"] + pub intstatus: self::channel::INTSTATUS, + #[doc = "0x90 - Interrupt Signal Enable Register"] + pub intsignal_en: self::channel::INTSIGNAL_EN, + #[doc = "0x98 - Interrupt Clear Register"] + pub intclear: self::channel::INTCLEAR, + _reserved16: [u8; 88usize], + #[doc = "0xf8 - Padding to make structure size 256 bytes so that channels\\[\\] +is an array"] + pub _reserved: self::channel::_RESERVED, + } + #[doc = r"Register block"] + #[doc = "Channel configuration"] + pub mod channel { + #[doc = "SAR Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sar](sar) module"] + pub type SAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAR; + #[doc = "`read()` method returns [sar::R](sar::R) reader structure"] + impl crate::Readable for SAR {} + #[doc = "`write(|w| ..)` method takes [sar::W](sar::W) writer structure"] + impl crate::Writable for SAR {} + #[doc = "SAR Address Register"] + pub mod sar { + #[doc = "Reader of register sar"] + pub type R = crate::R; + #[doc = "Writer for register sar"] + pub type W = crate::W; + #[doc = "Register sar `reset()`'s with value 0"] + impl crate::ResetValue for super::SAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DAR Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dar](dar) module"] + pub type DAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DAR; + #[doc = "`read()` method returns [dar::R](dar::R) reader structure"] + impl crate::Readable for DAR {} + #[doc = "`write(|w| ..)` method takes [dar::W](dar::W) writer structure"] + impl crate::Writable for DAR {} + #[doc = "DAR Address Register"] + pub mod dar { + #[doc = "Reader of register dar"] + pub type R = crate::R; + #[doc = "Writer for register dar"] + pub type W = crate::W; + #[doc = "Register dar `reset()`'s with value 0"] + impl crate::ResetValue for super::DAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Block Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [block_ts](block_ts) module"] + pub type BLOCK_TS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BLOCK_TS; + #[doc = "`read()` method returns [block_ts::R](block_ts::R) reader structure"] + impl crate::Readable for BLOCK_TS {} + #[doc = "`write(|w| ..)` method takes [block_ts::W](block_ts::W) writer structure"] + impl crate::Writable for BLOCK_TS {} + #[doc = "Block Transfer Size Register"] + pub mod block_ts { + #[doc = "Reader of register block_ts"] + pub type R = crate::R; + #[doc = "Writer for register block_ts"] + pub type W = crate::W; + #[doc = "Register block_ts `reset()`'s with value 0"] + impl crate::ResetValue for super::BLOCK_TS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_ts`"] + pub type BLOCK_TS_R = crate::R; + #[doc = "Write proxy for field `block_ts`"] + pub struct BLOCK_TS_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u64) & 0x003f_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:21 - Block transfer size"] + #[inline(always)] + pub fn block_ts(&self) -> BLOCK_TS_R { + BLOCK_TS_R::new((self.bits & 0x003f_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:21 - Block transfer size"] + #[inline(always)] + pub fn block_ts(&mut self) -> BLOCK_TS_W { + BLOCK_TS_W { w: self } + } + } + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](ctl) module"] + pub type CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTL; + #[doc = "`read()` method returns [ctl::R](ctl::R) reader structure"] + impl crate::Readable for CTL {} + #[doc = "`write(|w| ..)` method takes [ctl::W](ctl::W) writer structure"] + impl crate::Writable for CTL {} + #[doc = "Control Register"] + pub mod ctl { + #[doc = "Reader of register ctl"] + pub type R = crate::R; + #[doc = "Writer for register ctl"] + pub type W = crate::W; + #[doc = "Register ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::CTL { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Source master select\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum SMS_A { + #[doc = "0: AXI master 1"] + AXI_MASTER_1 = 0, + #[doc = "1: AXI master 2"] + AXI_MASTER_2 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: SMS_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `sms`"] + pub type SMS_R = crate::R; + impl SMS_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SMS_A { + match self.bits { + false => SMS_A::AXI_MASTER_1, + true => SMS_A::AXI_MASTER_2, + } + } + #[doc = "Checks if the value of the field is `AXI_MASTER_1`"] + #[inline(always)] + pub fn is_axi_master_1(&self) -> bool { + *self == SMS_A::AXI_MASTER_1 + } + #[doc = "Checks if the value of the field is `AXI_MASTER_2`"] + #[inline(always)] + pub fn is_axi_master_2(&self) -> bool { + *self == SMS_A::AXI_MASTER_2 + } + } + #[doc = "Write proxy for field `sms`"] + pub struct SMS_W<'a> { + w: &'a mut W, + } + impl<'a> SMS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SMS_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "AXI master 1"] + #[inline(always)] + pub fn axi_master_1(self) -> &'a mut W { + self.variant(SMS_A::AXI_MASTER_1) + } + #[doc = "AXI master 2"] + #[inline(always)] + pub fn axi_master_2(self) -> &'a mut W { + self.variant(SMS_A::AXI_MASTER_2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Destination master select"] + pub type DMS_A = SMS_A; + #[doc = "Reader of field `dms`"] + pub type DMS_R = crate::R; + #[doc = "Write proxy for field `dms`"] + pub struct DMS_W<'a> { + w: &'a mut W, + } + impl<'a> DMS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMS_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "AXI master 1"] + #[inline(always)] + pub fn axi_master_1(self) -> &'a mut W { + self.variant(DMS_A::AXI_MASTER_1) + } + #[doc = "AXI master 2"] + #[inline(always)] + pub fn axi_master_2(self) -> &'a mut W { + self.variant(DMS_A::AXI_MASTER_2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Source address increment\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum SINC_A { + #[doc = "0: Increment address"] + INCREMENT = 0, + #[doc = "1: Don't increment address"] + NOCHANGE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: SINC_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `sinc`"] + pub type SINC_R = crate::R; + impl SINC_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SINC_A { + match self.bits { + false => SINC_A::INCREMENT, + true => SINC_A::NOCHANGE, + } + } + #[doc = "Checks if the value of the field is `INCREMENT`"] + #[inline(always)] + pub fn is_increment(&self) -> bool { + *self == SINC_A::INCREMENT + } + #[doc = "Checks if the value of the field is `NOCHANGE`"] + #[inline(always)] + pub fn is_nochange(&self) -> bool { + *self == SINC_A::NOCHANGE + } + } + #[doc = "Write proxy for field `sinc`"] + pub struct SINC_W<'a> { + w: &'a mut W, + } + impl<'a> SINC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SINC_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Increment address"] + #[inline(always)] + pub fn increment(self) -> &'a mut W { + self.variant(SINC_A::INCREMENT) + } + #[doc = "Don't increment address"] + #[inline(always)] + pub fn nochange(self) -> &'a mut W { + self.variant(SINC_A::NOCHANGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Destination address increment"] + pub type DINC_A = SINC_A; + #[doc = "Reader of field `dinc`"] + pub type DINC_R = crate::R; + #[doc = "Write proxy for field `dinc`"] + pub struct DINC_W<'a> { + w: &'a mut W, + } + impl<'a> DINC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DINC_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Increment address"] + #[inline(always)] + pub fn increment(self) -> &'a mut W { + self.variant(DINC_A::INCREMENT) + } + #[doc = "Don't increment address"] + #[inline(always)] + pub fn nochange(self) -> &'a mut W { + self.variant(DINC_A::NOCHANGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Source transfer width\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SRC_TR_WIDTH_A { + #[doc = "0: 8 bits"] + WIDTH_8 = 0, + #[doc = "1: 16 bits"] + WIDTH_16 = 1, + #[doc = "2: 32 bits"] + WIDTH_32 = 2, + #[doc = "3: 64 bits"] + WIDTH_64 = 3, + #[doc = "4: 128 bits"] + WIDTH_128 = 4, + #[doc = "5: 256 bits"] + WIDTH_256 = 5, + #[doc = "6: 512 bits"] + WIDTH_512 = 6, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SRC_TR_WIDTH_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `src_tr_width`"] + pub type SRC_TR_WIDTH_R = crate::R; + impl SRC_TR_WIDTH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(SRC_TR_WIDTH_A::WIDTH_8), + 1 => Val(SRC_TR_WIDTH_A::WIDTH_16), + 2 => Val(SRC_TR_WIDTH_A::WIDTH_32), + 3 => Val(SRC_TR_WIDTH_A::WIDTH_64), + 4 => Val(SRC_TR_WIDTH_A::WIDTH_128), + 5 => Val(SRC_TR_WIDTH_A::WIDTH_256), + 6 => Val(SRC_TR_WIDTH_A::WIDTH_512), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `WIDTH_8`"] + #[inline(always)] + pub fn is_width_8(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_8 + } + #[doc = "Checks if the value of the field is `WIDTH_16`"] + #[inline(always)] + pub fn is_width_16(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_16 + } + #[doc = "Checks if the value of the field is `WIDTH_32`"] + #[inline(always)] + pub fn is_width_32(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_32 + } + #[doc = "Checks if the value of the field is `WIDTH_64`"] + #[inline(always)] + pub fn is_width_64(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_64 + } + #[doc = "Checks if the value of the field is `WIDTH_128`"] + #[inline(always)] + pub fn is_width_128(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_128 + } + #[doc = "Checks if the value of the field is `WIDTH_256`"] + #[inline(always)] + pub fn is_width_256(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_256 + } + #[doc = "Checks if the value of the field is `WIDTH_512`"] + #[inline(always)] + pub fn is_width_512(&self) -> bool { + *self == SRC_TR_WIDTH_A::WIDTH_512 + } + } + #[doc = "Write proxy for field `src_tr_width`"] + pub struct SRC_TR_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TR_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_TR_WIDTH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn width_8(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_8) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn width_16(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_16) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn width_32(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_32) + } + #[doc = "64 bits"] + #[inline(always)] + pub fn width_64(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_64) + } + #[doc = "128 bits"] + #[inline(always)] + pub fn width_128(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_128) + } + #[doc = "256 bits"] + #[inline(always)] + pub fn width_256(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_256) + } + #[doc = "512 bits"] + #[inline(always)] + pub fn width_512(self) -> &'a mut W { + self.variant(SRC_TR_WIDTH_A::WIDTH_512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u64) & 0x07) << 8); + self.w + } + } + #[doc = "Destination transfer width"] + pub type DST_TR_WIDTH_A = SRC_TR_WIDTH_A; + #[doc = "Reader of field `dst_tr_width`"] + pub type DST_TR_WIDTH_R = crate::R; + #[doc = "Write proxy for field `dst_tr_width`"] + pub struct DST_TR_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TR_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_TR_WIDTH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn width_8(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_8) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn width_16(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_16) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn width_32(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_32) + } + #[doc = "64 bits"] + #[inline(always)] + pub fn width_64(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_64) + } + #[doc = "128 bits"] + #[inline(always)] + pub fn width_128(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_128) + } + #[doc = "256 bits"] + #[inline(always)] + pub fn width_256(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_256) + } + #[doc = "512 bits"] + #[inline(always)] + pub fn width_512(self) -> &'a mut W { + self.variant(DST_TR_WIDTH_A::WIDTH_512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 11)) | (((value as u64) & 0x07) << 11); + self.w + } + } + #[doc = "Source burst transaction length\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SRC_MSIZE_A { + #[doc = "0: 1 data item"] + LENGTH_1 = 0, + #[doc = "1: 4 data items"] + LENGTH_4 = 1, + #[doc = "2: 8 data items"] + LENGTH_8 = 2, + #[doc = "3: 16 data items"] + LENGTH_16 = 3, + #[doc = "4: 32 data items"] + LENGTH_32 = 4, + #[doc = "5: 64 data items"] + LENGTH_64 = 5, + #[doc = "6: 128 data items"] + LENGTH_128 = 6, + #[doc = "7: 256 data items"] + LENGTH_256 = 7, + #[doc = "8: 512 data items"] + LENGTH_512 = 8, + #[doc = "9: 1024 data items"] + LENGTH_1024 = 9, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SRC_MSIZE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `src_msize`"] + pub type SRC_MSIZE_R = crate::R; + impl SRC_MSIZE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(SRC_MSIZE_A::LENGTH_1), + 1 => Val(SRC_MSIZE_A::LENGTH_4), + 2 => Val(SRC_MSIZE_A::LENGTH_8), + 3 => Val(SRC_MSIZE_A::LENGTH_16), + 4 => Val(SRC_MSIZE_A::LENGTH_32), + 5 => Val(SRC_MSIZE_A::LENGTH_64), + 6 => Val(SRC_MSIZE_A::LENGTH_128), + 7 => Val(SRC_MSIZE_A::LENGTH_256), + 8 => Val(SRC_MSIZE_A::LENGTH_512), + 9 => Val(SRC_MSIZE_A::LENGTH_1024), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `LENGTH_1`"] + #[inline(always)] + pub fn is_length_1(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_1 + } + #[doc = "Checks if the value of the field is `LENGTH_4`"] + #[inline(always)] + pub fn is_length_4(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_4 + } + #[doc = "Checks if the value of the field is `LENGTH_8`"] + #[inline(always)] + pub fn is_length_8(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_8 + } + #[doc = "Checks if the value of the field is `LENGTH_16`"] + #[inline(always)] + pub fn is_length_16(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_16 + } + #[doc = "Checks if the value of the field is `LENGTH_32`"] + #[inline(always)] + pub fn is_length_32(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_32 + } + #[doc = "Checks if the value of the field is `LENGTH_64`"] + #[inline(always)] + pub fn is_length_64(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_64 + } + #[doc = "Checks if the value of the field is `LENGTH_128`"] + #[inline(always)] + pub fn is_length_128(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_128 + } + #[doc = "Checks if the value of the field is `LENGTH_256`"] + #[inline(always)] + pub fn is_length_256(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_256 + } + #[doc = "Checks if the value of the field is `LENGTH_512`"] + #[inline(always)] + pub fn is_length_512(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_512 + } + #[doc = "Checks if the value of the field is `LENGTH_1024`"] + #[inline(always)] + pub fn is_length_1024(&self) -> bool { + *self == SRC_MSIZE_A::LENGTH_1024 + } + } + #[doc = "Write proxy for field `src_msize`"] + pub struct SRC_MSIZE_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_MSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_MSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 data item"] + #[inline(always)] + pub fn length_1(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_1) + } + #[doc = "4 data items"] + #[inline(always)] + pub fn length_4(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_4) + } + #[doc = "8 data items"] + #[inline(always)] + pub fn length_8(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_8) + } + #[doc = "16 data items"] + #[inline(always)] + pub fn length_16(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_16) + } + #[doc = "32 data items"] + #[inline(always)] + pub fn length_32(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_32) + } + #[doc = "64 data items"] + #[inline(always)] + pub fn length_64(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_64) + } + #[doc = "128 data items"] + #[inline(always)] + pub fn length_128(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_128) + } + #[doc = "256 data items"] + #[inline(always)] + pub fn length_256(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_256) + } + #[doc = "512 data items"] + #[inline(always)] + pub fn length_512(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_512) + } + #[doc = "1024 data items"] + #[inline(always)] + pub fn length_1024(self) -> &'a mut W { + self.variant(SRC_MSIZE_A::LENGTH_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 14)) | (((value as u64) & 0x0f) << 14); + self.w + } + } + #[doc = "Destination burst transaction length"] + pub type DST_MSIZE_A = SRC_MSIZE_A; + #[doc = "Reader of field `dst_msize`"] + pub type DST_MSIZE_R = crate::R; + #[doc = "Write proxy for field `dst_msize`"] + pub struct DST_MSIZE_W<'a> { + w: &'a mut W, + } + impl<'a> DST_MSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_MSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 data item"] + #[inline(always)] + pub fn length_1(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_1) + } + #[doc = "4 data items"] + #[inline(always)] + pub fn length_4(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_4) + } + #[doc = "8 data items"] + #[inline(always)] + pub fn length_8(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_8) + } + #[doc = "16 data items"] + #[inline(always)] + pub fn length_16(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_16) + } + #[doc = "32 data items"] + #[inline(always)] + pub fn length_32(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_32) + } + #[doc = "64 data items"] + #[inline(always)] + pub fn length_64(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_64) + } + #[doc = "128 data items"] + #[inline(always)] + pub fn length_128(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_128) + } + #[doc = "256 data items"] + #[inline(always)] + pub fn length_256(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_256) + } + #[doc = "512 data items"] + #[inline(always)] + pub fn length_512(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_512) + } + #[doc = "1024 data items"] + #[inline(always)] + pub fn length_1024(self) -> &'a mut W { + self.variant(DST_MSIZE_A::LENGTH_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u64) & 0x0f) << 18); + self.w + } + } + #[doc = "Reader of field `nonposted_lastwrite_en`"] + pub type NONPOSTED_LASTWRITE_EN_R = crate::R; + #[doc = "Write proxy for field `nonposted_lastwrite_en`"] + pub struct NONPOSTED_LASTWRITE_EN_W<'a> { + w: &'a mut W, + } + impl<'a> NONPOSTED_LASTWRITE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u64) & 0x01) << 30); + self.w + } + } + #[doc = "Reader of field `arlen_en`"] + pub type ARLEN_EN_R = crate::R; + #[doc = "Write proxy for field `arlen_en`"] + pub struct ARLEN_EN_W<'a> { + w: &'a mut W, + } + impl<'a> ARLEN_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 38)) | (((value as u64) & 0x01) << 38); + self.w + } + } + #[doc = "Reader of field `arlen`"] + pub type ARLEN_R = crate::R; + #[doc = "Write proxy for field `arlen`"] + pub struct ARLEN_W<'a> { + w: &'a mut W, + } + impl<'a> ARLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 39)) | (((value as u64) & 0xff) << 39); + self.w + } + } + #[doc = "Reader of field `awlen_en`"] + pub type AWLEN_EN_R = crate::R; + #[doc = "Write proxy for field `awlen_en`"] + pub struct AWLEN_EN_W<'a> { + w: &'a mut W, + } + impl<'a> AWLEN_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 47)) | (((value as u64) & 0x01) << 47); + self.w + } + } + #[doc = "Reader of field `awlen`"] + pub type AWLEN_R = crate::R; + #[doc = "Write proxy for field `awlen`"] + pub struct AWLEN_W<'a> { + w: &'a mut W, + } + impl<'a> AWLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 48)) | (((value as u64) & 0xff) << 48); + self.w + } + } + #[doc = "Reader of field `src_stat_en`"] + pub type SRC_STAT_EN_R = crate::R; + #[doc = "Write proxy for field `src_stat_en`"] + pub struct SRC_STAT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_STAT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 56)) | (((value as u64) & 0x01) << 56); + self.w + } + } + #[doc = "Reader of field `dst_stat_en`"] + pub type DST_STAT_EN_R = crate::R; + #[doc = "Write proxy for field `dst_stat_en`"] + pub struct DST_STAT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DST_STAT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 57)) | (((value as u64) & 0x01) << 57); + self.w + } + } + #[doc = "Reader of field `ioc_blktfr`"] + pub type IOC_BLKTFR_R = crate::R; + #[doc = "Write proxy for field `ioc_blktfr`"] + pub struct IOC_BLKTFR_W<'a> { + w: &'a mut W, + } + impl<'a> IOC_BLKTFR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 58)) | (((value as u64) & 0x01) << 58); + self.w + } + } + #[doc = "Reader of field `shadowreg_or_lli_last`"] + pub type SHADOWREG_OR_LLI_LAST_R = crate::R; + #[doc = "Write proxy for field `shadowreg_or_lli_last`"] + pub struct SHADOWREG_OR_LLI_LAST_W<'a> { + w: &'a mut W, + } + impl<'a> SHADOWREG_OR_LLI_LAST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 62)) | (((value as u64) & 0x01) << 62); + self.w + } + } + #[doc = "Reader of field `shadowreg_or_lli_valid`"] + pub type SHADOWREG_OR_LLI_VALID_R = crate::R; + #[doc = "Write proxy for field `shadowreg_or_lli_valid`"] + pub struct SHADOWREG_OR_LLI_VALID_W<'a> { + w: &'a mut W, + } + impl<'a> SHADOWREG_OR_LLI_VALID_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 63)) | (((value as u64) & 0x01) << 63); + self.w + } + } + impl R { + #[doc = "Bit 0 - Source master select"] + #[inline(always)] + pub fn sms(&self) -> SMS_R { + SMS_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Destination master select"] + #[inline(always)] + pub fn dms(&self) -> DMS_R { + DMS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Source address increment"] + #[inline(always)] + pub fn sinc(&self) -> SINC_R { + SINC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination address increment"] + #[inline(always)] + pub fn dinc(&self) -> DINC_R { + DINC_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Source transfer width"] + #[inline(always)] + pub fn src_tr_width(&self) -> SRC_TR_WIDTH_R { + SRC_TR_WIDTH_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 11:13 - Destination transfer width"] + #[inline(always)] + pub fn dst_tr_width(&self) -> DST_TR_WIDTH_R { + DST_TR_WIDTH_R::new(((self.bits >> 11) & 0x07) as u8) + } + #[doc = "Bits 14:17 - Source burst transaction length"] + #[inline(always)] + pub fn src_msize(&self) -> SRC_MSIZE_R { + SRC_MSIZE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - Destination burst transaction length"] + #[inline(always)] + pub fn dst_msize(&self) -> DST_MSIZE_R { + DST_MSIZE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 30 - Non Posted Last Write Enable (posted writes may be used till the end of the block)"] + #[inline(always)] + pub fn nonposted_lastwrite_en(&self) -> NONPOSTED_LASTWRITE_EN_R { + NONPOSTED_LASTWRITE_EN_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 38 - Source burst length enable"] + #[inline(always)] + pub fn arlen_en(&self) -> ARLEN_EN_R { + ARLEN_EN_R::new(((self.bits >> 38) & 0x01) != 0) + } + #[doc = "Bits 39:46 - Source burst length"] + #[inline(always)] + pub fn arlen(&self) -> ARLEN_R { + ARLEN_R::new(((self.bits >> 39) & 0xff) as u8) + } + #[doc = "Bit 47 - Destination burst length enable"] + #[inline(always)] + pub fn awlen_en(&self) -> AWLEN_EN_R { + AWLEN_EN_R::new(((self.bits >> 47) & 0x01) != 0) + } + #[doc = "Bits 48:55 - Destination burst length"] + #[inline(always)] + pub fn awlen(&self) -> AWLEN_R { + AWLEN_R::new(((self.bits >> 48) & 0xff) as u8) + } + #[doc = "Bit 56 - Source status enable"] + #[inline(always)] + pub fn src_stat_en(&self) -> SRC_STAT_EN_R { + SRC_STAT_EN_R::new(((self.bits >> 56) & 0x01) != 0) + } + #[doc = "Bit 57 - Destination status enable"] + #[inline(always)] + pub fn dst_stat_en(&self) -> DST_STAT_EN_R { + DST_STAT_EN_R::new(((self.bits >> 57) & 0x01) != 0) + } + #[doc = "Bit 58 - Interrupt completion of block transfer"] + #[inline(always)] + pub fn ioc_blktfr(&self) -> IOC_BLKTFR_R { + IOC_BLKTFR_R::new(((self.bits >> 58) & 0x01) != 0) + } + #[doc = "Bit 62 - Last shadow linked list item (indicates shadowreg/LLI content is the last one)"] + #[inline(always)] + pub fn shadowreg_or_lli_last(&self) -> SHADOWREG_OR_LLI_LAST_R { + SHADOWREG_OR_LLI_LAST_R::new(((self.bits >> 62) & 0x01) != 0) + } + #[doc = "Bit 63 - last shadow linked list item valid (indicate shadowreg/LLI content is valid)"] + #[inline(always)] + pub fn shadowreg_or_lli_valid(&self) -> SHADOWREG_OR_LLI_VALID_R { + SHADOWREG_OR_LLI_VALID_R::new(((self.bits >> 63) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Source master select"] + #[inline(always)] + pub fn sms(&mut self) -> SMS_W { + SMS_W { w: self } + } + #[doc = "Bit 2 - Destination master select"] + #[inline(always)] + pub fn dms(&mut self) -> DMS_W { + DMS_W { w: self } + } + #[doc = "Bit 4 - Source address increment"] + #[inline(always)] + pub fn sinc(&mut self) -> SINC_W { + SINC_W { w: self } + } + #[doc = "Bit 6 - Destination address increment"] + #[inline(always)] + pub fn dinc(&mut self) -> DINC_W { + DINC_W { w: self } + } + #[doc = "Bits 8:10 - Source transfer width"] + #[inline(always)] + pub fn src_tr_width(&mut self) -> SRC_TR_WIDTH_W { + SRC_TR_WIDTH_W { w: self } + } + #[doc = "Bits 11:13 - Destination transfer width"] + #[inline(always)] + pub fn dst_tr_width(&mut self) -> DST_TR_WIDTH_W { + DST_TR_WIDTH_W { w: self } + } + #[doc = "Bits 14:17 - Source burst transaction length"] + #[inline(always)] + pub fn src_msize(&mut self) -> SRC_MSIZE_W { + SRC_MSIZE_W { w: self } + } + #[doc = "Bits 18:21 - Destination burst transaction length"] + #[inline(always)] + pub fn dst_msize(&mut self) -> DST_MSIZE_W { + DST_MSIZE_W { w: self } + } + #[doc = "Bit 30 - Non Posted Last Write Enable (posted writes may be used till the end of the block)"] + #[inline(always)] + pub fn nonposted_lastwrite_en(&mut self) -> NONPOSTED_LASTWRITE_EN_W { + NONPOSTED_LASTWRITE_EN_W { w: self } + } + #[doc = "Bit 38 - Source burst length enable"] + #[inline(always)] + pub fn arlen_en(&mut self) -> ARLEN_EN_W { + ARLEN_EN_W { w: self } + } + #[doc = "Bits 39:46 - Source burst length"] + #[inline(always)] + pub fn arlen(&mut self) -> ARLEN_W { + ARLEN_W { w: self } + } + #[doc = "Bit 47 - Destination burst length enable"] + #[inline(always)] + pub fn awlen_en(&mut self) -> AWLEN_EN_W { + AWLEN_EN_W { w: self } + } + #[doc = "Bits 48:55 - Destination burst length"] + #[inline(always)] + pub fn awlen(&mut self) -> AWLEN_W { + AWLEN_W { w: self } + } + #[doc = "Bit 56 - Source status enable"] + #[inline(always)] + pub fn src_stat_en(&mut self) -> SRC_STAT_EN_W { + SRC_STAT_EN_W { w: self } + } + #[doc = "Bit 57 - Destination status enable"] + #[inline(always)] + pub fn dst_stat_en(&mut self) -> DST_STAT_EN_W { + DST_STAT_EN_W { w: self } + } + #[doc = "Bit 58 - Interrupt completion of block transfer"] + #[inline(always)] + pub fn ioc_blktfr(&mut self) -> IOC_BLKTFR_W { + IOC_BLKTFR_W { w: self } + } + #[doc = "Bit 62 - Last shadow linked list item (indicates shadowreg/LLI content is the last one)"] + #[inline(always)] + pub fn shadowreg_or_lli_last(&mut self) -> SHADOWREG_OR_LLI_LAST_W { + SHADOWREG_OR_LLI_LAST_W { w: self } + } + #[doc = "Bit 63 - last shadow linked list item valid (indicate shadowreg/LLI content is valid)"] + #[inline(always)] + pub fn shadowreg_or_lli_valid(&mut self) -> SHADOWREG_OR_LLI_VALID_W { + SHADOWREG_OR_LLI_VALID_W { w: self } + } + } + } + #[doc = "Configure Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] + pub type CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CFG; + #[doc = "`read()` method returns [cfg::R](cfg::R) reader structure"] + impl crate::Readable for CFG {} + #[doc = "`write(|w| ..)` method takes [cfg::W](cfg::W) writer structure"] + impl crate::Writable for CFG {} + #[doc = "Configure Register"] + pub mod cfg { + #[doc = "Reader of register cfg"] + pub type R = crate::R; + #[doc = "Writer for register cfg"] + pub type W = crate::W; + #[doc = "Register cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CFG { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Source multi-block transfer type\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SRC_MULTBLK_TYPE_A { + #[doc = "0: Continuous multi-block type"] + CONTIGUOUS = 0, + #[doc = "1: Reload multi-block type"] + RELOAD = 1, + #[doc = "2: Shadow register based multi-block type"] + SHADOW_REGISTER = 2, + #[doc = "3: Linked list based multi-block type"] + LINKED_LIST = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SRC_MULTBLK_TYPE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `src_multblk_type`"] + pub type SRC_MULTBLK_TYPE_R = crate::R; + impl SRC_MULTBLK_TYPE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_MULTBLK_TYPE_A { + match self.bits { + 0 => SRC_MULTBLK_TYPE_A::CONTIGUOUS, + 1 => SRC_MULTBLK_TYPE_A::RELOAD, + 2 => SRC_MULTBLK_TYPE_A::SHADOW_REGISTER, + 3 => SRC_MULTBLK_TYPE_A::LINKED_LIST, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CONTIGUOUS`"] + #[inline(always)] + pub fn is_contiguous(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::CONTIGUOUS + } + #[doc = "Checks if the value of the field is `RELOAD`"] + #[inline(always)] + pub fn is_reload(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::RELOAD + } + #[doc = "Checks if the value of the field is `SHADOW_REGISTER`"] + #[inline(always)] + pub fn is_shadow_register(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::SHADOW_REGISTER + } + #[doc = "Checks if the value of the field is `LINKED_LIST`"] + #[inline(always)] + pub fn is_linked_list(&self) -> bool { + *self == SRC_MULTBLK_TYPE_A::LINKED_LIST + } + } + #[doc = "Write proxy for field `src_multblk_type`"] + pub struct SRC_MULTBLK_TYPE_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_MULTBLK_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_MULTBLK_TYPE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Continuous multi-block type"] + #[inline(always)] + pub fn contiguous(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::CONTIGUOUS) + } + #[doc = "Reload multi-block type"] + #[inline(always)] + pub fn reload(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::RELOAD) + } + #[doc = "Shadow register based multi-block type"] + #[inline(always)] + pub fn shadow_register(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::SHADOW_REGISTER) + } + #[doc = "Linked list based multi-block type"] + #[inline(always)] + pub fn linked_list(self) -> &'a mut W { + self.variant(SRC_MULTBLK_TYPE_A::LINKED_LIST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u64) & 0x03); + self.w + } + } + #[doc = "Destination multi-block transfer type"] + pub type DST_MULTBLK_TYPE_A = SRC_MULTBLK_TYPE_A; + #[doc = "Reader of field `dst_multblk_type`"] + pub type DST_MULTBLK_TYPE_R = crate::R; + #[doc = "Write proxy for field `dst_multblk_type`"] + pub struct DST_MULTBLK_TYPE_W<'a> { + w: &'a mut W, + } + impl<'a> DST_MULTBLK_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_MULTBLK_TYPE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Continuous multi-block type"] + #[inline(always)] + pub fn contiguous(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::CONTIGUOUS) + } + #[doc = "Reload multi-block type"] + #[inline(always)] + pub fn reload(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::RELOAD) + } + #[doc = "Shadow register based multi-block type"] + #[inline(always)] + pub fn shadow_register(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::SHADOW_REGISTER) + } + #[doc = "Linked list based multi-block type"] + #[inline(always)] + pub fn linked_list(self) -> &'a mut W { + self.variant(DST_MULTBLK_TYPE_A::LINKED_LIST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u64) & 0x03) << 2); + self.w + } + } + #[doc = "Transfer type and flow control\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TT_FC_A { + #[doc = "0: Transfer memory to memory and flow controller is DMAC"] + MEM2MEM_DMA = 0, + #[doc = "1: Transfer memory to peripheral and flow controller is DMAC"] + MEM2PRF_DMA = 1, + #[doc = "2: Transfer peripheral to memory and flow controller is DMAC"] + PRF2MEM_DMA = 2, + #[doc = "3: Transfer peripheral to peripheral and flow controller is DMAC"] + PRF2PRF_DMA = 3, + #[doc = "4: Transfer peripheral to memory and flow controller is source peripheral"] + PRF2MEM_PRF = 4, + #[doc = "5: Transfer peripheral to peripheral and flow controller is source peripheral"] + PRF2PRF_SRCPRF = 5, + #[doc = "6: Transfer memory to peripheral and flow controller is destination peripheral"] + MEM2PRF_PRF = 6, + #[doc = "7: Transfer peripheral to peripheral and flow controller is destination peripheral"] + PRF2PRF_DSTPRF = 7, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TT_FC_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tt_fc`"] + pub type TT_FC_R = crate::R; + impl TT_FC_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TT_FC_A { + match self.bits { + 0 => TT_FC_A::MEM2MEM_DMA, + 1 => TT_FC_A::MEM2PRF_DMA, + 2 => TT_FC_A::PRF2MEM_DMA, + 3 => TT_FC_A::PRF2PRF_DMA, + 4 => TT_FC_A::PRF2MEM_PRF, + 5 => TT_FC_A::PRF2PRF_SRCPRF, + 6 => TT_FC_A::MEM2PRF_PRF, + 7 => TT_FC_A::PRF2PRF_DSTPRF, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `MEM2MEM_DMA`"] + #[inline(always)] + pub fn is_mem2mem_dma(&self) -> bool { + *self == TT_FC_A::MEM2MEM_DMA + } + #[doc = "Checks if the value of the field is `MEM2PRF_DMA`"] + #[inline(always)] + pub fn is_mem2prf_dma(&self) -> bool { + *self == TT_FC_A::MEM2PRF_DMA + } + #[doc = "Checks if the value of the field is `PRF2MEM_DMA`"] + #[inline(always)] + pub fn is_prf2mem_dma(&self) -> bool { + *self == TT_FC_A::PRF2MEM_DMA + } + #[doc = "Checks if the value of the field is `PRF2PRF_DMA`"] + #[inline(always)] + pub fn is_prf2prf_dma(&self) -> bool { + *self == TT_FC_A::PRF2PRF_DMA + } + #[doc = "Checks if the value of the field is `PRF2MEM_PRF`"] + #[inline(always)] + pub fn is_prf2mem_prf(&self) -> bool { + *self == TT_FC_A::PRF2MEM_PRF + } + #[doc = "Checks if the value of the field is `PRF2PRF_SRCPRF`"] + #[inline(always)] + pub fn is_prf2prf_srcprf(&self) -> bool { + *self == TT_FC_A::PRF2PRF_SRCPRF + } + #[doc = "Checks if the value of the field is `MEM2PRF_PRF`"] + #[inline(always)] + pub fn is_mem2prf_prf(&self) -> bool { + *self == TT_FC_A::MEM2PRF_PRF + } + #[doc = "Checks if the value of the field is `PRF2PRF_DSTPRF`"] + #[inline(always)] + pub fn is_prf2prf_dstprf(&self) -> bool { + *self == TT_FC_A::PRF2PRF_DSTPRF + } + } + #[doc = "Write proxy for field `tt_fc`"] + pub struct TT_FC_W<'a> { + w: &'a mut W, + } + impl<'a> TT_FC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TT_FC_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Transfer memory to memory and flow controller is DMAC"] + #[inline(always)] + pub fn mem2mem_dma(self) -> &'a mut W { + self.variant(TT_FC_A::MEM2MEM_DMA) + } + #[doc = "Transfer memory to peripheral and flow controller is DMAC"] + #[inline(always)] + pub fn mem2prf_dma(self) -> &'a mut W { + self.variant(TT_FC_A::MEM2PRF_DMA) + } + #[doc = "Transfer peripheral to memory and flow controller is DMAC"] + #[inline(always)] + pub fn prf2mem_dma(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2MEM_DMA) + } + #[doc = "Transfer peripheral to peripheral and flow controller is DMAC"] + #[inline(always)] + pub fn prf2prf_dma(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2PRF_DMA) + } + #[doc = "Transfer peripheral to memory and flow controller is source peripheral"] + #[inline(always)] + pub fn prf2mem_prf(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2MEM_PRF) + } + #[doc = "Transfer peripheral to peripheral and flow controller is source peripheral"] + #[inline(always)] + pub fn prf2prf_srcprf(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2PRF_SRCPRF) + } + #[doc = "Transfer memory to peripheral and flow controller is destination peripheral"] + #[inline(always)] + pub fn mem2prf_prf(self) -> &'a mut W { + self.variant(TT_FC_A::MEM2PRF_PRF) + } + #[doc = "Transfer peripheral to peripheral and flow controller is destination peripheral"] + #[inline(always)] + pub fn prf2prf_dstprf(self) -> &'a mut W { + self.variant(TT_FC_A::PRF2PRF_DSTPRF) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 32)) | (((value as u64) & 0x07) << 32); + self.w + } + } + #[doc = "Source software or hardware handshaking select\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum HS_SEL_SRC_A { + #[doc = "0: Hardware handshaking is used"] + HARDWARE = 0, + #[doc = "1: Software handshaking is used"] + SOFTWARE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: HS_SEL_SRC_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `hs_sel_src`"] + pub type HS_SEL_SRC_R = crate::R; + impl HS_SEL_SRC_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HS_SEL_SRC_A { + match self.bits { + false => HS_SEL_SRC_A::HARDWARE, + true => HS_SEL_SRC_A::SOFTWARE, + } + } + #[doc = "Checks if the value of the field is `HARDWARE`"] + #[inline(always)] + pub fn is_hardware(&self) -> bool { + *self == HS_SEL_SRC_A::HARDWARE + } + #[doc = "Checks if the value of the field is `SOFTWARE`"] + #[inline(always)] + pub fn is_software(&self) -> bool { + *self == HS_SEL_SRC_A::SOFTWARE + } + } + #[doc = "Write proxy for field `hs_sel_src`"] + pub struct HS_SEL_SRC_W<'a> { + w: &'a mut W, + } + impl<'a> HS_SEL_SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HS_SEL_SRC_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Hardware handshaking is used"] + #[inline(always)] + pub fn hardware(self) -> &'a mut W { + self.variant(HS_SEL_SRC_A::HARDWARE) + } + #[doc = "Software handshaking is used"] + #[inline(always)] + pub fn software(self) -> &'a mut W { + self.variant(HS_SEL_SRC_A::SOFTWARE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 35)) | (((value as u64) & 0x01) << 35); + self.w + } + } + #[doc = "Destination software or hardware handshaking select"] + pub type HS_SEL_DST_A = HS_SEL_SRC_A; + #[doc = "Reader of field `hs_sel_dst`"] + pub type HS_SEL_DST_R = crate::R; + #[doc = "Write proxy for field `hs_sel_dst`"] + pub struct HS_SEL_DST_W<'a> { + w: &'a mut W, + } + impl<'a> HS_SEL_DST_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HS_SEL_DST_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Hardware handshaking is used"] + #[inline(always)] + pub fn hardware(self) -> &'a mut W { + self.variant(HS_SEL_DST_A::HARDWARE) + } + #[doc = "Software handshaking is used"] + #[inline(always)] + pub fn software(self) -> &'a mut W { + self.variant(HS_SEL_DST_A::SOFTWARE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 36)) | (((value as u64) & 0x01) << 36); + self.w + } + } + #[doc = "Source hardware handshaking interface polarity\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum SRC_HWHS_POL_A { + #[doc = "0: Active high"] + ACTIVE_HIGH = 0, + #[doc = "1: Active low"] + ACTIVE_LOW = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: SRC_HWHS_POL_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `src_hwhs_pol`"] + pub type SRC_HWHS_POL_R = crate::R; + impl SRC_HWHS_POL_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_HWHS_POL_A { + match self.bits { + false => SRC_HWHS_POL_A::ACTIVE_HIGH, + true => SRC_HWHS_POL_A::ACTIVE_LOW, + } + } + #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == SRC_HWHS_POL_A::ACTIVE_HIGH + } + #[doc = "Checks if the value of the field is `ACTIVE_LOW`"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == SRC_HWHS_POL_A::ACTIVE_LOW + } + } + #[doc = "Write proxy for field `src_hwhs_pol`"] + pub struct SRC_HWHS_POL_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_HWHS_POL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_HWHS_POL_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(SRC_HWHS_POL_A::ACTIVE_HIGH) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(SRC_HWHS_POL_A::ACTIVE_LOW) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 37)) | (((value as u64) & 0x01) << 37); + self.w + } + } + #[doc = "Destination hardware handshaking interface polarity"] + pub type DST_HWHS_POL_A = SRC_HWHS_POL_A; + #[doc = "Reader of field `dst_hwhs_pol`"] + pub type DST_HWHS_POL_R = crate::R; + #[doc = "Write proxy for field `dst_hwhs_pol`"] + pub struct DST_HWHS_POL_W<'a> { + w: &'a mut W, + } + impl<'a> DST_HWHS_POL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DST_HWHS_POL_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut W { + self.variant(DST_HWHS_POL_A::ACTIVE_HIGH) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut W { + self.variant(DST_HWHS_POL_A::ACTIVE_LOW) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 38)) | (((value as u64) & 0x01) << 38); + self.w + } + } + #[doc = "Reader of field `src_per`"] + pub type SRC_PER_R = crate::R; + #[doc = "Write proxy for field `src_per`"] + pub struct SRC_PER_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 39)) | (((value as u64) & 0x0f) << 39); + self.w + } + } + #[doc = "Reader of field `dst_per`"] + pub type DST_PER_R = crate::R; + #[doc = "Write proxy for field `dst_per`"] + pub struct DST_PER_W<'a> { + w: &'a mut W, + } + impl<'a> DST_PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 44)) | (((value as u64) & 0x0f) << 44); + self.w + } + } + #[doc = "Reader of field `ch_prior`"] + pub type CH_PRIOR_R = crate::R; + #[doc = "Write proxy for field `ch_prior`"] + pub struct CH_PRIOR_W<'a> { + w: &'a mut W, + } + impl<'a> CH_PRIOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 49)) | (((value as u64) & 0x07) << 49); + self.w + } + } + #[doc = "Reader of field `lock_ch`"] + pub type LOCK_CH_R = crate::R; + #[doc = "Write proxy for field `lock_ch`"] + pub struct LOCK_CH_W<'a> { + w: &'a mut W, + } + impl<'a> LOCK_CH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 52)) | (((value as u64) & 0x01) << 52); + self.w + } + } + #[doc = "Channel lock level\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum LOCK_CH_L_A { + #[doc = "0: Duration of channel is locked for entire DMA transfer"] + DMA_TRANSFER = 0, + #[doc = "1: Duration of channel is locked for current block transfer"] + BLOCK_TRANSFER = 1, + #[doc = "2: Duration of channel is locked for current transaction"] + TRANSACTION = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_CH_L_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `lock_ch_l`"] + pub type LOCK_CH_L_R = crate::R; + impl LOCK_CH_L_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(LOCK_CH_L_A::DMA_TRANSFER), + 1 => Val(LOCK_CH_L_A::BLOCK_TRANSFER), + 2 => Val(LOCK_CH_L_A::TRANSACTION), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `DMA_TRANSFER`"] + #[inline(always)] + pub fn is_dma_transfer(&self) -> bool { + *self == LOCK_CH_L_A::DMA_TRANSFER + } + #[doc = "Checks if the value of the field is `BLOCK_TRANSFER`"] + #[inline(always)] + pub fn is_block_transfer(&self) -> bool { + *self == LOCK_CH_L_A::BLOCK_TRANSFER + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + *self == LOCK_CH_L_A::TRANSACTION + } + } + #[doc = "Write proxy for field `lock_ch_l`"] + pub struct LOCK_CH_L_W<'a> { + w: &'a mut W, + } + impl<'a> LOCK_CH_L_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LOCK_CH_L_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Duration of channel is locked for entire DMA transfer"] + #[inline(always)] + pub fn dma_transfer(self) -> &'a mut W { + self.variant(LOCK_CH_L_A::DMA_TRANSFER) + } + #[doc = "Duration of channel is locked for current block transfer"] + #[inline(always)] + pub fn block_transfer(self) -> &'a mut W { + self.variant(LOCK_CH_L_A::BLOCK_TRANSFER) + } + #[doc = "Duration of channel is locked for current transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(LOCK_CH_L_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 53)) | (((value as u64) & 0x03) << 53); + self.w + } + } + #[doc = "Reader of field `src_osr_lmt`"] + pub type SRC_OSR_LMT_R = crate::R; + #[doc = "Write proxy for field `src_osr_lmt`"] + pub struct SRC_OSR_LMT_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_OSR_LMT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 55)) | (((value as u64) & 0x0f) << 55); + self.w + } + } + #[doc = "Reader of field `dst_osr_lmt`"] + pub type DST_OSR_LMT_R = crate::R; + #[doc = "Write proxy for field `dst_osr_lmt`"] + pub struct DST_OSR_LMT_W<'a> { + w: &'a mut W, + } + impl<'a> DST_OSR_LMT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 59)) | (((value as u64) & 0x0f) << 59); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - Source multi-block transfer type"] + #[inline(always)] + pub fn src_multblk_type(&self) -> SRC_MULTBLK_TYPE_R { + SRC_MULTBLK_TYPE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Destination multi-block transfer type"] + #[inline(always)] + pub fn dst_multblk_type(&self) -> DST_MULTBLK_TYPE_R { + DST_MULTBLK_TYPE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 32:34 - Transfer type and flow control"] + #[inline(always)] + pub fn tt_fc(&self) -> TT_FC_R { + TT_FC_R::new(((self.bits >> 32) & 0x07) as u8) + } + #[doc = "Bit 35 - Source software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_src(&self) -> HS_SEL_SRC_R { + HS_SEL_SRC_R::new(((self.bits >> 35) & 0x01) != 0) + } + #[doc = "Bit 36 - Destination software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_dst(&self) -> HS_SEL_DST_R { + HS_SEL_DST_R::new(((self.bits >> 36) & 0x01) != 0) + } + #[doc = "Bit 37 - Source hardware handshaking interface polarity"] + #[inline(always)] + pub fn src_hwhs_pol(&self) -> SRC_HWHS_POL_R { + SRC_HWHS_POL_R::new(((self.bits >> 37) & 0x01) != 0) + } + #[doc = "Bit 38 - Destination hardware handshaking interface polarity"] + #[inline(always)] + pub fn dst_hwhs_pol(&self) -> DST_HWHS_POL_R { + DST_HWHS_POL_R::new(((self.bits >> 38) & 0x01) != 0) + } + #[doc = "Bits 39:42 - Assign a hardware handshaking interface to source of channel"] + #[inline(always)] + pub fn src_per(&self) -> SRC_PER_R { + SRC_PER_R::new(((self.bits >> 39) & 0x0f) as u8) + } + #[doc = "Bits 44:47 - Assign a hardware handshaking interface to destination of channel"] + #[inline(always)] + pub fn dst_per(&self) -> DST_PER_R { + DST_PER_R::new(((self.bits >> 44) & 0x0f) as u8) + } + #[doc = "Bits 49:51 - Channel priority (7 is highest, 0 is lowest)"] + #[inline(always)] + pub fn ch_prior(&self) -> CH_PRIOR_R { + CH_PRIOR_R::new(((self.bits >> 49) & 0x07) as u8) + } + #[doc = "Bit 52 - Channel lock bit"] + #[inline(always)] + pub fn lock_ch(&self) -> LOCK_CH_R { + LOCK_CH_R::new(((self.bits >> 52) & 0x01) != 0) + } + #[doc = "Bits 53:54 - Channel lock level"] + #[inline(always)] + pub fn lock_ch_l(&self) -> LOCK_CH_L_R { + LOCK_CH_L_R::new(((self.bits >> 53) & 0x03) as u8) + } + #[doc = "Bits 55:58 - Source outstanding request limit"] + #[inline(always)] + pub fn src_osr_lmt(&self) -> SRC_OSR_LMT_R { + SRC_OSR_LMT_R::new(((self.bits >> 55) & 0x0f) as u8) + } + #[doc = "Bits 59:62 - Destination outstanding request limit"] + #[inline(always)] + pub fn dst_osr_lmt(&self) -> DST_OSR_LMT_R { + DST_OSR_LMT_R::new(((self.bits >> 59) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - Source multi-block transfer type"] + #[inline(always)] + pub fn src_multblk_type(&mut self) -> SRC_MULTBLK_TYPE_W { + SRC_MULTBLK_TYPE_W { w: self } + } + #[doc = "Bits 2:3 - Destination multi-block transfer type"] + #[inline(always)] + pub fn dst_multblk_type(&mut self) -> DST_MULTBLK_TYPE_W { + DST_MULTBLK_TYPE_W { w: self } + } + #[doc = "Bits 32:34 - Transfer type and flow control"] + #[inline(always)] + pub fn tt_fc(&mut self) -> TT_FC_W { + TT_FC_W { w: self } + } + #[doc = "Bit 35 - Source software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_src(&mut self) -> HS_SEL_SRC_W { + HS_SEL_SRC_W { w: self } + } + #[doc = "Bit 36 - Destination software or hardware handshaking select"] + #[inline(always)] + pub fn hs_sel_dst(&mut self) -> HS_SEL_DST_W { + HS_SEL_DST_W { w: self } + } + #[doc = "Bit 37 - Source hardware handshaking interface polarity"] + #[inline(always)] + pub fn src_hwhs_pol(&mut self) -> SRC_HWHS_POL_W { + SRC_HWHS_POL_W { w: self } + } + #[doc = "Bit 38 - Destination hardware handshaking interface polarity"] + #[inline(always)] + pub fn dst_hwhs_pol(&mut self) -> DST_HWHS_POL_W { + DST_HWHS_POL_W { w: self } + } + #[doc = "Bits 39:42 - Assign a hardware handshaking interface to source of channel"] + #[inline(always)] + pub fn src_per(&mut self) -> SRC_PER_W { + SRC_PER_W { w: self } + } + #[doc = "Bits 44:47 - Assign a hardware handshaking interface to destination of channel"] + #[inline(always)] + pub fn dst_per(&mut self) -> DST_PER_W { + DST_PER_W { w: self } + } + #[doc = "Bits 49:51 - Channel priority (7 is highest, 0 is lowest)"] + #[inline(always)] + pub fn ch_prior(&mut self) -> CH_PRIOR_W { + CH_PRIOR_W { w: self } + } + #[doc = "Bit 52 - Channel lock bit"] + #[inline(always)] + pub fn lock_ch(&mut self) -> LOCK_CH_W { + LOCK_CH_W { w: self } + } + #[doc = "Bits 53:54 - Channel lock level"] + #[inline(always)] + pub fn lock_ch_l(&mut self) -> LOCK_CH_L_W { + LOCK_CH_L_W { w: self } + } + #[doc = "Bits 55:58 - Source outstanding request limit"] + #[inline(always)] + pub fn src_osr_lmt(&mut self) -> SRC_OSR_LMT_W { + SRC_OSR_LMT_W { w: self } + } + #[doc = "Bits 59:62 - Destination outstanding request limit"] + #[inline(always)] + pub fn dst_osr_lmt(&mut self) -> DST_OSR_LMT_W { + DST_OSR_LMT_W { w: self } + } + } + } + #[doc = "Linked List Pointer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [llp](llp) module"] + pub type LLP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LLP; + #[doc = "`read()` method returns [llp::R](llp::R) reader structure"] + impl crate::Readable for LLP {} + #[doc = "`write(|w| ..)` method takes [llp::W](llp::W) writer structure"] + impl crate::Writable for LLP {} + #[doc = "Linked List Pointer register"] + pub mod llp { + #[doc = "Reader of register llp"] + pub type R = crate::R; + #[doc = "Writer for register llp"] + pub type W = crate::W; + #[doc = "Register llp `reset()`'s with value 0"] + impl crate::ResetValue for super::LLP { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "LLI master select"] + pub type LMS_A = super::ctl::SMS_A; + #[doc = "Reader of field `lms`"] + pub type LMS_R = crate::R; + #[doc = "Write proxy for field `lms`"] + pub struct LMS_W<'a> { + w: &'a mut W, + } + impl<'a> LMS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LMS_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "AXI master 1"] + #[inline(always)] + pub fn axi_master_1(self) -> &'a mut W { + self.variant(LMS_A::AXI_MASTER_1) + } + #[doc = "AXI master 2"] + #[inline(always)] + pub fn axi_master_2(self) -> &'a mut W { + self.variant(LMS_A::AXI_MASTER_2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `loc`"] + pub type LOC_R = crate::R; + #[doc = "Write proxy for field `loc`"] + pub struct LOC_W<'a> { + w: &'a mut W, + } + impl<'a> LOC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u64) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff_ffff_ffff_ffff << 6)) + | (((value as u64) & 0x03ff_ffff_ffff_ffff) << 6); + self.w + } + } + impl R { + #[doc = "Bit 0 - LLI master select"] + #[inline(always)] + pub fn lms(&self) -> LMS_R { + LMS_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 6:63 - Starting address memeory of LLI block"] + #[inline(always)] + pub fn loc(&self) -> LOC_R { + LOC_R::new(((self.bits >> 6) & 0x03ff_ffff_ffff_ffff) as u64) + } + } + impl W { + #[doc = "Bit 0 - LLI master select"] + #[inline(always)] + pub fn lms(&mut self) -> LMS_W { + LMS_W { w: self } + } + #[doc = "Bits 6:63 - Starting address memeory of LLI block"] + #[inline(always)] + pub fn loc(&mut self) -> LOC_W { + LOC_W { w: self } + } + } + } + #[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"] + pub type STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS; + #[doc = "`read()` method returns [status::R](status::R) reader structure"] + impl crate::Readable for STATUS {} + #[doc = "`write(|w| ..)` method takes [status::W](status::W) writer structure"] + impl crate::Writable for STATUS {} + #[doc = "Channel Status Register"] + pub mod status { + #[doc = "Reader of register status"] + pub type R = crate::R; + #[doc = "Writer for register status"] + pub type W = crate::W; + #[doc = "Register status `reset()`'s with value 0"] + impl crate::ResetValue for super::STATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cmpltd_blk_size`"] + pub type CMPLTD_BLK_SIZE_R = crate::R; + #[doc = "Write proxy for field `cmpltd_blk_size`"] + pub struct CMPLTD_BLK_SIZE_W<'a> { + w: &'a mut W, + } + impl<'a> CMPLTD_BLK_SIZE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u64) & 0x003f_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:21 - Completed block transfer size"] + #[inline(always)] + pub fn cmpltd_blk_size(&self) -> CMPLTD_BLK_SIZE_R { + CMPLTD_BLK_SIZE_R::new((self.bits & 0x003f_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:21 - Completed block transfer size"] + #[inline(always)] + pub fn cmpltd_blk_size(&mut self) -> CMPLTD_BLK_SIZE_W { + CMPLTD_BLK_SIZE_W { w: self } + } + } + } + #[doc = "Channel Software handshake Source Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swhssrc](swhssrc) module"] + pub type SWHSSRC = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SWHSSRC; + #[doc = "`read()` method returns [swhssrc::R](swhssrc::R) reader structure"] + impl crate::Readable for SWHSSRC {} + #[doc = "`write(|w| ..)` method takes [swhssrc::W](swhssrc::W) writer structure"] + impl crate::Writable for SWHSSRC {} + #[doc = "Channel Software handshake Source Register"] + pub mod swhssrc { + #[doc = "Reader of register swhssrc"] + pub type R = crate::R; + #[doc = "Writer for register swhssrc"] + pub type W = crate::W; + #[doc = "Register swhssrc `reset()`'s with value 0"] + impl crate::ResetValue for super::SWHSSRC { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `req`"] + pub type REQ_R = crate::R; + #[doc = "Write proxy for field `req`"] + pub struct REQ_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `req_we`"] + pub type REQ_WE_R = crate::R; + #[doc = "Write proxy for field `req_we`"] + pub struct REQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `sglreq`"] + pub type SGLREQ_R = crate::R; + #[doc = "Write proxy for field `sglreq`"] + pub struct SGLREQ_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `sglreq_we`"] + pub type SGLREQ_WE_R = crate::R; + #[doc = "Write proxy for field `sglreq_we`"] + pub struct SGLREQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `lst`"] + pub type LST_R = crate::R; + #[doc = "Write proxy for field `lst`"] + pub struct LST_W<'a> { + w: &'a mut W, + } + impl<'a> LST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `lst_we`"] + pub type LST_WE_R = crate::R; + #[doc = "Write proxy for field `lst_we`"] + pub struct LST_WE_W<'a> { + w: &'a mut W, + } + impl<'a> LST_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0 - Software handshake request for channel source"] + #[inline(always)] + pub fn req(&self) -> REQ_R { + REQ_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&self) -> REQ_WE_R { + REQ_WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Software handshake single request for channel source"] + #[inline(always)] + pub fn sglreq(&self) -> SGLREQ_R { + SGLREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&self) -> SGLREQ_WE_R { + SGLREQ_WE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Software handshake last request for channel source"] + #[inline(always)] + pub fn lst(&self) -> LST_R { + LST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&self) -> LST_WE_R { + LST_WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Software handshake request for channel source"] + #[inline(always)] + pub fn req(&mut self) -> REQ_W { + REQ_W { w: self } + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&mut self) -> REQ_WE_W { + REQ_WE_W { w: self } + } + #[doc = "Bit 2 - Software handshake single request for channel source"] + #[inline(always)] + pub fn sglreq(&mut self) -> SGLREQ_W { + SGLREQ_W { w: self } + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&mut self) -> SGLREQ_WE_W { + SGLREQ_WE_W { w: self } + } + #[doc = "Bit 4 - Software handshake last request for channel source"] + #[inline(always)] + pub fn lst(&mut self) -> LST_W { + LST_W { w: self } + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&mut self) -> LST_WE_W { + LST_WE_W { w: self } + } + } + } + #[doc = "Channel Software handshake Destination Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swhsdst](swhsdst) module"] + pub type SWHSDST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SWHSDST; + #[doc = "`read()` method returns [swhsdst::R](swhsdst::R) reader structure"] + impl crate::Readable for SWHSDST {} + #[doc = "`write(|w| ..)` method takes [swhsdst::W](swhsdst::W) writer structure"] + impl crate::Writable for SWHSDST {} + #[doc = "Channel Software handshake Destination Register"] + pub mod swhsdst { + #[doc = "Reader of register swhsdst"] + pub type R = crate::R; + #[doc = "Writer for register swhsdst"] + pub type W = crate::W; + #[doc = "Register swhsdst `reset()`'s with value 0"] + impl crate::ResetValue for super::SWHSDST { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `req`"] + pub type REQ_R = crate::R; + #[doc = "Write proxy for field `req`"] + pub struct REQ_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `req_we`"] + pub type REQ_WE_R = crate::R; + #[doc = "Write proxy for field `req_we`"] + pub struct REQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> REQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `sglreq`"] + pub type SGLREQ_R = crate::R; + #[doc = "Write proxy for field `sglreq`"] + pub struct SGLREQ_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `sglreq_we`"] + pub type SGLREQ_WE_R = crate::R; + #[doc = "Write proxy for field `sglreq_we`"] + pub struct SGLREQ_WE_W<'a> { + w: &'a mut W, + } + impl<'a> SGLREQ_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `lst`"] + pub type LST_R = crate::R; + #[doc = "Write proxy for field `lst`"] + pub struct LST_W<'a> { + w: &'a mut W, + } + impl<'a> LST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `lst_we`"] + pub type LST_WE_R = crate::R; + #[doc = "Write proxy for field `lst_we`"] + pub struct LST_WE_W<'a> { + w: &'a mut W, + } + impl<'a> LST_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0 - Software handshake request for channel destination"] + #[inline(always)] + pub fn req(&self) -> REQ_R { + REQ_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&self) -> REQ_WE_R { + REQ_WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Software handshake single request for channel destination"] + #[inline(always)] + pub fn sglreq(&self) -> SGLREQ_R { + SGLREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&self) -> SGLREQ_WE_R { + SGLREQ_WE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Software handshake last request for channel destination"] + #[inline(always)] + pub fn lst(&self) -> LST_R { + LST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&self) -> LST_WE_R { + LST_WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Software handshake request for channel destination"] + #[inline(always)] + pub fn req(&mut self) -> REQ_W { + REQ_W { w: self } + } + #[doc = "Bit 1 - Write enable bit for software handshake request"] + #[inline(always)] + pub fn req_we(&mut self) -> REQ_WE_W { + REQ_WE_W { w: self } + } + #[doc = "Bit 2 - Software handshake single request for channel destination"] + #[inline(always)] + pub fn sglreq(&mut self) -> SGLREQ_W { + SGLREQ_W { w: self } + } + #[doc = "Bit 3 - Write enable bit for software handshake"] + #[inline(always)] + pub fn sglreq_we(&mut self) -> SGLREQ_WE_W { + SGLREQ_WE_W { w: self } + } + #[doc = "Bit 4 - Software handshake last request for channel destination"] + #[inline(always)] + pub fn lst(&mut self) -> LST_W { + LST_W { w: self } + } + #[doc = "Bit 5 - Write enable bit for software handshake last request"] + #[inline(always)] + pub fn lst_we(&mut self) -> LST_WE_W { + LST_WE_W { w: self } + } + } + } + #[doc = "Channel Block Transfer Resume Request Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blk_tfr](blk_tfr) module"] + pub type BLK_TFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BLK_TFR; + #[doc = "`read()` method returns [blk_tfr::R](blk_tfr::R) reader structure"] + impl crate::Readable for BLK_TFR {} + #[doc = "`write(|w| ..)` method takes [blk_tfr::W](blk_tfr::W) writer structure"] + impl crate::Writable for BLK_TFR {} + #[doc = "Channel Block Transfer Resume Request Register"] + pub mod blk_tfr { + #[doc = "Reader of register blk_tfr"] + pub type R = crate::R; + #[doc = "Writer for register blk_tfr"] + pub type W = crate::W; + #[doc = "Register blk_tfr `reset()`'s with value 0"] + impl crate::ResetValue for super::BLK_TFR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `resumereq`"] + pub type RESUMEREQ_R = crate::R; + #[doc = "Write proxy for field `resumereq`"] + pub struct RESUMEREQ_W<'a> { + w: &'a mut W, + } + impl<'a> RESUMEREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer resume request"] + #[inline(always)] + pub fn resumereq(&self) -> RESUMEREQ_R { + RESUMEREQ_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer resume request"] + #[inline(always)] + pub fn resumereq(&mut self) -> RESUMEREQ_W { + RESUMEREQ_W { w: self } + } + } + } + #[doc = "Channel AXI ID Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [axi_id](axi_id) module"] + pub type AXI_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AXI_ID; + #[doc = "`read()` method returns [axi_id::R](axi_id::R) reader structure"] + impl crate::Readable for AXI_ID {} + #[doc = "`write(|w| ..)` method takes [axi_id::W](axi_id::W) writer structure"] + impl crate::Writable for AXI_ID {} + #[doc = "Channel AXI ID Register"] + pub mod axi_id { + #[doc = "Reader of register axi_id"] + pub type R = crate::R; + #[doc = "Writer for register axi_id"] + pub type W = crate::W; + #[doc = "Register axi_id `reset()`'s with value 0"] + impl crate::ResetValue for super::AXI_ID { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "AXI QOS Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [axi_qos](axi_qos) module"] + pub type AXI_QOS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AXI_QOS; + #[doc = "`read()` method returns [axi_qos::R](axi_qos::R) reader structure"] + impl crate::Readable for AXI_QOS {} + #[doc = "`write(|w| ..)` method takes [axi_qos::W](axi_qos::W) writer structure"] + impl crate::Writable for AXI_QOS {} + #[doc = "AXI QOS Register"] + pub mod axi_qos { + #[doc = "Reader of register axi_qos"] + pub type R = crate::R; + #[doc = "Writer for register axi_qos"] + pub type W = crate::W; + #[doc = "Register axi_qos `reset()`'s with value 0"] + impl crate::ResetValue for super::AXI_QOS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus_en](intstatus_en) module"] + pub type INTSTATUS_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSTATUS_EN; + #[doc = "`read()` method returns [intstatus_en::R](intstatus_en::R) reader structure"] + impl crate::Readable for INTSTATUS_EN {} + #[doc = "`write(|w| ..)` method takes [intstatus_en::W](intstatus_en::W) writer structure"] + impl crate::Writable for INTSTATUS_EN {} + #[doc = "Interrupt Status Enable Register"] + pub mod intstatus_en { + #[doc = "Reader of register intstatus_en"] + pub type R = crate::R; + #[doc = "Writer for register intstatus_en"] + pub type W = crate::W; + #[doc = "Register intstatus_en `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSTATUS_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Channel Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](intstatus) module"] + pub type INTSTATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSTATUS; + #[doc = "`read()` method returns [intstatus::R](intstatus::R) reader structure"] + impl crate::Readable for INTSTATUS {} + #[doc = "`write(|w| ..)` method takes [intstatus::W](intstatus::W) writer structure"] + impl crate::Writable for INTSTATUS {} + #[doc = "Channel Interrupt Status Register"] + pub mod intstatus { + #[doc = "Reader of register intstatus"] + pub type R = crate::R; + #[doc = "Writer for register intstatus"] + pub type W = crate::W; + #[doc = "Register intstatus `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSTATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Interrupt Signal Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intsignal_en](intsignal_en) module"] + pub type INTSIGNAL_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSIGNAL_EN; + #[doc = "`read()` method returns [intsignal_en::R](intsignal_en::R) reader structure"] + impl crate::Readable for INTSIGNAL_EN {} + #[doc = "`write(|w| ..)` method takes [intsignal_en::W](intsignal_en::W) writer structure"] + impl crate::Writable for INTSIGNAL_EN {} + #[doc = "Interrupt Signal Enable Register"] + pub mod intsignal_en { + #[doc = "Reader of register intsignal_en"] + pub type R = crate::R; + #[doc = "Writer for register intsignal_en"] + pub type W = crate::W; + #[doc = "Register intsignal_en `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSIGNAL_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intclear](intclear) module"] + pub type INTCLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTCLEAR; + #[doc = "`read()` method returns [intclear::R](intclear::R) reader structure"] + impl crate::Readable for INTCLEAR {} + #[doc = "`write(|w| ..)` method takes [intclear::W](intclear::W) writer structure"] + impl crate::Writable for INTCLEAR {} + #[doc = "Interrupt Clear Register"] + pub mod intclear { + #[doc = "Reader of register intclear"] + pub type R = crate::R; + #[doc = "Writer for register intclear"] + pub type W = crate::W; + #[doc = "Register intclear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTCLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `block_tfr_done`"] + pub type BLOCK_TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `block_tfr_done`"] + pub struct BLOCK_TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> BLOCK_TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `tfr_done`"] + pub type TFR_DONE_R = crate::R; + #[doc = "Write proxy for field `tfr_done`"] + pub struct TFR_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> TFR_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `src_transcomp`"] + pub type SRC_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `src_transcomp`"] + pub struct SRC_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `dst_transcomp`"] + pub type DST_TRANSCOMP_R = crate::R; + #[doc = "Write proxy for field `dst_transcomp`"] + pub struct DST_TRANSCOMP_W<'a> { + w: &'a mut W, + } + impl<'a> DST_TRANSCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u64) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `src_dec_err`"] + pub type SRC_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `src_dec_err`"] + pub struct SRC_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u64) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `dst_dec_err`"] + pub type DST_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_dec_err`"] + pub struct DST_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u64) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `src_slv_err`"] + pub type SRC_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `src_slv_err`"] + pub struct SRC_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SRC_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u64) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `dst_slv_err`"] + pub type DST_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `dst_slv_err`"] + pub struct DST_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> DST_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `lli_rd_dec_err`"] + pub type LLI_RD_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_dec_err`"] + pub struct LLI_RD_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u64) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `lli_wr_dec_err`"] + pub type LLI_WR_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_dec_err`"] + pub struct LLI_WR_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u64) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `lli_rd_slv_err`"] + pub type LLI_RD_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_rd_slv_err`"] + pub struct LLI_RD_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_RD_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u64) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `lli_wr_slv_err`"] + pub type LLI_WR_SLV_ERR_R = crate::R; + #[doc = "Write proxy for field `lli_wr_slv_err`"] + pub struct LLI_WR_SLV_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> LLI_WR_SLV_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u64) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&self) -> BLOCK_TFR_DONE_R { + BLOCK_TFR_DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&self) -> TFR_DONE_R { + TFR_DONE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&self) -> SRC_TRANSCOMP_R { + SRC_TRANSCOMP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&self) -> DST_TRANSCOMP_R { + DST_TRANSCOMP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&self) -> SRC_DEC_ERR_R { + SRC_DEC_ERR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&self) -> DST_DEC_ERR_R { + DST_DEC_ERR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&self) -> SRC_SLV_ERR_R { + SRC_SLV_ERR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&self) -> DST_SLV_ERR_R { + DST_SLV_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&self) -> LLI_RD_DEC_ERR_R { + LLI_RD_DEC_ERR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&self) -> LLI_WR_DEC_ERR_R { + LLI_WR_DEC_ERR_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&self) -> LLI_RD_SLV_ERR_R { + LLI_RD_SLV_ERR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&self) -> LLI_WR_SLV_ERR_R { + LLI_WR_SLV_ERR_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Block transfer done"] + #[inline(always)] + pub fn block_tfr_done(&mut self) -> BLOCK_TFR_DONE_W { + BLOCK_TFR_DONE_W { w: self } + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn tfr_done(&mut self) -> TFR_DONE_W { + TFR_DONE_W { w: self } + } + #[doc = "Bit 3 - Source transaction complete"] + #[inline(always)] + pub fn src_transcomp(&mut self) -> SRC_TRANSCOMP_W { + SRC_TRANSCOMP_W { w: self } + } + #[doc = "Bit 4 - Destination transaction complete"] + #[inline(always)] + pub fn dst_transcomp(&mut self) -> DST_TRANSCOMP_W { + DST_TRANSCOMP_W { w: self } + } + #[doc = "Bit 5 - Source Decode Error"] + #[inline(always)] + pub fn src_dec_err(&mut self) -> SRC_DEC_ERR_W { + SRC_DEC_ERR_W { w: self } + } + #[doc = "Bit 6 - Destination Decode Error"] + #[inline(always)] + pub fn dst_dec_err(&mut self) -> DST_DEC_ERR_W { + DST_DEC_ERR_W { w: self } + } + #[doc = "Bit 7 - Source Slave Error"] + #[inline(always)] + pub fn src_slv_err(&mut self) -> SRC_SLV_ERR_W { + SRC_SLV_ERR_W { w: self } + } + #[doc = "Bit 8 - Destination Slave Error"] + #[inline(always)] + pub fn dst_slv_err(&mut self) -> DST_SLV_ERR_W { + DST_SLV_ERR_W { w: self } + } + #[doc = "Bit 9 - LLI Read Decode Error Status Enable"] + #[inline(always)] + pub fn lli_rd_dec_err(&mut self) -> LLI_RD_DEC_ERR_W { + LLI_RD_DEC_ERR_W { w: self } + } + #[doc = "Bit 10 - LLI WRITE Decode Error"] + #[inline(always)] + pub fn lli_wr_dec_err(&mut self) -> LLI_WR_DEC_ERR_W { + LLI_WR_DEC_ERR_W { w: self } + } + #[doc = "Bit 11 - LLI Read Slave Error"] + #[inline(always)] + pub fn lli_rd_slv_err(&mut self) -> LLI_RD_SLV_ERR_W { + LLI_RD_SLV_ERR_W { w: self } + } + #[doc = "Bit 12 - LLI WRITE Slave Error"] + #[inline(always)] + pub fn lli_wr_slv_err(&mut self) -> LLI_WR_SLV_ERR_W { + LLI_WR_SLV_ERR_W { w: self } + } + } + } + #[doc = "Padding to make structure size 256 bytes so that channels\\[\\] +is an array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_reserved](_reserved) module"] + pub type _RESERVED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct __RESERVED; + #[doc = "`read()` method returns [_reserved::R](_reserved::R) reader structure"] + impl crate::Readable for _RESERVED {} + #[doc = "`write(|w| ..)` method takes [_reserved::W](_reserved::W) writer structure"] + impl crate::Writable for _RESERVED {} + #[doc = "Padding to make structure size 256 bytes so that channels\\[\\] +is an array"] + pub mod _reserved { + #[doc = "Reader of register _reserved"] + pub type R = crate::R; + #[doc = "Writer for register _reserved"] + pub type W = crate::W; + #[doc = "Register _reserved `reset()`'s with value 0"] + impl crate::ResetValue for super::_RESERVED { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "ID Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id](id) module"] + pub type ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ID; + #[doc = "`read()` method returns [id::R](id::R) reader structure"] + impl crate::Readable for ID {} + #[doc = "`write(|w| ..)` method takes [id::W](id::W) writer structure"] + impl crate::Writable for ID {} + #[doc = "ID Register"] + pub mod id { + #[doc = "Reader of register id"] + pub type R = crate::R; + #[doc = "Writer for register id"] + pub type W = crate::W; + #[doc = "Register id `reset()`'s with value 0"] + impl crate::ResetValue for super::ID { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "COMPVER Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compver](compver) module"] + pub type COMPVER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMPVER; + #[doc = "`read()` method returns [compver::R](compver::R) reader structure"] + impl crate::Readable for COMPVER {} + #[doc = "`write(|w| ..)` method takes [compver::W](compver::W) writer structure"] + impl crate::Writable for COMPVER {} + #[doc = "COMPVER Register"] + pub mod compver { + #[doc = "Reader of register compver"] + pub type R = crate::R; + #[doc = "Writer for register compver"] + pub type W = crate::W; + #[doc = "Register compver `reset()`'s with value 0"] + impl crate::ResetValue for super::COMPVER { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Configure Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] + pub type CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CFG; + #[doc = "`read()` method returns [cfg::R](cfg::R) reader structure"] + impl crate::Readable for CFG {} + #[doc = "`write(|w| ..)` method takes [cfg::W](cfg::W) writer structure"] + impl crate::Writable for CFG {} + #[doc = "Configure Register"] + pub mod cfg { + #[doc = "Reader of register cfg"] + pub type R = crate::R; + #[doc = "Writer for register cfg"] + pub type W = crate::W; + #[doc = "Register cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CFG { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dmac_en`"] + pub type DMAC_EN_R = crate::R; + #[doc = "Write proxy for field `dmac_en`"] + pub struct DMAC_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMAC_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `int_en`"] + pub type INT_EN_R = crate::R; + #[doc = "Write proxy for field `int_en`"] + pub struct INT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> INT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Enable DMAC"] + #[inline(always)] + pub fn dmac_en(&self) -> DMAC_EN_R { + DMAC_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Globally enable interrupt generation"] + #[inline(always)] + pub fn int_en(&self) -> INT_EN_R { + INT_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Enable DMAC"] + #[inline(always)] + pub fn dmac_en(&mut self) -> DMAC_EN_W { + DMAC_EN_W { w: self } + } + #[doc = "Bit 1 - Globally enable interrupt generation"] + #[inline(always)] + pub fn int_en(&mut self) -> INT_EN_W { + INT_EN_W { w: self } + } + } + } + #[doc = "Channel Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chen](chen) module"] + pub type CHEN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CHEN; + #[doc = "`read()` method returns [chen::R](chen::R) reader structure"] + impl crate::Readable for CHEN {} + #[doc = "`write(|w| ..)` method takes [chen::W](chen::W) writer structure"] + impl crate::Writable for CHEN {} + #[doc = "Channel Enable Register"] + pub mod chen { + #[doc = "Reader of register chen"] + pub type R = crate::R; + #[doc = "Writer for register chen"] + pub type W = crate::W; + #[doc = "Register chen `reset()`'s with value 0"] + impl crate::ResetValue for super::CHEN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `ch(1-6)_en`"] + pub type CH_EN_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_en`"] + pub struct CH_EN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_en_we`"] + pub type CH_EN_WE_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_en_we`"] + pub struct CH_EN_WE_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_EN_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_susp`"] + pub type CH_SUSP_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_susp`"] + pub struct CH_SUSP_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_susp_we`"] + pub type CH_SUSP_WE_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_susp_we`"] + pub struct CH_SUSP_WE_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_SUSP_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_abort`"] + pub type CH_ABORT_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_abort`"] + pub struct CH_ABORT_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_ABORT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of fields `ch(1-6)_abort_we`"] + pub type CH_ABORT_WE_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_abort_we`"] + pub struct CH_ABORT_WE_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_ABORT_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = "Enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en(&self, n: usize) -> CH_EN_R { + CH_EN_R::new(((self.bits >> n - 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn ch1_en(&self) -> CH_EN_R { + CH_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable channel 2"] + #[inline(always)] + pub fn ch2_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Enable channel 3"] + #[inline(always)] + pub fn ch3_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Enable channel 4"] + #[inline(always)] + pub fn ch4_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Enable channel 5"] + #[inline(always)] + pub fn ch5_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Enable channel 6"] + #[inline(always)] + pub fn ch6_en(&self) -> CH_EN_R { + CH_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Write enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en_we(&self, n: usize) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> n - 1 + 8) & 0x01) != 0) + } + #[doc = "Bit 8 - Write enable channel 1"] + #[inline(always)] + pub fn ch1_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Write enable channel 2"] + #[inline(always)] + pub fn ch2_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Write enable channel 3"] + #[inline(always)] + pub fn ch3_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Write enable channel 4"] + #[inline(always)] + pub fn ch4_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Write enable channel 5"] + #[inline(always)] + pub fn ch5_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Write enable channel 6"] + #[inline(always)] + pub fn ch6_en_we(&self) -> CH_EN_WE_R { + CH_EN_WE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Suspend request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_susp(&self, n: usize) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> n - 1 + 16) & 0x01) != 0) + } + #[doc = "Bit 16 - Suspend request channel 1"] + #[inline(always)] + pub fn ch1_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Suspend request channel 2"] + #[inline(always)] + pub fn ch2_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Suspend request channel 3"] + #[inline(always)] + pub fn ch3_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Suspend request channel 4"] + #[inline(always)] + pub fn ch4_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Suspend request channel 5"] + #[inline(always)] + pub fn ch5_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Suspend request channel 6"] + #[inline(always)] + pub fn ch6_susp(&self) -> CH_SUSP_R { + CH_SUSP_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Enable write to ch(1-6)_susp bit"] + #[inline(always)] + pub unsafe fn ch_susp_we(&self, n: usize) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> n - 1 + 24) & 0x01) != 0) + } + #[doc = "Bit 24 - Enable write to ch1_susp bit"] + #[inline(always)] + pub fn ch1_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Enable write to ch2_susp bit"] + #[inline(always)] + pub fn ch2_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Enable write to ch3_susp bit"] + #[inline(always)] + pub fn ch3_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Enable write to ch4_susp bit"] + #[inline(always)] + pub fn ch4_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Enable write to ch5_susp bit"] + #[inline(always)] + pub fn ch5_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Enable write to ch6_susp bit"] + #[inline(always)] + pub fn ch6_susp_we(&self) -> CH_SUSP_WE_R { + CH_SUSP_WE_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Abort request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_abort(&self, n: usize) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> n - 1 + 32) & 0x01) != 0) + } + #[doc = "Bit 32 - Abort request channel 1"] + #[inline(always)] + pub fn ch1_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 32) & 0x01) != 0) + } + #[doc = "Bit 33 - Abort request channel 2"] + #[inline(always)] + pub fn ch2_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 33) & 0x01) != 0) + } + #[doc = "Bit 34 - Abort request channel 3"] + #[inline(always)] + pub fn ch3_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 34) & 0x01) != 0) + } + #[doc = "Bit 35 - Abort request channel 4"] + #[inline(always)] + pub fn ch4_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 35) & 0x01) != 0) + } + #[doc = "Bit 36 - Abort request channel 5"] + #[inline(always)] + pub fn ch5_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 36) & 0x01) != 0) + } + #[doc = "Bit 37 - Abort request channel 6"] + #[inline(always)] + pub fn ch6_abort(&self) -> CH_ABORT_R { + CH_ABORT_R::new(((self.bits >> 37) & 0x01) != 0) + } + #[doc = "Enable write to ch(1-6)_abort bit"] + #[inline(always)] + pub unsafe fn ch_abort_we(&self, n: usize) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> n - 1 + 40) & 0x01) != 0) + } + #[doc = "Bit 40 - Enable write to ch1_abort bit"] + #[inline(always)] + pub fn ch1_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 40) & 0x01) != 0) + } + #[doc = "Bit 41 - Enable write to ch2_abort bit"] + #[inline(always)] + pub fn ch2_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 41) & 0x01) != 0) + } + #[doc = "Bit 42 - Enable write to ch3_abort bit"] + #[inline(always)] + pub fn ch3_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 42) & 0x01) != 0) + } + #[doc = "Bit 43 - Enable write to ch4_abort bit"] + #[inline(always)] + pub fn ch4_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 43) & 0x01) != 0) + } + #[doc = "Bit 44 - Enable write to ch5_abort bit"] + #[inline(always)] + pub fn ch5_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 44) & 0x01) != 0) + } + #[doc = "Bit 45 - Enable write to ch6_abort bit"] + #[inline(always)] + pub fn ch6_abort_we(&self) -> CH_ABORT_WE_R { + CH_ABORT_WE_R::new(((self.bits >> 45) & 0x01) != 0) + } + } + impl W { + #[doc = "Enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en(&mut self, n: usize) -> CH_EN_W { + CH_EN_W { + w: self, + offset: n - 1, + } + } + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn ch1_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 0 } + } + #[doc = "Bit 1 - Enable channel 2"] + #[inline(always)] + pub fn ch2_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 1 } + } + #[doc = "Bit 2 - Enable channel 3"] + #[inline(always)] + pub fn ch3_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 2 } + } + #[doc = "Bit 3 - Enable channel 4"] + #[inline(always)] + pub fn ch4_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 3 } + } + #[doc = "Bit 4 - Enable channel 5"] + #[inline(always)] + pub fn ch5_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 4 } + } + #[doc = "Bit 5 - Enable channel 6"] + #[inline(always)] + pub fn ch6_en(&mut self) -> CH_EN_W { + CH_EN_W { w: self, offset: 5 } + } + #[doc = "Write enable channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_en_we(&mut self, n: usize) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: n - 1 + 8, + } + } + #[doc = "Bit 8 - Write enable channel 1"] + #[inline(always)] + pub fn ch1_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { w: self, offset: 8 } + } + #[doc = "Bit 9 - Write enable channel 2"] + #[inline(always)] + pub fn ch2_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { w: self, offset: 9 } + } + #[doc = "Bit 10 - Write enable channel 3"] + #[inline(always)] + pub fn ch3_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 10, + } + } + #[doc = "Bit 11 - Write enable channel 4"] + #[inline(always)] + pub fn ch4_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 11, + } + } + #[doc = "Bit 12 - Write enable channel 5"] + #[inline(always)] + pub fn ch5_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 12, + } + } + #[doc = "Bit 13 - Write enable channel 6"] + #[inline(always)] + pub fn ch6_en_we(&mut self) -> CH_EN_WE_W { + CH_EN_WE_W { + w: self, + offset: 13, + } + } + #[doc = "Suspend request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_susp(&mut self, n: usize) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: n - 1 + 16, + } + } + #[doc = "Bit 16 - Suspend request channel 1"] + #[inline(always)] + pub fn ch1_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 16, + } + } + #[doc = "Bit 17 - Suspend request channel 2"] + #[inline(always)] + pub fn ch2_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 17, + } + } + #[doc = "Bit 18 - Suspend request channel 3"] + #[inline(always)] + pub fn ch3_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 18, + } + } + #[doc = "Bit 19 - Suspend request channel 4"] + #[inline(always)] + pub fn ch4_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 19, + } + } + #[doc = "Bit 20 - Suspend request channel 5"] + #[inline(always)] + pub fn ch5_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 20, + } + } + #[doc = "Bit 21 - Suspend request channel 6"] + #[inline(always)] + pub fn ch6_susp(&mut self) -> CH_SUSP_W { + CH_SUSP_W { + w: self, + offset: 21, + } + } + #[doc = "Enable write to ch(1-6)_susp bit"] + #[inline(always)] + pub unsafe fn ch_susp_we(&mut self, n: usize) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: n - 1 + 24, + } + } + #[doc = "Bit 24 - Enable write to ch1_susp bit"] + #[inline(always)] + pub fn ch1_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 24, + } + } + #[doc = "Bit 25 - Enable write to ch2_susp bit"] + #[inline(always)] + pub fn ch2_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 25, + } + } + #[doc = "Bit 26 - Enable write to ch3_susp bit"] + #[inline(always)] + pub fn ch3_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 26, + } + } + #[doc = "Bit 27 - Enable write to ch4_susp bit"] + #[inline(always)] + pub fn ch4_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 27, + } + } + #[doc = "Bit 28 - Enable write to ch5_susp bit"] + #[inline(always)] + pub fn ch5_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 28, + } + } + #[doc = "Bit 29 - Enable write to ch6_susp bit"] + #[inline(always)] + pub fn ch6_susp_we(&mut self) -> CH_SUSP_WE_W { + CH_SUSP_WE_W { + w: self, + offset: 29, + } + } + #[doc = "Abort request channel (1-6)"] + #[inline(always)] + pub unsafe fn ch_abort(&mut self, n: usize) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: n - 1 + 32, + } + } + #[doc = "Bit 32 - Abort request channel 1"] + #[inline(always)] + pub fn ch1_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 32, + } + } + #[doc = "Bit 33 - Abort request channel 2"] + #[inline(always)] + pub fn ch2_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 33, + } + } + #[doc = "Bit 34 - Abort request channel 3"] + #[inline(always)] + pub fn ch3_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 34, + } + } + #[doc = "Bit 35 - Abort request channel 4"] + #[inline(always)] + pub fn ch4_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 35, + } + } + #[doc = "Bit 36 - Abort request channel 5"] + #[inline(always)] + pub fn ch5_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 36, + } + } + #[doc = "Bit 37 - Abort request channel 6"] + #[inline(always)] + pub fn ch6_abort(&mut self) -> CH_ABORT_W { + CH_ABORT_W { + w: self, + offset: 37, + } + } + #[doc = "Enable write to ch(1-6)_abort bit"] + #[inline(always)] + pub unsafe fn ch_abort_we(&mut self, n: usize) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: n - 1 + 40, + } + } + #[doc = "Bit 40 - Enable write to ch1_abort bit"] + #[inline(always)] + pub fn ch1_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 40, + } + } + #[doc = "Bit 41 - Enable write to ch2_abort bit"] + #[inline(always)] + pub fn ch2_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 41, + } + } + #[doc = "Bit 42 - Enable write to ch3_abort bit"] + #[inline(always)] + pub fn ch3_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 42, + } + } + #[doc = "Bit 43 - Enable write to ch4_abort bit"] + #[inline(always)] + pub fn ch4_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 43, + } + } + #[doc = "Bit 44 - Enable write to ch5_abort bit"] + #[inline(always)] + pub fn ch5_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 44, + } + } + #[doc = "Bit 45 - Enable write to ch6_abort bit"] + #[inline(always)] + pub fn ch6_abort_we(&mut self) -> CH_ABORT_WE_W { + CH_ABORT_WE_W { + w: self, + offset: 45, + } + } + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](intstatus) module"] + pub type INTSTATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTSTATUS; + #[doc = "`read()` method returns [intstatus::R](intstatus::R) reader structure"] + impl crate::Readable for INTSTATUS {} + #[doc = "`write(|w| ..)` method takes [intstatus::W](intstatus::W) writer structure"] + impl crate::Writable for INTSTATUS {} + #[doc = "Interrupt Status Register"] + pub mod intstatus { + #[doc = "Reader of register intstatus"] + pub type R = crate::R; + #[doc = "Writer for register intstatus"] + pub type W = crate::W; + #[doc = "Register intstatus `reset()`'s with value 0"] + impl crate::ResetValue for super::INTSTATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `ch(1-6)_intstat`"] + pub type CH_INTSTAT_R = crate::R; + #[doc = "Write proxy for fields `ch(1-6)_intstat`"] + pub struct CH_INTSTAT_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> CH_INTSTAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u64) & 0x01) << self.offset); + self.w + } + } + #[doc = "Reader of field `commonreg_intstat`"] + pub type COMMONREG_INTSTAT_R = crate::R; + #[doc = "Write proxy for field `commonreg_intstat`"] + pub struct COMMONREG_INTSTAT_W<'a> { + w: &'a mut W, + } + impl<'a> COMMONREG_INTSTAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u64) & 0x01) << 16); + self.w + } + } + impl R { + #[doc = "Channel (1-6) interrupt bit"] + #[inline(always)] + pub unsafe fn ch_intstat(&self, n: usize) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> n - 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel 1 interrupt bit"] + #[inline(always)] + pub fn ch1_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 2 interrupt bit"] + #[inline(always)] + pub fn ch2_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 3 interrupt bit"] + #[inline(always)] + pub fn ch3_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 4 interrupt bit"] + #[inline(always)] + pub fn ch4_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 5 interrupt bit"] + #[inline(always)] + pub fn ch5_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 6 interrupt bit"] + #[inline(always)] + pub fn ch6_intstat(&self) -> CH_INTSTAT_R { + CH_INTSTAT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Common register status bit"] + #[inline(always)] + pub fn commonreg_intstat(&self) -> COMMONREG_INTSTAT_R { + COMMONREG_INTSTAT_R::new(((self.bits >> 16) & 0x01) != 0) + } + } + impl W { + #[doc = "Channel (1-6) interrupt bit"] + #[inline(always)] + pub unsafe fn ch_intstat(&mut self, n: usize) -> CH_INTSTAT_W { + CH_INTSTAT_W { + w: self, + offset: n - 1, + } + } + #[doc = "Bit 0 - Channel 1 interrupt bit"] + #[inline(always)] + pub fn ch1_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 0 } + } + #[doc = "Bit 1 - Channel 2 interrupt bit"] + #[inline(always)] + pub fn ch2_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 1 } + } + #[doc = "Bit 2 - Channel 3 interrupt bit"] + #[inline(always)] + pub fn ch3_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 2 } + } + #[doc = "Bit 3 - Channel 4 interrupt bit"] + #[inline(always)] + pub fn ch4_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 3 } + } + #[doc = "Bit 4 - Channel 5 interrupt bit"] + #[inline(always)] + pub fn ch5_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 4 } + } + #[doc = "Bit 5 - Channel 6 interrupt bit"] + #[inline(always)] + pub fn ch6_intstat(&mut self) -> CH_INTSTAT_W { + CH_INTSTAT_W { w: self, offset: 5 } + } + #[doc = "Bit 16 - Common register status bit"] + #[inline(always)] + pub fn commonreg_intstat(&mut self) -> COMMONREG_INTSTAT_W { + COMMONREG_INTSTAT_W { w: self } + } + } + } + #[doc = "Common Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intclear](com_intclear) module"] + pub type COM_INTCLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTCLEAR; + #[doc = "`read()` method returns [com_intclear::R](com_intclear::R) reader structure"] + impl crate::Readable for COM_INTCLEAR {} + #[doc = "`write(|w| ..)` method takes [com_intclear::W](com_intclear::W) writer structure"] + impl crate::Writable for COM_INTCLEAR {} + #[doc = "Common Interrupt Clear Register"] + pub mod com_intclear { + #[doc = "Reader of register com_intclear"] + pub type R = crate::R; + #[doc = "Writer for register com_intclear"] + pub type W = crate::W; + #[doc = "Register com_intclear `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTCLEAR { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Clear slvif_dec_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clear slvif_wr2ro_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clear slvif_rd2wo_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear slvif_wronhold_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Clear slvif_undefinedreg_dec_err in com_intstatus"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Clear slvif_dec_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Clear slvif_wr2ro_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Clear slvif_rd2wo_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Clear slvif_wronhold_err interrupt in com_intstatus"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Clear slvif_undefinedreg_dec_err in com_intstatus"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Common Interrupt Status Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intstatus_en](com_intstatus_en) module"] + pub type COM_INTSTATUS_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTSTATUS_EN; + #[doc = "`read()` method returns [com_intstatus_en::R](com_intstatus_en::R) reader structure"] + impl crate::Readable for COM_INTSTATUS_EN {} + #[doc = "`write(|w| ..)` method takes [com_intstatus_en::W](com_intstatus_en::W) writer structure"] + impl crate::Writable for COM_INTSTATUS_EN {} + #[doc = "Common Interrupt Status Enable Register"] + pub mod com_intstatus_en { + #[doc = "Reader of register com_intstatus_en"] + pub type R = crate::R; + #[doc = "Writer for register com_intstatus_en"] + pub type W = crate::W; + #[doc = "Register com_intstatus_en `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTSTATUS_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Common Interrupt Signal Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intsignal_en](com_intsignal_en) module"] + pub type COM_INTSIGNAL_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTSIGNAL_EN; + #[doc = "`read()` method returns [com_intsignal_en::R](com_intsignal_en::R) reader structure"] + impl crate::Readable for COM_INTSIGNAL_EN {} + #[doc = "`write(|w| ..)` method takes [com_intsignal_en::W](com_intsignal_en::W) writer structure"] + impl crate::Writable for COM_INTSIGNAL_EN {} + #[doc = "Common Interrupt Signal Enable Register"] + pub mod com_intsignal_en { + #[doc = "Reader of register com_intsignal_en"] + pub type R = crate::R; + #[doc = "Writer for register com_intsignal_en"] + pub type W = crate::W; + #[doc = "Register com_intsignal_en `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTSIGNAL_EN { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Common Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [com_intstatus](com_intstatus) module"] + pub type COM_INTSTATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COM_INTSTATUS; + #[doc = "`read()` method returns [com_intstatus::R](com_intstatus::R) reader structure"] + impl crate::Readable for COM_INTSTATUS {} + #[doc = "`write(|w| ..)` method takes [com_intstatus::W](com_intstatus::W) writer structure"] + impl crate::Writable for COM_INTSTATUS {} + #[doc = "Common Interrupt Status"] + pub mod com_intstatus { + #[doc = "Reader of register com_intstatus"] + pub type R = crate::R; + #[doc = "Writer for register com_intstatus"] + pub type W = crate::W; + #[doc = "Register com_intstatus `reset()`'s with value 0"] + impl crate::ResetValue for super::COM_INTSTATUS { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `slvif_dec_err`"] + pub type SLVIF_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_dec_err`"] + pub struct SLVIF_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + #[doc = "Reader of field `slvif_wr2ro_err`"] + pub type SLVIF_WR2RO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wr2ro_err`"] + pub struct SLVIF_WR2RO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WR2RO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u64) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `slvif_rd2wo_err`"] + pub type SLVIF_RD2WO_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_rd2wo_err`"] + pub struct SLVIF_RD2WO_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_RD2WO_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u64) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `slvif_wronhold_err`"] + pub type SLVIF_WRONHOLD_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_wronhold_err`"] + pub struct SLVIF_WRONHOLD_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_WRONHOLD_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u64) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `slvif_undefinedreg_dec_err`"] + pub type SLVIF_UNDEFINEDREG_DEC_ERR_R = crate::R; + #[doc = "Write proxy for field `slvif_undefinedreg_dec_err`"] + pub struct SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + w: &'a mut W, + } + impl<'a> SLVIF_UNDEFINEDREG_DEC_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u64) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&self) -> SLVIF_DEC_ERR_R { + SLVIF_DEC_ERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&self) -> SLVIF_WR2RO_ERR_R { + SLVIF_WR2RO_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&self) -> SLVIF_RD2WO_ERR_R { + SLVIF_RD2WO_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&self) -> SLVIF_WRONHOLD_ERR_R { + SLVIF_WRONHOLD_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_R { + SLVIF_UNDEFINEDREG_DEC_ERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Slave Interface Common Register Decode Error"] + #[inline(always)] + pub fn slvif_dec_err(&mut self) -> SLVIF_DEC_ERR_W { + SLVIF_DEC_ERR_W { w: self } + } + #[doc = "Bit 1 - Slave Interface Common Register Write to Read only Error"] + #[inline(always)] + pub fn slvif_wr2ro_err(&mut self) -> SLVIF_WR2RO_ERR_W { + SLVIF_WR2RO_ERR_W { w: self } + } + #[doc = "Bit 2 - Slave Interface Common Register Read to Write-only Error"] + #[inline(always)] + pub fn slvif_rd2wo_err(&mut self) -> SLVIF_RD2WO_ERR_W { + SLVIF_RD2WO_ERR_W { w: self } + } + #[doc = "Bit 3 - Slave Interface Common Register Write On Hold Error"] + #[inline(always)] + pub fn slvif_wronhold_err(&mut self) -> SLVIF_WRONHOLD_ERR_W { + SLVIF_WRONHOLD_ERR_W { w: self } + } + #[doc = "Bit 8 - Slave Interface Undefined Register Decode Error"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err(&mut self) -> SLVIF_UNDEFINEDREG_DEC_ERR_W { + SLVIF_UNDEFINEDREG_DEC_ERR_W { w: self } + } + } + } + #[doc = "Reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reset](reset) module"] + pub type RESET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RESET; + #[doc = "`read()` method returns [reset::R](reset::R) reader structure"] + impl crate::Readable for RESET {} + #[doc = "`write(|w| ..)` method takes [reset::W](reset::W) writer structure"] + impl crate::Writable for RESET {} + #[doc = "Reset register"] + pub mod reset { + #[doc = "Reader of register reset"] + pub type R = crate::R; + #[doc = "Writer for register reset"] + pub type W = crate::W; + #[doc = "Register reset `reset()`'s with value 0"] + impl crate::ResetValue for super::RESET { + type Type = u64; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rst`"] + pub type RST_R = crate::R; + #[doc = "Write proxy for field `rst`"] + pub struct RST_W<'a> { + w: &'a mut W, + } + impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u64) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - DMAC reset request bit"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - DMAC reset request bit"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + } + } +} +#[doc = "General Purpose Input/Output Interface"] +pub struct GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO {} +impl GPIO { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio::RegisterBlock { + 0x5020_0000 as *const _ + } +} +impl Deref for GPIO { + type Target = gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*GPIO::ptr() } + } +} +#[doc = "General Purpose Input/Output Interface"] +pub mod gpio { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Data (output) registers"] + pub data_output: DATA_OUTPUT, + #[doc = "0x04 - Data direction registers"] + pub direction: DIRECTION, + #[doc = "0x08 - Data source registers"] + pub source: SOURCE, + _reserved3: [u8; 36usize], + #[doc = "0x30 - Interrupt enable/disable registers"] + pub interrupt_enable: INTERRUPT_ENABLE, + #[doc = "0x34 - Interrupt mask registers"] + pub interrupt_mask: INTERRUPT_MASK, + #[doc = "0x38 - Interrupt level registers"] + pub interrupt_level: INTERRUPT_LEVEL, + #[doc = "0x3c - Interrupt polarity registers"] + pub interrupt_polarity: INTERRUPT_POLARITY, + #[doc = "0x40 - Interrupt status registers"] + pub interrupt_status: INTERRUPT_STATUS, + #[doc = "0x44 - Raw interrupt status registers"] + pub interrupt_status_raw: INTERRUPT_STATUS_RAW, + #[doc = "0x48 - Interrupt debounce registers"] + pub interrupt_debounce: INTERRUPT_DEBOUNCE, + #[doc = "0x4c - Registers for clearing interrupts"] + pub interrupt_clear: INTERRUPT_CLEAR, + #[doc = "0x50 - External port (data input) registers"] + pub data_input: DATA_INPUT, + _reserved12: [u8; 12usize], + #[doc = "0x60 - Sync level registers"] + pub sync_level: SYNC_LEVEL, + #[doc = "0x64 - ID code"] + pub id_code: ID_CODE, + #[doc = "0x68 - Interrupt both edge type"] + pub interrupt_bothedge: INTERRUPT_BOTHEDGE, + } + #[doc = "Data (output) registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_output](data_output) module"] + pub type DATA_OUTPUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_OUTPUT; + #[doc = "`read()` method returns [data_output::R](data_output::R) reader structure"] + impl crate::Readable for DATA_OUTPUT {} + #[doc = "`write(|w| ..)` method takes [data_output::W](data_output::W) writer structure"] + impl crate::Writable for DATA_OUTPUT {} + #[doc = "Data (output) registers"] + pub mod data_output { + #[doc = "Reader of register data_output"] + pub type R = crate::R; + #[doc = "Writer for register data_output"] + pub type W = crate::W; + #[doc = "Register data_output `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_OUTPUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-7)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-7)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + } + } + #[doc = "Data direction registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [direction](direction) module"] + pub type DIRECTION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DIRECTION; + #[doc = "`read()` method returns [direction::R](direction::R) reader structure"] + impl crate::Readable for DIRECTION {} + #[doc = "`write(|w| ..)` method takes [direction::W](direction::W) writer structure"] + impl crate::Writable for DIRECTION {} + #[doc = "Data direction registers"] + pub mod direction { + #[doc = "Reader of register direction"] + pub type R = crate::R; + #[doc = "Writer for register direction"] + pub type W = crate::W; + #[doc = "Register direction `reset()`'s with value 0"] + impl crate::ResetValue for super::DIRECTION { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum PIN_A { + #[doc = "0: Pin is input"] + INPUT = 0, + #[doc = "1: Pin is output"] + OUTPUT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: PIN_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of fields `pin(0-7)`"] + pub type PIN_R = crate::R; + impl PIN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIN_A { + match self.bits { + false => PIN_A::INPUT, + true => PIN_A::OUTPUT, + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == PIN_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == PIN_A::OUTPUT + } + } + #[doc = "Write proxy for fields `pin(0-7)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PIN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Pin is input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(PIN_A::INPUT) + } + #[doc = "Pin is output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(PIN_A::OUTPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + } + } + #[doc = "Data source registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [source](source) module"] + pub type SOURCE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SOURCE; + #[doc = "`read()` method returns [source::R](source::R) reader structure"] + impl crate::Readable for SOURCE {} + #[doc = "`write(|w| ..)` method takes [source::W](source::W) writer structure"] + impl crate::Writable for SOURCE {} + #[doc = "Data source registers"] + pub mod source { + #[doc = "Reader of register source"] + pub type R = crate::R; + #[doc = "Writer for register source"] + pub type W = crate::W; + #[doc = "Register source `reset()`'s with value 0"] + impl crate::ResetValue for super::SOURCE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt enable/disable registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_enable](interrupt_enable) module"] + pub type INTERRUPT_ENABLE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_ENABLE; + #[doc = "`read()` method returns [interrupt_enable::R](interrupt_enable::R) reader structure"] + impl crate::Readable for INTERRUPT_ENABLE {} + #[doc = "`write(|w| ..)` method takes [interrupt_enable::W](interrupt_enable::W) writer structure"] + impl crate::Writable for INTERRUPT_ENABLE {} + #[doc = "Interrupt enable/disable registers"] + pub mod interrupt_enable { + #[doc = "Reader of register interrupt_enable"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_enable"] + pub type W = crate::W; + #[doc = "Register interrupt_enable `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_ENABLE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt mask registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_mask](interrupt_mask) module"] + pub type INTERRUPT_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_MASK; + #[doc = "`read()` method returns [interrupt_mask::R](interrupt_mask::R) reader structure"] + impl crate::Readable for INTERRUPT_MASK {} + #[doc = "`write(|w| ..)` method takes [interrupt_mask::W](interrupt_mask::W) writer structure"] + impl crate::Writable for INTERRUPT_MASK {} + #[doc = "Interrupt mask registers"] + pub mod interrupt_mask { + #[doc = "Reader of register interrupt_mask"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_mask"] + pub type W = crate::W; + #[doc = "Register interrupt_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_MASK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt level registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_level](interrupt_level) module"] + pub type INTERRUPT_LEVEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_LEVEL; + #[doc = "`read()` method returns [interrupt_level::R](interrupt_level::R) reader structure"] + impl crate::Readable for INTERRUPT_LEVEL {} + #[doc = "`write(|w| ..)` method takes [interrupt_level::W](interrupt_level::W) writer structure"] + impl crate::Writable for INTERRUPT_LEVEL {} + #[doc = "Interrupt level registers"] + pub mod interrupt_level { + #[doc = "Reader of register interrupt_level"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_level"] + pub type W = crate::W; + #[doc = "Register interrupt_level `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_LEVEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt polarity registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_polarity](interrupt_polarity) module"] + pub type INTERRUPT_POLARITY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_POLARITY; + #[doc = "`read()` method returns [interrupt_polarity::R](interrupt_polarity::R) reader structure"] + impl crate::Readable for INTERRUPT_POLARITY {} + #[doc = "`write(|w| ..)` method takes [interrupt_polarity::W](interrupt_polarity::W) writer structure"] + impl crate::Writable for INTERRUPT_POLARITY {} + #[doc = "Interrupt polarity registers"] + pub mod interrupt_polarity { + #[doc = "Reader of register interrupt_polarity"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_polarity"] + pub type W = crate::W; + #[doc = "Register interrupt_polarity `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_POLARITY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt status registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_status](interrupt_status) module"] + pub type INTERRUPT_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_STATUS; + #[doc = "`read()` method returns [interrupt_status::R](interrupt_status::R) reader structure"] + impl crate::Readable for INTERRUPT_STATUS {} + #[doc = "`write(|w| ..)` method takes [interrupt_status::W](interrupt_status::W) writer structure"] + impl crate::Writable for INTERRUPT_STATUS {} + #[doc = "Interrupt status registers"] + pub mod interrupt_status { + #[doc = "Reader of register interrupt_status"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_status"] + pub type W = crate::W; + #[doc = "Register interrupt_status `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_STATUS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw interrupt status registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_status_raw](interrupt_status_raw) module"] + pub type INTERRUPT_STATUS_RAW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_STATUS_RAW; + #[doc = "`read()` method returns [interrupt_status_raw::R](interrupt_status_raw::R) reader structure"] + impl crate::Readable for INTERRUPT_STATUS_RAW {} + #[doc = "`write(|w| ..)` method takes [interrupt_status_raw::W](interrupt_status_raw::W) writer structure"] + impl crate::Writable for INTERRUPT_STATUS_RAW {} + #[doc = "Raw interrupt status registers"] + pub mod interrupt_status_raw { + #[doc = "Reader of register interrupt_status_raw"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_status_raw"] + pub type W = crate::W; + #[doc = "Register interrupt_status_raw `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_STATUS_RAW { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt debounce registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_debounce](interrupt_debounce) module"] + pub type INTERRUPT_DEBOUNCE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_DEBOUNCE; + #[doc = "`read()` method returns [interrupt_debounce::R](interrupt_debounce::R) reader structure"] + impl crate::Readable for INTERRUPT_DEBOUNCE {} + #[doc = "`write(|w| ..)` method takes [interrupt_debounce::W](interrupt_debounce::W) writer structure"] + impl crate::Writable for INTERRUPT_DEBOUNCE {} + #[doc = "Interrupt debounce registers"] + pub mod interrupt_debounce { + #[doc = "Reader of register interrupt_debounce"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_debounce"] + pub type W = crate::W; + #[doc = "Register interrupt_debounce `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_DEBOUNCE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Registers for clearing interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_clear](interrupt_clear) module"] + pub type INTERRUPT_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_CLEAR; + #[doc = "`read()` method returns [interrupt_clear::R](interrupt_clear::R) reader structure"] + impl crate::Readable for INTERRUPT_CLEAR {} + #[doc = "`write(|w| ..)` method takes [interrupt_clear::W](interrupt_clear::W) writer structure"] + impl crate::Writable for INTERRUPT_CLEAR {} + #[doc = "Registers for clearing interrupts"] + pub mod interrupt_clear { + #[doc = "Reader of register interrupt_clear"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_clear"] + pub type W = crate::W; + #[doc = "Register interrupt_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_CLEAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "External port (data input) registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_input](data_input) module"] + pub type DATA_INPUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_INPUT; + #[doc = "`read()` method returns [data_input::R](data_input::R) reader structure"] + impl crate::Readable for DATA_INPUT {} + #[doc = "`write(|w| ..)` method takes [data_input::W](data_input::W) writer structure"] + impl crate::Writable for DATA_INPUT {} + #[doc = "External port (data input) registers"] + pub mod data_input { + #[doc = "Reader of register data_input"] + pub type R = crate::R; + #[doc = "Writer for register data_input"] + pub type W = crate::W; + #[doc = "Register data_input `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_INPUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `pin(0-7)`"] + pub type PIN_R = crate::R; + #[doc = "Write proxy for fields `pin(0-7)`"] + pub struct PIN_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> PIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << self.offset)) + | (((value as u32) & 0x01) << self.offset); + self.w + } + } + impl R { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&self, n: usize) -> PIN_R { + PIN_R::new(((self.bits >> n) & 0x01) != 0) + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&self) -> PIN_R { + PIN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&self) -> PIN_R { + PIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&self) -> PIN_R { + PIN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&self) -> PIN_R { + PIN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&self) -> PIN_R { + PIN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&self) -> PIN_R { + PIN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&self) -> PIN_R { + PIN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&self) -> PIN_R { + PIN_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = ""] + #[inline(always)] + pub unsafe fn pin(&mut self, n: usize) -> PIN_W { + PIN_W { w: self, offset: n } + } + #[doc = "Bit 0"] + #[inline(always)] + pub fn pin0(&mut self) -> PIN_W { + PIN_W { w: self, offset: 0 } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin1(&mut self) -> PIN_W { + PIN_W { w: self, offset: 1 } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pin2(&mut self) -> PIN_W { + PIN_W { w: self, offset: 2 } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn pin3(&mut self) -> PIN_W { + PIN_W { w: self, offset: 3 } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn pin4(&mut self) -> PIN_W { + PIN_W { w: self, offset: 4 } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn pin5(&mut self) -> PIN_W { + PIN_W { w: self, offset: 5 } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn pin6(&mut self) -> PIN_W { + PIN_W { w: self, offset: 6 } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn pin7(&mut self) -> PIN_W { + PIN_W { w: self, offset: 7 } + } + } + } + #[doc = "Sync level registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sync_level](sync_level) module"] + pub type SYNC_LEVEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SYNC_LEVEL; + #[doc = "`read()` method returns [sync_level::R](sync_level::R) reader structure"] + impl crate::Readable for SYNC_LEVEL {} + #[doc = "`write(|w| ..)` method takes [sync_level::W](sync_level::W) writer structure"] + impl crate::Writable for SYNC_LEVEL {} + #[doc = "Sync level registers"] + pub mod sync_level { + #[doc = "Reader of register sync_level"] + pub type R = crate::R; + #[doc = "Writer for register sync_level"] + pub type W = crate::W; + #[doc = "Register sync_level `reset()`'s with value 0"] + impl crate::ResetValue for super::SYNC_LEVEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "ID code\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id_code](id_code) module"] + pub type ID_CODE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ID_CODE; + #[doc = "`read()` method returns [id_code::R](id_code::R) reader structure"] + impl crate::Readable for ID_CODE {} + #[doc = "`write(|w| ..)` method takes [id_code::W](id_code::W) writer structure"] + impl crate::Writable for ID_CODE {} + #[doc = "ID code"] + pub mod id_code { + #[doc = "Reader of register id_code"] + pub type R = crate::R; + #[doc = "Writer for register id_code"] + pub type W = crate::W; + #[doc = "Register id_code `reset()`'s with value 0"] + impl crate::ResetValue for super::ID_CODE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt both edge type\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_bothedge](interrupt_bothedge) module"] + pub type INTERRUPT_BOTHEDGE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_BOTHEDGE; + #[doc = "`read()` method returns [interrupt_bothedge::R](interrupt_bothedge::R) reader structure"] + impl crate::Readable for INTERRUPT_BOTHEDGE {} + #[doc = "`write(|w| ..)` method takes [interrupt_bothedge::W](interrupt_bothedge::W) writer structure"] + impl crate::Writable for INTERRUPT_BOTHEDGE {} + #[doc = "Interrupt both edge type"] + pub mod interrupt_bothedge { + #[doc = "Reader of register interrupt_bothedge"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_bothedge"] + pub type W = crate::W; + #[doc = "Register interrupt_bothedge `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_BOTHEDGE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 1"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + 0x5021_0000 as *const _ + } +} +impl Deref for UART1 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UART1::ptr() } + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 1"] +pub mod uart1 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)"] + pub rbr_dll_thr: RBR_DLL_THR, + #[doc = "0x04 - Divisor Latch (High) / Interrupt Enable Register"] + pub dlh_ier: DLH_IER, + #[doc = "0x08 - FIFO Control Register / Interrupt Identification Register"] + pub fcr_iir: FCR_IIR, + #[doc = "0x0c - Line Control Register"] + pub lcr: LCR, + #[doc = "0x10 - Modem Control Register"] + pub mcr: MCR, + #[doc = "0x14 - Line Status Register"] + pub lsr: LSR, + #[doc = "0x18 - Modem Status Register"] + pub msr: MSR, + #[doc = "0x1c - Scratchpad Register"] + pub scr: SCR, + #[doc = "0x20 - Low Power Divisor Latch (Low) Register"] + pub lpdll: LPDLL, + #[doc = "0x24 - Low Power Divisor Latch (High) Register"] + pub lpdlh: LPDLH, + _reserved10: [u8; 8usize], + #[doc = "0x30 - Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)"] + pub srbr_sthr: [SRBR_STHR; 16], + #[doc = "0x70 - FIFO Access Register"] + pub far: FAR, + #[doc = "0x74 - Transmit FIFO Read Register"] + pub tfr: TFR, + #[doc = "0x78 - Receive FIFO Write Register"] + pub rfw: RFW, + #[doc = "0x7c - UART Status Register"] + pub usr: USR, + #[doc = "0x80 - Transmit FIFO Level"] + pub tfl: TFL, + #[doc = "0x84 - Receive FIFO Level"] + pub rfl: RFL, + #[doc = "0x88 - Software Reset Register"] + pub srr: SRR, + #[doc = "0x8c - Shadow Request to Send Register"] + pub srts: SRTS, + #[doc = "0x90 - Shadow Break Control Register"] + pub sbcr: SBCR, + #[doc = "0x94 - Shadow DMA Mode"] + pub sdmam: SDMAM, + #[doc = "0x98 - Shadow FIFO Enable"] + pub sfe: SFE, + #[doc = "0x9c - Shadow RCVR Trigger Register"] + pub srt: SRT, + #[doc = "0xa0 - Shadow TX Empty Trigger Register"] + pub stet: STET, + #[doc = "0xa4 - Halt TX Regster"] + pub htx: HTX, + #[doc = "0xa8 - DMA Software Acknowledge Register"] + pub dmasa: DMASA, + #[doc = "0xac - Transfer Control Register"] + pub tcr: TCR, + #[doc = "0xb0 - DE Enable Register"] + pub de_en: DE_EN, + #[doc = "0xb4 - RE Enable Register"] + pub re_en: RE_EN, + #[doc = "0xb8 - DE Assertion Time Register"] + pub det: DET, + #[doc = "0xbc - Turn-Around Time Register"] + pub tat: TAT, + #[doc = "0xc0 - Divisor Latch (Fractional) Register"] + pub dlf: DLF, + #[doc = "0xc4 - Receive-Mode Address Register"] + pub rar: RAR, + #[doc = "0xc8 - Transmit-Mode Address Register"] + pub tar: TAR, + #[doc = "0xcc - Line Control Register (Extended)"] + pub lcr_ext: LCR_EXT, + _reserved35: [u8; 36usize], + #[doc = "0xf4 - Component Parameter Register"] + pub cpr: CPR, + #[doc = "0xf8 - UART Component Version"] + pub ucv: UCV, + #[doc = "0xfc - Component Type Register"] + pub ctr: CTR, + } + #[doc = "Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rbr_dll_thr](rbr_dll_thr) module"] + pub type RBR_DLL_THR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RBR_DLL_THR; + #[doc = "`read()` method returns [rbr_dll_thr::R](rbr_dll_thr::R) reader structure"] + impl crate::Readable for RBR_DLL_THR {} + #[doc = "`write(|w| ..)` method takes [rbr_dll_thr::W](rbr_dll_thr::W) writer structure"] + impl crate::Writable for RBR_DLL_THR {} + #[doc = "Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)"] + pub mod rbr_dll_thr { + #[doc = "Reader of register rbr_dll_thr"] + pub type R = crate::R; + #[doc = "Writer for register rbr_dll_thr"] + pub type W = crate::W; + #[doc = "Register rbr_dll_thr `reset()`'s with value 0"] + impl crate::ResetValue for super::RBR_DLL_THR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Divisor Latch (High) / Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlh_ier](dlh_ier) module"] + pub type DLH_IER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DLH_IER; + #[doc = "`read()` method returns [dlh_ier::R](dlh_ier::R) reader structure"] + impl crate::Readable for DLH_IER {} + #[doc = "`write(|w| ..)` method takes [dlh_ier::W](dlh_ier::W) writer structure"] + impl crate::Writable for DLH_IER {} + #[doc = "Divisor Latch (High) / Interrupt Enable Register"] + pub mod dlh_ier { + #[doc = "Reader of register dlh_ier"] + pub type R = crate::R; + #[doc = "Writer for register dlh_ier"] + pub type W = crate::W; + #[doc = "Register dlh_ier `reset()`'s with value 0"] + impl crate::ResetValue for super::DLH_IER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FIFO Control Register / Interrupt Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcr_iir](fcr_iir) module"] + pub type FCR_IIR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FCR_IIR; + #[doc = "`read()` method returns [fcr_iir::R](fcr_iir::R) reader structure"] + impl crate::Readable for FCR_IIR {} + #[doc = "`write(|w| ..)` method takes [fcr_iir::W](fcr_iir::W) writer structure"] + impl crate::Writable for FCR_IIR {} + #[doc = "FIFO Control Register / Interrupt Identification Register"] + pub mod fcr_iir { + #[doc = "Reader of register fcr_iir"] + pub type R = crate::R; + #[doc = "Writer for register fcr_iir"] + pub type W = crate::W; + #[doc = "Register fcr_iir `reset()`'s with value 0"] + impl crate::ResetValue for super::FCR_IIR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](lcr) module"] + pub type LCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LCR; + #[doc = "`read()` method returns [lcr::R](lcr::R) reader structure"] + impl crate::Readable for LCR {} + #[doc = "`write(|w| ..)` method takes [lcr::W](lcr::W) writer structure"] + impl crate::Writable for LCR {} + #[doc = "Line Control Register"] + pub mod lcr { + #[doc = "Reader of register lcr"] + pub type R = crate::R; + #[doc = "Writer for register lcr"] + pub type W = crate::W; + #[doc = "Register lcr `reset()`'s with value 0"] + impl crate::ResetValue for super::LCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Modem Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](mcr) module"] + pub type MCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MCR; + #[doc = "`read()` method returns [mcr::R](mcr::R) reader structure"] + impl crate::Readable for MCR {} + #[doc = "`write(|w| ..)` method takes [mcr::W](mcr::W) writer structure"] + impl crate::Writable for MCR {} + #[doc = "Modem Control Register"] + pub mod mcr { + #[doc = "Reader of register mcr"] + pub type R = crate::R; + #[doc = "Writer for register mcr"] + pub type W = crate::W; + #[doc = "Register mcr `reset()`'s with value 0"] + impl crate::ResetValue for super::MCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Line Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](lsr) module"] + pub type LSR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LSR; + #[doc = "`read()` method returns [lsr::R](lsr::R) reader structure"] + impl crate::Readable for LSR {} + #[doc = "`write(|w| ..)` method takes [lsr::W](lsr::W) writer structure"] + impl crate::Writable for LSR {} + #[doc = "Line Status Register"] + pub mod lsr { + #[doc = "Reader of register lsr"] + pub type R = crate::R; + #[doc = "Writer for register lsr"] + pub type W = crate::W; + #[doc = "Register lsr `reset()`'s with value 0"] + impl crate::ResetValue for super::LSR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Modem Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](msr) module"] + pub type MSR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSR; + #[doc = "`read()` method returns [msr::R](msr::R) reader structure"] + impl crate::Readable for MSR {} + #[doc = "`write(|w| ..)` method takes [msr::W](msr::W) writer structure"] + impl crate::Writable for MSR {} + #[doc = "Modem Status Register"] + pub mod msr { + #[doc = "Reader of register msr"] + pub type R = crate::R; + #[doc = "Writer for register msr"] + pub type W = crate::W; + #[doc = "Register msr `reset()`'s with value 0"] + impl crate::ResetValue for super::MSR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Scratchpad Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](scr) module"] + pub type SCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SCR; + #[doc = "`read()` method returns [scr::R](scr::R) reader structure"] + impl crate::Readable for SCR {} + #[doc = "`write(|w| ..)` method takes [scr::W](scr::W) writer structure"] + impl crate::Writable for SCR {} + #[doc = "Scratchpad Register"] + pub mod scr { + #[doc = "Reader of register scr"] + pub type R = crate::R; + #[doc = "Writer for register scr"] + pub type W = crate::W; + #[doc = "Register scr `reset()`'s with value 0"] + impl crate::ResetValue for super::SCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Low Power Divisor Latch (Low) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpdll](lpdll) module"] + pub type LPDLL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LPDLL; + #[doc = "`read()` method returns [lpdll::R](lpdll::R) reader structure"] + impl crate::Readable for LPDLL {} + #[doc = "`write(|w| ..)` method takes [lpdll::W](lpdll::W) writer structure"] + impl crate::Writable for LPDLL {} + #[doc = "Low Power Divisor Latch (Low) Register"] + pub mod lpdll { + #[doc = "Reader of register lpdll"] + pub type R = crate::R; + #[doc = "Writer for register lpdll"] + pub type W = crate::W; + #[doc = "Register lpdll `reset()`'s with value 0"] + impl crate::ResetValue for super::LPDLL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Low Power Divisor Latch (High) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpdlh](lpdlh) module"] + pub type LPDLH = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LPDLH; + #[doc = "`read()` method returns [lpdlh::R](lpdlh::R) reader structure"] + impl crate::Readable for LPDLH {} + #[doc = "`write(|w| ..)` method takes [lpdlh::W](lpdlh::W) writer structure"] + impl crate::Writable for LPDLH {} + #[doc = "Low Power Divisor Latch (High) Register"] + pub mod lpdlh { + #[doc = "Reader of register lpdlh"] + pub type R = crate::R; + #[doc = "Writer for register lpdlh"] + pub type W = crate::W; + #[doc = "Register lpdlh `reset()`'s with value 0"] + impl crate::ResetValue for super::LPDLH { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srbr_sthr](srbr_sthr) module"] + pub type SRBR_STHR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRBR_STHR; + #[doc = "`read()` method returns [srbr_sthr::R](srbr_sthr::R) reader structure"] + impl crate::Readable for SRBR_STHR {} + #[doc = "`write(|w| ..)` method takes [srbr_sthr::W](srbr_sthr::W) writer structure"] + impl crate::Writable for SRBR_STHR {} + #[doc = "Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)"] + pub mod srbr_sthr { + #[doc = "Reader of register srbr_sthr[%s]"] + pub type R = crate::R; + #[doc = "Writer for register srbr_sthr[%s]"] + pub type W = crate::W; + #[doc = "Register srbr_sthr[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::SRBR_STHR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FIFO Access Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [far](far) module"] + pub type FAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FAR; + #[doc = "`read()` method returns [far::R](far::R) reader structure"] + impl crate::Readable for FAR {} + #[doc = "`write(|w| ..)` method takes [far::W](far::W) writer structure"] + impl crate::Writable for FAR {} + #[doc = "FIFO Access Register"] + pub mod far { + #[doc = "Reader of register far"] + pub type R = crate::R; + #[doc = "Writer for register far"] + pub type W = crate::W; + #[doc = "Register far `reset()`'s with value 0"] + impl crate::ResetValue for super::FAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Read Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfr](tfr) module"] + pub type TFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFR; + #[doc = "`read()` method returns [tfr::R](tfr::R) reader structure"] + impl crate::Readable for TFR {} + #[doc = "`write(|w| ..)` method takes [tfr::W](tfr::W) writer structure"] + impl crate::Writable for TFR {} + #[doc = "Transmit FIFO Read Register"] + pub mod tfr { + #[doc = "Reader of register tfr"] + pub type R = crate::R; + #[doc = "Writer for register tfr"] + pub type W = crate::W; + #[doc = "Register tfr `reset()`'s with value 0"] + impl crate::ResetValue for super::TFR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Write Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfw](rfw) module"] + pub type RFW = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFW; + #[doc = "`read()` method returns [rfw::R](rfw::R) reader structure"] + impl crate::Readable for RFW {} + #[doc = "`write(|w| ..)` method takes [rfw::W](rfw::W) writer structure"] + impl crate::Writable for RFW {} + #[doc = "Receive FIFO Write Register"] + pub mod rfw { + #[doc = "Reader of register rfw"] + pub type R = crate::R; + #[doc = "Writer for register rfw"] + pub type W = crate::W; + #[doc = "Register rfw `reset()`'s with value 0"] + impl crate::ResetValue for super::RFW { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "UART Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usr](usr) module"] + pub type USR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _USR; + #[doc = "`read()` method returns [usr::R](usr::R) reader structure"] + impl crate::Readable for USR {} + #[doc = "`write(|w| ..)` method takes [usr::W](usr::W) writer structure"] + impl crate::Writable for USR {} + #[doc = "UART Status Register"] + pub mod usr { + #[doc = "Reader of register usr"] + pub type R = crate::R; + #[doc = "Writer for register usr"] + pub type W = crate::W; + #[doc = "Register usr `reset()`'s with value 0"] + impl crate::ResetValue for super::USR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfl](tfl) module"] + pub type TFL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFL; + #[doc = "`read()` method returns [tfl::R](tfl::R) reader structure"] + impl crate::Readable for TFL {} + #[doc = "`write(|w| ..)` method takes [tfl::W](tfl::W) writer structure"] + impl crate::Writable for TFL {} + #[doc = "Transmit FIFO Level"] + pub mod tfl { + #[doc = "Reader of register tfl"] + pub type R = crate::R; + #[doc = "Writer for register tfl"] + pub type W = crate::W; + #[doc = "Register tfl `reset()`'s with value 0"] + impl crate::ResetValue for super::TFL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfl](rfl) module"] + pub type RFL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFL; + #[doc = "`read()` method returns [rfl::R](rfl::R) reader structure"] + impl crate::Readable for RFL {} + #[doc = "`write(|w| ..)` method takes [rfl::W](rfl::W) writer structure"] + impl crate::Writable for RFL {} + #[doc = "Receive FIFO Level"] + pub mod rfl { + #[doc = "Reader of register rfl"] + pub type R = crate::R; + #[doc = "Writer for register rfl"] + pub type W = crate::W; + #[doc = "Register rfl `reset()`'s with value 0"] + impl crate::ResetValue for super::RFL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Software Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srr](srr) module"] + pub type SRR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRR; + #[doc = "`read()` method returns [srr::R](srr::R) reader structure"] + impl crate::Readable for SRR {} + #[doc = "`write(|w| ..)` method takes [srr::W](srr::W) writer structure"] + impl crate::Writable for SRR {} + #[doc = "Software Reset Register"] + pub mod srr { + #[doc = "Reader of register srr"] + pub type R = crate::R; + #[doc = "Writer for register srr"] + pub type W = crate::W; + #[doc = "Register srr `reset()`'s with value 0"] + impl crate::ResetValue for super::SRR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow Request to Send Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srts](srts) module"] + pub type SRTS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRTS; + #[doc = "`read()` method returns [srts::R](srts::R) reader structure"] + impl crate::Readable for SRTS {} + #[doc = "`write(|w| ..)` method takes [srts::W](srts::W) writer structure"] + impl crate::Writable for SRTS {} + #[doc = "Shadow Request to Send Register"] + pub mod srts { + #[doc = "Reader of register srts"] + pub type R = crate::R; + #[doc = "Writer for register srts"] + pub type W = crate::W; + #[doc = "Register srts `reset()`'s with value 0"] + impl crate::ResetValue for super::SRTS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow Break Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sbcr](sbcr) module"] + pub type SBCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SBCR; + #[doc = "`read()` method returns [sbcr::R](sbcr::R) reader structure"] + impl crate::Readable for SBCR {} + #[doc = "`write(|w| ..)` method takes [sbcr::W](sbcr::W) writer structure"] + impl crate::Writable for SBCR {} + #[doc = "Shadow Break Control Register"] + pub mod sbcr { + #[doc = "Reader of register sbcr"] + pub type R = crate::R; + #[doc = "Writer for register sbcr"] + pub type W = crate::W; + #[doc = "Register sbcr `reset()`'s with value 0"] + impl crate::ResetValue for super::SBCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow DMA Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdmam](sdmam) module"] + pub type SDMAM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SDMAM; + #[doc = "`read()` method returns [sdmam::R](sdmam::R) reader structure"] + impl crate::Readable for SDMAM {} + #[doc = "`write(|w| ..)` method takes [sdmam::W](sdmam::W) writer structure"] + impl crate::Writable for SDMAM {} + #[doc = "Shadow DMA Mode"] + pub mod sdmam { + #[doc = "Reader of register sdmam"] + pub type R = crate::R; + #[doc = "Writer for register sdmam"] + pub type W = crate::W; + #[doc = "Register sdmam `reset()`'s with value 0"] + impl crate::ResetValue for super::SDMAM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow FIFO Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfe](sfe) module"] + pub type SFE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SFE; + #[doc = "`read()` method returns [sfe::R](sfe::R) reader structure"] + impl crate::Readable for SFE {} + #[doc = "`write(|w| ..)` method takes [sfe::W](sfe::W) writer structure"] + impl crate::Writable for SFE {} + #[doc = "Shadow FIFO Enable"] + pub mod sfe { + #[doc = "Reader of register sfe"] + pub type R = crate::R; + #[doc = "Writer for register sfe"] + pub type W = crate::W; + #[doc = "Register sfe `reset()`'s with value 0"] + impl crate::ResetValue for super::SFE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow RCVR Trigger Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [srt](srt) module"] + pub type SRT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SRT; + #[doc = "`read()` method returns [srt::R](srt::R) reader structure"] + impl crate::Readable for SRT {} + #[doc = "`write(|w| ..)` method takes [srt::W](srt::W) writer structure"] + impl crate::Writable for SRT {} + #[doc = "Shadow RCVR Trigger Register"] + pub mod srt { + #[doc = "Reader of register srt"] + pub type R = crate::R; + #[doc = "Writer for register srt"] + pub type W = crate::W; + #[doc = "Register srt `reset()`'s with value 0"] + impl crate::ResetValue for super::SRT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Shadow TX Empty Trigger Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stet](stet) module"] + pub type STET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STET; + #[doc = "`read()` method returns [stet::R](stet::R) reader structure"] + impl crate::Readable for STET {} + #[doc = "`write(|w| ..)` method takes [stet::W](stet::W) writer structure"] + impl crate::Writable for STET {} + #[doc = "Shadow TX Empty Trigger Register"] + pub mod stet { + #[doc = "Reader of register stet"] + pub type R = crate::R; + #[doc = "Writer for register stet"] + pub type W = crate::W; + #[doc = "Register stet `reset()`'s with value 0"] + impl crate::ResetValue for super::STET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Halt TX Regster\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [htx](htx) module"] + pub type HTX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _HTX; + #[doc = "`read()` method returns [htx::R](htx::R) reader structure"] + impl crate::Readable for HTX {} + #[doc = "`write(|w| ..)` method takes [htx::W](htx::W) writer structure"] + impl crate::Writable for HTX {} + #[doc = "Halt TX Regster"] + pub mod htx { + #[doc = "Reader of register htx"] + pub type R = crate::R; + #[doc = "Writer for register htx"] + pub type W = crate::W; + #[doc = "Register htx `reset()`'s with value 0"] + impl crate::ResetValue for super::HTX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Software Acknowledge Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasa](dmasa) module"] + pub type DMASA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMASA; + #[doc = "`read()` method returns [dmasa::R](dmasa::R) reader structure"] + impl crate::Readable for DMASA {} + #[doc = "`write(|w| ..)` method takes [dmasa::W](dmasa::W) writer structure"] + impl crate::Writable for DMASA {} + #[doc = "DMA Software Acknowledge Register"] + pub mod dmasa { + #[doc = "Reader of register dmasa"] + pub type R = crate::R; + #[doc = "Writer for register dmasa"] + pub type W = crate::W; + #[doc = "Register dmasa `reset()`'s with value 0"] + impl crate::ResetValue for super::DMASA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transfer Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](tcr) module"] + pub type TCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TCR; + #[doc = "`read()` method returns [tcr::R](tcr::R) reader structure"] + impl crate::Readable for TCR {} + #[doc = "`write(|w| ..)` method takes [tcr::W](tcr::W) writer structure"] + impl crate::Writable for TCR {} + #[doc = "Transfer Control Register"] + pub mod tcr { + #[doc = "Reader of register tcr"] + pub type R = crate::R; + #[doc = "Writer for register tcr"] + pub type W = crate::W; + #[doc = "Register tcr `reset()`'s with value 0"] + impl crate::ResetValue for super::TCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DE Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [de_en](de_en) module"] + pub type DE_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DE_EN; + #[doc = "`read()` method returns [de_en::R](de_en::R) reader structure"] + impl crate::Readable for DE_EN {} + #[doc = "`write(|w| ..)` method takes [de_en::W](de_en::W) writer structure"] + impl crate::Writable for DE_EN {} + #[doc = "DE Enable Register"] + pub mod de_en { + #[doc = "Reader of register de_en"] + pub type R = crate::R; + #[doc = "Writer for register de_en"] + pub type W = crate::W; + #[doc = "Register de_en `reset()`'s with value 0"] + impl crate::ResetValue for super::DE_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RE Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [re_en](re_en) module"] + pub type RE_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RE_EN; + #[doc = "`read()` method returns [re_en::R](re_en::R) reader structure"] + impl crate::Readable for RE_EN {} + #[doc = "`write(|w| ..)` method takes [re_en::W](re_en::W) writer structure"] + impl crate::Writable for RE_EN {} + #[doc = "RE Enable Register"] + pub mod re_en { + #[doc = "Reader of register re_en"] + pub type R = crate::R; + #[doc = "Writer for register re_en"] + pub type W = crate::W; + #[doc = "Register re_en `reset()`'s with value 0"] + impl crate::ResetValue for super::RE_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DE Assertion Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [det](det) module"] + pub type DET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DET; + #[doc = "`read()` method returns [det::R](det::R) reader structure"] + impl crate::Readable for DET {} + #[doc = "`write(|w| ..)` method takes [det::W](det::W) writer structure"] + impl crate::Writable for DET {} + #[doc = "DE Assertion Time Register"] + pub mod det { + #[doc = "Reader of register det"] + pub type R = crate::R; + #[doc = "Writer for register det"] + pub type W = crate::W; + #[doc = "Register det `reset()`'s with value 0"] + impl crate::ResetValue for super::DET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Turn-Around Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tat](tat) module"] + pub type TAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAT; + #[doc = "`read()` method returns [tat::R](tat::R) reader structure"] + impl crate::Readable for TAT {} + #[doc = "`write(|w| ..)` method takes [tat::W](tat::W) writer structure"] + impl crate::Writable for TAT {} + #[doc = "Turn-Around Time Register"] + pub mod tat { + #[doc = "Reader of register tat"] + pub type R = crate::R; + #[doc = "Writer for register tat"] + pub type W = crate::W; + #[doc = "Register tat `reset()`'s with value 0"] + impl crate::ResetValue for super::TAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Divisor Latch (Fractional) Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlf](dlf) module"] + pub type DLF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DLF; + #[doc = "`read()` method returns [dlf::R](dlf::R) reader structure"] + impl crate::Readable for DLF {} + #[doc = "`write(|w| ..)` method takes [dlf::W](dlf::W) writer structure"] + impl crate::Writable for DLF {} + #[doc = "Divisor Latch (Fractional) Register"] + pub mod dlf { + #[doc = "Reader of register dlf"] + pub type R = crate::R; + #[doc = "Writer for register dlf"] + pub type W = crate::W; + #[doc = "Register dlf `reset()`'s with value 0"] + impl crate::ResetValue for super::DLF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive-Mode Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rar](rar) module"] + pub type RAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RAR; + #[doc = "`read()` method returns [rar::R](rar::R) reader structure"] + impl crate::Readable for RAR {} + #[doc = "`write(|w| ..)` method takes [rar::W](rar::W) writer structure"] + impl crate::Writable for RAR {} + #[doc = "Receive-Mode Address Register"] + pub mod rar { + #[doc = "Reader of register rar"] + pub type R = crate::R; + #[doc = "Writer for register rar"] + pub type W = crate::W; + #[doc = "Register rar `reset()`'s with value 0"] + impl crate::ResetValue for super::RAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit-Mode Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tar](tar) module"] + pub type TAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAR; + #[doc = "`read()` method returns [tar::R](tar::R) reader structure"] + impl crate::Readable for TAR {} + #[doc = "`write(|w| ..)` method takes [tar::W](tar::W) writer structure"] + impl crate::Writable for TAR {} + #[doc = "Transmit-Mode Address Register"] + pub mod tar { + #[doc = "Reader of register tar"] + pub type R = crate::R; + #[doc = "Writer for register tar"] + pub type W = crate::W; + #[doc = "Register tar `reset()`'s with value 0"] + impl crate::ResetValue for super::TAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Line Control Register (Extended)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_ext](lcr_ext) module"] + pub type LCR_EXT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LCR_EXT; + #[doc = "`read()` method returns [lcr_ext::R](lcr_ext::R) reader structure"] + impl crate::Readable for LCR_EXT {} + #[doc = "`write(|w| ..)` method takes [lcr_ext::W](lcr_ext::W) writer structure"] + impl crate::Writable for LCR_EXT {} + #[doc = "Line Control Register (Extended)"] + pub mod lcr_ext { + #[doc = "Reader of register lcr_ext"] + pub type R = crate::R; + #[doc = "Writer for register lcr_ext"] + pub type W = crate::W; + #[doc = "Register lcr_ext `reset()`'s with value 0"] + impl crate::ResetValue for super::LCR_EXT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Parameter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpr](cpr) module"] + pub type CPR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CPR; + #[doc = "`read()` method returns [cpr::R](cpr::R) reader structure"] + impl crate::Readable for CPR {} + #[doc = "`write(|w| ..)` method takes [cpr::W](cpr::W) writer structure"] + impl crate::Writable for CPR {} + #[doc = "Component Parameter Register"] + pub mod cpr { + #[doc = "Reader of register cpr"] + pub type R = crate::R; + #[doc = "Writer for register cpr"] + pub type W = crate::W; + #[doc = "Register cpr `reset()`'s with value 0"] + impl crate::ResetValue for super::CPR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "UART Component Version\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucv](ucv) module"] + pub type UCV = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _UCV; + #[doc = "`read()` method returns [ucv::R](ucv::R) reader structure"] + impl crate::Readable for UCV {} + #[doc = "`write(|w| ..)` method takes [ucv::W](ucv::W) writer structure"] + impl crate::Writable for UCV {} + #[doc = "UART Component Version"] + pub mod ucv { + #[doc = "Reader of register ucv"] + pub type R = crate::R; + #[doc = "Writer for register ucv"] + pub type W = crate::W; + #[doc = "Register ucv `reset()`'s with value 0"] + impl crate::ResetValue for super::UCV { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctr](ctr) module"] + pub type CTR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTR; + #[doc = "`read()` method returns [ctr::R](ctr::R) reader structure"] + impl crate::Readable for CTR {} + #[doc = "`write(|w| ..)` method takes [ctr::W](ctr::W) writer structure"] + impl crate::Writable for CTR {} + #[doc = "Component Type Register"] + pub mod ctr { + #[doc = "Reader of register ctr"] + pub type R = crate::R; + #[doc = "Writer for register ctr"] + pub type W = crate::W; + #[doc = "Register ctr `reset()`'s with value 0"] + impl crate::ResetValue for super::CTR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 2"] +pub struct UART2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART2 {} +impl UART2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + 0x5022_0000 as *const _ + } +} +impl Deref for UART2 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UART2::ptr() } + } +} +#[doc = "Universal Asynchronous Receiver-Transmitter 3"] +pub struct UART3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART3 {} +impl UART3 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + 0x5023_0000 as *const _ + } +} +impl Deref for UART3 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*UART3::ptr() } + } +} +#[doc = "Serial Peripheral Interface 0 (master)"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + 0x5200_0000 as *const _ + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI0::ptr() } + } +} +#[doc = "Serial Peripheral Interface 0 (master)"] +pub mod spi0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register 0"] + pub ctrlr0: CTRLR0, + #[doc = "0x04 - Control Register 1"] + pub ctrlr1: CTRLR1, + #[doc = "0x08 - Enable Register"] + pub ssienr: SSIENR, + #[doc = "0x0c - Microwire Control Register"] + pub mwcr: MWCR, + #[doc = "0x10 - Slave Enable Register"] + pub ser: SER, + #[doc = "0x14 - Baud Rate Select"] + pub baudr: BAUDR, + #[doc = "0x18 - Transmit FIFO Threshold Level"] + pub txftlr: TXFTLR, + #[doc = "0x1c - Receive FIFO Threshold Level"] + pub rxftlr: RXFTLR, + #[doc = "0x20 - Transmit FIFO Level Register"] + pub txflr: TXFLR, + #[doc = "0x24 - Receive FIFO Level Register"] + pub rxflr: RXFLR, + #[doc = "0x28 - Status Register"] + pub sr: SR, + #[doc = "0x2c - Interrupt Mask Register"] + pub imr: IMR, + #[doc = "0x30 - Interrupt Status Register"] + pub isr: ISR, + #[doc = "0x34 - Raw Interrupt Status Register"] + pub risr: RISR, + #[doc = "0x38 - Transmit FIFO Overflow Interrupt Clear Register"] + pub txoicr: TXOICR, + #[doc = "0x3c - Receive FIFO Overflow Interrupt Clear Register"] + pub rxoicr: RXOICR, + #[doc = "0x40 - Receive FIFO Underflow Interrupt Clear Register"] + pub rxuicr: RXUICR, + #[doc = "0x44 - Multi-Master Interrupt Clear Register"] + pub msticr: MSTICR, + #[doc = "0x48 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x4c - DMA Control Register"] + pub dmacr: DMACR, + #[doc = "0x50 - DMA Transmit Data Level"] + pub dmatdlr: DMATDLR, + #[doc = "0x54 - DMA Receive Data Level"] + pub dmardlr: DMARDLR, + #[doc = "0x58 - Identification Register"] + pub idr: IDR, + #[doc = "0x5c - DWC_ssi component version"] + pub ssic_version_id: SSIC_VERSION_ID, + #[doc = "0x60 - Data Register"] + pub dr: [DR; 36], + #[doc = "0xf0 - RX Sample Delay Register"] + pub rx_sample_delay: RX_SAMPLE_DELAY, + #[doc = "0xf4 - SPI Control Register"] + pub spi_ctrlr0: SPI_CTRLR0, + _reserved27: [u8; 4usize], + #[doc = "0xfc - XIP Mode bits"] + pub xip_mode_bits: XIP_MODE_BITS, + #[doc = "0x100 - XIP INCR transfer opcode"] + pub xip_incr_inst: XIP_INCR_INST, + #[doc = "0x104 - XIP WRAP transfer opcode"] + pub xip_wrap_inst: XIP_WRAP_INST, + #[doc = "0x108 - XIP Control Register"] + pub xip_ctrl: XIP_CTRL, + #[doc = "0x10c - XIP Slave Enable Register"] + pub xip_ser: XIP_SER, + #[doc = "0x110 - XIP Receive FIFO Overflow Interrupt Clear Register"] + pub xrxoicr: XRXOICR, + #[doc = "0x114 - XIP time out register for continuous transfers"] + pub xip_cnt_time_out: XIP_CNT_TIME_OUT, + #[doc = "0x118 - ENDIAN"] + pub endian: ENDIAN, + } + #[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr0](ctrlr0) module"] + pub type CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR0; + #[doc = "`read()` method returns [ctrlr0::R](ctrlr0::R) reader structure"] + impl crate::Readable for CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [ctrlr0::W](ctrlr0::W) writer structure"] + impl crate::Writable for CTRLR0 {} + #[doc = "Control Register 0"] + pub mod ctrlr0 { + #[doc = "Reader of register ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr0"] + pub type W = crate::W; + #[doc = "Register ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "WORK_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum WORK_MODE_A { + #[doc = "0: MODE_0"] + MODE0 = 0, + #[doc = "1: MODE_1"] + MODE1 = 1, + #[doc = "2: MODE_2"] + MODE2 = 2, + #[doc = "3: MODE_3"] + MODE3 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: WORK_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `work_mode`"] + pub type WORK_MODE_R = crate::R; + impl WORK_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORK_MODE_A { + match self.bits { + 0 => WORK_MODE_A::MODE0, + 1 => WORK_MODE_A::MODE1, + 2 => WORK_MODE_A::MODE2, + 3 => WORK_MODE_A::MODE3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `MODE0`"] + #[inline(always)] + pub fn is_mode0(&self) -> bool { + *self == WORK_MODE_A::MODE0 + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == WORK_MODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == WORK_MODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + *self == WORK_MODE_A::MODE3 + } + } + #[doc = "Write proxy for field `work_mode`"] + pub struct WORK_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> WORK_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORK_MODE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "MODE_0"] + #[inline(always)] + pub fn mode0(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE0) + } + #[doc = "MODE_1"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE1) + } + #[doc = "MODE_2"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE2) + } + #[doc = "MODE_3"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6); + self.w + } + } + #[doc = "TRANSFER_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TMOD_A { + #[doc = "0: TRANS_RECV"] + TRANS_RECV = 0, + #[doc = "1: TRANS"] + TRANS = 1, + #[doc = "2: RECV"] + RECV = 2, + #[doc = "3: EEROM"] + EEROM = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TMOD_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tmod`"] + pub type TMOD_R = crate::R; + impl TMOD_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TMOD_A { + match self.bits { + 0 => TMOD_A::TRANS_RECV, + 1 => TMOD_A::TRANS, + 2 => TMOD_A::RECV, + 3 => TMOD_A::EEROM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TRANS_RECV`"] + #[inline(always)] + pub fn is_trans_recv(&self) -> bool { + *self == TMOD_A::TRANS_RECV + } + #[doc = "Checks if the value of the field is `TRANS`"] + #[inline(always)] + pub fn is_trans(&self) -> bool { + *self == TMOD_A::TRANS + } + #[doc = "Checks if the value of the field is `RECV`"] + #[inline(always)] + pub fn is_recv(&self) -> bool { + *self == TMOD_A::RECV + } + #[doc = "Checks if the value of the field is `EEROM`"] + #[inline(always)] + pub fn is_eerom(&self) -> bool { + *self == TMOD_A::EEROM + } + } + #[doc = "Write proxy for field `tmod`"] + pub struct TMOD_W<'a> { + w: &'a mut W, + } + impl<'a> TMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TMOD_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "TRANS_RECV"] + #[inline(always)] + pub fn trans_recv(self) -> &'a mut W { + self.variant(TMOD_A::TRANS_RECV) + } + #[doc = "TRANS"] + #[inline(always)] + pub fn trans(self) -> &'a mut W { + self.variant(TMOD_A::TRANS) + } + #[doc = "RECV"] + #[inline(always)] + pub fn recv(self) -> &'a mut W { + self.variant(TMOD_A::RECV) + } + #[doc = "EEROM"] + #[inline(always)] + pub fn eerom(self) -> &'a mut W { + self.variant(TMOD_A::EEROM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "FRAME_FORMAT\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum FRAME_FORMAT_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: DUAL"] + DUAL = 1, + #[doc = "2: QUAD"] + QUAD = 2, + #[doc = "3: OCTAL"] + OCTAL = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: FRAME_FORMAT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `frame_format`"] + pub type FRAME_FORMAT_R = crate::R; + impl FRAME_FORMAT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRAME_FORMAT_A { + match self.bits { + 0 => FRAME_FORMAT_A::STANDARD, + 1 => FRAME_FORMAT_A::DUAL, + 2 => FRAME_FORMAT_A::QUAD, + 3 => FRAME_FORMAT_A::OCTAL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == FRAME_FORMAT_A::STANDARD + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + *self == FRAME_FORMAT_A::DUAL + } + #[doc = "Checks if the value of the field is `QUAD`"] + #[inline(always)] + pub fn is_quad(&self) -> bool { + *self == FRAME_FORMAT_A::QUAD + } + #[doc = "Checks if the value of the field is `OCTAL`"] + #[inline(always)] + pub fn is_octal(&self) -> bool { + *self == FRAME_FORMAT_A::OCTAL + } + } + #[doc = "Write proxy for field `frame_format`"] + pub struct FRAME_FORMAT_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FORMAT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRAME_FORMAT_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::STANDARD) + } + #[doc = "DUAL"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::DUAL) + } + #[doc = "QUAD"] + #[inline(always)] + pub fn quad(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::QUAD) + } + #[doc = "OCTAL"] + #[inline(always)] + pub fn octal(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::OCTAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21); + self.w + } + } + #[doc = "Reader of field `data_length`"] + pub type DATA_LENGTH_R = crate::R; + #[doc = "Write proxy for field `data_length`"] + pub struct DATA_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16); + self.w + } + } + impl R { + #[doc = "Bits 6:7 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 8:9 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&self) -> TMOD_R { + TMOD_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 21:22 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&self) -> FRAME_FORMAT_R { + FRAME_FORMAT_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bits 16:20 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&self) -> DATA_LENGTH_R { + DATA_LENGTH_R::new(((self.bits >> 16) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 6:7 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W { w: self } + } + #[doc = "Bits 8:9 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&mut self) -> TMOD_W { + TMOD_W { w: self } + } + #[doc = "Bits 21:22 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&mut self) -> FRAME_FORMAT_W { + FRAME_FORMAT_W { w: self } + } + #[doc = "Bits 16:20 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&mut self) -> DATA_LENGTH_W { + DATA_LENGTH_W { w: self } + } + } + } + #[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr1](ctrlr1) module"] + pub type CTRLR1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR1; + #[doc = "`read()` method returns [ctrlr1::R](ctrlr1::R) reader structure"] + impl crate::Readable for CTRLR1 {} + #[doc = "`write(|w| ..)` method takes [ctrlr1::W](ctrlr1::W) writer structure"] + impl crate::Writable for CTRLR1 {} + #[doc = "Control Register 1"] + pub mod ctrlr1 { + #[doc = "Reader of register ctrlr1"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr1"] + pub type W = crate::W; + #[doc = "Register ctrlr1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssienr](ssienr) module"] + pub type SSIENR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIENR; + #[doc = "`read()` method returns [ssienr::R](ssienr::R) reader structure"] + impl crate::Readable for SSIENR {} + #[doc = "`write(|w| ..)` method takes [ssienr::W](ssienr::W) writer structure"] + impl crate::Writable for SSIENR {} + #[doc = "Enable Register"] + pub mod ssienr { + #[doc = "Reader of register ssienr"] + pub type R = crate::R; + #[doc = "Writer for register ssienr"] + pub type W = crate::W; + #[doc = "Register ssienr `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIENR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Microwire Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mwcr](mwcr) module"] + pub type MWCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MWCR; + #[doc = "`read()` method returns [mwcr::R](mwcr::R) reader structure"] + impl crate::Readable for MWCR {} + #[doc = "`write(|w| ..)` method takes [mwcr::W](mwcr::W) writer structure"] + impl crate::Writable for MWCR {} + #[doc = "Microwire Control Register"] + pub mod mwcr { + #[doc = "Reader of register mwcr"] + pub type R = crate::R; + #[doc = "Writer for register mwcr"] + pub type W = crate::W; + #[doc = "Register mwcr `reset()`'s with value 0"] + impl crate::ResetValue for super::MWCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ser](ser) module"] + pub type SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SER; + #[doc = "`read()` method returns [ser::R](ser::R) reader structure"] + impl crate::Readable for SER {} + #[doc = "`write(|w| ..)` method takes [ser::W](ser::W) writer structure"] + impl crate::Writable for SER {} + #[doc = "Slave Enable Register"] + pub mod ser { + #[doc = "Reader of register ser"] + pub type R = crate::R; + #[doc = "Writer for register ser"] + pub type W = crate::W; + #[doc = "Register ser `reset()`'s with value 0"] + impl crate::ResetValue for super::SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Baud Rate Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudr](baudr) module"] + pub type BAUDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BAUDR; + #[doc = "`read()` method returns [baudr::R](baudr::R) reader structure"] + impl crate::Readable for BAUDR {} + #[doc = "`write(|w| ..)` method takes [baudr::W](baudr::W) writer structure"] + impl crate::Writable for BAUDR {} + #[doc = "Baud Rate Select"] + pub mod baudr { + #[doc = "Reader of register baudr"] + pub type R = crate::R; + #[doc = "Writer for register baudr"] + pub type W = crate::W; + #[doc = "Register baudr `reset()`'s with value 0"] + impl crate::ResetValue for super::BAUDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txftlr](txftlr) module"] + pub type TXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFTLR; + #[doc = "`read()` method returns [txftlr::R](txftlr::R) reader structure"] + impl crate::Readable for TXFTLR {} + #[doc = "`write(|w| ..)` method takes [txftlr::W](txftlr::W) writer structure"] + impl crate::Writable for TXFTLR {} + #[doc = "Transmit FIFO Threshold Level"] + pub mod txftlr { + #[doc = "Reader of register txftlr"] + pub type R = crate::R; + #[doc = "Writer for register txftlr"] + pub type W = crate::W; + #[doc = "Register txftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxftlr](rxftlr) module"] + pub type RXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFTLR; + #[doc = "`read()` method returns [rxftlr::R](rxftlr::R) reader structure"] + impl crate::Readable for RXFTLR {} + #[doc = "`write(|w| ..)` method takes [rxftlr::W](rxftlr::W) writer structure"] + impl crate::Writable for RXFTLR {} + #[doc = "Receive FIFO Threshold Level"] + pub mod rxftlr { + #[doc = "Reader of register rxftlr"] + pub type R = crate::R; + #[doc = "Writer for register rxftlr"] + pub type W = crate::W; + #[doc = "Register rxftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](txflr) module"] + pub type TXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFLR; + #[doc = "`read()` method returns [txflr::R](txflr::R) reader structure"] + impl crate::Readable for TXFLR {} + #[doc = "`write(|w| ..)` method takes [txflr::W](txflr::W) writer structure"] + impl crate::Writable for TXFLR {} + #[doc = "Transmit FIFO Level Register"] + pub mod txflr { + #[doc = "Reader of register txflr"] + pub type R = crate::R; + #[doc = "Writer for register txflr"] + pub type W = crate::W; + #[doc = "Register txflr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](rxflr) module"] + pub type RXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFLR; + #[doc = "`read()` method returns [rxflr::R](rxflr::R) reader structure"] + impl crate::Readable for RXFLR {} + #[doc = "`write(|w| ..)` method takes [rxflr::W](rxflr::W) writer structure"] + impl crate::Writable for RXFLR {} + #[doc = "Receive FIFO Level Register"] + pub mod rxflr { + #[doc = "Reader of register rxflr"] + pub type R = crate::R; + #[doc = "Writer for register rxflr"] + pub type W = crate::W; + #[doc = "Register rxflr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](sr) module"] + pub type SR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SR; + #[doc = "`read()` method returns [sr::R](sr::R) reader structure"] + impl crate::Readable for SR {} + #[doc = "`write(|w| ..)` method takes [sr::W](sr::W) writer structure"] + impl crate::Writable for SR {} + #[doc = "Status Register"] + pub mod sr { + #[doc = "Reader of register sr"] + pub type R = crate::R; + #[doc = "Writer for register sr"] + pub type W = crate::W; + #[doc = "Register sr `reset()`'s with value 0"] + impl crate::ResetValue for super::SR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](imr) module"] + pub type IMR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IMR; + #[doc = "`read()` method returns [imr::R](imr::R) reader structure"] + impl crate::Readable for IMR {} + #[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"] + impl crate::Writable for IMR {} + #[doc = "Interrupt Mask Register"] + pub mod imr { + #[doc = "Reader of register imr"] + pub type R = crate::R; + #[doc = "Writer for register imr"] + pub type W = crate::W; + #[doc = "Register imr `reset()`'s with value 0"] + impl crate::ResetValue for super::IMR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](isr) module"] + pub type ISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ISR; + #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] + impl crate::Readable for ISR {} + #[doc = "`write(|w| ..)` method takes [isr::W](isr::W) writer structure"] + impl crate::Writable for ISR {} + #[doc = "Interrupt Status Register"] + pub mod isr { + #[doc = "Reader of register isr"] + pub type R = crate::R; + #[doc = "Writer for register isr"] + pub type W = crate::W; + #[doc = "Register isr `reset()`'s with value 0"] + impl crate::ResetValue for super::ISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [risr](risr) module"] + pub type RISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISR; + #[doc = "`read()` method returns [risr::R](risr::R) reader structure"] + impl crate::Readable for RISR {} + #[doc = "`write(|w| ..)` method takes [risr::W](risr::W) writer structure"] + impl crate::Writable for RISR {} + #[doc = "Raw Interrupt Status Register"] + pub mod risr { + #[doc = "Reader of register risr"] + pub type R = crate::R; + #[doc = "Writer for register risr"] + pub type W = crate::W; + #[doc = "Register risr `reset()`'s with value 0"] + impl crate::ResetValue for super::RISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoicr](txoicr) module"] + pub type TXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXOICR; + #[doc = "`read()` method returns [txoicr::R](txoicr::R) reader structure"] + impl crate::Readable for TXOICR {} + #[doc = "`write(|w| ..)` method takes [txoicr::W](txoicr::W) writer structure"] + impl crate::Writable for TXOICR {} + #[doc = "Transmit FIFO Overflow Interrupt Clear Register"] + pub mod txoicr { + #[doc = "Reader of register txoicr"] + pub type R = crate::R; + #[doc = "Writer for register txoicr"] + pub type W = crate::W; + #[doc = "Register txoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoicr](rxoicr) module"] + pub type RXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXOICR; + #[doc = "`read()` method returns [rxoicr::R](rxoicr::R) reader structure"] + impl crate::Readable for RXOICR {} + #[doc = "`write(|w| ..)` method takes [rxoicr::W](rxoicr::W) writer structure"] + impl crate::Writable for RXOICR {} + #[doc = "Receive FIFO Overflow Interrupt Clear Register"] + pub mod rxoicr { + #[doc = "Reader of register rxoicr"] + pub type R = crate::R; + #[doc = "Writer for register rxoicr"] + pub type W = crate::W; + #[doc = "Register rxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Underflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxuicr](rxuicr) module"] + pub type RXUICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXUICR; + #[doc = "`read()` method returns [rxuicr::R](rxuicr::R) reader structure"] + impl crate::Readable for RXUICR {} + #[doc = "`write(|w| ..)` method takes [rxuicr::W](rxuicr::W) writer structure"] + impl crate::Writable for RXUICR {} + #[doc = "Receive FIFO Underflow Interrupt Clear Register"] + pub mod rxuicr { + #[doc = "Reader of register rxuicr"] + pub type R = crate::R; + #[doc = "Writer for register rxuicr"] + pub type W = crate::W; + #[doc = "Register rxuicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXUICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Multi-Master Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msticr](msticr) module"] + pub type MSTICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSTICR; + #[doc = "`read()` method returns [msticr::R](msticr::R) reader structure"] + impl crate::Readable for MSTICR {} + #[doc = "`write(|w| ..)` method takes [msticr::W](msticr::W) writer structure"] + impl crate::Writable for MSTICR {} + #[doc = "Multi-Master Interrupt Clear Register"] + pub mod msticr { + #[doc = "Reader of register msticr"] + pub type R = crate::R; + #[doc = "Writer for register msticr"] + pub type W = crate::W; + #[doc = "Register msticr `reset()`'s with value 0"] + impl crate::ResetValue for super::MSTICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](icr) module"] + pub type ICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ICR; + #[doc = "`read()` method returns [icr::R](icr::R) reader structure"] + impl crate::Readable for ICR {} + #[doc = "`write(|w| ..)` method takes [icr::W](icr::W) writer structure"] + impl crate::Writable for ICR {} + #[doc = "Interrupt Clear Register"] + pub mod icr { + #[doc = "Reader of register icr"] + pub type R = crate::R; + #[doc = "Writer for register icr"] + pub type W = crate::W; + #[doc = "Register icr `reset()`'s with value 0"] + impl crate::ResetValue for super::ICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](dmacr) module"] + pub type DMACR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMACR; + #[doc = "`read()` method returns [dmacr::R](dmacr::R) reader structure"] + impl crate::Readable for DMACR {} + #[doc = "`write(|w| ..)` method takes [dmacr::W](dmacr::W) writer structure"] + impl crate::Writable for DMACR {} + #[doc = "DMA Control Register"] + pub mod dmacr { + #[doc = "Reader of register dmacr"] + pub type R = crate::R; + #[doc = "Writer for register dmacr"] + pub type W = crate::W; + #[doc = "Register dmacr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMACR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Transmit Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatdlr](dmatdlr) module"] + pub type DMATDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMATDLR; + #[doc = "`read()` method returns [dmatdlr::R](dmatdlr::R) reader structure"] + impl crate::Readable for DMATDLR {} + #[doc = "`write(|w| ..)` method takes [dmatdlr::W](dmatdlr::W) writer structure"] + impl crate::Writable for DMATDLR {} + #[doc = "DMA Transmit Data Level"] + pub mod dmatdlr { + #[doc = "Reader of register dmatdlr"] + pub type R = crate::R; + #[doc = "Writer for register dmatdlr"] + pub type W = crate::W; + #[doc = "Register dmatdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMATDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Receive Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmardlr](dmardlr) module"] + pub type DMARDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMARDLR; + #[doc = "`read()` method returns [dmardlr::R](dmardlr::R) reader structure"] + impl crate::Readable for DMARDLR {} + #[doc = "`write(|w| ..)` method takes [dmardlr::W](dmardlr::W) writer structure"] + impl crate::Writable for DMARDLR {} + #[doc = "DMA Receive Data Level"] + pub mod dmardlr { + #[doc = "Reader of register dmardlr"] + pub type R = crate::R; + #[doc = "Writer for register dmardlr"] + pub type W = crate::W; + #[doc = "Register dmardlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMARDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](idr) module"] + pub type IDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IDR; + #[doc = "`read()` method returns [idr::R](idr::R) reader structure"] + impl crate::Readable for IDR {} + #[doc = "`write(|w| ..)` method takes [idr::W](idr::W) writer structure"] + impl crate::Writable for IDR {} + #[doc = "Identification Register"] + pub mod idr { + #[doc = "Reader of register idr"] + pub type R = crate::R; + #[doc = "Writer for register idr"] + pub type W = crate::W; + #[doc = "Register idr `reset()`'s with value 0"] + impl crate::ResetValue for super::IDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DWC_ssi component version\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssic_version_id](ssic_version_id) module"] + pub type SSIC_VERSION_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIC_VERSION_ID; + #[doc = "`read()` method returns [ssic_version_id::R](ssic_version_id::R) reader structure"] + impl crate::Readable for SSIC_VERSION_ID {} + #[doc = "`write(|w| ..)` method takes [ssic_version_id::W](ssic_version_id::W) writer structure"] + impl crate::Writable for SSIC_VERSION_ID {} + #[doc = "DWC_ssi component version"] + pub mod ssic_version_id { + #[doc = "Reader of register ssic_version_id"] + pub type R = crate::R; + #[doc = "Writer for register ssic_version_id"] + pub type W = crate::W; + #[doc = "Register ssic_version_id `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIC_VERSION_ID { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](dr) module"] + pub type DR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DR; + #[doc = "`read()` method returns [dr::R](dr::R) reader structure"] + impl crate::Readable for DR {} + #[doc = "`write(|w| ..)` method takes [dr::W](dr::W) writer structure"] + impl crate::Writable for DR {} + #[doc = "Data Register"] + pub mod dr { + #[doc = "Reader of register dr%s"] + pub type R = crate::R; + #[doc = "Writer for register dr%s"] + pub type W = crate::W; + #[doc = "Register dr%s `reset()`'s with value 0"] + impl crate::ResetValue for super::DR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RX Sample Delay Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_sample_delay](rx_sample_delay) module"] + pub type RX_SAMPLE_DELAY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RX_SAMPLE_DELAY; + #[doc = "`read()` method returns [rx_sample_delay::R](rx_sample_delay::R) reader structure"] + impl crate::Readable for RX_SAMPLE_DELAY {} + #[doc = "`write(|w| ..)` method takes [rx_sample_delay::W](rx_sample_delay::W) writer structure"] + impl crate::Writable for RX_SAMPLE_DELAY {} + #[doc = "RX Sample Delay Register"] + pub mod rx_sample_delay { + #[doc = "Reader of register rx_sample_delay"] + pub type R = crate::R; + #[doc = "Writer for register rx_sample_delay"] + pub type W = crate::W; + #[doc = "Register rx_sample_delay `reset()`'s with value 0"] + impl crate::ResetValue for super::RX_SAMPLE_DELAY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "SPI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_ctrlr0](spi_ctrlr0) module"] + pub type SPI_CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SPI_CTRLR0; + #[doc = "`read()` method returns [spi_ctrlr0::R](spi_ctrlr0::R) reader structure"] + impl crate::Readable for SPI_CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [spi_ctrlr0::W](spi_ctrlr0::W) writer structure"] + impl crate::Writable for SPI_CTRLR0 {} + #[doc = "SPI Control Register"] + pub mod spi_ctrlr0 { + #[doc = "Reader of register spi_ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register spi_ctrlr0"] + pub type W = crate::W; + #[doc = "Register spi_ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::SPI_CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "instruction_address_trans_mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum AITM_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: ADDR_STANDARD"] + ADDR_STANDARD = 1, + #[doc = "2: AS_FRAME_FORMAT"] + AS_FRAME_FORMAT = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: AITM_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `aitm`"] + pub type AITM_R = crate::R; + impl AITM_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(AITM_A::STANDARD), + 1 => Val(AITM_A::ADDR_STANDARD), + 2 => Val(AITM_A::AS_FRAME_FORMAT), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == AITM_A::STANDARD + } + #[doc = "Checks if the value of the field is `ADDR_STANDARD`"] + #[inline(always)] + pub fn is_addr_standard(&self) -> bool { + *self == AITM_A::ADDR_STANDARD + } + #[doc = "Checks if the value of the field is `AS_FRAME_FORMAT`"] + #[inline(always)] + pub fn is_as_frame_format(&self) -> bool { + *self == AITM_A::AS_FRAME_FORMAT + } + } + #[doc = "Write proxy for field `aitm`"] + pub struct AITM_W<'a> { + w: &'a mut W, + } + impl<'a> AITM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AITM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(AITM_A::STANDARD) + } + #[doc = "ADDR_STANDARD"] + #[inline(always)] + pub fn addr_standard(self) -> &'a mut W { + self.variant(AITM_A::ADDR_STANDARD) + } + #[doc = "AS_FRAME_FORMAT"] + #[inline(always)] + pub fn as_frame_format(self) -> &'a mut W { + self.variant(AITM_A::AS_FRAME_FORMAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `addr_length`"] + pub type ADDR_LENGTH_R = crate::R; + #[doc = "Write proxy for field `addr_length`"] + pub struct ADDR_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 2)) | (((value as u32) & 0x0f) << 2); + self.w + } + } + #[doc = "Reader of field `inst_length`"] + pub type INST_LENGTH_R = crate::R; + #[doc = "Write proxy for field `inst_length`"] + pub struct INST_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> INST_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `wait_cycles`"] + pub type WAIT_CYCLES_R = crate::R; + #[doc = "Write proxy for field `wait_cycles`"] + pub struct WAIT_CYCLES_W<'a> { + w: &'a mut W, + } + impl<'a> WAIT_CYCLES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 11)) | (((value as u32) & 0x1f) << 11); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&self) -> AITM_R { + AITM_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&self) -> ADDR_LENGTH_R { + ADDR_LENGTH_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&self) -> INST_LENGTH_R { + INST_LENGTH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&self) -> WAIT_CYCLES_R { + WAIT_CYCLES_R::new(((self.bits >> 11) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&mut self) -> AITM_W { + AITM_W { w: self } + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&mut self) -> ADDR_LENGTH_W { + ADDR_LENGTH_W { w: self } + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&mut self) -> INST_LENGTH_W { + INST_LENGTH_W { w: self } + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W { + WAIT_CYCLES_W { w: self } + } + } + } + #[doc = "XIP Mode bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_mode_bits](xip_mode_bits) module"] + pub type XIP_MODE_BITS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_MODE_BITS; + #[doc = "`read()` method returns [xip_mode_bits::R](xip_mode_bits::R) reader structure"] + impl crate::Readable for XIP_MODE_BITS {} + #[doc = "`write(|w| ..)` method takes [xip_mode_bits::W](xip_mode_bits::W) writer structure"] + impl crate::Writable for XIP_MODE_BITS {} + #[doc = "XIP Mode bits"] + pub mod xip_mode_bits { + #[doc = "Reader of register xip_mode_bits"] + pub type R = crate::R; + #[doc = "Writer for register xip_mode_bits"] + pub type W = crate::W; + #[doc = "Register xip_mode_bits `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_MODE_BITS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP INCR transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_incr_inst](xip_incr_inst) module"] + pub type XIP_INCR_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_INCR_INST; + #[doc = "`read()` method returns [xip_incr_inst::R](xip_incr_inst::R) reader structure"] + impl crate::Readable for XIP_INCR_INST {} + #[doc = "`write(|w| ..)` method takes [xip_incr_inst::W](xip_incr_inst::W) writer structure"] + impl crate::Writable for XIP_INCR_INST {} + #[doc = "XIP INCR transfer opcode"] + pub mod xip_incr_inst { + #[doc = "Reader of register xip_incr_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_incr_inst"] + pub type W = crate::W; + #[doc = "Register xip_incr_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_INCR_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP WRAP transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_wrap_inst](xip_wrap_inst) module"] + pub type XIP_WRAP_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_WRAP_INST; + #[doc = "`read()` method returns [xip_wrap_inst::R](xip_wrap_inst::R) reader structure"] + impl crate::Readable for XIP_WRAP_INST {} + #[doc = "`write(|w| ..)` method takes [xip_wrap_inst::W](xip_wrap_inst::W) writer structure"] + impl crate::Writable for XIP_WRAP_INST {} + #[doc = "XIP WRAP transfer opcode"] + pub mod xip_wrap_inst { + #[doc = "Reader of register xip_wrap_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_wrap_inst"] + pub type W = crate::W; + #[doc = "Register xip_wrap_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_WRAP_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ctrl](xip_ctrl) module"] + pub type XIP_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CTRL; + #[doc = "`read()` method returns [xip_ctrl::R](xip_ctrl::R) reader structure"] + impl crate::Readable for XIP_CTRL {} + #[doc = "`write(|w| ..)` method takes [xip_ctrl::W](xip_ctrl::W) writer structure"] + impl crate::Writable for XIP_CTRL {} + #[doc = "XIP Control Register"] + pub mod xip_ctrl { + #[doc = "Reader of register xip_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register xip_ctrl"] + pub type W = crate::W; + #[doc = "Register xip_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ser](xip_ser) module"] + pub type XIP_SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_SER; + #[doc = "`read()` method returns [xip_ser::R](xip_ser::R) reader structure"] + impl crate::Readable for XIP_SER {} + #[doc = "`write(|w| ..)` method takes [xip_ser::W](xip_ser::W) writer structure"] + impl crate::Writable for XIP_SER {} + #[doc = "XIP Slave Enable Register"] + pub mod xip_ser { + #[doc = "Reader of register xip_ser"] + pub type R = crate::R; + #[doc = "Writer for register xip_ser"] + pub type W = crate::W; + #[doc = "Register xip_ser `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xrxoicr](xrxoicr) module"] + pub type XRXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XRXOICR; + #[doc = "`read()` method returns [xrxoicr::R](xrxoicr::R) reader structure"] + impl crate::Readable for XRXOICR {} + #[doc = "`write(|w| ..)` method takes [xrxoicr::W](xrxoicr::W) writer structure"] + impl crate::Writable for XRXOICR {} + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register"] + pub mod xrxoicr { + #[doc = "Reader of register xrxoicr"] + pub type R = crate::R; + #[doc = "Writer for register xrxoicr"] + pub type W = crate::W; + #[doc = "Register xrxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::XRXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP time out register for continuous transfers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_cnt_time_out](xip_cnt_time_out) module"] + pub type XIP_CNT_TIME_OUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CNT_TIME_OUT; + #[doc = "`read()` method returns [xip_cnt_time_out::R](xip_cnt_time_out::R) reader structure"] + impl crate::Readable for XIP_CNT_TIME_OUT {} + #[doc = "`write(|w| ..)` method takes [xip_cnt_time_out::W](xip_cnt_time_out::W) writer structure"] + impl crate::Writable for XIP_CNT_TIME_OUT {} + #[doc = "XIP time out register for continuous transfers"] + pub mod xip_cnt_time_out { + #[doc = "Reader of register xip_cnt_time_out"] + pub type R = crate::R; + #[doc = "Writer for register xip_cnt_time_out"] + pub type W = crate::W; + #[doc = "Register xip_cnt_time_out `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CNT_TIME_OUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "ENDIAN\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endian](endian) module"] + pub type ENDIAN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENDIAN; + #[doc = "`read()` method returns [endian::R](endian::R) reader structure"] + impl crate::Readable for ENDIAN {} + #[doc = "`write(|w| ..)` method takes [endian::W](endian::W) writer structure"] + impl crate::Writable for ENDIAN {} + #[doc = "ENDIAN"] + pub mod endian { + #[doc = "Reader of register endian"] + pub type R = crate::R; + #[doc = "Writer for register endian"] + pub type W = crate::W; + #[doc = "Register endian `reset()`'s with value 0"] + impl crate::ResetValue for super::ENDIAN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Serial Peripheral Interface 1 (master)"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + 0x5300_0000 as *const _ + } +} +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI1::ptr() } + } +} +#[doc = "Serial Peripheral Interface 2 (slave)"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi2::RegisterBlock { + 0x5024_0000 as *const _ + } +} +impl Deref for SPI2 { + type Target = spi2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI2::ptr() } + } +} +#[doc = "Serial Peripheral Interface 2 (slave)"] +pub mod spi2 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Dummy register: this peripheral is not implemented yet"] + pub dummy: DUMMY, + } + #[doc = "Dummy register: this peripheral is not implemented yet\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dummy](dummy) module"] + pub type DUMMY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DUMMY; + #[doc = "`read()` method returns [dummy::R](dummy::R) reader structure"] + impl crate::Readable for DUMMY {} + #[doc = "`write(|w| ..)` method takes [dummy::W](dummy::W) writer structure"] + impl crate::Writable for DUMMY {} + #[doc = "Dummy register: this peripheral is not implemented yet"] + pub mod dummy { + #[doc = "Reader of register dummy"] + pub type R = crate::R; + #[doc = "Writer for register dummy"] + pub type W = crate::W; + #[doc = "Register dummy `reset()`'s with value 0"] + impl crate::ResetValue for super::DUMMY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Serial Peripheral Interface 3 (master)"] +pub struct SPI3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI3 {} +impl SPI3 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi3::RegisterBlock { + 0x5400_0000 as *const _ + } +} +impl Deref for SPI3 { + type Target = spi3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SPI3::ptr() } + } +} +#[doc = "Serial Peripheral Interface 3 (master)"] +pub mod spi3 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register 0"] + pub ctrlr0: CTRLR0, + #[doc = "0x04 - Control Register 1"] + pub ctrlr1: CTRLR1, + #[doc = "0x08 - Enable Register"] + pub ssienr: SSIENR, + #[doc = "0x0c - Microwire Control Register"] + pub mwcr: MWCR, + #[doc = "0x10 - Slave Enable Register"] + pub ser: SER, + #[doc = "0x14 - Baud Rate Select"] + pub baudr: BAUDR, + #[doc = "0x18 - Transmit FIFO Threshold Level"] + pub txftlr: TXFTLR, + #[doc = "0x1c - Receive FIFO Threshold Level"] + pub rxftlr: RXFTLR, + #[doc = "0x20 - Transmit FIFO Level Register"] + pub txflr: TXFLR, + #[doc = "0x24 - Receive FIFO Level Register"] + pub rxflr: RXFLR, + #[doc = "0x28 - Status Register"] + pub sr: SR, + #[doc = "0x2c - Interrupt Mask Register"] + pub imr: IMR, + #[doc = "0x30 - Interrupt Status Register"] + pub isr: ISR, + #[doc = "0x34 - Raw Interrupt Status Register"] + pub risr: RISR, + #[doc = "0x38 - Transmit FIFO Overflow Interrupt Clear Register"] + pub txoicr: TXOICR, + #[doc = "0x3c - Receive FIFO Overflow Interrupt Clear Register"] + pub rxoicr: RXOICR, + #[doc = "0x40 - Receive FIFO Underflow Interrupt Clear Register"] + pub rxuicr: RXUICR, + #[doc = "0x44 - Multi-Master Interrupt Clear Register"] + pub msticr: MSTICR, + #[doc = "0x48 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x4c - DMA Control Register"] + pub dmacr: DMACR, + #[doc = "0x50 - DMA Transmit Data Level"] + pub dmatdlr: DMATDLR, + #[doc = "0x54 - DMA Receive Data Level"] + pub dmardlr: DMARDLR, + #[doc = "0x58 - Identification Register"] + pub idr: IDR, + #[doc = "0x5c - DWC_ssi component version"] + pub ssic_version_id: SSIC_VERSION_ID, + #[doc = "0x60 - Data Register"] + pub dr: [DR; 36], + #[doc = "0xf0 - RX Sample Delay Register"] + pub rx_sample_delay: RX_SAMPLE_DELAY, + #[doc = "0xf4 - SPI Control Register"] + pub spi_ctrlr0: SPI_CTRLR0, + _reserved27: [u8; 4usize], + #[doc = "0xfc - XIP Mode bits"] + pub xip_mode_bits: XIP_MODE_BITS, + #[doc = "0x100 - XIP INCR transfer opcode"] + pub xip_incr_inst: XIP_INCR_INST, + #[doc = "0x104 - XIP WRAP transfer opcode"] + pub xip_wrap_inst: XIP_WRAP_INST, + #[doc = "0x108 - XIP Control Register"] + pub xip_ctrl: XIP_CTRL, + #[doc = "0x10c - XIP Slave Enable Register"] + pub xip_ser: XIP_SER, + #[doc = "0x110 - XIP Receive FIFO Overflow Interrupt Clear Register"] + pub xrxoicr: XRXOICR, + #[doc = "0x114 - XIP time out register for continuous transfers"] + pub xip_cnt_time_out: XIP_CNT_TIME_OUT, + #[doc = "0x118 - ENDIAN"] + pub endian: ENDIAN, + } + #[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr0](ctrlr0) module"] + pub type CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR0; + #[doc = "`read()` method returns [ctrlr0::R](ctrlr0::R) reader structure"] + impl crate::Readable for CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [ctrlr0::W](ctrlr0::W) writer structure"] + impl crate::Writable for CTRLR0 {} + #[doc = "Control Register 0"] + pub mod ctrlr0 { + #[doc = "Reader of register ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr0"] + pub type W = crate::W; + #[doc = "Register ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data_length`"] + pub type DATA_LENGTH_R = crate::R; + #[doc = "Write proxy for field `data_length`"] + pub struct DATA_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f); + self.w + } + } + #[doc = "WORK_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum WORK_MODE_A { + #[doc = "0: MODE_0"] + MODE0 = 0, + #[doc = "1: MODE_1"] + MODE1 = 1, + #[doc = "2: MODE_2"] + MODE2 = 2, + #[doc = "3: MODE_3"] + MODE3 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: WORK_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `work_mode`"] + pub type WORK_MODE_R = crate::R; + impl WORK_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORK_MODE_A { + match self.bits { + 0 => WORK_MODE_A::MODE0, + 1 => WORK_MODE_A::MODE1, + 2 => WORK_MODE_A::MODE2, + 3 => WORK_MODE_A::MODE3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `MODE0`"] + #[inline(always)] + pub fn is_mode0(&self) -> bool { + *self == WORK_MODE_A::MODE0 + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == WORK_MODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == WORK_MODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + *self == WORK_MODE_A::MODE3 + } + } + #[doc = "Write proxy for field `work_mode`"] + pub struct WORK_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> WORK_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORK_MODE_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "MODE_0"] + #[inline(always)] + pub fn mode0(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE0) + } + #[doc = "MODE_1"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE1) + } + #[doc = "MODE_2"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE2) + } + #[doc = "MODE_3"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WORK_MODE_A::MODE3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "TRANSFER_MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TMOD_A { + #[doc = "0: TRANS_RECV"] + TRANS_RECV = 0, + #[doc = "1: TRANS"] + TRANS = 1, + #[doc = "2: RECV"] + RECV = 2, + #[doc = "3: EEROM"] + EEROM = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TMOD_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tmod`"] + pub type TMOD_R = crate::R; + impl TMOD_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TMOD_A { + match self.bits { + 0 => TMOD_A::TRANS_RECV, + 1 => TMOD_A::TRANS, + 2 => TMOD_A::RECV, + 3 => TMOD_A::EEROM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TRANS_RECV`"] + #[inline(always)] + pub fn is_trans_recv(&self) -> bool { + *self == TMOD_A::TRANS_RECV + } + #[doc = "Checks if the value of the field is `TRANS`"] + #[inline(always)] + pub fn is_trans(&self) -> bool { + *self == TMOD_A::TRANS + } + #[doc = "Checks if the value of the field is `RECV`"] + #[inline(always)] + pub fn is_recv(&self) -> bool { + *self == TMOD_A::RECV + } + #[doc = "Checks if the value of the field is `EEROM`"] + #[inline(always)] + pub fn is_eerom(&self) -> bool { + *self == TMOD_A::EEROM + } + } + #[doc = "Write proxy for field `tmod`"] + pub struct TMOD_W<'a> { + w: &'a mut W, + } + impl<'a> TMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TMOD_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "TRANS_RECV"] + #[inline(always)] + pub fn trans_recv(self) -> &'a mut W { + self.variant(TMOD_A::TRANS_RECV) + } + #[doc = "TRANS"] + #[inline(always)] + pub fn trans(self) -> &'a mut W { + self.variant(TMOD_A::TRANS) + } + #[doc = "RECV"] + #[inline(always)] + pub fn recv(self) -> &'a mut W { + self.variant(TMOD_A::RECV) + } + #[doc = "EEROM"] + #[inline(always)] + pub fn eerom(self) -> &'a mut W { + self.variant(TMOD_A::EEROM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10); + self.w + } + } + #[doc = "FRAME_FORMAT\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum FRAME_FORMAT_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: DUAL"] + DUAL = 1, + #[doc = "2: QUAD"] + QUAD = 2, + #[doc = "3: OCTAL"] + OCTAL = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: FRAME_FORMAT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `frame_format`"] + pub type FRAME_FORMAT_R = crate::R; + impl FRAME_FORMAT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRAME_FORMAT_A { + match self.bits { + 0 => FRAME_FORMAT_A::STANDARD, + 1 => FRAME_FORMAT_A::DUAL, + 2 => FRAME_FORMAT_A::QUAD, + 3 => FRAME_FORMAT_A::OCTAL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == FRAME_FORMAT_A::STANDARD + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + *self == FRAME_FORMAT_A::DUAL + } + #[doc = "Checks if the value of the field is `QUAD`"] + #[inline(always)] + pub fn is_quad(&self) -> bool { + *self == FRAME_FORMAT_A::QUAD + } + #[doc = "Checks if the value of the field is `OCTAL`"] + #[inline(always)] + pub fn is_octal(&self) -> bool { + *self == FRAME_FORMAT_A::OCTAL + } + } + #[doc = "Write proxy for field `frame_format`"] + pub struct FRAME_FORMAT_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FORMAT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRAME_FORMAT_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::STANDARD) + } + #[doc = "DUAL"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::DUAL) + } + #[doc = "QUAD"] + #[inline(always)] + pub fn quad(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::QUAD) + } + #[doc = "OCTAL"] + #[inline(always)] + pub fn octal(self) -> &'a mut W { + self.variant(FRAME_FORMAT_A::OCTAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22); + self.w + } + } + impl R { + #[doc = "Bits 0:4 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&self) -> DATA_LENGTH_R { + DATA_LENGTH_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:9 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&self) -> TMOD_R { + TMOD_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 22:23 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&self) -> FRAME_FORMAT_R { + FRAME_FORMAT_R::new(((self.bits >> 22) & 0x03) as u8) + } + } + impl W { + #[doc = "Bits 0:4 - DATA_BIT_LENGTH"] + #[inline(always)] + pub fn data_length(&mut self) -> DATA_LENGTH_W { + DATA_LENGTH_W { w: self } + } + #[doc = "Bits 8:9 - WORK_MODE"] + #[inline(always)] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W { w: self } + } + #[doc = "Bits 10:11 - TRANSFER_MODE"] + #[inline(always)] + pub fn tmod(&mut self) -> TMOD_W { + TMOD_W { w: self } + } + #[doc = "Bits 22:23 - FRAME_FORMAT"] + #[inline(always)] + pub fn frame_format(&mut self) -> FRAME_FORMAT_W { + FRAME_FORMAT_W { w: self } + } + } + } + #[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr1](ctrlr1) module"] + pub type CTRLR1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTRLR1; + #[doc = "`read()` method returns [ctrlr1::R](ctrlr1::R) reader structure"] + impl crate::Readable for CTRLR1 {} + #[doc = "`write(|w| ..)` method takes [ctrlr1::W](ctrlr1::W) writer structure"] + impl crate::Writable for CTRLR1 {} + #[doc = "Control Register 1"] + pub mod ctrlr1 { + #[doc = "Reader of register ctrlr1"] + pub type R = crate::R; + #[doc = "Writer for register ctrlr1"] + pub type W = crate::W; + #[doc = "Register ctrlr1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CTRLR1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssienr](ssienr) module"] + pub type SSIENR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIENR; + #[doc = "`read()` method returns [ssienr::R](ssienr::R) reader structure"] + impl crate::Readable for SSIENR {} + #[doc = "`write(|w| ..)` method takes [ssienr::W](ssienr::W) writer structure"] + impl crate::Writable for SSIENR {} + #[doc = "Enable Register"] + pub mod ssienr { + #[doc = "Reader of register ssienr"] + pub type R = crate::R; + #[doc = "Writer for register ssienr"] + pub type W = crate::W; + #[doc = "Register ssienr `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIENR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Microwire Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mwcr](mwcr) module"] + pub type MWCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MWCR; + #[doc = "`read()` method returns [mwcr::R](mwcr::R) reader structure"] + impl crate::Readable for MWCR {} + #[doc = "`write(|w| ..)` method takes [mwcr::W](mwcr::W) writer structure"] + impl crate::Writable for MWCR {} + #[doc = "Microwire Control Register"] + pub mod mwcr { + #[doc = "Reader of register mwcr"] + pub type R = crate::R; + #[doc = "Writer for register mwcr"] + pub type W = crate::W; + #[doc = "Register mwcr `reset()`'s with value 0"] + impl crate::ResetValue for super::MWCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ser](ser) module"] + pub type SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SER; + #[doc = "`read()` method returns [ser::R](ser::R) reader structure"] + impl crate::Readable for SER {} + #[doc = "`write(|w| ..)` method takes [ser::W](ser::W) writer structure"] + impl crate::Writable for SER {} + #[doc = "Slave Enable Register"] + pub mod ser { + #[doc = "Reader of register ser"] + pub type R = crate::R; + #[doc = "Writer for register ser"] + pub type W = crate::W; + #[doc = "Register ser `reset()`'s with value 0"] + impl crate::ResetValue for super::SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Baud Rate Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudr](baudr) module"] + pub type BAUDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _BAUDR; + #[doc = "`read()` method returns [baudr::R](baudr::R) reader structure"] + impl crate::Readable for BAUDR {} + #[doc = "`write(|w| ..)` method takes [baudr::W](baudr::W) writer structure"] + impl crate::Writable for BAUDR {} + #[doc = "Baud Rate Select"] + pub mod baudr { + #[doc = "Reader of register baudr"] + pub type R = crate::R; + #[doc = "Writer for register baudr"] + pub type W = crate::W; + #[doc = "Register baudr `reset()`'s with value 0"] + impl crate::ResetValue for super::BAUDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txftlr](txftlr) module"] + pub type TXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFTLR; + #[doc = "`read()` method returns [txftlr::R](txftlr::R) reader structure"] + impl crate::Readable for TXFTLR {} + #[doc = "`write(|w| ..)` method takes [txftlr::W](txftlr::W) writer structure"] + impl crate::Writable for TXFTLR {} + #[doc = "Transmit FIFO Threshold Level"] + pub mod txftlr { + #[doc = "Reader of register txftlr"] + pub type R = crate::R; + #[doc = "Writer for register txftlr"] + pub type W = crate::W; + #[doc = "Register txftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Threshold Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxftlr](rxftlr) module"] + pub type RXFTLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFTLR; + #[doc = "`read()` method returns [rxftlr::R](rxftlr::R) reader structure"] + impl crate::Readable for RXFTLR {} + #[doc = "`write(|w| ..)` method takes [rxftlr::W](rxftlr::W) writer structure"] + impl crate::Writable for RXFTLR {} + #[doc = "Receive FIFO Threshold Level"] + pub mod rxftlr { + #[doc = "Reader of register rxftlr"] + pub type R = crate::R; + #[doc = "Writer for register rxftlr"] + pub type W = crate::W; + #[doc = "Register rxftlr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFTLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](txflr) module"] + pub type TXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFLR; + #[doc = "`read()` method returns [txflr::R](txflr::R) reader structure"] + impl crate::Readable for TXFLR {} + #[doc = "`write(|w| ..)` method takes [txflr::W](txflr::W) writer structure"] + impl crate::Writable for TXFLR {} + #[doc = "Transmit FIFO Level Register"] + pub mod txflr { + #[doc = "Reader of register txflr"] + pub type R = crate::R; + #[doc = "Writer for register txflr"] + pub type W = crate::W; + #[doc = "Register txflr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](rxflr) module"] + pub type RXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFLR; + #[doc = "`read()` method returns [rxflr::R](rxflr::R) reader structure"] + impl crate::Readable for RXFLR {} + #[doc = "`write(|w| ..)` method takes [rxflr::W](rxflr::W) writer structure"] + impl crate::Writable for RXFLR {} + #[doc = "Receive FIFO Level Register"] + pub mod rxflr { + #[doc = "Reader of register rxflr"] + pub type R = crate::R; + #[doc = "Writer for register rxflr"] + pub type W = crate::W; + #[doc = "Register rxflr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](sr) module"] + pub type SR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SR; + #[doc = "`read()` method returns [sr::R](sr::R) reader structure"] + impl crate::Readable for SR {} + #[doc = "`write(|w| ..)` method takes [sr::W](sr::W) writer structure"] + impl crate::Writable for SR {} + #[doc = "Status Register"] + pub mod sr { + #[doc = "Reader of register sr"] + pub type R = crate::R; + #[doc = "Writer for register sr"] + pub type W = crate::W; + #[doc = "Register sr `reset()`'s with value 0"] + impl crate::ResetValue for super::SR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](imr) module"] + pub type IMR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IMR; + #[doc = "`read()` method returns [imr::R](imr::R) reader structure"] + impl crate::Readable for IMR {} + #[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"] + impl crate::Writable for IMR {} + #[doc = "Interrupt Mask Register"] + pub mod imr { + #[doc = "Reader of register imr"] + pub type R = crate::R; + #[doc = "Writer for register imr"] + pub type W = crate::W; + #[doc = "Register imr `reset()`'s with value 0"] + impl crate::ResetValue for super::IMR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](isr) module"] + pub type ISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ISR; + #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] + impl crate::Readable for ISR {} + #[doc = "`write(|w| ..)` method takes [isr::W](isr::W) writer structure"] + impl crate::Writable for ISR {} + #[doc = "Interrupt Status Register"] + pub mod isr { + #[doc = "Reader of register isr"] + pub type R = crate::R; + #[doc = "Writer for register isr"] + pub type W = crate::W; + #[doc = "Register isr `reset()`'s with value 0"] + impl crate::ResetValue for super::ISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [risr](risr) module"] + pub type RISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RISR; + #[doc = "`read()` method returns [risr::R](risr::R) reader structure"] + impl crate::Readable for RISR {} + #[doc = "`write(|w| ..)` method takes [risr::W](risr::W) writer structure"] + impl crate::Writable for RISR {} + #[doc = "Raw Interrupt Status Register"] + pub mod risr { + #[doc = "Reader of register risr"] + pub type R = crate::R; + #[doc = "Writer for register risr"] + pub type W = crate::W; + #[doc = "Register risr `reset()`'s with value 0"] + impl crate::ResetValue for super::RISR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmit FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoicr](txoicr) module"] + pub type TXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXOICR; + #[doc = "`read()` method returns [txoicr::R](txoicr::R) reader structure"] + impl crate::Readable for TXOICR {} + #[doc = "`write(|w| ..)` method takes [txoicr::W](txoicr::W) writer structure"] + impl crate::Writable for TXOICR {} + #[doc = "Transmit FIFO Overflow Interrupt Clear Register"] + pub mod txoicr { + #[doc = "Reader of register txoicr"] + pub type R = crate::R; + #[doc = "Writer for register txoicr"] + pub type W = crate::W; + #[doc = "Register txoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoicr](rxoicr) module"] + pub type RXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXOICR; + #[doc = "`read()` method returns [rxoicr::R](rxoicr::R) reader structure"] + impl crate::Readable for RXOICR {} + #[doc = "`write(|w| ..)` method takes [rxoicr::W](rxoicr::W) writer structure"] + impl crate::Writable for RXOICR {} + #[doc = "Receive FIFO Overflow Interrupt Clear Register"] + pub mod rxoicr { + #[doc = "Reader of register rxoicr"] + pub type R = crate::R; + #[doc = "Writer for register rxoicr"] + pub type W = crate::W; + #[doc = "Register rxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive FIFO Underflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxuicr](rxuicr) module"] + pub type RXUICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXUICR; + #[doc = "`read()` method returns [rxuicr::R](rxuicr::R) reader structure"] + impl crate::Readable for RXUICR {} + #[doc = "`write(|w| ..)` method takes [rxuicr::W](rxuicr::W) writer structure"] + impl crate::Writable for RXUICR {} + #[doc = "Receive FIFO Underflow Interrupt Clear Register"] + pub mod rxuicr { + #[doc = "Reader of register rxuicr"] + pub type R = crate::R; + #[doc = "Writer for register rxuicr"] + pub type W = crate::W; + #[doc = "Register rxuicr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXUICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Multi-Master Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msticr](msticr) module"] + pub type MSTICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MSTICR; + #[doc = "`read()` method returns [msticr::R](msticr::R) reader structure"] + impl crate::Readable for MSTICR {} + #[doc = "`write(|w| ..)` method takes [msticr::W](msticr::W) writer structure"] + impl crate::Writable for MSTICR {} + #[doc = "Multi-Master Interrupt Clear Register"] + pub mod msticr { + #[doc = "Reader of register msticr"] + pub type R = crate::R; + #[doc = "Writer for register msticr"] + pub type W = crate::W; + #[doc = "Register msticr `reset()`'s with value 0"] + impl crate::ResetValue for super::MSTICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](icr) module"] + pub type ICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ICR; + #[doc = "`read()` method returns [icr::R](icr::R) reader structure"] + impl crate::Readable for ICR {} + #[doc = "`write(|w| ..)` method takes [icr::W](icr::W) writer structure"] + impl crate::Writable for ICR {} + #[doc = "Interrupt Clear Register"] + pub mod icr { + #[doc = "Reader of register icr"] + pub type R = crate::R; + #[doc = "Writer for register icr"] + pub type W = crate::W; + #[doc = "Register icr `reset()`'s with value 0"] + impl crate::ResetValue for super::ICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](dmacr) module"] + pub type DMACR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMACR; + #[doc = "`read()` method returns [dmacr::R](dmacr::R) reader structure"] + impl crate::Readable for DMACR {} + #[doc = "`write(|w| ..)` method takes [dmacr::W](dmacr::W) writer structure"] + impl crate::Writable for DMACR {} + #[doc = "DMA Control Register"] + pub mod dmacr { + #[doc = "Reader of register dmacr"] + pub type R = crate::R; + #[doc = "Writer for register dmacr"] + pub type W = crate::W; + #[doc = "Register dmacr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMACR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Transmit Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatdlr](dmatdlr) module"] + pub type DMATDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMATDLR; + #[doc = "`read()` method returns [dmatdlr::R](dmatdlr::R) reader structure"] + impl crate::Readable for DMATDLR {} + #[doc = "`write(|w| ..)` method takes [dmatdlr::W](dmatdlr::W) writer structure"] + impl crate::Writable for DMATDLR {} + #[doc = "DMA Transmit Data Level"] + pub mod dmatdlr { + #[doc = "Reader of register dmatdlr"] + pub type R = crate::R; + #[doc = "Writer for register dmatdlr"] + pub type W = crate::W; + #[doc = "Register dmatdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMATDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DMA Receive Data Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmardlr](dmardlr) module"] + pub type DMARDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMARDLR; + #[doc = "`read()` method returns [dmardlr::R](dmardlr::R) reader structure"] + impl crate::Readable for DMARDLR {} + #[doc = "`write(|w| ..)` method takes [dmardlr::W](dmardlr::W) writer structure"] + impl crate::Writable for DMARDLR {} + #[doc = "DMA Receive Data Level"] + pub mod dmardlr { + #[doc = "Reader of register dmardlr"] + pub type R = crate::R; + #[doc = "Writer for register dmardlr"] + pub type W = crate::W; + #[doc = "Register dmardlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMARDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](idr) module"] + pub type IDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IDR; + #[doc = "`read()` method returns [idr::R](idr::R) reader structure"] + impl crate::Readable for IDR {} + #[doc = "`write(|w| ..)` method takes [idr::W](idr::W) writer structure"] + impl crate::Writable for IDR {} + #[doc = "Identification Register"] + pub mod idr { + #[doc = "Reader of register idr"] + pub type R = crate::R; + #[doc = "Writer for register idr"] + pub type W = crate::W; + #[doc = "Register idr `reset()`'s with value 0"] + impl crate::ResetValue for super::IDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "DWC_ssi component version\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssic_version_id](ssic_version_id) module"] + pub type SSIC_VERSION_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SSIC_VERSION_ID; + #[doc = "`read()` method returns [ssic_version_id::R](ssic_version_id::R) reader structure"] + impl crate::Readable for SSIC_VERSION_ID {} + #[doc = "`write(|w| ..)` method takes [ssic_version_id::W](ssic_version_id::W) writer structure"] + impl crate::Writable for SSIC_VERSION_ID {} + #[doc = "DWC_ssi component version"] + pub mod ssic_version_id { + #[doc = "Reader of register ssic_version_id"] + pub type R = crate::R; + #[doc = "Writer for register ssic_version_id"] + pub type W = crate::W; + #[doc = "Register ssic_version_id `reset()`'s with value 0"] + impl crate::ResetValue for super::SSIC_VERSION_ID { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](dr) module"] + pub type DR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DR; + #[doc = "`read()` method returns [dr::R](dr::R) reader structure"] + impl crate::Readable for DR {} + #[doc = "`write(|w| ..)` method takes [dr::W](dr::W) writer structure"] + impl crate::Writable for DR {} + #[doc = "Data Register"] + pub mod dr { + #[doc = "Reader of register dr%s"] + pub type R = crate::R; + #[doc = "Writer for register dr%s"] + pub type W = crate::W; + #[doc = "Register dr%s `reset()`'s with value 0"] + impl crate::ResetValue for super::DR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RX Sample Delay Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_sample_delay](rx_sample_delay) module"] + pub type RX_SAMPLE_DELAY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RX_SAMPLE_DELAY; + #[doc = "`read()` method returns [rx_sample_delay::R](rx_sample_delay::R) reader structure"] + impl crate::Readable for RX_SAMPLE_DELAY {} + #[doc = "`write(|w| ..)` method takes [rx_sample_delay::W](rx_sample_delay::W) writer structure"] + impl crate::Writable for RX_SAMPLE_DELAY {} + #[doc = "RX Sample Delay Register"] + pub mod rx_sample_delay { + #[doc = "Reader of register rx_sample_delay"] + pub type R = crate::R; + #[doc = "Writer for register rx_sample_delay"] + pub type W = crate::W; + #[doc = "Register rx_sample_delay `reset()`'s with value 0"] + impl crate::ResetValue for super::RX_SAMPLE_DELAY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "SPI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_ctrlr0](spi_ctrlr0) module"] + pub type SPI_CTRLR0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SPI_CTRLR0; + #[doc = "`read()` method returns [spi_ctrlr0::R](spi_ctrlr0::R) reader structure"] + impl crate::Readable for SPI_CTRLR0 {} + #[doc = "`write(|w| ..)` method takes [spi_ctrlr0::W](spi_ctrlr0::W) writer structure"] + impl crate::Writable for SPI_CTRLR0 {} + #[doc = "SPI Control Register"] + pub mod spi_ctrlr0 { + #[doc = "Reader of register spi_ctrlr0"] + pub type R = crate::R; + #[doc = "Writer for register spi_ctrlr0"] + pub type W = crate::W; + #[doc = "Register spi_ctrlr0 `reset()`'s with value 0"] + impl crate::ResetValue for super::SPI_CTRLR0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "instruction_address_trans_mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum AITM_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: ADDR_STANDARD"] + ADDR_STANDARD = 1, + #[doc = "2: AS_FRAME_FORMAT"] + AS_FRAME_FORMAT = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: AITM_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `aitm`"] + pub type AITM_R = crate::R; + impl AITM_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(AITM_A::STANDARD), + 1 => Val(AITM_A::ADDR_STANDARD), + 2 => Val(AITM_A::AS_FRAME_FORMAT), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == AITM_A::STANDARD + } + #[doc = "Checks if the value of the field is `ADDR_STANDARD`"] + #[inline(always)] + pub fn is_addr_standard(&self) -> bool { + *self == AITM_A::ADDR_STANDARD + } + #[doc = "Checks if the value of the field is `AS_FRAME_FORMAT`"] + #[inline(always)] + pub fn is_as_frame_format(&self) -> bool { + *self == AITM_A::AS_FRAME_FORMAT + } + } + #[doc = "Write proxy for field `aitm`"] + pub struct AITM_W<'a> { + w: &'a mut W, + } + impl<'a> AITM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AITM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(AITM_A::STANDARD) + } + #[doc = "ADDR_STANDARD"] + #[inline(always)] + pub fn addr_standard(self) -> &'a mut W { + self.variant(AITM_A::ADDR_STANDARD) + } + #[doc = "AS_FRAME_FORMAT"] + #[inline(always)] + pub fn as_frame_format(self) -> &'a mut W { + self.variant(AITM_A::AS_FRAME_FORMAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `addr_length`"] + pub type ADDR_LENGTH_R = crate::R; + #[doc = "Write proxy for field `addr_length`"] + pub struct ADDR_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 2)) | (((value as u32) & 0x0f) << 2); + self.w + } + } + #[doc = "Reader of field `inst_length`"] + pub type INST_LENGTH_R = crate::R; + #[doc = "Write proxy for field `inst_length`"] + pub struct INST_LENGTH_W<'a> { + w: &'a mut W, + } + impl<'a> INST_LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `wait_cycles`"] + pub type WAIT_CYCLES_R = crate::R; + #[doc = "Write proxy for field `wait_cycles`"] + pub struct WAIT_CYCLES_W<'a> { + w: &'a mut W, + } + impl<'a> WAIT_CYCLES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 11)) | (((value as u32) & 0x1f) << 11); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&self) -> AITM_R { + AITM_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&self) -> ADDR_LENGTH_R { + ADDR_LENGTH_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&self) -> INST_LENGTH_R { + INST_LENGTH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&self) -> WAIT_CYCLES_R { + WAIT_CYCLES_R::new(((self.bits >> 11) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - instruction_address_trans_mode"] + #[inline(always)] + pub fn aitm(&mut self) -> AITM_W { + AITM_W { w: self } + } + #[doc = "Bits 2:5 - ADDR_LENGTH"] + #[inline(always)] + pub fn addr_length(&mut self) -> ADDR_LENGTH_W { + ADDR_LENGTH_W { w: self } + } + #[doc = "Bits 8:9 - INSTRUCTION_LENGTH"] + #[inline(always)] + pub fn inst_length(&mut self) -> INST_LENGTH_W { + INST_LENGTH_W { w: self } + } + #[doc = "Bits 11:15 - WAIT_CYCLES"] + #[inline(always)] + pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W { + WAIT_CYCLES_W { w: self } + } + } + } + #[doc = "XIP Mode bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_mode_bits](xip_mode_bits) module"] + pub type XIP_MODE_BITS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_MODE_BITS; + #[doc = "`read()` method returns [xip_mode_bits::R](xip_mode_bits::R) reader structure"] + impl crate::Readable for XIP_MODE_BITS {} + #[doc = "`write(|w| ..)` method takes [xip_mode_bits::W](xip_mode_bits::W) writer structure"] + impl crate::Writable for XIP_MODE_BITS {} + #[doc = "XIP Mode bits"] + pub mod xip_mode_bits { + #[doc = "Reader of register xip_mode_bits"] + pub type R = crate::R; + #[doc = "Writer for register xip_mode_bits"] + pub type W = crate::W; + #[doc = "Register xip_mode_bits `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_MODE_BITS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP INCR transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_incr_inst](xip_incr_inst) module"] + pub type XIP_INCR_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_INCR_INST; + #[doc = "`read()` method returns [xip_incr_inst::R](xip_incr_inst::R) reader structure"] + impl crate::Readable for XIP_INCR_INST {} + #[doc = "`write(|w| ..)` method takes [xip_incr_inst::W](xip_incr_inst::W) writer structure"] + impl crate::Writable for XIP_INCR_INST {} + #[doc = "XIP INCR transfer opcode"] + pub mod xip_incr_inst { + #[doc = "Reader of register xip_incr_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_incr_inst"] + pub type W = crate::W; + #[doc = "Register xip_incr_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_INCR_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP WRAP transfer opcode\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_wrap_inst](xip_wrap_inst) module"] + pub type XIP_WRAP_INST = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_WRAP_INST; + #[doc = "`read()` method returns [xip_wrap_inst::R](xip_wrap_inst::R) reader structure"] + impl crate::Readable for XIP_WRAP_INST {} + #[doc = "`write(|w| ..)` method takes [xip_wrap_inst::W](xip_wrap_inst::W) writer structure"] + impl crate::Writable for XIP_WRAP_INST {} + #[doc = "XIP WRAP transfer opcode"] + pub mod xip_wrap_inst { + #[doc = "Reader of register xip_wrap_inst"] + pub type R = crate::R; + #[doc = "Writer for register xip_wrap_inst"] + pub type W = crate::W; + #[doc = "Register xip_wrap_inst `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_WRAP_INST { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ctrl](xip_ctrl) module"] + pub type XIP_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CTRL; + #[doc = "`read()` method returns [xip_ctrl::R](xip_ctrl::R) reader structure"] + impl crate::Readable for XIP_CTRL {} + #[doc = "`write(|w| ..)` method takes [xip_ctrl::W](xip_ctrl::W) writer structure"] + impl crate::Writable for XIP_CTRL {} + #[doc = "XIP Control Register"] + pub mod xip_ctrl { + #[doc = "Reader of register xip_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register xip_ctrl"] + pub type W = crate::W; + #[doc = "Register xip_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Slave Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_ser](xip_ser) module"] + pub type XIP_SER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_SER; + #[doc = "`read()` method returns [xip_ser::R](xip_ser::R) reader structure"] + impl crate::Readable for XIP_SER {} + #[doc = "`write(|w| ..)` method takes [xip_ser::W](xip_ser::W) writer structure"] + impl crate::Writable for XIP_SER {} + #[doc = "XIP Slave Enable Register"] + pub mod xip_ser { + #[doc = "Reader of register xip_ser"] + pub type R = crate::R; + #[doc = "Writer for register xip_ser"] + pub type W = crate::W; + #[doc = "Register xip_ser `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_SER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xrxoicr](xrxoicr) module"] + pub type XRXOICR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XRXOICR; + #[doc = "`read()` method returns [xrxoicr::R](xrxoicr::R) reader structure"] + impl crate::Readable for XRXOICR {} + #[doc = "`write(|w| ..)` method takes [xrxoicr::W](xrxoicr::W) writer structure"] + impl crate::Writable for XRXOICR {} + #[doc = "XIP Receive FIFO Overflow Interrupt Clear Register"] + pub mod xrxoicr { + #[doc = "Reader of register xrxoicr"] + pub type R = crate::R; + #[doc = "Writer for register xrxoicr"] + pub type W = crate::W; + #[doc = "Register xrxoicr `reset()`'s with value 0"] + impl crate::ResetValue for super::XRXOICR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "XIP time out register for continuous transfers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xip_cnt_time_out](xip_cnt_time_out) module"] + pub type XIP_CNT_TIME_OUT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _XIP_CNT_TIME_OUT; + #[doc = "`read()` method returns [xip_cnt_time_out::R](xip_cnt_time_out::R) reader structure"] + impl crate::Readable for XIP_CNT_TIME_OUT {} + #[doc = "`write(|w| ..)` method takes [xip_cnt_time_out::W](xip_cnt_time_out::W) writer structure"] + impl crate::Writable for XIP_CNT_TIME_OUT {} + #[doc = "XIP time out register for continuous transfers"] + pub mod xip_cnt_time_out { + #[doc = "Reader of register xip_cnt_time_out"] + pub type R = crate::R; + #[doc = "Writer for register xip_cnt_time_out"] + pub type W = crate::W; + #[doc = "Register xip_cnt_time_out `reset()`'s with value 0"] + impl crate::ResetValue for super::XIP_CNT_TIME_OUT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "ENDIAN\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endian](endian) module"] + pub type ENDIAN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENDIAN; + #[doc = "`read()` method returns [endian::R](endian::R) reader structure"] + impl crate::Readable for ENDIAN {} + #[doc = "`write(|w| ..)` method takes [endian::W](endian::W) writer structure"] + impl crate::Writable for ENDIAN {} + #[doc = "ENDIAN"] + pub mod endian { + #[doc = "Reader of register endian"] + pub type R = crate::R; + #[doc = "Writer for register endian"] + pub type W = crate::W; + #[doc = "Register endian `reset()`'s with value 0"] + impl crate::ResetValue for super::ENDIAN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Inter-Integrated Sound Interface 0"] +pub struct I2S0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S0 {} +impl I2S0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + 0x5025_0000 as *const _ + } +} +impl Deref for I2S0 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2S0::ptr() } + } +} +#[doc = "Inter-Integrated Sound Interface 0"] +pub mod i2s0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Enable Register"] + pub ier: IER, + #[doc = "0x04 - Receiver Block Enable Register"] + pub irer: IRER, + #[doc = "0x08 - Transmitter Block Enable Register"] + pub iter: ITER, + #[doc = "0x0c - Clock Generation enable"] + pub cer: CER, + #[doc = "0x10 - Clock Configuration Register"] + pub ccr: CCR, + #[doc = "0x14 - Receiver Block FIFO Reset Register"] + pub rxffr: RXFFR, + #[doc = "0x18 - Transmitter Block FIFO Reset Register"] + pub txffr: TXFFR, + _reserved7: [u8; 4usize], + #[doc = "0x20 - Channel cluster"] + pub channel: [CHANNEL; 4], + _reserved8: [u8; 160usize], + #[doc = "0x1c0 - Receiver Block DMA Register"] + pub rxdma: RXDMA, + #[doc = "0x1c4 - Reset Receiver Block DMA Register"] + pub rrxdma: RRXDMA, + #[doc = "0x1c8 - Transmitter Block DMA Register"] + pub txdma: TXDMA, + #[doc = "0x1cc - Reset Transmitter Block DMA Register"] + pub rtxdma: RTXDMA, + _reserved12: [u8; 32usize], + #[doc = "0x1f0 - Component Parameter Register 2"] + pub i2s_comp_param_2: I2S_COMP_PARAM_2, + #[doc = "0x1f4 - Component Parameter Register 1"] + pub i2s_comp_param_1: I2S_COMP_PARAM_1, + #[doc = "0x1f8 - Component Version Register"] + pub i2s_comp_version_1: I2S_COMP_VERSION_1, + #[doc = "0x1fc - Component Type Register"] + pub i2s_comp_type: I2S_COMP_TYPE, + } + #[doc = r"Register block"] + #[repr(C)] + pub struct CHANNEL { + #[doc = "0x00 - Left Receive or Left Transmit Register"] + pub left_rxtx: self::channel::LEFT_RXTX, + #[doc = "0x04 - Right Receive or Right Transmit Register"] + pub right_rxtx: self::channel::RIGHT_RXTX, + #[doc = "0x08 - Receive Enable Register"] + pub rer: self::channel::RER, + #[doc = "0x0c - Transmit Enable Register"] + pub ter: self::channel::TER, + #[doc = "0x10 - Receive Configuration Register"] + pub rcr: self::channel::RCR, + #[doc = "0x14 - Transmit Configuration Register"] + pub tcr: self::channel::TCR, + #[doc = "0x18 - Interrupt Status Register"] + pub isr: self::channel::ISR, + #[doc = "0x1c - Interrupt Mask Register"] + pub imr: self::channel::IMR, + #[doc = "0x20 - Receive Overrun Register"] + pub ror: self::channel::ROR, + #[doc = "0x24 - Transmit Overrun Register"] + pub tor: self::channel::TOR, + #[doc = "0x28 - Receive FIFO Configuration Register"] + pub rfcr: self::channel::RFCR, + #[doc = "0x2c - Transmit FIFO Configuration Register"] + pub tfcr: self::channel::TFCR, + #[doc = "0x30 - Receive FIFO Flush Register"] + pub rff: self::channel::RFF, + #[doc = "0x34 - Transmit FIFO Flush Register"] + pub tff: self::channel::TFF, + #[doc = "0x38 - _RESERVED0"] + pub _reserved: [self::channel::_RESERVED; 2], + } + #[doc = r"Register block"] + #[doc = "Channel cluster"] + pub mod channel { + #[doc = "Left Receive or Left Transmit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [left_rxtx](left_rxtx) module"] + pub type LEFT_RXTX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LEFT_RXTX; + #[doc = "`read()` method returns [left_rxtx::R](left_rxtx::R) reader structure"] + impl crate::Readable for LEFT_RXTX {} + #[doc = "`write(|w| ..)` method takes [left_rxtx::W](left_rxtx::W) writer structure"] + impl crate::Writable for LEFT_RXTX {} + #[doc = "Left Receive or Left Transmit Register"] + pub mod left_rxtx { + #[doc = "Reader of register left_rxtx"] + pub type R = crate::R; + #[doc = "Writer for register left_rxtx"] + pub type W = crate::W; + #[doc = "Register left_rxtx `reset()`'s with value 0"] + impl crate::ResetValue for super::LEFT_RXTX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Right Receive or Right Transmit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [right_rxtx](right_rxtx) module"] + pub type RIGHT_RXTX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RIGHT_RXTX; + #[doc = "`read()` method returns [right_rxtx::R](right_rxtx::R) reader structure"] + impl crate::Readable for RIGHT_RXTX {} + #[doc = "`write(|w| ..)` method takes [right_rxtx::W](right_rxtx::W) writer structure"] + impl crate::Writable for RIGHT_RXTX {} + #[doc = "Right Receive or Right Transmit Register"] + pub mod right_rxtx { + #[doc = "Reader of register right_rxtx"] + pub type R = crate::R; + #[doc = "Writer for register right_rxtx"] + pub type W = crate::W; + #[doc = "Register right_rxtx `reset()`'s with value 0"] + impl crate::ResetValue for super::RIGHT_RXTX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Receive Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rer](rer) module"] + pub type RER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RER; + #[doc = "`read()` method returns [rer::R](rer::R) reader structure"] + impl crate::Readable for RER {} + #[doc = "`write(|w| ..)` method takes [rer::W](rer::W) writer structure"] + impl crate::Writable for RER {} + #[doc = "Receive Enable Register"] + pub mod rer { + #[doc = "Reader of register rer"] + pub type R = crate::R; + #[doc = "Writer for register rer"] + pub type W = crate::W; + #[doc = "Register rer `reset()`'s with value 0"] + impl crate::ResetValue for super::RER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxchenx`"] + pub type RXCHENX_R = crate::R; + #[doc = "Write proxy for field `rxchenx`"] + pub struct RXCHENX_W<'a> { + w: &'a mut W, + } + impl<'a> RXCHENX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receive channel enable/disable"] + #[inline(always)] + pub fn rxchenx(&self) -> RXCHENX_R { + RXCHENX_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receive channel enable/disable"] + #[inline(always)] + pub fn rxchenx(&mut self) -> RXCHENX_W { + RXCHENX_W { w: self } + } + } + } + #[doc = "Transmit Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ter](ter) module"] + pub type TER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TER; + #[doc = "`read()` method returns [ter::R](ter::R) reader structure"] + impl crate::Readable for TER {} + #[doc = "`write(|w| ..)` method takes [ter::W](ter::W) writer structure"] + impl crate::Writable for TER {} + #[doc = "Transmit Enable Register"] + pub mod ter { + #[doc = "Reader of register ter"] + pub type R = crate::R; + #[doc = "Writer for register ter"] + pub type W = crate::W; + #[doc = "Register ter `reset()`'s with value 0"] + impl crate::ResetValue for super::TER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txchenx`"] + pub type TXCHENX_R = crate::R; + #[doc = "Write proxy for field `txchenx`"] + pub struct TXCHENX_W<'a> { + w: &'a mut W, + } + impl<'a> TXCHENX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit channel enable/disable"] + #[inline(always)] + pub fn txchenx(&self) -> TXCHENX_R { + TXCHENX_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit channel enable/disable"] + #[inline(always)] + pub fn txchenx(&mut self) -> TXCHENX_W { + TXCHENX_W { w: self } + } + } + } + #[doc = "Receive Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcr](rcr) module"] + pub type RCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RCR; + #[doc = "`read()` method returns [rcr::R](rcr::R) reader structure"] + impl crate::Readable for RCR {} + #[doc = "`write(|w| ..)` method takes [rcr::W](rcr::W) writer structure"] + impl crate::Writable for RCR {} + #[doc = "Receive Configuration Register"] + pub mod rcr { + #[doc = "Reader of register rcr"] + pub type R = crate::R; + #[doc = "Writer for register rcr"] + pub type W = crate::W; + #[doc = "Register rcr `reset()`'s with value 0"] + impl crate::ResetValue for super::RCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Desired data resolution of receiver\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum WLEN_A { + #[doc = "0: Ignore the word length"] + IGNORE = 0, + #[doc = "1: 12-bit data resolution of the receiver"] + RESOLUTION12 = 1, + #[doc = "2: 16-bit data resolution of the receiver"] + RESOLUTION16 = 2, + #[doc = "3: 20-bit data resolution of the receiver"] + RESOLUTION20 = 3, + #[doc = "4: 24-bit data resolution of the receiver"] + RESOLUTION24 = 4, + #[doc = "5: 32-bit data resolution of the receiver"] + RESOLUTION32 = 5, + } + impl From for u8 { + #[inline(always)] + fn from(variant: WLEN_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `wlen`"] + pub type WLEN_R = crate::R; + impl WLEN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(WLEN_A::IGNORE), + 1 => Val(WLEN_A::RESOLUTION12), + 2 => Val(WLEN_A::RESOLUTION16), + 3 => Val(WLEN_A::RESOLUTION20), + 4 => Val(WLEN_A::RESOLUTION24), + 5 => Val(WLEN_A::RESOLUTION32), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `IGNORE`"] + #[inline(always)] + pub fn is_ignore(&self) -> bool { + *self == WLEN_A::IGNORE + } + #[doc = "Checks if the value of the field is `RESOLUTION12`"] + #[inline(always)] + pub fn is_resolution12(&self) -> bool { + *self == WLEN_A::RESOLUTION12 + } + #[doc = "Checks if the value of the field is `RESOLUTION16`"] + #[inline(always)] + pub fn is_resolution16(&self) -> bool { + *self == WLEN_A::RESOLUTION16 + } + #[doc = "Checks if the value of the field is `RESOLUTION20`"] + #[inline(always)] + pub fn is_resolution20(&self) -> bool { + *self == WLEN_A::RESOLUTION20 + } + #[doc = "Checks if the value of the field is `RESOLUTION24`"] + #[inline(always)] + pub fn is_resolution24(&self) -> bool { + *self == WLEN_A::RESOLUTION24 + } + #[doc = "Checks if the value of the field is `RESOLUTION32`"] + #[inline(always)] + pub fn is_resolution32(&self) -> bool { + *self == WLEN_A::RESOLUTION32 + } + } + #[doc = "Write proxy for field `wlen`"] + pub struct WLEN_W<'a> { + w: &'a mut W, + } + impl<'a> WLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Ignore the word length"] + #[inline(always)] + pub fn ignore(self) -> &'a mut W { + self.variant(WLEN_A::IGNORE) + } + #[doc = "12-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution12(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION12) + } + #[doc = "16-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution16(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION16) + } + #[doc = "20-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution20(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION20) + } + #[doc = "24-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution24(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION24) + } + #[doc = "32-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution32(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Desired data resolution of receiver"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - Desired data resolution of receiver"] + #[inline(always)] + pub fn wlen(&mut self) -> WLEN_W { + WLEN_W { w: self } + } + } + } + #[doc = "Transmit Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](tcr) module"] + pub type TCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TCR; + #[doc = "`read()` method returns [tcr::R](tcr::R) reader structure"] + impl crate::Readable for TCR {} + #[doc = "`write(|w| ..)` method takes [tcr::W](tcr::W) writer structure"] + impl crate::Writable for TCR {} + #[doc = "Transmit Configuration Register"] + pub mod tcr { + #[doc = "Reader of register tcr"] + pub type R = crate::R; + #[doc = "Writer for register tcr"] + pub type W = crate::W; + #[doc = "Register tcr `reset()`'s with value 0"] + impl crate::ResetValue for super::TCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Desired data resolution of transmitter"] + pub type WLEN_A = super::rcr::WLEN_A; + #[doc = "Reader of field `wlen`"] + pub type WLEN_R = crate::R; + #[doc = "Write proxy for field `wlen`"] + pub struct WLEN_W<'a> { + w: &'a mut W, + } + impl<'a> WLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Ignore the word length"] + #[inline(always)] + pub fn ignore(self) -> &'a mut W { + self.variant(WLEN_A::IGNORE) + } + #[doc = "12-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution12(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION12) + } + #[doc = "16-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution16(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION16) + } + #[doc = "20-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution20(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION20) + } + #[doc = "24-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution24(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION24) + } + #[doc = "32-bit data resolution of the receiver"] + #[inline(always)] + pub fn resolution32(self) -> &'a mut W { + self.variant(WLEN_A::RESOLUTION32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Desired data resolution of transmitter"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - Desired data resolution of transmitter"] + #[inline(always)] + pub fn wlen(&mut self) -> WLEN_W { + WLEN_W { w: self } + } + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](isr) module"] + pub type ISR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ISR; + #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] + impl crate::Readable for ISR {} + #[doc = "Interrupt Status Register"] + pub mod isr { + #[doc = "Reader of register isr"] + pub type R = crate::R; + #[doc = "Reader of field `rxda`"] + pub type RXDA_R = crate::R; + #[doc = "Reader of field `rxfo`"] + pub type RXFO_R = crate::R; + #[doc = "Reader of field `txfe`"] + pub type TXFE_R = crate::R; + #[doc = "Reader of field `txfo`"] + pub type TXFO_R = crate::R; + impl R { + #[doc = "Bit 0 - Status of receiver data avaliable interrupt"] + #[inline(always)] + pub fn rxda(&self) -> RXDA_R { + RXDA_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Status of data overrun interrupt for RX channel"] + #[inline(always)] + pub fn rxfo(&self) -> RXFO_R { + RXFO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Status of transmit empty triger interrupt"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Status of data overrun interrupt for the TX channel"] + #[inline(always)] + pub fn txfo(&self) -> TXFO_R { + TXFO_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](imr) module"] + pub type IMR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IMR; + #[doc = "`read()` method returns [imr::R](imr::R) reader structure"] + impl crate::Readable for IMR {} + #[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"] + impl crate::Writable for IMR {} + #[doc = "Interrupt Mask Register"] + pub mod imr { + #[doc = "Reader of register imr"] + pub type R = crate::R; + #[doc = "Writer for register imr"] + pub type W = crate::W; + #[doc = "Register imr `reset()`'s with value 0"] + impl crate::ResetValue for super::IMR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxdam`"] + pub type RXDAM_R = crate::R; + #[doc = "Write proxy for field `rxdam`"] + pub struct RXDAM_W<'a> { + w: &'a mut W, + } + impl<'a> RXDAM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rxfom`"] + pub type RXFOM_R = crate::R; + #[doc = "Write proxy for field `rxfom`"] + pub struct RXFOM_W<'a> { + w: &'a mut W, + } + impl<'a> RXFOM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `txfem`"] + pub type TXFEM_R = crate::R; + #[doc = "Write proxy for field `txfem`"] + pub struct TXFEM_W<'a> { + w: &'a mut W, + } + impl<'a> TXFEM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `txfom`"] + pub type TXFOM_R = crate::R; + #[doc = "Write proxy for field `txfom`"] + pub struct TXFOM_W<'a> { + w: &'a mut W, + } + impl<'a> TXFOM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0 - Mask RX FIFO data avaliable interrupt"] + #[inline(always)] + pub fn rxdam(&self) -> RXDAM_R { + RXDAM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Mask RX FIFO overrun interrupt"] + #[inline(always)] + pub fn rxfom(&self) -> RXFOM_R { + RXFOM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Mask TX FIFO empty interrupt"] + #[inline(always)] + pub fn txfem(&self) -> TXFEM_R { + TXFEM_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Mask TX FIFO overrun interrupt"] + #[inline(always)] + pub fn txfom(&self) -> TXFOM_R { + TXFOM_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Mask RX FIFO data avaliable interrupt"] + #[inline(always)] + pub fn rxdam(&mut self) -> RXDAM_W { + RXDAM_W { w: self } + } + #[doc = "Bit 1 - Mask RX FIFO overrun interrupt"] + #[inline(always)] + pub fn rxfom(&mut self) -> RXFOM_W { + RXFOM_W { w: self } + } + #[doc = "Bit 4 - Mask TX FIFO empty interrupt"] + #[inline(always)] + pub fn txfem(&mut self) -> TXFEM_W { + TXFEM_W { w: self } + } + #[doc = "Bit 5 - Mask TX FIFO overrun interrupt"] + #[inline(always)] + pub fn txfom(&mut self) -> TXFOM_W { + TXFOM_W { w: self } + } + } + } + #[doc = "Receive Overrun Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ror](ror) module"] + pub type ROR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ROR; + #[doc = "`read()` method returns [ror::R](ror::R) reader structure"] + impl crate::Readable for ROR {} + #[doc = "Receive Overrun Register"] + pub mod ror { + #[doc = "Reader of register ror"] + pub type R = crate::R; + #[doc = "Reader of field `rxcho`"] + pub type RXCHO_R = crate::R; + impl R { + #[doc = "Bit 0 - Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun"] + #[inline(always)] + pub fn rxcho(&self) -> RXCHO_R { + RXCHO_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Transmit Overrun Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tor](tor) module"] + pub type TOR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TOR; + #[doc = "`read()` method returns [tor::R](tor::R) reader structure"] + impl crate::Readable for TOR {} + #[doc = "Transmit Overrun Register"] + pub mod tor { + #[doc = "Reader of register tor"] + pub type R = crate::R; + #[doc = "Reader of field `txcho`"] + pub type TXCHO_R = crate::R; + impl R { + #[doc = "Bit 0 - Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun"] + #[inline(always)] + pub fn txcho(&self) -> TXCHO_R { + TXCHO_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Receive FIFO Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfcr](rfcr) module"] + pub type RFCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFCR; + #[doc = "`read()` method returns [rfcr::R](rfcr::R) reader structure"] + impl crate::Readable for RFCR {} + #[doc = "`write(|w| ..)` method takes [rfcr::W](rfcr::W) writer structure"] + impl crate::Writable for RFCR {} + #[doc = "Receive FIFO Configuration Register"] + pub mod rfcr { + #[doc = "Reader of register rfcr"] + pub type R = crate::R; + #[doc = "Writer for register rfcr"] + pub type W = crate::W; + #[doc = "Register rfcr `reset()`'s with value 0"] + impl crate::ResetValue for super::RFCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Trigger level in the RX FIFO at which the receiver data available interrupt generate\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum RXCHDT_A { + #[doc = "0: Interrupt trigger when FIFO level is 1"] + LEVEL1 = 0, + #[doc = "1: Interrupt trigger when FIFO level is 2"] + LEVEL2 = 1, + #[doc = "2: Interrupt trigger when FIFO level is 3"] + LEVEL3 = 2, + #[doc = "3: Interrupt trigger when FIFO level is 4"] + LEVEL4 = 3, + #[doc = "4: Interrupt trigger when FIFO level is 5"] + LEVEL5 = 4, + #[doc = "5: Interrupt trigger when FIFO level is 6"] + LEVEL6 = 5, + #[doc = "6: Interrupt trigger when FIFO level is 7"] + LEVEL7 = 6, + #[doc = "7: Interrupt trigger when FIFO level is 8"] + LEVEL8 = 7, + #[doc = "8: Interrupt trigger when FIFO level is 9"] + LEVEL9 = 8, + #[doc = "9: Interrupt trigger when FIFO level is 10"] + LEVEL10 = 9, + #[doc = "10: Interrupt trigger when FIFO level is 11"] + LEVEL11 = 10, + #[doc = "11: Interrupt trigger when FIFO level is 12"] + LEVEL12 = 11, + #[doc = "12: Interrupt trigger when FIFO level is 13"] + LEVEL13 = 12, + #[doc = "13: Interrupt trigger when FIFO level is 14"] + LEVEL14 = 13, + #[doc = "14: Interrupt trigger when FIFO level is 15"] + LEVEL15 = 14, + #[doc = "15: Interrupt trigger when FIFO level is 16"] + LEVEL16 = 15, + } + impl From for u8 { + #[inline(always)] + fn from(variant: RXCHDT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `rxchdt`"] + pub type RXCHDT_R = crate::R; + impl RXCHDT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXCHDT_A { + match self.bits { + 0 => RXCHDT_A::LEVEL1, + 1 => RXCHDT_A::LEVEL2, + 2 => RXCHDT_A::LEVEL3, + 3 => RXCHDT_A::LEVEL4, + 4 => RXCHDT_A::LEVEL5, + 5 => RXCHDT_A::LEVEL6, + 6 => RXCHDT_A::LEVEL7, + 7 => RXCHDT_A::LEVEL8, + 8 => RXCHDT_A::LEVEL9, + 9 => RXCHDT_A::LEVEL10, + 10 => RXCHDT_A::LEVEL11, + 11 => RXCHDT_A::LEVEL12, + 12 => RXCHDT_A::LEVEL13, + 13 => RXCHDT_A::LEVEL14, + 14 => RXCHDT_A::LEVEL15, + 15 => RXCHDT_A::LEVEL16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LEVEL1`"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == RXCHDT_A::LEVEL1 + } + #[doc = "Checks if the value of the field is `LEVEL2`"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == RXCHDT_A::LEVEL2 + } + #[doc = "Checks if the value of the field is `LEVEL3`"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == RXCHDT_A::LEVEL3 + } + #[doc = "Checks if the value of the field is `LEVEL4`"] + #[inline(always)] + pub fn is_level4(&self) -> bool { + *self == RXCHDT_A::LEVEL4 + } + #[doc = "Checks if the value of the field is `LEVEL5`"] + #[inline(always)] + pub fn is_level5(&self) -> bool { + *self == RXCHDT_A::LEVEL5 + } + #[doc = "Checks if the value of the field is `LEVEL6`"] + #[inline(always)] + pub fn is_level6(&self) -> bool { + *self == RXCHDT_A::LEVEL6 + } + #[doc = "Checks if the value of the field is `LEVEL7`"] + #[inline(always)] + pub fn is_level7(&self) -> bool { + *self == RXCHDT_A::LEVEL7 + } + #[doc = "Checks if the value of the field is `LEVEL8`"] + #[inline(always)] + pub fn is_level8(&self) -> bool { + *self == RXCHDT_A::LEVEL8 + } + #[doc = "Checks if the value of the field is `LEVEL9`"] + #[inline(always)] + pub fn is_level9(&self) -> bool { + *self == RXCHDT_A::LEVEL9 + } + #[doc = "Checks if the value of the field is `LEVEL10`"] + #[inline(always)] + pub fn is_level10(&self) -> bool { + *self == RXCHDT_A::LEVEL10 + } + #[doc = "Checks if the value of the field is `LEVEL11`"] + #[inline(always)] + pub fn is_level11(&self) -> bool { + *self == RXCHDT_A::LEVEL11 + } + #[doc = "Checks if the value of the field is `LEVEL12`"] + #[inline(always)] + pub fn is_level12(&self) -> bool { + *self == RXCHDT_A::LEVEL12 + } + #[doc = "Checks if the value of the field is `LEVEL13`"] + #[inline(always)] + pub fn is_level13(&self) -> bool { + *self == RXCHDT_A::LEVEL13 + } + #[doc = "Checks if the value of the field is `LEVEL14`"] + #[inline(always)] + pub fn is_level14(&self) -> bool { + *self == RXCHDT_A::LEVEL14 + } + #[doc = "Checks if the value of the field is `LEVEL15`"] + #[inline(always)] + pub fn is_level15(&self) -> bool { + *self == RXCHDT_A::LEVEL15 + } + #[doc = "Checks if the value of the field is `LEVEL16`"] + #[inline(always)] + pub fn is_level16(&self) -> bool { + *self == RXCHDT_A::LEVEL16 + } + } + #[doc = "Write proxy for field `rxchdt`"] + pub struct RXCHDT_W<'a> { + w: &'a mut W, + } + impl<'a> RXCHDT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXCHDT_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Interrupt trigger when FIFO level is 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL1) + } + #[doc = "Interrupt trigger when FIFO level is 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL2) + } + #[doc = "Interrupt trigger when FIFO level is 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL3) + } + #[doc = "Interrupt trigger when FIFO level is 4"] + #[inline(always)] + pub fn level4(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL4) + } + #[doc = "Interrupt trigger when FIFO level is 5"] + #[inline(always)] + pub fn level5(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL5) + } + #[doc = "Interrupt trigger when FIFO level is 6"] + #[inline(always)] + pub fn level6(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL6) + } + #[doc = "Interrupt trigger when FIFO level is 7"] + #[inline(always)] + pub fn level7(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL7) + } + #[doc = "Interrupt trigger when FIFO level is 8"] + #[inline(always)] + pub fn level8(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL8) + } + #[doc = "Interrupt trigger when FIFO level is 9"] + #[inline(always)] + pub fn level9(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL9) + } + #[doc = "Interrupt trigger when FIFO level is 10"] + #[inline(always)] + pub fn level10(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL10) + } + #[doc = "Interrupt trigger when FIFO level is 11"] + #[inline(always)] + pub fn level11(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL11) + } + #[doc = "Interrupt trigger when FIFO level is 12"] + #[inline(always)] + pub fn level12(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL12) + } + #[doc = "Interrupt trigger when FIFO level is 13"] + #[inline(always)] + pub fn level13(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL13) + } + #[doc = "Interrupt trigger when FIFO level is 14"] + #[inline(always)] + pub fn level14(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL14) + } + #[doc = "Interrupt trigger when FIFO level is 15"] + #[inline(always)] + pub fn level15(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL15) + } + #[doc = "Interrupt trigger when FIFO level is 16"] + #[inline(always)] + pub fn level16(self) -> &'a mut W { + self.variant(RXCHDT_A::LEVEL16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - Trigger level in the RX FIFO at which the receiver data available interrupt generate"] + #[inline(always)] + pub fn rxchdt(&self) -> RXCHDT_R { + RXCHDT_R::new((self.bits & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - Trigger level in the RX FIFO at which the receiver data available interrupt generate"] + #[inline(always)] + pub fn rxchdt(&mut self) -> RXCHDT_W { + RXCHDT_W { w: self } + } + } + } + #[doc = "Transmit FIFO Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfcr](tfcr) module"] + pub type TFCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFCR; + #[doc = "`read()` method returns [tfcr::R](tfcr::R) reader structure"] + impl crate::Readable for TFCR {} + #[doc = "`write(|w| ..)` method takes [tfcr::W](tfcr::W) writer structure"] + impl crate::Writable for TFCR {} + #[doc = "Transmit FIFO Configuration Register"] + pub mod tfcr { + #[doc = "Reader of register tfcr"] + pub type R = crate::R; + #[doc = "Writer for register tfcr"] + pub type W = crate::W; + #[doc = "Register tfcr `reset()`'s with value 0"] + impl crate::ResetValue for super::TFCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Trigger level in the TX FIFO at which the transmitter data available interrupt generate"] + pub type TXCHET_A = super::rfcr::RXCHDT_A; + #[doc = "Reader of field `txchet`"] + pub type TXCHET_R = crate::R; + #[doc = "Write proxy for field `txchet`"] + pub struct TXCHET_W<'a> { + w: &'a mut W, + } + impl<'a> TXCHET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXCHET_A) -> &'a mut W { + { + self.bits(variant.into()) + } + } + #[doc = "Interrupt trigger when FIFO level is 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL1) + } + #[doc = "Interrupt trigger when FIFO level is 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL2) + } + #[doc = "Interrupt trigger when FIFO level is 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL3) + } + #[doc = "Interrupt trigger when FIFO level is 4"] + #[inline(always)] + pub fn level4(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL4) + } + #[doc = "Interrupt trigger when FIFO level is 5"] + #[inline(always)] + pub fn level5(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL5) + } + #[doc = "Interrupt trigger when FIFO level is 6"] + #[inline(always)] + pub fn level6(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL6) + } + #[doc = "Interrupt trigger when FIFO level is 7"] + #[inline(always)] + pub fn level7(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL7) + } + #[doc = "Interrupt trigger when FIFO level is 8"] + #[inline(always)] + pub fn level8(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL8) + } + #[doc = "Interrupt trigger when FIFO level is 9"] + #[inline(always)] + pub fn level9(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL9) + } + #[doc = "Interrupt trigger when FIFO level is 10"] + #[inline(always)] + pub fn level10(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL10) + } + #[doc = "Interrupt trigger when FIFO level is 11"] + #[inline(always)] + pub fn level11(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL11) + } + #[doc = "Interrupt trigger when FIFO level is 12"] + #[inline(always)] + pub fn level12(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL12) + } + #[doc = "Interrupt trigger when FIFO level is 13"] + #[inline(always)] + pub fn level13(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL13) + } + #[doc = "Interrupt trigger when FIFO level is 14"] + #[inline(always)] + pub fn level14(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL14) + } + #[doc = "Interrupt trigger when FIFO level is 15"] + #[inline(always)] + pub fn level15(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL15) + } + #[doc = "Interrupt trigger when FIFO level is 16"] + #[inline(always)] + pub fn level16(self) -> &'a mut W { + self.variant(TXCHET_A::LEVEL16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - Trigger level in the TX FIFO at which the transmitter data available interrupt generate"] + #[inline(always)] + pub fn txchet(&self) -> TXCHET_R { + TXCHET_R::new((self.bits & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - Trigger level in the TX FIFO at which the transmitter data available interrupt generate"] + #[inline(always)] + pub fn txchet(&mut self) -> TXCHET_W { + TXCHET_W { w: self } + } + } + } + #[doc = "Receive FIFO Flush Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rff](rff) module"] + pub type RFF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RFF; + #[doc = "`read()` method returns [rff::R](rff::R) reader structure"] + impl crate::Readable for RFF {} + #[doc = "`write(|w| ..)` method takes [rff::W](rff::W) writer structure"] + impl crate::Writable for RFF {} + #[doc = "Receive FIFO Flush Register"] + pub mod rff { + #[doc = "Reader of register rff"] + pub type R = crate::R; + #[doc = "Writer for register rff"] + pub type W = crate::W; + #[doc = "Register rff `reset()`'s with value 0"] + impl crate::ResetValue for super::RFF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Receiver channel FIFO reset\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum RXCHFR_A { + #[doc = "0: Not flush an individual FIFO"] + NOT_FLUSH = 0, + #[doc = "1: Flush an indiviadual FIFO"] + FLUSH = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: RXCHFR_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `rxchfr`"] + pub type RXCHFR_R = crate::R; + impl RXCHFR_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXCHFR_A { + match self.bits { + false => RXCHFR_A::NOT_FLUSH, + true => RXCHFR_A::FLUSH, + } + } + #[doc = "Checks if the value of the field is `NOT_FLUSH`"] + #[inline(always)] + pub fn is_not_flush(&self) -> bool { + *self == RXCHFR_A::NOT_FLUSH + } + #[doc = "Checks if the value of the field is `FLUSH`"] + #[inline(always)] + pub fn is_flush(&self) -> bool { + *self == RXCHFR_A::FLUSH + } + } + #[doc = "Write proxy for field `rxchfr`"] + pub struct RXCHFR_W<'a> { + w: &'a mut W, + } + impl<'a> RXCHFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXCHFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush an individual FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RXCHFR_A::NOT_FLUSH) + } + #[doc = "Flush an indiviadual FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RXCHFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receiver channel FIFO reset"] + #[inline(always)] + pub fn rxchfr(&self) -> RXCHFR_R { + RXCHFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receiver channel FIFO reset"] + #[inline(always)] + pub fn rxchfr(&mut self) -> RXCHFR_W { + RXCHFR_W { w: self } + } + } + } + #[doc = "Transmit FIFO Flush Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tff](tff) module"] + pub type TFF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TFF; + #[doc = "`read()` method returns [tff::R](tff::R) reader structure"] + impl crate::Readable for TFF {} + #[doc = "`write(|w| ..)` method takes [tff::W](tff::W) writer structure"] + impl crate::Writable for TFF {} + #[doc = "Transmit FIFO Flush Register"] + pub mod tff { + #[doc = "Reader of register tff"] + pub type R = crate::R; + #[doc = "Writer for register tff"] + pub type W = crate::W; + #[doc = "Register tff `reset()`'s with value 0"] + impl crate::ResetValue for super::TFF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Transmit channel FIFO reset"] + pub type RTXCHFR_A = super::rff::RXCHFR_A; + #[doc = "Reader of field `rtxchfr`"] + pub type RTXCHFR_R = crate::R; + #[doc = "Write proxy for field `rtxchfr`"] + pub struct RTXCHFR_W<'a> { + w: &'a mut W, + } + impl<'a> RTXCHFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTXCHFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush an individual FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RTXCHFR_A::NOT_FLUSH) + } + #[doc = "Flush an indiviadual FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RTXCHFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmit channel FIFO reset"] + #[inline(always)] + pub fn rtxchfr(&self) -> RTXCHFR_R { + RTXCHFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmit channel FIFO reset"] + #[inline(always)] + pub fn rtxchfr(&mut self) -> RTXCHFR_W { + RTXCHFR_W { w: self } + } + } + } + #[doc = "_RESERVED0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_reserved](_reserved) module"] + pub type _RESERVED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct __RESERVED; + #[doc = "`read()` method returns [_reserved::R](_reserved::R) reader structure"] + impl crate::Readable for _RESERVED {} + #[doc = "`write(|w| ..)` method takes [_reserved::W](_reserved::W) writer structure"] + impl crate::Writable for _RESERVED {} + #[doc = "_RESERVED0"] + pub mod _reserved { + #[doc = "Reader of register _reserved%s"] + pub type R = crate::R; + #[doc = "Writer for register _reserved%s"] + pub type W = crate::W; + #[doc = "Register _reserved%s `reset()`'s with value 0"] + impl crate::ResetValue for super::_RESERVED { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](ier) module"] + pub type IER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IER; + #[doc = "`read()` method returns [ier::R](ier::R) reader structure"] + impl crate::Readable for IER {} + #[doc = "`write(|w| ..)` method takes [ier::W](ier::W) writer structure"] + impl crate::Writable for IER {} + #[doc = "Enable Register"] + pub mod ier { + #[doc = "Reader of register ier"] + pub type R = crate::R; + #[doc = "Writer for register ier"] + pub type W = crate::W; + #[doc = "Register ier `reset()`'s with value 0"] + impl crate::ResetValue for super::IER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `ien`"] + pub type IEN_R = crate::R; + #[doc = "Write proxy for field `ien`"] + pub struct IEN_W<'a> { + w: &'a mut W, + } + impl<'a> IEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - I2S Enable"] + #[inline(always)] + pub fn ien(&self) -> IEN_R { + IEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - I2S Enable"] + #[inline(always)] + pub fn ien(&mut self) -> IEN_W { + IEN_W { w: self } + } + } + } + #[doc = "Receiver Block Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irer](irer) module"] + pub type IRER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IRER; + #[doc = "`read()` method returns [irer::R](irer::R) reader structure"] + impl crate::Readable for IRER {} + #[doc = "`write(|w| ..)` method takes [irer::W](irer::W) writer structure"] + impl crate::Writable for IRER {} + #[doc = "Receiver Block Enable Register"] + pub mod irer { + #[doc = "Reader of register irer"] + pub type R = crate::R; + #[doc = "Writer for register irer"] + pub type W = crate::W; + #[doc = "Register irer `reset()`'s with value 0"] + impl crate::ResetValue for super::IRER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rxen`"] + pub type RXEN_R = crate::R; + #[doc = "Write proxy for field `rxen`"] + pub struct RXEN_W<'a> { + w: &'a mut W, + } + impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receiver block enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receiver block enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + } + } + #[doc = "Transmitter Block Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iter](iter) module"] + pub type ITER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ITER; + #[doc = "`read()` method returns [iter::R](iter::R) reader structure"] + impl crate::Readable for ITER {} + #[doc = "`write(|w| ..)` method takes [iter::W](iter::W) writer structure"] + impl crate::Writable for ITER {} + #[doc = "Transmitter Block Enable Register"] + pub mod iter { + #[doc = "Reader of register iter"] + pub type R = crate::R; + #[doc = "Writer for register iter"] + pub type W = crate::W; + #[doc = "Register iter `reset()`'s with value 0"] + impl crate::ResetValue for super::ITER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `txen`"] + pub type TXEN_R = crate::R; + #[doc = "Write proxy for field `txen`"] + pub struct TXEN_W<'a> { + w: &'a mut W, + } + impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + } + } + #[doc = "Clock Generation enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cer](cer) module"] + pub type CER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CER; + #[doc = "`read()` method returns [cer::R](cer::R) reader structure"] + impl crate::Readable for CER {} + #[doc = "`write(|w| ..)` method takes [cer::W](cer::W) writer structure"] + impl crate::Writable for CER {} + #[doc = "Clock Generation enable"] + pub mod cer { + #[doc = "Reader of register cer"] + pub type R = crate::R; + #[doc = "Writer for register cer"] + pub type W = crate::W; + #[doc = "Register cer `reset()`'s with value 0"] + impl crate::ResetValue for super::CER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clken`"] + pub type CLKEN_R = crate::R; + #[doc = "Write proxy for field `clken`"] + pub struct CLKEN_W<'a> { + w: &'a mut W, + } + impl<'a> CLKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn clken(&self) -> CLKEN_R { + CLKEN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmitter block enable"] + #[inline(always)] + pub fn clken(&mut self) -> CLKEN_W { + CLKEN_W { w: self } + } + } + } + #[doc = "Clock Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](ccr) module"] + pub type CCR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CCR; + #[doc = "`read()` method returns [ccr::R](ccr::R) reader structure"] + impl crate::Readable for CCR {} + #[doc = "`write(|w| ..)` method takes [ccr::W](ccr::W) writer structure"] + impl crate::Writable for CCR {} + #[doc = "Clock Configuration Register"] + pub mod ccr { + #[doc = "Reader of register ccr"] + pub type R = crate::R; + #[doc = "Writer for register ccr"] + pub type W = crate::W; + #[doc = "Register ccr `reset()`'s with value 0"] + impl crate::ResetValue for super::CCR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Gating of sclk\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum CLK_GATE_A { + #[doc = "0: Clock gating is disabled"] + NO = 0, + #[doc = "1: Gating after 12 sclk cycles"] + CYCLES12 = 1, + #[doc = "2: Gating after 16 sclk cycles"] + CYCLES16 = 2, + #[doc = "3: Gating after 20 sclk cycles"] + CYCLES20 = 3, + #[doc = "4: Gating after 24 sclk cycles"] + CYCLES24 = 4, + } + impl From for u8 { + #[inline(always)] + fn from(variant: CLK_GATE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `clk_gate`"] + pub type CLK_GATE_R = crate::R; + impl CLK_GATE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(CLK_GATE_A::NO), + 1 => Val(CLK_GATE_A::CYCLES12), + 2 => Val(CLK_GATE_A::CYCLES16), + 3 => Val(CLK_GATE_A::CYCLES20), + 4 => Val(CLK_GATE_A::CYCLES24), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `NO`"] + #[inline(always)] + pub fn is_no(&self) -> bool { + *self == CLK_GATE_A::NO + } + #[doc = "Checks if the value of the field is `CYCLES12`"] + #[inline(always)] + pub fn is_cycles12(&self) -> bool { + *self == CLK_GATE_A::CYCLES12 + } + #[doc = "Checks if the value of the field is `CYCLES16`"] + #[inline(always)] + pub fn is_cycles16(&self) -> bool { + *self == CLK_GATE_A::CYCLES16 + } + #[doc = "Checks if the value of the field is `CYCLES20`"] + #[inline(always)] + pub fn is_cycles20(&self) -> bool { + *self == CLK_GATE_A::CYCLES20 + } + #[doc = "Checks if the value of the field is `CYCLES24`"] + #[inline(always)] + pub fn is_cycles24(&self) -> bool { + *self == CLK_GATE_A::CYCLES24 + } + } + #[doc = "Write proxy for field `clk_gate`"] + pub struct CLK_GATE_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_GATE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLK_GATE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clock gating is disabled"] + #[inline(always)] + pub fn no(self) -> &'a mut W { + self.variant(CLK_GATE_A::NO) + } + #[doc = "Gating after 12 sclk cycles"] + #[inline(always)] + pub fn cycles12(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES12) + } + #[doc = "Gating after 16 sclk cycles"] + #[inline(always)] + pub fn cycles16(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES16) + } + #[doc = "Gating after 20 sclk cycles"] + #[inline(always)] + pub fn cycles20(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES20) + } + #[doc = "Gating after 24 sclk cycles"] + #[inline(always)] + pub fn cycles24(self) -> &'a mut W { + self.variant(CLK_GATE_A::CYCLES24) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum CLK_WORD_SIZE_A { + #[doc = "0: 16 sclk cycles"] + CYCLES16 = 0, + #[doc = "1: 24 sclk cycles"] + CYCLES24 = 1, + #[doc = "2: 32 sclk cycles"] + CYCLES32 = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: CLK_WORD_SIZE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `clk_word_size`"] + pub type CLK_WORD_SIZE_R = crate::R; + impl CLK_WORD_SIZE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(CLK_WORD_SIZE_A::CYCLES16), + 1 => Val(CLK_WORD_SIZE_A::CYCLES24), + 2 => Val(CLK_WORD_SIZE_A::CYCLES32), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `CYCLES16`"] + #[inline(always)] + pub fn is_cycles16(&self) -> bool { + *self == CLK_WORD_SIZE_A::CYCLES16 + } + #[doc = "Checks if the value of the field is `CYCLES24`"] + #[inline(always)] + pub fn is_cycles24(&self) -> bool { + *self == CLK_WORD_SIZE_A::CYCLES24 + } + #[doc = "Checks if the value of the field is `CYCLES32`"] + #[inline(always)] + pub fn is_cycles32(&self) -> bool { + *self == CLK_WORD_SIZE_A::CYCLES32 + } + } + #[doc = "Write proxy for field `clk_word_size`"] + pub struct CLK_WORD_SIZE_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_WORD_SIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLK_WORD_SIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16 sclk cycles"] + #[inline(always)] + pub fn cycles16(self) -> &'a mut W { + self.variant(CLK_WORD_SIZE_A::CYCLES16) + } + #[doc = "24 sclk cycles"] + #[inline(always)] + pub fn cycles24(self) -> &'a mut W { + self.variant(CLK_WORD_SIZE_A::CYCLES24) + } + #[doc = "32 sclk cycles"] + #[inline(always)] + pub fn cycles32(self) -> &'a mut W { + self.variant(CLK_WORD_SIZE_A::CYCLES32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3); + self.w + } + } + #[doc = "Alignment mode setting\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum ALIGN_MODE_A { + #[doc = "1: Standard I2S format"] + STANDARD = 1, + #[doc = "2: Right aligned format"] + RIGHT = 2, + #[doc = "4: Left aligned format"] + LEFT = 4, + } + impl From for u8 { + #[inline(always)] + fn from(variant: ALIGN_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `align_mode`"] + pub type ALIGN_MODE_R = crate::R; + impl ALIGN_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 1 => Val(ALIGN_MODE_A::STANDARD), + 2 => Val(ALIGN_MODE_A::RIGHT), + 4 => Val(ALIGN_MODE_A::LEFT), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == ALIGN_MODE_A::STANDARD + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + *self == ALIGN_MODE_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + *self == ALIGN_MODE_A::LEFT + } + } + #[doc = "Write proxy for field `align_mode`"] + pub struct ALIGN_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> ALIGN_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ALIGN_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard I2S format"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(ALIGN_MODE_A::STANDARD) + } + #[doc = "Right aligned format"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(ALIGN_MODE_A::RIGHT) + } + #[doc = "Left aligned format"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(ALIGN_MODE_A::LEFT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5); + self.w + } + } + #[doc = "Reader of field `dma_tx_en`"] + pub type DMA_TX_EN_R = crate::R; + #[doc = "Write proxy for field `dma_tx_en`"] + pub struct DMA_TX_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_TX_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `dma_rx_en`"] + pub type DMA_RX_EN_R = crate::R; + #[doc = "Write proxy for field `dma_rx_en`"] + pub struct DMA_RX_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_RX_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `dma_divide_16`"] + pub type DMA_DIVIDE_16_R = crate::R; + #[doc = "Write proxy for field `dma_divide_16`"] + pub struct DMA_DIVIDE_16_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_DIVIDE_16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `sign_expand_en`"] + pub type SIGN_EXPAND_EN_R = crate::R; + #[doc = "Write proxy for field `sign_expand_en`"] + pub struct SIGN_EXPAND_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SIGN_EXPAND_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Gating of sclk"] + #[inline(always)] + pub fn clk_gate(&self) -> CLK_GATE_R { + CLK_GATE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode"] + #[inline(always)] + pub fn clk_word_size(&self) -> CLK_WORD_SIZE_R { + CLK_WORD_SIZE_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - Alignment mode setting"] + #[inline(always)] + pub fn align_mode(&self) -> ALIGN_MODE_R { + ALIGN_MODE_R::new(((self.bits >> 5) & 0x07) as u8) + } + #[doc = "Bit 8 - DMA transmit enable control"] + #[inline(always)] + pub fn dma_tx_en(&self) -> DMA_TX_EN_R { + DMA_TX_EN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DMA receive enable control"] + #[inline(always)] + pub fn dma_rx_en(&self) -> DMA_RX_EN_R { + DMA_RX_EN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en"] + #[inline(always)] + pub fn dma_divide_16(&self) -> DMA_DIVIDE_16_R { + DMA_DIVIDE_16_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - SIGN_EXPAND_EN"] + #[inline(always)] + pub fn sign_expand_en(&self) -> SIGN_EXPAND_EN_R { + SIGN_EXPAND_EN_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:2 - Gating of sclk"] + #[inline(always)] + pub fn clk_gate(&mut self) -> CLK_GATE_W { + CLK_GATE_W { w: self } + } + #[doc = "Bits 3:4 - The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode"] + #[inline(always)] + pub fn clk_word_size(&mut self) -> CLK_WORD_SIZE_W { + CLK_WORD_SIZE_W { w: self } + } + #[doc = "Bits 5:7 - Alignment mode setting"] + #[inline(always)] + pub fn align_mode(&mut self) -> ALIGN_MODE_W { + ALIGN_MODE_W { w: self } + } + #[doc = "Bit 8 - DMA transmit enable control"] + #[inline(always)] + pub fn dma_tx_en(&mut self) -> DMA_TX_EN_W { + DMA_TX_EN_W { w: self } + } + #[doc = "Bit 9 - DMA receive enable control"] + #[inline(always)] + pub fn dma_rx_en(&mut self) -> DMA_RX_EN_W { + DMA_RX_EN_W { w: self } + } + #[doc = "Bit 10 - Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en"] + #[inline(always)] + pub fn dma_divide_16(&mut self) -> DMA_DIVIDE_16_W { + DMA_DIVIDE_16_W { w: self } + } + #[doc = "Bit 11 - SIGN_EXPAND_EN"] + #[inline(always)] + pub fn sign_expand_en(&mut self) -> SIGN_EXPAND_EN_W { + SIGN_EXPAND_EN_W { w: self } + } + } + } + #[doc = "Receiver Block FIFO Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxffr](rxffr) module"] + pub type RXFFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFFR; + #[doc = "`read()` method returns [rxffr::R](rxffr::R) reader structure"] + impl crate::Readable for RXFFR {} + #[doc = "`write(|w| ..)` method takes [rxffr::W](rxffr::W) writer structure"] + impl crate::Writable for RXFFR {} + #[doc = "Receiver Block FIFO Reset Register"] + pub mod rxffr { + #[doc = "Reader of register rxffr"] + pub type R = crate::R; + #[doc = "Writer for register rxffr"] + pub type W = crate::W; + #[doc = "Register rxffr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFFR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Receiver FIFO reset\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum RXFFR_A { + #[doc = "0: Not flush FIFO"] + NOT_FLUSH = 0, + #[doc = "1: Flush FIFO"] + FLUSH = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: RXFFR_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `rxffr`"] + pub type RXFFR_R = crate::R; + impl RXFFR_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXFFR_A { + match self.bits { + false => RXFFR_A::NOT_FLUSH, + true => RXFFR_A::FLUSH, + } + } + #[doc = "Checks if the value of the field is `NOT_FLUSH`"] + #[inline(always)] + pub fn is_not_flush(&self) -> bool { + *self == RXFFR_A::NOT_FLUSH + } + #[doc = "Checks if the value of the field is `FLUSH`"] + #[inline(always)] + pub fn is_flush(&self) -> bool { + *self == RXFFR_A::FLUSH + } + } + #[doc = "Write proxy for field `rxffr`"] + pub struct RXFFR_W<'a> { + w: &'a mut W, + } + impl<'a> RXFFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXFFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RXFFR_A::NOT_FLUSH) + } + #[doc = "Flush FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RXFFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Receiver FIFO reset"] + #[inline(always)] + pub fn rxffr(&self) -> RXFFR_R { + RXFFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Receiver FIFO reset"] + #[inline(always)] + pub fn rxffr(&mut self) -> RXFFR_W { + RXFFR_W { w: self } + } + } + } + #[doc = "Transmitter Block FIFO Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txffr](txffr) module"] + pub type TXFFR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFFR; + #[doc = "`read()` method returns [txffr::R](txffr::R) reader structure"] + impl crate::Readable for TXFFR {} + #[doc = "`write(|w| ..)` method takes [txffr::W](txffr::W) writer structure"] + impl crate::Writable for TXFFR {} + #[doc = "Transmitter Block FIFO Reset Register"] + pub mod txffr { + #[doc = "Reader of register txffr"] + pub type R = crate::R; + #[doc = "Writer for register txffr"] + pub type W = crate::W; + #[doc = "Register txffr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFFR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Transmitter FIFO reset"] + pub type RXFFR_A = super::rxffr::RXFFR_A; + #[doc = "Reader of field `rxffr`"] + pub type RXFFR_R = crate::R; + #[doc = "Write proxy for field `rxffr`"] + pub struct RXFFR_W<'a> { + w: &'a mut W, + } + impl<'a> RXFFR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXFFR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Not flush FIFO"] + #[inline(always)] + pub fn not_flush(self) -> &'a mut W { + self.variant(RXFFR_A::NOT_FLUSH) + } + #[doc = "Flush FIFO"] + #[inline(always)] + pub fn flush(self) -> &'a mut W { + self.variant(RXFFR_A::FLUSH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Transmitter FIFO reset"] + #[inline(always)] + pub fn rxffr(&self) -> RXFFR_R { + RXFFR_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Transmitter FIFO reset"] + #[inline(always)] + pub fn rxffr(&mut self) -> RXFFR_W { + RXFFR_W { w: self } + } + } + } + #[doc = "Receiver Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdma](rxdma) module"] + pub type RXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXDMA; + #[doc = "`read()` method returns [rxdma::R](rxdma::R) reader structure"] + impl crate::Readable for RXDMA {} + #[doc = "`write(|w| ..)` method takes [rxdma::W](rxdma::W) writer structure"] + impl crate::Writable for RXDMA {} + #[doc = "Receiver Block DMA Register"] + pub mod rxdma { + #[doc = "Reader of register rxdma"] + pub type R = crate::R; + #[doc = "Writer for register rxdma"] + pub type W = crate::W; + #[doc = "Register rxdma `reset()`'s with value 0"] + impl crate::ResetValue for super::RXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Reset Receiver Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rrxdma](rrxdma) module"] + pub type RRXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RRXDMA; + #[doc = "`read()` method returns [rrxdma::R](rrxdma::R) reader structure"] + impl crate::Readable for RRXDMA {} + #[doc = "`write(|w| ..)` method takes [rrxdma::W](rrxdma::W) writer structure"] + impl crate::Writable for RRXDMA {} + #[doc = "Reset Receiver Block DMA Register"] + pub mod rrxdma { + #[doc = "Reader of register rrxdma"] + pub type R = crate::R; + #[doc = "Writer for register rrxdma"] + pub type W = crate::W; + #[doc = "Register rrxdma `reset()`'s with value 0"] + impl crate::ResetValue for super::RRXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Transmitter Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdma](txdma) module"] + pub type TXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXDMA; + #[doc = "`read()` method returns [txdma::R](txdma::R) reader structure"] + impl crate::Readable for TXDMA {} + #[doc = "`write(|w| ..)` method takes [txdma::W](txdma::W) writer structure"] + impl crate::Writable for TXDMA {} + #[doc = "Transmitter Block DMA Register"] + pub mod txdma { + #[doc = "Reader of register txdma"] + pub type R = crate::R; + #[doc = "Writer for register txdma"] + pub type W = crate::W; + #[doc = "Register txdma `reset()`'s with value 0"] + impl crate::ResetValue for super::TXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Reset Transmitter Block DMA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtxdma](rtxdma) module"] + pub type RTXDMA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RTXDMA; + #[doc = "`read()` method returns [rtxdma::R](rtxdma::R) reader structure"] + impl crate::Readable for RTXDMA {} + #[doc = "`write(|w| ..)` method takes [rtxdma::W](rtxdma::W) writer structure"] + impl crate::Writable for RTXDMA {} + #[doc = "Reset Transmitter Block DMA Register"] + pub mod rtxdma { + #[doc = "Reader of register rtxdma"] + pub type R = crate::R; + #[doc = "Writer for register rtxdma"] + pub type W = crate::W; + #[doc = "Register rtxdma `reset()`'s with value 0"] + impl crate::ResetValue for super::RTXDMA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Parameter Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_param_2](i2s_comp_param_2) module"] + pub type I2S_COMP_PARAM_2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_PARAM_2; + #[doc = "`read()` method returns [i2s_comp_param_2::R](i2s_comp_param_2::R) reader structure"] + impl crate::Readable for I2S_COMP_PARAM_2 {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_param_2::W](i2s_comp_param_2::W) writer structure"] + impl crate::Writable for I2S_COMP_PARAM_2 {} + #[doc = "Component Parameter Register 2"] + pub mod i2s_comp_param_2 { + #[doc = "Reader of register i2s_comp_param_2"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_param_2"] + pub type W = crate::W; + #[doc = "Register i2s_comp_param_2 `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_PARAM_2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Parameter Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_param_1](i2s_comp_param_1) module"] + pub type I2S_COMP_PARAM_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_PARAM_1; + #[doc = "`read()` method returns [i2s_comp_param_1::R](i2s_comp_param_1::R) reader structure"] + impl crate::Readable for I2S_COMP_PARAM_1 {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_param_1::W](i2s_comp_param_1::W) writer structure"] + impl crate::Writable for I2S_COMP_PARAM_1 {} + #[doc = "Component Parameter Register 1"] + pub mod i2s_comp_param_1 { + #[doc = "Reader of register i2s_comp_param_1"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_param_1"] + pub type W = crate::W; + #[doc = "Register i2s_comp_param_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_PARAM_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_version_1](i2s_comp_version_1) module"] + pub type I2S_COMP_VERSION_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_VERSION_1; + #[doc = "`read()` method returns [i2s_comp_version_1::R](i2s_comp_version_1::R) reader structure"] + impl crate::Readable for I2S_COMP_VERSION_1 {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_version_1::W](i2s_comp_version_1::W) writer structure"] + impl crate::Writable for I2S_COMP_VERSION_1 {} + #[doc = "Component Version Register"] + pub mod i2s_comp_version_1 { + #[doc = "Reader of register i2s_comp_version_1"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_version_1"] + pub type W = crate::W; + #[doc = "Register i2s_comp_version_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_VERSION_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_comp_type](i2s_comp_type) module"] + pub type I2S_COMP_TYPE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _I2S_COMP_TYPE; + #[doc = "`read()` method returns [i2s_comp_type::R](i2s_comp_type::R) reader structure"] + impl crate::Readable for I2S_COMP_TYPE {} + #[doc = "`write(|w| ..)` method takes [i2s_comp_type::W](i2s_comp_type::W) writer structure"] + impl crate::Writable for I2S_COMP_TYPE {} + #[doc = "Component Type Register"] + pub mod i2s_comp_type { + #[doc = "Reader of register i2s_comp_type"] + pub type R = crate::R; + #[doc = "Writer for register i2s_comp_type"] + pub type W = crate::W; + #[doc = "Register i2s_comp_type `reset()`'s with value 0"] + impl crate::ResetValue for super::I2S_COMP_TYPE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Audio Processor"] +pub struct APU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for APU {} +impl APU { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const apu::RegisterBlock { + 0x5025_0200 as *const _ + } +} +impl Deref for APU { + type Target = apu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*APU::ptr() } + } +} +#[doc = "Audio Processor"] +pub mod apu { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Channel Config Register"] + pub ch_cfg: CH_CFG, + #[doc = "0x04 - Control Register"] + pub ctl: CTL, + #[doc = "0x08 - Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)"] + pub dir_bidx: [DIR_BIDX; 32], + #[doc = "0x88 - FIR0 pre-filter coefficients"] + pub pre_fir0_coef: [PRE_FIR0_COEF; 9], + #[doc = "0xac - FIR0 post-filter coefficients"] + pub post_fir0_coef: [POST_FIR0_COEF; 9], + #[doc = "0xd0 - FIR1 pre-filter coeffecients"] + pub pre_fir1_coef: [PRE_FIR1_COEF; 9], + #[doc = "0xf4 - FIR1 post-filter coefficients"] + pub post_fir1_coef: [POST_FIR1_COEF; 9], + #[doc = "0x118 - Downsize Config Register"] + pub dwsz_cfg: DWSZ_CFG, + #[doc = "0x11c - FFT Config Register"] + pub fft_cfg: FFT_CFG, + #[doc = "0x120 - Read register for DMA to sample-out buffers"] + pub sobuf_dma_rdata: SOBUF_DMA_RDATA, + #[doc = "0x124 - Read register for DMA to voice-out buffers"] + pub vobuf_dma_rdata: VOBUF_DMA_RDATA, + #[doc = "0x128 - Interrupt Status Register"] + pub int_stat: INT_STAT, + #[doc = "0x12c - Interrupt Mask Register"] + pub int_mask: INT_MASK, + #[doc = "0x130 - Saturation Counter"] + pub sat_counter: SAT_COUNTER, + #[doc = "0x134 - Saturation Limits"] + pub sat_limits: SAT_LIMITS, + } + #[doc = "Channel Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch_cfg](ch_cfg) module"] + pub type CH_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CH_CFG; + #[doc = "`read()` method returns [ch_cfg::R](ch_cfg::R) reader structure"] + impl crate::Readable for CH_CFG {} + #[doc = "`write(|w| ..)` method takes [ch_cfg::W](ch_cfg::W) writer structure"] + impl crate::Writable for CH_CFG {} + #[doc = "Channel Config Register"] + pub mod ch_cfg { + #[doc = "Reader of register ch_cfg"] + pub type R = crate::R; + #[doc = "Writer for register ch_cfg"] + pub type W = crate::W; + #[doc = "Register ch_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CH_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `sound_ch_en`"] + pub type SOUND_CH_EN_R = crate::R; + #[doc = "Write proxy for field `sound_ch_en`"] + pub struct SOUND_CH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SOUND_CH_EN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `target_dir`"] + pub type TARGET_DIR_R = crate::R; + #[doc = "Write proxy for field `target_dir`"] + pub struct TARGET_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> TARGET_DIR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); + self.w + } + } + #[doc = "Reader of field `audio_gain`"] + pub type AUDIO_GAIN_R = crate::R; + #[doc = "Write proxy for field `audio_gain`"] + pub struct AUDIO_GAIN_W<'a> { + w: &'a mut W, + } + impl<'a> AUDIO_GAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 12)) | (((value as u32) & 0x07ff) << 12); + self.w + } + } + #[doc = "Reader of field `data_src_mode`"] + pub type DATA_SRC_MODE_R = crate::R; + #[doc = "Write proxy for field `data_src_mode`"] + pub struct DATA_SRC_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_SRC_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Write proxy for field `we_sound_ch_en`"] + pub struct WE_SOUND_CH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_SOUND_CH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); + self.w + } + } + #[doc = "Write proxy for field `we_target_dir`"] + pub struct WE_TARGET_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> WE_TARGET_DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + #[doc = "Write proxy for field `we_audio_gain`"] + pub struct WE_AUDIO_GAIN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_AUDIO_GAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); + self.w + } + } + #[doc = "Write proxy for field `we_data_src_mode`"] + pub struct WE_DATA_SRC_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> WE_DATA_SRC_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - BF unit sound channel enable control bits"] + #[inline(always)] + pub fn sound_ch_en(&self) -> SOUND_CH_EN_R { + SOUND_CH_EN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Target direction select for valid voice output"] + #[inline(always)] + pub fn target_dir(&self) -> TARGET_DIR_R { + TARGET_DIR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:22 - Audio sample gain factor"] + #[inline(always)] + pub fn audio_gain(&self) -> AUDIO_GAIN_R { + AUDIO_GAIN_R::new(((self.bits >> 12) & 0x07ff) as u16) + } + #[doc = "Bit 24 - Audio data source configure parameter"] + #[inline(always)] + pub fn data_src_mode(&self) -> DATA_SRC_MODE_R { + DATA_SRC_MODE_R::new(((self.bits >> 24) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - BF unit sound channel enable control bits"] + #[inline(always)] + pub fn sound_ch_en(&mut self) -> SOUND_CH_EN_W { + SOUND_CH_EN_W { w: self } + } + #[doc = "Bits 8:11 - Target direction select for valid voice output"] + #[inline(always)] + pub fn target_dir(&mut self) -> TARGET_DIR_W { + TARGET_DIR_W { w: self } + } + #[doc = "Bits 12:22 - Audio sample gain factor"] + #[inline(always)] + pub fn audio_gain(&mut self) -> AUDIO_GAIN_W { + AUDIO_GAIN_W { w: self } + } + #[doc = "Bit 24 - Audio data source configure parameter"] + #[inline(always)] + pub fn data_src_mode(&mut self) -> DATA_SRC_MODE_W { + DATA_SRC_MODE_W { w: self } + } + #[doc = "Bit 28 - Write enable for sound_ch_en parameter"] + #[inline(always)] + pub fn we_sound_ch_en(&mut self) -> WE_SOUND_CH_EN_W { + WE_SOUND_CH_EN_W { w: self } + } + #[doc = "Bit 29 - Write enable for target_dir parameter"] + #[inline(always)] + pub fn we_target_dir(&mut self) -> WE_TARGET_DIR_W { + WE_TARGET_DIR_W { w: self } + } + #[doc = "Bit 30 - Write enable for audio_gain parameter"] + #[inline(always)] + pub fn we_audio_gain(&mut self) -> WE_AUDIO_GAIN_W { + WE_AUDIO_GAIN_W { w: self } + } + #[doc = "Bit 31 - Write enable for data_out_mode parameter"] + #[inline(always)] + pub fn we_data_src_mode(&mut self) -> WE_DATA_SRC_MODE_W { + WE_DATA_SRC_MODE_W { w: self } + } + } + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](ctl) module"] + pub type CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CTL; + #[doc = "`read()` method returns [ctl::R](ctl::R) reader structure"] + impl crate::Readable for CTL {} + #[doc = "`write(|w| ..)` method takes [ctl::W](ctl::W) writer structure"] + impl crate::Writable for CTL {} + #[doc = "Control Register"] + pub mod ctl { + #[doc = "Reader of register ctl"] + pub type R = crate::R; + #[doc = "Writer for register ctl"] + pub type W = crate::W; + #[doc = "Register ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::CTL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_search_en`"] + pub type DIR_SEARCH_EN_R = crate::R; + #[doc = "Write proxy for field `dir_search_en`"] + pub struct DIR_SEARCH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_SEARCH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `search_path_reset`"] + pub type SEARCH_PATH_RESET_R = crate::R; + #[doc = "Write proxy for field `search_path_reset`"] + pub struct SEARCH_PATH_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SEARCH_PATH_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `stream_gen_en`"] + pub type STREAM_GEN_EN_R = crate::R; + #[doc = "Write proxy for field `stream_gen_en`"] + pub struct STREAM_GEN_EN_W<'a> { + w: &'a mut W, + } + impl<'a> STREAM_GEN_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `voice_gen_path_reset`"] + pub type VOICE_GEN_PATH_RESET_R = crate::R; + #[doc = "Write proxy for field `voice_gen_path_reset`"] + pub struct VOICE_GEN_PATH_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> VOICE_GEN_PATH_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `update_voice_dir`"] + pub type UPDATE_VOICE_DIR_R = crate::R; + #[doc = "Write proxy for field `update_voice_dir`"] + pub struct UPDATE_VOICE_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> UPDATE_VOICE_DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Write proxy for field `we_dir_search_en`"] + pub struct WE_DIR_SEARCH_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_DIR_SEARCH_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Write proxy for field `we_search_path_rst`"] + pub struct WE_SEARCH_PATH_RST_W<'a> { + w: &'a mut W, + } + impl<'a> WE_SEARCH_PATH_RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Write proxy for field `we_stream_gen`"] + pub struct WE_STREAM_GEN_W<'a> { + w: &'a mut W, + } + impl<'a> WE_STREAM_GEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Write proxy for field `we_voice_gen_path_rst`"] + pub struct WE_VOICE_GEN_PATH_RST_W<'a> { + w: &'a mut W, + } + impl<'a> WE_VOICE_GEN_PATH_RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Write proxy for field `we_update_voice_dir`"] + pub struct WE_UPDATE_VOICE_DIR_W<'a> { + w: &'a mut W, + } + impl<'a> WE_UPDATE_VOICE_DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bit 0 - Sound direction searching enable bit"] + #[inline(always)] + pub fn dir_search_en(&self) -> DIR_SEARCH_EN_R { + DIR_SEARCH_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Reset all control logic on direction search processing path"] + #[inline(always)] + pub fn search_path_reset(&self) -> SEARCH_PATH_RESET_R { + SEARCH_PATH_RESET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Valid voice sample stream generation enable bit"] + #[inline(always)] + pub fn stream_gen_en(&self) -> STREAM_GEN_EN_R { + STREAM_GEN_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Reset all control logic on voice stream generating path"] + #[inline(always)] + pub fn voice_gen_path_reset(&self) -> VOICE_GEN_PATH_RESET_R { + VOICE_GEN_PATH_RESET_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Switch to a new voice source direction"] + #[inline(always)] + pub fn update_voice_dir(&self) -> UPDATE_VOICE_DIR_R { + UPDATE_VOICE_DIR_R::new(((self.bits >> 6) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Sound direction searching enable bit"] + #[inline(always)] + pub fn dir_search_en(&mut self) -> DIR_SEARCH_EN_W { + DIR_SEARCH_EN_W { w: self } + } + #[doc = "Bit 1 - Reset all control logic on direction search processing path"] + #[inline(always)] + pub fn search_path_reset(&mut self) -> SEARCH_PATH_RESET_W { + SEARCH_PATH_RESET_W { w: self } + } + #[doc = "Bit 4 - Valid voice sample stream generation enable bit"] + #[inline(always)] + pub fn stream_gen_en(&mut self) -> STREAM_GEN_EN_W { + STREAM_GEN_EN_W { w: self } + } + #[doc = "Bit 5 - Reset all control logic on voice stream generating path"] + #[inline(always)] + pub fn voice_gen_path_reset(&mut self) -> VOICE_GEN_PATH_RESET_W { + VOICE_GEN_PATH_RESET_W { w: self } + } + #[doc = "Bit 6 - Switch to a new voice source direction"] + #[inline(always)] + pub fn update_voice_dir(&mut self) -> UPDATE_VOICE_DIR_W { + UPDATE_VOICE_DIR_W { w: self } + } + #[doc = "Bit 8 - Write enable for we_dir_search_en parameter"] + #[inline(always)] + pub fn we_dir_search_en(&mut self) -> WE_DIR_SEARCH_EN_W { + WE_DIR_SEARCH_EN_W { w: self } + } + #[doc = "Bit 9 - Write enable for we_search_path_rst parameter"] + #[inline(always)] + pub fn we_search_path_rst(&mut self) -> WE_SEARCH_PATH_RST_W { + WE_SEARCH_PATH_RST_W { w: self } + } + #[doc = "Bit 10 - Write enable for we_stream_gen parameter"] + #[inline(always)] + pub fn we_stream_gen(&mut self) -> WE_STREAM_GEN_W { + WE_STREAM_GEN_W { w: self } + } + #[doc = "Bit 11 - Write enable for we_voice_gen_path_rst parameter"] + #[inline(always)] + pub fn we_voice_gen_path_rst(&mut self) -> WE_VOICE_GEN_PATH_RST_W { + WE_VOICE_GEN_PATH_RST_W { w: self } + } + #[doc = "Bit 12 - Write enable for we_update_voice_dir parameter"] + #[inline(always)] + pub fn we_update_voice_dir(&mut self) -> WE_UPDATE_VOICE_DIR_W { + WE_UPDATE_VOICE_DIR_W { w: self } + } + } + } + #[doc = "Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir_bidx](dir_bidx) module"] + pub type DIR_BIDX = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DIR_BIDX; + #[doc = "`read()` method returns [dir_bidx::R](dir_bidx::R) reader structure"] + impl crate::Readable for DIR_BIDX {} + #[doc = "`write(|w| ..)` method takes [dir_bidx::W](dir_bidx::W) writer structure"] + impl crate::Writable for DIR_BIDX {} + #[doc = "Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices)"] + pub mod dir_bidx { + #[doc = "Reader of register dir_bidx[%s]"] + pub type R = crate::R; + #[doc = "Writer for register dir_bidx[%s]"] + pub type W = crate::W; + #[doc = "Register dir_bidx[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::DIR_BIDX { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of fields `rd_idx(0-3)`"] + pub type RD_IDX_R = crate::R; + #[doc = "Write proxy for fields `rd_idx(0-3)`"] + pub struct RD_IDX_W<'a> { + w: &'a mut W, + offset: usize, + } + impl<'a> RD_IDX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << self.offset)) + | (((value as u32) & 0x3f) << self.offset); + self.w + } + } + impl R { + #[doc = "rd_idx(0-3)"] + #[inline(always)] + pub unsafe fn rd_idx(&self, n: usize) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> n * 8) & 0x3f) as u8) + } + #[doc = "Bits 0:5 - rd_idx0"] + #[inline(always)] + pub fn rd_idx0(&self) -> RD_IDX_R { + RD_IDX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - rd_idx1"] + #[inline(always)] + pub fn rd_idx1(&self) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - rd_idx2"] + #[inline(always)] + pub fn rd_idx2(&self) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - rd_idx3"] + #[inline(always)] + pub fn rd_idx3(&self) -> RD_IDX_R { + RD_IDX_R::new(((self.bits >> 24) & 0x3f) as u8) + } + } + impl W { + #[doc = "rd_idx(0-3)"] + #[inline(always)] + pub unsafe fn rd_idx(&mut self, n: usize) -> RD_IDX_W { + RD_IDX_W { + w: self, + offset: n * 8, + } + } + #[doc = "Bits 0:5 - rd_idx0"] + #[inline(always)] + pub fn rd_idx0(&mut self) -> RD_IDX_W { + RD_IDX_W { w: self, offset: 0 } + } + #[doc = "Bits 8:13 - rd_idx1"] + #[inline(always)] + pub fn rd_idx1(&mut self) -> RD_IDX_W { + RD_IDX_W { w: self, offset: 8 } + } + #[doc = "Bits 16:21 - rd_idx2"] + #[inline(always)] + pub fn rd_idx2(&mut self) -> RD_IDX_W { + RD_IDX_W { + w: self, + offset: 16, + } + } + #[doc = "Bits 24:29 - rd_idx3"] + #[inline(always)] + pub fn rd_idx3(&mut self) -> RD_IDX_W { + RD_IDX_W { + w: self, + offset: 24, + } + } + } + } + #[doc = "FIR0 pre-filter coefficients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pre_fir0_coef](pre_fir0_coef) module"] + pub type PRE_FIR0_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PRE_FIR0_COEF; + #[doc = "`read()` method returns [pre_fir0_coef::R](pre_fir0_coef::R) reader structure"] + impl crate::Readable for PRE_FIR0_COEF {} + #[doc = "`write(|w| ..)` method takes [pre_fir0_coef::W](pre_fir0_coef::W) writer structure"] + impl crate::Writable for PRE_FIR0_COEF {} + #[doc = "FIR0 pre-filter coefficients"] + pub mod pre_fir0_coef { + #[doc = "Reader of register pre_fir0_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register pre_fir0_coef[%s]"] + pub type W = crate::W; + #[doc = "Register pre_fir0_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PRE_FIR0_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "FIR0 post-filter coefficients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [post_fir0_coef](post_fir0_coef) module"] + pub type POST_FIR0_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _POST_FIR0_COEF; + #[doc = "`read()` method returns [post_fir0_coef::R](post_fir0_coef::R) reader structure"] + impl crate::Readable for POST_FIR0_COEF {} + #[doc = "`write(|w| ..)` method takes [post_fir0_coef::W](post_fir0_coef::W) writer structure"] + impl crate::Writable for POST_FIR0_COEF {} + #[doc = "FIR0 post-filter coefficients"] + pub mod post_fir0_coef { + #[doc = "Reader of register post_fir0_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register post_fir0_coef[%s]"] + pub type W = crate::W; + #[doc = "Register post_fir0_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::POST_FIR0_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "FIR1 pre-filter coeffecients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pre_fir1_coef](pre_fir1_coef) module"] + pub type PRE_FIR1_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PRE_FIR1_COEF; + #[doc = "`read()` method returns [pre_fir1_coef::R](pre_fir1_coef::R) reader structure"] + impl crate::Readable for PRE_FIR1_COEF {} + #[doc = "`write(|w| ..)` method takes [pre_fir1_coef::W](pre_fir1_coef::W) writer structure"] + impl crate::Writable for PRE_FIR1_COEF {} + #[doc = "FIR1 pre-filter coeffecients"] + pub mod pre_fir1_coef { + #[doc = "Reader of register pre_fir1_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register pre_fir1_coef[%s]"] + pub type W = crate::W; + #[doc = "Register pre_fir1_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::PRE_FIR1_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "FIR1 post-filter coefficients\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [post_fir1_coef](post_fir1_coef) module"] + pub type POST_FIR1_COEF = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _POST_FIR1_COEF; + #[doc = "`read()` method returns [post_fir1_coef::R](post_fir1_coef::R) reader structure"] + impl crate::Readable for POST_FIR1_COEF {} + #[doc = "`write(|w| ..)` method takes [post_fir1_coef::W](post_fir1_coef::W) writer structure"] + impl crate::Writable for POST_FIR1_COEF {} + #[doc = "FIR1 post-filter coefficients"] + pub mod post_fir1_coef { + #[doc = "Reader of register post_fir1_coef[%s]"] + pub type R = crate::R; + #[doc = "Writer for register post_fir1_coef[%s]"] + pub type W = crate::W; + #[doc = "Register post_fir1_coef[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::POST_FIR1_COEF { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tap0`"] + pub type TAP0_R = crate::R; + #[doc = "Write proxy for field `tap0`"] + pub struct TAP0_W<'a> { + w: &'a mut W, + } + impl<'a> TAP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `tap1`"] + pub type TAP1_R = crate::R; + #[doc = "Write proxy for field `tap1`"] + pub struct TAP1_W<'a> { + w: &'a mut W, + } + impl<'a> TAP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&self) -> TAP0_R { + TAP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&self) -> TAP1_R { + TAP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Tap 0"] + #[inline(always)] + pub fn tap0(&mut self) -> TAP0_W { + TAP0_W { w: self } + } + #[doc = "Bits 16:31 - Tap 1"] + #[inline(always)] + pub fn tap1(&mut self) -> TAP1_W { + TAP1_W { w: self } + } + } + } + #[doc = "Downsize Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dwsz_cfg](dwsz_cfg) module"] + pub type DWSZ_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DWSZ_CFG; + #[doc = "`read()` method returns [dwsz_cfg::R](dwsz_cfg::R) reader structure"] + impl crate::Readable for DWSZ_CFG {} + #[doc = "`write(|w| ..)` method takes [dwsz_cfg::W](dwsz_cfg::W) writer structure"] + impl crate::Writable for DWSZ_CFG {} + #[doc = "Downsize Config Register"] + pub mod dwsz_cfg { + #[doc = "Reader of register dwsz_cfg"] + pub type R = crate::R; + #[doc = "Writer for register dwsz_cfg"] + pub type W = crate::W; + #[doc = "Register dwsz_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::DWSZ_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_dwn_siz_rate`"] + pub type DIR_DWN_SIZ_RATE_R = crate::R; + #[doc = "Write proxy for field `dir_dwn_siz_rate`"] + pub struct DIR_DWN_SIZ_RATE_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_DWN_SIZ_RATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `voc_dwn_siz_rate`"] + pub type VOC_DWN_SIZ_RATE_R = crate::R; + #[doc = "Write proxy for field `voc_dwn_siz_rate`"] + pub struct VOC_DWN_SIZ_RATE_W<'a> { + w: &'a mut W, + } + impl<'a> VOC_DWN_SIZ_RATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); + self.w + } + } + #[doc = "Reader of field `smpl_shift_bits`"] + pub type SMPL_SHIFT_BITS_R = crate::R; + #[doc = "Write proxy for field `smpl_shift_bits`"] + pub struct SMPL_SHIFT_BITS_W<'a> { + w: &'a mut W, + } + impl<'a> SMPL_SHIFT_BITS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - Down-sizing ratio used for direction searching"] + #[inline(always)] + pub fn dir_dwn_siz_rate(&self) -> DIR_DWN_SIZ_RATE_R { + DIR_DWN_SIZ_RATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Down-sizing ratio used for voice stream generation"] + #[inline(always)] + pub fn voc_dwn_siz_rate(&self) -> VOC_DWN_SIZ_RATE_R { + VOC_DWN_SIZ_RATE_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Sample precision reduction when the source sound sample precision is 20/24/32 bits"] + #[inline(always)] + pub fn smpl_shift_bits(&self) -> SMPL_SHIFT_BITS_R { + SMPL_SHIFT_BITS_R::new(((self.bits >> 8) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - Down-sizing ratio used for direction searching"] + #[inline(always)] + pub fn dir_dwn_siz_rate(&mut self) -> DIR_DWN_SIZ_RATE_W { + DIR_DWN_SIZ_RATE_W { w: self } + } + #[doc = "Bits 4:7 - Down-sizing ratio used for voice stream generation"] + #[inline(always)] + pub fn voc_dwn_siz_rate(&mut self) -> VOC_DWN_SIZ_RATE_W { + VOC_DWN_SIZ_RATE_W { w: self } + } + #[doc = "Bits 8:12 - Sample precision reduction when the source sound sample precision is 20/24/32 bits"] + #[inline(always)] + pub fn smpl_shift_bits(&mut self) -> SMPL_SHIFT_BITS_W { + SMPL_SHIFT_BITS_W { w: self } + } + } + } + #[doc = "FFT Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fft_cfg](fft_cfg) module"] + pub type FFT_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FFT_CFG; + #[doc = "`read()` method returns [fft_cfg::R](fft_cfg::R) reader structure"] + impl crate::Readable for FFT_CFG {} + #[doc = "`write(|w| ..)` method takes [fft_cfg::W](fft_cfg::W) writer structure"] + impl crate::Writable for FFT_CFG {} + #[doc = "FFT Config Register"] + pub mod fft_cfg { + #[doc = "Reader of register fft_cfg"] + pub type R = crate::R; + #[doc = "Writer for register fft_cfg"] + pub type W = crate::W; + #[doc = "Register fft_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::FFT_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Read register for DMA to sample-out buffers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sobuf_dma_rdata](sobuf_dma_rdata) module"] + pub type SOBUF_DMA_RDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SOBUF_DMA_RDATA; + #[doc = "`read()` method returns [sobuf_dma_rdata::R](sobuf_dma_rdata::R) reader structure"] + impl crate::Readable for SOBUF_DMA_RDATA {} + #[doc = "`write(|w| ..)` method takes [sobuf_dma_rdata::W](sobuf_dma_rdata::W) writer structure"] + impl crate::Writable for SOBUF_DMA_RDATA {} + #[doc = "Read register for DMA to sample-out buffers"] + pub mod sobuf_dma_rdata { + #[doc = "Reader of register sobuf_dma_rdata"] + pub type R = crate::R; + #[doc = "Writer for register sobuf_dma_rdata"] + pub type W = crate::W; + #[doc = "Register sobuf_dma_rdata `reset()`'s with value 0"] + impl crate::ResetValue for super::SOBUF_DMA_RDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Read register for DMA to voice-out buffers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vobuf_dma_rdata](vobuf_dma_rdata) module"] + pub type VOBUF_DMA_RDATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _VOBUF_DMA_RDATA; + #[doc = "`read()` method returns [vobuf_dma_rdata::R](vobuf_dma_rdata::R) reader structure"] + impl crate::Readable for VOBUF_DMA_RDATA {} + #[doc = "`write(|w| ..)` method takes [vobuf_dma_rdata::W](vobuf_dma_rdata::W) writer structure"] + impl crate::Writable for VOBUF_DMA_RDATA {} + #[doc = "Read register for DMA to voice-out buffers"] + pub mod vobuf_dma_rdata { + #[doc = "Reader of register vobuf_dma_rdata"] + pub type R = crate::R; + #[doc = "Writer for register vobuf_dma_rdata"] + pub type W = crate::W; + #[doc = "Register vobuf_dma_rdata `reset()`'s with value 0"] + impl crate::ResetValue for super::VOBUF_DMA_RDATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_stat](int_stat) module"] + pub type INT_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INT_STAT; + #[doc = "`read()` method returns [int_stat::R](int_stat::R) reader structure"] + impl crate::Readable for INT_STAT {} + #[doc = "`write(|w| ..)` method takes [int_stat::W](int_stat::W) writer structure"] + impl crate::Writable for INT_STAT {} + #[doc = "Interrupt Status Register"] + pub mod int_stat { + #[doc = "Reader of register int_stat"] + pub type R = crate::R; + #[doc = "Writer for register int_stat"] + pub type W = crate::W; + #[doc = "Register int_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::INT_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_search_data_rdy`"] + pub type DIR_SEARCH_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `dir_search_data_rdy`"] + pub struct DIR_SEARCH_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_SEARCH_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `voc_buf_data_rdy`"] + pub type VOC_BUF_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `voc_buf_data_rdy`"] + pub struct VOC_BUF_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> VOC_BUF_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&self) -> DIR_SEARCH_DATA_RDY_R { + DIR_SEARCH_DATA_RDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&self) -> VOC_BUF_DATA_RDY_R { + VOC_BUF_DATA_RDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&mut self) -> DIR_SEARCH_DATA_RDY_W { + DIR_SEARCH_DATA_RDY_W { w: self } + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&mut self) -> VOC_BUF_DATA_RDY_W { + VOC_BUF_DATA_RDY_W { w: self } + } + } + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_mask](int_mask) module"] + pub type INT_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INT_MASK; + #[doc = "`read()` method returns [int_mask::R](int_mask::R) reader structure"] + impl crate::Readable for INT_MASK {} + #[doc = "`write(|w| ..)` method takes [int_mask::W](int_mask::W) writer structure"] + impl crate::Writable for INT_MASK {} + #[doc = "Interrupt Mask Register"] + pub mod int_mask { + #[doc = "Reader of register int_mask"] + pub type R = crate::R; + #[doc = "Writer for register int_mask"] + pub type W = crate::W; + #[doc = "Register int_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INT_MASK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dir_search_data_rdy`"] + pub type DIR_SEARCH_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `dir_search_data_rdy`"] + pub struct DIR_SEARCH_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> DIR_SEARCH_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `voc_buf_data_rdy`"] + pub type VOC_BUF_DATA_RDY_R = crate::R; + #[doc = "Write proxy for field `voc_buf_data_rdy`"] + pub struct VOC_BUF_DATA_RDY_W<'a> { + w: &'a mut W, + } + impl<'a> VOC_BUF_DATA_RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&self) -> DIR_SEARCH_DATA_RDY_R { + DIR_SEARCH_DATA_RDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&self) -> VOC_BUF_DATA_RDY_R { + VOC_BUF_DATA_RDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Sound direction searching data ready interrupt event"] + #[inline(always)] + pub fn dir_search_data_rdy(&mut self) -> DIR_SEARCH_DATA_RDY_W { + DIR_SEARCH_DATA_RDY_W { w: self } + } + #[doc = "Bit 1 - Voice output stream buffer data ready interrupt event"] + #[inline(always)] + pub fn voc_buf_data_rdy(&mut self) -> VOC_BUF_DATA_RDY_W { + VOC_BUF_DATA_RDY_W { w: self } + } + } + } + #[doc = "Saturation Counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sat_counter](sat_counter) module"] + pub type SAT_COUNTER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAT_COUNTER; + #[doc = "`read()` method returns [sat_counter::R](sat_counter::R) reader structure"] + impl crate::Readable for SAT_COUNTER {} + #[doc = "`write(|w| ..)` method takes [sat_counter::W](sat_counter::W) writer structure"] + impl crate::Writable for SAT_COUNTER {} + #[doc = "Saturation Counter"] + pub mod sat_counter { + #[doc = "Reader of register sat_counter"] + pub type R = crate::R; + #[doc = "Writer for register sat_counter"] + pub type W = crate::W; + #[doc = "Register sat_counter `reset()`'s with value 0"] + impl crate::ResetValue for super::SAT_COUNTER { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `counter`"] + pub type COUNTER_R = crate::R; + #[doc = "Write proxy for field `counter`"] + pub struct COUNTER_W<'a> { + w: &'a mut W, + } + impl<'a> COUNTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `total`"] + pub type TOTAL_R = crate::R; + #[doc = "Write proxy for field `total`"] + pub struct TOTAL_W<'a> { + w: &'a mut W, + } + impl<'a> TOTAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Counter"] + #[inline(always)] + pub fn counter(&self) -> COUNTER_R { + COUNTER_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Total"] + #[inline(always)] + pub fn total(&self) -> TOTAL_R { + TOTAL_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Counter"] + #[inline(always)] + pub fn counter(&mut self) -> COUNTER_W { + COUNTER_W { w: self } + } + #[doc = "Bits 16:31 - Total"] + #[inline(always)] + pub fn total(&mut self) -> TOTAL_W { + TOTAL_W { w: self } + } + } + } + #[doc = "Saturation Limits\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sat_limits](sat_limits) module"] + pub type SAT_LIMITS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAT_LIMITS; + #[doc = "`read()` method returns [sat_limits::R](sat_limits::R) reader structure"] + impl crate::Readable for SAT_LIMITS {} + #[doc = "`write(|w| ..)` method takes [sat_limits::W](sat_limits::W) writer structure"] + impl crate::Writable for SAT_LIMITS {} + #[doc = "Saturation Limits"] + pub mod sat_limits { + #[doc = "Reader of register sat_limits"] + pub type R = crate::R; + #[doc = "Writer for register sat_limits"] + pub type W = crate::W; + #[doc = "Register sat_limits `reset()`'s with value 0"] + impl crate::ResetValue for super::SAT_LIMITS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `upper`"] + pub type UPPER_R = crate::R; + #[doc = "Write proxy for field `upper`"] + pub struct UPPER_W<'a> { + w: &'a mut W, + } + impl<'a> UPPER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `bottom`"] + pub type BOTTOM_R = crate::R; + #[doc = "Write proxy for field `bottom`"] + pub struct BOTTOM_W<'a> { + w: &'a mut W, + } + impl<'a> BOTTOM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - Upper limit"] + #[inline(always)] + pub fn upper(&self) -> UPPER_R { + UPPER_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Bottom limit"] + #[inline(always)] + pub fn bottom(&self) -> BOTTOM_R { + BOTTOM_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - Upper limit"] + #[inline(always)] + pub fn upper(&mut self) -> UPPER_W { + UPPER_W { w: self } + } + #[doc = "Bits 16:31 - Bottom limit"] + #[inline(always)] + pub fn bottom(&mut self) -> BOTTOM_W { + BOTTOM_W { w: self } + } + } + } +} +#[doc = "Inter-Integrated Sound Interface 1"] +pub struct I2S1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S1 {} +impl I2S1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + 0x5026_0000 as *const _ + } +} +impl Deref for I2S1 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2S1::ptr() } + } +} +#[doc = "Inter-Integrated Sound Interface 2"] +pub struct I2S2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S2 {} +impl I2S2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + 0x5027_0000 as *const _ + } +} +impl Deref for I2S2 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2S2::ptr() } + } +} +#[doc = "Inter-Integrated Circuit Bus 0"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + 0x5028_0000 as *const _ + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2C0::ptr() } + } +} +#[doc = "Inter-Integrated Circuit Bus 0"] +pub mod i2c0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub con: CON, + #[doc = "0x04 - Target Address Register"] + pub tar: TAR, + #[doc = "0x08 - Slave Address Register"] + pub sar: SAR, + _reserved3: [u8; 4usize], + #[doc = "0x10 - Data Buffer and Command Register"] + pub data_cmd: DATA_CMD, + #[doc = "0x14 - Standard Speed Clock SCL High Count Register"] + pub ss_scl_hcnt: SS_SCL_HCNT, + #[doc = "0x18 - Standard Speed Clock SCL Low Count Register"] + pub ss_scl_lcnt: SS_SCL_LCNT, + _reserved6: [u8; 16usize], + #[doc = "0x2c - Interrupt Status Register"] + pub intr_stat: INTR_STAT, + #[doc = "0x30 - Interrupt Mask Register"] + pub intr_mask: INTR_MASK, + #[doc = "0x34 - Raw Interrupt Status Register"] + pub raw_intr_stat: RAW_INTR_STAT, + #[doc = "0x38 - Receive FIFO Threshold Register"] + pub rx_tl: RX_TL, + #[doc = "0x3c - Transmit FIFO Threshold Register"] + pub tx_tl: TX_TL, + #[doc = "0x40 - Clear Combined and Individual Interrupt Register"] + pub clr_intr: CLR_INTR, + #[doc = "0x44 - Clear RX_UNDER Interrupt Register"] + pub clr_rx_under: CLR_RX_UNDER, + #[doc = "0x48 - Clear RX_OVER Interrupt Register"] + pub clr_rx_over: CLR_RX_OVER, + #[doc = "0x4c - Clear TX_OVER Interrupt Register"] + pub clr_tx_over: CLR_TX_OVER, + #[doc = "0x50 - Clear RD_REQ Interrupt Register"] + pub clr_rd_req: CLR_RD_REQ, + #[doc = "0x54 - Clear TX_ABRT Interrupt Register"] + pub clr_tx_abrt: CLR_TX_ABRT, + #[doc = "0x58 - Clear RX_DONE Interrupt Register"] + pub clr_rx_done: CLR_RX_DONE, + #[doc = "0x5c - Clear ACTIVITY Interrupt Register"] + pub clr_activity: CLR_ACTIVITY, + #[doc = "0x60 - Clear STOP_DET Interrupt Register"] + pub clr_stop_det: CLR_STOP_DET, + #[doc = "0x64 - Clear START_DET Interrupt Register"] + pub clr_start_det: CLR_START_DET, + #[doc = "0x68 - I2C Clear GEN_CALL Interrupt Register"] + pub clr_gen_call: CLR_GEN_CALL, + #[doc = "0x6c - Enable Register"] + pub enable: ENABLE, + #[doc = "0x70 - Status Register"] + pub status: STATUS, + #[doc = "0x74 - Transmit FIFO Level Register"] + pub txflr: TXFLR, + #[doc = "0x78 - Receive FIFO Level Register"] + pub rxflr: RXFLR, + #[doc = "0x7c - SDA Hold Time Length Register"] + pub sda_hold: SDA_HOLD, + #[doc = "0x80 - Transmit Abort Source Register"] + pub tx_abrt_source: TX_ABRT_SOURCE, + _reserved28: [u8; 4usize], + #[doc = "0x88 - I2C DMA Control Register"] + pub dma_cr: DMA_CR, + #[doc = "0x8c - DMA Transmit Data Level Register"] + pub dma_tdlr: DMA_TDLR, + #[doc = "0x90 - DMA Receive Data Level Register"] + pub dma_rdlr: DMA_RDLR, + #[doc = "0x94 - SDA Setup Register"] + pub sda_setup: SDA_SETUP, + #[doc = "0x98 - ACK General Call Register"] + pub general_call: GENERAL_CALL, + #[doc = "0x9c - Enable Status Register"] + pub enable_status: ENABLE_STATUS, + #[doc = "0xa0 - SS, FS or FM+ spike suppression limit"] + pub fs_spklen: FS_SPKLEN, + _reserved35: [u8; 80usize], + #[doc = "0xf4 - Component Parameter Register 1"] + pub comp_param_1: COMP_PARAM_1, + #[doc = "0xf8 - Component Version Register"] + pub comp_version: COMP_VERSION, + #[doc = "0xfc - Component Type Register"] + pub comp_type: COMP_TYPE, + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [con](con) module"] + pub type CON = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CON; + #[doc = "`read()` method returns [con::R](con::R) reader structure"] + impl crate::Readable for CON {} + #[doc = "`write(|w| ..)` method takes [con::W](con::W) writer structure"] + impl crate::Writable for CON {} + #[doc = "Control Register"] + pub mod con { + #[doc = "Reader of register con"] + pub type R = crate::R; + #[doc = "Writer for register con"] + pub type W = crate::W; + #[doc = "Register con `reset()`'s with value 0"] + impl crate::ResetValue for super::CON { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `master_mode`"] + pub type MASTER_MODE_R = crate::R; + #[doc = "Write proxy for field `master_mode`"] + pub struct MASTER_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> MASTER_MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Speed\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum SPEED_A { + #[doc = "0: STANDARD"] + STANDARD = 0, + #[doc = "1: FAST"] + FAST = 1, + #[doc = "2: HIGHSPEED"] + HIGHSPEED = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `speed`"] + pub type SPEED_R = crate::R; + impl SPEED_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(SPEED_A::STANDARD), + 1 => Val(SPEED_A::FAST), + 2 => Val(SPEED_A::HIGHSPEED), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `STANDARD`"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == SPEED_A::STANDARD + } + #[doc = "Checks if the value of the field is `FAST`"] + #[inline(always)] + pub fn is_fast(&self) -> bool { + *self == SPEED_A::FAST + } + #[doc = "Checks if the value of the field is `HIGHSPEED`"] + #[inline(always)] + pub fn is_highspeed(&self) -> bool { + *self == SPEED_A::HIGHSPEED + } + } + #[doc = "Write proxy for field `speed`"] + pub struct SPEED_W<'a> { + w: &'a mut W, + } + impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "STANDARD"] + #[inline(always)] + pub fn standard(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD) + } + #[doc = "FAST"] + #[inline(always)] + pub fn fast(self) -> &'a mut W { + self.variant(SPEED_A::FAST) + } + #[doc = "HIGHSPEED"] + #[inline(always)] + pub fn highspeed(self) -> &'a mut W { + self.variant(SPEED_A::HIGHSPEED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1); + self.w + } + } + #[doc = "Slave address width\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ADDR_SLAVE_WIDTH_A { + #[doc = "0: 7-bit address"] + B7 = 0, + #[doc = "1: 10-bit address"] + B10 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ADDR_SLAVE_WIDTH_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `addr_slave_width`"] + pub type ADDR_SLAVE_WIDTH_R = crate::R; + impl ADDR_SLAVE_WIDTH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ADDR_SLAVE_WIDTH_A { + match self.bits { + false => ADDR_SLAVE_WIDTH_A::B7, + true => ADDR_SLAVE_WIDTH_A::B10, + } + } + #[doc = "Checks if the value of the field is `B7`"] + #[inline(always)] + pub fn is_b7(&self) -> bool { + *self == ADDR_SLAVE_WIDTH_A::B7 + } + #[doc = "Checks if the value of the field is `B10`"] + #[inline(always)] + pub fn is_b10(&self) -> bool { + *self == ADDR_SLAVE_WIDTH_A::B10 + } + } + #[doc = "Write proxy for field `addr_slave_width`"] + pub struct ADDR_SLAVE_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_SLAVE_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ADDR_SLAVE_WIDTH_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "7-bit address"] + #[inline(always)] + pub fn b7(self) -> &'a mut W { + self.variant(ADDR_SLAVE_WIDTH_A::B7) + } + #[doc = "10-bit address"] + #[inline(always)] + pub fn b10(self) -> &'a mut W { + self.variant(ADDR_SLAVE_WIDTH_A::B10) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `restart_en`"] + pub type RESTART_EN_R = crate::R; + #[doc = "Write proxy for field `restart_en`"] + pub struct RESTART_EN_W<'a> { + w: &'a mut W, + } + impl<'a> RESTART_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `slave_disable`"] + pub type SLAVE_DISABLE_R = crate::R; + #[doc = "Write proxy for field `slave_disable`"] + pub struct SLAVE_DISABLE_W<'a> { + w: &'a mut W, + } + impl<'a> SLAVE_DISABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Write proxy for field `stop_det`"] + pub struct STOP_DET_W<'a> { + w: &'a mut W, + } + impl<'a> STOP_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Write proxy for field `tx_empty`"] + pub struct TX_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - Master Mode"] + #[inline(always)] + pub fn master_mode(&self) -> MASTER_MODE_R { + MASTER_MODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 3 - Slave address width"] + #[inline(always)] + pub fn addr_slave_width(&self) -> ADDR_SLAVE_WIDTH_R { + ADDR_SLAVE_WIDTH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - Enable Restart"] + #[inline(always)] + pub fn restart_en(&self) -> RESTART_EN_R { + RESTART_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Disable Slave"] + #[inline(always)] + pub fn slave_disable(&self) -> SLAVE_DISABLE_R { + SLAVE_DISABLE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - STOP_DET_IFADDRESSED"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - TX_EMPTY_CTRL"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Master Mode"] + #[inline(always)] + pub fn master_mode(&mut self) -> MASTER_MODE_W { + MASTER_MODE_W { w: self } + } + #[doc = "Bits 1:2 - Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 3 - Slave address width"] + #[inline(always)] + pub fn addr_slave_width(&mut self) -> ADDR_SLAVE_WIDTH_W { + ADDR_SLAVE_WIDTH_W { w: self } + } + #[doc = "Bit 5 - Enable Restart"] + #[inline(always)] + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W { w: self } + } + #[doc = "Bit 6 - Disable Slave"] + #[inline(always)] + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W { w: self } + } + #[doc = "Bit 7 - STOP_DET_IFADDRESSED"] + #[inline(always)] + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W { w: self } + } + #[doc = "Bit 8 - TX_EMPTY_CTRL"] + #[inline(always)] + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W { w: self } + } + } + } + #[doc = "Target Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tar](tar) module"] + pub type TAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAR; + #[doc = "`read()` method returns [tar::R](tar::R) reader structure"] + impl crate::Readable for TAR {} + #[doc = "`write(|w| ..)` method takes [tar::W](tar::W) writer structure"] + impl crate::Writable for TAR {} + #[doc = "Target Address Register"] + pub mod tar { + #[doc = "Reader of register tar"] + pub type R = crate::R; + #[doc = "Writer for register tar"] + pub type W = crate::W; + #[doc = "Register tar `reset()`'s with value 0"] + impl crate::ResetValue for super::TAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `address`"] + pub type ADDRESS_R = crate::R; + #[doc = "Write proxy for field `address`"] + pub struct ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff); + self.w + } + } + #[doc = "Reader of field `gc`"] + pub type GC_R = crate::R; + #[doc = "Write proxy for field `gc`"] + pub struct GC_W<'a> { + w: &'a mut W, + } + impl<'a> GC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `special`"] + pub type SPECIAL_R = crate::R; + #[doc = "Write proxy for field `special`"] + pub struct SPECIAL_W<'a> { + w: &'a mut W, + } + impl<'a> SPECIAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Master Address\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ADDR_MASTER_WIDTH_A { + #[doc = "0: 7-bit address"] + B7 = 0, + #[doc = "1: 10-bit address"] + B10 = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ADDR_MASTER_WIDTH_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `addr_master_width`"] + pub type ADDR_MASTER_WIDTH_R = crate::R; + impl ADDR_MASTER_WIDTH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ADDR_MASTER_WIDTH_A { + match self.bits { + false => ADDR_MASTER_WIDTH_A::B7, + true => ADDR_MASTER_WIDTH_A::B10, + } + } + #[doc = "Checks if the value of the field is `B7`"] + #[inline(always)] + pub fn is_b7(&self) -> bool { + *self == ADDR_MASTER_WIDTH_A::B7 + } + #[doc = "Checks if the value of the field is `B10`"] + #[inline(always)] + pub fn is_b10(&self) -> bool { + *self == ADDR_MASTER_WIDTH_A::B10 + } + } + #[doc = "Write proxy for field `addr_master_width`"] + pub struct ADDR_MASTER_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR_MASTER_WIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ADDR_MASTER_WIDTH_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "7-bit address"] + #[inline(always)] + pub fn b7(self) -> &'a mut W { + self.variant(ADDR_MASTER_WIDTH_A::B7) + } + #[doc = "10-bit address"] + #[inline(always)] + pub fn b10(self) -> &'a mut W { + self.variant(ADDR_MASTER_WIDTH_A::B10) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + impl R { + #[doc = "Bits 0:9 - Target Address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - GC_OR_START"] + #[inline(always)] + pub fn gc(&self) -> GC_R { + GC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - SPECIAL"] + #[inline(always)] + pub fn special(&self) -> SPECIAL_R { + SPECIAL_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Master Address"] + #[inline(always)] + pub fn addr_master_width(&self) -> ADDR_MASTER_WIDTH_R { + ADDR_MASTER_WIDTH_R::new(((self.bits >> 12) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:9 - Target Address"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W { w: self } + } + #[doc = "Bit 10 - GC_OR_START"] + #[inline(always)] + pub fn gc(&mut self) -> GC_W { + GC_W { w: self } + } + #[doc = "Bit 11 - SPECIAL"] + #[inline(always)] + pub fn special(&mut self) -> SPECIAL_W { + SPECIAL_W { w: self } + } + #[doc = "Bit 12 - Master Address"] + #[inline(always)] + pub fn addr_master_width(&mut self) -> ADDR_MASTER_WIDTH_W { + ADDR_MASTER_WIDTH_W { w: self } + } + } + } + #[doc = "Slave Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sar](sar) module"] + pub type SAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SAR; + #[doc = "`read()` method returns [sar::R](sar::R) reader structure"] + impl crate::Readable for SAR {} + #[doc = "`write(|w| ..)` method takes [sar::W](sar::W) writer structure"] + impl crate::Writable for SAR {} + #[doc = "Slave Address Register"] + pub mod sar { + #[doc = "Reader of register sar"] + pub type R = crate::R; + #[doc = "Writer for register sar"] + pub type W = crate::W; + #[doc = "Register sar `reset()`'s with value 0"] + impl crate::ResetValue for super::SAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `address`"] + pub type ADDRESS_R = crate::R; + #[doc = "Write proxy for field `address`"] + pub struct ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff); + self.w + } + } + impl R { + #[doc = "Bits 0:9 - Slave Address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x03ff) as u16) + } + } + impl W { + #[doc = "Bits 0:9 - Slave Address"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W { w: self } + } + } + } + #[doc = "Data Buffer and Command Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_cmd](data_cmd) module"] + pub type DATA_CMD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_CMD; + #[doc = "`read()` method returns [data_cmd::R](data_cmd::R) reader structure"] + impl crate::Readable for DATA_CMD {} + #[doc = "`write(|w| ..)` method takes [data_cmd::W](data_cmd::W) writer structure"] + impl crate::Writable for DATA_CMD {} + #[doc = "Data Buffer and Command Register"] + pub mod data_cmd { + #[doc = "Reader of register data_cmd"] + pub type R = crate::R; + #[doc = "Writer for register data_cmd"] + pub type W = crate::W; + #[doc = "Register data_cmd `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_CMD { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cmd`"] + pub type CMD_R = crate::R; + #[doc = "Write proxy for field `cmd`"] + pub struct CMD_W<'a> { + w: &'a mut W, + } + impl<'a> CMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `data`"] + pub type DATA_R = crate::R; + #[doc = "Write proxy for field `data`"] + pub struct DATA_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bit 8 - CMD"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bit 8 - CMD"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + } + } + #[doc = "Standard Speed Clock SCL High Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ss_scl_hcnt](ss_scl_hcnt) module"] + pub type SS_SCL_HCNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SS_SCL_HCNT; + #[doc = "`read()` method returns [ss_scl_hcnt::R](ss_scl_hcnt::R) reader structure"] + impl crate::Readable for SS_SCL_HCNT {} + #[doc = "`write(|w| ..)` method takes [ss_scl_hcnt::W](ss_scl_hcnt::W) writer structure"] + impl crate::Writable for SS_SCL_HCNT {} + #[doc = "Standard Speed Clock SCL High Count Register"] + pub mod ss_scl_hcnt { + #[doc = "Reader of register ss_scl_hcnt"] + pub type R = crate::R; + #[doc = "Writer for register ss_scl_hcnt"] + pub type W = crate::W; + #[doc = "Register ss_scl_hcnt `reset()`'s with value 0"] + impl crate::ResetValue for super::SS_SCL_HCNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "Standard Speed Clock SCL Low Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ss_scl_lcnt](ss_scl_lcnt) module"] + pub type SS_SCL_LCNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SS_SCL_LCNT; + #[doc = "`read()` method returns [ss_scl_lcnt::R](ss_scl_lcnt::R) reader structure"] + impl crate::Readable for SS_SCL_LCNT {} + #[doc = "`write(|w| ..)` method takes [ss_scl_lcnt::W](ss_scl_lcnt::W) writer structure"] + impl crate::Writable for SS_SCL_LCNT {} + #[doc = "Standard Speed Clock SCL Low Count Register"] + pub mod ss_scl_lcnt { + #[doc = "Reader of register ss_scl_lcnt"] + pub type R = crate::R; + #[doc = "Writer for register ss_scl_lcnt"] + pub type W = crate::W; + #[doc = "Register ss_scl_lcnt `reset()`'s with value 0"] + impl crate::ResetValue for super::SS_SCL_LCNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - COUNT"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_stat](intr_stat) module"] + pub type INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_STAT; + #[doc = "`read()` method returns [intr_stat::R](intr_stat::R) reader structure"] + impl crate::Readable for INTR_STAT {} + #[doc = "Interrupt Status Register"] + pub mod intr_stat { + #[doc = "Reader of register intr_stat"] + pub type R = crate::R; + #[doc = "Reader of field `rx_under`"] + pub type RX_UNDER_R = crate::R; + #[doc = "Reader of field `rx_over`"] + pub type RX_OVER_R = crate::R; + #[doc = "Reader of field `rx_full`"] + pub type RX_FULL_R = crate::R; + #[doc = "Reader of field `tx_over`"] + pub type TX_OVER_R = crate::R; + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Reader of field `rd_req`"] + pub type RD_REQ_R = crate::R; + #[doc = "Reader of field `tx_abrt`"] + pub type TX_ABRT_R = crate::R; + #[doc = "Reader of field `rx_done`"] + pub type RX_DONE_R = crate::R; + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Reader of field `start_det`"] + pub type START_DET_R = crate::R; + #[doc = "Reader of field `gen_call`"] + pub type GEN_CALL_R = crate::R; + impl R { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + } + #[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_mask](intr_mask) module"] + pub type INTR_MASK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_MASK; + #[doc = "`read()` method returns [intr_mask::R](intr_mask::R) reader structure"] + impl crate::Readable for INTR_MASK {} + #[doc = "`write(|w| ..)` method takes [intr_mask::W](intr_mask::W) writer structure"] + impl crate::Writable for INTR_MASK {} + #[doc = "Interrupt Mask Register"] + pub mod intr_mask { + #[doc = "Reader of register intr_mask"] + pub type R = crate::R; + #[doc = "Writer for register intr_mask"] + pub type W = crate::W; + #[doc = "Register intr_mask `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_MASK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rx_under`"] + pub type RX_UNDER_R = crate::R; + #[doc = "Write proxy for field `rx_under`"] + pub struct RX_UNDER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_UNDER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rx_over`"] + pub type RX_OVER_R = crate::R; + #[doc = "Write proxy for field `rx_over`"] + pub struct RX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `rx_full`"] + pub type RX_FULL_R = crate::R; + #[doc = "Write proxy for field `rx_full`"] + pub struct RX_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> RX_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `tx_over`"] + pub type TX_OVER_R = crate::R; + #[doc = "Write proxy for field `tx_over`"] + pub struct TX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> TX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Write proxy for field `tx_empty`"] + pub struct TX_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `rd_req`"] + pub type RD_REQ_R = crate::R; + #[doc = "Write proxy for field `rd_req`"] + pub struct RD_REQ_W<'a> { + w: &'a mut W, + } + impl<'a> RD_REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `tx_abrt`"] + pub type TX_ABRT_R = crate::R; + #[doc = "Write proxy for field `tx_abrt`"] + pub struct TX_ABRT_W<'a> { + w: &'a mut W, + } + impl<'a> TX_ABRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `rx_done`"] + pub type RX_DONE_R = crate::R; + #[doc = "Write proxy for field `rx_done`"] + pub struct RX_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> RX_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Write proxy for field `activity`"] + pub struct ACTIVITY_W<'a> { + w: &'a mut W, + } + impl<'a> ACTIVITY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Write proxy for field `stop_det`"] + pub struct STOP_DET_W<'a> { + w: &'a mut W, + } + impl<'a> STOP_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `start_det`"] + pub type START_DET_R = crate::R; + #[doc = "Write proxy for field `start_det`"] + pub struct START_DET_W<'a> { + w: &'a mut W, + } + impl<'a> START_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `gen_call`"] + pub type GEN_CALL_R = crate::R; + #[doc = "Write proxy for field `gen_call`"] + pub struct GEN_CALL_W<'a> { + w: &'a mut W, + } + impl<'a> GEN_CALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + impl R { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W { w: self } + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W { w: self } + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W { w: self } + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W { w: self } + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W { w: self } + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W { w: self } + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W { w: self } + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W { w: self } + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W { w: self } + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W { w: self } + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W { w: self } + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W { w: self } + } + } + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [raw_intr_stat](raw_intr_stat) module"] + pub type RAW_INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RAW_INTR_STAT; + #[doc = "`read()` method returns [raw_intr_stat::R](raw_intr_stat::R) reader structure"] + impl crate::Readable for RAW_INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [raw_intr_stat::W](raw_intr_stat::W) writer structure"] + impl crate::Writable for RAW_INTR_STAT {} + #[doc = "Raw Interrupt Status Register"] + pub mod raw_intr_stat { + #[doc = "Reader of register raw_intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register raw_intr_stat"] + pub type W = crate::W; + #[doc = "Register raw_intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::RAW_INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rx_under`"] + pub type RX_UNDER_R = crate::R; + #[doc = "Write proxy for field `rx_under`"] + pub struct RX_UNDER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_UNDER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rx_over`"] + pub type RX_OVER_R = crate::R; + #[doc = "Write proxy for field `rx_over`"] + pub struct RX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> RX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `rx_full`"] + pub type RX_FULL_R = crate::R; + #[doc = "Write proxy for field `rx_full`"] + pub struct RX_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> RX_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `tx_over`"] + pub type TX_OVER_R = crate::R; + #[doc = "Write proxy for field `tx_over`"] + pub struct TX_OVER_W<'a> { + w: &'a mut W, + } + impl<'a> TX_OVER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `tx_empty`"] + pub type TX_EMPTY_R = crate::R; + #[doc = "Write proxy for field `tx_empty`"] + pub struct TX_EMPTY_W<'a> { + w: &'a mut W, + } + impl<'a> TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `rd_req`"] + pub type RD_REQ_R = crate::R; + #[doc = "Write proxy for field `rd_req`"] + pub struct RD_REQ_W<'a> { + w: &'a mut W, + } + impl<'a> RD_REQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `tx_abrt`"] + pub type TX_ABRT_R = crate::R; + #[doc = "Write proxy for field `tx_abrt`"] + pub struct TX_ABRT_W<'a> { + w: &'a mut W, + } + impl<'a> TX_ABRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `rx_done`"] + pub type RX_DONE_R = crate::R; + #[doc = "Write proxy for field `rx_done`"] + pub struct RX_DONE_W<'a> { + w: &'a mut W, + } + impl<'a> RX_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Write proxy for field `activity`"] + pub struct ACTIVITY_W<'a> { + w: &'a mut W, + } + impl<'a> ACTIVITY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `stop_det`"] + pub type STOP_DET_R = crate::R; + #[doc = "Write proxy for field `stop_det`"] + pub struct STOP_DET_W<'a> { + w: &'a mut W, + } + impl<'a> STOP_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `start_det`"] + pub type START_DET_R = crate::R; + #[doc = "Write proxy for field `start_det`"] + pub struct START_DET_W<'a> { + w: &'a mut W, + } + impl<'a> START_DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `gen_call`"] + pub type GEN_CALL_R = crate::R; + #[doc = "Write proxy for field `gen_call`"] + pub struct GEN_CALL_W<'a> { + w: &'a mut W, + } + impl<'a> GEN_CALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + impl R { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RX_UNDER"] + #[inline(always)] + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W { w: self } + } + #[doc = "Bit 1 - RX_OVER"] + #[inline(always)] + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W { w: self } + } + #[doc = "Bit 2 - RX_FULL"] + #[inline(always)] + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W { w: self } + } + #[doc = "Bit 3 - TX_OVER"] + #[inline(always)] + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W { w: self } + } + #[doc = "Bit 4 - TX_EMPTY"] + #[inline(always)] + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W { w: self } + } + #[doc = "Bit 5 - RD_REQ"] + #[inline(always)] + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W { w: self } + } + #[doc = "Bit 6 - TX_ABRT"] + #[inline(always)] + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W { w: self } + } + #[doc = "Bit 7 - RX_DONE"] + #[inline(always)] + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W { w: self } + } + #[doc = "Bit 8 - ACTIVITY"] + #[inline(always)] + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W { w: self } + } + #[doc = "Bit 9 - STOP_DET"] + #[inline(always)] + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W { w: self } + } + #[doc = "Bit 10 - START_DET"] + #[inline(always)] + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W { w: self } + } + #[doc = "Bit 11 - GEN_CALL"] + #[inline(always)] + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W { w: self } + } + } + } + #[doc = "Receive FIFO Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_tl](rx_tl) module"] + pub type RX_TL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RX_TL; + #[doc = "`read()` method returns [rx_tl::R](rx_tl::R) reader structure"] + impl crate::Readable for RX_TL {} + #[doc = "`write(|w| ..)` method takes [rx_tl::W](rx_tl::W) writer structure"] + impl crate::Writable for RX_TL {} + #[doc = "Receive FIFO Threshold Register"] + pub mod rx_tl { + #[doc = "Reader of register rx_tl"] + pub type R = crate::R; + #[doc = "Writer for register rx_tl"] + pub type W = crate::W; + #[doc = "Register rx_tl `reset()`'s with value 0"] + impl crate::ResetValue for super::RX_TL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Transmit FIFO Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_tl](tx_tl) module"] + pub type TX_TL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TX_TL; + #[doc = "`read()` method returns [tx_tl::R](tx_tl::R) reader structure"] + impl crate::Readable for TX_TL {} + #[doc = "`write(|w| ..)` method takes [tx_tl::W](tx_tl::W) writer structure"] + impl crate::Writable for TX_TL {} + #[doc = "Transmit FIFO Threshold Register"] + pub mod tx_tl { + #[doc = "Reader of register tx_tl"] + pub type R = crate::R; + #[doc = "Writer for register tx_tl"] + pub type W = crate::W; + #[doc = "Register tx_tl `reset()`'s with value 0"] + impl crate::ResetValue for super::TX_TL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Clear Combined and Individual Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_intr](clr_intr) module"] + pub type CLR_INTR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_INTR; + #[doc = "`read()` method returns [clr_intr::R](clr_intr::R) reader structure"] + impl crate::Readable for CLR_INTR {} + #[doc = "Clear Combined and Individual Interrupt Register"] + pub mod clr_intr { + #[doc = "Reader of register clr_intr"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RX_UNDER Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rx_under](clr_rx_under) module"] + pub type CLR_RX_UNDER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RX_UNDER; + #[doc = "`read()` method returns [clr_rx_under::R](clr_rx_under::R) reader structure"] + impl crate::Readable for CLR_RX_UNDER {} + #[doc = "Clear RX_UNDER Interrupt Register"] + pub mod clr_rx_under { + #[doc = "Reader of register clr_rx_under"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RX_OVER Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rx_over](clr_rx_over) module"] + pub type CLR_RX_OVER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RX_OVER; + #[doc = "`read()` method returns [clr_rx_over::R](clr_rx_over::R) reader structure"] + impl crate::Readable for CLR_RX_OVER {} + #[doc = "Clear RX_OVER Interrupt Register"] + pub mod clr_rx_over { + #[doc = "Reader of register clr_rx_over"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear TX_OVER Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_tx_over](clr_tx_over) module"] + pub type CLR_TX_OVER = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_TX_OVER; + #[doc = "`read()` method returns [clr_tx_over::R](clr_tx_over::R) reader structure"] + impl crate::Readable for CLR_TX_OVER {} + #[doc = "Clear TX_OVER Interrupt Register"] + pub mod clr_tx_over { + #[doc = "Reader of register clr_tx_over"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RD_REQ Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rd_req](clr_rd_req) module"] + pub type CLR_RD_REQ = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RD_REQ; + #[doc = "`read()` method returns [clr_rd_req::R](clr_rd_req::R) reader structure"] + impl crate::Readable for CLR_RD_REQ {} + #[doc = "Clear RD_REQ Interrupt Register"] + pub mod clr_rd_req { + #[doc = "Reader of register clr_rd_req"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear TX_ABRT Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_tx_abrt](clr_tx_abrt) module"] + pub type CLR_TX_ABRT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_TX_ABRT; + #[doc = "`read()` method returns [clr_tx_abrt::R](clr_tx_abrt::R) reader structure"] + impl crate::Readable for CLR_TX_ABRT {} + #[doc = "Clear TX_ABRT Interrupt Register"] + pub mod clr_tx_abrt { + #[doc = "Reader of register clr_tx_abrt"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear RX_DONE Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_rx_done](clr_rx_done) module"] + pub type CLR_RX_DONE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_RX_DONE; + #[doc = "`read()` method returns [clr_rx_done::R](clr_rx_done::R) reader structure"] + impl crate::Readable for CLR_RX_DONE {} + #[doc = "Clear RX_DONE Interrupt Register"] + pub mod clr_rx_done { + #[doc = "Reader of register clr_rx_done"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear ACTIVITY Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_activity](clr_activity) module"] + pub type CLR_ACTIVITY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_ACTIVITY; + #[doc = "`read()` method returns [clr_activity::R](clr_activity::R) reader structure"] + impl crate::Readable for CLR_ACTIVITY {} + #[doc = "Clear ACTIVITY Interrupt Register"] + pub mod clr_activity { + #[doc = "Reader of register clr_activity"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear STOP_DET Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_stop_det](clr_stop_det) module"] + pub type CLR_STOP_DET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_STOP_DET; + #[doc = "`read()` method returns [clr_stop_det::R](clr_stop_det::R) reader structure"] + impl crate::Readable for CLR_STOP_DET {} + #[doc = "Clear STOP_DET Interrupt Register"] + pub mod clr_stop_det { + #[doc = "Reader of register clr_stop_det"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Clear START_DET Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_start_det](clr_start_det) module"] + pub type CLR_START_DET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_START_DET; + #[doc = "`read()` method returns [clr_start_det::R](clr_start_det::R) reader structure"] + impl crate::Readable for CLR_START_DET {} + #[doc = "Clear START_DET Interrupt Register"] + pub mod clr_start_det { + #[doc = "Reader of register clr_start_det"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "I2C Clear GEN_CALL Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clr_gen_call](clr_gen_call) module"] + pub type CLR_GEN_CALL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLR_GEN_CALL; + #[doc = "`read()` method returns [clr_gen_call::R](clr_gen_call::R) reader structure"] + impl crate::Readable for CLR_GEN_CALL {} + #[doc = "I2C Clear GEN_CALL Interrupt Register"] + pub mod clr_gen_call { + #[doc = "Reader of register clr_gen_call"] + pub type R = crate::R; + #[doc = "Reader of field `clr`"] + pub type CLR_R = crate::R; + impl R { + #[doc = "Bit 0 - CLR"] + #[inline(always)] + pub fn clr(&self) -> CLR_R { + CLR_R::new((self.bits & 0x01) != 0) + } + } + } + #[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](enable) module"] + pub type ENABLE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENABLE; + #[doc = "`read()` method returns [enable::R](enable::R) reader structure"] + impl crate::Readable for ENABLE {} + #[doc = "`write(|w| ..)` method takes [enable::W](enable::W) writer structure"] + impl crate::Writable for ENABLE {} + #[doc = "Enable Register"] + pub mod enable { + #[doc = "Reader of register enable"] + pub type R = crate::R; + #[doc = "Writer for register enable"] + pub type W = crate::W; + #[doc = "Register enable `reset()`'s with value 0"] + impl crate::ResetValue for super::ENABLE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `abort`"] + pub type ABORT_R = crate::R; + #[doc = "Write proxy for field `abort`"] + pub struct ABORT_W<'a> { + w: &'a mut W, + } + impl<'a> ABORT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `tx_cmd_block`"] + pub type TX_CMD_BLOCK_R = crate::R; + #[doc = "Write proxy for field `tx_cmd_block`"] + pub struct TX_CMD_BLOCK_W<'a> { + w: &'a mut W, + } + impl<'a> TX_CMD_BLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ABORT"] + #[inline(always)] + pub fn abort(&self) -> ABORT_R { + ABORT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TX_CMD_BLOCK"] + #[inline(always)] + pub fn tx_cmd_block(&self) -> TX_CMD_BLOCK_R { + TX_CMD_BLOCK_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - ABORT"] + #[inline(always)] + pub fn abort(&mut self) -> ABORT_W { + ABORT_W { w: self } + } + #[doc = "Bit 2 - TX_CMD_BLOCK"] + #[inline(always)] + pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W { + TX_CMD_BLOCK_W { w: self } + } + } + } + #[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"] + pub type STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STATUS; + #[doc = "`read()` method returns [status::R](status::R) reader structure"] + impl crate::Readable for STATUS {} + #[doc = "Status Register"] + pub mod status { + #[doc = "Reader of register status"] + pub type R = crate::R; + #[doc = "Reader of field `activity`"] + pub type ACTIVITY_R = crate::R; + #[doc = "Reader of field `tfnf`"] + pub type TFNF_R = crate::R; + #[doc = "Reader of field `tfe`"] + pub type TFE_R = crate::R; + #[doc = "Reader of field `rfne`"] + pub type RFNE_R = crate::R; + #[doc = "Reader of field `rff`"] + pub type RFF_R = crate::R; + #[doc = "Reader of field `mst_activity`"] + pub type MST_ACTIVITY_R = crate::R; + #[doc = "Reader of field `slv_activity`"] + pub type SLV_ACTIVITY_R = crate::R; + impl R { + #[doc = "Bit 0 - ACTIVITY"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - TFNF"] + #[inline(always)] + pub fn tfnf(&self) -> TFNF_R { + TFNF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TFE"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RFNE"] + #[inline(always)] + pub fn rfne(&self) -> RFNE_R { + RFNE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RFF"] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MST_ACTIVITY"] + #[inline(always)] + pub fn mst_activity(&self) -> MST_ACTIVITY_R { + MST_ACTIVITY_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SLV_ACTIVITY"] + #[inline(always)] + pub fn slv_activity(&self) -> SLV_ACTIVITY_R { + SLV_ACTIVITY_R::new(((self.bits >> 6) & 0x01) != 0) + } + } + } + #[doc = "Transmit FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](txflr) module"] + pub type TXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TXFLR; + #[doc = "`read()` method returns [txflr::R](txflr::R) reader structure"] + impl crate::Readable for TXFLR {} + #[doc = "`write(|w| ..)` method takes [txflr::W](txflr::W) writer structure"] + impl crate::Writable for TXFLR {} + #[doc = "Transmit FIFO Level Register"] + pub mod txflr { + #[doc = "Reader of register txflr"] + pub type R = crate::R; + #[doc = "Writer for register txflr"] + pub type W = crate::W; + #[doc = "Register txflr `reset()`'s with value 0"] + impl crate::ResetValue for super::TXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Receive FIFO Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](rxflr) module"] + pub type RXFLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RXFLR; + #[doc = "`read()` method returns [rxflr::R](rxflr::R) reader structure"] + impl crate::Readable for RXFLR {} + #[doc = "`write(|w| ..)` method takes [rxflr::W](rxflr::W) writer structure"] + impl crate::Writable for RXFLR {} + #[doc = "Receive FIFO Level Register"] + pub mod rxflr { + #[doc = "Reader of register rxflr"] + pub type R = crate::R; + #[doc = "Writer for register rxflr"] + pub type W = crate::W; + #[doc = "Register rxflr `reset()`'s with value 0"] + impl crate::ResetValue for super::RXFLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "SDA Hold Time Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda_hold](sda_hold) module"] + pub type SDA_HOLD = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SDA_HOLD; + #[doc = "`read()` method returns [sda_hold::R](sda_hold::R) reader structure"] + impl crate::Readable for SDA_HOLD {} + #[doc = "`write(|w| ..)` method takes [sda_hold::W](sda_hold::W) writer structure"] + impl crate::Writable for SDA_HOLD {} + #[doc = "SDA Hold Time Length Register"] + pub mod sda_hold { + #[doc = "Reader of register sda_hold"] + pub type R = crate::R; + #[doc = "Writer for register sda_hold"] + pub type W = crate::W; + #[doc = "Register sda_hold `reset()`'s with value 0"] + impl crate::ResetValue for super::SDA_HOLD { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tx`"] + pub type TX_R = crate::R; + #[doc = "Write proxy for field `tx`"] + pub struct TX_W<'a> { + w: &'a mut W, + } + impl<'a> TX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `rx`"] + pub type RX_R = crate::R; + #[doc = "Write proxy for field `rx`"] + pub struct RX_W<'a> { + w: &'a mut W, + } + impl<'a> RX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - TX"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - RX"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 16) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:15 - TX"] + #[inline(always)] + pub fn tx(&mut self) -> TX_W { + TX_W { w: self } + } + #[doc = "Bits 16:23 - RX"] + #[inline(always)] + pub fn rx(&mut self) -> RX_W { + RX_W { w: self } + } + } + } + #[doc = "Transmit Abort Source Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_abrt_source](tx_abrt_source) module"] + pub type TX_ABRT_SOURCE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TX_ABRT_SOURCE; + #[doc = "`read()` method returns [tx_abrt_source::R](tx_abrt_source::R) reader structure"] + impl crate::Readable for TX_ABRT_SOURCE {} + #[doc = "`write(|w| ..)` method takes [tx_abrt_source::W](tx_abrt_source::W) writer structure"] + impl crate::Writable for TX_ABRT_SOURCE {} + #[doc = "Transmit Abort Source Register"] + pub mod tx_abrt_source { + #[doc = "Reader of register tx_abrt_source"] + pub type R = crate::R; + #[doc = "Writer for register tx_abrt_source"] + pub type W = crate::W; + #[doc = "Register tx_abrt_source `reset()`'s with value 0"] + impl crate::ResetValue for super::TX_ABRT_SOURCE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `addr7_noack`"] + pub type ADDR7_NOACK_R = crate::R; + #[doc = "Write proxy for field `addr7_noack`"] + pub struct ADDR7_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR7_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `addr1_10_noack`"] + pub type ADDR1_10_NOACK_R = crate::R; + #[doc = "Write proxy for field `addr1_10_noack`"] + pub struct ADDR1_10_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR1_10_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `addr2_10_noack`"] + pub type ADDR2_10_NOACK_R = crate::R; + #[doc = "Write proxy for field `addr2_10_noack`"] + pub struct ADDR2_10_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> ADDR2_10_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `txdata_noack`"] + pub type TXDATA_NOACK_R = crate::R; + #[doc = "Write proxy for field `txdata_noack`"] + pub struct TXDATA_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> TXDATA_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `gcall_noack`"] + pub type GCALL_NOACK_R = crate::R; + #[doc = "Write proxy for field `gcall_noack`"] + pub struct GCALL_NOACK_W<'a> { + w: &'a mut W, + } + impl<'a> GCALL_NOACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `gcall_read`"] + pub type GCALL_READ_R = crate::R; + #[doc = "Write proxy for field `gcall_read`"] + pub struct GCALL_READ_W<'a> { + w: &'a mut W, + } + impl<'a> GCALL_READ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `hs_ackdet`"] + pub type HS_ACKDET_R = crate::R; + #[doc = "Write proxy for field `hs_ackdet`"] + pub struct HS_ACKDET_W<'a> { + w: &'a mut W, + } + impl<'a> HS_ACKDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `sbyte_ackdet`"] + pub type SBYTE_ACKDET_R = crate::R; + #[doc = "Write proxy for field `sbyte_ackdet`"] + pub struct SBYTE_ACKDET_W<'a> { + w: &'a mut W, + } + impl<'a> SBYTE_ACKDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `hs_norstrt`"] + pub type HS_NORSTRT_R = crate::R; + #[doc = "Write proxy for field `hs_norstrt`"] + pub struct HS_NORSTRT_W<'a> { + w: &'a mut W, + } + impl<'a> HS_NORSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `sbyte_norstrt`"] + pub type SBYTE_NORSTRT_R = crate::R; + #[doc = "Write proxy for field `sbyte_norstrt`"] + pub struct SBYTE_NORSTRT_W<'a> { + w: &'a mut W, + } + impl<'a> SBYTE_NORSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `rd_10_norstrt`"] + pub type RD_10_NORSTRT_R = crate::R; + #[doc = "Write proxy for field `rd_10_norstrt`"] + pub struct RD_10_NORSTRT_W<'a> { + w: &'a mut W, + } + impl<'a> RD_10_NORSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `master_dis`"] + pub type MASTER_DIS_R = crate::R; + #[doc = "Write proxy for field `master_dis`"] + pub struct MASTER_DIS_W<'a> { + w: &'a mut W, + } + impl<'a> MASTER_DIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `mst_arblost`"] + pub type MST_ARBLOST_R = crate::R; + #[doc = "Write proxy for field `mst_arblost`"] + pub struct MST_ARBLOST_W<'a> { + w: &'a mut W, + } + impl<'a> MST_ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `slvflush_txfifo`"] + pub type SLVFLUSH_TXFIFO_R = crate::R; + #[doc = "Write proxy for field `slvflush_txfifo`"] + pub struct SLVFLUSH_TXFIFO_W<'a> { + w: &'a mut W, + } + impl<'a> SLVFLUSH_TXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `slv_arblost`"] + pub type SLV_ARBLOST_R = crate::R; + #[doc = "Write proxy for field `slv_arblost`"] + pub struct SLV_ARBLOST_W<'a> { + w: &'a mut W, + } + impl<'a> SLV_ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `slvrd_intx`"] + pub type SLVRD_INTX_R = crate::R; + #[doc = "Write proxy for field `slvrd_intx`"] + pub struct SLVRD_INTX_W<'a> { + w: &'a mut W, + } + impl<'a> SLVRD_INTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `user_abrt`"] + pub type USER_ABRT_R = crate::R; + #[doc = "Write proxy for field `user_abrt`"] + pub struct USER_ABRT_W<'a> { + w: &'a mut W, + } + impl<'a> USER_ABRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - 7B_ADDR_NOACK"] + #[inline(always)] + pub fn addr7_noack(&self) -> ADDR7_NOACK_R { + ADDR7_NOACK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - 10B_ADDR1_NOACK"] + #[inline(always)] + pub fn addr1_10_noack(&self) -> ADDR1_10_NOACK_R { + ADDR1_10_NOACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 10B_ADDR2_NOACK"] + #[inline(always)] + pub fn addr2_10_noack(&self) -> ADDR2_10_NOACK_R { + ADDR2_10_NOACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TXDATA_NOACK"] + #[inline(always)] + pub fn txdata_noack(&self) -> TXDATA_NOACK_R { + TXDATA_NOACK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - GCALL_NOACK"] + #[inline(always)] + pub fn gcall_noack(&self) -> GCALL_NOACK_R { + GCALL_NOACK_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - GCALL_READ"] + #[inline(always)] + pub fn gcall_read(&self) -> GCALL_READ_R { + GCALL_READ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HS_ACKDET"] + #[inline(always)] + pub fn hs_ackdet(&self) -> HS_ACKDET_R { + HS_ACKDET_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - SBYTE_ACKDET"] + #[inline(always)] + pub fn sbyte_ackdet(&self) -> SBYTE_ACKDET_R { + SBYTE_ACKDET_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - HS_NORSTRT"] + #[inline(always)] + pub fn hs_norstrt(&self) -> HS_NORSTRT_R { + HS_NORSTRT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - SBYTE_NORSTRT"] + #[inline(always)] + pub fn sbyte_norstrt(&self) -> SBYTE_NORSTRT_R { + SBYTE_NORSTRT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - 10B_RD_NORSTRT"] + #[inline(always)] + pub fn rd_10_norstrt(&self) -> RD_10_NORSTRT_R { + RD_10_NORSTRT_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - MASTER_DIS"] + #[inline(always)] + pub fn master_dis(&self) -> MASTER_DIS_R { + MASTER_DIS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - MST_ARBLOST"] + #[inline(always)] + pub fn mst_arblost(&self) -> MST_ARBLOST_R { + MST_ARBLOST_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - SLVFLUSH_TXFIFO"] + #[inline(always)] + pub fn slvflush_txfifo(&self) -> SLVFLUSH_TXFIFO_R { + SLVFLUSH_TXFIFO_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - SLV_ARBLOST"] + #[inline(always)] + pub fn slv_arblost(&self) -> SLV_ARBLOST_R { + SLV_ARBLOST_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - SLVRD_INTX"] + #[inline(always)] + pub fn slvrd_intx(&self) -> SLVRD_INTX_R { + SLVRD_INTX_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - USER_ABRT"] + #[inline(always)] + pub fn user_abrt(&self) -> USER_ABRT_R { + USER_ABRT_R::new(((self.bits >> 16) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - 7B_ADDR_NOACK"] + #[inline(always)] + pub fn addr7_noack(&mut self) -> ADDR7_NOACK_W { + ADDR7_NOACK_W { w: self } + } + #[doc = "Bit 1 - 10B_ADDR1_NOACK"] + #[inline(always)] + pub fn addr1_10_noack(&mut self) -> ADDR1_10_NOACK_W { + ADDR1_10_NOACK_W { w: self } + } + #[doc = "Bit 2 - 10B_ADDR2_NOACK"] + #[inline(always)] + pub fn addr2_10_noack(&mut self) -> ADDR2_10_NOACK_W { + ADDR2_10_NOACK_W { w: self } + } + #[doc = "Bit 3 - TXDATA_NOACK"] + #[inline(always)] + pub fn txdata_noack(&mut self) -> TXDATA_NOACK_W { + TXDATA_NOACK_W { w: self } + } + #[doc = "Bit 4 - GCALL_NOACK"] + #[inline(always)] + pub fn gcall_noack(&mut self) -> GCALL_NOACK_W { + GCALL_NOACK_W { w: self } + } + #[doc = "Bit 5 - GCALL_READ"] + #[inline(always)] + pub fn gcall_read(&mut self) -> GCALL_READ_W { + GCALL_READ_W { w: self } + } + #[doc = "Bit 6 - HS_ACKDET"] + #[inline(always)] + pub fn hs_ackdet(&mut self) -> HS_ACKDET_W { + HS_ACKDET_W { w: self } + } + #[doc = "Bit 7 - SBYTE_ACKDET"] + #[inline(always)] + pub fn sbyte_ackdet(&mut self) -> SBYTE_ACKDET_W { + SBYTE_ACKDET_W { w: self } + } + #[doc = "Bit 8 - HS_NORSTRT"] + #[inline(always)] + pub fn hs_norstrt(&mut self) -> HS_NORSTRT_W { + HS_NORSTRT_W { w: self } + } + #[doc = "Bit 9 - SBYTE_NORSTRT"] + #[inline(always)] + pub fn sbyte_norstrt(&mut self) -> SBYTE_NORSTRT_W { + SBYTE_NORSTRT_W { w: self } + } + #[doc = "Bit 10 - 10B_RD_NORSTRT"] + #[inline(always)] + pub fn rd_10_norstrt(&mut self) -> RD_10_NORSTRT_W { + RD_10_NORSTRT_W { w: self } + } + #[doc = "Bit 11 - MASTER_DIS"] + #[inline(always)] + pub fn master_dis(&mut self) -> MASTER_DIS_W { + MASTER_DIS_W { w: self } + } + #[doc = "Bit 12 - MST_ARBLOST"] + #[inline(always)] + pub fn mst_arblost(&mut self) -> MST_ARBLOST_W { + MST_ARBLOST_W { w: self } + } + #[doc = "Bit 13 - SLVFLUSH_TXFIFO"] + #[inline(always)] + pub fn slvflush_txfifo(&mut self) -> SLVFLUSH_TXFIFO_W { + SLVFLUSH_TXFIFO_W { w: self } + } + #[doc = "Bit 14 - SLV_ARBLOST"] + #[inline(always)] + pub fn slv_arblost(&mut self) -> SLV_ARBLOST_W { + SLV_ARBLOST_W { w: self } + } + #[doc = "Bit 15 - SLVRD_INTX"] + #[inline(always)] + pub fn slvrd_intx(&mut self) -> SLVRD_INTX_W { + SLVRD_INTX_W { w: self } + } + #[doc = "Bit 16 - USER_ABRT"] + #[inline(always)] + pub fn user_abrt(&mut self) -> USER_ABRT_W { + USER_ABRT_W { w: self } + } + } + } + #[doc = "I2C DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_cr](dma_cr) module"] + pub type DMA_CR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_CR; + #[doc = "`read()` method returns [dma_cr::R](dma_cr::R) reader structure"] + impl crate::Readable for DMA_CR {} + #[doc = "`write(|w| ..)` method takes [dma_cr::W](dma_cr::W) writer structure"] + impl crate::Writable for DMA_CR {} + #[doc = "I2C DMA Control Register"] + pub mod dma_cr { + #[doc = "Reader of register dma_cr"] + pub type R = crate::R; + #[doc = "Writer for register dma_cr"] + pub type W = crate::W; + #[doc = "Register dma_cr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_CR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `RDMAE`"] + pub type RDMAE_R = crate::R; + #[doc = "Write proxy for field `RDMAE`"] + pub struct RDMAE_W<'a> { + w: &'a mut W, + } + impl<'a> RDMAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `TDMAE`"] + pub type TDMAE_R = crate::R; + #[doc = "Write proxy for field `TDMAE`"] + pub struct TDMAE_W<'a> { + w: &'a mut W, + } + impl<'a> TDMAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0 - RDMAE"] + #[inline(always)] + pub fn rdmae(&self) -> RDMAE_R { + RDMAE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - TDMAE"] + #[inline(always)] + pub fn tdmae(&self) -> TDMAE_R { + TDMAE_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RDMAE"] + #[inline(always)] + pub fn rdmae(&mut self) -> RDMAE_W { + RDMAE_W { w: self } + } + #[doc = "Bit 1 - TDMAE"] + #[inline(always)] + pub fn tdmae(&mut self) -> TDMAE_W { + TDMAE_W { w: self } + } + } + } + #[doc = "DMA Transmit Data Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_tdlr](dma_tdlr) module"] + pub type DMA_TDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_TDLR; + #[doc = "`read()` method returns [dma_tdlr::R](dma_tdlr::R) reader structure"] + impl crate::Readable for DMA_TDLR {} + #[doc = "`write(|w| ..)` method takes [dma_tdlr::W](dma_tdlr::W) writer structure"] + impl crate::Writable for DMA_TDLR {} + #[doc = "DMA Transmit Data Level Register"] + pub mod dma_tdlr { + #[doc = "Reader of register dma_tdlr"] + pub type R = crate::R; + #[doc = "Writer for register dma_tdlr"] + pub type W = crate::W; + #[doc = "Register dma_tdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_TDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "DMA Receive Data Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_rdlr](dma_rdlr) module"] + pub type DMA_RDLR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_RDLR; + #[doc = "`read()` method returns [dma_rdlr::R](dma_rdlr::R) reader structure"] + impl crate::Readable for DMA_RDLR {} + #[doc = "`write(|w| ..)` method takes [dma_rdlr::W](dma_rdlr::W) writer structure"] + impl crate::Writable for DMA_RDLR {} + #[doc = "DMA Receive Data Level Register"] + pub mod dma_rdlr { + #[doc = "Reader of register dma_rdlr"] + pub type R = crate::R; + #[doc = "Writer for register dma_rdlr"] + pub type W = crate::W; + #[doc = "Register dma_rdlr `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_RDLR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "SDA Setup Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda_setup](sda_setup) module"] + pub type SDA_SETUP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SDA_SETUP; + #[doc = "`read()` method returns [sda_setup::R](sda_setup::R) reader structure"] + impl crate::Readable for SDA_SETUP {} + #[doc = "`write(|w| ..)` method takes [sda_setup::W](sda_setup::W) writer structure"] + impl crate::Writable for SDA_SETUP {} + #[doc = "SDA Setup Register"] + pub mod sda_setup { + #[doc = "Reader of register sda_setup"] + pub type R = crate::R; + #[doc = "Writer for register sda_setup"] + pub type W = crate::W; + #[doc = "Register sda_setup `reset()`'s with value 0"] + impl crate::ResetValue for super::SDA_SETUP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "ACK General Call Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [general_call](general_call) module"] + pub type GENERAL_CALL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GENERAL_CALL; + #[doc = "`read()` method returns [general_call::R](general_call::R) reader structure"] + impl crate::Readable for GENERAL_CALL {} + #[doc = "`write(|w| ..)` method takes [general_call::W](general_call::W) writer structure"] + impl crate::Writable for GENERAL_CALL {} + #[doc = "ACK General Call Register"] + pub mod general_call { + #[doc = "Reader of register general_call"] + pub type R = crate::R; + #[doc = "Writer for register general_call"] + pub type W = crate::W; + #[doc = "Register general_call `reset()`'s with value 0"] + impl crate::ResetValue for super::GENERAL_CALL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `call_enable`"] + pub type CALL_ENABLE_R = crate::R; + #[doc = "Write proxy for field `call_enable`"] + pub struct CALL_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> CALL_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - CALL_ENABLE"] + #[inline(always)] + pub fn call_enable(&self) -> CALL_ENABLE_R { + CALL_ENABLE_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - CALL_ENABLE"] + #[inline(always)] + pub fn call_enable(&mut self) -> CALL_ENABLE_W { + CALL_ENABLE_W { w: self } + } + } + } + #[doc = "Enable Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_status](enable_status) module"] + pub type ENABLE_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENABLE_STATUS; + #[doc = "`read()` method returns [enable_status::R](enable_status::R) reader structure"] + impl crate::Readable for ENABLE_STATUS {} + #[doc = "Enable Status Register"] + pub mod enable_status { + #[doc = "Reader of register enable_status"] + pub type R = crate::R; + #[doc = "Reader of field `ic_enable`"] + pub type IC_ENABLE_R = crate::R; + #[doc = "Reader of field `slv_dis_busy`"] + pub type SLV_DIS_BUSY_R = crate::R; + #[doc = "Reader of field `slv_rx_data_lost`"] + pub type SLV_RX_DATA_LOST_R = crate::R; + impl R { + #[doc = "Bit 0 - IC_ENABLE"] + #[inline(always)] + pub fn ic_enable(&self) -> IC_ENABLE_R { + IC_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SLV_DIS_BUSY"] + #[inline(always)] + pub fn slv_dis_busy(&self) -> SLV_DIS_BUSY_R { + SLV_DIS_BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SLV_RX_DATA_LOST"] + #[inline(always)] + pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R { + SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 0x01) != 0) + } + } + } + #[doc = "SS, FS or FM+ spike suppression limit\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fs_spklen](fs_spklen) module"] + pub type FS_SPKLEN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FS_SPKLEN; + #[doc = "`read()` method returns [fs_spklen::R](fs_spklen::R) reader structure"] + impl crate::Readable for FS_SPKLEN {} + #[doc = "`write(|w| ..)` method takes [fs_spklen::W](fs_spklen::W) writer structure"] + impl crate::Writable for FS_SPKLEN {} + #[doc = "SS, FS or FM+ spike suppression limit"] + pub mod fs_spklen { + #[doc = "Reader of register fs_spklen"] + pub type R = crate::R; + #[doc = "Writer for register fs_spklen"] + pub type W = crate::W; + #[doc = "Register fs_spklen `reset()`'s with value 0"] + impl crate::ResetValue for super::FS_SPKLEN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + #[doc = "Write proxy for field `value`"] + pub struct VALUE_W<'a> { + w: &'a mut W, + } + impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - VALUE"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + } + } + #[doc = "Component Parameter Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_1](comp_param_1) module"] + pub type COMP_PARAM_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_1; + #[doc = "`read()` method returns [comp_param_1::R](comp_param_1::R) reader structure"] + impl crate::Readable for COMP_PARAM_1 {} + #[doc = "Component Parameter Register 1"] + pub mod comp_param_1 { + #[doc = "Reader of register comp_param_1"] + pub type R = crate::R; + #[doc = "Reader of field `apb_data_width`"] + pub type APB_DATA_WIDTH_R = crate::R; + #[doc = "Reader of field `max_speed_mode`"] + pub type MAX_SPEED_MODE_R = crate::R; + #[doc = "Reader of field `hc_count_values`"] + pub type HC_COUNT_VALUES_R = crate::R; + #[doc = "Reader of field `intr_io`"] + pub type INTR_IO_R = crate::R; + #[doc = "Reader of field `has_dma`"] + pub type HAS_DMA_R = crate::R; + #[doc = "Reader of field `encoded_params`"] + pub type ENCODED_PARAMS_R = crate::R; + #[doc = "Reader of field `rx_buffer_depth`"] + pub type RX_BUFFER_DEPTH_R = crate::R; + #[doc = "Reader of field `tx_buffer_depth`"] + pub type TX_BUFFER_DEPTH_R = crate::R; + impl R { + #[doc = "Bits 0:1 - APB_DATA_WIDTH"] + #[inline(always)] + pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R { + APB_DATA_WIDTH_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - MAX_SPEED_MODE"] + #[inline(always)] + pub fn max_speed_mode(&self) -> MAX_SPEED_MODE_R { + MAX_SPEED_MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - HC_COUNT_VALUES"] + #[inline(always)] + pub fn hc_count_values(&self) -> HC_COUNT_VALUES_R { + HC_COUNT_VALUES_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - INTR_IO"] + #[inline(always)] + pub fn intr_io(&self) -> INTR_IO_R { + INTR_IO_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HAS_DMA"] + #[inline(always)] + pub fn has_dma(&self) -> HAS_DMA_R { + HAS_DMA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - ENCODED_PARAMS"] + #[inline(always)] + pub fn encoded_params(&self) -> ENCODED_PARAMS_R { + ENCODED_PARAMS_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:15 - RX_BUFFER_DEPTH"] + #[inline(always)] + pub fn rx_buffer_depth(&self) -> RX_BUFFER_DEPTH_R { + RX_BUFFER_DEPTH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - TX_BUFFER_DEPTH"] + #[inline(always)] + pub fn tx_buffer_depth(&self) -> TX_BUFFER_DEPTH_R { + TX_BUFFER_DEPTH_R::new(((self.bits >> 16) & 0xff) as u8) + } + } + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_version](comp_version) module"] + pub type COMP_VERSION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_VERSION; + #[doc = "`read()` method returns [comp_version::R](comp_version::R) reader structure"] + impl crate::Readable for COMP_VERSION {} + #[doc = "Component Version Register"] + pub mod comp_version { + #[doc = "Reader of register comp_version"] + pub type R = crate::R; + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + impl R { + #[doc = "Bits 0:31 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xffff_ffff) as u32) + } + } + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_type](comp_type) module"] + pub type COMP_TYPE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_TYPE; + #[doc = "`read()` method returns [comp_type::R](comp_type::R) reader structure"] + impl crate::Readable for COMP_TYPE {} + #[doc = "Component Type Register"] + pub mod comp_type { + #[doc = "Reader of register comp_type"] + pub type R = crate::R; + #[doc = "Reader of field `value`"] + pub type VALUE_R = crate::R; + impl R { + #[doc = "Bits 0:31 - VALUE"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xffff_ffff) as u32) + } + } + } +} +#[doc = "Inter-Integrated Circuit Bus 1"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + 0x5029_0000 as *const _ + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2C1::ptr() } + } +} +#[doc = "Inter-Integrated Circuit Bus 2"] +pub struct I2C2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C2 {} +impl I2C2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + 0x502a_0000 as *const _ + } +} +impl Deref for I2C2 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*I2C2::ptr() } + } +} +#[doc = "Field Programmable IO Array"] +pub struct FPIOA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FPIOA {} +impl FPIOA { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fpioa::RegisterBlock { + 0x502b_0000 as *const _ + } +} +impl Deref for FPIOA { + type Target = fpioa::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*FPIOA::ptr() } + } +} +#[doc = "Field Programmable IO Array"] +pub mod fpioa { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - FPIOA GPIO multiplexer io array"] + pub io: [IO; 48], + #[doc = "0xc0 - FPIOA GPIO multiplexer tie enable array"] + pub tie_en: [TIE_EN; 8], + #[doc = "0xe0 - FPIOA GPIO multiplexer tie value array"] + pub tie_val: [TIE_VAL; 8], + } + #[doc = "FPIOA GPIO multiplexer io array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](io) module"] + pub type IO = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IO; + #[doc = "`read()` method returns [io::R](io::R) reader structure"] + impl crate::Readable for IO {} + #[doc = "`write(|w| ..)` method takes [io::W](io::W) writer structure"] + impl crate::Writable for IO {} + #[doc = "FPIOA GPIO multiplexer io array"] + pub mod io { + #[doc = "Reader of register io[%s]"] + pub type R = crate::R; + #[doc = "Writer for register io[%s]"] + pub type W = crate::W; + #[doc = "Register io[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::IO { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `ch_sel`"] + pub type CH_SEL_R = crate::R; + #[doc = "Write proxy for field `ch_sel`"] + pub struct CH_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> CH_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `ds`"] + pub type DS_R = crate::R; + #[doc = "Write proxy for field `ds`"] + pub struct DS_W<'a> { + w: &'a mut W, + } + impl<'a> DS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); + self.w + } + } + #[doc = "Reader of field `oe_en`"] + pub type OE_EN_R = crate::R; + #[doc = "Write proxy for field `oe_en`"] + pub struct OE_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `oe_inv`"] + pub type OE_INV_R = crate::R; + #[doc = "Write proxy for field `oe_inv`"] + pub struct OE_INV_W<'a> { + w: &'a mut W, + } + impl<'a> OE_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `do_sel`"] + pub type DO_SEL_R = crate::R; + #[doc = "Write proxy for field `do_sel`"] + pub struct DO_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> DO_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `do_inv`"] + pub type DO_INV_R = crate::R; + #[doc = "Write proxy for field `do_inv`"] + pub struct DO_INV_W<'a> { + w: &'a mut W, + } + impl<'a> DO_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `pu`"] + pub type PU_R = crate::R; + #[doc = "Write proxy for field `pu`"] + pub struct PU_W<'a> { + w: &'a mut W, + } + impl<'a> PU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `pd`"] + pub type PD_R = crate::R; + #[doc = "Write proxy for field `pd`"] + pub struct PD_W<'a> { + w: &'a mut W, + } + impl<'a> PD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `sl`"] + pub type SL_R = crate::R; + #[doc = "Write proxy for field `sl`"] + pub struct SL_W<'a> { + w: &'a mut W, + } + impl<'a> SL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `ie_en`"] + pub type IE_EN_R = crate::R; + #[doc = "Write proxy for field `ie_en`"] + pub struct IE_EN_W<'a> { + w: &'a mut W, + } + impl<'a> IE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `ie_inv`"] + pub type IE_INV_R = crate::R; + #[doc = "Write proxy for field `ie_inv`"] + pub struct IE_INV_W<'a> { + w: &'a mut W, + } + impl<'a> IE_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `di_inv`"] + pub type DI_INV_R = crate::R; + #[doc = "Write proxy for field `di_inv`"] + pub struct DI_INV_W<'a> { + w: &'a mut W, + } + impl<'a> DI_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `st`"] + pub type ST_R = crate::R; + #[doc = "Write proxy for field `st`"] + pub struct ST_W<'a> { + w: &'a mut W, + } + impl<'a> ST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `pad_di`"] + pub type PAD_DI_R = crate::R; + #[doc = "Write proxy for field `pad_di`"] + pub struct PAD_DI_W<'a> { + w: &'a mut W, + } + impl<'a> PAD_DI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - Channel select from 256 input"] + #[inline(always)] + pub fn ch_sel(&self) -> CH_SEL_R { + CH_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Driving selector"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Static output enable, will AND with OE_INV"] + #[inline(always)] + pub fn oe_en(&self) -> OE_EN_R { + OE_EN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Invert output enable"] + #[inline(always)] + pub fn oe_inv(&self) -> OE_INV_R { + OE_INV_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Data output select: 0 for DO, 1 for OE"] + #[inline(always)] + pub fn do_sel(&self) -> DO_SEL_R { + DO_SEL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Invert the result of data output select (DO_SEL)"] + #[inline(always)] + pub fn do_inv(&self) -> DO_INV_R { + DO_INV_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Pull up enable. 0 for nothing, 1 for pull up"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Pull down enable. 0 for nothing, 1 for pull down"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 19 - Slew rate control enable"] + #[inline(always)] + pub fn sl(&self) -> SL_R { + SL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Static input enable, will AND with IE_INV"] + #[inline(always)] + pub fn ie_en(&self) -> IE_EN_R { + IE_EN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Invert input enable"] + #[inline(always)] + pub fn ie_inv(&self) -> IE_INV_R { + IE_INV_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Invert Data input"] + #[inline(always)] + pub fn di_inv(&self) -> DI_INV_R { + DI_INV_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Schmitt trigger"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 31 - Read current IO's data input"] + #[inline(always)] + pub fn pad_di(&self) -> PAD_DI_R { + PAD_DI_R::new(((self.bits >> 31) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - Channel select from 256 input"] + #[inline(always)] + pub fn ch_sel(&mut self) -> CH_SEL_W { + CH_SEL_W { w: self } + } + #[doc = "Bits 8:11 - Driving selector"] + #[inline(always)] + pub fn ds(&mut self) -> DS_W { + DS_W { w: self } + } + #[doc = "Bit 12 - Static output enable, will AND with OE_INV"] + #[inline(always)] + pub fn oe_en(&mut self) -> OE_EN_W { + OE_EN_W { w: self } + } + #[doc = "Bit 13 - Invert output enable"] + #[inline(always)] + pub fn oe_inv(&mut self) -> OE_INV_W { + OE_INV_W { w: self } + } + #[doc = "Bit 14 - Data output select: 0 for DO, 1 for OE"] + #[inline(always)] + pub fn do_sel(&mut self) -> DO_SEL_W { + DO_SEL_W { w: self } + } + #[doc = "Bit 15 - Invert the result of data output select (DO_SEL)"] + #[inline(always)] + pub fn do_inv(&mut self) -> DO_INV_W { + DO_INV_W { w: self } + } + #[doc = "Bit 16 - Pull up enable. 0 for nothing, 1 for pull up"] + #[inline(always)] + pub fn pu(&mut self) -> PU_W { + PU_W { w: self } + } + #[doc = "Bit 17 - Pull down enable. 0 for nothing, 1 for pull down"] + #[inline(always)] + pub fn pd(&mut self) -> PD_W { + PD_W { w: self } + } + #[doc = "Bit 19 - Slew rate control enable"] + #[inline(always)] + pub fn sl(&mut self) -> SL_W { + SL_W { w: self } + } + #[doc = "Bit 20 - Static input enable, will AND with IE_INV"] + #[inline(always)] + pub fn ie_en(&mut self) -> IE_EN_W { + IE_EN_W { w: self } + } + #[doc = "Bit 21 - Invert input enable"] + #[inline(always)] + pub fn ie_inv(&mut self) -> IE_INV_W { + IE_INV_W { w: self } + } + #[doc = "Bit 22 - Invert Data input"] + #[inline(always)] + pub fn di_inv(&mut self) -> DI_INV_W { + DI_INV_W { w: self } + } + #[doc = "Bit 23 - Schmitt trigger"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Bit 31 - Read current IO's data input"] + #[inline(always)] + pub fn pad_di(&mut self) -> PAD_DI_W { + PAD_DI_W { w: self } + } + } + } + #[doc = "FPIOA GPIO multiplexer tie enable array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tie_en](tie_en) module"] + pub type TIE_EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TIE_EN; + #[doc = "`read()` method returns [tie_en::R](tie_en::R) reader structure"] + impl crate::Readable for TIE_EN {} + #[doc = "`write(|w| ..)` method takes [tie_en::W](tie_en::W) writer structure"] + impl crate::Writable for TIE_EN {} + #[doc = "FPIOA GPIO multiplexer tie enable array"] + pub mod tie_en { + #[doc = "Reader of register tie_en[%s]"] + pub type R = crate::R; + #[doc = "Writer for register tie_en[%s]"] + pub type W = crate::W; + #[doc = "Register tie_en[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::TIE_EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "FPIOA GPIO multiplexer tie value array\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tie_val](tie_val) module"] + pub type TIE_VAL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TIE_VAL; + #[doc = "`read()` method returns [tie_val::R](tie_val::R) reader structure"] + impl crate::Readable for TIE_VAL {} + #[doc = "`write(|w| ..)` method takes [tie_val::W](tie_val::W) writer structure"] + impl crate::Writable for TIE_VAL {} + #[doc = "FPIOA GPIO multiplexer tie value array"] + pub mod tie_val { + #[doc = "Reader of register tie_val[%s]"] + pub type R = crate::R; + #[doc = "Writer for register tie_val[%s]"] + pub type W = crate::W; + #[doc = "Register tie_val[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::TIE_VAL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "SHA256 Accelerator"] +pub struct SHA256 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SHA256 {} +impl SHA256 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sha256::RegisterBlock { + 0x502c_0000 as *const _ + } +} +impl Deref for SHA256 { + type Target = sha256::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SHA256::ptr() } + } +} +#[doc = "SHA256 Accelerator"] +pub mod sha256 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Calculated SHA256 return value"] + pub result: [RESULT; 8], + #[doc = "0x20 - SHA256 input data is written to this register"] + pub data_in: DATA_IN, + _reserved2: [u8; 4usize], + #[doc = "0x28 - Counters register"] + pub num_reg: NUM_REG, + #[doc = "0x2c - Function configuration register 0"] + pub function_reg_0: FUNCTION_REG_0, + _reserved4: [u8; 4usize], + #[doc = "0x34 - Function configuration register 1"] + pub function_reg_1: FUNCTION_REG_1, + } + #[doc = "Calculated SHA256 return value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](result) module"] + pub type RESULT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RESULT; + #[doc = "`read()` method returns [result::R](result::R) reader structure"] + impl crate::Readable for RESULT {} + #[doc = "`write(|w| ..)` method takes [result::W](result::W) writer structure"] + impl crate::Writable for RESULT {} + #[doc = "Calculated SHA256 return value"] + pub mod result { + #[doc = "Reader of register result[%s]"] + pub type R = crate::R; + #[doc = "Writer for register result[%s]"] + pub type W = crate::W; + #[doc = "Register result[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::RESULT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "SHA256 input data is written to this register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_in](data_in) module"] + pub type DATA_IN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_IN; + #[doc = "`read()` method returns [data_in::R](data_in::R) reader structure"] + impl crate::Readable for DATA_IN {} + #[doc = "`write(|w| ..)` method takes [data_in::W](data_in::W) writer structure"] + impl crate::Writable for DATA_IN {} + #[doc = "SHA256 input data is written to this register"] + pub mod data_in { + #[doc = "Reader of register data_in"] + pub type R = crate::R; + #[doc = "Writer for register data_in"] + pub type W = crate::W; + #[doc = "Register data_in `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_IN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Counters register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [num_reg](num_reg) module"] + pub type NUM_REG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _NUM_REG; + #[doc = "`read()` method returns [num_reg::R](num_reg::R) reader structure"] + impl crate::Readable for NUM_REG {} + #[doc = "`write(|w| ..)` method takes [num_reg::W](num_reg::W) writer structure"] + impl crate::Writable for NUM_REG {} + #[doc = "Counters register"] + pub mod num_reg { + #[doc = "Reader of register num_reg"] + pub type R = crate::R; + #[doc = "Writer for register num_reg"] + pub type W = crate::W; + #[doc = "Register num_reg `reset()`'s with value 0"] + impl crate::ResetValue for super::NUM_REG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `data_cnt`"] + pub type DATA_CNT_R = crate::R; + #[doc = "Write proxy for field `data_cnt`"] + pub struct DATA_CNT_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_CNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `data_num`"] + pub type DATA_NUM_R = crate::R; + #[doc = "Write proxy for field `data_num`"] + pub struct DATA_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_NUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15 - The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit"] + #[inline(always)] + pub fn data_cnt(&self) -> DATA_CNT_R { + DATA_CNT_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Currently calculated block number. 512bit=1block"] + #[inline(always)] + pub fn data_num(&self) -> DATA_NUM_R { + DATA_NUM_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15 - The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit"] + #[inline(always)] + pub fn data_cnt(&mut self) -> DATA_CNT_W { + DATA_CNT_W { w: self } + } + #[doc = "Bits 16:31 - Currently calculated block number. 512bit=1block"] + #[inline(always)] + pub fn data_num(&mut self) -> DATA_NUM_W { + DATA_NUM_W { w: self } + } + } + } + #[doc = "Function configuration register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [function_reg_0](function_reg_0) module"] + pub type FUNCTION_REG_0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FUNCTION_REG_0; + #[doc = "`read()` method returns [function_reg_0::R](function_reg_0::R) reader structure"] + impl crate::Readable for FUNCTION_REG_0 {} + #[doc = "`write(|w| ..)` method takes [function_reg_0::W](function_reg_0::W) writer structure"] + impl crate::Writable for FUNCTION_REG_0 {} + #[doc = "Function configuration register 0"] + pub mod function_reg_0 { + #[doc = "Reader of register function_reg_0"] + pub type R = crate::R; + #[doc = "Writer for register function_reg_0"] + pub type W = crate::W; + #[doc = "Register function_reg_0 `reset()`'s with value 0"] + impl crate::ResetValue for super::FUNCTION_REG_0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `en`"] + pub type EN_R = crate::R; + #[doc = "Write proxy for field `en`"] + pub struct EN_W<'a> { + w: &'a mut W, + } + impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `overflow`"] + pub type OVERFLOW_R = crate::R; + #[doc = "Write proxy for field `overflow`"] + pub struct OVERFLOW_W<'a> { + w: &'a mut W, + } + impl<'a> OVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Endian setting\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ENDIAN_A { + #[doc = "0: Little endian"] + LE = 0, + #[doc = "1: Big endian"] + BE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ENDIAN_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `endian`"] + pub type ENDIAN_R = crate::R; + impl ENDIAN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIAN_A { + match self.bits { + false => ENDIAN_A::LE, + true => ENDIAN_A::BE, + } + } + #[doc = "Checks if the value of the field is `LE`"] + #[inline(always)] + pub fn is_le(&self) -> bool { + *self == ENDIAN_A::LE + } + #[doc = "Checks if the value of the field is `BE`"] + #[inline(always)] + pub fn is_be(&self) -> bool { + *self == ENDIAN_A::BE + } + } + #[doc = "Write proxy for field `endian`"] + pub struct ENDIAN_W<'a> { + w: &'a mut W, + } + impl<'a> ENDIAN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIAN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Little endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(ENDIAN_A::LE) + } + #[doc = "Big endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(ENDIAN_A::BE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + impl R { + #[doc = "Bit 0 - write:SHA256 enable register. read:Calculation completed flag"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 8 - SHA256 calculation overflow flag"] + #[inline(always)] + pub fn overflow(&self) -> OVERFLOW_R { + OVERFLOW_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 16 - Endian setting"] + #[inline(always)] + pub fn endian(&self) -> ENDIAN_R { + ENDIAN_R::new(((self.bits >> 16) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - write:SHA256 enable register. read:Calculation completed flag"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Bit 8 - SHA256 calculation overflow flag"] + #[inline(always)] + pub fn overflow(&mut self) -> OVERFLOW_W { + OVERFLOW_W { w: self } + } + #[doc = "Bit 16 - Endian setting"] + #[inline(always)] + pub fn endian(&mut self) -> ENDIAN_W { + ENDIAN_W { w: self } + } + } + } + #[doc = "Function configuration register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [function_reg_1](function_reg_1) module"] + pub type FUNCTION_REG_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FUNCTION_REG_1; + #[doc = "`read()` method returns [function_reg_1::R](function_reg_1::R) reader structure"] + impl crate::Readable for FUNCTION_REG_1 {} + #[doc = "`write(|w| ..)` method takes [function_reg_1::W](function_reg_1::W) writer structure"] + impl crate::Writable for FUNCTION_REG_1 {} + #[doc = "Function configuration register 1"] + pub mod function_reg_1 { + #[doc = "Reader of register function_reg_1"] + pub type R = crate::R; + #[doc = "Writer for register function_reg_1"] + pub type W = crate::W; + #[doc = "Register function_reg_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::FUNCTION_REG_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dma_en`"] + pub type DMA_EN_R = crate::R; + #[doc = "Write proxy for field `dma_en`"] + pub struct DMA_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `fifo_in_full`"] + pub type FIFO_IN_FULL_R = crate::R; + #[doc = "Write proxy for field `fifo_in_full`"] + pub struct FIFO_IN_FULL_W<'a> { + w: &'a mut W, + } + impl<'a> FIFO_IN_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + impl R { + #[doc = "Bit 0 - SHA and DMA handshake signals enable. 1:enable; 0:disable"] + #[inline(always)] + pub fn dma_en(&self) -> DMA_EN_R { + DMA_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 8 - 1:SHA256 input fifo is full; 0:not full"] + #[inline(always)] + pub fn fifo_in_full(&self) -> FIFO_IN_FULL_R { + FIFO_IN_FULL_R::new(((self.bits >> 8) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - SHA and DMA handshake signals enable. 1:enable; 0:disable"] + #[inline(always)] + pub fn dma_en(&mut self) -> DMA_EN_W { + DMA_EN_W { w: self } + } + #[doc = "Bit 8 - 1:SHA256 input fifo is full; 0:not full"] + #[inline(always)] + pub fn fifo_in_full(&mut self) -> FIFO_IN_FULL_W { + FIFO_IN_FULL_W { w: self } + } + } + } +} +#[doc = "Timer 0"] +pub struct TIMER0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0 {} +impl TIMER0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + 0x502d_0000 as *const _ + } +} +impl Deref for TIMER0 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*TIMER0::ptr() } + } +} +#[doc = "Timer 0"] +pub mod timer0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Channel cluster: load_count, current_value, control, eoi and intr_stat registers"] + pub channel: [CHANNEL; 4], + _reserved1: [u8; 80usize], + #[doc = "0xa0 - Interrupt Status Register"] + pub intr_stat: INTR_STAT, + #[doc = "0xa4 - Interrupt Clear Register"] + pub eoi: EOI, + #[doc = "0xa8 - Raw Interrupt Status Register"] + pub raw_intr_stat: RAW_INTR_STAT, + #[doc = "0xac - Component Version Register"] + pub comp_version: COMP_VERSION, + #[doc = "0xb0 - Load Count2 Register"] + pub load_count2: [LOAD_COUNT2; 4], + } + #[doc = r"Register block"] + #[repr(C)] + pub struct CHANNEL { + #[doc = "0x00 - Load Count Register"] + pub load_count: self::channel::LOAD_COUNT, + #[doc = "0x04 - Current Value Register"] + pub current_value: self::channel::CURRENT_VALUE, + #[doc = "0x08 - Control Register"] + pub control: self::channel::CONTROL, + #[doc = "0x0c - Interrupt Clear Register"] + pub eoi: self::channel::EOI, + #[doc = "0x10 - Interrupt Status Register"] + pub intr_stat: self::channel::INTR_STAT, + } + #[doc = r"Register block"] + #[doc = "Channel cluster: load_count, current_value, control, eoi and intr_stat registers"] + pub mod channel { + #[doc = "Load Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [load_count](load_count) module"] + pub type LOAD_COUNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOAD_COUNT; + #[doc = "`read()` method returns [load_count::R](load_count::R) reader structure"] + impl crate::Readable for LOAD_COUNT {} + #[doc = "`write(|w| ..)` method takes [load_count::W](load_count::W) writer structure"] + impl crate::Writable for LOAD_COUNT {} + #[doc = "Load Count Register"] + pub mod load_count { + #[doc = "Reader of register load_count"] + pub type R = crate::R; + #[doc = "Writer for register load_count"] + pub type W = crate::W; + #[doc = "Register load_count `reset()`'s with value 0"] + impl crate::ResetValue for super::LOAD_COUNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [current_value](current_value) module"] + pub type CURRENT_VALUE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CURRENT_VALUE; + #[doc = "`read()` method returns [current_value::R](current_value::R) reader structure"] + impl crate::Readable for CURRENT_VALUE {} + #[doc = "`write(|w| ..)` method takes [current_value::W](current_value::W) writer structure"] + impl crate::Writable for CURRENT_VALUE {} + #[doc = "Current Value Register"] + pub mod current_value { + #[doc = "Reader of register current_value"] + pub type R = crate::R; + #[doc = "Writer for register current_value"] + pub type W = crate::W; + #[doc = "Register current_value `reset()`'s with value 0"] + impl crate::ResetValue for super::CURRENT_VALUE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control](control) module"] + pub type CONTROL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CONTROL; + #[doc = "`read()` method returns [control::R](control::R) reader structure"] + impl crate::Readable for CONTROL {} + #[doc = "`write(|w| ..)` method takes [control::W](control::W) writer structure"] + impl crate::Writable for CONTROL {} + #[doc = "Control Register"] + pub mod control { + #[doc = "Reader of register control"] + pub type R = crate::R; + #[doc = "Writer for register control"] + pub type W = crate::W; + #[doc = "Register control `reset()`'s with value 0"] + impl crate::ResetValue for super::CONTROL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "MODE\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum MODE_A { + #[doc = "0: FREE_MODE"] + FREE = 0, + #[doc = "1: USER_MODE"] + USER = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `mode`"] + pub type MODE_R = crate::R; + impl MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::FREE, + true => MODE_A::USER, + } + } + #[doc = "Checks if the value of the field is `FREE`"] + #[inline(always)] + pub fn is_free(&self) -> bool { + *self == MODE_A::FREE + } + #[doc = "Checks if the value of the field is `USER`"] + #[inline(always)] + pub fn is_user(&self) -> bool { + *self == MODE_A::USER + } + } + #[doc = "Write proxy for field `mode`"] + pub struct MODE_W<'a> { + w: &'a mut W, + } + impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "FREE_MODE"] + #[inline(always)] + pub fn free(self) -> &'a mut W { + self.variant(MODE_A::FREE) + } + #[doc = "USER_MODE"] + #[inline(always)] + pub fn user(self) -> &'a mut W { + self.variant(MODE_A::USER) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `interrupt`"] + pub type INTERRUPT_R = crate::R; + #[doc = "Write proxy for field `interrupt`"] + pub struct INTERRUPT_W<'a> { + w: &'a mut W, + } + impl<'a> INTERRUPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `pwm_enable`"] + pub type PWM_ENABLE_R = crate::R; + #[doc = "Write proxy for field `pwm_enable`"] + pub struct PWM_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> PWM_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + impl R { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - MODE"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INTERRUPT_MASK"] + #[inline(always)] + pub fn interrupt(&self) -> INTERRUPT_R { + INTERRUPT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - PWM_ENABLE"] + #[inline(always)] + pub fn pwm_enable(&self) -> PWM_ENABLE_R { + PWM_ENABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - ENABLE"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - MODE"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 2 - INTERRUPT_MASK"] + #[inline(always)] + pub fn interrupt(&mut self) -> INTERRUPT_W { + INTERRUPT_W { w: self } + } + #[doc = "Bit 3 - PWM_ENABLE"] + #[inline(always)] + pub fn pwm_enable(&mut self) -> PWM_ENABLE_W { + PWM_ENABLE_W { w: self } + } + } + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eoi](eoi) module"] + pub type EOI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EOI; + #[doc = "`read()` method returns [eoi::R](eoi::R) reader structure"] + impl crate::Readable for EOI {} + #[doc = "`write(|w| ..)` method takes [eoi::W](eoi::W) writer structure"] + impl crate::Writable for EOI {} + #[doc = "Interrupt Clear Register"] + pub mod eoi { + #[doc = "Reader of register eoi"] + pub type R = crate::R; + #[doc = "Writer for register eoi"] + pub type W = crate::W; + #[doc = "Register eoi `reset()`'s with value 0"] + impl crate::ResetValue for super::EOI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_stat](intr_stat) module"] + pub type INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_STAT; + #[doc = "`read()` method returns [intr_stat::R](intr_stat::R) reader structure"] + impl crate::Readable for INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [intr_stat::W](intr_stat::W) writer structure"] + impl crate::Writable for INTR_STAT {} + #[doc = "Interrupt Status Register"] + pub mod intr_stat { + #[doc = "Reader of register intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register intr_stat"] + pub type W = crate::W; + #[doc = "Register intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_stat](intr_stat) module"] + pub type INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTR_STAT; + #[doc = "`read()` method returns [intr_stat::R](intr_stat::R) reader structure"] + impl crate::Readable for INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [intr_stat::W](intr_stat::W) writer structure"] + impl crate::Writable for INTR_STAT {} + #[doc = "Interrupt Status Register"] + pub mod intr_stat { + #[doc = "Reader of register intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register intr_stat"] + pub type W = crate::W; + #[doc = "Register intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eoi](eoi) module"] + pub type EOI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EOI; + #[doc = "`read()` method returns [eoi::R](eoi::R) reader structure"] + impl crate::Readable for EOI {} + #[doc = "`write(|w| ..)` method takes [eoi::W](eoi::W) writer structure"] + impl crate::Writable for EOI {} + #[doc = "Interrupt Clear Register"] + pub mod eoi { + #[doc = "Reader of register eoi"] + pub type R = crate::R; + #[doc = "Writer for register eoi"] + pub type W = crate::W; + #[doc = "Register eoi `reset()`'s with value 0"] + impl crate::ResetValue for super::EOI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [raw_intr_stat](raw_intr_stat) module"] + pub type RAW_INTR_STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RAW_INTR_STAT; + #[doc = "`read()` method returns [raw_intr_stat::R](raw_intr_stat::R) reader structure"] + impl crate::Readable for RAW_INTR_STAT {} + #[doc = "`write(|w| ..)` method takes [raw_intr_stat::W](raw_intr_stat::W) writer structure"] + impl crate::Writable for RAW_INTR_STAT {} + #[doc = "Raw Interrupt Status Register"] + pub mod raw_intr_stat { + #[doc = "Reader of register raw_intr_stat"] + pub type R = crate::R; + #[doc = "Writer for register raw_intr_stat"] + pub type W = crate::W; + #[doc = "Register raw_intr_stat `reset()`'s with value 0"] + impl crate::ResetValue for super::RAW_INTR_STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_version](comp_version) module"] + pub type COMP_VERSION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_VERSION; + #[doc = "`read()` method returns [comp_version::R](comp_version::R) reader structure"] + impl crate::Readable for COMP_VERSION {} + #[doc = "`write(|w| ..)` method takes [comp_version::W](comp_version::W) writer structure"] + impl crate::Writable for COMP_VERSION {} + #[doc = "Component Version Register"] + pub mod comp_version { + #[doc = "Reader of register comp_version"] + pub type R = crate::R; + #[doc = "Writer for register comp_version"] + pub type W = crate::W; + #[doc = "Register comp_version `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_VERSION { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Load Count2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [load_count2](load_count2) module"] + pub type LOAD_COUNT2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _LOAD_COUNT2; + #[doc = "`read()` method returns [load_count2::R](load_count2::R) reader structure"] + impl crate::Readable for LOAD_COUNT2 {} + #[doc = "`write(|w| ..)` method takes [load_count2::W](load_count2::W) writer structure"] + impl crate::Writable for LOAD_COUNT2 {} + #[doc = "Load Count2 Register"] + pub mod load_count2 { + #[doc = "Reader of register load_count2%s"] + pub type R = crate::R; + #[doc = "Writer for register load_count2%s"] + pub type W = crate::W; + #[doc = "Register load_count2%s `reset()`'s with value 0"] + impl crate::ResetValue for super::LOAD_COUNT2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Timer 1"] +pub struct TIMER1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1 {} +impl TIMER1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + 0x502e_0000 as *const _ + } +} +impl Deref for TIMER1 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*TIMER1::ptr() } + } +} +#[doc = "Timer 2"] +pub struct TIMER2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER2 {} +impl TIMER2 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + 0x502f_0000 as *const _ + } +} +impl Deref for TIMER2 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*TIMER2::ptr() } + } +} +#[doc = "Watchdog Timer 0"] +pub struct WDT0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT0 {} +impl WDT0 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt0::RegisterBlock { + 0x5040_0000 as *const _ + } +} +impl Deref for WDT0 { + type Target = wdt0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*WDT0::ptr() } + } +} +#[doc = "Watchdog Timer 0"] +pub mod wdt0 { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub cr: CR, + #[doc = "0x04 - Timeout Range Register"] + pub torr: TORR, + #[doc = "0x08 - Current Counter Value Register"] + pub ccvr: CCVR, + #[doc = "0x0c - Counter Restart Register"] + pub crr: CRR, + #[doc = "0x10 - Interrupt Status Register"] + pub stat: STAT, + #[doc = "0x14 - Interrupt Clear Register"] + pub eoi: EOI, + _reserved6: [u8; 4usize], + #[doc = "0x1c - Protection level Register"] + pub prot_level: PROT_LEVEL, + _reserved7: [u8; 196usize], + #[doc = "0xe4 - Component Parameters Register 5"] + pub comp_param_5: COMP_PARAM_5, + #[doc = "0xe8 - Component Parameters Register 4"] + pub comp_param_4: COMP_PARAM_4, + #[doc = "0xec - Component Parameters Register 3"] + pub comp_param_3: COMP_PARAM_3, + #[doc = "0xf0 - Component Parameters Register 2"] + pub comp_param_2: COMP_PARAM_2, + #[doc = "0xf4 - Component Parameters Register 1"] + pub comp_param_1: COMP_PARAM_1, + #[doc = "0xf8 - Component Version Register"] + pub comp_version: COMP_VERSION, + #[doc = "0xfc - Component Type Register"] + pub comp_type: COMP_TYPE, + } + #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](cr) module"] + pub type CR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CR; + #[doc = "`read()` method returns [cr::R](cr::R) reader structure"] + impl crate::Readable for CR {} + #[doc = "`write(|w| ..)` method takes [cr::W](cr::W) writer structure"] + impl crate::Writable for CR {} + #[doc = "Control Register"] + pub mod cr { + #[doc = "Reader of register cr"] + pub type R = crate::R; + #[doc = "Writer for register cr"] + pub type W = crate::W; + #[doc = "Register cr `reset()`'s with value 0"] + impl crate::ResetValue for super::CR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `enable`"] + pub type ENABLE_R = crate::R; + #[doc = "Write proxy for field `enable`"] + pub struct ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "rmod\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum RMOD_A { + #[doc = "0: RESET"] + RESET = 0, + #[doc = "1: INTERRUPT"] + INTERRUPT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: RMOD_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `rmod`"] + pub type RMOD_R = crate::R; + impl RMOD_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RMOD_A { + match self.bits { + false => RMOD_A::RESET, + true => RMOD_A::INTERRUPT, + } + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == RMOD_A::RESET + } + #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == RMOD_A::INTERRUPT + } + } + #[doc = "Write proxy for field `rmod`"] + pub struct RMOD_W<'a> { + w: &'a mut W, + } + impl<'a> RMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RMOD_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "RESET"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(RMOD_A::RESET) + } + #[doc = "INTERRUPT"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut W { + self.variant(RMOD_A::INTERRUPT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `rpl`"] + pub type RPL_R = crate::R; + #[doc = "Write proxy for field `rpl`"] + pub struct RPL_W<'a> { + w: &'a mut W, + } + impl<'a> RPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | (((value as u32) & 0x07) << 2); + self.w + } + } + impl R { + #[doc = "Bit 0 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - rmod"] + #[inline(always)] + pub fn rmod(&self) -> RMOD_R { + RMOD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - rpl"] + #[inline(always)] + pub fn rpl(&self) -> RPL_R { + RPL_R::new(((self.bits >> 2) & 0x07) as u8) + } + } + impl W { + #[doc = "Bit 0 - enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - rmod"] + #[inline(always)] + pub fn rmod(&mut self) -> RMOD_W { + RMOD_W { w: self } + } + #[doc = "Bits 2:4 - rpl"] + #[inline(always)] + pub fn rpl(&mut self) -> RPL_W { + RPL_W { w: self } + } + } + } + #[doc = "Timeout Range Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [torr](torr) module"] + pub type TORR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TORR; + #[doc = "`read()` method returns [torr::R](torr::R) reader structure"] + impl crate::Readable for TORR {} + #[doc = "`write(|w| ..)` method takes [torr::W](torr::W) writer structure"] + impl crate::Writable for TORR {} + #[doc = "Timeout Range Register"] + pub mod torr { + #[doc = "Reader of register torr"] + pub type R = crate::R; + #[doc = "Writer for register torr"] + pub type W = crate::W; + #[doc = "Register torr `reset()`'s with value 0"] + impl crate::ResetValue for super::TORR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `top0`"] + pub type TOP0_R = crate::R; + #[doc = "Write proxy for field `top0`"] + pub struct TOP0_W<'a> { + w: &'a mut W, + } + impl<'a> TOP0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `top1`"] + pub type TOP1_R = crate::R; + #[doc = "Write proxy for field `top1`"] + pub struct TOP1_W<'a> { + w: &'a mut W, + } + impl<'a> TOP1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); + self.w + } + } + impl R { + #[doc = "Bits 0:3 - top (lower half)"] + #[inline(always)] + pub fn top0(&self) -> TOP0_R { + TOP0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - top (upper half)"] + #[inline(always)] + pub fn top1(&self) -> TOP1_R { + TOP1_R::new(((self.bits >> 4) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3 - top (lower half)"] + #[inline(always)] + pub fn top0(&mut self) -> TOP0_W { + TOP0_W { w: self } + } + #[doc = "Bits 4:7 - top (upper half)"] + #[inline(always)] + pub fn top1(&mut self) -> TOP1_W { + TOP1_W { w: self } + } + } + } + #[doc = "Current Counter Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccvr](ccvr) module"] + pub type CCVR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CCVR; + #[doc = "`read()` method returns [ccvr::R](ccvr::R) reader structure"] + impl crate::Readable for CCVR {} + #[doc = "`write(|w| ..)` method takes [ccvr::W](ccvr::W) writer structure"] + impl crate::Writable for CCVR {} + #[doc = "Current Counter Value Register"] + pub mod ccvr { + #[doc = "Reader of register ccvr"] + pub type R = crate::R; + #[doc = "Writer for register ccvr"] + pub type W = crate::W; + #[doc = "Register ccvr `reset()`'s with value 0"] + impl crate::ResetValue for super::CCVR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Counter Restart Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crr](crr) module"] + pub type CRR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CRR; + #[doc = "`read()` method returns [crr::R](crr::R) reader structure"] + impl crate::Readable for CRR {} + #[doc = "`write(|w| ..)` method takes [crr::W](crr::W) writer structure"] + impl crate::Writable for CRR {} + #[doc = "Counter Restart Register"] + pub mod crr { + #[doc = "Reader of register crr"] + pub type R = crate::R; + #[doc = "Writer for register crr"] + pub type W = crate::W; + #[doc = "Register crr `reset()`'s with value 0"] + impl crate::ResetValue for super::CRR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](stat) module"] + pub type STAT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STAT; + #[doc = "`read()` method returns [stat::R](stat::R) reader structure"] + impl crate::Readable for STAT {} + #[doc = "`write(|w| ..)` method takes [stat::W](stat::W) writer structure"] + impl crate::Writable for STAT {} + #[doc = "Interrupt Status Register"] + pub mod stat { + #[doc = "Reader of register stat"] + pub type R = crate::R; + #[doc = "Writer for register stat"] + pub type W = crate::W; + #[doc = "Register stat `reset()`'s with value 0"] + impl crate::ResetValue for super::STAT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `stat`"] + pub type STAT_R = crate::R; + #[doc = "Write proxy for field `stat`"] + pub struct STAT_W<'a> { + w: &'a mut W, + } + impl<'a> STAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - stat"] + #[inline(always)] + pub fn stat(&self) -> STAT_R { + STAT_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - stat"] + #[inline(always)] + pub fn stat(&mut self) -> STAT_W { + STAT_W { w: self } + } + } + } + #[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eoi](eoi) module"] + pub type EOI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EOI; + #[doc = "`read()` method returns [eoi::R](eoi::R) reader structure"] + impl crate::Readable for EOI {} + #[doc = "`write(|w| ..)` method takes [eoi::W](eoi::W) writer structure"] + impl crate::Writable for EOI {} + #[doc = "Interrupt Clear Register"] + pub mod eoi { + #[doc = "Reader of register eoi"] + pub type R = crate::R; + #[doc = "Writer for register eoi"] + pub type W = crate::W; + #[doc = "Register eoi `reset()`'s with value 0"] + impl crate::ResetValue for super::EOI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `eoi`"] + pub type EOI_R = crate::R; + #[doc = "Write proxy for field `eoi`"] + pub struct EOI_W<'a> { + w: &'a mut W, + } + impl<'a> EOI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - eoi"] + #[inline(always)] + pub fn eoi(&self) -> EOI_R { + EOI_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - eoi"] + #[inline(always)] + pub fn eoi(&mut self) -> EOI_W { + EOI_W { w: self } + } + } + } + #[doc = "Protection level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prot_level](prot_level) module"] + pub type PROT_LEVEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PROT_LEVEL; + #[doc = "`read()` method returns [prot_level::R](prot_level::R) reader structure"] + impl crate::Readable for PROT_LEVEL {} + #[doc = "`write(|w| ..)` method takes [prot_level::W](prot_level::W) writer structure"] + impl crate::Writable for PROT_LEVEL {} + #[doc = "Protection level Register"] + pub mod prot_level { + #[doc = "Reader of register prot_level"] + pub type R = crate::R; + #[doc = "Writer for register prot_level"] + pub type W = crate::W; + #[doc = "Register prot_level `reset()`'s with value 0"] + impl crate::ResetValue for super::PROT_LEVEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `prot_level`"] + pub type PROT_LEVEL_R = crate::R; + #[doc = "Write proxy for field `prot_level`"] + pub struct PROT_LEVEL_W<'a> { + w: &'a mut W, + } + impl<'a> PROT_LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - prot_level"] + #[inline(always)] + pub fn prot_level(&self) -> PROT_LEVEL_R { + PROT_LEVEL_R::new((self.bits & 0x07) as u8) + } + } + impl W { + #[doc = "Bits 0:2 - prot_level"] + #[inline(always)] + pub fn prot_level(&mut self) -> PROT_LEVEL_W { + PROT_LEVEL_W { w: self } + } + } + } + #[doc = "Component Parameters Register 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_5](comp_param_5) module"] + pub type COMP_PARAM_5 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_5; + #[doc = "`read()` method returns [comp_param_5::R](comp_param_5::R) reader structure"] + impl crate::Readable for COMP_PARAM_5 {} + #[doc = "`write(|w| ..)` method takes [comp_param_5::W](comp_param_5::W) writer structure"] + impl crate::Writable for COMP_PARAM_5 {} + #[doc = "Component Parameters Register 5"] + pub mod comp_param_5 { + #[doc = "Reader of register comp_param_5"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_5"] + pub type W = crate::W; + #[doc = "Register comp_param_5 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_5 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `user_top_max`"] + pub type USER_TOP_MAX_R = crate::R; + #[doc = "Write proxy for field `user_top_max`"] + pub struct USER_TOP_MAX_W<'a> { + w: &'a mut W, + } + impl<'a> USER_TOP_MAX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - user_top_max"] + #[inline(always)] + pub fn user_top_max(&self) -> USER_TOP_MAX_R { + USER_TOP_MAX_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - user_top_max"] + #[inline(always)] + pub fn user_top_max(&mut self) -> USER_TOP_MAX_W { + USER_TOP_MAX_W { w: self } + } + } + } + #[doc = "Component Parameters Register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_4](comp_param_4) module"] + pub type COMP_PARAM_4 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_4; + #[doc = "`read()` method returns [comp_param_4::R](comp_param_4::R) reader structure"] + impl crate::Readable for COMP_PARAM_4 {} + #[doc = "`write(|w| ..)` method takes [comp_param_4::W](comp_param_4::W) writer structure"] + impl crate::Writable for COMP_PARAM_4 {} + #[doc = "Component Parameters Register 4"] + pub mod comp_param_4 { + #[doc = "Reader of register comp_param_4"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_4"] + pub type W = crate::W; + #[doc = "Register comp_param_4 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_4 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `user_top_init_max`"] + pub type USER_TOP_INIT_MAX_R = crate::R; + #[doc = "Write proxy for field `user_top_init_max`"] + pub struct USER_TOP_INIT_MAX_W<'a> { + w: &'a mut W, + } + impl<'a> USER_TOP_INIT_MAX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - user_top_init_max"] + #[inline(always)] + pub fn user_top_init_max(&self) -> USER_TOP_INIT_MAX_R { + USER_TOP_INIT_MAX_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - user_top_init_max"] + #[inline(always)] + pub fn user_top_init_max(&mut self) -> USER_TOP_INIT_MAX_W { + USER_TOP_INIT_MAX_W { w: self } + } + } + } + #[doc = "Component Parameters Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_3](comp_param_3) module"] + pub type COMP_PARAM_3 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_3; + #[doc = "`read()` method returns [comp_param_3::R](comp_param_3::R) reader structure"] + impl crate::Readable for COMP_PARAM_3 {} + #[doc = "`write(|w| ..)` method takes [comp_param_3::W](comp_param_3::W) writer structure"] + impl crate::Writable for COMP_PARAM_3 {} + #[doc = "Component Parameters Register 3"] + pub mod comp_param_3 { + #[doc = "Reader of register comp_param_3"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_3"] + pub type W = crate::W; + #[doc = "Register comp_param_3 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_3 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `top_rst`"] + pub type TOP_RST_R = crate::R; + #[doc = "Write proxy for field `top_rst`"] + pub struct TOP_RST_W<'a> { + w: &'a mut W, + } + impl<'a> TOP_RST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - top_rst"] + #[inline(always)] + pub fn top_rst(&self) -> TOP_RST_R { + TOP_RST_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - top_rst"] + #[inline(always)] + pub fn top_rst(&mut self) -> TOP_RST_W { + TOP_RST_W { w: self } + } + } + } + #[doc = "Component Parameters Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_2](comp_param_2) module"] + pub type COMP_PARAM_2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_2; + #[doc = "`read()` method returns [comp_param_2::R](comp_param_2::R) reader structure"] + impl crate::Readable for COMP_PARAM_2 {} + #[doc = "`write(|w| ..)` method takes [comp_param_2::W](comp_param_2::W) writer structure"] + impl crate::Writable for COMP_PARAM_2 {} + #[doc = "Component Parameters Register 2"] + pub mod comp_param_2 { + #[doc = "Reader of register comp_param_2"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_2"] + pub type W = crate::W; + #[doc = "Register comp_param_2 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cnt_rst`"] + pub type CNT_RST_R = crate::R; + #[doc = "Write proxy for field `cnt_rst`"] + pub struct CNT_RST_W<'a> { + w: &'a mut W, + } + impl<'a> CNT_RST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - cnt_rst"] + #[inline(always)] + pub fn cnt_rst(&self) -> CNT_RST_R { + CNT_RST_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - cnt_rst"] + #[inline(always)] + pub fn cnt_rst(&mut self) -> CNT_RST_W { + CNT_RST_W { w: self } + } + } + } + #[doc = "Component Parameters Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_param_1](comp_param_1) module"] + pub type COMP_PARAM_1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_PARAM_1; + #[doc = "`read()` method returns [comp_param_1::R](comp_param_1::R) reader structure"] + impl crate::Readable for COMP_PARAM_1 {} + #[doc = "`write(|w| ..)` method takes [comp_param_1::W](comp_param_1::W) writer structure"] + impl crate::Writable for COMP_PARAM_1 {} + #[doc = "Component Parameters Register 1"] + pub mod comp_param_1 { + #[doc = "Reader of register comp_param_1"] + pub type R = crate::R; + #[doc = "Writer for register comp_param_1"] + pub type W = crate::W; + #[doc = "Register comp_param_1 `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_PARAM_1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `always_en`"] + pub type ALWAYS_EN_R = crate::R; + #[doc = "Write proxy for field `always_en`"] + pub struct ALWAYS_EN_W<'a> { + w: &'a mut W, + } + impl<'a> ALWAYS_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `dflt_rmod`"] + pub type DFLT_RMOD_R = crate::R; + #[doc = "Write proxy for field `dflt_rmod`"] + pub struct DFLT_RMOD_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_RMOD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `dual_top`"] + pub type DUAL_TOP_R = crate::R; + #[doc = "Write proxy for field `dual_top`"] + pub struct DUAL_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> DUAL_TOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `hc_rmod`"] + pub type HC_RMOD_R = crate::R; + #[doc = "Write proxy for field `hc_rmod`"] + pub struct HC_RMOD_W<'a> { + w: &'a mut W, + } + impl<'a> HC_RMOD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `hc_rpl`"] + pub type HC_RPL_R = crate::R; + #[doc = "Write proxy for field `hc_rpl`"] + pub struct HC_RPL_W<'a> { + w: &'a mut W, + } + impl<'a> HC_RPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `hc_top`"] + pub type HC_TOP_R = crate::R; + #[doc = "Write proxy for field `hc_top`"] + pub struct HC_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> HC_TOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `use_fix_top`"] + pub type USE_FIX_TOP_R = crate::R; + #[doc = "Write proxy for field `use_fix_top`"] + pub struct USE_FIX_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> USE_FIX_TOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `pause`"] + pub type PAUSE_R = crate::R; + #[doc = "Write proxy for field `pause`"] + pub struct PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `apb_data_width`"] + pub type APB_DATA_WIDTH_R = crate::R; + #[doc = "Write proxy for field `apb_data_width`"] + pub struct APB_DATA_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> APB_DATA_WIDTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `dflt_rpl`"] + pub type DFLT_RPL_R = crate::R; + #[doc = "Write proxy for field `dflt_rpl`"] + pub struct DFLT_RPL_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_RPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 10)) | (((value as u32) & 0x07) << 10); + self.w + } + } + #[doc = "Reader of field `dflt_top`"] + pub type DFLT_TOP_R = crate::R; + #[doc = "Write proxy for field `dflt_top`"] + pub struct DFLT_TOP_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_TOP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + #[doc = "Reader of field `dflt_top_init`"] + pub type DFLT_TOP_INIT_R = crate::R; + #[doc = "Write proxy for field `dflt_top_init`"] + pub struct DFLT_TOP_INIT_W<'a> { + w: &'a mut W, + } + impl<'a> DFLT_TOP_INIT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20); + self.w + } + } + #[doc = "Reader of field `cnt_width`"] + pub type CNT_WIDTH_R = crate::R; + #[doc = "Write proxy for field `cnt_width`"] + pub struct CNT_WIDTH_W<'a> { + w: &'a mut W, + } + impl<'a> CNT_WIDTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24); + self.w + } + } + impl R { + #[doc = "Bit 0 - always_en"] + #[inline(always)] + pub fn always_en(&self) -> ALWAYS_EN_R { + ALWAYS_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - dflt_rmod"] + #[inline(always)] + pub fn dflt_rmod(&self) -> DFLT_RMOD_R { + DFLT_RMOD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - dual_top"] + #[inline(always)] + pub fn dual_top(&self) -> DUAL_TOP_R { + DUAL_TOP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - hc_rmod"] + #[inline(always)] + pub fn hc_rmod(&self) -> HC_RMOD_R { + HC_RMOD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - hc_rpl"] + #[inline(always)] + pub fn hc_rpl(&self) -> HC_RPL_R { + HC_RPL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - hc_top"] + #[inline(always)] + pub fn hc_top(&self) -> HC_TOP_R { + HC_TOP_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - use_fix_top"] + #[inline(always)] + pub fn use_fix_top(&self) -> USE_FIX_TOP_R { + USE_FIX_TOP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - pause"] + #[inline(always)] + pub fn pause(&self) -> PAUSE_R { + PAUSE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - apb_data_width"] + #[inline(always)] + pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R { + APB_DATA_WIDTH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:12 - dflt_rpl"] + #[inline(always)] + pub fn dflt_rpl(&self) -> DFLT_RPL_R { + DFLT_RPL_R::new(((self.bits >> 10) & 0x07) as u8) + } + #[doc = "Bits 16:19 - dflt_top"] + #[inline(always)] + pub fn dflt_top(&self) -> DFLT_TOP_R { + DFLT_TOP_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - dflt_top_init"] + #[inline(always)] + pub fn dflt_top_init(&self) -> DFLT_TOP_INIT_R { + DFLT_TOP_INIT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:28 - cnt_width"] + #[inline(always)] + pub fn cnt_width(&self) -> CNT_WIDTH_R { + CNT_WIDTH_R::new(((self.bits >> 24) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bit 0 - always_en"] + #[inline(always)] + pub fn always_en(&mut self) -> ALWAYS_EN_W { + ALWAYS_EN_W { w: self } + } + #[doc = "Bit 1 - dflt_rmod"] + #[inline(always)] + pub fn dflt_rmod(&mut self) -> DFLT_RMOD_W { + DFLT_RMOD_W { w: self } + } + #[doc = "Bit 2 - dual_top"] + #[inline(always)] + pub fn dual_top(&mut self) -> DUAL_TOP_W { + DUAL_TOP_W { w: self } + } + #[doc = "Bit 3 - hc_rmod"] + #[inline(always)] + pub fn hc_rmod(&mut self) -> HC_RMOD_W { + HC_RMOD_W { w: self } + } + #[doc = "Bit 4 - hc_rpl"] + #[inline(always)] + pub fn hc_rpl(&mut self) -> HC_RPL_W { + HC_RPL_W { w: self } + } + #[doc = "Bit 5 - hc_top"] + #[inline(always)] + pub fn hc_top(&mut self) -> HC_TOP_W { + HC_TOP_W { w: self } + } + #[doc = "Bit 6 - use_fix_top"] + #[inline(always)] + pub fn use_fix_top(&mut self) -> USE_FIX_TOP_W { + USE_FIX_TOP_W { w: self } + } + #[doc = "Bit 7 - pause"] + #[inline(always)] + pub fn pause(&mut self) -> PAUSE_W { + PAUSE_W { w: self } + } + #[doc = "Bits 8:9 - apb_data_width"] + #[inline(always)] + pub fn apb_data_width(&mut self) -> APB_DATA_WIDTH_W { + APB_DATA_WIDTH_W { w: self } + } + #[doc = "Bits 10:12 - dflt_rpl"] + #[inline(always)] + pub fn dflt_rpl(&mut self) -> DFLT_RPL_W { + DFLT_RPL_W { w: self } + } + #[doc = "Bits 16:19 - dflt_top"] + #[inline(always)] + pub fn dflt_top(&mut self) -> DFLT_TOP_W { + DFLT_TOP_W { w: self } + } + #[doc = "Bits 20:23 - dflt_top_init"] + #[inline(always)] + pub fn dflt_top_init(&mut self) -> DFLT_TOP_INIT_W { + DFLT_TOP_INIT_W { w: self } + } + #[doc = "Bits 24:28 - cnt_width"] + #[inline(always)] + pub fn cnt_width(&mut self) -> CNT_WIDTH_W { + CNT_WIDTH_W { w: self } + } + } + } + #[doc = "Component Version Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_version](comp_version) module"] + pub type COMP_VERSION = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_VERSION; + #[doc = "`read()` method returns [comp_version::R](comp_version::R) reader structure"] + impl crate::Readable for COMP_VERSION {} + #[doc = "`write(|w| ..)` method takes [comp_version::W](comp_version::W) writer structure"] + impl crate::Writable for COMP_VERSION {} + #[doc = "Component Version Register"] + pub mod comp_version { + #[doc = "Reader of register comp_version"] + pub type R = crate::R; + #[doc = "Writer for register comp_version"] + pub type W = crate::W; + #[doc = "Register comp_version `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_VERSION { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Component Type Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_type](comp_type) module"] + pub type COMP_TYPE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _COMP_TYPE; + #[doc = "`read()` method returns [comp_type::R](comp_type::R) reader structure"] + impl crate::Readable for COMP_TYPE {} + #[doc = "`write(|w| ..)` method takes [comp_type::W](comp_type::W) writer structure"] + impl crate::Writable for COMP_TYPE {} + #[doc = "Component Type Register"] + pub mod comp_type { + #[doc = "Reader of register comp_type"] + pub type R = crate::R; + #[doc = "Writer for register comp_type"] + pub type W = crate::W; + #[doc = "Register comp_type `reset()`'s with value 0"] + impl crate::ResetValue for super::COMP_TYPE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Watchdog Timer 1"] +pub struct WDT1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT1 {} +impl WDT1 { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt0::RegisterBlock { + 0x5041_0000 as *const _ + } +} +impl Deref for WDT1 { + type Target = wdt0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*WDT1::ptr() } + } +} +#[doc = "One-Time Programmable Memory Controller"] +pub struct OTP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP {} +impl OTP { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp::RegisterBlock { + 0x5042_0000 as *const _ + } +} +impl Deref for OTP { + type Target = otp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*OTP::ptr() } + } +} +#[doc = "One-Time Programmable Memory Controller"] +pub mod otp { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Dummy register: this peripheral is not implemented yet"] + pub dummy: DUMMY, + } + #[doc = "Dummy register: this peripheral is not implemented yet\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dummy](dummy) module"] + pub type DUMMY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DUMMY; + #[doc = "`read()` method returns [dummy::R](dummy::R) reader structure"] + impl crate::Readable for DUMMY {} + #[doc = "`write(|w| ..)` method takes [dummy::W](dummy::W) writer structure"] + impl crate::Writable for DUMMY {} + #[doc = "Dummy register: this peripheral is not implemented yet"] + pub mod dummy { + #[doc = "Reader of register dummy"] + pub type R = crate::R; + #[doc = "Writer for register dummy"] + pub type W = crate::W; + #[doc = "Register dummy `reset()`'s with value 0"] + impl crate::ResetValue for super::DUMMY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Digital Video Port"] +pub struct DVP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DVP {} +impl DVP { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dvp::RegisterBlock { + 0x5043_0000 as *const _ + } +} +impl Deref for DVP { + type Target = dvp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*DVP::ptr() } + } +} +#[doc = "Digital Video Port"] +pub mod dvp { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Config Register"] + pub dvp_cfg: DVP_CFG, + #[doc = "0x04 - R_ADDR"] + pub r_addr: R_ADDR, + #[doc = "0x08 - G_ADDR"] + pub g_addr: G_ADDR, + #[doc = "0x0c - B_ADDR"] + pub b_addr: B_ADDR, + #[doc = "0x10 - CMOS Config Register"] + pub cmos_cfg: CMOS_CFG, + #[doc = "0x14 - SCCB Config Register"] + pub sccb_cfg: SCCB_CFG, + #[doc = "0x18 - SCCB Control Register"] + pub sccb_ctl: SCCB_CTL, + #[doc = "0x1c - AXI Register"] + pub axi: AXI, + #[doc = "0x20 - STS Register"] + pub sts: STS, + #[doc = "0x24 - REVERSE"] + pub reverse: REVERSE, + #[doc = "0x28 - RGB_ADDR"] + pub rgb_addr: RGB_ADDR, + } + #[doc = "Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvp_cfg](dvp_cfg) module"] + pub type DVP_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DVP_CFG; + #[doc = "`read()` method returns [dvp_cfg::R](dvp_cfg::R) reader structure"] + impl crate::Readable for DVP_CFG {} + #[doc = "`write(|w| ..)` method takes [dvp_cfg::W](dvp_cfg::W) writer structure"] + impl crate::Writable for DVP_CFG {} + #[doc = "Config Register"] + pub mod dvp_cfg { + #[doc = "Reader of register dvp_cfg"] + pub type R = crate::R; + #[doc = "Writer for register dvp_cfg"] + pub type W = crate::W; + #[doc = "Register dvp_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::DVP_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `start_int_enable`"] + pub type START_INT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `start_int_enable`"] + pub struct START_INT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> START_INT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `finish_int_enable`"] + pub type FINISH_INT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `finish_int_enable`"] + pub struct FINISH_INT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> FINISH_INT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ai_output_enable`"] + pub type AI_OUTPUT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `ai_output_enable`"] + pub struct AI_OUTPUT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> AI_OUTPUT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `display_output_enable`"] + pub type DISPLAY_OUTPUT_ENABLE_R = crate::R; + #[doc = "Write proxy for field `display_output_enable`"] + pub struct DISPLAY_OUTPUT_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> DISPLAY_OUTPUT_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `auto_enable`"] + pub type AUTO_ENABLE_R = crate::R; + #[doc = "Write proxy for field `auto_enable`"] + pub struct AUTO_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> AUTO_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `burst_size_4beats`"] + pub type BURST_SIZE_4BEATS_R = crate::R; + #[doc = "Write proxy for field `burst_size_4beats`"] + pub struct BURST_SIZE_4BEATS_W<'a> { + w: &'a mut W, + } + impl<'a> BURST_SIZE_4BEATS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "FORMAT\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum FORMAT_A { + #[doc = "0: RGB_FORMAT"] + RGB = 0, + #[doc = "1: YUV_FORMAT"] + YUV = 1, + #[doc = "3: Y_FORMAT"] + Y = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: FORMAT_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `format`"] + pub type FORMAT_R = crate::R; + impl FORMAT_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(FORMAT_A::RGB), + 1 => Val(FORMAT_A::YUV), + 3 => Val(FORMAT_A::Y), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `RGB`"] + #[inline(always)] + pub fn is_rgb(&self) -> bool { + *self == FORMAT_A::RGB + } + #[doc = "Checks if the value of the field is `YUV`"] + #[inline(always)] + pub fn is_yuv(&self) -> bool { + *self == FORMAT_A::YUV + } + #[doc = "Checks if the value of the field is `Y`"] + #[inline(always)] + pub fn is_y(&self) -> bool { + *self == FORMAT_A::Y + } + } + #[doc = "Write proxy for field `format`"] + pub struct FORMAT_W<'a> { + w: &'a mut W, + } + impl<'a> FORMAT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORMAT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RGB_FORMAT"] + #[inline(always)] + pub fn rgb(self) -> &'a mut W { + self.variant(FORMAT_A::RGB) + } + #[doc = "YUV_FORMAT"] + #[inline(always)] + pub fn yuv(self) -> &'a mut W { + self.variant(FORMAT_A::YUV) + } + #[doc = "Y_FORMAT"] + #[inline(always)] + pub fn y(self) -> &'a mut W { + self.variant(FORMAT_A::Y) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u32) & 0x03) << 9); + self.w + } + } + #[doc = "Reader of field `href_burst_num`"] + pub type HREF_BURST_NUM_R = crate::R; + #[doc = "Write proxy for field `href_burst_num`"] + pub struct HREF_BURST_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> HREF_BURST_NUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 12)) | (((value as u32) & 0xff) << 12); + self.w + } + } + #[doc = "Reader of field `line_num`"] + pub type LINE_NUM_R = crate::R; + #[doc = "Write proxy for field `line_num`"] + pub struct LINE_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> LINE_NUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 20)) | (((value as u32) & 0x03ff) << 20); + self.w + } + } + impl R { + #[doc = "Bit 0 - START_INT_ENABLE"] + #[inline(always)] + pub fn start_int_enable(&self) -> START_INT_ENABLE_R { + START_INT_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - FINISH_INT_ENABLE"] + #[inline(always)] + pub fn finish_int_enable(&self) -> FINISH_INT_ENABLE_R { + FINISH_INT_ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - AI_OUTPUT_ENABLE"] + #[inline(always)] + pub fn ai_output_enable(&self) -> AI_OUTPUT_ENABLE_R { + AI_OUTPUT_ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DISPLAY_OUTPUT_ENABLE"] + #[inline(always)] + pub fn display_output_enable(&self) -> DISPLAY_OUTPUT_ENABLE_R { + DISPLAY_OUTPUT_ENABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AUTO_ENABLE"] + #[inline(always)] + pub fn auto_enable(&self) -> AUTO_ENABLE_R { + AUTO_ENABLE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - BURST_SIZE_4BEATS"] + #[inline(always)] + pub fn burst_size_4beats(&self) -> BURST_SIZE_4BEATS_R { + BURST_SIZE_4BEATS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 9:10 - FORMAT"] + #[inline(always)] + pub fn format(&self) -> FORMAT_R { + FORMAT_R::new(((self.bits >> 9) & 0x03) as u8) + } + #[doc = "Bits 12:19 - HREF_BURST_NUM"] + #[inline(always)] + pub fn href_burst_num(&self) -> HREF_BURST_NUM_R { + HREF_BURST_NUM_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 20:29 - LINE_NUM"] + #[inline(always)] + pub fn line_num(&self) -> LINE_NUM_R { + LINE_NUM_R::new(((self.bits >> 20) & 0x03ff) as u16) + } + } + impl W { + #[doc = "Bit 0 - START_INT_ENABLE"] + #[inline(always)] + pub fn start_int_enable(&mut self) -> START_INT_ENABLE_W { + START_INT_ENABLE_W { w: self } + } + #[doc = "Bit 1 - FINISH_INT_ENABLE"] + #[inline(always)] + pub fn finish_int_enable(&mut self) -> FINISH_INT_ENABLE_W { + FINISH_INT_ENABLE_W { w: self } + } + #[doc = "Bit 2 - AI_OUTPUT_ENABLE"] + #[inline(always)] + pub fn ai_output_enable(&mut self) -> AI_OUTPUT_ENABLE_W { + AI_OUTPUT_ENABLE_W { w: self } + } + #[doc = "Bit 3 - DISPLAY_OUTPUT_ENABLE"] + #[inline(always)] + pub fn display_output_enable(&mut self) -> DISPLAY_OUTPUT_ENABLE_W { + DISPLAY_OUTPUT_ENABLE_W { w: self } + } + #[doc = "Bit 4 - AUTO_ENABLE"] + #[inline(always)] + pub fn auto_enable(&mut self) -> AUTO_ENABLE_W { + AUTO_ENABLE_W { w: self } + } + #[doc = "Bit 8 - BURST_SIZE_4BEATS"] + #[inline(always)] + pub fn burst_size_4beats(&mut self) -> BURST_SIZE_4BEATS_W { + BURST_SIZE_4BEATS_W { w: self } + } + #[doc = "Bits 9:10 - FORMAT"] + #[inline(always)] + pub fn format(&mut self) -> FORMAT_W { + FORMAT_W { w: self } + } + #[doc = "Bits 12:19 - HREF_BURST_NUM"] + #[inline(always)] + pub fn href_burst_num(&mut self) -> HREF_BURST_NUM_W { + HREF_BURST_NUM_W { w: self } + } + #[doc = "Bits 20:29 - LINE_NUM"] + #[inline(always)] + pub fn line_num(&mut self) -> LINE_NUM_W { + LINE_NUM_W { w: self } + } + } + } + #[doc = "R_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r_addr](r_addr) module"] + pub type R_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _R_ADDR; + #[doc = "`read()` method returns [r_addr::R](r_addr::R) reader structure"] + impl crate::Readable for R_ADDR {} + #[doc = "`write(|w| ..)` method takes [r_addr::W](r_addr::W) writer structure"] + impl crate::Writable for R_ADDR {} + #[doc = "R_ADDR"] + pub mod r_addr { + #[doc = "Reader of register r_addr"] + pub type R = crate::R; + #[doc = "Writer for register r_addr"] + pub type W = crate::W; + #[doc = "Register r_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::R_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "G_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [g_addr](g_addr) module"] + pub type G_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _G_ADDR; + #[doc = "`read()` method returns [g_addr::R](g_addr::R) reader structure"] + impl crate::Readable for G_ADDR {} + #[doc = "`write(|w| ..)` method takes [g_addr::W](g_addr::W) writer structure"] + impl crate::Writable for G_ADDR {} + #[doc = "G_ADDR"] + pub mod g_addr { + #[doc = "Reader of register g_addr"] + pub type R = crate::R; + #[doc = "Writer for register g_addr"] + pub type W = crate::W; + #[doc = "Register g_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::G_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "B_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [b_addr](b_addr) module"] + pub type B_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _B_ADDR; + #[doc = "`read()` method returns [b_addr::R](b_addr::R) reader structure"] + impl crate::Readable for B_ADDR {} + #[doc = "`write(|w| ..)` method takes [b_addr::W](b_addr::W) writer structure"] + impl crate::Writable for B_ADDR {} + #[doc = "B_ADDR"] + pub mod b_addr { + #[doc = "Reader of register b_addr"] + pub type R = crate::R; + #[doc = "Writer for register b_addr"] + pub type W = crate::W; + #[doc = "Register b_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::B_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "CMOS Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmos_cfg](cmos_cfg) module"] + pub type CMOS_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CMOS_CFG; + #[doc = "`read()` method returns [cmos_cfg::R](cmos_cfg::R) reader structure"] + impl crate::Readable for CMOS_CFG {} + #[doc = "`write(|w| ..)` method takes [cmos_cfg::W](cmos_cfg::W) writer structure"] + impl crate::Writable for CMOS_CFG {} + #[doc = "CMOS Config Register"] + pub mod cmos_cfg { + #[doc = "Reader of register cmos_cfg"] + pub type R = crate::R; + #[doc = "Writer for register cmos_cfg"] + pub type W = crate::W; + #[doc = "Register cmos_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::CMOS_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clk_div`"] + pub type CLK_DIV_R = crate::R; + #[doc = "Write proxy for field `clk_div`"] + pub struct CLK_DIV_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `clk_enable`"] + pub type CLK_ENABLE_R = crate::R; + #[doc = "Write proxy for field `clk_enable`"] + pub struct CLK_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> CLK_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `power_down`"] + pub type POWER_DOWN_R = crate::R; + #[doc = "Write proxy for field `power_down`"] + pub struct POWER_DOWN_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_DOWN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - CLK_DIV"] + #[inline(always)] + pub fn clk_div(&self) -> CLK_DIV_R { + CLK_DIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - CLK_ENABLE"] + #[inline(always)] + pub fn clk_enable(&self) -> CLK_ENABLE_R { + CLK_ENABLE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 16 - RESET"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 24 - POWER_DOWN"] + #[inline(always)] + pub fn power_down(&self) -> POWER_DOWN_R { + POWER_DOWN_R::new(((self.bits >> 24) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:7 - CLK_DIV"] + #[inline(always)] + pub fn clk_div(&mut self) -> CLK_DIV_W { + CLK_DIV_W { w: self } + } + #[doc = "Bit 8 - CLK_ENABLE"] + #[inline(always)] + pub fn clk_enable(&mut self) -> CLK_ENABLE_W { + CLK_ENABLE_W { w: self } + } + #[doc = "Bit 16 - RESET"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 24 - POWER_DOWN"] + #[inline(always)] + pub fn power_down(&mut self) -> POWER_DOWN_W { + POWER_DOWN_W { w: self } + } + } + } + #[doc = "SCCB Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sccb_cfg](sccb_cfg) module"] + pub type SCCB_CFG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SCCB_CFG; + #[doc = "`read()` method returns [sccb_cfg::R](sccb_cfg::R) reader structure"] + impl crate::Readable for SCCB_CFG {} + #[doc = "`write(|w| ..)` method takes [sccb_cfg::W](sccb_cfg::W) writer structure"] + impl crate::Writable for SCCB_CFG {} + #[doc = "SCCB Config Register"] + pub mod sccb_cfg { + #[doc = "Reader of register sccb_cfg"] + pub type R = crate::R; + #[doc = "Writer for register sccb_cfg"] + pub type W = crate::W; + #[doc = "Register sccb_cfg `reset()`'s with value 0"] + impl crate::ResetValue for super::SCCB_CFG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "BYTE_NUM\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum BYTE_NUM_A { + #[doc = "1: BYTE_NUM_2"] + NUM2 = 1, + #[doc = "2: BYTE_NUM_3"] + NUM3 = 2, + #[doc = "3: BYTE_NUM_4"] + NUM4 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: BYTE_NUM_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `byte_num`"] + pub type BYTE_NUM_R = crate::R; + impl BYTE_NUM_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 1 => Val(BYTE_NUM_A::NUM2), + 2 => Val(BYTE_NUM_A::NUM3), + 3 => Val(BYTE_NUM_A::NUM4), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `NUM2`"] + #[inline(always)] + pub fn is_num2(&self) -> bool { + *self == BYTE_NUM_A::NUM2 + } + #[doc = "Checks if the value of the field is `NUM3`"] + #[inline(always)] + pub fn is_num3(&self) -> bool { + *self == BYTE_NUM_A::NUM3 + } + #[doc = "Checks if the value of the field is `NUM4`"] + #[inline(always)] + pub fn is_num4(&self) -> bool { + *self == BYTE_NUM_A::NUM4 + } + } + #[doc = "Write proxy for field `byte_num`"] + pub struct BYTE_NUM_W<'a> { + w: &'a mut W, + } + impl<'a> BYTE_NUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BYTE_NUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "BYTE_NUM_2"] + #[inline(always)] + pub fn num2(self) -> &'a mut W { + self.variant(BYTE_NUM_A::NUM2) + } + #[doc = "BYTE_NUM_3"] + #[inline(always)] + pub fn num3(self) -> &'a mut W { + self.variant(BYTE_NUM_A::NUM3) + } + #[doc = "BYTE_NUM_4"] + #[inline(always)] + pub fn num4(self) -> &'a mut W { + self.variant(BYTE_NUM_A::NUM4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `scl_lcnt`"] + pub type SCL_LCNT_R = crate::R; + #[doc = "Write proxy for field `scl_lcnt`"] + pub struct SCL_LCNT_W<'a> { + w: &'a mut W, + } + impl<'a> SCL_LCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `scl_hcnt`"] + pub type SCL_HCNT_R = crate::R; + #[doc = "Write proxy for field `scl_hcnt`"] + pub struct SCL_HCNT_W<'a> { + w: &'a mut W, + } + impl<'a> SCL_HCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `rdata`"] + pub type RDATA_R = crate::R; + impl R { + #[doc = "Bits 0:1 - BYTE_NUM"] + #[inline(always)] + pub fn byte_num(&self) -> BYTE_NUM_R { + BYTE_NUM_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 8:15 - SCL_LCNT"] + #[inline(always)] + pub fn scl_lcnt(&self) -> SCL_LCNT_R { + SCL_LCNT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - SCL_HCNT"] + #[inline(always)] + pub fn scl_hcnt(&self) -> SCL_HCNT_R { + SCL_HCNT_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - RDATA"] + #[inline(always)] + pub fn rdata(&self) -> RDATA_R { + RDATA_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - BYTE_NUM"] + #[inline(always)] + pub fn byte_num(&mut self) -> BYTE_NUM_W { + BYTE_NUM_W { w: self } + } + #[doc = "Bits 8:15 - SCL_LCNT"] + #[inline(always)] + pub fn scl_lcnt(&mut self) -> SCL_LCNT_W { + SCL_LCNT_W { w: self } + } + #[doc = "Bits 16:23 - SCL_HCNT"] + #[inline(always)] + pub fn scl_hcnt(&mut self) -> SCL_HCNT_W { + SCL_HCNT_W { w: self } + } + } + } + #[doc = "SCCB Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sccb_ctl](sccb_ctl) module"] + pub type SCCB_CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SCCB_CTL; + #[doc = "`read()` method returns [sccb_ctl::R](sccb_ctl::R) reader structure"] + impl crate::Readable for SCCB_CTL {} + #[doc = "`write(|w| ..)` method takes [sccb_ctl::W](sccb_ctl::W) writer structure"] + impl crate::Writable for SCCB_CTL {} + #[doc = "SCCB Control Register"] + pub mod sccb_ctl { + #[doc = "Reader of register sccb_ctl"] + pub type R = crate::R; + #[doc = "Writer for register sccb_ctl"] + pub type W = crate::W; + #[doc = "Register sccb_ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::SCCB_CTL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `device_address`"] + pub type DEVICE_ADDRESS_R = crate::R; + #[doc = "Write proxy for field `device_address`"] + pub struct DEVICE_ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> DEVICE_ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `reg_address`"] + pub type REG_ADDRESS_R = crate::R; + #[doc = "Write proxy for field `reg_address`"] + pub struct REG_ADDRESS_W<'a> { + w: &'a mut W, + } + impl<'a> REG_ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `wdata_byte0`"] + pub type WDATA_BYTE0_R = crate::R; + #[doc = "Write proxy for field `wdata_byte0`"] + pub struct WDATA_BYTE0_W<'a> { + w: &'a mut W, + } + impl<'a> WDATA_BYTE0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `wdata_byte1`"] + pub type WDATA_BYTE1_R = crate::R; + #[doc = "Write proxy for field `wdata_byte1`"] + pub struct WDATA_BYTE1_W<'a> { + w: &'a mut W, + } + impl<'a> WDATA_BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - DEVICE_ADDRESS"] + #[inline(always)] + pub fn device_address(&self) -> DEVICE_ADDRESS_R { + DEVICE_ADDRESS_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - REG_ADDRESS"] + #[inline(always)] + pub fn reg_address(&self) -> REG_ADDRESS_R { + REG_ADDRESS_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - WDATA_BYTE0"] + #[inline(always)] + pub fn wdata_byte0(&self) -> WDATA_BYTE0_R { + WDATA_BYTE0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - WDATA_BYTE1"] + #[inline(always)] + pub fn wdata_byte1(&self) -> WDATA_BYTE1_R { + WDATA_BYTE1_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - DEVICE_ADDRESS"] + #[inline(always)] + pub fn device_address(&mut self) -> DEVICE_ADDRESS_W { + DEVICE_ADDRESS_W { w: self } + } + #[doc = "Bits 8:15 - REG_ADDRESS"] + #[inline(always)] + pub fn reg_address(&mut self) -> REG_ADDRESS_W { + REG_ADDRESS_W { w: self } + } + #[doc = "Bits 16:23 - WDATA_BYTE0"] + #[inline(always)] + pub fn wdata_byte0(&mut self) -> WDATA_BYTE0_W { + WDATA_BYTE0_W { w: self } + } + #[doc = "Bits 24:31 - WDATA_BYTE1"] + #[inline(always)] + pub fn wdata_byte1(&mut self) -> WDATA_BYTE1_W { + WDATA_BYTE1_W { w: self } + } + } + } + #[doc = "AXI Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [axi](axi) module"] + pub type AXI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AXI; + #[doc = "`read()` method returns [axi::R](axi::R) reader structure"] + impl crate::Readable for AXI {} + #[doc = "`write(|w| ..)` method takes [axi::W](axi::W) writer structure"] + impl crate::Writable for AXI {} + #[doc = "AXI Register"] + pub mod axi { + #[doc = "Reader of register axi"] + pub type R = crate::R; + #[doc = "Writer for register axi"] + pub type W = crate::W; + #[doc = "Register axi `reset()`'s with value 0"] + impl crate::ResetValue for super::AXI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "GM_MLEN\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum GM_MLEN_A { + #[doc = "0: GM_MLEN_1BYTE"] + BYTE1 = 0, + #[doc = "3: GM_MLEN_4BYTE"] + BYTE4 = 3, + } + impl From for u8 { + #[inline(always)] + fn from(variant: GM_MLEN_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `gm_mlen`"] + pub type GM_MLEN_R = crate::R; + impl GM_MLEN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(GM_MLEN_A::BYTE1), + 3 => Val(GM_MLEN_A::BYTE4), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `BYTE1`"] + #[inline(always)] + pub fn is_byte1(&self) -> bool { + *self == GM_MLEN_A::BYTE1 + } + #[doc = "Checks if the value of the field is `BYTE4`"] + #[inline(always)] + pub fn is_byte4(&self) -> bool { + *self == GM_MLEN_A::BYTE4 + } + } + #[doc = "Write proxy for field `gm_mlen`"] + pub struct GM_MLEN_W<'a> { + w: &'a mut W, + } + impl<'a> GM_MLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GM_MLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "GM_MLEN_1BYTE"] + #[inline(always)] + pub fn byte1(self) -> &'a mut W { + self.variant(GM_MLEN_A::BYTE1) + } + #[doc = "GM_MLEN_4BYTE"] + #[inline(always)] + pub fn byte4(self) -> &'a mut W { + self.variant(GM_MLEN_A::BYTE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + impl R { + #[doc = "Bits 0:7 - GM_MLEN"] + #[inline(always)] + pub fn gm_mlen(&self) -> GM_MLEN_R { + GM_MLEN_R::new((self.bits & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7 - GM_MLEN"] + #[inline(always)] + pub fn gm_mlen(&mut self) -> GM_MLEN_W { + GM_MLEN_W { w: self } + } + } + } + #[doc = "STS Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sts](sts) module"] + pub type STS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _STS; + #[doc = "`read()` method returns [sts::R](sts::R) reader structure"] + impl crate::Readable for STS {} + #[doc = "`write(|w| ..)` method takes [sts::W](sts::W) writer structure"] + impl crate::Writable for STS {} + #[doc = "STS Register"] + pub mod sts { + #[doc = "Reader of register sts"] + pub type R = crate::R; + #[doc = "Writer for register sts"] + pub type W = crate::W; + #[doc = "Register sts `reset()`'s with value 0"] + impl crate::ResetValue for super::STS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `frame_start`"] + pub type FRAME_START_R = crate::R; + #[doc = "Write proxy for field `frame_start`"] + pub struct FRAME_START_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `frame_start_we`"] + pub type FRAME_START_WE_R = crate::R; + #[doc = "Write proxy for field `frame_start_we`"] + pub struct FRAME_START_WE_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_START_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `frame_finish`"] + pub type FRAME_FINISH_R = crate::R; + #[doc = "Write proxy for field `frame_finish`"] + pub struct FRAME_FINISH_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FINISH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `frame_finish_we`"] + pub type FRAME_FINISH_WE_R = crate::R; + #[doc = "Write proxy for field `frame_finish_we`"] + pub struct FRAME_FINISH_WE_W<'a> { + w: &'a mut W, + } + impl<'a> FRAME_FINISH_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `dvp_en`"] + pub type DVP_EN_R = crate::R; + #[doc = "Write proxy for field `dvp_en`"] + pub struct DVP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `dvp_en_we`"] + pub type DVP_EN_WE_R = crate::R; + #[doc = "Write proxy for field `dvp_en_we`"] + pub struct DVP_EN_WE_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_EN_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `sccb_en`"] + pub type SCCB_EN_R = crate::R; + #[doc = "Write proxy for field `sccb_en`"] + pub struct SCCB_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SCCB_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `sccb_en_we`"] + pub type SCCB_EN_WE_R = crate::R; + #[doc = "Write proxy for field `sccb_en_we`"] + pub struct SCCB_EN_WE_W<'a> { + w: &'a mut W, + } + impl<'a> SCCB_EN_WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + impl R { + #[doc = "Bit 0 - FRAME_START"] + #[inline(always)] + pub fn frame_start(&self) -> FRAME_START_R { + FRAME_START_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - FRAME_START_WE"] + #[inline(always)] + pub fn frame_start_we(&self) -> FRAME_START_WE_R { + FRAME_START_WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 8 - FRAME_FINISH"] + #[inline(always)] + pub fn frame_finish(&self) -> FRAME_FINISH_R { + FRAME_FINISH_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - FRAME_FINISH_WE"] + #[inline(always)] + pub fn frame_finish_we(&self) -> FRAME_FINISH_WE_R { + FRAME_FINISH_WE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 16 - DVP_EN"] + #[inline(always)] + pub fn dvp_en(&self) -> DVP_EN_R { + DVP_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DVP_EN_WE"] + #[inline(always)] + pub fn dvp_en_we(&self) -> DVP_EN_WE_R { + DVP_EN_WE_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 24 - SCCB_EN"] + #[inline(always)] + pub fn sccb_en(&self) -> SCCB_EN_R { + SCCB_EN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - SCCB_EN_WE"] + #[inline(always)] + pub fn sccb_en_we(&self) -> SCCB_EN_WE_R { + SCCB_EN_WE_R::new(((self.bits >> 25) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - FRAME_START"] + #[inline(always)] + pub fn frame_start(&mut self) -> FRAME_START_W { + FRAME_START_W { w: self } + } + #[doc = "Bit 1 - FRAME_START_WE"] + #[inline(always)] + pub fn frame_start_we(&mut self) -> FRAME_START_WE_W { + FRAME_START_WE_W { w: self } + } + #[doc = "Bit 8 - FRAME_FINISH"] + #[inline(always)] + pub fn frame_finish(&mut self) -> FRAME_FINISH_W { + FRAME_FINISH_W { w: self } + } + #[doc = "Bit 9 - FRAME_FINISH_WE"] + #[inline(always)] + pub fn frame_finish_we(&mut self) -> FRAME_FINISH_WE_W { + FRAME_FINISH_WE_W { w: self } + } + #[doc = "Bit 16 - DVP_EN"] + #[inline(always)] + pub fn dvp_en(&mut self) -> DVP_EN_W { + DVP_EN_W { w: self } + } + #[doc = "Bit 17 - DVP_EN_WE"] + #[inline(always)] + pub fn dvp_en_we(&mut self) -> DVP_EN_WE_W { + DVP_EN_WE_W { w: self } + } + #[doc = "Bit 24 - SCCB_EN"] + #[inline(always)] + pub fn sccb_en(&mut self) -> SCCB_EN_W { + SCCB_EN_W { w: self } + } + #[doc = "Bit 25 - SCCB_EN_WE"] + #[inline(always)] + pub fn sccb_en_we(&mut self) -> SCCB_EN_WE_W { + SCCB_EN_WE_W { w: self } + } + } + } + #[doc = "REVERSE\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reverse](reverse) module"] + pub type REVERSE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _REVERSE; + #[doc = "`read()` method returns [reverse::R](reverse::R) reader structure"] + impl crate::Readable for REVERSE {} + #[doc = "`write(|w| ..)` method takes [reverse::W](reverse::W) writer structure"] + impl crate::Writable for REVERSE {} + #[doc = "REVERSE"] + pub mod reverse { + #[doc = "Reader of register reverse"] + pub type R = crate::R; + #[doc = "Writer for register reverse"] + pub type W = crate::W; + #[doc = "Register reverse `reset()`'s with value 0"] + impl crate::ResetValue for super::REVERSE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "RGB_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rgb_addr](rgb_addr) module"] + pub type RGB_ADDR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RGB_ADDR; + #[doc = "`read()` method returns [rgb_addr::R](rgb_addr::R) reader structure"] + impl crate::Readable for RGB_ADDR {} + #[doc = "`write(|w| ..)` method takes [rgb_addr::W](rgb_addr::W) writer structure"] + impl crate::Writable for RGB_ADDR {} + #[doc = "RGB_ADDR"] + pub mod rgb_addr { + #[doc = "Reader of register rgb_addr"] + pub type R = crate::R; + #[doc = "Writer for register rgb_addr"] + pub type W = crate::W; + #[doc = "Register rgb_addr `reset()`'s with value 0"] + impl crate::ResetValue for super::RGB_ADDR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "System Controller"] +pub struct SYSCTL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCTL {} +impl SYSCTL { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysctl::RegisterBlock { + 0x5044_0000 as *const _ + } +} +impl Deref for SYSCTL { + type Target = sysctl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*SYSCTL::ptr() } + } +} +#[doc = "System Controller"] +pub mod sysctl { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Git short commit id"] + pub git_id: GIT_ID, + #[doc = "0x04 - System clock base frequency"] + pub clk_freq: CLK_FREQ, + #[doc = "0x08 - PLL0 controller"] + pub pll0: PLL0, + #[doc = "0x0c - PLL1 controller"] + pub pll1: PLL1, + #[doc = "0x10 - PLL2 controller"] + pub pll2: PLL2, + _reserved5: [u8; 4usize], + #[doc = "0x18 - PLL lock tester"] + pub pll_lock: PLL_LOCK, + #[doc = "0x1c - AXI ROM detector"] + pub rom_error: ROM_ERROR, + #[doc = "0x20 - Clock select controller 0"] + pub clk_sel0: CLK_SEL0, + #[doc = "0x24 - Clock select controller 1"] + pub clk_sel1: CLK_SEL1, + #[doc = "0x28 - Central clock enable"] + pub clk_en_cent: CLK_EN_CENT, + #[doc = "0x2c - Peripheral clock enable"] + pub clk_en_peri: CLK_EN_PERI, + #[doc = "0x30 - Soft reset ctrl"] + pub soft_reset: SOFT_RESET, + #[doc = "0x34 - Peripheral reset controller"] + pub peri_reset: PERI_RESET, + #[doc = "0x38 - Clock threshold controller 0"] + pub clk_th0: CLK_TH0, + #[doc = "0x3c - Clock threshold controller 1"] + pub clk_th1: CLK_TH1, + #[doc = "0x40 - Clock threshold controller 2"] + pub clk_th2: CLK_TH2, + #[doc = "0x44 - Clock threshold controller 3"] + pub clk_th3: CLK_TH3, + #[doc = "0x48 - Clock threshold controller 4"] + pub clk_th4: CLK_TH4, + #[doc = "0x4c - Clock threshold controller 5"] + pub clk_th5: CLK_TH5, + #[doc = "0x50 - Clock threshold controller 6"] + pub clk_th6: CLK_TH6, + #[doc = "0x54 - Miscellaneous controller"] + pub misc: MISC, + #[doc = "0x58 - Peripheral controller"] + pub peri: PERI, + #[doc = "0x5c - SPI sleep controller"] + pub spi_sleep: SPI_SLEEP, + #[doc = "0x60 - Reset source status"] + pub reset_status: RESET_STATUS, + #[doc = "0x64 - DMA handshake selector"] + pub dma_sel0: DMA_SEL0, + #[doc = "0x68 - DMA handshake selector"] + pub dma_sel1: DMA_SEL1, + #[doc = "0x6c - IO Power Mode Select controller"] + pub power_sel: POWER_SEL, + } + #[doc = "Git short commit id\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [git_id](git_id) module"] + pub type GIT_ID = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GIT_ID; + #[doc = "`read()` method returns [git_id::R](git_id::R) reader structure"] + impl crate::Readable for GIT_ID {} + #[doc = "`write(|w| ..)` method takes [git_id::W](git_id::W) writer structure"] + impl crate::Writable for GIT_ID {} + #[doc = "Git short commit id"] + pub mod git_id { + #[doc = "Reader of register git_id"] + pub type R = crate::R; + #[doc = "Writer for register git_id"] + pub type W = crate::W; + #[doc = "Register git_id `reset()`'s with value 0"] + impl crate::ResetValue for super::GIT_ID { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "System clock base frequency\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_freq](clk_freq) module"] + pub type CLK_FREQ = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_FREQ; + #[doc = "`read()` method returns [clk_freq::R](clk_freq::R) reader structure"] + impl crate::Readable for CLK_FREQ {} + #[doc = "`write(|w| ..)` method takes [clk_freq::W](clk_freq::W) writer structure"] + impl crate::Writable for CLK_FREQ {} + #[doc = "System clock base frequency"] + pub mod clk_freq { + #[doc = "Reader of register clk_freq"] + pub type R = crate::R; + #[doc = "Writer for register clk_freq"] + pub type W = crate::W; + #[doc = "Register clk_freq `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_FREQ { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "PLL0 controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0](pll0) module"] + pub type PLL0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL0; + #[doc = "`read()` method returns [pll0::R](pll0::R) reader structure"] + impl crate::Readable for PLL0 {} + #[doc = "`write(|w| ..)` method takes [pll0::W](pll0::W) writer structure"] + impl crate::Writable for PLL0 {} + #[doc = "PLL0 controller"] + pub mod pll0 { + #[doc = "Reader of register pll0"] + pub type R = crate::R; + #[doc = "Writer for register pll0"] + pub type W = crate::W; + #[doc = "Register pll0 `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clkr`"] + pub type CLKR_R = crate::R; + #[doc = "Write proxy for field `clkr`"] + pub struct CLKR_W<'a> { + w: &'a mut W, + } + impl<'a> CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `clkf`"] + pub type CLKF_R = crate::R; + #[doc = "Write proxy for field `clkf`"] + pub struct CLKF_W<'a> { + w: &'a mut W, + } + impl<'a> CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4); + self.w + } + } + #[doc = "Reader of field `clkod`"] + pub type CLKOD_R = crate::R; + #[doc = "Write proxy for field `clkod`"] + pub struct CLKOD_W<'a> { + w: &'a mut W, + } + impl<'a> CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); + self.w + } + } + #[doc = "Reader of field `bwadj`"] + pub type BWADJ_R = crate::R; + #[doc = "Write proxy for field `bwadj`"] + pub struct BWADJ_W<'a> { + w: &'a mut W, + } + impl<'a> BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 14)) | (((value as u32) & 0x3f) << 14); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `pwrd`"] + pub type PWRD_R = crate::R; + #[doc = "Write proxy for field `pwrd`"] + pub struct PWRD_W<'a> { + w: &'a mut W, + } + impl<'a> PWRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `intfb`"] + pub type INTFB_R = crate::R; + #[doc = "Write proxy for field `intfb`"] + pub struct INTFB_W<'a> { + w: &'a mut W, + } + impl<'a> INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `bypass`"] + pub type BYPASS_R = crate::R; + #[doc = "Write proxy for field `bypass`"] + pub struct BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `test`"] + pub type TEST_R = crate::R; + #[doc = "Write proxy for field `test`"] + pub struct TEST_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `out_en`"] + pub type OUT_EN_R = crate::R; + #[doc = "Write proxy for field `out_en`"] + pub struct OUT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OUT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `test_en`"] + pub type TEST_EN_R = crate::R; + #[doc = "Write proxy for field `test_en`"] + pub struct TEST_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&self) -> CLKR_R { + CLKR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&self) -> CLKF_R { + CLKF_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&self) -> CLKOD_R { + CLKOD_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&self) -> BWADJ_R { + BWADJ_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&self) -> PWRD_R { + PWRD_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&self) -> INTFB_R { + INTFB_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&self) -> OUT_EN_R { + OUT_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn test_en(&self) -> TEST_EN_R { + TEST_EN_R::new(((self.bits >> 26) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&mut self) -> CLKR_W { + CLKR_W { w: self } + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&mut self) -> CLKF_W { + CLKF_W { w: self } + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&mut self) -> CLKOD_W { + CLKOD_W { w: self } + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&mut self) -> BWADJ_W { + BWADJ_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&mut self) -> PWRD_W { + PWRD_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&mut self) -> INTFB_W { + INTFB_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&mut self) -> OUT_EN_W { + OUT_EN_W { w: self } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn test_en(&mut self) -> TEST_EN_W { + TEST_EN_W { w: self } + } + } + } + #[doc = "PLL1 controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1](pll1) module"] + pub type PLL1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL1; + #[doc = "`read()` method returns [pll1::R](pll1::R) reader structure"] + impl crate::Readable for PLL1 {} + #[doc = "`write(|w| ..)` method takes [pll1::W](pll1::W) writer structure"] + impl crate::Writable for PLL1 {} + #[doc = "PLL1 controller"] + pub mod pll1 { + #[doc = "Reader of register pll1"] + pub type R = crate::R; + #[doc = "Writer for register pll1"] + pub type W = crate::W; + #[doc = "Register pll1 `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clkr`"] + pub type CLKR_R = crate::R; + #[doc = "Write proxy for field `clkr`"] + pub struct CLKR_W<'a> { + w: &'a mut W, + } + impl<'a> CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `clkf`"] + pub type CLKF_R = crate::R; + #[doc = "Write proxy for field `clkf`"] + pub struct CLKF_W<'a> { + w: &'a mut W, + } + impl<'a> CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4); + self.w + } + } + #[doc = "Reader of field `clkod`"] + pub type CLKOD_R = crate::R; + #[doc = "Write proxy for field `clkod`"] + pub struct CLKOD_W<'a> { + w: &'a mut W, + } + impl<'a> CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); + self.w + } + } + #[doc = "Reader of field `bwadj`"] + pub type BWADJ_R = crate::R; + #[doc = "Write proxy for field `bwadj`"] + pub struct BWADJ_W<'a> { + w: &'a mut W, + } + impl<'a> BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 14)) | (((value as u32) & 0x3f) << 14); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `pwrd`"] + pub type PWRD_R = crate::R; + #[doc = "Write proxy for field `pwrd`"] + pub struct PWRD_W<'a> { + w: &'a mut W, + } + impl<'a> PWRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `intfb`"] + pub type INTFB_R = crate::R; + #[doc = "Write proxy for field `intfb`"] + pub struct INTFB_W<'a> { + w: &'a mut W, + } + impl<'a> INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `bypass`"] + pub type BYPASS_R = crate::R; + #[doc = "Write proxy for field `bypass`"] + pub struct BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `test`"] + pub type TEST_R = crate::R; + #[doc = "Write proxy for field `test`"] + pub struct TEST_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `out_en`"] + pub type OUT_EN_R = crate::R; + #[doc = "Write proxy for field `out_en`"] + pub struct OUT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OUT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&self) -> CLKR_R { + CLKR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&self) -> CLKF_R { + CLKF_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&self) -> CLKOD_R { + CLKOD_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&self) -> BWADJ_R { + BWADJ_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&self) -> PWRD_R { + PWRD_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&self) -> INTFB_R { + INTFB_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&self) -> OUT_EN_R { + OUT_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&mut self) -> CLKR_W { + CLKR_W { w: self } + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&mut self) -> CLKF_W { + CLKF_W { w: self } + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&mut self) -> CLKOD_W { + CLKOD_W { w: self } + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&mut self) -> BWADJ_W { + BWADJ_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&mut self) -> PWRD_W { + PWRD_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&mut self) -> INTFB_W { + INTFB_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&mut self) -> OUT_EN_W { + OUT_EN_W { w: self } + } + } + } + #[doc = "PLL2 controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll2](pll2) module"] + pub type PLL2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL2; + #[doc = "`read()` method returns [pll2::R](pll2::R) reader structure"] + impl crate::Readable for PLL2 {} + #[doc = "`write(|w| ..)` method takes [pll2::W](pll2::W) writer structure"] + impl crate::Writable for PLL2 {} + #[doc = "PLL2 controller"] + pub mod pll2 { + #[doc = "Reader of register pll2"] + pub type R = crate::R; + #[doc = "Writer for register pll2"] + pub type W = crate::W; + #[doc = "Register pll2 `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `clkr`"] + pub type CLKR_R = crate::R; + #[doc = "Write proxy for field `clkr`"] + pub struct CLKR_W<'a> { + w: &'a mut W, + } + impl<'a> CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `clkf`"] + pub type CLKF_R = crate::R; + #[doc = "Write proxy for field `clkf`"] + pub struct CLKF_W<'a> { + w: &'a mut W, + } + impl<'a> CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4); + self.w + } + } + #[doc = "Reader of field `clkod`"] + pub type CLKOD_R = crate::R; + #[doc = "Write proxy for field `clkod`"] + pub struct CLKOD_W<'a> { + w: &'a mut W, + } + impl<'a> CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); + self.w + } + } + #[doc = "Reader of field `bwadj`"] + pub type BWADJ_R = crate::R; + #[doc = "Write proxy for field `bwadj`"] + pub struct BWADJ_W<'a> { + w: &'a mut W, + } + impl<'a> BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 14)) | (((value as u32) & 0x3f) << 14); + self.w + } + } + #[doc = "Reader of field `reset`"] + pub type RESET_R = crate::R; + #[doc = "Write proxy for field `reset`"] + pub struct RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `pwrd`"] + pub type PWRD_R = crate::R; + #[doc = "Write proxy for field `pwrd`"] + pub struct PWRD_W<'a> { + w: &'a mut W, + } + impl<'a> PWRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `intfb`"] + pub type INTFB_R = crate::R; + #[doc = "Write proxy for field `intfb`"] + pub struct INTFB_W<'a> { + w: &'a mut W, + } + impl<'a> INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `bypass`"] + pub type BYPASS_R = crate::R; + #[doc = "Write proxy for field `bypass`"] + pub struct BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `test`"] + pub type TEST_R = crate::R; + #[doc = "Write proxy for field `test`"] + pub struct TEST_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `out_en`"] + pub type OUT_EN_R = crate::R; + #[doc = "Write proxy for field `out_en`"] + pub struct OUT_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OUT_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `ckin_sel`"] + pub type CKIN_SEL_R = crate::R; + #[doc = "Write proxy for field `ckin_sel`"] + pub struct CKIN_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> CKIN_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&self) -> CLKR_R { + CLKR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&self) -> CLKF_R { + CLKF_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&self) -> CLKOD_R { + CLKOD_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&self) -> BWADJ_R { + BWADJ_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&self) -> PWRD_R { + PWRD_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&self) -> INTFB_R { + INTFB_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&self) -> OUT_EN_R { + OUT_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bits 26:27"] + #[inline(always)] + pub fn ckin_sel(&self) -> CKIN_SEL_R { + CKIN_SEL_R::new(((self.bits >> 26) & 0x03) as u8) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn clkr(&mut self) -> CLKR_W { + CLKR_W { w: self } + } + #[doc = "Bits 4:9"] + #[inline(always)] + pub fn clkf(&mut self) -> CLKF_W { + CLKF_W { w: self } + } + #[doc = "Bits 10:13"] + #[inline(always)] + pub fn clkod(&mut self) -> CLKOD_W { + CLKOD_W { w: self } + } + #[doc = "Bits 14:19"] + #[inline(always)] + pub fn bwadj(&mut self) -> BWADJ_W { + BWADJ_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn pwrd(&mut self) -> PWRD_W { + PWRD_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn intfb(&mut self) -> INTFB_W { + INTFB_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn out_en(&mut self) -> OUT_EN_W { + OUT_EN_W { w: self } + } + #[doc = "Bits 26:27"] + #[inline(always)] + pub fn ckin_sel(&mut self) -> CKIN_SEL_W { + CKIN_SEL_W { w: self } + } + } + } + #[doc = "PLL lock tester\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll_lock](pll_lock) module"] + pub type PLL_LOCK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PLL_LOCK; + #[doc = "`read()` method returns [pll_lock::R](pll_lock::R) reader structure"] + impl crate::Readable for PLL_LOCK {} + #[doc = "`write(|w| ..)` method takes [pll_lock::W](pll_lock::W) writer structure"] + impl crate::Writable for PLL_LOCK {} + #[doc = "PLL lock tester"] + pub mod pll_lock { + #[doc = "Reader of register pll_lock"] + pub type R = crate::R; + #[doc = "Writer for register pll_lock"] + pub type W = crate::W; + #[doc = "Register pll_lock `reset()`'s with value 0"] + impl crate::ResetValue for super::PLL_LOCK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `pll_lock0`"] + pub type PLL_LOCK0_R = crate::R; + #[doc = "Write proxy for field `pll_lock0`"] + pub struct PLL_LOCK0_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_LOCK0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + #[doc = "Reader of field `pll_slip_clear0`"] + pub type PLL_SLIP_CLEAR0_R = crate::R; + #[doc = "Write proxy for field `pll_slip_clear0`"] + pub struct PLL_SLIP_CLEAR0_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_SLIP_CLEAR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `test_clk_out0`"] + pub type TEST_CLK_OUT0_R = crate::R; + #[doc = "Write proxy for field `test_clk_out0`"] + pub struct TEST_CLK_OUT0_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_CLK_OUT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `pll_lock1`"] + pub type PLL_LOCK1_R = crate::R; + #[doc = "Write proxy for field `pll_lock1`"] + pub struct PLL_LOCK1_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_LOCK1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); + self.w + } + } + #[doc = "Reader of field `pll_slip_clear1`"] + pub type PLL_SLIP_CLEAR1_R = crate::R; + #[doc = "Write proxy for field `pll_slip_clear1`"] + pub struct PLL_SLIP_CLEAR1_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_SLIP_CLEAR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `test_clk_out1`"] + pub type TEST_CLK_OUT1_R = crate::R; + #[doc = "Write proxy for field `test_clk_out1`"] + pub struct TEST_CLK_OUT1_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_CLK_OUT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `pll_lock2`"] + pub type PLL_LOCK2_R = crate::R; + #[doc = "Write proxy for field `pll_lock2`"] + pub struct PLL_LOCK2_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_LOCK2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16); + self.w + } + } + #[doc = "Reader of field `pll_slip_clear2`"] + pub type PLL_SLIP_CLEAR2_R = crate::R; + #[doc = "Write proxy for field `pll_slip_clear2`"] + pub struct PLL_SLIP_CLEAR2_W<'a> { + w: &'a mut W, + } + impl<'a> PLL_SLIP_CLEAR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `test_clk_out2`"] + pub type TEST_CLK_OUT2_R = crate::R; + #[doc = "Write proxy for field `test_clk_out2`"] + pub struct TEST_CLK_OUT2_W<'a> { + w: &'a mut W, + } + impl<'a> TEST_CLK_OUT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + impl R { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn pll_lock0(&self) -> PLL_LOCK0_R { + PLL_LOCK0_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pll_slip_clear0(&self) -> PLL_SLIP_CLEAR0_R { + PLL_SLIP_CLEAR0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn test_clk_out0(&self) -> TEST_CLK_OUT0_R { + TEST_CLK_OUT0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:9"] + #[inline(always)] + pub fn pll_lock1(&self) -> PLL_LOCK1_R { + PLL_LOCK1_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pll_slip_clear1(&self) -> PLL_SLIP_CLEAR1_R { + PLL_SLIP_CLEAR1_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn test_clk_out1(&self) -> TEST_CLK_OUT1_R { + TEST_CLK_OUT1_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn pll_lock2(&self) -> PLL_LOCK2_R { + PLL_LOCK2_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pll_slip_clear2(&self) -> PLL_SLIP_CLEAR2_R { + PLL_SLIP_CLEAR2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn test_clk_out2(&self) -> TEST_CLK_OUT2_R { + TEST_CLK_OUT2_R::new(((self.bits >> 19) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn pll_lock0(&mut self) -> PLL_LOCK0_W { + PLL_LOCK0_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn pll_slip_clear0(&mut self) -> PLL_SLIP_CLEAR0_W { + PLL_SLIP_CLEAR0_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn test_clk_out0(&mut self) -> TEST_CLK_OUT0_W { + TEST_CLK_OUT0_W { w: self } + } + #[doc = "Bits 8:9"] + #[inline(always)] + pub fn pll_lock1(&mut self) -> PLL_LOCK1_W { + PLL_LOCK1_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pll_slip_clear1(&mut self) -> PLL_SLIP_CLEAR1_W { + PLL_SLIP_CLEAR1_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn test_clk_out1(&mut self) -> TEST_CLK_OUT1_W { + TEST_CLK_OUT1_W { w: self } + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn pll_lock2(&mut self) -> PLL_LOCK2_W { + PLL_LOCK2_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn pll_slip_clear2(&mut self) -> PLL_SLIP_CLEAR2_W { + PLL_SLIP_CLEAR2_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn test_clk_out2(&mut self) -> TEST_CLK_OUT2_W { + TEST_CLK_OUT2_W { w: self } + } + } + } + #[doc = "AXI ROM detector\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_error](rom_error) module"] + pub type ROM_ERROR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ROM_ERROR; + #[doc = "`read()` method returns [rom_error::R](rom_error::R) reader structure"] + impl crate::Readable for ROM_ERROR {} + #[doc = "`write(|w| ..)` method takes [rom_error::W](rom_error::W) writer structure"] + impl crate::Writable for ROM_ERROR {} + #[doc = "AXI ROM detector"] + pub mod rom_error { + #[doc = "Reader of register rom_error"] + pub type R = crate::R; + #[doc = "Writer for register rom_error"] + pub type W = crate::W; + #[doc = "Register rom_error `reset()`'s with value 0"] + impl crate::ResetValue for super::ROM_ERROR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rom_mul_error`"] + pub type ROM_MUL_ERROR_R = crate::R; + #[doc = "Write proxy for field `rom_mul_error`"] + pub struct ROM_MUL_ERROR_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_MUL_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `rom_one_error`"] + pub type ROM_ONE_ERROR_R = crate::R; + #[doc = "Write proxy for field `rom_one_error`"] + pub struct ROM_ONE_ERROR_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_ONE_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_mul_error(&self) -> ROM_MUL_ERROR_R { + ROM_MUL_ERROR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn rom_one_error(&self) -> ROM_ONE_ERROR_R { + ROM_ONE_ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_mul_error(&mut self) -> ROM_MUL_ERROR_W { + ROM_MUL_ERROR_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn rom_one_error(&mut self) -> ROM_ONE_ERROR_W { + ROM_ONE_ERROR_W { w: self } + } + } + } + #[doc = "Clock select controller 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_sel0](clk_sel0) module"] + pub type CLK_SEL0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_SEL0; + #[doc = "`read()` method returns [clk_sel0::R](clk_sel0::R) reader structure"] + impl crate::Readable for CLK_SEL0 {} + #[doc = "`write(|w| ..)` method takes [clk_sel0::W](clk_sel0::W) writer structure"] + impl crate::Writable for CLK_SEL0 {} + #[doc = "Clock select controller 0"] + pub mod clk_sel0 { + #[doc = "Reader of register clk_sel0"] + pub type R = crate::R; + #[doc = "Writer for register clk_sel0"] + pub type W = crate::W; + #[doc = "Register clk_sel0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_SEL0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `aclk_sel`"] + pub type ACLK_SEL_R = crate::R; + #[doc = "Write proxy for field `aclk_sel`"] + pub struct ACLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> ACLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `aclk_divider_sel`"] + pub type ACLK_DIVIDER_SEL_R = crate::R; + #[doc = "Write proxy for field `aclk_divider_sel`"] + pub struct ACLK_DIVIDER_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> ACLK_DIVIDER_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1); + self.w + } + } + #[doc = "Reader of field `apb0_clk_sel`"] + pub type APB0_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `apb0_clk_sel`"] + pub struct APB0_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> APB0_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | (((value as u32) & 0x07) << 3); + self.w + } + } + #[doc = "Reader of field `apb1_clk_sel`"] + pub type APB1_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `apb1_clk_sel`"] + pub struct APB1_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> APB1_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 6)) | (((value as u32) & 0x07) << 6); + self.w + } + } + #[doc = "Reader of field `apb2_clk_sel`"] + pub type APB2_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `apb2_clk_sel`"] + pub struct APB2_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> APB2_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9); + self.w + } + } + #[doc = "Reader of field `spi3_clk_sel`"] + pub type SPI3_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `spi3_clk_sel`"] + pub struct SPI3_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `timer0_clk_sel`"] + pub type TIMER0_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `timer0_clk_sel`"] + pub struct TIMER0_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `timer1_clk_sel`"] + pub type TIMER1_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `timer1_clk_sel`"] + pub struct TIMER1_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `timer2_clk_sel`"] + pub type TIMER2_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `timer2_clk_sel`"] + pub struct TIMER2_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn aclk_sel(&self) -> ACLK_SEL_R { + ACLK_SEL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2"] + #[inline(always)] + pub fn aclk_divider_sel(&self) -> ACLK_DIVIDER_SEL_R { + ACLK_DIVIDER_SEL_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bits 3:5"] + #[inline(always)] + pub fn apb0_clk_sel(&self) -> APB0_CLK_SEL_R { + APB0_CLK_SEL_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:8"] + #[inline(always)] + pub fn apb1_clk_sel(&self) -> APB1_CLK_SEL_R { + APB1_CLK_SEL_R::new(((self.bits >> 6) & 0x07) as u8) + } + #[doc = "Bits 9:11"] + #[inline(always)] + pub fn apb2_clk_sel(&self) -> APB2_CLK_SEL_R { + APB2_CLK_SEL_R::new(((self.bits >> 9) & 0x07) as u8) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi3_clk_sel(&self) -> SPI3_CLK_SEL_R { + SPI3_CLK_SEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn timer0_clk_sel(&self) -> TIMER0_CLK_SEL_R { + TIMER0_CLK_SEL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn timer1_clk_sel(&self) -> TIMER1_CLK_SEL_R { + TIMER1_CLK_SEL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn timer2_clk_sel(&self) -> TIMER2_CLK_SEL_R { + TIMER2_CLK_SEL_R::new(((self.bits >> 15) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn aclk_sel(&mut self) -> ACLK_SEL_W { + ACLK_SEL_W { w: self } + } + #[doc = "Bits 1:2"] + #[inline(always)] + pub fn aclk_divider_sel(&mut self) -> ACLK_DIVIDER_SEL_W { + ACLK_DIVIDER_SEL_W { w: self } + } + #[doc = "Bits 3:5"] + #[inline(always)] + pub fn apb0_clk_sel(&mut self) -> APB0_CLK_SEL_W { + APB0_CLK_SEL_W { w: self } + } + #[doc = "Bits 6:8"] + #[inline(always)] + pub fn apb1_clk_sel(&mut self) -> APB1_CLK_SEL_W { + APB1_CLK_SEL_W { w: self } + } + #[doc = "Bits 9:11"] + #[inline(always)] + pub fn apb2_clk_sel(&mut self) -> APB2_CLK_SEL_W { + APB2_CLK_SEL_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi3_clk_sel(&mut self) -> SPI3_CLK_SEL_W { + SPI3_CLK_SEL_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn timer0_clk_sel(&mut self) -> TIMER0_CLK_SEL_W { + TIMER0_CLK_SEL_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn timer1_clk_sel(&mut self) -> TIMER1_CLK_SEL_W { + TIMER1_CLK_SEL_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn timer2_clk_sel(&mut self) -> TIMER2_CLK_SEL_W { + TIMER2_CLK_SEL_W { w: self } + } + } + } + #[doc = "Clock select controller 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_sel1](clk_sel1) module"] + pub type CLK_SEL1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_SEL1; + #[doc = "`read()` method returns [clk_sel1::R](clk_sel1::R) reader structure"] + impl crate::Readable for CLK_SEL1 {} + #[doc = "`write(|w| ..)` method takes [clk_sel1::W](clk_sel1::W) writer structure"] + impl crate::Writable for CLK_SEL1 {} + #[doc = "Clock select controller 1"] + pub mod clk_sel1 { + #[doc = "Reader of register clk_sel1"] + pub type R = crate::R; + #[doc = "Writer for register clk_sel1"] + pub type W = crate::W; + #[doc = "Register clk_sel1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_SEL1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `spi3_sample_clk_sel`"] + pub type SPI3_SAMPLE_CLK_SEL_R = crate::R; + #[doc = "Write proxy for field `spi3_sample_clk_sel`"] + pub struct SPI3_SAMPLE_CLK_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_SAMPLE_CLK_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn spi3_sample_clk_sel(&self) -> SPI3_SAMPLE_CLK_SEL_R { + SPI3_SAMPLE_CLK_SEL_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn spi3_sample_clk_sel(&mut self) -> SPI3_SAMPLE_CLK_SEL_W { + SPI3_SAMPLE_CLK_SEL_W { w: self } + } + } + } + #[doc = "Central clock enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_en_cent](clk_en_cent) module"] + pub type CLK_EN_CENT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_EN_CENT; + #[doc = "`read()` method returns [clk_en_cent::R](clk_en_cent::R) reader structure"] + impl crate::Readable for CLK_EN_CENT {} + #[doc = "`write(|w| ..)` method takes [clk_en_cent::W](clk_en_cent::W) writer structure"] + impl crate::Writable for CLK_EN_CENT {} + #[doc = "Central clock enable"] + pub mod clk_en_cent { + #[doc = "Reader of register clk_en_cent"] + pub type R = crate::R; + #[doc = "Writer for register clk_en_cent"] + pub type W = crate::W; + #[doc = "Register clk_en_cent `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_EN_CENT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `cpu_clk_en`"] + pub type CPU_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `cpu_clk_en`"] + pub struct CPU_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> CPU_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `sram0_clk_en`"] + pub type SRAM0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `sram0_clk_en`"] + pub struct SRAM0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `sram1_clk_en`"] + pub type SRAM1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `sram1_clk_en`"] + pub struct SRAM1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `apb0_clk_en`"] + pub type APB0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `apb0_clk_en`"] + pub struct APB0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> APB0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `apb1_clk_en`"] + pub type APB1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `apb1_clk_en`"] + pub struct APB1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> APB1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `apb2_clk_en`"] + pub type APB2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `apb2_clk_en`"] + pub struct APB2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> APB2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn cpu_clk_en(&self) -> CPU_CLK_EN_R { + CPU_CLK_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sram0_clk_en(&self) -> SRAM0_CLK_EN_R { + SRAM0_CLK_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sram1_clk_en(&self) -> SRAM1_CLK_EN_R { + SRAM1_CLK_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb0_clk_en(&self) -> APB0_CLK_EN_R { + APB0_CLK_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb1_clk_en(&self) -> APB1_CLK_EN_R { + APB1_CLK_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn apb2_clk_en(&self) -> APB2_CLK_EN_R { + APB2_CLK_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn cpu_clk_en(&mut self) -> CPU_CLK_EN_W { + CPU_CLK_EN_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sram0_clk_en(&mut self) -> SRAM0_CLK_EN_W { + SRAM0_CLK_EN_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sram1_clk_en(&mut self) -> SRAM1_CLK_EN_W { + SRAM1_CLK_EN_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb0_clk_en(&mut self) -> APB0_CLK_EN_W { + APB0_CLK_EN_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb1_clk_en(&mut self) -> APB1_CLK_EN_W { + APB1_CLK_EN_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn apb2_clk_en(&mut self) -> APB2_CLK_EN_W { + APB2_CLK_EN_W { w: self } + } + } + } + #[doc = "Peripheral clock enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_en_peri](clk_en_peri) module"] + pub type CLK_EN_PERI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_EN_PERI; + #[doc = "`read()` method returns [clk_en_peri::R](clk_en_peri::R) reader structure"] + impl crate::Readable for CLK_EN_PERI {} + #[doc = "`write(|w| ..)` method takes [clk_en_peri::W](clk_en_peri::W) writer structure"] + impl crate::Writable for CLK_EN_PERI {} + #[doc = "Peripheral clock enable"] + pub mod clk_en_peri { + #[doc = "Reader of register clk_en_peri"] + pub type R = crate::R; + #[doc = "Writer for register clk_en_peri"] + pub type W = crate::W; + #[doc = "Register clk_en_peri `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_EN_PERI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rom_clk_en`"] + pub type ROM_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `rom_clk_en`"] + pub struct ROM_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `dma_clk_en`"] + pub type DMA_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `dma_clk_en`"] + pub struct DMA_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ai_clk_en`"] + pub type AI_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `ai_clk_en`"] + pub struct AI_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> AI_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `dvp_clk_en`"] + pub type DVP_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `dvp_clk_en`"] + pub struct DVP_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `fft_clk_en`"] + pub type FFT_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `fft_clk_en`"] + pub struct FFT_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `gpio_clk_en`"] + pub type GPIO_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `gpio_clk_en`"] + pub struct GPIO_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> GPIO_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `spi0_clk_en`"] + pub type SPI0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi0_clk_en`"] + pub struct SPI0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `spi1_clk_en`"] + pub type SPI1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi1_clk_en`"] + pub struct SPI1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `spi2_clk_en`"] + pub type SPI2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi2_clk_en`"] + pub struct SPI2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `spi3_clk_en`"] + pub type SPI3_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `spi3_clk_en`"] + pub struct SPI3_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `i2s0_clk_en`"] + pub type I2S0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2s0_clk_en`"] + pub struct I2S0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `i2s1_clk_en`"] + pub type I2S1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2s1_clk_en`"] + pub struct I2S1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `i2s2_clk_en`"] + pub type I2S2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2s2_clk_en`"] + pub struct I2S2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `i2c0_clk_en`"] + pub type I2C0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2c0_clk_en`"] + pub struct I2C0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2C0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `i2c1_clk_en`"] + pub type I2C1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2c1_clk_en`"] + pub struct I2C1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2C1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `i2c2_clk_en`"] + pub type I2C2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `i2c2_clk_en`"] + pub struct I2C2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> I2C2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `uart1_clk_en`"] + pub type UART1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `uart1_clk_en`"] + pub struct UART1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> UART1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `uart2_clk_en`"] + pub type UART2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `uart2_clk_en`"] + pub struct UART2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> UART2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `uart3_clk_en`"] + pub type UART3_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `uart3_clk_en`"] + pub struct UART3_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> UART3_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `aes_clk_en`"] + pub type AES_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `aes_clk_en`"] + pub struct AES_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> AES_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `fpioa_clk_en`"] + pub type FPIOA_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `fpioa_clk_en`"] + pub struct FPIOA_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> FPIOA_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `timer0_clk_en`"] + pub type TIMER0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `timer0_clk_en`"] + pub struct TIMER0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `timer1_clk_en`"] + pub type TIMER1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `timer1_clk_en`"] + pub struct TIMER1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `timer2_clk_en`"] + pub type TIMER2_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `timer2_clk_en`"] + pub struct TIMER2_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `wdt0_clk_en`"] + pub type WDT0_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `wdt0_clk_en`"] + pub struct WDT0_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `wdt1_clk_en`"] + pub type WDT1_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `wdt1_clk_en`"] + pub struct WDT1_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `sha_clk_en`"] + pub type SHA_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `sha_clk_en`"] + pub struct SHA_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SHA_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); + self.w + } + } + #[doc = "Reader of field `otp_clk_en`"] + pub type OTP_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `otp_clk_en`"] + pub struct OTP_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> OTP_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27); + self.w + } + } + #[doc = "Reader of field `rtc_clk_en`"] + pub type RTC_CLK_EN_R = crate::R; + #[doc = "Write proxy for field `rtc_clk_en`"] + pub struct RTC_CLK_EN_W<'a> { + w: &'a mut W, + } + impl<'a> RTC_CLK_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_clk_en(&self) -> ROM_CLK_EN_R { + ROM_CLK_EN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_clk_en(&self) -> DMA_CLK_EN_R { + DMA_CLK_EN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_clk_en(&self) -> AI_CLK_EN_R { + AI_CLK_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_clk_en(&self) -> DVP_CLK_EN_R { + DVP_CLK_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_clk_en(&self) -> FFT_CLK_EN_R { + FFT_CLK_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_clk_en(&self) -> GPIO_CLK_EN_R { + GPIO_CLK_EN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_clk_en(&self) -> SPI0_CLK_EN_R { + SPI0_CLK_EN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_clk_en(&self) -> SPI1_CLK_EN_R { + SPI1_CLK_EN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_clk_en(&self) -> SPI2_CLK_EN_R { + SPI2_CLK_EN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_clk_en(&self) -> SPI3_CLK_EN_R { + SPI3_CLK_EN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_clk_en(&self) -> I2S0_CLK_EN_R { + I2S0_CLK_EN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_clk_en(&self) -> I2S1_CLK_EN_R { + I2S1_CLK_EN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_clk_en(&self) -> I2S2_CLK_EN_R { + I2S2_CLK_EN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_clk_en(&self) -> I2C0_CLK_EN_R { + I2C0_CLK_EN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_clk_en(&self) -> I2C1_CLK_EN_R { + I2C1_CLK_EN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_clk_en(&self) -> I2C2_CLK_EN_R { + I2C2_CLK_EN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R { + UART1_CLK_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_clk_en(&self) -> UART2_CLK_EN_R { + UART2_CLK_EN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_clk_en(&self) -> UART3_CLK_EN_R { + UART3_CLK_EN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_clk_en(&self) -> AES_CLK_EN_R { + AES_CLK_EN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_clk_en(&self) -> FPIOA_CLK_EN_R { + FPIOA_CLK_EN_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_clk_en(&self) -> TIMER0_CLK_EN_R { + TIMER0_CLK_EN_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_clk_en(&self) -> TIMER1_CLK_EN_R { + TIMER1_CLK_EN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_clk_en(&self) -> TIMER2_CLK_EN_R { + TIMER2_CLK_EN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_clk_en(&self) -> WDT0_CLK_EN_R { + WDT0_CLK_EN_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_clk_en(&self) -> WDT1_CLK_EN_R { + WDT1_CLK_EN_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_clk_en(&self) -> SHA_CLK_EN_R { + SHA_CLK_EN_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn otp_clk_en(&self) -> OTP_CLK_EN_R { + OTP_CLK_EN_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_clk_en(&self) -> RTC_CLK_EN_R { + RTC_CLK_EN_R::new(((self.bits >> 29) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_clk_en(&mut self) -> ROM_CLK_EN_W { + ROM_CLK_EN_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W { + DMA_CLK_EN_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_clk_en(&mut self) -> AI_CLK_EN_W { + AI_CLK_EN_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_clk_en(&mut self) -> DVP_CLK_EN_W { + DVP_CLK_EN_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_clk_en(&mut self) -> FFT_CLK_EN_W { + FFT_CLK_EN_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_clk_en(&mut self) -> GPIO_CLK_EN_W { + GPIO_CLK_EN_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_clk_en(&mut self) -> SPI0_CLK_EN_W { + SPI0_CLK_EN_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_clk_en(&mut self) -> SPI1_CLK_EN_W { + SPI1_CLK_EN_W { w: self } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W { + SPI2_CLK_EN_W { w: self } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W { + SPI3_CLK_EN_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W { + I2S0_CLK_EN_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W { + I2S1_CLK_EN_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_clk_en(&mut self) -> I2S2_CLK_EN_W { + I2S2_CLK_EN_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_clk_en(&mut self) -> I2C0_CLK_EN_W { + I2C0_CLK_EN_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_clk_en(&mut self) -> I2C1_CLK_EN_W { + I2C1_CLK_EN_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_clk_en(&mut self) -> I2C2_CLK_EN_W { + I2C2_CLK_EN_W { w: self } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W { + UART1_CLK_EN_W { w: self } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W { + UART2_CLK_EN_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_clk_en(&mut self) -> UART3_CLK_EN_W { + UART3_CLK_EN_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_clk_en(&mut self) -> AES_CLK_EN_W { + AES_CLK_EN_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_clk_en(&mut self) -> FPIOA_CLK_EN_W { + FPIOA_CLK_EN_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_clk_en(&mut self) -> TIMER0_CLK_EN_W { + TIMER0_CLK_EN_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_clk_en(&mut self) -> TIMER1_CLK_EN_W { + TIMER1_CLK_EN_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_clk_en(&mut self) -> TIMER2_CLK_EN_W { + TIMER2_CLK_EN_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_clk_en(&mut self) -> WDT0_CLK_EN_W { + WDT0_CLK_EN_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_clk_en(&mut self) -> WDT1_CLK_EN_W { + WDT1_CLK_EN_W { w: self } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_clk_en(&mut self) -> SHA_CLK_EN_W { + SHA_CLK_EN_W { w: self } + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn otp_clk_en(&mut self) -> OTP_CLK_EN_W { + OTP_CLK_EN_W { w: self } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_clk_en(&mut self) -> RTC_CLK_EN_W { + RTC_CLK_EN_W { w: self } + } + } + } + #[doc = "Soft reset ctrl\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [soft_reset](soft_reset) module"] + pub type SOFT_RESET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SOFT_RESET; + #[doc = "`read()` method returns [soft_reset::R](soft_reset::R) reader structure"] + impl crate::Readable for SOFT_RESET {} + #[doc = "`write(|w| ..)` method takes [soft_reset::W](soft_reset::W) writer structure"] + impl crate::Writable for SOFT_RESET {} + #[doc = "Soft reset ctrl"] + pub mod soft_reset { + #[doc = "Reader of register soft_reset"] + pub type R = crate::R; + #[doc = "Writer for register soft_reset"] + pub type W = crate::W; + #[doc = "Register soft_reset `reset()`'s with value 0"] + impl crate::ResetValue for super::SOFT_RESET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `soft_reset`"] + pub type SOFT_RESET_R = crate::R; + #[doc = "Write proxy for field `soft_reset`"] + pub struct SOFT_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SOFT_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn soft_reset(&self) -> SOFT_RESET_R { + SOFT_RESET_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn soft_reset(&mut self) -> SOFT_RESET_W { + SOFT_RESET_W { w: self } + } + } + } + #[doc = "Peripheral reset controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peri_reset](peri_reset) module"] + pub type PERI_RESET = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PERI_RESET; + #[doc = "`read()` method returns [peri_reset::R](peri_reset::R) reader structure"] + impl crate::Readable for PERI_RESET {} + #[doc = "`write(|w| ..)` method takes [peri_reset::W](peri_reset::W) writer structure"] + impl crate::Writable for PERI_RESET {} + #[doc = "Peripheral reset controller"] + pub mod peri_reset { + #[doc = "Reader of register peri_reset"] + pub type R = crate::R; + #[doc = "Writer for register peri_reset"] + pub type W = crate::W; + #[doc = "Register peri_reset `reset()`'s with value 0"] + impl crate::ResetValue for super::PERI_RESET { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `rom_reset`"] + pub type ROM_RESET_R = crate::R; + #[doc = "Write proxy for field `rom_reset`"] + pub struct ROM_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `dma_reset`"] + pub type DMA_RESET_R = crate::R; + #[doc = "Write proxy for field `dma_reset`"] + pub struct DMA_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ai_reset`"] + pub type AI_RESET_R = crate::R; + #[doc = "Write proxy for field `ai_reset`"] + pub struct AI_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> AI_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `dvp_reset`"] + pub type DVP_RESET_R = crate::R; + #[doc = "Write proxy for field `dvp_reset`"] + pub struct DVP_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `fft_reset`"] + pub type FFT_RESET_R = crate::R; + #[doc = "Write proxy for field `fft_reset`"] + pub struct FFT_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> FFT_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `gpio_reset`"] + pub type GPIO_RESET_R = crate::R; + #[doc = "Write proxy for field `gpio_reset`"] + pub struct GPIO_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> GPIO_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `spi0_reset`"] + pub type SPI0_RESET_R = crate::R; + #[doc = "Write proxy for field `spi0_reset`"] + pub struct SPI0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `spi1_reset`"] + pub type SPI1_RESET_R = crate::R; + #[doc = "Write proxy for field `spi1_reset`"] + pub struct SPI1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `spi2_reset`"] + pub type SPI2_RESET_R = crate::R; + #[doc = "Write proxy for field `spi2_reset`"] + pub struct SPI2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `spi3_reset`"] + pub type SPI3_RESET_R = crate::R; + #[doc = "Write proxy for field `spi3_reset`"] + pub struct SPI3_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `i2s0_reset`"] + pub type I2S0_RESET_R = crate::R; + #[doc = "Write proxy for field `i2s0_reset`"] + pub struct I2S0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `i2s1_reset`"] + pub type I2S1_RESET_R = crate::R; + #[doc = "Write proxy for field `i2s1_reset`"] + pub struct I2S1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `i2s2_reset`"] + pub type I2S2_RESET_R = crate::R; + #[doc = "Write proxy for field `i2s2_reset`"] + pub struct I2S2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `i2c0_reset`"] + pub type I2C0_RESET_R = crate::R; + #[doc = "Write proxy for field `i2c0_reset`"] + pub struct I2C0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2C0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `i2c1_reset`"] + pub type I2C1_RESET_R = crate::R; + #[doc = "Write proxy for field `i2c1_reset`"] + pub struct I2C1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2C1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `i2c2_reset`"] + pub type I2C2_RESET_R = crate::R; + #[doc = "Write proxy for field `i2c2_reset`"] + pub struct I2C2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> I2C2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `uart1_reset`"] + pub type UART1_RESET_R = crate::R; + #[doc = "Write proxy for field `uart1_reset`"] + pub struct UART1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> UART1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `uart2_reset`"] + pub type UART2_RESET_R = crate::R; + #[doc = "Write proxy for field `uart2_reset`"] + pub struct UART2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> UART2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `uart3_reset`"] + pub type UART3_RESET_R = crate::R; + #[doc = "Write proxy for field `uart3_reset`"] + pub struct UART3_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> UART3_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `aes_reset`"] + pub type AES_RESET_R = crate::R; + #[doc = "Write proxy for field `aes_reset`"] + pub struct AES_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> AES_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `fpioa_reset`"] + pub type FPIOA_RESET_R = crate::R; + #[doc = "Write proxy for field `fpioa_reset`"] + pub struct FPIOA_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> FPIOA_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `timer0_reset`"] + pub type TIMER0_RESET_R = crate::R; + #[doc = "Write proxy for field `timer0_reset`"] + pub struct TIMER0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `timer1_reset`"] + pub type TIMER1_RESET_R = crate::R; + #[doc = "Write proxy for field `timer1_reset`"] + pub struct TIMER1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `timer2_reset`"] + pub type TIMER2_RESET_R = crate::R; + #[doc = "Write proxy for field `timer2_reset`"] + pub struct TIMER2_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `wdt0_reset`"] + pub type WDT0_RESET_R = crate::R; + #[doc = "Write proxy for field `wdt0_reset`"] + pub struct WDT0_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + #[doc = "Reader of field `wdt1_reset`"] + pub type WDT1_RESET_R = crate::R; + #[doc = "Write proxy for field `wdt1_reset`"] + pub struct WDT1_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); + self.w + } + } + #[doc = "Reader of field `sha_reset`"] + pub type SHA_RESET_R = crate::R; + #[doc = "Write proxy for field `sha_reset`"] + pub struct SHA_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> SHA_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); + self.w + } + } + #[doc = "Reader of field `rtc_reset`"] + pub type RTC_RESET_R = crate::R; + #[doc = "Write proxy for field `rtc_reset`"] + pub struct RTC_RESET_W<'a> { + w: &'a mut W, + } + impl<'a> RTC_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_reset(&self) -> ROM_RESET_R { + ROM_RESET_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_reset(&self) -> DMA_RESET_R { + DMA_RESET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_reset(&self) -> AI_RESET_R { + AI_RESET_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_reset(&self) -> DVP_RESET_R { + DVP_RESET_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_reset(&self) -> FFT_RESET_R { + FFT_RESET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_reset(&self) -> GPIO_RESET_R { + GPIO_RESET_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_reset(&self) -> SPI0_RESET_R { + SPI0_RESET_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_reset(&self) -> SPI1_RESET_R { + SPI1_RESET_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_reset(&self) -> SPI2_RESET_R { + SPI2_RESET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_reset(&self) -> SPI3_RESET_R { + SPI3_RESET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_reset(&self) -> I2S0_RESET_R { + I2S0_RESET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_reset(&self) -> I2S1_RESET_R { + I2S1_RESET_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_reset(&self) -> I2S2_RESET_R { + I2S2_RESET_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_reset(&self) -> I2C0_RESET_R { + I2C0_RESET_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_reset(&self) -> I2C1_RESET_R { + I2C1_RESET_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_reset(&self) -> I2C2_RESET_R { + I2C2_RESET_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_reset(&self) -> UART1_RESET_R { + UART1_RESET_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_reset(&self) -> UART2_RESET_R { + UART2_RESET_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_reset(&self) -> UART3_RESET_R { + UART3_RESET_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_reset(&self) -> AES_RESET_R { + AES_RESET_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_reset(&self) -> FPIOA_RESET_R { + FPIOA_RESET_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_reset(&self) -> TIMER0_RESET_R { + TIMER0_RESET_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_reset(&self) -> TIMER1_RESET_R { + TIMER1_RESET_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_reset(&self) -> TIMER2_RESET_R { + TIMER2_RESET_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_reset(&self) -> WDT0_RESET_R { + WDT0_RESET_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_reset(&self) -> WDT1_RESET_R { + WDT1_RESET_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_reset(&self) -> SHA_RESET_R { + SHA_RESET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_reset(&self) -> RTC_RESET_R { + RTC_RESET_R::new(((self.bits >> 29) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn rom_reset(&mut self) -> ROM_RESET_W { + ROM_RESET_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dma_reset(&mut self) -> DMA_RESET_W { + DMA_RESET_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ai_reset(&mut self) -> AI_RESET_W { + AI_RESET_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dvp_reset(&mut self) -> DVP_RESET_W { + DVP_RESET_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn fft_reset(&mut self) -> FFT_RESET_W { + FFT_RESET_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_reset(&mut self) -> GPIO_RESET_W { + GPIO_RESET_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn spi0_reset(&mut self) -> SPI0_RESET_W { + SPI0_RESET_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn spi1_reset(&mut self) -> SPI1_RESET_W { + SPI1_RESET_W { w: self } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn spi2_reset(&mut self) -> SPI2_RESET_W { + SPI2_RESET_W { w: self } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn spi3_reset(&mut self) -> SPI3_RESET_W { + SPI3_RESET_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn i2s0_reset(&mut self) -> I2S0_RESET_W { + I2S0_RESET_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn i2s1_reset(&mut self) -> I2S1_RESET_W { + I2S1_RESET_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn i2s2_reset(&mut self) -> I2S2_RESET_W { + I2S2_RESET_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn i2c0_reset(&mut self) -> I2C0_RESET_W { + I2C0_RESET_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn i2c1_reset(&mut self) -> I2C1_RESET_W { + I2C1_RESET_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn i2c2_reset(&mut self) -> I2C2_RESET_W { + I2C2_RESET_W { w: self } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn uart1_reset(&mut self) -> UART1_RESET_W { + UART1_RESET_W { w: self } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn uart2_reset(&mut self) -> UART2_RESET_W { + UART2_RESET_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn uart3_reset(&mut self) -> UART3_RESET_W { + UART3_RESET_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn aes_reset(&mut self) -> AES_RESET_W { + AES_RESET_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fpioa_reset(&mut self) -> FPIOA_RESET_W { + FPIOA_RESET_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn timer0_reset(&mut self) -> TIMER0_RESET_W { + TIMER0_RESET_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn timer1_reset(&mut self) -> TIMER1_RESET_W { + TIMER1_RESET_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer2_reset(&mut self) -> TIMER2_RESET_W { + TIMER2_RESET_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn wdt0_reset(&mut self) -> WDT0_RESET_W { + WDT0_RESET_W { w: self } + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn wdt1_reset(&mut self) -> WDT1_RESET_W { + WDT1_RESET_W { w: self } + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn sha_reset(&mut self) -> SHA_RESET_W { + SHA_RESET_W { w: self } + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn rtc_reset(&mut self) -> RTC_RESET_W { + RTC_RESET_W { w: self } + } + } + } + #[doc = "Clock threshold controller 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th0](clk_th0) module"] + pub type CLK_TH0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH0; + #[doc = "`read()` method returns [clk_th0::R](clk_th0::R) reader structure"] + impl crate::Readable for CLK_TH0 {} + #[doc = "`write(|w| ..)` method takes [clk_th0::W](clk_th0::W) writer structure"] + impl crate::Writable for CLK_TH0 {} + #[doc = "Clock threshold controller 0"] + pub mod clk_th0 { + #[doc = "Reader of register clk_th0"] + pub type R = crate::R; + #[doc = "Writer for register clk_th0"] + pub type W = crate::W; + #[doc = "Register clk_th0 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `sram0_gclk`"] + pub type SRAM0_GCLK_R = crate::R; + #[doc = "Write proxy for field `sram0_gclk`"] + pub struct SRAM0_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM0_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); + self.w + } + } + #[doc = "Reader of field `sram1_gclk`"] + pub type SRAM1_GCLK_R = crate::R; + #[doc = "Write proxy for field `sram1_gclk`"] + pub struct SRAM1_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> SRAM1_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); + self.w + } + } + #[doc = "Reader of field `ai_gclk`"] + pub type AI_GCLK_R = crate::R; + #[doc = "Write proxy for field `ai_gclk`"] + pub struct AI_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> AI_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); + self.w + } + } + #[doc = "Reader of field `dvp_gclk`"] + pub type DVP_GCLK_R = crate::R; + #[doc = "Write proxy for field `dvp_gclk`"] + pub struct DVP_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12); + self.w + } + } + #[doc = "Reader of field `rom_gclk`"] + pub type ROM_GCLK_R = crate::R; + #[doc = "Write proxy for field `rom_gclk`"] + pub struct ROM_GCLK_W<'a> { + w: &'a mut W, + } + impl<'a> ROM_GCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn sram0_gclk(&self) -> SRAM0_GCLK_R { + SRAM0_GCLK_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7"] + #[inline(always)] + pub fn sram1_gclk(&self) -> SRAM1_GCLK_R { + SRAM1_GCLK_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn ai_gclk(&self) -> AI_GCLK_R { + AI_GCLK_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15"] + #[inline(always)] + pub fn dvp_gclk(&self) -> DVP_GCLK_R { + DVP_GCLK_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19"] + #[inline(always)] + pub fn rom_gclk(&self) -> ROM_GCLK_R { + ROM_GCLK_R::new(((self.bits >> 16) & 0x0f) as u8) + } + } + impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn sram0_gclk(&mut self) -> SRAM0_GCLK_W { + SRAM0_GCLK_W { w: self } + } + #[doc = "Bits 4:7"] + #[inline(always)] + pub fn sram1_gclk(&mut self) -> SRAM1_GCLK_W { + SRAM1_GCLK_W { w: self } + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn ai_gclk(&mut self) -> AI_GCLK_W { + AI_GCLK_W { w: self } + } + #[doc = "Bits 12:15"] + #[inline(always)] + pub fn dvp_gclk(&mut self) -> DVP_GCLK_W { + DVP_GCLK_W { w: self } + } + #[doc = "Bits 16:19"] + #[inline(always)] + pub fn rom_gclk(&mut self) -> ROM_GCLK_W { + ROM_GCLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th1](clk_th1) module"] + pub type CLK_TH1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH1; + #[doc = "`read()` method returns [clk_th1::R](clk_th1::R) reader structure"] + impl crate::Readable for CLK_TH1 {} + #[doc = "`write(|w| ..)` method takes [clk_th1::W](clk_th1::W) writer structure"] + impl crate::Writable for CLK_TH1 {} + #[doc = "Clock threshold controller 1"] + pub mod clk_th1 { + #[doc = "Reader of register clk_th1"] + pub type R = crate::R; + #[doc = "Writer for register clk_th1"] + pub type W = crate::W; + #[doc = "Register clk_th1 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `spi0_clk`"] + pub type SPI0_CLK_R = crate::R; + #[doc = "Write proxy for field `spi0_clk`"] + pub struct SPI0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `spi1_clk`"] + pub type SPI1_CLK_R = crate::R; + #[doc = "Write proxy for field `spi1_clk`"] + pub struct SPI1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `spi2_clk`"] + pub type SPI2_CLK_R = crate::R; + #[doc = "Write proxy for field `spi2_clk`"] + pub struct SPI2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `spi3_clk`"] + pub type SPI3_CLK_R = crate::R; + #[doc = "Write proxy for field `spi3_clk`"] + pub struct SPI3_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn spi0_clk(&self) -> SPI0_CLK_R { + SPI0_CLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn spi1_clk(&self) -> SPI1_CLK_R { + SPI1_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn spi2_clk(&self) -> SPI2_CLK_R { + SPI2_CLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn spi3_clk(&self) -> SPI3_CLK_R { + SPI3_CLK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn spi0_clk(&mut self) -> SPI0_CLK_W { + SPI0_CLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn spi1_clk(&mut self) -> SPI1_CLK_W { + SPI1_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn spi2_clk(&mut self) -> SPI2_CLK_W { + SPI2_CLK_W { w: self } + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn spi3_clk(&mut self) -> SPI3_CLK_W { + SPI3_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th2](clk_th2) module"] + pub type CLK_TH2 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH2; + #[doc = "`read()` method returns [clk_th2::R](clk_th2::R) reader structure"] + impl crate::Readable for CLK_TH2 {} + #[doc = "`write(|w| ..)` method takes [clk_th2::W](clk_th2::W) writer structure"] + impl crate::Writable for CLK_TH2 {} + #[doc = "Clock threshold controller 2"] + pub mod clk_th2 { + #[doc = "Reader of register clk_th2"] + pub type R = crate::R; + #[doc = "Writer for register clk_th2"] + pub type W = crate::W; + #[doc = "Register clk_th2 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH2 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `timer0_clk`"] + pub type TIMER0_CLK_R = crate::R; + #[doc = "Write proxy for field `timer0_clk`"] + pub struct TIMER0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `timer1_clk`"] + pub type TIMER1_CLK_R = crate::R; + #[doc = "Write proxy for field `timer1_clk`"] + pub struct TIMER1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `timer2_clk`"] + pub type TIMER2_CLK_R = crate::R; + #[doc = "Write proxy for field `timer2_clk`"] + pub struct TIMER2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn timer0_clk(&self) -> TIMER0_CLK_R { + TIMER0_CLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn timer1_clk(&self) -> TIMER1_CLK_R { + TIMER1_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn timer2_clk(&self) -> TIMER2_CLK_R { + TIMER2_CLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn timer0_clk(&mut self) -> TIMER0_CLK_W { + TIMER0_CLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn timer1_clk(&mut self) -> TIMER1_CLK_W { + TIMER1_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn timer2_clk(&mut self) -> TIMER2_CLK_W { + TIMER2_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th3](clk_th3) module"] + pub type CLK_TH3 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH3; + #[doc = "`read()` method returns [clk_th3::R](clk_th3::R) reader structure"] + impl crate::Readable for CLK_TH3 {} + #[doc = "`write(|w| ..)` method takes [clk_th3::W](clk_th3::W) writer structure"] + impl crate::Writable for CLK_TH3 {} + #[doc = "Clock threshold controller 3"] + pub mod clk_th3 { + #[doc = "Reader of register clk_th3"] + pub type R = crate::R; + #[doc = "Writer for register clk_th3"] + pub type W = crate::W; + #[doc = "Register clk_th3 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH3 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `i2s0_clk`"] + pub type I2S0_CLK_R = crate::R; + #[doc = "Write proxy for field `i2s0_clk`"] + pub struct I2S0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `i2s1_clk`"] + pub type I2S1_CLK_R = crate::R; + #[doc = "Write proxy for field `i2s1_clk`"] + pub struct I2S1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); + self.w + } + } + impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s0_clk(&self) -> I2S0_CLK_R { + I2S0_CLK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn i2s1_clk(&self) -> I2S1_CLK_R { + I2S1_CLK_R::new(((self.bits >> 16) & 0xffff) as u16) + } + } + impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s0_clk(&mut self) -> I2S0_CLK_W { + I2S0_CLK_W { w: self } + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn i2s1_clk(&mut self) -> I2S1_CLK_W { + I2S1_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th4](clk_th4) module"] + pub type CLK_TH4 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH4; + #[doc = "`read()` method returns [clk_th4::R](clk_th4::R) reader structure"] + impl crate::Readable for CLK_TH4 {} + #[doc = "`write(|w| ..)` method takes [clk_th4::W](clk_th4::W) writer structure"] + impl crate::Writable for CLK_TH4 {} + #[doc = "Clock threshold controller 4"] + pub mod clk_th4 { + #[doc = "Reader of register clk_th4"] + pub type R = crate::R; + #[doc = "Writer for register clk_th4"] + pub type W = crate::W; + #[doc = "Register clk_th4 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH4 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `i2s2_clk`"] + pub type I2S2_CLK_R = crate::R; + #[doc = "Write proxy for field `i2s2_clk`"] + pub struct I2S2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff); + self.w + } + } + #[doc = "Reader of field `i2s0_mclk`"] + pub type I2S0_MCLK_R = crate::R; + #[doc = "Write proxy for field `i2s0_mclk`"] + pub struct I2S0_MCLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_MCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `i2s1_mclk`"] + pub type I2S1_MCLK_R = crate::R; + #[doc = "Write proxy for field `i2s1_mclk`"] + pub struct I2S1_MCLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_MCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s2_clk(&self) -> I2S2_CLK_R { + I2S2_CLK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2s0_mclk(&self) -> I2S0_MCLK_R { + I2S0_MCLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2s1_mclk(&self) -> I2S1_MCLK_R { + I2S1_MCLK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn i2s2_clk(&mut self) -> I2S2_CLK_W { + I2S2_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2s0_mclk(&mut self) -> I2S0_MCLK_W { + I2S0_MCLK_W { w: self } + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2s1_mclk(&mut self) -> I2S1_MCLK_W { + I2S1_MCLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th5](clk_th5) module"] + pub type CLK_TH5 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH5; + #[doc = "`read()` method returns [clk_th5::R](clk_th5::R) reader structure"] + impl crate::Readable for CLK_TH5 {} + #[doc = "`write(|w| ..)` method takes [clk_th5::W](clk_th5::W) writer structure"] + impl crate::Writable for CLK_TH5 {} + #[doc = "Clock threshold controller 5"] + pub mod clk_th5 { + #[doc = "Reader of register clk_th5"] + pub type R = crate::R; + #[doc = "Writer for register clk_th5"] + pub type W = crate::W; + #[doc = "Register clk_th5 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH5 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `i2s2_mclk`"] + pub type I2S2_MCLK_R = crate::R; + #[doc = "Write proxy for field `i2s2_mclk`"] + pub struct I2S2_MCLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_MCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `i2c0_clk`"] + pub type I2C0_CLK_R = crate::R; + #[doc = "Write proxy for field `i2c0_clk`"] + pub struct I2C0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2C0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + #[doc = "Reader of field `i2c1_clk`"] + pub type I2C1_CLK_R = crate::R; + #[doc = "Write proxy for field `i2c1_clk`"] + pub struct I2C1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2C1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); + self.w + } + } + #[doc = "Reader of field `i2c2_clk`"] + pub type I2C2_CLK_R = crate::R; + #[doc = "Write proxy for field `i2c2_clk`"] + pub struct I2C2_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> I2C2_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn i2s2_mclk(&self) -> I2S2_MCLK_R { + I2S2_MCLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn i2c0_clk(&self) -> I2C0_CLK_R { + I2C0_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2c1_clk(&self) -> I2C1_CLK_R { + I2C1_CLK_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2c2_clk(&self) -> I2C2_CLK_R { + I2C2_CLK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn i2s2_mclk(&mut self) -> I2S2_MCLK_W { + I2S2_MCLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn i2c0_clk(&mut self) -> I2C0_CLK_W { + I2C0_CLK_W { w: self } + } + #[doc = "Bits 16:23"] + #[inline(always)] + pub fn i2c1_clk(&mut self) -> I2C1_CLK_W { + I2C1_CLK_W { w: self } + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn i2c2_clk(&mut self) -> I2C2_CLK_W { + I2C2_CLK_W { w: self } + } + } + } + #[doc = "Clock threshold controller 6\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_th6](clk_th6) module"] + pub type CLK_TH6 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CLK_TH6; + #[doc = "`read()` method returns [clk_th6::R](clk_th6::R) reader structure"] + impl crate::Readable for CLK_TH6 {} + #[doc = "`write(|w| ..)` method takes [clk_th6::W](clk_th6::W) writer structure"] + impl crate::Writable for CLK_TH6 {} + #[doc = "Clock threshold controller 6"] + pub mod clk_th6 { + #[doc = "Reader of register clk_th6"] + pub type R = crate::R; + #[doc = "Writer for register clk_th6"] + pub type W = crate::W; + #[doc = "Register clk_th6 `reset()`'s with value 0"] + impl crate::ResetValue for super::CLK_TH6 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `wdt0_clk`"] + pub type WDT0_CLK_R = crate::R; + #[doc = "Write proxy for field `wdt0_clk`"] + pub struct WDT0_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); + self.w + } + } + #[doc = "Reader of field `wdt1_clk`"] + pub type WDT1_CLK_R = crate::R; + #[doc = "Write proxy for field `wdt1_clk`"] + pub struct WDT1_CLK_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_CLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); + self.w + } + } + impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn wdt0_clk(&self) -> WDT0_CLK_R { + WDT0_CLK_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn wdt1_clk(&self) -> WDT1_CLK_R { + WDT1_CLK_R::new(((self.bits >> 8) & 0xff) as u8) + } + } + impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn wdt0_clk(&mut self) -> WDT0_CLK_W { + WDT0_CLK_W { w: self } + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn wdt1_clk(&mut self) -> WDT1_CLK_W { + WDT1_CLK_W { w: self } + } + } + } + #[doc = "Miscellaneous controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [misc](misc) module"] + pub type MISC = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MISC; + #[doc = "`read()` method returns [misc::R](misc::R) reader structure"] + impl crate::Readable for MISC {} + #[doc = "`write(|w| ..)` method takes [misc::W](misc::W) writer structure"] + impl crate::Writable for MISC {} + #[doc = "Miscellaneous controller"] + pub mod misc { + #[doc = "Reader of register misc"] + pub type R = crate::R; + #[doc = "Writer for register misc"] + pub type W = crate::W; + #[doc = "Register misc `reset()`'s with value 0"] + impl crate::ResetValue for super::MISC { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `debug_sel`"] + pub type DEBUG_SEL_R = crate::R; + #[doc = "Write proxy for field `debug_sel`"] + pub struct DEBUG_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> DEBUG_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f); + self.w + } + } + #[doc = "Reader of field `spi_dvp_data_enable`"] + pub type SPI_DVP_DATA_ENABLE_R = crate::R; + #[doc = "Write proxy for field `spi_dvp_data_enable`"] + pub struct SPI_DVP_DATA_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> SPI_DVP_DATA_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn debug_sel(&self) -> DEBUG_SEL_R { + DEBUG_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn spi_dvp_data_enable(&self) -> SPI_DVP_DATA_ENABLE_R { + SPI_DVP_DATA_ENABLE_R::new(((self.bits >> 10) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn debug_sel(&mut self) -> DEBUG_SEL_W { + DEBUG_SEL_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn spi_dvp_data_enable(&mut self) -> SPI_DVP_DATA_ENABLE_W { + SPI_DVP_DATA_ENABLE_W { w: self } + } + } + } + #[doc = "Peripheral controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peri](peri) module"] + pub type PERI = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PERI; + #[doc = "`read()` method returns [peri::R](peri::R) reader structure"] + impl crate::Readable for PERI {} + #[doc = "`write(|w| ..)` method takes [peri::W](peri::W) writer structure"] + impl crate::Writable for PERI {} + #[doc = "Peripheral controller"] + pub mod peri { + #[doc = "Reader of register peri"] + pub type R = crate::R; + #[doc = "Writer for register peri"] + pub type W = crate::W; + #[doc = "Register peri `reset()`'s with value 0"] + impl crate::ResetValue for super::PERI { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `timer0_pause`"] + pub type TIMER0_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer0_pause`"] + pub struct TIMER0_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER0_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `timer1_pause`"] + pub type TIMER1_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer1_pause`"] + pub struct TIMER1_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER1_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `timer2_pause`"] + pub type TIMER2_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer2_pause`"] + pub struct TIMER2_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER2_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `timer3_pause`"] + pub type TIMER3_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer3_pause`"] + pub struct TIMER3_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER3_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `timer4_pause`"] + pub type TIMER4_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer4_pause`"] + pub struct TIMER4_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER4_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `timer5_pause`"] + pub type TIMER5_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer5_pause`"] + pub struct TIMER5_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER5_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `timer6_pause`"] + pub type TIMER6_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer6_pause`"] + pub struct TIMER6_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER6_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `timer7_pause`"] + pub type TIMER7_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer7_pause`"] + pub struct TIMER7_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER7_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Reader of field `timer8_pause`"] + pub type TIMER8_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer8_pause`"] + pub struct TIMER8_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER8_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); + self.w + } + } + #[doc = "Reader of field `timer9_pause`"] + pub type TIMER9_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer9_pause`"] + pub struct TIMER9_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER9_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + #[doc = "Reader of field `timer10_pause`"] + pub type TIMER10_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer10_pause`"] + pub struct TIMER10_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER10_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); + self.w + } + } + #[doc = "Reader of field `timer11_pause`"] + pub type TIMER11_PAUSE_R = crate::R; + #[doc = "Write proxy for field `timer11_pause`"] + pub struct TIMER11_PAUSE_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER11_PAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); + self.w + } + } + #[doc = "Reader of field `spi0_xip_en`"] + pub type SPI0_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi0_xip_en`"] + pub struct SPI0_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); + self.w + } + } + #[doc = "Reader of field `spi1_xip_en`"] + pub type SPI1_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi1_xip_en`"] + pub struct SPI1_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); + self.w + } + } + #[doc = "Reader of field `spi2_xip_en`"] + pub type SPI2_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi2_xip_en`"] + pub struct SPI2_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); + self.w + } + } + #[doc = "Reader of field `spi3_xip_en`"] + pub type SPI3_XIP_EN_R = crate::R; + #[doc = "Write proxy for field `spi3_xip_en`"] + pub struct SPI3_XIP_EN_W<'a> { + w: &'a mut W, + } + impl<'a> SPI3_XIP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); + self.w + } + } + #[doc = "Reader of field `spi0_clk_bypass`"] + pub type SPI0_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `spi0_clk_bypass`"] + pub struct SPI0_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> SPI0_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); + self.w + } + } + #[doc = "Reader of field `spi1_clk_bypass`"] + pub type SPI1_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `spi1_clk_bypass`"] + pub struct SPI1_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> SPI1_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); + self.w + } + } + #[doc = "Reader of field `spi2_clk_bypass`"] + pub type SPI2_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `spi2_clk_bypass`"] + pub struct SPI2_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> SPI2_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); + self.w + } + } + #[doc = "Reader of field `i2s0_clk_bypass`"] + pub type I2S0_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `i2s0_clk_bypass`"] + pub struct I2S0_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> I2S0_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); + self.w + } + } + #[doc = "Reader of field `i2s1_clk_bypass`"] + pub type I2S1_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `i2s1_clk_bypass`"] + pub struct I2S1_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> I2S1_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); + self.w + } + } + #[doc = "Reader of field `i2s2_clk_bypass`"] + pub type I2S2_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `i2s2_clk_bypass`"] + pub struct I2S2_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> I2S2_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); + self.w + } + } + #[doc = "Reader of field `jtag_clk_bypass`"] + pub type JTAG_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `jtag_clk_bypass`"] + pub struct JTAG_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> JTAG_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); + self.w + } + } + #[doc = "Reader of field `dvp_clk_bypass`"] + pub type DVP_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `dvp_clk_bypass`"] + pub struct DVP_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> DVP_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); + self.w + } + } + #[doc = "Reader of field `debug_clk_bypass`"] + pub type DEBUG_CLK_BYPASS_R = crate::R; + #[doc = "Write proxy for field `debug_clk_bypass`"] + pub struct DEBUG_CLK_BYPASS_W<'a> { + w: &'a mut W, + } + impl<'a> DEBUG_CLK_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn timer0_pause(&self) -> TIMER0_PAUSE_R { + TIMER0_PAUSE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer1_pause(&self) -> TIMER1_PAUSE_R { + TIMER1_PAUSE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn timer2_pause(&self) -> TIMER2_PAUSE_R { + TIMER2_PAUSE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn timer3_pause(&self) -> TIMER3_PAUSE_R { + TIMER3_PAUSE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn timer4_pause(&self) -> TIMER4_PAUSE_R { + TIMER4_PAUSE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn timer5_pause(&self) -> TIMER5_PAUSE_R { + TIMER5_PAUSE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn timer6_pause(&self) -> TIMER6_PAUSE_R { + TIMER6_PAUSE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn timer7_pause(&self) -> TIMER7_PAUSE_R { + TIMER7_PAUSE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn timer8_pause(&self) -> TIMER8_PAUSE_R { + TIMER8_PAUSE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn timer9_pause(&self) -> TIMER9_PAUSE_R { + TIMER9_PAUSE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn timer10_pause(&self) -> TIMER10_PAUSE_R { + TIMER10_PAUSE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn timer11_pause(&self) -> TIMER11_PAUSE_R { + TIMER11_PAUSE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi0_xip_en(&self) -> SPI0_XIP_EN_R { + SPI0_XIP_EN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn spi1_xip_en(&self) -> SPI1_XIP_EN_R { + SPI1_XIP_EN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn spi2_xip_en(&self) -> SPI2_XIP_EN_R { + SPI2_XIP_EN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn spi3_xip_en(&self) -> SPI3_XIP_EN_R { + SPI3_XIP_EN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn spi0_clk_bypass(&self) -> SPI0_CLK_BYPASS_R { + SPI0_CLK_BYPASS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn spi1_clk_bypass(&self) -> SPI1_CLK_BYPASS_R { + SPI1_CLK_BYPASS_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi2_clk_bypass(&self) -> SPI2_CLK_BYPASS_R { + SPI2_CLK_BYPASS_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn i2s0_clk_bypass(&self) -> I2S0_CLK_BYPASS_R { + I2S0_CLK_BYPASS_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn i2s1_clk_bypass(&self) -> I2S1_CLK_BYPASS_R { + I2S1_CLK_BYPASS_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn i2s2_clk_bypass(&self) -> I2S2_CLK_BYPASS_R { + I2S2_CLK_BYPASS_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn jtag_clk_bypass(&self) -> JTAG_CLK_BYPASS_R { + JTAG_CLK_BYPASS_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn dvp_clk_bypass(&self) -> DVP_CLK_BYPASS_R { + DVP_CLK_BYPASS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn debug_clk_bypass(&self) -> DEBUG_CLK_BYPASS_R { + DEBUG_CLK_BYPASS_R::new(((self.bits >> 24) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn timer0_pause(&mut self) -> TIMER0_PAUSE_W { + TIMER0_PAUSE_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer1_pause(&mut self) -> TIMER1_PAUSE_W { + TIMER1_PAUSE_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn timer2_pause(&mut self) -> TIMER2_PAUSE_W { + TIMER2_PAUSE_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn timer3_pause(&mut self) -> TIMER3_PAUSE_W { + TIMER3_PAUSE_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn timer4_pause(&mut self) -> TIMER4_PAUSE_W { + TIMER4_PAUSE_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn timer5_pause(&mut self) -> TIMER5_PAUSE_W { + TIMER5_PAUSE_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn timer6_pause(&mut self) -> TIMER6_PAUSE_W { + TIMER6_PAUSE_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn timer7_pause(&mut self) -> TIMER7_PAUSE_W { + TIMER7_PAUSE_W { w: self } + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn timer8_pause(&mut self) -> TIMER8_PAUSE_W { + TIMER8_PAUSE_W { w: self } + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn timer9_pause(&mut self) -> TIMER9_PAUSE_W { + TIMER9_PAUSE_W { w: self } + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn timer10_pause(&mut self) -> TIMER10_PAUSE_W { + TIMER10_PAUSE_W { w: self } + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn timer11_pause(&mut self) -> TIMER11_PAUSE_W { + TIMER11_PAUSE_W { w: self } + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn spi0_xip_en(&mut self) -> SPI0_XIP_EN_W { + SPI0_XIP_EN_W { w: self } + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn spi1_xip_en(&mut self) -> SPI1_XIP_EN_W { + SPI1_XIP_EN_W { w: self } + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn spi2_xip_en(&mut self) -> SPI2_XIP_EN_W { + SPI2_XIP_EN_W { w: self } + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn spi3_xip_en(&mut self) -> SPI3_XIP_EN_W { + SPI3_XIP_EN_W { w: self } + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn spi0_clk_bypass(&mut self) -> SPI0_CLK_BYPASS_W { + SPI0_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn spi1_clk_bypass(&mut self) -> SPI1_CLK_BYPASS_W { + SPI1_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi2_clk_bypass(&mut self) -> SPI2_CLK_BYPASS_W { + SPI2_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn i2s0_clk_bypass(&mut self) -> I2S0_CLK_BYPASS_W { + I2S0_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn i2s1_clk_bypass(&mut self) -> I2S1_CLK_BYPASS_W { + I2S1_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn i2s2_clk_bypass(&mut self) -> I2S2_CLK_BYPASS_W { + I2S2_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn jtag_clk_bypass(&mut self) -> JTAG_CLK_BYPASS_W { + JTAG_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn dvp_clk_bypass(&mut self) -> DVP_CLK_BYPASS_W { + DVP_CLK_BYPASS_W { w: self } + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn debug_clk_bypass(&mut self) -> DEBUG_CLK_BYPASS_W { + DEBUG_CLK_BYPASS_W { w: self } + } + } + } + #[doc = "SPI sleep controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_sleep](spi_sleep) module"] + pub type SPI_SLEEP = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _SPI_SLEEP; + #[doc = "`read()` method returns [spi_sleep::R](spi_sleep::R) reader structure"] + impl crate::Readable for SPI_SLEEP {} + #[doc = "`write(|w| ..)` method takes [spi_sleep::W](spi_sleep::W) writer structure"] + impl crate::Writable for SPI_SLEEP {} + #[doc = "SPI sleep controller"] + pub mod spi_sleep { + #[doc = "Reader of register spi_sleep"] + pub type R = crate::R; + #[doc = "Writer for register spi_sleep"] + pub type W = crate::W; + #[doc = "Register spi_sleep `reset()`'s with value 0"] + impl crate::ResetValue for super::SPI_SLEEP { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `ssi0_sleep`"] + pub type SSI0_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi0_sleep`"] + pub struct SSI0_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI0_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `ssi1_sleep`"] + pub type SSI1_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi1_sleep`"] + pub struct SSI1_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI1_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `ssi2_sleep`"] + pub type SSI2_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi2_sleep`"] + pub struct SSI2_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI2_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `ssi3_sleep`"] + pub type SSI3_SLEEP_R = crate::R; + #[doc = "Write proxy for field `ssi3_sleep`"] + pub struct SSI3_SLEEP_W<'a> { + w: &'a mut W, + } + impl<'a> SSI3_SLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ssi0_sleep(&self) -> SSI0_SLEEP_R { + SSI0_SLEEP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ssi1_sleep(&self) -> SSI1_SLEEP_R { + SSI1_SLEEP_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ssi2_sleep(&self) -> SSI2_SLEEP_R { + SSI2_SLEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ssi3_sleep(&self) -> SSI3_SLEEP_R { + SSI3_SLEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ssi0_sleep(&mut self) -> SSI0_SLEEP_W { + SSI0_SLEEP_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ssi1_sleep(&mut self) -> SSI1_SLEEP_W { + SSI1_SLEEP_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ssi2_sleep(&mut self) -> SSI2_SLEEP_W { + SSI2_SLEEP_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ssi3_sleep(&mut self) -> SSI3_SLEEP_W { + SSI3_SLEEP_W { w: self } + } + } + } + #[doc = "Reset source status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reset_status](reset_status) module"] + pub type RESET_STATUS = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _RESET_STATUS; + #[doc = "`read()` method returns [reset_status::R](reset_status::R) reader structure"] + impl crate::Readable for RESET_STATUS {} + #[doc = "`write(|w| ..)` method takes [reset_status::W](reset_status::W) writer structure"] + impl crate::Writable for RESET_STATUS {} + #[doc = "Reset source status"] + pub mod reset_status { + #[doc = "Reader of register reset_status"] + pub type R = crate::R; + #[doc = "Writer for register reset_status"] + pub type W = crate::W; + #[doc = "Register reset_status `reset()`'s with value 0"] + impl crate::ResetValue for super::RESET_STATUS { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `reset_sts_clr`"] + pub type RESET_STS_CLR_R = crate::R; + #[doc = "Write proxy for field `reset_sts_clr`"] + pub struct RESET_STS_CLR_W<'a> { + w: &'a mut W, + } + impl<'a> RESET_STS_CLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `pin_reset_sts`"] + pub type PIN_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `pin_reset_sts`"] + pub struct PIN_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> PIN_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `wdt0_reset_sts`"] + pub type WDT0_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `wdt0_reset_sts`"] + pub struct WDT0_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> WDT0_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `wdt1_reset_sts`"] + pub type WDT1_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `wdt1_reset_sts`"] + pub struct WDT1_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> WDT1_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `soft_reset_sts`"] + pub type SOFT_RESET_STS_R = crate::R; + #[doc = "Write proxy for field `soft_reset_sts`"] + pub struct SOFT_RESET_STS_W<'a> { + w: &'a mut W, + } + impl<'a> SOFT_RESET_STS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn reset_sts_clr(&self) -> RESET_STS_CLR_R { + RESET_STS_CLR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin_reset_sts(&self) -> PIN_RESET_STS_R { + PIN_RESET_STS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn wdt0_reset_sts(&self) -> WDT0_RESET_STS_R { + WDT0_RESET_STS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn wdt1_reset_sts(&self) -> WDT1_RESET_STS_R { + WDT1_RESET_STS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn soft_reset_sts(&self) -> SOFT_RESET_STS_R { + SOFT_RESET_STS_R::new(((self.bits >> 4) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn reset_sts_clr(&mut self) -> RESET_STS_CLR_W { + RESET_STS_CLR_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn pin_reset_sts(&mut self) -> PIN_RESET_STS_W { + PIN_RESET_STS_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn wdt0_reset_sts(&mut self) -> WDT0_RESET_STS_W { + WDT0_RESET_STS_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn wdt1_reset_sts(&mut self) -> WDT1_RESET_STS_W { + WDT1_RESET_STS_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn soft_reset_sts(&mut self) -> SOFT_RESET_STS_W { + SOFT_RESET_STS_W { w: self } + } + } + } + #[doc = "DMA handshake selector\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sel0](dma_sel0) module"] + pub type DMA_SEL0 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_SEL0; + #[doc = "`read()` method returns [dma_sel0::R](dma_sel0::R) reader structure"] + impl crate::Readable for DMA_SEL0 {} + #[doc = "`write(|w| ..)` method takes [dma_sel0::W](dma_sel0::W) writer structure"] + impl crate::Writable for DMA_SEL0 {} + #[doc = "DMA handshake selector"] + pub mod dma_sel0 { + #[doc = "Reader of register dma_sel0"] + pub type R = crate::R; + #[doc = "Writer for register dma_sel0"] + pub type W = crate::W; + #[doc = "Register dma_sel0 `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_SEL0 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum DMA_SEL0_A { + #[doc = "0: `0`"] + SSI0_RX_REQ = 0, + #[doc = "1: `1`"] + SSI0_TX_REQ = 1, + #[doc = "2: `10`"] + SSI1_RX_REQ = 2, + #[doc = "3: `11`"] + SSI1_TX_REQ = 3, + #[doc = "4: `100`"] + SSI2_RX_REQ = 4, + #[doc = "5: `101`"] + SSI2_TX_REQ = 5, + #[doc = "6: `110`"] + SSI3_RX_REQ = 6, + #[doc = "7: `111`"] + SSI3_TX_REQ = 7, + #[doc = "8: `1000`"] + I2C0_RX_REQ = 8, + #[doc = "9: `1001`"] + I2C0_TX_REQ = 9, + #[doc = "10: `1010`"] + I2C1_RX_REQ = 10, + #[doc = "11: `1011`"] + I2C1_TX_REQ = 11, + #[doc = "12: `1100`"] + I2C2_RX_REQ = 12, + #[doc = "13: `1101`"] + I2C2_TX_REQ = 13, + #[doc = "14: `1110`"] + UART1_RX_REQ = 14, + #[doc = "15: `1111`"] + UART1_TX_REQ = 15, + #[doc = "16: `10000`"] + UART2_RX_REQ = 16, + #[doc = "17: `10001`"] + UART2_TX_REQ = 17, + #[doc = "18: `10010`"] + UART3_RX_REQ = 18, + #[doc = "19: `10011`"] + UART3_TX_REQ = 19, + #[doc = "20: `10100`"] + AES_REQ = 20, + #[doc = "21: `10101`"] + SHA_RX_REQ = 21, + #[doc = "22: `10110`"] + AI_RX_REQ = 22, + #[doc = "23: `10111`"] + FFT_RX_REQ = 23, + #[doc = "24: `11000`"] + FFT_TX_REQ = 24, + #[doc = "25: `11001`"] + I2S0_TX_REQ = 25, + #[doc = "26: `11010`"] + I2S0_RX_REQ = 26, + #[doc = "27: `11011`"] + I2S1_TX_REQ = 27, + #[doc = "28: `11100`"] + I2S1_RX_REQ = 28, + #[doc = "29: `11101`"] + I2S2_TX_REQ = 29, + #[doc = "30: `11110`"] + I2S2_RX_REQ = 30, + #[doc = "31: `11111`"] + I2S0_BF_DIR_REQ = 31, + #[doc = "32: `100000`"] + I2S0_BF_VOICE_REQ = 32, + } + impl From for u8 { + #[inline(always)] + fn from(variant: DMA_SEL0_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `dma_sel0`"] + pub type DMA_SEL0_R = crate::R; + impl DMA_SEL0_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(DMA_SEL0_A::SSI0_RX_REQ), + 1 => Val(DMA_SEL0_A::SSI0_TX_REQ), + 2 => Val(DMA_SEL0_A::SSI1_RX_REQ), + 3 => Val(DMA_SEL0_A::SSI1_TX_REQ), + 4 => Val(DMA_SEL0_A::SSI2_RX_REQ), + 5 => Val(DMA_SEL0_A::SSI2_TX_REQ), + 6 => Val(DMA_SEL0_A::SSI3_RX_REQ), + 7 => Val(DMA_SEL0_A::SSI3_TX_REQ), + 8 => Val(DMA_SEL0_A::I2C0_RX_REQ), + 9 => Val(DMA_SEL0_A::I2C0_TX_REQ), + 10 => Val(DMA_SEL0_A::I2C1_RX_REQ), + 11 => Val(DMA_SEL0_A::I2C1_TX_REQ), + 12 => Val(DMA_SEL0_A::I2C2_RX_REQ), + 13 => Val(DMA_SEL0_A::I2C2_TX_REQ), + 14 => Val(DMA_SEL0_A::UART1_RX_REQ), + 15 => Val(DMA_SEL0_A::UART1_TX_REQ), + 16 => Val(DMA_SEL0_A::UART2_RX_REQ), + 17 => Val(DMA_SEL0_A::UART2_TX_REQ), + 18 => Val(DMA_SEL0_A::UART3_RX_REQ), + 19 => Val(DMA_SEL0_A::UART3_TX_REQ), + 20 => Val(DMA_SEL0_A::AES_REQ), + 21 => Val(DMA_SEL0_A::SHA_RX_REQ), + 22 => Val(DMA_SEL0_A::AI_RX_REQ), + 23 => Val(DMA_SEL0_A::FFT_RX_REQ), + 24 => Val(DMA_SEL0_A::FFT_TX_REQ), + 25 => Val(DMA_SEL0_A::I2S0_TX_REQ), + 26 => Val(DMA_SEL0_A::I2S0_RX_REQ), + 27 => Val(DMA_SEL0_A::I2S1_TX_REQ), + 28 => Val(DMA_SEL0_A::I2S1_RX_REQ), + 29 => Val(DMA_SEL0_A::I2S2_TX_REQ), + 30 => Val(DMA_SEL0_A::I2S2_RX_REQ), + 31 => Val(DMA_SEL0_A::I2S0_BF_DIR_REQ), + 32 => Val(DMA_SEL0_A::I2S0_BF_VOICE_REQ), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `SSI0_RX_REQ`"] + #[inline(always)] + pub fn is_ssi0_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI0_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI0_TX_REQ`"] + #[inline(always)] + pub fn is_ssi0_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI0_TX_REQ + } + #[doc = "Checks if the value of the field is `SSI1_RX_REQ`"] + #[inline(always)] + pub fn is_ssi1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI1_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI1_TX_REQ`"] + #[inline(always)] + pub fn is_ssi1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI1_TX_REQ + } + #[doc = "Checks if the value of the field is `SSI2_RX_REQ`"] + #[inline(always)] + pub fn is_ssi2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI2_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI2_TX_REQ`"] + #[inline(always)] + pub fn is_ssi2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI2_TX_REQ + } + #[doc = "Checks if the value of the field is `SSI3_RX_REQ`"] + #[inline(always)] + pub fn is_ssi3_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI3_RX_REQ + } + #[doc = "Checks if the value of the field is `SSI3_TX_REQ`"] + #[inline(always)] + pub fn is_ssi3_tx_req(&self) -> bool { + *self == DMA_SEL0_A::SSI3_TX_REQ + } + #[doc = "Checks if the value of the field is `I2C0_RX_REQ`"] + #[inline(always)] + pub fn is_i2c0_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C0_RX_REQ + } + #[doc = "Checks if the value of the field is `I2C0_TX_REQ`"] + #[inline(always)] + pub fn is_i2c0_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C0_TX_REQ + } + #[doc = "Checks if the value of the field is `I2C1_RX_REQ`"] + #[inline(always)] + pub fn is_i2c1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C1_RX_REQ + } + #[doc = "Checks if the value of the field is `I2C1_TX_REQ`"] + #[inline(always)] + pub fn is_i2c1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C1_TX_REQ + } + #[doc = "Checks if the value of the field is `I2C2_RX_REQ`"] + #[inline(always)] + pub fn is_i2c2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C2_RX_REQ + } + #[doc = "Checks if the value of the field is `I2C2_TX_REQ`"] + #[inline(always)] + pub fn is_i2c2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2C2_TX_REQ + } + #[doc = "Checks if the value of the field is `UART1_RX_REQ`"] + #[inline(always)] + pub fn is_uart1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::UART1_RX_REQ + } + #[doc = "Checks if the value of the field is `UART1_TX_REQ`"] + #[inline(always)] + pub fn is_uart1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::UART1_TX_REQ + } + #[doc = "Checks if the value of the field is `UART2_RX_REQ`"] + #[inline(always)] + pub fn is_uart2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::UART2_RX_REQ + } + #[doc = "Checks if the value of the field is `UART2_TX_REQ`"] + #[inline(always)] + pub fn is_uart2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::UART2_TX_REQ + } + #[doc = "Checks if the value of the field is `UART3_RX_REQ`"] + #[inline(always)] + pub fn is_uart3_rx_req(&self) -> bool { + *self == DMA_SEL0_A::UART3_RX_REQ + } + #[doc = "Checks if the value of the field is `UART3_TX_REQ`"] + #[inline(always)] + pub fn is_uart3_tx_req(&self) -> bool { + *self == DMA_SEL0_A::UART3_TX_REQ + } + #[doc = "Checks if the value of the field is `AES_REQ`"] + #[inline(always)] + pub fn is_aes_req(&self) -> bool { + *self == DMA_SEL0_A::AES_REQ + } + #[doc = "Checks if the value of the field is `SHA_RX_REQ`"] + #[inline(always)] + pub fn is_sha_rx_req(&self) -> bool { + *self == DMA_SEL0_A::SHA_RX_REQ + } + #[doc = "Checks if the value of the field is `AI_RX_REQ`"] + #[inline(always)] + pub fn is_ai_rx_req(&self) -> bool { + *self == DMA_SEL0_A::AI_RX_REQ + } + #[doc = "Checks if the value of the field is `FFT_RX_REQ`"] + #[inline(always)] + pub fn is_fft_rx_req(&self) -> bool { + *self == DMA_SEL0_A::FFT_RX_REQ + } + #[doc = "Checks if the value of the field is `FFT_TX_REQ`"] + #[inline(always)] + pub fn is_fft_tx_req(&self) -> bool { + *self == DMA_SEL0_A::FFT_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S0_TX_REQ`"] + #[inline(always)] + pub fn is_i2s0_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S0_RX_REQ`"] + #[inline(always)] + pub fn is_i2s0_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_RX_REQ + } + #[doc = "Checks if the value of the field is `I2S1_TX_REQ`"] + #[inline(always)] + pub fn is_i2s1_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S1_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S1_RX_REQ`"] + #[inline(always)] + pub fn is_i2s1_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S1_RX_REQ + } + #[doc = "Checks if the value of the field is `I2S2_TX_REQ`"] + #[inline(always)] + pub fn is_i2s2_tx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S2_TX_REQ + } + #[doc = "Checks if the value of the field is `I2S2_RX_REQ`"] + #[inline(always)] + pub fn is_i2s2_rx_req(&self) -> bool { + *self == DMA_SEL0_A::I2S2_RX_REQ + } + #[doc = "Checks if the value of the field is `I2S0_BF_DIR_REQ`"] + #[inline(always)] + pub fn is_i2s0_bf_dir_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_BF_DIR_REQ + } + #[doc = "Checks if the value of the field is `I2S0_BF_VOICE_REQ`"] + #[inline(always)] + pub fn is_i2s0_bf_voice_req(&self) -> bool { + *self == DMA_SEL0_A::I2S0_BF_VOICE_REQ + } + } + #[doc = "Write proxy for field `dma_sel0`"] + pub struct DMA_SEL0_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL0_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f); + self.w + } + } + #[doc = ""] + pub type DMA_SEL1_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel1`"] + pub type DMA_SEL1_R = crate::R; + #[doc = "Write proxy for field `dma_sel1`"] + pub struct DMA_SEL1_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL1_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | (((value as u32) & 0x3f) << 6); + self.w + } + } + #[doc = ""] + pub type DMA_SEL2_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel2`"] + pub type DMA_SEL2_R = crate::R; + #[doc = "Write proxy for field `dma_sel2`"] + pub struct DMA_SEL2_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL2_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 12)) | (((value as u32) & 0x3f) << 12); + self.w + } + } + #[doc = ""] + pub type DMA_SEL3_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel3`"] + pub type DMA_SEL3_R = crate::R; + #[doc = "Write proxy for field `dma_sel3`"] + pub struct DMA_SEL3_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL3_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 18)) | (((value as u32) & 0x3f) << 18); + self.w + } + } + #[doc = ""] + pub type DMA_SEL4_A = DMA_SEL0_A; + #[doc = "Reader of field `dma_sel4`"] + pub type DMA_SEL4_R = crate::R; + #[doc = "Write proxy for field `dma_sel4`"] + pub struct DMA_SEL4_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL4_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | (((value as u32) & 0x3f) << 24); + self.w + } + } + impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel0(&self) -> DMA_SEL0_R { + DMA_SEL0_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11"] + #[inline(always)] + pub fn dma_sel1(&self) -> DMA_SEL1_R { + DMA_SEL1_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17"] + #[inline(always)] + pub fn dma_sel2(&self) -> DMA_SEL2_R { + DMA_SEL2_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:23"] + #[inline(always)] + pub fn dma_sel3(&self) -> DMA_SEL3_R { + DMA_SEL3_R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:29"] + #[inline(always)] + pub fn dma_sel4(&self) -> DMA_SEL4_R { + DMA_SEL4_R::new(((self.bits >> 24) & 0x3f) as u8) + } + } + impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel0(&mut self) -> DMA_SEL0_W { + DMA_SEL0_W { w: self } + } + #[doc = "Bits 6:11"] + #[inline(always)] + pub fn dma_sel1(&mut self) -> DMA_SEL1_W { + DMA_SEL1_W { w: self } + } + #[doc = "Bits 12:17"] + #[inline(always)] + pub fn dma_sel2(&mut self) -> DMA_SEL2_W { + DMA_SEL2_W { w: self } + } + #[doc = "Bits 18:23"] + #[inline(always)] + pub fn dma_sel3(&mut self) -> DMA_SEL3_W { + DMA_SEL3_W { w: self } + } + #[doc = "Bits 24:29"] + #[inline(always)] + pub fn dma_sel4(&mut self) -> DMA_SEL4_W { + DMA_SEL4_W { w: self } + } + } + } + #[doc = "DMA handshake selector\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sel1](dma_sel1) module"] + pub type DMA_SEL1 = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_SEL1; + #[doc = "`read()` method returns [dma_sel1::R](dma_sel1::R) reader structure"] + impl crate::Readable for DMA_SEL1 {} + #[doc = "`write(|w| ..)` method takes [dma_sel1::W](dma_sel1::W) writer structure"] + impl crate::Writable for DMA_SEL1 {} + #[doc = "DMA handshake selector"] + pub mod dma_sel1 { + #[doc = "Reader of register dma_sel1"] + pub type R = crate::R; + #[doc = "Writer for register dma_sel1"] + pub type W = crate::W; + #[doc = "Register dma_sel1 `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_SEL1 { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = ""] + pub type DMA_SEL5_A = super::dma_sel0::DMA_SEL0_A; + #[doc = "Reader of field `dma_sel5`"] + pub type DMA_SEL5_R = crate::R; + #[doc = "Write proxy for field `dma_sel5`"] + pub struct DMA_SEL5_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_SEL5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "`0`"] + #[inline(always)] + pub fn ssi0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI0_RX_REQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ssi0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI0_TX_REQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn ssi1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI1_RX_REQ) + } + #[doc = "`11`"] + #[inline(always)] + pub fn ssi1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI1_TX_REQ) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ssi2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI2_RX_REQ) + } + #[doc = "`101`"] + #[inline(always)] + pub fn ssi2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI2_TX_REQ) + } + #[doc = "`110`"] + #[inline(always)] + pub fn ssi3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI3_RX_REQ) + } + #[doc = "`111`"] + #[inline(always)] + pub fn ssi3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SSI3_TX_REQ) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn i2c0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C0_RX_REQ) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn i2c0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C0_TX_REQ) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn i2c1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C1_RX_REQ) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn i2c1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C1_TX_REQ) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn i2c2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C2_RX_REQ) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn i2c2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2C2_TX_REQ) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn uart1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART1_RX_REQ) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn uart1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART1_TX_REQ) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn uart2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART2_RX_REQ) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn uart2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART2_TX_REQ) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn uart3_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART3_RX_REQ) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn uart3_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::UART3_TX_REQ) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn aes_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::AES_REQ) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sha_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::SHA_RX_REQ) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn ai_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::AI_RX_REQ) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn fft_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::FFT_RX_REQ) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn fft_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::FFT_TX_REQ) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn i2s0_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_TX_REQ) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn i2s0_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_RX_REQ) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn i2s1_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S1_TX_REQ) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn i2s1_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S1_RX_REQ) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn i2s2_tx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S2_TX_REQ) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn i2s2_rx_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S2_RX_REQ) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn i2s0_bf_dir_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_BF_DIR_REQ) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn i2s0_bf_voice_req(self) -> &'a mut W { + self.variant(DMA_SEL5_A::I2S0_BF_VOICE_REQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f); + self.w + } + } + impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel5(&self) -> DMA_SEL5_R { + DMA_SEL5_R::new((self.bits & 0x3f) as u8) + } + } + impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn dma_sel5(&mut self) -> DMA_SEL5_W { + DMA_SEL5_W { w: self } + } + } + } + #[doc = "IO Power Mode Select controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power_sel](power_sel) module"] + pub type POWER_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _POWER_SEL; + #[doc = "`read()` method returns [power_sel::R](power_sel::R) reader structure"] + impl crate::Readable for POWER_SEL {} + #[doc = "`write(|w| ..)` method takes [power_sel::W](power_sel::W) writer structure"] + impl crate::Writable for POWER_SEL {} + #[doc = "IO Power Mode Select controller"] + pub mod power_sel { + #[doc = "Reader of register power_sel"] + pub type R = crate::R; + #[doc = "Writer for register power_sel"] + pub type W = crate::W; + #[doc = "Register power_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::POWER_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `power_mode_sel0`"] + pub type POWER_MODE_SEL0_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel0`"] + pub struct POWER_MODE_SEL0_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `power_mode_sel1`"] + pub type POWER_MODE_SEL1_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel1`"] + pub struct POWER_MODE_SEL1_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `power_mode_sel2`"] + pub type POWER_MODE_SEL2_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel2`"] + pub struct POWER_MODE_SEL2_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); + self.w + } + } + #[doc = "Reader of field `power_mode_sel3`"] + pub type POWER_MODE_SEL3_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel3`"] + pub struct POWER_MODE_SEL3_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); + self.w + } + } + #[doc = "Reader of field `power_mode_sel4`"] + pub type POWER_MODE_SEL4_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel4`"] + pub struct POWER_MODE_SEL4_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); + self.w + } + } + #[doc = "Reader of field `power_mode_sel5`"] + pub type POWER_MODE_SEL5_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel5`"] + pub struct POWER_MODE_SEL5_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Reader of field `power_mode_sel6`"] + pub type POWER_MODE_SEL6_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel6`"] + pub struct POWER_MODE_SEL6_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); + self.w + } + } + #[doc = "Reader of field `power_mode_sel7`"] + pub type POWER_MODE_SEL7_R = crate::R; + #[doc = "Write proxy for field `power_mode_sel7`"] + pub struct POWER_MODE_SEL7_W<'a> { + w: &'a mut W, + } + impl<'a> POWER_MODE_SEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn power_mode_sel0(&self) -> POWER_MODE_SEL0_R { + POWER_MODE_SEL0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn power_mode_sel1(&self) -> POWER_MODE_SEL1_R { + POWER_MODE_SEL1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn power_mode_sel2(&self) -> POWER_MODE_SEL2_R { + POWER_MODE_SEL2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn power_mode_sel3(&self) -> POWER_MODE_SEL3_R { + POWER_MODE_SEL3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn power_mode_sel4(&self) -> POWER_MODE_SEL4_R { + POWER_MODE_SEL4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn power_mode_sel5(&self) -> POWER_MODE_SEL5_R { + POWER_MODE_SEL5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn power_mode_sel6(&self) -> POWER_MODE_SEL6_R { + POWER_MODE_SEL6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn power_mode_sel7(&self) -> POWER_MODE_SEL7_R { + POWER_MODE_SEL7_R::new(((self.bits >> 7) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn power_mode_sel0(&mut self) -> POWER_MODE_SEL0_W { + POWER_MODE_SEL0_W { w: self } + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn power_mode_sel1(&mut self) -> POWER_MODE_SEL1_W { + POWER_MODE_SEL1_W { w: self } + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn power_mode_sel2(&mut self) -> POWER_MODE_SEL2_W { + POWER_MODE_SEL2_W { w: self } + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn power_mode_sel3(&mut self) -> POWER_MODE_SEL3_W { + POWER_MODE_SEL3_W { w: self } + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn power_mode_sel4(&mut self) -> POWER_MODE_SEL4_W { + POWER_MODE_SEL4_W { w: self } + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn power_mode_sel5(&mut self) -> POWER_MODE_SEL5_W { + POWER_MODE_SEL5_W { w: self } + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn power_mode_sel6(&mut self) -> POWER_MODE_SEL6_W { + POWER_MODE_SEL6_W { w: self } + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn power_mode_sel7(&mut self) -> POWER_MODE_SEL7_W { + POWER_MODE_SEL7_W { w: self } + } + } + } +} +#[doc = "AES Accelerator"] +pub struct AES { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AES {} +impl AES { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aes::RegisterBlock { + 0x5045_0000 as *const _ + } +} +impl Deref for AES { + type Target = aes::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*AES::ptr() } + } +} +#[doc = "AES Accelerator"] +pub mod aes { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - 1st-4th word of key"] + pub key: [KEY; 4], + #[doc = "0x10 - Encryption or decryption select"] + pub encrypt_sel: ENCRYPT_SEL, + #[doc = "0x14 - AES mode register"] + pub mode_ctl: MODE_CTL, + #[doc = "0x18 - Initialisation Vector (96 bit for GCM, 128 bit for CBC)"] + pub iv: [IV; 4], + #[doc = "0x28 - Endian control"] + pub endian: ENDIAN, + #[doc = "0x2c - Finished status"] + pub finish: FINISH, + #[doc = "0x30 - DMA select"] + pub dma_sel: DMA_SEL, + #[doc = "0x34 - GCM additional authenticated data count in bytes, minus one"] + pub aad_num: AAD_NUM, + _reserved8: [u8; 4usize], + #[doc = "0x3c - Plaintext/ciphertext input data count in bytes, minus one"] + pub pc_num: PC_NUM, + #[doc = "0x40 - Plaintext/ciphertext input data"] + pub text_data: TEXT_DATA, + #[doc = "0x44 - Additional authenticated data"] + pub aad_data: AAD_DATA, + #[doc = "0x48 - Tag check status"] + pub tag_chk: TAG_CHK, + #[doc = "0x4c - Data can input flag"] + pub data_in_flag: DATA_IN_FLAG, + #[doc = "0x50 - GCM input tag for comparison with the calculated tag"] + pub gcm_in_tag: [GCM_IN_TAG; 4], + #[doc = "0x60 - Plaintext/ciphertext output data"] + pub out_data: OUT_DATA, + #[doc = "0x64 - AES module enable"] + pub en: EN, + #[doc = "0x68 - Data can output flag"] + pub data_out_flag: DATA_OUT_FLAG, + #[doc = "0x6c - Can input tag (when using GCM)"] + pub tag_in_flag: TAG_IN_FLAG, + #[doc = "0x70 - Tag clear (a write to this register clears the tag_chk status)"] + pub tag_clear: TAG_CLEAR, + #[doc = "0x74 - Computed GCM output tag"] + pub gcm_out_tag: [GCM_OUT_TAG; 4], + #[doc = "0x84 - 5th-8th word of key"] + pub key_ext: [KEY_EXT; 4], + } + #[doc = "1st-4th word of key\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key](key) module"] + pub type KEY = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _KEY; + #[doc = "`read()` method returns [key::R](key::R) reader structure"] + impl crate::Readable for KEY {} + #[doc = "`write(|w| ..)` method takes [key::W](key::W) writer structure"] + impl crate::Writable for KEY {} + #[doc = "1st-4th word of key"] + pub mod key { + #[doc = "Reader of register key[%s]"] + pub type R = crate::R; + #[doc = "Writer for register key[%s]"] + pub type W = crate::W; + #[doc = "Register key[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::KEY { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Encryption or decryption select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [encrypt_sel](encrypt_sel) module"] + pub type ENCRYPT_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENCRYPT_SEL; + #[doc = "`read()` method returns [encrypt_sel::R](encrypt_sel::R) reader structure"] + impl crate::Readable for ENCRYPT_SEL {} + #[doc = "`write(|w| ..)` method takes [encrypt_sel::W](encrypt_sel::W) writer structure"] + impl crate::Writable for ENCRYPT_SEL {} + #[doc = "Encryption or decryption select"] + pub mod encrypt_sel { + #[doc = "Reader of register encrypt_sel"] + pub type R = crate::R; + #[doc = "Writer for register encrypt_sel"] + pub type W = crate::W; + #[doc = "Register encrypt_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::ENCRYPT_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Select encryption or decryption mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum ENCRYPT_SEL_A { + #[doc = "0: Sets encryption mode"] + ENCRYPTION = 0, + #[doc = "1: Sets decryption mode"] + DECRYPTION = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: ENCRYPT_SEL_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `encrypt_sel`"] + pub type ENCRYPT_SEL_R = crate::R; + impl ENCRYPT_SEL_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENCRYPT_SEL_A { + match self.bits { + false => ENCRYPT_SEL_A::ENCRYPTION, + true => ENCRYPT_SEL_A::DECRYPTION, + } + } + #[doc = "Checks if the value of the field is `ENCRYPTION`"] + #[inline(always)] + pub fn is_encryption(&self) -> bool { + *self == ENCRYPT_SEL_A::ENCRYPTION + } + #[doc = "Checks if the value of the field is `DECRYPTION`"] + #[inline(always)] + pub fn is_decryption(&self) -> bool { + *self == ENCRYPT_SEL_A::DECRYPTION + } + } + #[doc = "Write proxy for field `encrypt_sel`"] + pub struct ENCRYPT_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> ENCRYPT_SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENCRYPT_SEL_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Sets encryption mode"] + #[inline(always)] + pub fn encryption(self) -> &'a mut W { + self.variant(ENCRYPT_SEL_A::ENCRYPTION) + } + #[doc = "Sets decryption mode"] + #[inline(always)] + pub fn decryption(self) -> &'a mut W { + self.variant(ENCRYPT_SEL_A::DECRYPTION) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Select encryption or decryption mode"] + #[inline(always)] + pub fn encrypt_sel(&self) -> ENCRYPT_SEL_R { + ENCRYPT_SEL_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Select encryption or decryption mode"] + #[inline(always)] + pub fn encrypt_sel(&mut self) -> ENCRYPT_SEL_W { + ENCRYPT_SEL_W { w: self } + } + } + } + #[doc = "AES mode register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode_ctl](mode_ctl) module"] + pub type MODE_CTL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _MODE_CTL; + #[doc = "`read()` method returns [mode_ctl::R](mode_ctl::R) reader structure"] + impl crate::Readable for MODE_CTL {} + #[doc = "`write(|w| ..)` method takes [mode_ctl::W](mode_ctl::W) writer structure"] + impl crate::Writable for MODE_CTL {} + #[doc = "AES mode register"] + pub mod mode_ctl { + #[doc = "Reader of register mode_ctl"] + pub type R = crate::R; + #[doc = "Writer for register mode_ctl"] + pub type W = crate::W; + #[doc = "Register mode_ctl `reset()`'s with value 0"] + impl crate::ResetValue for super::MODE_CTL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Cipher mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum CIPHER_MODE_A { + #[doc = "0: Electronic Codebook"] + ECB = 0, + #[doc = "1: Cipher Block Chaining"] + CBC = 1, + #[doc = "2: Galois/Counter Mode"] + GCM = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: CIPHER_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `cipher_mode`"] + pub type CIPHER_MODE_R = crate::R; + impl CIPHER_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(CIPHER_MODE_A::ECB), + 1 => Val(CIPHER_MODE_A::CBC), + 2 => Val(CIPHER_MODE_A::GCM), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `ECB`"] + #[inline(always)] + pub fn is_ecb(&self) -> bool { + *self == CIPHER_MODE_A::ECB + } + #[doc = "Checks if the value of the field is `CBC`"] + #[inline(always)] + pub fn is_cbc(&self) -> bool { + *self == CIPHER_MODE_A::CBC + } + #[doc = "Checks if the value of the field is `GCM`"] + #[inline(always)] + pub fn is_gcm(&self) -> bool { + *self == CIPHER_MODE_A::GCM + } + } + #[doc = "Write proxy for field `cipher_mode`"] + pub struct CIPHER_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> CIPHER_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CIPHER_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Electronic Codebook"] + #[inline(always)] + pub fn ecb(self) -> &'a mut W { + self.variant(CIPHER_MODE_A::ECB) + } + #[doc = "Cipher Block Chaining"] + #[inline(always)] + pub fn cbc(self) -> &'a mut W { + self.variant(CIPHER_MODE_A::CBC) + } + #[doc = "Galois/Counter Mode"] + #[inline(always)] + pub fn gcm(self) -> &'a mut W { + self.variant(CIPHER_MODE_A::GCM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "Key mode\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum KEY_MODE_A { + #[doc = "0: AES-128"] + AES128 = 0, + #[doc = "1: AES-192"] + AES192 = 1, + #[doc = "2: AES-256"] + AES256 = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: KEY_MODE_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `key_mode`"] + pub type KEY_MODE_R = crate::R; + impl KEY_MODE_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(KEY_MODE_A::AES128), + 1 => Val(KEY_MODE_A::AES192), + 2 => Val(KEY_MODE_A::AES256), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `AES128`"] + #[inline(always)] + pub fn is_aes128(&self) -> bool { + *self == KEY_MODE_A::AES128 + } + #[doc = "Checks if the value of the field is `AES192`"] + #[inline(always)] + pub fn is_aes192(&self) -> bool { + *self == KEY_MODE_A::AES192 + } + #[doc = "Checks if the value of the field is `AES256`"] + #[inline(always)] + pub fn is_aes256(&self) -> bool { + *self == KEY_MODE_A::AES256 + } + } + #[doc = "Write proxy for field `key_mode`"] + pub struct KEY_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> KEY_MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AES-128"] + #[inline(always)] + pub fn aes128(self) -> &'a mut W { + self.variant(KEY_MODE_A::AES128) + } + #[doc = "AES-192"] + #[inline(always)] + pub fn aes192(self) -> &'a mut W { + self.variant(KEY_MODE_A::AES192) + } + #[doc = "AES-256"] + #[inline(always)] + pub fn aes256(self) -> &'a mut W { + self.variant(KEY_MODE_A::AES256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3); + self.w + } + } + #[doc = "Input key order\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum KEY_ORDER_A { + #[doc = "0: Big Endian"] + BE = 0, + #[doc = "1: Little Endian"] + LE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: KEY_ORDER_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `key_order`"] + pub type KEY_ORDER_R = crate::R; + impl KEY_ORDER_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> KEY_ORDER_A { + match self.bits { + false => KEY_ORDER_A::BE, + true => KEY_ORDER_A::LE, + } + } + #[doc = "Checks if the value of the field is `BE`"] + #[inline(always)] + pub fn is_be(&self) -> bool { + *self == KEY_ORDER_A::BE + } + #[doc = "Checks if the value of the field is `LE`"] + #[inline(always)] + pub fn is_le(&self) -> bool { + *self == KEY_ORDER_A::LE + } + } + #[doc = "Write proxy for field `key_order`"] + pub struct KEY_ORDER_W<'a> { + w: &'a mut W, + } + impl<'a> KEY_ORDER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_ORDER_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(KEY_ORDER_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(KEY_ORDER_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + #[doc = "Input data order"] + pub type INPUT_ORDER_A = KEY_ORDER_A; + #[doc = "Reader of field `input_order`"] + pub type INPUT_ORDER_R = crate::R; + #[doc = "Write proxy for field `input_order`"] + pub struct INPUT_ORDER_W<'a> { + w: &'a mut W, + } + impl<'a> INPUT_ORDER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INPUT_ORDER_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(INPUT_ORDER_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(INPUT_ORDER_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); + self.w + } + } + #[doc = "Output data order"] + pub type OUTPUT_ORDER_A = KEY_ORDER_A; + #[doc = "Reader of field `output_order`"] + pub type OUTPUT_ORDER_R = crate::R; + #[doc = "Write proxy for field `output_order`"] + pub struct OUTPUT_ORDER_W<'a> { + w: &'a mut W, + } + impl<'a> OUTPUT_ORDER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUTPUT_ORDER_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(OUTPUT_ORDER_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(OUTPUT_ORDER_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Cipher mode"] + #[inline(always)] + pub fn cipher_mode(&self) -> CIPHER_MODE_R { + CIPHER_MODE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - Key mode"] + #[inline(always)] + pub fn key_mode(&self) -> KEY_MODE_R { + KEY_MODE_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Input key order"] + #[inline(always)] + pub fn key_order(&self) -> KEY_ORDER_R { + KEY_ORDER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Input data order"] + #[inline(always)] + pub fn input_order(&self) -> INPUT_ORDER_R { + INPUT_ORDER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Output data order"] + #[inline(always)] + pub fn output_order(&self) -> OUTPUT_ORDER_R { + OUTPUT_ORDER_R::new(((self.bits >> 9) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:2 - Cipher mode"] + #[inline(always)] + pub fn cipher_mode(&mut self) -> CIPHER_MODE_W { + CIPHER_MODE_W { w: self } + } + #[doc = "Bits 3:4 - Key mode"] + #[inline(always)] + pub fn key_mode(&mut self) -> KEY_MODE_W { + KEY_MODE_W { w: self } + } + #[doc = "Bit 5 - Input key order"] + #[inline(always)] + pub fn key_order(&mut self) -> KEY_ORDER_W { + KEY_ORDER_W { w: self } + } + #[doc = "Bit 7 - Input data order"] + #[inline(always)] + pub fn input_order(&mut self) -> INPUT_ORDER_W { + INPUT_ORDER_W { w: self } + } + #[doc = "Bit 9 - Output data order"] + #[inline(always)] + pub fn output_order(&mut self) -> OUTPUT_ORDER_W { + OUTPUT_ORDER_W { w: self } + } + } + } + #[doc = "Initialisation Vector (96 bit for GCM, 128 bit for CBC)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iv](iv) module"] + pub type IV = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _IV; + #[doc = "`read()` method returns [iv::R](iv::R) reader structure"] + impl crate::Readable for IV {} + #[doc = "`write(|w| ..)` method takes [iv::W](iv::W) writer structure"] + impl crate::Writable for IV {} + #[doc = "Initialisation Vector (96 bit for GCM, 128 bit for CBC)"] + pub mod iv { + #[doc = "Reader of register iv[%s]"] + pub type R = crate::R; + #[doc = "Writer for register iv[%s]"] + pub type W = crate::W; + #[doc = "Register iv[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::IV { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Endian control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endian](endian) module"] + pub type ENDIAN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ENDIAN; + #[doc = "`read()` method returns [endian::R](endian::R) reader structure"] + impl crate::Readable for ENDIAN {} + #[doc = "`write(|w| ..)` method takes [endian::W](endian::W) writer structure"] + impl crate::Writable for ENDIAN {} + #[doc = "Endian control"] + pub mod endian { + #[doc = "Reader of register endian"] + pub type R = crate::R; + #[doc = "Writer for register endian"] + pub type W = crate::W; + #[doc = "Register endian `reset()`'s with value 0"] + impl crate::ResetValue for super::ENDIAN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Input data endian"] + pub type ENDIAN_A = super::mode_ctl::KEY_ORDER_A; + #[doc = "Reader of field `endian`"] + pub type ENDIAN_R = crate::R; + #[doc = "Write proxy for field `endian`"] + pub struct ENDIAN_W<'a> { + w: &'a mut W, + } + impl<'a> ENDIAN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIAN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Big Endian"] + #[inline(always)] + pub fn be(self) -> &'a mut W { + self.variant(ENDIAN_A::BE) + } + #[doc = "Little Endian"] + #[inline(always)] + pub fn le(self) -> &'a mut W { + self.variant(ENDIAN_A::LE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Input data endian"] + #[inline(always)] + pub fn endian(&self) -> ENDIAN_R { + ENDIAN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Input data endian"] + #[inline(always)] + pub fn endian(&mut self) -> ENDIAN_W { + ENDIAN_W { w: self } + } + } + } + #[doc = "Finished status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [finish](finish) module"] + pub type FINISH = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _FINISH; + #[doc = "`read()` method returns [finish::R](finish::R) reader structure"] + impl crate::Readable for FINISH {} + #[doc = "`write(|w| ..)` method takes [finish::W](finish::W) writer structure"] + impl crate::Writable for FINISH {} + #[doc = "Finished status"] + pub mod finish { + #[doc = "Reader of register finish"] + pub type R = crate::R; + #[doc = "Writer for register finish"] + pub type W = crate::W; + #[doc = "Register finish `reset()`'s with value 0"] + impl crate::ResetValue for super::FINISH { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "AES operation finished status\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum FINISH_A { + #[doc = "0: Operation not finished"] + NOT_FINISHED = 0, + #[doc = "1: Operation finished"] + FINISHED = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: FINISH_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `finish`"] + pub type FINISH_R = crate::R; + impl FINISH_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FINISH_A { + match self.bits { + false => FINISH_A::NOT_FINISHED, + true => FINISH_A::FINISHED, + } + } + #[doc = "Checks if the value of the field is `NOT_FINISHED`"] + #[inline(always)] + pub fn is_not_finished(&self) -> bool { + *self == FINISH_A::NOT_FINISHED + } + #[doc = "Checks if the value of the field is `FINISHED`"] + #[inline(always)] + pub fn is_finished(&self) -> bool { + *self == FINISH_A::FINISHED + } + } + #[doc = "Write proxy for field `finish`"] + pub struct FINISH_W<'a> { + w: &'a mut W, + } + impl<'a> FINISH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FINISH_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Operation not finished"] + #[inline(always)] + pub fn not_finished(self) -> &'a mut W { + self.variant(FINISH_A::NOT_FINISHED) + } + #[doc = "Operation finished"] + #[inline(always)] + pub fn finished(self) -> &'a mut W { + self.variant(FINISH_A::FINISHED) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - AES operation finished status"] + #[inline(always)] + pub fn finish(&self) -> FINISH_R { + FINISH_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - AES operation finished status"] + #[inline(always)] + pub fn finish(&mut self) -> FINISH_W { + FINISH_W { w: self } + } + } + } + #[doc = "DMA select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sel](dma_sel) module"] + pub type DMA_SEL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DMA_SEL; + #[doc = "`read()` method returns [dma_sel::R](dma_sel::R) reader structure"] + impl crate::Readable for DMA_SEL {} + #[doc = "`write(|w| ..)` method takes [dma_sel::W](dma_sel::W) writer structure"] + impl crate::Writable for DMA_SEL {} + #[doc = "DMA select"] + pub mod dma_sel { + #[doc = "Reader of register dma_sel"] + pub type R = crate::R; + #[doc = "Writer for register dma_sel"] + pub type W = crate::W; + #[doc = "Register dma_sel `reset()`'s with value 0"] + impl crate::ResetValue for super::DMA_SEL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `dma_sel`"] + pub type DMA_SEL_R = crate::R; + #[doc = "Write proxy for field `dma_sel`"] + pub struct DMA_SEL_W<'a> { + w: &'a mut W, + } + impl<'a> DMA_SEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Output to DMA if set, to CPU otherwise"] + #[inline(always)] + pub fn dma_sel(&self) -> DMA_SEL_R { + DMA_SEL_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Output to DMA if set, to CPU otherwise"] + #[inline(always)] + pub fn dma_sel(&mut self) -> DMA_SEL_W { + DMA_SEL_W { w: self } + } + } + } + #[doc = "GCM additional authenticated data count in bytes, minus one\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aad_num](aad_num) module"] + pub type AAD_NUM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AAD_NUM; + #[doc = "`read()` method returns [aad_num::R](aad_num::R) reader structure"] + impl crate::Readable for AAD_NUM {} + #[doc = "`write(|w| ..)` method takes [aad_num::W](aad_num::W) writer structure"] + impl crate::Writable for AAD_NUM {} + #[doc = "GCM additional authenticated data count in bytes, minus one"] + pub mod aad_num { + #[doc = "Reader of register aad_num"] + pub type R = crate::R; + #[doc = "Writer for register aad_num"] + pub type W = crate::W; + #[doc = "Register aad_num `reset()`'s with value 0"] + impl crate::ResetValue for super::AAD_NUM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Plaintext/ciphertext input data count in bytes, minus one\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pc_num](pc_num) module"] + pub type PC_NUM = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _PC_NUM; + #[doc = "`read()` method returns [pc_num::R](pc_num::R) reader structure"] + impl crate::Readable for PC_NUM {} + #[doc = "`write(|w| ..)` method takes [pc_num::W](pc_num::W) writer structure"] + impl crate::Writable for PC_NUM {} + #[doc = "Plaintext/ciphertext input data count in bytes, minus one"] + pub mod pc_num { + #[doc = "Reader of register pc_num"] + pub type R = crate::R; + #[doc = "Writer for register pc_num"] + pub type W = crate::W; + #[doc = "Register pc_num `reset()`'s with value 0"] + impl crate::ResetValue for super::PC_NUM { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Plaintext/ciphertext input data\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [text_data](text_data) module"] + pub type TEXT_DATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TEXT_DATA; + #[doc = "`read()` method returns [text_data::R](text_data::R) reader structure"] + impl crate::Readable for TEXT_DATA {} + #[doc = "`write(|w| ..)` method takes [text_data::W](text_data::W) writer structure"] + impl crate::Writable for TEXT_DATA {} + #[doc = "Plaintext/ciphertext input data"] + pub mod text_data { + #[doc = "Reader of register text_data"] + pub type R = crate::R; + #[doc = "Writer for register text_data"] + pub type W = crate::W; + #[doc = "Register text_data `reset()`'s with value 0"] + impl crate::ResetValue for super::TEXT_DATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Additional authenticated data\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aad_data](aad_data) module"] + pub type AAD_DATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _AAD_DATA; + #[doc = "`read()` method returns [aad_data::R](aad_data::R) reader structure"] + impl crate::Readable for AAD_DATA {} + #[doc = "`write(|w| ..)` method takes [aad_data::W](aad_data::W) writer structure"] + impl crate::Writable for AAD_DATA {} + #[doc = "Additional authenticated data"] + pub mod aad_data { + #[doc = "Reader of register aad_data"] + pub type R = crate::R; + #[doc = "Writer for register aad_data"] + pub type W = crate::W; + #[doc = "Register aad_data `reset()`'s with value 0"] + impl crate::ResetValue for super::AAD_DATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Tag check status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tag_chk](tag_chk) module"] + pub type TAG_CHK = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAG_CHK; + #[doc = "`read()` method returns [tag_chk::R](tag_chk::R) reader structure"] + impl crate::Readable for TAG_CHK {} + #[doc = "`write(|w| ..)` method takes [tag_chk::W](tag_chk::W) writer structure"] + impl crate::Writable for TAG_CHK {} + #[doc = "Tag check status"] + pub mod tag_chk { + #[doc = "Reader of register tag_chk"] + pub type R = crate::R; + #[doc = "Writer for register tag_chk"] + pub type W = crate::W; + #[doc = "Register tag_chk `reset()`'s with value 0"] + impl crate::ResetValue for super::TAG_CHK { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Tag check status\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + #[repr(u8)] + pub enum TAG_CHK_A { + #[doc = "0: Check not finished"] + BUSY = 0, + #[doc = "1: Check failed"] + FAIL = 1, + #[doc = "2: Check success"] + SUCCESS = 2, + } + impl From for u8 { + #[inline(always)] + fn from(variant: TAG_CHK_A) -> Self { + variant as _ + } + } + #[doc = "Reader of field `tag_chk`"] + pub type TAG_CHK_R = crate::R; + impl TAG_CHK_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> crate::Variant { + use crate::Variant::*; + match self.bits { + 0 => Val(TAG_CHK_A::BUSY), + 1 => Val(TAG_CHK_A::FAIL), + 2 => Val(TAG_CHK_A::SUCCESS), + i => Res(i), + } + } + #[doc = "Checks if the value of the field is `BUSY`"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == TAG_CHK_A::BUSY + } + #[doc = "Checks if the value of the field is `FAIL`"] + #[inline(always)] + pub fn is_fail(&self) -> bool { + *self == TAG_CHK_A::FAIL + } + #[doc = "Checks if the value of the field is `SUCCESS`"] + #[inline(always)] + pub fn is_success(&self) -> bool { + *self == TAG_CHK_A::SUCCESS + } + } + #[doc = "Write proxy for field `tag_chk`"] + pub struct TAG_CHK_W<'a> { + w: &'a mut W, + } + impl<'a> TAG_CHK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TAG_CHK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Check not finished"] + #[inline(always)] + pub fn busy(self) -> &'a mut W { + self.variant(TAG_CHK_A::BUSY) + } + #[doc = "Check failed"] + #[inline(always)] + pub fn fail(self) -> &'a mut W { + self.variant(TAG_CHK_A::FAIL) + } + #[doc = "Check success"] + #[inline(always)] + pub fn success(self) -> &'a mut W { + self.variant(TAG_CHK_A::SUCCESS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); + self.w + } + } + impl R { + #[doc = "Bits 0:1 - Tag check status"] + #[inline(always)] + pub fn tag_chk(&self) -> TAG_CHK_R { + TAG_CHK_R::new((self.bits & 0x03) as u8) + } + } + impl W { + #[doc = "Bits 0:1 - Tag check status"] + #[inline(always)] + pub fn tag_chk(&mut self) -> TAG_CHK_W { + TAG_CHK_W { w: self } + } + } + } + #[doc = "Data can input flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_in_flag](data_in_flag) module"] + pub type DATA_IN_FLAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_IN_FLAG; + #[doc = "`read()` method returns [data_in_flag::R](data_in_flag::R) reader structure"] + impl crate::Readable for DATA_IN_FLAG {} + #[doc = "`write(|w| ..)` method takes [data_in_flag::W](data_in_flag::W) writer structure"] + impl crate::Writable for DATA_IN_FLAG {} + #[doc = "Data can input flag"] + pub mod data_in_flag { + #[doc = "Reader of register data_in_flag"] + pub type R = crate::R; + #[doc = "Writer for register data_in_flag"] + pub type W = crate::W; + #[doc = "Register data_in_flag `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_IN_FLAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Data can be written to text_data or aad_data when this flag is set\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum DATA_IN_FLAG_A { + #[doc = "0: Cannot input"] + CANNOT_INPUT = 0, + #[doc = "1: Can input"] + CAN_INPUT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: DATA_IN_FLAG_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `data_in_flag`"] + pub type DATA_IN_FLAG_R = crate::R; + impl DATA_IN_FLAG_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATA_IN_FLAG_A { + match self.bits { + false => DATA_IN_FLAG_A::CANNOT_INPUT, + true => DATA_IN_FLAG_A::CAN_INPUT, + } + } + #[doc = "Checks if the value of the field is `CANNOT_INPUT`"] + #[inline(always)] + pub fn is_cannot_input(&self) -> bool { + *self == DATA_IN_FLAG_A::CANNOT_INPUT + } + #[doc = "Checks if the value of the field is `CAN_INPUT`"] + #[inline(always)] + pub fn is_can_input(&self) -> bool { + *self == DATA_IN_FLAG_A::CAN_INPUT + } + } + #[doc = "Write proxy for field `data_in_flag`"] + pub struct DATA_IN_FLAG_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_IN_FLAG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATA_IN_FLAG_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Cannot input"] + #[inline(always)] + pub fn cannot_input(self) -> &'a mut W { + self.variant(DATA_IN_FLAG_A::CANNOT_INPUT) + } + #[doc = "Can input"] + #[inline(always)] + pub fn can_input(self) -> &'a mut W { + self.variant(DATA_IN_FLAG_A::CAN_INPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Data can be written to text_data or aad_data when this flag is set"] + #[inline(always)] + pub fn data_in_flag(&self) -> DATA_IN_FLAG_R { + DATA_IN_FLAG_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Data can be written to text_data or aad_data when this flag is set"] + #[inline(always)] + pub fn data_in_flag(&mut self) -> DATA_IN_FLAG_W { + DATA_IN_FLAG_W { w: self } + } + } + } + #[doc = "GCM input tag for comparison with the calculated tag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcm_in_tag](gcm_in_tag) module"] + pub type GCM_IN_TAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GCM_IN_TAG; + #[doc = "`read()` method returns [gcm_in_tag::R](gcm_in_tag::R) reader structure"] + impl crate::Readable for GCM_IN_TAG {} + #[doc = "`write(|w| ..)` method takes [gcm_in_tag::W](gcm_in_tag::W) writer structure"] + impl crate::Writable for GCM_IN_TAG {} + #[doc = "GCM input tag for comparison with the calculated tag"] + pub mod gcm_in_tag { + #[doc = "Reader of register gcm_in_tag[%s]"] + pub type R = crate::R; + #[doc = "Writer for register gcm_in_tag[%s]"] + pub type W = crate::W; + #[doc = "Register gcm_in_tag[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::GCM_IN_TAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Plaintext/ciphertext output data\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_data](out_data) module"] + pub type OUT_DATA = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _OUT_DATA; + #[doc = "`read()` method returns [out_data::R](out_data::R) reader structure"] + impl crate::Readable for OUT_DATA {} + #[doc = "`write(|w| ..)` method takes [out_data::W](out_data::W) writer structure"] + impl crate::Writable for OUT_DATA {} + #[doc = "Plaintext/ciphertext output data"] + pub mod out_data { + #[doc = "Reader of register out_data"] + pub type R = crate::R; + #[doc = "Writer for register out_data"] + pub type W = crate::W; + #[doc = "Register out_data `reset()`'s with value 0"] + impl crate::ResetValue for super::OUT_DATA { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "AES module enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en](en) module"] + pub type EN = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EN; + #[doc = "`read()` method returns [en::R](en::R) reader structure"] + impl crate::Readable for EN {} + #[doc = "`write(|w| ..)` method takes [en::W](en::W) writer structure"] + impl crate::Writable for EN {} + #[doc = "AES module enable"] + pub mod en { + #[doc = "Reader of register en"] + pub type R = crate::R; + #[doc = "Writer for register en"] + pub type W = crate::W; + #[doc = "Register en `reset()`'s with value 0"] + impl crate::ResetValue for super::EN { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "AES module enable\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum EN_A { + #[doc = "0: Disable module"] + DISABLE = 0, + #[doc = "1: Enable module"] + ENABLE = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: EN_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `en`"] + pub type EN_R = crate::R; + impl EN_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EN_A { + match self.bits { + false => EN_A::DISABLE, + true => EN_A::ENABLE, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == EN_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == EN_A::ENABLE + } + } + #[doc = "Write proxy for field `en`"] + pub struct EN_W<'a> { + w: &'a mut W, + } + impl<'a> EN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EN_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Disable module"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(EN_A::DISABLE) + } + #[doc = "Enable module"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(EN_A::ENABLE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - AES module enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - AES module enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + } + } + #[doc = "Data can output flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data_out_flag](data_out_flag) module"] + pub type DATA_OUT_FLAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATA_OUT_FLAG; + #[doc = "`read()` method returns [data_out_flag::R](data_out_flag::R) reader structure"] + impl crate::Readable for DATA_OUT_FLAG {} + #[doc = "`write(|w| ..)` method takes [data_out_flag::W](data_out_flag::W) writer structure"] + impl crate::Writable for DATA_OUT_FLAG {} + #[doc = "Data can output flag"] + pub mod data_out_flag { + #[doc = "Reader of register data_out_flag"] + pub type R = crate::R; + #[doc = "Writer for register data_out_flag"] + pub type W = crate::W; + #[doc = "Register data_out_flag `reset()`'s with value 0"] + impl crate::ResetValue for super::DATA_OUT_FLAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Data can be read from out_data when this flag is set\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum DATA_OUT_FLAG_A { + #[doc = "0: Data cannot output"] + CANNOT_OUTPUT = 0, + #[doc = "1: Data can output"] + CAN_OUTPUT = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: DATA_OUT_FLAG_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `data_out_flag`"] + pub type DATA_OUT_FLAG_R = crate::R; + impl DATA_OUT_FLAG_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATA_OUT_FLAG_A { + match self.bits { + false => DATA_OUT_FLAG_A::CANNOT_OUTPUT, + true => DATA_OUT_FLAG_A::CAN_OUTPUT, + } + } + #[doc = "Checks if the value of the field is `CANNOT_OUTPUT`"] + #[inline(always)] + pub fn is_cannot_output(&self) -> bool { + *self == DATA_OUT_FLAG_A::CANNOT_OUTPUT + } + #[doc = "Checks if the value of the field is `CAN_OUTPUT`"] + #[inline(always)] + pub fn is_can_output(&self) -> bool { + *self == DATA_OUT_FLAG_A::CAN_OUTPUT + } + } + #[doc = "Write proxy for field `data_out_flag`"] + pub struct DATA_OUT_FLAG_W<'a> { + w: &'a mut W, + } + impl<'a> DATA_OUT_FLAG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATA_OUT_FLAG_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Data cannot output"] + #[inline(always)] + pub fn cannot_output(self) -> &'a mut W { + self.variant(DATA_OUT_FLAG_A::CANNOT_OUTPUT) + } + #[doc = "Data can output"] + #[inline(always)] + pub fn can_output(self) -> &'a mut W { + self.variant(DATA_OUT_FLAG_A::CAN_OUTPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - Data can be read from out_data when this flag is set"] + #[inline(always)] + pub fn data_out_flag(&self) -> DATA_OUT_FLAG_R { + DATA_OUT_FLAG_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - Data can be read from out_data when this flag is set"] + #[inline(always)] + pub fn data_out_flag(&mut self) -> DATA_OUT_FLAG_W { + DATA_OUT_FLAG_W { w: self } + } + } + } + #[doc = "Can input tag (when using GCM)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tag_in_flag](tag_in_flag) module"] + pub type TAG_IN_FLAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAG_IN_FLAG; + #[doc = "`read()` method returns [tag_in_flag::R](tag_in_flag::R) reader structure"] + impl crate::Readable for TAG_IN_FLAG {} + #[doc = "`write(|w| ..)` method takes [tag_in_flag::W](tag_in_flag::W) writer structure"] + impl crate::Writable for TAG_IN_FLAG {} + #[doc = "Can input tag (when using GCM)"] + pub mod tag_in_flag { + #[doc = "Reader of register tag_in_flag"] + pub type R = crate::R; + #[doc = "Writer for register tag_in_flag"] + pub type W = crate::W; + #[doc = "Register tag_in_flag `reset()`'s with value 0"] + impl crate::ResetValue for super::TAG_IN_FLAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "GCM tag can be written to gcm_in_tag when this flag is set"] + pub type TAG_IN_FLAG_A = super::data_in_flag::DATA_IN_FLAG_A; + #[doc = "Reader of field `tag_in_flag`"] + pub type TAG_IN_FLAG_R = crate::R; + #[doc = "Write proxy for field `tag_in_flag`"] + pub struct TAG_IN_FLAG_W<'a> { + w: &'a mut W, + } + impl<'a> TAG_IN_FLAG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TAG_IN_FLAG_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "Cannot input"] + #[inline(always)] + pub fn cannot_input(self) -> &'a mut W { + self.variant(TAG_IN_FLAG_A::CANNOT_INPUT) + } + #[doc = "Can input"] + #[inline(always)] + pub fn can_input(self) -> &'a mut W { + self.variant(TAG_IN_FLAG_A::CAN_INPUT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + impl R { + #[doc = "Bit 0 - GCM tag can be written to gcm_in_tag when this flag is set"] + #[inline(always)] + pub fn tag_in_flag(&self) -> TAG_IN_FLAG_R { + TAG_IN_FLAG_R::new((self.bits & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - GCM tag can be written to gcm_in_tag when this flag is set"] + #[inline(always)] + pub fn tag_in_flag(&mut self) -> TAG_IN_FLAG_W { + TAG_IN_FLAG_W { w: self } + } + } + } + #[doc = "Tag clear (a write to this register clears the tag_chk status)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tag_clear](tag_clear) module"] + pub type TAG_CLEAR = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TAG_CLEAR; + #[doc = "`read()` method returns [tag_clear::R](tag_clear::R) reader structure"] + impl crate::Readable for TAG_CLEAR {} + #[doc = "`write(|w| ..)` method takes [tag_clear::W](tag_clear::W) writer structure"] + impl crate::Writable for TAG_CLEAR {} + #[doc = "Tag clear (a write to this register clears the tag_chk status)"] + pub mod tag_clear { + #[doc = "Reader of register tag_clear"] + pub type R = crate::R; + #[doc = "Writer for register tag_clear"] + pub type W = crate::W; + #[doc = "Register tag_clear `reset()`'s with value 0"] + impl crate::ResetValue for super::TAG_CLEAR { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "Computed GCM output tag\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcm_out_tag](gcm_out_tag) module"] + pub type GCM_OUT_TAG = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _GCM_OUT_TAG; + #[doc = "`read()` method returns [gcm_out_tag::R](gcm_out_tag::R) reader structure"] + impl crate::Readable for GCM_OUT_TAG {} + #[doc = "`write(|w| ..)` method takes [gcm_out_tag::W](gcm_out_tag::W) writer structure"] + impl crate::Writable for GCM_OUT_TAG {} + #[doc = "Computed GCM output tag"] + pub mod gcm_out_tag { + #[doc = "Reader of register gcm_out_tag[%s]"] + pub type R = crate::R; + #[doc = "Writer for register gcm_out_tag[%s]"] + pub type W = crate::W; + #[doc = "Register gcm_out_tag[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::GCM_OUT_TAG { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } + #[doc = "5th-8th word of key\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key_ext](key_ext) module"] + pub type KEY_EXT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _KEY_EXT; + #[doc = "`read()` method returns [key_ext::R](key_ext::R) reader structure"] + impl crate::Readable for KEY_EXT {} + #[doc = "`write(|w| ..)` method takes [key_ext::W](key_ext::W) writer structure"] + impl crate::Writable for KEY_EXT {} + #[doc = "5th-8th word of key"] + pub mod key_ext { + #[doc = "Reader of register key_ext[%s]"] + pub type R = crate::R; + #[doc = "Writer for register key_ext[%s]"] + pub type W = crate::W; + #[doc = "Register key_ext[%s] +`reset()`'s with value 0"] + impl crate::ResetValue for super::KEY_EXT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + impl R {} + impl W {} + } +} +#[doc = "Real Time Clock"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Returns a pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + 0x5046_0000 as *const _ + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*RTC::ptr() } + } +} +#[doc = "Real Time Clock"] +pub mod rtc { + #[doc = r"Register block"] + #[repr(C)] + pub struct RegisterBlock { + #[doc = "0x00 - Timer date information"] + pub date: DATE, + #[doc = "0x04 - Timer time information"] + pub time: TIME, + #[doc = "0x08 - Alarm date information"] + pub alarm_date: ALARM_DATE, + #[doc = "0x0c - Alarm time information"] + pub alarm_time: ALARM_TIME, + #[doc = "0x10 - Timer counter initial value"] + pub initial_count: INITIAL_COUNT, + #[doc = "0x14 - Timer counter current value"] + pub current_count: CURRENT_COUNT, + #[doc = "0x18 - RTC interrupt settings"] + pub interrupt_ctrl: INTERRUPT_CTRL, + #[doc = "0x1c - RTC register settings"] + pub register_ctrl: REGISTER_CTRL, + _reserved8: [u8; 8usize], + #[doc = "0x28 - Timer extended information"] + pub extended: EXTENDED, + } + #[doc = "Timer date information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [date](date) module"] + pub type DATE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _DATE; + #[doc = "`read()` method returns [date::R](date::R) reader structure"] + impl crate::Readable for DATE {} + #[doc = "`write(|w| ..)` method takes [date::W](date::W) writer structure"] + impl crate::Writable for DATE {} + #[doc = "Timer date information"] + pub mod date { + #[doc = "Reader of register date"] + pub type R = crate::R; + #[doc = "Writer for register date"] + pub type W = crate::W; + #[doc = "Register date `reset()`'s with value 0"] + impl crate::ResetValue for super::DATE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `week`"] + pub type WEEK_R = crate::R; + #[doc = "Write proxy for field `week`"] + pub struct WEEK_W<'a> { + w: &'a mut W, + } + impl<'a> WEEK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "Reader of field `day`"] + pub type DAY_R = crate::R; + #[doc = "Write proxy for field `day`"] + pub struct DAY_W<'a> { + w: &'a mut W, + } + impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8); + self.w + } + } + #[doc = "Reader of field `month`"] + pub type MONTH_R = crate::R; + #[doc = "Write proxy for field `month`"] + pub struct MONTH_W<'a> { + w: &'a mut W, + } + impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + #[doc = "Reader of field `year`"] + pub type YEAR_R = crate::R; + #[doc = "Write proxy for field `year`"] + pub struct YEAR_W<'a> { + w: &'a mut W, + } + impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | (((value as u32) & 0x0fff) << 20); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&self) -> WEEK_R { + WEEK_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 20) & 0x0fff) as u16) + } + } + impl W { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&mut self) -> WEEK_W { + WEEK_W { w: self } + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + } + } + #[doc = "Timer time information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [time](time) module"] + pub type TIME = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _TIME; + #[doc = "`read()` method returns [time::R](time::R) reader structure"] + impl crate::Readable for TIME {} + #[doc = "`write(|w| ..)` method takes [time::W](time::W) writer structure"] + impl crate::Writable for TIME {} + #[doc = "Timer time information"] + pub mod time { + #[doc = "Reader of register time"] + pub type R = crate::R; + #[doc = "Writer for register time"] + pub type W = crate::W; + #[doc = "Register time `reset()`'s with value 0"] + impl crate::ResetValue for super::TIME { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `second`"] + pub type SECOND_R = crate::R; + #[doc = "Write proxy for field `second`"] + pub struct SECOND_W<'a> { + w: &'a mut W, + } + impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | (((value as u32) & 0x3f) << 10); + self.w + } + } + #[doc = "Reader of field `minute`"] + pub type MINUTE_R = crate::R; + #[doc = "Write proxy for field `minute`"] + pub struct MINUTE_W<'a> { + w: &'a mut W, + } + impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | (((value as u32) & 0x3f) << 16); + self.w + } + } + #[doc = "Reader of field `hour`"] + pub type HOUR_R = crate::R; + #[doc = "Write proxy for field `hour`"] + pub struct HOUR_W<'a> { + w: &'a mut W, + } + impl<'a> HOUR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24); + self.w + } + } + impl R { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 24) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + } + } + #[doc = "Alarm date information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm_date](alarm_date) module"] + pub type ALARM_DATE = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ALARM_DATE; + #[doc = "`read()` method returns [alarm_date::R](alarm_date::R) reader structure"] + impl crate::Readable for ALARM_DATE {} + #[doc = "`write(|w| ..)` method takes [alarm_date::W](alarm_date::W) writer structure"] + impl crate::Writable for ALARM_DATE {} + #[doc = "Alarm date information"] + pub mod alarm_date { + #[doc = "Reader of register alarm_date"] + pub type R = crate::R; + #[doc = "Writer for register alarm_date"] + pub type W = crate::W; + #[doc = "Register alarm_date `reset()`'s with value 0"] + impl crate::ResetValue for super::ALARM_DATE { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `week`"] + pub type WEEK_R = crate::R; + #[doc = "Write proxy for field `week`"] + pub struct WEEK_W<'a> { + w: &'a mut W, + } + impl<'a> WEEK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); + self.w + } + } + #[doc = "Reader of field `day`"] + pub type DAY_R = crate::R; + #[doc = "Write proxy for field `day`"] + pub struct DAY_W<'a> { + w: &'a mut W, + } + impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8); + self.w + } + } + #[doc = "Reader of field `month`"] + pub type MONTH_R = crate::R; + #[doc = "Write proxy for field `month`"] + pub struct MONTH_W<'a> { + w: &'a mut W, + } + impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); + self.w + } + } + #[doc = "Reader of field `year`"] + pub type YEAR_R = crate::R; + #[doc = "Write proxy for field `year`"] + pub struct YEAR_W<'a> { + w: &'a mut W, + } + impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | (((value as u32) & 0x0fff) << 20); + self.w + } + } + impl R { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&self) -> WEEK_R { + WEEK_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 20) & 0x0fff) as u16) + } + } + impl W { + #[doc = "Bits 0:2 - Week. Range \\[0,6\\]. 0 is Sunday."] + #[inline(always)] + pub fn week(&mut self) -> WEEK_W { + WEEK_W { w: self } + } + #[doc = "Bits 8:12 - Day. Range \\[1,31\\] +or \\[1,30\\] +or \\[1,29\\] +or \\[1,28\\]"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 16:19 - Month. Range \\[1,12\\]"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 20:31 - Year. Range \\[0,99\\]"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + } + } + #[doc = "Alarm time information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm_time](alarm_time) module"] + pub type ALARM_TIME = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _ALARM_TIME; + #[doc = "`read()` method returns [alarm_time::R](alarm_time::R) reader structure"] + impl crate::Readable for ALARM_TIME {} + #[doc = "`write(|w| ..)` method takes [alarm_time::W](alarm_time::W) writer structure"] + impl crate::Writable for ALARM_TIME {} + #[doc = "Alarm time information"] + pub mod alarm_time { + #[doc = "Reader of register alarm_time"] + pub type R = crate::R; + #[doc = "Writer for register alarm_time"] + pub type W = crate::W; + #[doc = "Register alarm_time `reset()`'s with value 0"] + impl crate::ResetValue for super::ALARM_TIME { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `second`"] + pub type SECOND_R = crate::R; + #[doc = "Write proxy for field `second`"] + pub struct SECOND_W<'a> { + w: &'a mut W, + } + impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | (((value as u32) & 0x3f) << 10); + self.w + } + } + #[doc = "Reader of field `minute`"] + pub type MINUTE_R = crate::R; + #[doc = "Write proxy for field `minute`"] + pub struct MINUTE_W<'a> { + w: &'a mut W, + } + impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | (((value as u32) & 0x3f) << 16); + self.w + } + } + #[doc = "Reader of field `hour`"] + pub type HOUR_R = crate::R; + #[doc = "Write proxy for field `hour`"] + pub struct HOUR_W<'a> { + w: &'a mut W, + } + impl<'a> HOUR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24); + self.w + } + } + impl R { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 24) & 0x1f) as u8) + } + } + impl W { + #[doc = "Bits 10:15 - Second. Range \\[0,59\\]"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 16:21 - Minute. Range \\[0,59\\]"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 24:28 - Hour. Range \\[0,23\\]"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + } + } + #[doc = "Timer counter initial value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [initial_count](initial_count) module"] + pub type INITIAL_COUNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INITIAL_COUNT; + #[doc = "`read()` method returns [initial_count::R](initial_count::R) reader structure"] + impl crate::Readable for INITIAL_COUNT {} + #[doc = "`write(|w| ..)` method takes [initial_count::W](initial_count::W) writer structure"] + impl crate::Writable for INITIAL_COUNT {} + #[doc = "Timer counter initial value"] + pub mod initial_count { + #[doc = "Reader of register initial_count"] + pub type R = crate::R; + #[doc = "Writer for register initial_count"] + pub type W = crate::W; + #[doc = "Register initial_count `reset()`'s with value 0"] + impl crate::ResetValue for super::INITIAL_COUNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - RTC counter initial value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - RTC counter initial value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "Timer counter current value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [current_count](current_count) module"] + pub type CURRENT_COUNT = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _CURRENT_COUNT; + #[doc = "`read()` method returns [current_count::R](current_count::R) reader structure"] + impl crate::Readable for CURRENT_COUNT {} + #[doc = "`write(|w| ..)` method takes [current_count::W](current_count::W) writer structure"] + impl crate::Writable for CURRENT_COUNT {} + #[doc = "Timer counter current value"] + pub mod current_count { + #[doc = "Reader of register current_count"] + pub type R = crate::R; + #[doc = "Writer for register current_count"] + pub type W = crate::W; + #[doc = "Register current_count `reset()`'s with value 0"] + impl crate::ResetValue for super::CURRENT_COUNT { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `count`"] + pub type COUNT_R = crate::R; + #[doc = "Write proxy for field `count`"] + pub struct COUNT_W<'a> { + w: &'a mut W, + } + impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); + self.w + } + } + impl R { + #[doc = "Bits 0:31 - RTC counter current value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } + } + impl W { + #[doc = "Bits 0:31 - RTC counter current value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + } + } + #[doc = "RTC interrupt settings\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_ctrl](interrupt_ctrl) module"] + pub type INTERRUPT_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _INTERRUPT_CTRL; + #[doc = "`read()` method returns [interrupt_ctrl::R](interrupt_ctrl::R) reader structure"] + impl crate::Readable for INTERRUPT_CTRL {} + #[doc = "`write(|w| ..)` method takes [interrupt_ctrl::W](interrupt_ctrl::W) writer structure"] + impl crate::Writable for INTERRUPT_CTRL {} + #[doc = "RTC interrupt settings"] + pub mod interrupt_ctrl { + #[doc = "Reader of register interrupt_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register interrupt_ctrl"] + pub type W = crate::W; + #[doc = "Register interrupt_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::INTERRUPT_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `tick_enable`"] + pub type TICK_ENABLE_R = crate::R; + #[doc = "Write proxy for field `tick_enable`"] + pub struct TICK_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> TICK_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `alarm_enable`"] + pub type ALARM_ENABLE_R = crate::R; + #[doc = "Write proxy for field `alarm_enable`"] + pub struct ALARM_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> ALARM_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `tick_int_mode`"] + pub type TICK_INT_MODE_R = crate::R; + #[doc = "Write proxy for field `tick_int_mode`"] + pub struct TICK_INT_MODE_W<'a> { + w: &'a mut W, + } + impl<'a> TICK_INT_MODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2); + self.w + } + } + #[doc = "Reader of field `alarm_compare_mask`"] + pub type ALARM_COMPARE_MASK_R = crate::R; + #[doc = "Write proxy for field `alarm_compare_mask`"] + pub struct ALARM_COMPARE_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> ALARM_COMPARE_MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); + self.w + } + } + impl R { + #[doc = "Bit 0 - TICK_ENABLE"] + #[inline(always)] + pub fn tick_enable(&self) -> TICK_ENABLE_R { + TICK_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Alarm interrupt enable"] + #[inline(always)] + pub fn alarm_enable(&self) -> ALARM_ENABLE_R { + ALARM_ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Tick interrupt enable"] + #[inline(always)] + pub fn tick_int_mode(&self) -> TICK_INT_MODE_R { + TICK_INT_MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 24:31 - Alarm compare mask for interrupt"] + #[inline(always)] + pub fn alarm_compare_mask(&self) -> ALARM_COMPARE_MASK_R { + ALARM_COMPARE_MASK_R::new(((self.bits >> 24) & 0xff) as u8) + } + } + impl W { + #[doc = "Bit 0 - TICK_ENABLE"] + #[inline(always)] + pub fn tick_enable(&mut self) -> TICK_ENABLE_W { + TICK_ENABLE_W { w: self } + } + #[doc = "Bit 1 - Alarm interrupt enable"] + #[inline(always)] + pub fn alarm_enable(&mut self) -> ALARM_ENABLE_W { + ALARM_ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Tick interrupt enable"] + #[inline(always)] + pub fn tick_int_mode(&mut self) -> TICK_INT_MODE_W { + TICK_INT_MODE_W { w: self } + } + #[doc = "Bits 24:31 - Alarm compare mask for interrupt"] + #[inline(always)] + pub fn alarm_compare_mask(&mut self) -> ALARM_COMPARE_MASK_W { + ALARM_COMPARE_MASK_W { w: self } + } + } + } + #[doc = "RTC register settings\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [register_ctrl](register_ctrl) module"] + pub type REGISTER_CTRL = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _REGISTER_CTRL; + #[doc = "`read()` method returns [register_ctrl::R](register_ctrl::R) reader structure"] + impl crate::Readable for REGISTER_CTRL {} + #[doc = "`write(|w| ..)` method takes [register_ctrl::W](register_ctrl::W) writer structure"] + impl crate::Writable for REGISTER_CTRL {} + #[doc = "RTC register settings"] + pub mod register_ctrl { + #[doc = "Reader of register register_ctrl"] + pub type R = crate::R; + #[doc = "Writer for register register_ctrl"] + pub type W = crate::W; + #[doc = "Register register_ctrl `reset()`'s with value 0"] + impl crate::ResetValue for super::REGISTER_CTRL { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `read_enable`"] + pub type READ_ENABLE_R = crate::R; + #[doc = "Write proxy for field `read_enable`"] + pub struct READ_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> READ_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } + } + #[doc = "Reader of field `write_enable`"] + pub type WRITE_ENABLE_R = crate::R; + #[doc = "Write proxy for field `write_enable`"] + pub struct WRITE_ENABLE_W<'a> { + w: &'a mut W, + } + impl<'a> WRITE_ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); + self.w + } + } + #[doc = "Reader of field `timer_mask`"] + pub type TIMER_MASK_R = crate::R; + #[doc = "Write proxy for field `timer_mask`"] + pub struct TIMER_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> TIMER_MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 13)) | (((value as u32) & 0xff) << 13); + self.w + } + } + #[doc = "Reader of field `alarm_mask`"] + pub type ALARM_MASK_R = crate::R; + #[doc = "Write proxy for field `alarm_mask`"] + pub struct ALARM_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> ALARM_MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 21)) | (((value as u32) & 0xff) << 21); + self.w + } + } + #[doc = "Reader of field `initial_count_mask`"] + pub type INITIAL_COUNT_MASK_R = crate::R; + #[doc = "Write proxy for field `initial_count_mask`"] + pub struct INITIAL_COUNT_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> INITIAL_COUNT_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); + self.w + } + } + #[doc = "Reader of field `interrupt_register_mask`"] + pub type INTERRUPT_REGISTER_MASK_R = crate::R; + #[doc = "Write proxy for field `interrupt_register_mask`"] + pub struct INTERRUPT_REGISTER_MASK_W<'a> { + w: &'a mut W, + } + impl<'a> INTERRUPT_REGISTER_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); + self.w + } + } + impl R { + #[doc = "Bit 0 - RTC timer read enable"] + #[inline(always)] + pub fn read_enable(&self) -> READ_ENABLE_R { + READ_ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RTC timer write enable"] + #[inline(always)] + pub fn write_enable(&self) -> WRITE_ENABLE_R { + WRITE_ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 13:20 - RTC timer mask"] + #[inline(always)] + pub fn timer_mask(&self) -> TIMER_MASK_R { + TIMER_MASK_R::new(((self.bits >> 13) & 0xff) as u8) + } + #[doc = "Bits 21:28 - RTC alarm mask"] + #[inline(always)] + pub fn alarm_mask(&self) -> ALARM_MASK_R { + ALARM_MASK_R::new(((self.bits >> 21) & 0xff) as u8) + } + #[doc = "Bit 29 - RTC counter initial count value mask"] + #[inline(always)] + pub fn initial_count_mask(&self) -> INITIAL_COUNT_MASK_R { + INITIAL_COUNT_MASK_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - RTC interrupt register mask"] + #[inline(always)] + pub fn interrupt_register_mask(&self) -> INTERRUPT_REGISTER_MASK_R { + INTERRUPT_REGISTER_MASK_R::new(((self.bits >> 30) & 0x01) != 0) + } + } + impl W { + #[doc = "Bit 0 - RTC timer read enable"] + #[inline(always)] + pub fn read_enable(&mut self) -> READ_ENABLE_W { + READ_ENABLE_W { w: self } + } + #[doc = "Bit 1 - RTC timer write enable"] + #[inline(always)] + pub fn write_enable(&mut self) -> WRITE_ENABLE_W { + WRITE_ENABLE_W { w: self } + } + #[doc = "Bits 13:20 - RTC timer mask"] + #[inline(always)] + pub fn timer_mask(&mut self) -> TIMER_MASK_W { + TIMER_MASK_W { w: self } + } + #[doc = "Bits 21:28 - RTC alarm mask"] + #[inline(always)] + pub fn alarm_mask(&mut self) -> ALARM_MASK_W { + ALARM_MASK_W { w: self } + } + #[doc = "Bit 29 - RTC counter initial count value mask"] + #[inline(always)] + pub fn initial_count_mask(&mut self) -> INITIAL_COUNT_MASK_W { + INITIAL_COUNT_MASK_W { w: self } + } + #[doc = "Bit 30 - RTC interrupt register mask"] + #[inline(always)] + pub fn interrupt_register_mask(&mut self) -> INTERRUPT_REGISTER_MASK_W { + INTERRUPT_REGISTER_MASK_W { w: self } + } + } + } + #[doc = "Timer extended information\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extended](extended) module"] + pub type EXTENDED = crate::Reg; + #[allow(missing_docs)] + #[doc(hidden)] + pub struct _EXTENDED; + #[doc = "`read()` method returns [extended::R](extended::R) reader structure"] + impl crate::Readable for EXTENDED {} + #[doc = "`write(|w| ..)` method takes [extended::W](extended::W) writer structure"] + impl crate::Writable for EXTENDED {} + #[doc = "Timer extended information"] + pub mod extended { + #[doc = "Reader of register extended"] + pub type R = crate::R; + #[doc = "Writer for register extended"] + pub type W = crate::W; + #[doc = "Register extended `reset()`'s with value 0"] + impl crate::ResetValue for super::EXTENDED { + type Type = u32; + #[inline(always)] + fn reset_value() -> Self::Type { + 0 + } + } + #[doc = "Reader of field `century`"] + pub type CENTURY_R = crate::R; + #[doc = "Write proxy for field `century`"] + pub struct CENTURY_W<'a> { + w: &'a mut W, + } + impl<'a> CENTURY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f); + self.w + } + } + #[doc = "Is leap year. 1 is leap year, 0 is not leap year\n\nValue on reset: 0"] + #[derive(Clone, Copy, Debug, PartialEq)] + pub enum LEAP_YEAR_A { + #[doc = "0: 0 is not leap year"] + NOT_LEAP = 0, + #[doc = "1: 1 is leap year"] + LEAP = 1, + } + impl From for bool { + #[inline(always)] + fn from(variant: LEAP_YEAR_A) -> Self { + variant as u8 != 0 + } + } + #[doc = "Reader of field `leap_year`"] + pub type LEAP_YEAR_R = crate::R; + impl LEAP_YEAR_R { + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LEAP_YEAR_A { + match self.bits { + false => LEAP_YEAR_A::NOT_LEAP, + true => LEAP_YEAR_A::LEAP, + } + } + #[doc = "Checks if the value of the field is `NOT_LEAP`"] + #[inline(always)] + pub fn is_not_leap(&self) -> bool { + *self == LEAP_YEAR_A::NOT_LEAP + } + #[doc = "Checks if the value of the field is `LEAP`"] + #[inline(always)] + pub fn is_leap(&self) -> bool { + *self == LEAP_YEAR_A::LEAP + } + } + #[doc = "Write proxy for field `leap_year`"] + pub struct LEAP_YEAR_W<'a> { + w: &'a mut W, + } + impl<'a> LEAP_YEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LEAP_YEAR_A) -> &'a mut W { + { + self.bit(variant.into()) + } + } + #[doc = "0 is not leap year"] + #[inline(always)] + pub fn not_leap(self) -> &'a mut W { + self.variant(LEAP_YEAR_A::NOT_LEAP) + } + #[doc = "1 is leap year"] + #[inline(always)] + pub fn leap(self) -> &'a mut W { + self.variant(LEAP_YEAR_A::LEAP) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); + self.w + } + } + impl R { + #[doc = "Bits 0:4 - Century. Range \\[0,31\\]"] + #[inline(always)] + pub fn century(&self) -> CENTURY_R { + CENTURY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Is leap year. 1 is leap year, 0 is not leap year"] + #[inline(always)] + pub fn leap_year(&self) -> LEAP_YEAR_R { + LEAP_YEAR_R::new(((self.bits >> 5) & 0x01) != 0) + } + } + impl W { + #[doc = "Bits 0:4 - Century. Range \\[0,31\\]"] + #[inline(always)] + pub fn century(&mut self) -> CENTURY_W { + CENTURY_W { w: self } + } + #[doc = "Bit 5 - Is leap year. 1 is leap year, 0 is not leap year"] + #[inline(always)] + pub fn leap_year(&mut self) -> LEAP_YEAR_W { + LEAP_YEAR_W { w: self } + } + } + } +} +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "CLINT"] + pub CLINT: CLINT, + #[doc = "PLIC"] + pub PLIC: PLIC, + #[doc = "UARTHS"] + pub UARTHS: UARTHS, + #[doc = "GPIOHS"] + pub GPIOHS: GPIOHS, + #[doc = "KPU"] + pub KPU: KPU, + #[doc = "FFT"] + pub FFT: FFT, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "GPIO"] + pub GPIO: GPIO, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "UART2"] + pub UART2: UART2, + #[doc = "UART3"] + pub UART3: UART3, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "SPI3"] + pub SPI3: SPI3, + #[doc = "I2S0"] + pub I2S0: I2S0, + #[doc = "APU"] + pub APU: APU, + #[doc = "I2S1"] + pub I2S1: I2S1, + #[doc = "I2S2"] + pub I2S2: I2S2, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "I2C2"] + pub I2C2: I2C2, + #[doc = "FPIOA"] + pub FPIOA: FPIOA, + #[doc = "SHA256"] + pub SHA256: SHA256, + #[doc = "TIMER0"] + pub TIMER0: TIMER0, + #[doc = "TIMER1"] + pub TIMER1: TIMER1, + #[doc = "TIMER2"] + pub TIMER2: TIMER2, + #[doc = "WDT0"] + pub WDT0: WDT0, + #[doc = "WDT1"] + pub WDT1: WDT1, + #[doc = "OTP"] + pub OTP: OTP, + #[doc = "DVP"] + pub DVP: DVP, + #[doc = "SYSCTL"] + pub SYSCTL: SYSCTL, + #[doc = "AES"] + pub AES: AES, + #[doc = "RTC"] + pub RTC: RTC, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + riscv::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + //Some(unsafe { Peripherals::steal() }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + CLINT: CLINT { + _marker: PhantomData, + }, + PLIC: PLIC { + _marker: PhantomData, + }, + UARTHS: UARTHS { + _marker: PhantomData, + }, + GPIOHS: GPIOHS { + _marker: PhantomData, + }, + KPU: KPU { + _marker: PhantomData, + }, + FFT: FFT { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + GPIO: GPIO { + _marker: PhantomData, + }, + UART1: UART1 { + _marker: PhantomData, + }, + UART2: UART2 { + _marker: PhantomData, + }, + UART3: UART3 { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + SPI3: SPI3 { + _marker: PhantomData, + }, + I2S0: I2S0 { + _marker: PhantomData, + }, + APU: APU { + _marker: PhantomData, + }, + I2S1: I2S1 { + _marker: PhantomData, + }, + I2S2: I2S2 { + _marker: PhantomData, + }, + I2C0: I2C0 { + _marker: PhantomData, + }, + I2C1: I2C1 { + _marker: PhantomData, + }, + I2C2: I2C2 { + _marker: PhantomData, + }, + FPIOA: FPIOA { + _marker: PhantomData, + }, + SHA256: SHA256 { + _marker: PhantomData, + }, + TIMER0: TIMER0 { + _marker: PhantomData, + }, + TIMER1: TIMER1 { + _marker: PhantomData, + }, + TIMER2: TIMER2 { + _marker: PhantomData, + }, + WDT0: WDT0 { + _marker: PhantomData, + }, + WDT1: WDT1 { + _marker: PhantomData, + }, + OTP: OTP { + _marker: PhantomData, + }, + DVP: DVP { + _marker: PhantomData, + }, + SYSCTL: SYSCTL { + _marker: PhantomData, + }, + AES: AES { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + } + } +} diff --git a/third-party/k210-pac/update.sh b/third-party/k210-pac/update.sh new file mode 100755 index 00000000..c4d3ecc1 --- /dev/null +++ b/third-party/k210-pac/update.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash +set -x +set -e + +rm -rf src +mkdir src +svd2rust --target riscv -i k210.svd +mv lib.rs src/ +cargo fmt diff --git a/third-party/k210-soc/.gitignore b/third-party/k210-soc/.gitignore new file mode 100644 index 00000000..77147e20 --- /dev/null +++ b/third-party/k210-soc/.gitignore @@ -0,0 +1,3 @@ +/target +Cargo.lock +.idea/ diff --git a/third-party/k210-soc/Cargo.toml b/third-party/k210-soc/Cargo.toml new file mode 100644 index 00000000..fc233e88 --- /dev/null +++ b/third-party/k210-soc/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "k210-soc" +version = "0.1.0" +authors = ["Yifan Wu "] +edition = "2018" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +k210-hal = { path = "../k210-hal" } +k210-pac = { path = "../k210-pac" } +riscv = { path = "../riscv", features = ["inline-asm"] } diff --git a/third-party/k210-soc/README.md b/third-party/k210-soc/README.md new file mode 100644 index 00000000..8ecd2e33 --- /dev/null +++ b/third-party/k210-soc/README.md @@ -0,0 +1 @@ +From [here](https://github.com/laanwj/k210-sdk-stuff/tree/master/rust/k210-shared/src/soc). \ No newline at end of file diff --git a/third-party/k210-soc/src/dmac.rs b/third-party/k210-soc/src/dmac.rs new file mode 100644 index 00000000..55885481 --- /dev/null +++ b/third-party/k210-soc/src/dmac.rs @@ -0,0 +1,637 @@ +#![allow(unused)] +#![allow(non_camel_case_types)] + +//! DMAC peripheral +//use k210_hal::pac; +use k210_pac as pac; +use pac::dmac::channel::cfg::{TT_FC_A,HS_SEL_SRC_A}; +use pac::dmac::channel::ctl::{SMS_A}; + +use super::sysctl; + +/** Extension trait for adding configure() to DMAC peripheral */ +pub trait DMACExt: Sized { + /// Constrains DVP peripheral + fn configure(self) -> DMAC; +} + +impl DMACExt for pac::DMAC { + fn configure(self) -> DMAC { DMAC::new(self) } +} + +/** DMAC peripheral abstraction */ +pub struct DMAC { + dmac: pac::DMAC, +} + +/* +typedef struct _dmac_context +{ + dmac_channel_number_t dmac_channel; + plic_irq_callback_t callback; + void *ctx; +} dmac_context_t; + +dmac_context_t dmac_context[6]; +*/ + +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum src_dst_select { + SRC = 0x1, + DST = 0x2, + SRC_DST = 0x3, +} + +pub use super::sysctl::dma_channel; +pub type master_number = pac::dmac::channel::ctl::SMS_A; +pub type address_increment = pac::dmac::channel::ctl::SINC_A; +pub type burst_length = pac::dmac::channel::ctl::SRC_MSIZE_A; +pub type transfer_width = pac::dmac::channel::ctl::SRC_TR_WIDTH_A; + +/** Return whether a specific address considered considered memory or peripheral */ +fn is_memory(address: u64) -> bool { + let mem_len = 6 * 1024 * 1024; + let mem_no_cache_len = 8 * 1024 * 1024; + // Note: This comes from the Kendryte SDK as-is. No, I have no idea why the AES accelerator + // input address 0x50450040 is considered memory, either. + ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) + || ((address >= 0x40000000) && (address < 0x40000000 + mem_no_cache_len)) + || (address == 0x50450040) +} + +impl DMAC { + fn new(dmac: pac::DMAC) -> Self { + let rv = Self { dmac }; + rv.init(); + rv + } + + /** Get DMAC ID */ + pub fn read_id(&self) -> u64 { + return self.dmac.id.read().bits(); + } + + /** Get DMAC version */ + pub fn read_version(&self) -> u64 { + return self.dmac.compver.read().bits(); + } + + /** Get AXI ID for channel */ + pub fn read_channel_id(&self, channel_num: dma_channel) -> u64 { + return self.dmac.channel[channel_num.idx()].axi_id.read().bits(); + } + + /** Enable DMAC peripheral. */ + fn enable(&self) { + self.dmac.cfg.modify(|_,w| w.dmac_en().set_bit() + .int_en().set_bit()); + } + + /** Disable DMAC peripheral. */ + pub fn disable(&self) { + self.dmac.cfg.modify(|_,w| w.dmac_en().clear_bit() + .int_en().clear_bit()); + } + + pub fn src_transaction_complete_int_enable(&self, channel_num: dma_channel) { + self.dmac.channel[channel_num.idx()].intstatus_en.modify( + |_,w| w.src_transcomp().set_bit()); + } + + /** Enable a DMA channel. */ + pub fn channel_enable(&self, channel_num: dma_channel) { + use dma_channel::*; + // Note: chX bit names start counting from 1, while channels start counting from 0 + match channel_num { + CHANNEL0 => { + self.dmac.chen.modify(|_,w| w.ch1_en().set_bit() + .ch1_en_we().set_bit()); + } + CHANNEL1 => { + self.dmac.chen.modify(|_,w| w.ch2_en().set_bit() + .ch2_en_we().set_bit()); + } + CHANNEL2 => { + self.dmac.chen.modify(|_,w| w.ch3_en().set_bit() + .ch3_en_we().set_bit()); + } + CHANNEL3 => { + self.dmac.chen.modify(|_,w| w.ch4_en().set_bit() + .ch4_en_we().set_bit()); + } + CHANNEL4 => { + self.dmac.chen.modify(|_,w| w.ch5_en().set_bit() + .ch5_en_we().set_bit()); + } + CHANNEL5 => { + self.dmac.chen.modify(|_,w| w.ch6_en().set_bit() + .ch6_en_we().set_bit()); + } + } + } + + /** Disable a DMA channel. */ + pub fn channel_disable(&self, channel_num: dma_channel) { + use dma_channel::*; + // Note: chX bit names start counting from 1, while channels start counting from 0 + match channel_num { + CHANNEL0 => { + self.dmac.chen.modify(|_,w| w.ch1_en().clear_bit() + .ch1_en_we().set_bit()); + } + CHANNEL1 => { + self.dmac.chen.modify(|_,w| w.ch2_en().clear_bit() + .ch2_en_we().set_bit()); + } + CHANNEL2 => { + self.dmac.chen.modify(|_,w| w.ch3_en().clear_bit() + .ch3_en_we().set_bit()); + } + CHANNEL3 => { + self.dmac.chen.modify(|_,w| w.ch4_en().clear_bit() + .ch4_en_we().set_bit()); + } + CHANNEL4 => { + self.dmac.chen.modify(|_,w| w.ch5_en().clear_bit() + .ch5_en_we().set_bit()); + } + CHANNEL5 => { + self.dmac.chen.modify(|_,w| w.ch6_en().clear_bit() + .ch6_en_we().set_bit()); + } + } + } + + /** Check if a DMA channel is busy. */ + pub fn check_channel_busy(&self, channel_num: dma_channel) -> bool { + use dma_channel::*; + match channel_num { + CHANNEL0 => self.dmac.chen.read().ch1_en().bit(), + CHANNEL1 => self.dmac.chen.read().ch2_en().bit(), + CHANNEL2 => self.dmac.chen.read().ch3_en().bit(), + CHANNEL3 => self.dmac.chen.read().ch4_en().bit(), + CHANNEL4 => self.dmac.chen.read().ch5_en().bit(), + CHANNEL5 => self.dmac.chen.read().ch6_en().bit(), + } + // Note: Kendryte SDK writes back the value after reading it, + // is this necessary? It seems not. + } + + pub fn set_list_master_select(&self, channel_num: dma_channel, sd_sel: src_dst_select, mst_num: master_number) -> Result<(),()> { + if !self.check_channel_busy(channel_num) { + use src_dst_select::*; + self.dmac.channel[channel_num.idx()].ctl.modify(|_,w| { + let w = if sd_sel == SRC || sd_sel == SRC_DST { + w.sms().variant(mst_num) + } else { + w + }; + if sd_sel == DST || sd_sel == SRC_DST { + w.dms().variant(mst_num) + } else { + w + } + }); + // Note: there's some weird tmp|= line here in the Kendryte SDK + // with the result going unused. I've decided to leave this out + // because I assume it's another C UB workaround. + Ok(()) + } else { + Err(()) + } + } + + pub fn enable_common_interrupt_status(&self) { + self.dmac.com_intstatus_en.modify(|_,w| + w.slvif_dec_err().set_bit() + .slvif_wr2ro_err().set_bit() + .slvif_rd2wo_err().set_bit() + .slvif_wronhold_err().set_bit() + .slvif_undefinedreg_dec_err().set_bit() + ); + } + + pub fn enable_common_interrupt_signal(&self) { + self.dmac.com_intsignal_en.modify(|_,w| + w.slvif_dec_err().set_bit() + .slvif_wr2ro_err().set_bit() + .slvif_rd2wo_err().set_bit() + .slvif_wronhold_err().set_bit() + .slvif_undefinedreg_dec_err().set_bit() + ); + } + + fn enable_channel_interrupt(&self, channel_num: dma_channel) { + unsafe { + let ch = &self.dmac.channel[channel_num.idx()]; + ch.intclear.write(|w| w.bits(0xffffffff)); + ch.intstatus_en.write(|w| w.bits(0x2)); + } + } + + pub fn disable_channel_interrupt(&self, channel_num: dma_channel) { + unsafe { + self.dmac.channel[channel_num.idx()].intstatus_en.write( + |w| w.bits(0x0)); + } + } + + fn channel_interrupt_clear(&self, channel_num: dma_channel) { + unsafe { + self.dmac.channel[channel_num.idx()].intclear.write( + |w| w.bits(0xffffffff)); + } + } + + /** Set DMA channel parameters. */ + pub fn set_channel_param(&self, channel_num: dma_channel, + src: u64, dest: u64, src_inc: address_increment, dest_inc: address_increment, + burst_size: burst_length, + trans_width: transfer_width, + block_size: u32) { + unsafe { + let ch = &self.dmac.channel[channel_num.idx()]; + let src_is_mem = is_memory(src); + let dest_is_mem = is_memory(dest); + let flow_control = match (src_is_mem, dest_is_mem) { + (false, false) => TT_FC_A::PRF2PRF_DMA, + (true, false) => TT_FC_A::MEM2PRF_DMA, + (false, true) => TT_FC_A::PRF2MEM_DMA, + (true, true) => TT_FC_A::MEM2MEM_DMA, + }; + + /* + * cfg register must configure before ts_block and + * sar dar register + */ + ch.cfg.modify(|_,w| + w.tt_fc().variant(flow_control) + .hs_sel_src().variant(if src_is_mem { HS_SEL_SRC_A::SOFTWARE } else { HS_SEL_SRC_A::HARDWARE } ) + .hs_sel_dst().variant(if dest_is_mem { HS_SEL_SRC_A::SOFTWARE } else { HS_SEL_SRC_A::HARDWARE } ) + // Note: from SVD: "Assign a hardware handshaking interface to source of channel", + // these are set using sysctl::dma_select; this configuration seems to indicate + // that in principle, it's possible to use a different source and destination + // handshaking interface for a channel, but that would sacrifice the interface of + // another channel. + .src_per().bits(channel_num as u8) + .dst_per().bits(channel_num as u8) + .src_multblk_type().bits(0) + .dst_multblk_type().bits(0) + ); + + ch.sar.write(|w| w.bits(src)); + ch.dar.write(|w| w.bits(dest)); + + ch.ctl.modify(|_,w| + w.sms().variant(SMS_A::AXI_MASTER_1) + .dms().variant(SMS_A::AXI_MASTER_2) + /* master select */ + .sinc().variant(src_inc) + .dinc().variant(dest_inc) + /* address incrememt */ + .src_tr_width().variant(trans_width) + .dst_tr_width().variant(trans_width) + /* transfer width */ + .src_msize().variant(burst_size) + .dst_msize().variant(burst_size) + ); + + ch.block_ts.write(|w| w.block_ts().bits(block_size - 1)); + /*the number of (blcok_ts +1) data of width SRC_TR_WIDTF to be */ + /* transferred in a dma block transfer */ + } + } + + /* + pub void set_address(&self, dmac_channel_number_t channel_num, uint64_t src_addr, + uint64_t dst_addr) { + writeq(src_addr, &dmac->channel[channel_num].sar); + writeq(dst_addr, &dmac->channel[channel_num].dar); + } + */ + + /* + pub void set_block_ts(&self, dmac_channel_number_t channel_num, + uint32_t block_size) { + uint32_t block_ts; + + block_ts = block_size & 0x3fffff; + writeq(block_ts, &dmac->channel[channel_num].block_ts); + } + */ + + /* + pub void source_control(&self, dmac_channel_number_t channel_num, + dmac_master_number_t master_select, + dmac_address_increment_t address_mode, + dmac_transfer_width_t tr_width, + dmac_burst_length_t burst_length) { + dmac_ch_ctl_u_t ctl_u; + + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + ctl_u.ch_ctl.sms = master_select; + ctl_u.ch_ctl.sinc = address_mode; + ctl_u.ch_ctl.src_tr_width = tr_width; + ctl_u.ch_ctl.src_msize = burst_length; + + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + } + */ + + /* + pub void master_control(&self, dmac_channel_number_t channel_num, + dmac_master_number_t master_select, + dmac_address_increment_t address_mode, + dmac_transfer_width_t tr_width, + dmac_burst_length_t burst_length) { + dmac_ch_ctl_u_t ctl_u; + + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + ctl_u.ch_ctl.dms = master_select; + ctl_u.ch_ctl.dinc = address_mode; + ctl_u.ch_ctl.dst_tr_width = tr_width; + ctl_u.ch_ctl.dst_msize = burst_length; + + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + } + */ + + /* + pub void set_source_transfer_control(&self, dmac_channel_number_t channel_num, + dmac_multiblk_transfer_type_t transfer_type, + dmac_sw_hw_hs_select_t handshak_select) { + dmac_ch_cfg_u_t cfg_u; + + cfg_u.data = readq(&dmac->channel[channel_num].cfg); + cfg_u.ch_cfg.src_multblk_type = transfer_type; + cfg_u.ch_cfg.hs_sel_src = handshak_select; + + writeq(cfg_u.data, &dmac->channel[channel_num].cfg); + } + */ + + /* + pub void set_destination_transfer_control(&self, dmac_channel_number_t channel_num, + dmac_multiblk_transfer_type_t transfer_type, + dmac_sw_hw_hs_select_t handshak_select) { + dmac_ch_cfg_u_t cfg_u; + + cfg_u.data = readq(&dmac->channel[channel_num].cfg); + cfg_u.ch_cfg.dst_multblk_type = transfer_type; + cfg_u.ch_cfg.hs_sel_dst = handshak_select; + + writeq(cfg_u.data, &dmac->channel[channel_num].cfg); + } + */ + + /* + pub void set_flow_control(&self, dmac_channel_number_t channel_num, + dmac_transfer_flow_t flow_control) { + dmac_ch_cfg_u_t cfg_u; + + cfg_u.data = readq(&dmac->channel[channel_num].cfg); + cfg_u.ch_cfg.tt_fc = flow_control; + + writeq(cfg_u.data, &dmac->channel[channel_num].cfg); + } + */ + + /* + pub void set_linked_list_addr_point(&self, dmac_channel_number_t channel_num, + uint64_t *addr) { + dmac_ch_llp_u_t llp_u; + + llp_u.data = readq(&dmac->channel[channel_num].llp); + /* Cast pointer to uint64_t */ + llp_u.llp.loc = (uint64_t)addr; + writeq(llp_u.data, &dmac->channel[channel_num].llp); + } + */ + + /** Initialize DMA controller */ + pub fn init(&self) { + sysctl::clock_enable(sysctl::clock::DMA); + + /* reset dmac */ + self.dmac.reset.modify(|_,w| w.rst().set_bit()); + while self.dmac.reset.read().rst().bit() { + // IDLE + } + + /* clear common register interrupt */ + self.dmac.com_intclear.modify(|_,w| + w.slvif_dec_err().set_bit() + .slvif_wr2ro_err().set_bit() + .slvif_rd2wo_err().set_bit() + .slvif_wronhold_err().set_bit() + .slvif_undefinedreg_dec_err().set_bit() + ); + + /* disable dmac and disable interrupt */ + self.dmac.cfg.modify(|_,w| + w.dmac_en().clear_bit() + .int_en().clear_bit() + ); + + while self.dmac.cfg.read().bits() != 0 { + // IDLE + } + /* disable all channel before configure */ + /* Note: changed from the SDK code, which doesn't clear channel 4 and 5, + * and doesn't set associated _we bits */ + self.dmac.chen.modify(|_,w| + w.ch1_en().clear_bit() + .ch1_en_we().set_bit() + .ch2_en().clear_bit() + .ch2_en_we().set_bit() + .ch3_en().clear_bit() + .ch3_en_we().set_bit() + .ch4_en().clear_bit() + .ch4_en_we().set_bit() + .ch5_en().clear_bit() + .ch5_en_we().set_bit() + ); + + self.enable(); + } + +// TODO: list (scatter/gather) functionality + + /* + static void list_add(struct list_head_t *new, struct list_head_t *prev, + struct list_head_t *next) { + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; + } + */ + + /* + pub void list_add_tail(struct list_head_t *new, struct list_head_t *head) { + list_add(new, head->prev, head); + } + */ + + /* + pub void INIT_LIST_HEAD(struct list_head_t *list) { + list->next = list; + list->prev = list; + } + */ + + /* + pub void link_list_item(dmac_channel_number_t channel_num, + uint8_t LLI_row_num, int8_t LLI_last_row, + dmac_lli_item_t *lli_item, + dmac_channel_config_t *cfg_param) { + dmac_ch_ctl_u_t ctl; + dmac_ch_llp_u_t llp_u; + + lli_item[LLI_row_num].sar = cfg_param->sar; + lli_item[LLI_row_num].dar = cfg_param->dar; + + ctl.data = readq(&dmac->channel[channel_num].ctl); + ctl.ch_ctl.sms = cfg_param->ctl_sms; + ctl.ch_ctl.dms = cfg_param->ctl_dms; + ctl.ch_ctl.sinc = cfg_param->ctl_sinc; + ctl.ch_ctl.dinc = cfg_param->ctl_dinc; + ctl.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width; + ctl.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width; + ctl.ch_ctl.src_msize = cfg_param->ctl_src_msize; + ctl.ch_ctl.dst_msize = cfg_param->ctl_drc_msize; + ctl.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en; + ctl.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en; + + if(LLI_last_row != LAST_ROW) + { + ctl.ch_ctl.shadowreg_or_lli_valid = 1; + ctl.ch_ctl.shadowreg_or_lli_last = 0; + } else + { + ctl.ch_ctl.shadowreg_or_lli_valid = 1; + ctl.ch_ctl.shadowreg_or_lli_last = 1; + } + + lli_item[LLI_row_num].ctl = ctl.data; + + lli_item[LLI_row_num].ch_block_ts = cfg_param->ctl_block_ts; + lli_item[LLI_row_num].sstat = 0; + lli_item[LLI_row_num].dstat = 0; + + llp_u.data = readq(&dmac->channel[channel_num].llp); + + if(LLI_last_row != LAST_ROW) + llp_u.llp.loc = ((uint64_t)&lli_item[LLI_row_num + 1]) >> 6; + else + llp_u.llp.loc = 0; + + lli_item[LLI_row_num].llp = llp_u.data; + } + + pub void update_shadow_register(&self, dmac_channel_number_t channel_num, + int8_t last_block, dmac_channel_config_t *cfg_param) { + dmac_ch_ctl_u_t ctl_u; + + do + { + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + } while(ctl_u.ch_ctl.shadowreg_or_lli_valid); + + writeq(cfg_param->sar, &dmac->channel[channel_num].sar); + writeq(cfg_param->dar, &dmac->channel[channel_num].dar); + writeq(cfg_param->ctl_block_ts, &dmac->channel[channel_num].block_ts); + + ctl_u.ch_ctl.sms = cfg_param->ctl_sms; + ctl_u.ch_ctl.dms = cfg_param->ctl_dms; + ctl_u.ch_ctl.sinc = cfg_param->ctl_sinc; + ctl_u.ch_ctl.dinc = cfg_param->ctl_dinc; + ctl_u.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width; + ctl_u.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width; + ctl_u.ch_ctl.src_msize = cfg_param->ctl_src_msize; + ctl_u.ch_ctl.dst_msize = cfg_param->ctl_drc_msize; + ctl_u.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en; + ctl_u.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en; + if(last_block != LAST_ROW) + { + ctl_u.ch_ctl.shadowreg_or_lli_valid = 1; + ctl_u.ch_ctl.shadowreg_or_lli_last = 0; + } else + { + ctl_u.ch_ctl.shadowreg_or_lli_valid = 1; + ctl_u.ch_ctl.shadowreg_or_lli_last = 1; + } + + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + writeq(0, &dmac->channel[channel_num].blk_tfr); + } + */ + + /* + pub void set_shadow_invalid_flag(&self, dmac_channel_number_t channel_num) { + dmac_ch_ctl_u_t ctl_u; + + ctl_u.data = readq(&dmac->channel[channel_num].ctl); + ctl_u.ch_ctl.shadowreg_or_lli_valid = 1; + ctl_u.ch_ctl.shadowreg_or_lli_last = 0; + writeq(ctl_u.data, &dmac->channel[channel_num].ctl); + } + */ + + /** Start a single DMA transfer. */ + pub fn set_single_mode(&self, channel_num: dma_channel, + src: u64, dest: u64, src_inc: address_increment, + dest_inc: address_increment, + burst_size: burst_length, + trans_width: transfer_width, + block_size: u32) { + self.channel_interrupt_clear(channel_num); + self.channel_disable(channel_num); + self.wait_idle(channel_num); + self.set_channel_param(channel_num, src, dest, src_inc, dest_inc, + burst_size, trans_width, block_size); + self.enable(); + self.channel_enable(channel_num); + } + + /* + pub int is_done(&self, dmac_channel_number_t channel_num) { + if(readq(&dmac->channel[channel_num].intstatus) & 0x2) + return 1; + else + return 0; + } + */ + + /** Wait for dmac work done. */ + pub fn wait_done(&self, channel_num: dma_channel) { + self.wait_idle(channel_num); + } + + /** Determine if a DMA channel is idle or not. */ + pub fn is_idle(&self, channel_num: dma_channel) -> bool { + !self.check_channel_busy(channel_num) + } + + /** Wait for a DMA channel to be idle. */ + pub fn wait_idle(&self, channel_num: dma_channel) { + while !self.is_idle(channel_num) { + } + self.channel_interrupt_clear(channel_num); /* clear interrupt */ + } + + /* + pub void set_src_dest_length(&self, dmac_channel_number_t channel_num, const void *src, void *dest, size_t len) { + if(src != NULL) + dmac->channel[channel_num].sar = (uint64_t)src; + if(dest != NULL) + dmac->channel[channel_num].dar = (uint64_t)dest; + if(len > 0) + dmac_set_block_ts(channel_num, len - 1); + dmac_channel_enable(channel_num); + } + */ + +// TODO: completion IRQ functionality + +} diff --git a/third-party/k210-soc/src/fpioa.rs b/third-party/k210-soc/src/fpioa.rs new file mode 100644 index 00000000..83662e19 --- /dev/null +++ b/third-party/k210-soc/src/fpioa.rs @@ -0,0 +1,481 @@ +//! FPIOA peripheral + +#![allow(unused)] +#![allow(non_camel_case_types)] + +//use k210_hal::pac; +use k210_pac as pac; + +#[derive(Copy, Clone)] +pub enum function { + JTAG_TCLK = 0, /* JTAG Test Clock */ + JTAG_TDI = 1, /* JTAG Test Data In */ + JTAG_TMS = 2, /* JTAG Test Mode Select */ + JTAG_TDO = 3, /* JTAG Test Data Out */ + SPI0_D0 = 4, /* SPI0 Data 0 */ + SPI0_D1 = 5, /* SPI0 Data 1 */ + SPI0_D2 = 6, /* SPI0 Data 2 */ + SPI0_D3 = 7, /* SPI0 Data 3 */ + SPI0_D4 = 8, /* SPI0 Data 4 */ + SPI0_D5 = 9, /* SPI0 Data 5 */ + SPI0_D6 = 10, /* SPI0 Data 6 */ + SPI0_D7 = 11, /* SPI0 Data 7 */ + SPI0_SS0 = 12, /* SPI0 Chip Select 0 */ + SPI0_SS1 = 13, /* SPI0 Chip Select 1 */ + SPI0_SS2 = 14, /* SPI0 Chip Select 2 */ + SPI0_SS3 = 15, /* SPI0 Chip Select 3 */ + SPI0_ARB = 16, /* SPI0 Arbitration */ + SPI0_SCLK = 17, /* SPI0 Serial Clock */ + UARTHS_RX = 18, /* UART High speed Receiver */ + UARTHS_TX = 19, /* UART High speed Transmitter */ + RESV6 = 20, /* Reserved function */ + RESV7 = 21, /* Reserved function */ + CLK_SPI1 = 22, /* Clock SPI1 */ + CLK_I2C1 = 23, /* Clock I2C1 */ + GPIOHS0 = 24, /* GPIO High speed 0 */ + GPIOHS1 = 25, /* GPIO High speed 1 */ + GPIOHS2 = 26, /* GPIO High speed 2 */ + GPIOHS3 = 27, /* GPIO High speed 3 */ + GPIOHS4 = 28, /* GPIO High speed 4 */ + GPIOHS5 = 29, /* GPIO High speed 5 */ + GPIOHS6 = 30, /* GPIO High speed 6 */ + GPIOHS7 = 31, /* GPIO High speed 7 */ + GPIOHS8 = 32, /* GPIO High speed 8 */ + GPIOHS9 = 33, /* GPIO High speed 9 */ + GPIOHS10 = 34, /* GPIO High speed 10 */ + GPIOHS11 = 35, /* GPIO High speed 11 */ + GPIOHS12 = 36, /* GPIO High speed 12 */ + GPIOHS13 = 37, /* GPIO High speed 13 */ + GPIOHS14 = 38, /* GPIO High speed 14 */ + GPIOHS15 = 39, /* GPIO High speed 15 */ + GPIOHS16 = 40, /* GPIO High speed 16 */ + GPIOHS17 = 41, /* GPIO High speed 17 */ + GPIOHS18 = 42, /* GPIO High speed 18 */ + GPIOHS19 = 43, /* GPIO High speed 19 */ + GPIOHS20 = 44, /* GPIO High speed 20 */ + GPIOHS21 = 45, /* GPIO High speed 21 */ + GPIOHS22 = 46, /* GPIO High speed 22 */ + GPIOHS23 = 47, /* GPIO High speed 23 */ + GPIOHS24 = 48, /* GPIO High speed 24 */ + GPIOHS25 = 49, /* GPIO High speed 25 */ + GPIOHS26 = 50, /* GPIO High speed 26 */ + GPIOHS27 = 51, /* GPIO High speed 27 */ + GPIOHS28 = 52, /* GPIO High speed 28 */ + GPIOHS29 = 53, /* GPIO High speed 29 */ + GPIOHS30 = 54, /* GPIO High speed 30 */ + GPIOHS31 = 55, /* GPIO High speed 31 */ + GPIO0 = 56, /* GPIO pin 0 */ + GPIO1 = 57, /* GPIO pin 1 */ + GPIO2 = 58, /* GPIO pin 2 */ + GPIO3 = 59, /* GPIO pin 3 */ + GPIO4 = 60, /* GPIO pin 4 */ + GPIO5 = 61, /* GPIO pin 5 */ + GPIO6 = 62, /* GPIO pin 6 */ + GPIO7 = 63, /* GPIO pin 7 */ + UART1_RX = 64, /* UART1 Receiver */ + UART1_TX = 65, /* UART1 Transmitter */ + UART2_RX = 66, /* UART2 Receiver */ + UART2_TX = 67, /* UART2 Transmitter */ + UART3_RX = 68, /* UART3 Receiver */ + UART3_TX = 69, /* UART3 Transmitter */ + SPI1_D0 = 70, /* SPI1 Data 0 */ + SPI1_D1 = 71, /* SPI1 Data 1 */ + SPI1_D2 = 72, /* SPI1 Data 2 */ + SPI1_D3 = 73, /* SPI1 Data 3 */ + SPI1_D4 = 74, /* SPI1 Data 4 */ + SPI1_D5 = 75, /* SPI1 Data 5 */ + SPI1_D6 = 76, /* SPI1 Data 6 */ + SPI1_D7 = 77, /* SPI1 Data 7 */ + SPI1_SS0 = 78, /* SPI1 Chip Select 0 */ + SPI1_SS1 = 79, /* SPI1 Chip Select 1 */ + SPI1_SS2 = 80, /* SPI1 Chip Select 2 */ + SPI1_SS3 = 81, /* SPI1 Chip Select 3 */ + SPI1_ARB = 82, /* SPI1 Arbitration */ + SPI1_SCLK = 83, /* SPI1 Serial Clock */ + SPI_SLAVE_D0 = 84, /* SPI Slave Data 0 */ + SPI_SLAVE_SS = 85, /* SPI Slave Select */ + SPI_SLAVE_SCLK = 86, /* SPI Slave Serial Clock */ + I2S0_MCLK = 87, /* I2S0 Master Clock */ + I2S0_SCLK = 88, /* I2S0 Serial Clock(BCLK) */ + I2S0_WS = 89, /* I2S0 Word Select(LRCLK) */ + I2S0_IN_D0 = 90, /* I2S0 Serial Data Input 0 */ + I2S0_IN_D1 = 91, /* I2S0 Serial Data Input 1 */ + I2S0_IN_D2 = 92, /* I2S0 Serial Data Input 2 */ + I2S0_IN_D3 = 93, /* I2S0 Serial Data Input 3 */ + I2S0_OUT_D0 = 94, /* I2S0 Serial Data Output 0 */ + I2S0_OUT_D1 = 95, /* I2S0 Serial Data Output 1 */ + I2S0_OUT_D2 = 96, /* I2S0 Serial Data Output 2 */ + I2S0_OUT_D3 = 97, /* I2S0 Serial Data Output 3 */ + I2S1_MCLK = 98, /* I2S1 Master Clock */ + I2S1_SCLK = 99, /* I2S1 Serial Clock(BCLK) */ + I2S1_WS = 100, /* I2S1 Word Select(LRCLK) */ + I2S1_IN_D0 = 101, /* I2S1 Serial Data Input 0 */ + I2S1_IN_D1 = 102, /* I2S1 Serial Data Input 1 */ + I2S1_IN_D2 = 103, /* I2S1 Serial Data Input 2 */ + I2S1_IN_D3 = 104, /* I2S1 Serial Data Input 3 */ + I2S1_OUT_D0 = 105, /* I2S1 Serial Data Output 0 */ + I2S1_OUT_D1 = 106, /* I2S1 Serial Data Output 1 */ + I2S1_OUT_D2 = 107, /* I2S1 Serial Data Output 2 */ + I2S1_OUT_D3 = 108, /* I2S1 Serial Data Output 3 */ + I2S2_MCLK = 109, /* I2S2 Master Clock */ + I2S2_SCLK = 110, /* I2S2 Serial Clock(BCLK) */ + I2S2_WS = 111, /* I2S2 Word Select(LRCLK) */ + I2S2_IN_D0 = 112, /* I2S2 Serial Data Input 0 */ + I2S2_IN_D1 = 113, /* I2S2 Serial Data Input 1 */ + I2S2_IN_D2 = 114, /* I2S2 Serial Data Input 2 */ + I2S2_IN_D3 = 115, /* I2S2 Serial Data Input 3 */ + I2S2_OUT_D0 = 116, /* I2S2 Serial Data Output 0 */ + I2S2_OUT_D1 = 117, /* I2S2 Serial Data Output 1 */ + I2S2_OUT_D2 = 118, /* I2S2 Serial Data Output 2 */ + I2S2_OUT_D3 = 119, /* I2S2 Serial Data Output 3 */ + RESV0 = 120, /* Reserved function */ + RESV1 = 121, /* Reserved function */ + RESV2 = 122, /* Reserved function */ + RESV3 = 123, /* Reserved function */ + RESV4 = 124, /* Reserved function */ + RESV5 = 125, /* Reserved function */ + I2C0_SCLK = 126, /* I2C0 Serial Clock */ + I2C0_SDA = 127, /* I2C0 Serial Data */ + I2C1_SCLK = 128, /* I2C1 Serial Clock */ + I2C1_SDA = 129, /* I2C1 Serial Data */ + I2C2_SCLK = 130, /* I2C2 Serial Clock */ + I2C2_SDA = 131, /* I2C2 Serial Data */ + CMOS_XCLK = 132, /* DVP System Clock */ + CMOS_RST = 133, /* DVP System Reset */ + CMOS_PWDN = 134, /* DVP Power Down Mode */ + CMOS_VSYNC = 135, /* DVP Vertical Sync */ + CMOS_HREF = 136, /* DVP Horizontal Reference output */ + CMOS_PCLK = 137, /* Pixel Clock */ + CMOS_D0 = 138, /* Data Bit 0 */ + CMOS_D1 = 139, /* Data Bit 1 */ + CMOS_D2 = 140, /* Data Bit 2 */ + CMOS_D3 = 141, /* Data Bit 3 */ + CMOS_D4 = 142, /* Data Bit 4 */ + CMOS_D5 = 143, /* Data Bit 5 */ + CMOS_D6 = 144, /* Data Bit 6 */ + CMOS_D7 = 145, /* Data Bit 7 */ + SCCB_SCLK = 146, /* SCCB Serial Clock */ + SCCB_SDA = 147, /* SCCB Serial Data */ + UART1_CTS = 148, /* UART1 Clear To Send */ + UART1_DSR = 149, /* UART1 Data Set Ready */ + UART1_DCD = 150, /* UART1 Data Carrier Detect */ + UART1_RI = 151, /* UART1 Ring Indicator */ + UART1_SIR_IN = 152, /* UART1 Serial Infrared Input */ + UART1_DTR = 153, /* UART1 Data Terminal Ready */ + UART1_RTS = 154, /* UART1 Request To Send */ + UART1_OUT2 = 155, /* UART1 User-designated Output 2 */ + UART1_OUT1 = 156, /* UART1 User-designated Output 1 */ + UART1_SIR_OUT = 157, /* UART1 Serial Infrared Output */ + UART1_BAUD = 158, /* UART1 Transmit Clock Output */ + UART1_RE = 159, /* UART1 Receiver Output Enable */ + UART1_DE = 160, /* UART1 Driver Output Enable */ + UART1_RS485_EN = 161, /* UART1 RS485 Enable */ + UART2_CTS = 162, /* UART2 Clear To Send */ + UART2_DSR = 163, /* UART2 Data Set Ready */ + UART2_DCD = 164, /* UART2 Data Carrier Detect */ + UART2_RI = 165, /* UART2 Ring Indicator */ + UART2_SIR_IN = 166, /* UART2 Serial Infrared Input */ + UART2_DTR = 167, /* UART2 Data Terminal Ready */ + UART2_RTS = 168, /* UART2 Request To Send */ + UART2_OUT2 = 169, /* UART2 User-designated Output 2 */ + UART2_OUT1 = 170, /* UART2 User-designated Output 1 */ + UART2_SIR_OUT = 171, /* UART2 Serial Infrared Output */ + UART2_BAUD = 172, /* UART2 Transmit Clock Output */ + UART2_RE = 173, /* UART2 Receiver Output Enable */ + UART2_DE = 174, /* UART2 Driver Output Enable */ + UART2_RS485_EN = 175, /* UART2 RS485 Enable */ + UART3_CTS = 176, /* UART3 Clear To Send */ + UART3_DSR = 177, /* UART3 Data Set Ready */ + UART3_DCD = 178, /* UART3 Data Carrier Detect */ + UART3_RI = 179, /* UART3 Ring Indicator */ + UART3_SIR_IN = 180, /* UART3 Serial Infrared Input */ + UART3_DTR = 181, /* UART3 Data Terminal Ready */ + UART3_RTS = 182, /* UART3 Request To Send */ + UART3_OUT2 = 183, /* UART3 User-designated Output 2 */ + UART3_OUT1 = 184, /* UART3 User-designated Output 1 */ + UART3_SIR_OUT = 185, /* UART3 Serial Infrared Output */ + UART3_BAUD = 186, /* UART3 Transmit Clock Output */ + UART3_RE = 187, /* UART3 Receiver Output Enable */ + UART3_DE = 188, /* UART3 Driver Output Enable */ + UART3_RS485_EN = 189, /* UART3 RS485 Enable */ + TIMER0_TOGGLE1 = 190, /* TIMER0 Toggle Output 1 */ + TIMER0_TOGGLE2 = 191, /* TIMER0 Toggle Output 2 */ + TIMER0_TOGGLE3 = 192, /* TIMER0 Toggle Output 3 */ + TIMER0_TOGGLE4 = 193, /* TIMER0 Toggle Output 4 */ + TIMER1_TOGGLE1 = 194, /* TIMER1 Toggle Output 1 */ + TIMER1_TOGGLE2 = 195, /* TIMER1 Toggle Output 2 */ + TIMER1_TOGGLE3 = 196, /* TIMER1 Toggle Output 3 */ + TIMER1_TOGGLE4 = 197, /* TIMER1 Toggle Output 4 */ + TIMER2_TOGGLE1 = 198, /* TIMER2 Toggle Output 1 */ + TIMER2_TOGGLE2 = 199, /* TIMER2 Toggle Output 2 */ + TIMER2_TOGGLE3 = 200, /* TIMER2 Toggle Output 3 */ + TIMER2_TOGGLE4 = 201, /* TIMER2 Toggle Output 4 */ + CLK_SPI2 = 202, /* Clock SPI2 */ + CLK_I2C2 = 203, /* Clock I2C2 */ + INTERNAL0 = 204, /* Internal function signal 0 */ + INTERNAL1 = 205, /* Internal function signal 1 */ + INTERNAL2 = 206, /* Internal function signal 2 */ + INTERNAL3 = 207, /* Internal function signal 3 */ + INTERNAL4 = 208, /* Internal function signal 4 */ + INTERNAL5 = 209, /* Internal function signal 5 */ + INTERNAL6 = 210, /* Internal function signal 6 */ + INTERNAL7 = 211, /* Internal function signal 7 */ + INTERNAL8 = 212, /* Internal function signal 8 */ + INTERNAL9 = 213, /* Internal function signal 9 */ + INTERNAL10 = 214, /* Internal function signal 10 */ + INTERNAL11 = 215, /* Internal function signal 11 */ + INTERNAL12 = 216, /* Internal function signal 12 */ + INTERNAL13 = 217, /* Internal function signal 13 */ + INTERNAL14 = 218, /* Internal function signal 14 */ + INTERNAL15 = 219, /* Internal function signal 15 */ + INTERNAL16 = 220, /* Internal function signal 16 */ + INTERNAL17 = 221, /* Internal function signal 17 */ + CONSTANT = 222, /* Constant function */ + INTERNAL18 = 223, /* Internal function signal 18 */ + DEBUG0 = 224, /* Debug function 0 */ + DEBUG1 = 225, /* Debug function 1 */ + DEBUG2 = 226, /* Debug function 2 */ + DEBUG3 = 227, /* Debug function 3 */ + DEBUG4 = 228, /* Debug function 4 */ + DEBUG5 = 229, /* Debug function 5 */ + DEBUG6 = 230, /* Debug function 6 */ + DEBUG7 = 231, /* Debug function 7 */ + DEBUG8 = 232, /* Debug function 8 */ + DEBUG9 = 233, /* Debug function 9 */ + DEBUG10 = 234, /* Debug function 10 */ + DEBUG11 = 235, /* Debug function 11 */ + DEBUG12 = 236, /* Debug function 12 */ + DEBUG13 = 237, /* Debug function 13 */ + DEBUG14 = 238, /* Debug function 14 */ + DEBUG15 = 239, /* Debug function 15 */ + DEBUG16 = 240, /* Debug function 16 */ + DEBUG17 = 241, /* Debug function 17 */ + DEBUG18 = 242, /* Debug function 18 */ + DEBUG19 = 243, /* Debug function 19 */ + DEBUG20 = 244, /* Debug function 20 */ + DEBUG21 = 245, /* Debug function 21 */ + DEBUG22 = 246, /* Debug function 22 */ + DEBUG23 = 247, /* Debug function 23 */ + DEBUG24 = 248, /* Debug function 24 */ + DEBUG25 = 249, /* Debug function 25 */ + DEBUG26 = 250, /* Debug function 26 */ + DEBUG27 = 251, /* Debug function 27 */ + DEBUG28 = 252, /* Debug function 28 */ + DEBUG29 = 253, /* Debug function 29 */ + DEBUG30 = 254, /* Debug function 30 */ + DEBUG31 = 255, /* Debug function 31 */ +} + +impl function { + /** GPIOHS pin to function */ + pub fn gpiohs(num: u8) -> function { + use function::*; + match num { + 0 => GPIOHS0, + 1 => GPIOHS1, + 2 => GPIOHS2, + 3 => GPIOHS3, + 4 => GPIOHS4, + 5 => GPIOHS5, + 6 => GPIOHS6, + 7 => GPIOHS7, + 8 => GPIOHS8, + 9 => GPIOHS9, + 10 => GPIOHS10, + 11 => GPIOHS11, + 12 => GPIOHS12, + 13 => GPIOHS13, + 14 => GPIOHS14, + 15 => GPIOHS15, + 16 => GPIOHS16, + 17 => GPIOHS17, + 18 => GPIOHS18, + 19 => GPIOHS19, + 20 => GPIOHS20, + 21 => GPIOHS21, + 22 => GPIOHS22, + 23 => GPIOHS23, + 24 => GPIOHS24, + 25 => GPIOHS25, + 26 => GPIOHS26, + 27 => GPIOHS27, + 28 => GPIOHS28, + 29 => GPIOHS29, + 30 => GPIOHS30, + 31 => GPIOHS31, + _ => panic!("no such GPIO pin"), + } + } +} + +#[derive(Copy, Clone)] +pub enum pull { + /** No Pull */ + NONE, + /** Pull Down */ + DOWN, + /** Pull Up */ + UP, +} + +/** Defaults per function (from Kendryte fpioa.c) */ +#[cfg_attr(rustfmt, rustfmt_skip)] +static FUNCTION_DEFAULTS: &[u32] = &[ + 0x00900000, 0x00900001, 0x00900002, 0x00001f03, 0x00b03f04, 0x00b03f05, 0x00b03f06, 0x00b03f07, + 0x00b03f08, 0x00b03f09, 0x00b03f0a, 0x00b03f0b, 0x00001f0c, 0x00001f0d, 0x00001f0e, 0x00001f0f, + 0x03900010, 0x00001f11, 0x00900012, 0x00001f13, 0x00900014, 0x00900015, 0x00001f16, 0x00001f17, + 0x00901f18, 0x00901f19, 0x00901f1a, 0x00901f1b, 0x00901f1c, 0x00901f1d, 0x00901f1e, 0x00901f1f, + 0x00901f20, 0x00901f21, 0x00901f22, 0x00901f23, 0x00901f24, 0x00901f25, 0x00901f26, 0x00901f27, + 0x00901f28, 0x00901f29, 0x00901f2a, 0x00901f2b, 0x00901f2c, 0x00901f2d, 0x00901f2e, 0x00901f2f, + 0x00901f30, 0x00901f31, 0x00901f32, 0x00901f33, 0x00901f34, 0x00901f35, 0x00901f36, 0x00901f37, + 0x00901f38, 0x00901f39, 0x00901f3a, 0x00901f3b, 0x00901f3c, 0x00901f3d, 0x00901f3e, 0x00901f3f, + 0x00900040, 0x00001f41, 0x00900042, 0x00001f43, 0x00900044, 0x00001f45, 0x00b03f46, 0x00b03f47, + 0x00b03f48, 0x00b03f49, 0x00b03f4a, 0x00b03f4b, 0x00b03f4c, 0x00b03f4d, 0x00001f4e, 0x00001f4f, + 0x00001f50, 0x00001f51, 0x03900052, 0x00001f53, 0x00b03f54, 0x00900055, 0x00900056, 0x00001f57, + 0x00001f58, 0x00001f59, 0x0090005a, 0x0090005b, 0x0090005c, 0x0090005d, 0x00001f5e, 0x00001f5f, + 0x00001f60, 0x00001f61, 0x00001f62, 0x00001f63, 0x00001f64, 0x00900065, 0x00900066, 0x00900067, + 0x00900068, 0x00001f69, 0x00001f6a, 0x00001f6b, 0x00001f6c, 0x00001f6d, 0x00001f6e, 0x00001f6f, + 0x00900070, 0x00900071, 0x00900072, 0x00900073, 0x00001f74, 0x00001f75, 0x00001f76, 0x00001f77, + 0x00000078, 0x00000079, 0x0000007a, 0x0000007b, 0x0000007c, 0x0000007d, 0x0099107e, 0x0099107f, + 0x00991080, 0x00991081, 0x00991082, 0x00991083, 0x00001f84, 0x00001f85, 0x00001f86, 0x00900087, + 0x00900088, 0x00900089, 0x0090008a, 0x0090008b, 0x0090008c, 0x0090008d, 0x0090008e, 0x0090008f, + 0x00900090, 0x00900091, 0x00993092, 0x00993093, 0x00900094, 0x00900095, 0x00900096, 0x00900097, + 0x00900098, 0x00001f99, 0x00001f9a, 0x00001f9b, 0x00001f9c, 0x00001f9d, 0x00001f9e, 0x00001f9f, + 0x00001fa0, 0x00001fa1, 0x009000a2, 0x009000a3, 0x009000a4, 0x009000a5, 0x009000a6, 0x00001fa7, + 0x00001fa8, 0x00001fa9, 0x00001faa, 0x00001fab, 0x00001fac, 0x00001fad, 0x00001fae, 0x00001faf, + 0x009000b0, 0x009000b1, 0x009000b2, 0x009000b3, 0x009000b4, 0x00001fb5, 0x00001fb6, 0x00001fb7, + 0x00001fb8, 0x00001fb9, 0x00001fba, 0x00001fbb, 0x00001fbc, 0x00001fbd, 0x00001fbe, 0x00001fbf, + 0x00001fc0, 0x00001fc1, 0x00001fc2, 0x00001fc3, 0x00001fc4, 0x00001fc5, 0x00001fc6, 0x00001fc7, + 0x00001fc8, 0x00001fc9, 0x00001fca, 0x00001fcb, 0x00001fcc, 0x00001fcd, 0x00001fce, 0x00001fcf, + 0x00001fd0, 0x00001fd1, 0x00001fd2, 0x00001fd3, 0x00001fd4, 0x009000d5, 0x009000d6, 0x009000d7, + 0x009000d8, 0x009100d9, 0x00991fda, 0x009000db, 0x009000dc, 0x009000dd, 0x000000de, 0x009000df, + 0x00001fe0, 0x00001fe1, 0x00001fe2, 0x00001fe3, 0x00001fe4, 0x00001fe5, 0x00001fe6, 0x00001fe7, + 0x00001fe8, 0x00001fe9, 0x00001fea, 0x00001feb, 0x00001fec, 0x00001fed, 0x00001fee, 0x00001fef, + 0x00001ff0, 0x00001ff1, 0x00001ff2, 0x00001ff3, 0x00001ff4, 0x00001ff5, 0x00001ff6, 0x00001ff7, + 0x00001ff8, 0x00001ff9, 0x00001ffa, 0x00001ffb, 0x00001ffc, 0x00001ffd, 0x00001ffe, 0x00001fff, +]; + +pub fn set_function>(number: N, function: function) { + // TODO: check for overlapping assignments and assign to RESV0 as the Kendryte SDK does? + unsafe { + let ptr = pac::FPIOA::ptr(); + (*ptr).io[number.into()].write(|w| w.bits(FUNCTION_DEFAULTS[function as usize])); + } +} + +pub fn set_io_pull>(number: N, pull: pull) { + unsafe { + (*pac::FPIOA::ptr()).io[number.into()].modify(|_, w| match pull { + pull::NONE => w.pu().bit(false).pd().bit(false), + pull::DOWN => w.pu().bit(false).pd().bit(true), + pull::UP => w.pu().bit(true).pd().bit(false), + }); + } +} + +/** I/O pins for FPIOA */ +#[derive(Copy, Clone)] +pub enum io { + /** JTAG TCK */ + JTAG_TCK = 0, + /** JTAG TDI */ + JTAG_TDI = 1, + /** JTAG TMS */ + JTAG_TMS = 2, + /** JTAG TDO */ + JTAG_TDO = 3, + /** Host RX (from STM32F103C8) */ + ISP_RX = 4, + /** Host TX (to STM32F103C8) */ + ISP_TX = 5, + /** WIFI serial TX (from perspective of ESP8285, so our RX) */ + WIFI_TX = 6, + /** WIFI serial RX (from perspective of ESP8285, so our TX) */ + WIFI_RX = 7, + /** WIFI enable (to ESP8285) */ + WIFI_EN = 8, + /** Unused */ + BPSK_P = 9, + /** Unused */ + BPSK_N = 10, + /** General purpose I/O pin */ + IO11 = 11, + /** Blue led (output) */ + LED_B = 12, + /** Green led (output) */ + LED_G = 13, + /** Red led (output) */ + LED_R = 14, + /** Key direction 1 press (input) */ + KEY1 = 15, + /** Key center press (input) */ + BOOT_KEY0 = 16, + /** Key direction 2 press (input) */ + KEY2 = 17, + /** Microphone I2S BCK */ + MIC_BCK = 18, + /** Microphone I2S WS */ + MIC_WS = 19, + /** Microphone I2S DAT3 */ + MIC_DAT3 = 20, + /** Microphone I2S DAT2 */ + MIC_DAT2 = 21, + /** Microphone I2S DAT1 */ + MIC_DAT1 = 22, + /** Microphone I2S DAT0 */ + MIC_DAT0 = 23, + /** Microphone LED DAT */ + MIC_LED_DAT = 24, + /** Microphone LED CLK */ + MIC_LED_CLK = 25, + /** SDCARD SPI MISO */ + SPI0_MISO = 26, + /** SDCARD SPI SCLK */ + SPI0_SCLK = 27, + /** SDCARD SPI MOSI */ + SPI0_MOSI = 28, + /** SDCARD SPI CS */ + SPI0_CS0 = 29, + /** I2C bus 1 SCLK (NS2009, MSA300) */ + I2C1_SCL = 30, + /** I2C bus 2 SDA (NS2009, MSA300) */ + I2C1_SDA = 31, + /** General purpose I/O pin */ + IO32 = 32, + /** DAC I2S WS */ + I2S_WS = 33, + /** DAC I2S DA */ + I2S_DA = 34, + /** DAC I2S BCK */ + I2S_BCK = 35, + /** LCD chip select (output) */ + LCD_CS = 36, + /** LCD reset (output) */ + LCD_RST = 37, + /** LCD Data/Command */ + LCD_DC = 38, + /** LCD SPI SCLK */ + LCD_WR = 39, + /** Camera DVP SDA */ + DVP_SDA = 40, + /** Camera DVP SCL */ + DVP_SCL = 41, + /** Camera DVP RST */ + DVP_RST = 42, + /** Camera DVP VSYNC */ + DVP_VSYNC = 43, + /** Camera DVP PWDN */ + DVP_PWDN = 44, + /** Camera DVP HSYNC */ + DVP_HSYNC = 45, + /** Camera DVP XCLK */ + DVP_XCLK = 46, + /** Camera DVP PCLK */ + DVP_PCLK = 47, +} + +impl From for usize { + fn from(io: io) -> Self { + io as usize + } +} \ No newline at end of file diff --git a/third-party/k210-soc/src/gpio.rs b/third-party/k210-soc/src/gpio.rs new file mode 100644 index 00000000..fc2a665e --- /dev/null +++ b/third-party/k210-soc/src/gpio.rs @@ -0,0 +1,11 @@ +//! GPIO peripheral + +#![allow(non_camel_case_types)] + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum direction { + INPUT, + OUTPUT, +} + +// TODO \ No newline at end of file diff --git a/third-party/k210-soc/src/gpiohs.rs b/third-party/k210-soc/src/gpiohs.rs new file mode 100644 index 00000000..f8e08153 --- /dev/null +++ b/third-party/k210-soc/src/gpiohs.rs @@ -0,0 +1,41 @@ +#![allow(unused)] + +//! GPIOHS peripheral +//use k210_hal::pac; +use k210_pac as pac; + +use super::gpio; +use super::utils::{set_bit,get_bit}; + +// TODO embedded-hal::digital::v2::{InputPin, OutputPin} + +/** Set input/output direction for a GPIOHS pin */ +pub fn set_direction(pin: u8, direction: gpio::direction) { + unsafe { + let ptr = pac::GPIOHS::ptr(); + (*ptr) + .output_en + .modify(|r, w| w.bits(set_bit(r.bits(), pin, direction == gpio::direction::OUTPUT))); + (*ptr) + .input_en + .modify(|r, w| w.bits(set_bit(r.bits(), pin, direction == gpio::direction::INPUT))); + } +} + +/** Set output value for a GPIOHS pin */ +pub fn set_pin(pin: u8, value: bool) { + unsafe { + let ptr = pac::GPIOHS::ptr(); + (*ptr) + .output_val + .modify(|r, w| w.bits(set_bit(r.bits(), pin, value))); + } +} + +/** Get input value for a GPIOHS pin */ +pub fn get_pin(pin: u8) -> bool { + unsafe { + let ptr = pac::GPIOHS::ptr(); + get_bit((*ptr).input_val.read().bits(), pin) + } +} \ No newline at end of file diff --git a/third-party/k210-soc/src/lib.rs b/third-party/k210-soc/src/lib.rs new file mode 100644 index 00000000..352e95ac --- /dev/null +++ b/third-party/k210-soc/src/lib.rs @@ -0,0 +1,10 @@ +#![no_std] + +pub mod dmac; +pub mod fpioa; +pub mod gpio; +pub mod gpiohs; +pub mod sleep; +pub mod spi; +pub mod sysctl; +pub mod utils; diff --git a/third-party/k210-soc/src/sleep.rs b/third-party/k210-soc/src/sleep.rs new file mode 100644 index 00000000..cdd4c484 --- /dev/null +++ b/third-party/k210-soc/src/sleep.rs @@ -0,0 +1,12 @@ +use super::sysctl; +use riscv::register::time; + +pub fn time_sleep(n: usize) { + let start = time::read(); + while time::read() < start + n {} +} + +pub fn usleep(n: usize) { + let freq = sysctl::clock_get_freq(sysctl::clock::CPU) as usize / 62; + time_sleep(freq * n / 1000000); +} diff --git a/third-party/k210-soc/src/spi.rs b/third-party/k210-soc/src/spi.rs new file mode 100644 index 00000000..e3aeb36d --- /dev/null +++ b/third-party/k210-soc/src/spi.rs @@ -0,0 +1,316 @@ +//! SPI peripherals handling +use core::cmp; +use core::convert::TryInto; +use core::ops::Deref; +//use k210_hal::pac; +use k210_pac as pac; +use pac::{SPI0,SPI1,spi0}; +use pac::spi0::ctrlr0; +use pac::spi0::spi_ctrlr0; + +//use super::sysctl; +use super::sysctl::{dma_channel, self}; +use super::dmac::{DMAC, address_increment, burst_length, transfer_width}; + +/// Extension trait that constrains SPI peripherals +pub trait SPIExt: Sized { + /// Constrains SPI peripheral so it plays nicely with the other abstractions + fn constrain(self) -> SPIImpl; +} + +/// Trait for generalizing over SPI0 and SPI1 (SPI2 is slave-only and SPI3 is !!!special!!!) +pub trait SPI01: Deref { + #[doc(hidden)] + const CLK: sysctl::clock; + #[doc(hidden)] + const DIV: sysctl::threshold; + #[doc(hidden)] + const DMA_RX: sysctl::dma_select; + #[doc(hidden)] + const DMA_TX: sysctl::dma_select; +} + +impl SPI01 for SPI0 { + const CLK: sysctl::clock = sysctl::clock::SPI0; + const DIV: sysctl::threshold = sysctl::threshold::SPI0; + const DMA_RX: sysctl::dma_select = sysctl::dma_select::SSI0_RX_REQ; + const DMA_TX: sysctl::dma_select = sysctl::dma_select::SSI0_TX_REQ; +} +impl SPI01 for SPI1 { + const CLK: sysctl::clock = sysctl::clock::SPI1; + const DIV: sysctl::threshold = sysctl::threshold::SPI1; + const DMA_RX: sysctl::dma_select = sysctl::dma_select::SSI1_RX_REQ; + const DMA_TX: sysctl::dma_select = sysctl::dma_select::SSI1_TX_REQ; +} + +impl SPIExt for SPI { + fn constrain(self) -> SPIImpl { + SPIImpl::::new(self) + } +} + +pub struct SPIImpl { + spi: IF, +} + +/** Borrow work mode from pac */ +pub use ctrlr0::WORK_MODE_A as work_mode; +/** Borrow frame format from pac */ +pub use ctrlr0::FRAME_FORMAT_A as frame_format; +/** Borrow aitm from pac */ +pub use spi_ctrlr0::AITM_A as aitm; +/** Borrow tmod from pac */ +pub use ctrlr0::TMOD_A as tmod; + +pub trait SPI { + fn configure( + &self, + work_mode: work_mode, + frame_format: frame_format, + data_bit_length: u8, + endian: u32, + instruction_length: u8, + address_length: u8, + wait_cycles: u8, + instruction_address_trans_mode: aitm, + tmod: tmod, + ); + fn set_clk_rate(&self, spi_clk: u32) -> u32; + fn recv_data(&self, chip_select: u32, rx: &mut [X]); + fn recv_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, rx: &mut [u32]); + fn send_data + Copy>(&self, chip_select: u32, tx: &[X]); + fn send_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, tx: &[u32]); + fn fill_data(&self, chip_select: u32, value: u32, tx_len: usize); + fn fill_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, value: u32, tx_len: usize); +} + +impl SPIImpl { + pub fn new(spi: IF) -> Self { + Self { spi } + } +} + +/** Trait for trunction of a SPI frame from u32 register to other unsigned integer types. */ +pub trait TruncU32 { + fn trunc(val: u32)-> Self; +} +impl TruncU32 for u32 { fn trunc(val: u32) -> u32 { return val; } } +impl TruncU32 for u16 { fn trunc(val: u32) -> u16 { return (val & 0xffff) as u16; } } +impl TruncU32 for u8 { fn trunc(val: u32) -> u8 { return (val & 0xff) as u8; } } + +impl SPI for SPIImpl { + /// Configure SPI transaction + fn configure( + &self, + work_mode: work_mode, + frame_format: frame_format, + data_bit_length: u8, + endian: u32, + instruction_length: u8, + address_length: u8, + wait_cycles: u8, + instruction_address_trans_mode: aitm, + tmod: tmod, + ) { + assert!(data_bit_length >= 4 && data_bit_length <= 32); + assert!(wait_cycles < (1 << 5)); + let inst_l: u8 = match instruction_length { + 0 => 0, + 4 => 1, + 8 => 2, + 16 => 3, + _ => panic!("unhandled intruction length"), + }; + + assert!(address_length % 4 == 0 && address_length <= 60); + let addr_l: u8 = address_length / 4; + + unsafe { + self.spi.imr.write(|w| w.bits(0x00)); + self.spi.dmacr.write(|w| w.bits(0x00)); + self.spi.dmatdlr.write(|w| w.bits(0x10)); + self.spi.dmardlr.write(|w| w.bits(0x00)); + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + self.spi.ctrlr0.write(|w| { + w.work_mode() + .variant(work_mode) + .tmod() + .variant(tmod) + .frame_format() + .variant(frame_format) + .data_length() + .bits(data_bit_length - 1) + }); + self.spi.spi_ctrlr0.write(|w| { + w.aitm() + .variant(instruction_address_trans_mode) + .addr_length() + .bits(addr_l) + .inst_length() + .bits(inst_l) + .wait_cycles() + .bits(wait_cycles) + }); + self.spi.endian.write(|w| w.bits(endian)); + } + } + + /// Set SPI clock rate + fn set_clk_rate(&self, spi_clk: u32) -> u32 { + sysctl::clock_enable(IF::CLK); + sysctl::clock_set_threshold(IF::DIV, 0); + let clock_freq: u32 = sysctl::clock_get_freq(sysctl::clock::SPI0); + let spi_baudr = clock_freq / spi_clk; + // Clamp baudrate divider to valid range + let spi_baudr = cmp::min(cmp::max(spi_baudr, 2), 65534); + unsafe { + self.spi.baudr.write(|w| w.bits(spi_baudr)); + } + clock_freq / spi_baudr + } + + /// Receive arbitrary data + // make sure to set tmod to tmod::RECV + fn recv_data(&self, chip_select: u32, rx: &mut [X]) { + if rx.len() == 0 { + return; + } + unsafe { + self.spi.ctrlr1.write(|w| w.bits((rx.len() - 1).try_into().unwrap())); + self.spi.ssienr.write(|w| w.bits(0x01)); + self.spi.dr[0].write(|w| w.bits(0xffffffff)); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + + let mut fifo_len = 0; + for val in rx.iter_mut() { + while fifo_len == 0 { + fifo_len = self.spi.rxflr.read().bits(); + } + *val = X::trunc(self.spi.dr[0].read().bits()); + fifo_len -= 1; + } + + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Receive 32-bit data using DMA. + // make sure to set tmod to tmod::RECV + fn recv_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, rx: &mut [u32]) { + if rx.len() == 0 { + return; + } + unsafe { + self.spi.ctrlr1.write(|w| w.bits((rx.len() - 1).try_into().unwrap())); + self.spi.ssienr.write(|w| w.bits(0x01)); + self.spi.dmacr.write(|w| w.bits(0x3)); /*enable dma receive */ + + sysctl::dma_select(channel_num, IF::DMA_RX); + dmac.set_single_mode(channel_num, self.spi.dr.as_ptr() as u64, rx.as_ptr() as u64, + address_increment::NOCHANGE, address_increment::INCREMENT, + burst_length::LENGTH_1, transfer_width::WIDTH_32, rx.len() as u32); + self.spi.dr[0].write(|w| w.bits(0xffffffff)); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + dmac.wait_done(channel_num); + + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send arbitrary data + fn send_data + Copy>(&self, chip_select: u32, tx: &[X]) { + unsafe { + self.spi.ser.write(|w| w.bits(1 << chip_select)); + self.spi.ssienr.write(|w| w.bits(0x01)); + + let mut fifo_len = 0; + for &val in tx { + while fifo_len == 0 { + fifo_len = 32 - self.spi.txflr.read().bits(); + } + self.spi.dr[0].write(|f| f.bits(val.into())); + fifo_len -= 1; + } + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send 32-bit data using DMA. + /// If you want to use this function to send 8-bit or 16-bit data, you need to wrap each + /// data unit in a 32-bit word. + /// This is intentionally left to the caller: the difficulty here is to avoid the need for alloc/freeing() + /// buffers every time as the SDK does because this is highly undesirable! + fn send_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, tx: &[u32]) { + unsafe { + self.spi.dmacr.write(|w| w.bits(0x2)); /*enable dma transmit*/ + self.spi.ssienr.write(|w| w.bits(0x01)); + + sysctl::dma_select(channel_num, IF::DMA_TX); + dmac.set_single_mode(channel_num, tx.as_ptr() as u64, self.spi.dr.as_ptr() as u64, + address_increment::INCREMENT, address_increment::NOCHANGE, + burst_length::LENGTH_4, transfer_width::WIDTH_32, tx.len() as u32); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + dmac.wait_done(channel_num); + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send repeated data + fn fill_data(&self, chip_select: u32, value: u32, mut tx_len: usize) { + unsafe { + self.spi.ser.write(|w| w.bits(1 << chip_select)); + self.spi.ssienr.write(|w| w.bits(0x01)); + + while tx_len != 0 { + let fifo_len = (32 - self.spi.txflr.read().bits()) as usize; + let fifo_len = cmp::min(fifo_len, tx_len); + for _ in 0..fifo_len { + self.spi.dr[0].write(|f| f.bits(value)); + } + tx_len -= fifo_len; + } + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } + + /// Send repeated data (using DMA) + fn fill_data_dma(&self, dmac: &DMAC, channel_num: dma_channel, chip_select: u32, value: u32, tx_len: usize) { + unsafe { + self.spi.dmacr.write(|w| w.bits(0x2)); /*enable dma transmit*/ + self.spi.ssienr.write(|w| w.bits(0x01)); + + sysctl::dma_select(channel_num, IF::DMA_TX); + let val = [value]; + // simple trick to repeating a value: don't increment the source address + dmac.set_single_mode(channel_num, val.as_ptr() as u64, self.spi.dr.as_ptr() as u64, + address_increment::NOCHANGE, address_increment::NOCHANGE, + burst_length::LENGTH_4, transfer_width::WIDTH_32, tx_len.try_into().unwrap()); + self.spi.ser.write(|w| w.bits(1 << chip_select)); + dmac.wait_done(channel_num); + + while (self.spi.sr.read().bits() & 0x05) != 0x04 { + // IDLE + } + self.spi.ser.write(|w| w.bits(0x00)); + self.spi.ssienr.write(|w| w.bits(0x00)); + } + } +} \ No newline at end of file diff --git a/third-party/k210-soc/src/sysctl.rs b/third-party/k210-soc/src/sysctl.rs new file mode 100644 index 00000000..6ee2b9d7 --- /dev/null +++ b/third-party/k210-soc/src/sysctl.rs @@ -0,0 +1,854 @@ +#![allow(unused)] +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] + +//! SYSCTL peripheral +//use k210_hal::pac; +use k210_pac as pac; + +use core::convert::TryInto; + +use super::utils::set_bit; +use super::sleep::usleep; + +mod pll_compute; + +const SYSCTRL_CLOCK_FREQ_IN0: u32 = 26000000; + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum pll { + /** PLL0 can usually be selected as alternative to IN0, for example the CPU + * clock speed. It can be used as source for PLL2. */ + PLL0, + /** PLL1 is used for the KPU clock, and can be used as source for PLL2. */ + PLL1, + /** PLL2 is used for I2S clocks. */ + PLL2, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum clock_source { + IN0, + PLL0, + PLL1, + PLL2, + ACLK, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum clock { + PLL0, + PLL1, + PLL2, + CPU, + SRAM0, + SRAM1, + APB0, + APB1, + APB2, + ROM, + DMA, + AI, + DVP, + FFT, + GPIO, + SPI0, + SPI1, + SPI2, + SPI3, + I2S0, + I2S1, + I2S2, + I2C0, + I2C1, + I2C2, + UART1, + UART2, + UART3, + AES, + FPIOA, + TIMER0, + TIMER1, + TIMER2, + WDT0, + WDT1, + SHA, + OTP, + RTC, + ACLK, + HCLK, + IN0, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum threshold { + ACLK, + APB0, + APB1, + APB2, + SRAM0, + SRAM1, + AI, + DVP, + ROM, + SPI0, + SPI1, + SPI2, + SPI3, + TIMER0, + TIMER1, + TIMER2, + I2S0, + I2S1, + I2S2, + I2S0_M, + I2S1_M, + I2S2_M, + I2C0, + I2C1, + I2C2, + WDT0, + WDT1, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum clock_select { + PLL0_BYPASS, + PLL1_BYPASS, + PLL2_BYPASS, + PLL2, + ACLK, + SPI3, + TIMER0, + TIMER1, + TIMER2, + SPI3_SAMPLE, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum io_power_mode { + V33, + V18, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum power_bank { + BANK0 = 0, + BANK1, + BANK2, + BANK3, + BANK4, + BANK5, + BANK6, + BANK7, +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub enum reset { + SOC, + ROM, + DMA, + AI, + DVP, + FFT, + GPIO, + SPI0, + SPI1, + SPI2, + SPI3, + I2S0, + I2S1, + I2S2, + I2C0, + I2C1, + I2C2, + UART1, + UART2, + UART3, + AES, + FPIOA, + TIMER0, + TIMER1, + TIMER2, + WDT0, + WDT1, + SHA, + RTC, +} + +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum dma_channel { + CHANNEL0 = 0, + CHANNEL1 = 1, + CHANNEL2 = 2, + CHANNEL3 = 3, + CHANNEL4 = 4, + CHANNEL5 = 5, +} + +impl dma_channel { + pub fn idx(self) -> usize { self as usize } +} + +pub type dma_select = pac::sysctl::dma_sel0::DMA_SEL0_A; + +fn clock_bus_en(clock: clock, en: bool) { + /* + * The timer is under APB0, to prevent apb0_clk_en1 and apb0_clk_en0 + * on same register, we split it to peripheral and central two + * registers, to protect CPU close apb0 clock accidentally. + * + * The apb0_clk_en0 and apb0_clk_en1 have same function, + * one of them set, the APB0 clock enable. + */ + + /* The APB clock should carefully disable */ + if en { + match clock { + /* + * These peripheral devices are under APB0 + * GPIO, UART1, UART2, UART3, SPI_SLAVE, I2S0, I2S1, + * I2S2, I2C0, I2C1, I2C2, FPIOA, SHA256, TIMER0, + * TIMER1, TIMER2 + */ + clock::GPIO + | clock::SPI2 + | clock::I2S0 + | clock::I2S1 + | clock::I2S2 + | clock::I2C0 + | clock::I2C1 + | clock::I2C2 + | clock::UART1 + | clock::UART2 + | clock::UART3 + | clock::FPIOA + | clock::TIMER0 + | clock::TIMER1 + | clock::TIMER2 + | clock::SHA => unsafe { + (*pac::SYSCTL::ptr()) + .clk_en_cent + .modify(|_, w| w.apb0_clk_en().bit(en)); + }, + + /* + * These peripheral devices are under APB1 + * WDT, AES, OTP, DVP, SYSCTL + */ + clock::AES | clock::WDT0 | clock::WDT1 | clock::OTP | clock::RTC => unsafe { + (*pac::SYSCTL::ptr()) + .clk_en_cent + .modify(|_, w| w.apb1_clk_en().bit(en)); + }, + + /* + * These peripheral devices are under APB2 + * SPI0, SPI1 + */ + clock::SPI0 | clock::SPI1 => unsafe { + (*pac::SYSCTL::ptr()) + .clk_en_cent + .modify(|_, w| w.apb2_clk_en().bit(en)); + }, + + _ => {} + } + } +} + +fn clock_device_en(clock: clock, en: bool) { + unsafe { + let ptr = pac::SYSCTL::ptr(); + match clock { + clock::PLL0 => (*ptr).pll0.modify(|_, w| w.out_en().bit(en)), + clock::PLL1 => (*ptr).pll1.modify(|_, w| w.out_en().bit(en)), + clock::PLL2 => (*ptr).pll2.modify(|_, w| w.out_en().bit(en)), + clock::CPU => (*ptr).clk_en_cent.modify(|_, w| w.cpu_clk_en().bit(en)), + clock::SRAM0 => (*ptr).clk_en_cent.modify(|_, w| w.sram0_clk_en().bit(en)), + clock::SRAM1 => (*ptr).clk_en_cent.modify(|_, w| w.sram1_clk_en().bit(en)), + clock::APB0 => (*ptr).clk_en_cent.modify(|_, w| w.apb0_clk_en().bit(en)), + clock::APB1 => (*ptr).clk_en_cent.modify(|_, w| w.apb1_clk_en().bit(en)), + clock::APB2 => (*ptr).clk_en_cent.modify(|_, w| w.apb2_clk_en().bit(en)), + clock::ROM => (*ptr).clk_en_peri.modify(|_, w| w.rom_clk_en().bit(en)), + clock::DMA => (*ptr).clk_en_peri.modify(|_, w| w.dma_clk_en().bit(en)), + clock::AI => (*ptr).clk_en_peri.modify(|_, w| w.ai_clk_en().bit(en)), + clock::DVP => (*ptr).clk_en_peri.modify(|_, w| w.dvp_clk_en().bit(en)), + clock::FFT => (*ptr).clk_en_peri.modify(|_, w| w.fft_clk_en().bit(en)), + clock::SPI3 => (*ptr).clk_en_peri.modify(|_, w| w.spi3_clk_en().bit(en)), + clock::GPIO => (*ptr).clk_en_peri.modify(|_, w| w.gpio_clk_en().bit(en)), + clock::SPI2 => (*ptr).clk_en_peri.modify(|_, w| w.spi2_clk_en().bit(en)), + clock::I2S0 => (*ptr).clk_en_peri.modify(|_, w| w.i2s0_clk_en().bit(en)), + clock::I2S1 => (*ptr).clk_en_peri.modify(|_, w| w.i2s1_clk_en().bit(en)), + clock::I2S2 => (*ptr).clk_en_peri.modify(|_, w| w.i2s2_clk_en().bit(en)), + clock::I2C0 => (*ptr).clk_en_peri.modify(|_, w| w.i2c0_clk_en().bit(en)), + clock::I2C1 => (*ptr).clk_en_peri.modify(|_, w| w.i2c1_clk_en().bit(en)), + clock::I2C2 => (*ptr).clk_en_peri.modify(|_, w| w.i2c2_clk_en().bit(en)), + clock::UART1 => (*ptr).clk_en_peri.modify(|_, w| w.uart1_clk_en().bit(en)), + clock::UART2 => (*ptr).clk_en_peri.modify(|_, w| w.uart2_clk_en().bit(en)), + clock::UART3 => (*ptr).clk_en_peri.modify(|_, w| w.uart3_clk_en().bit(en)), + clock::FPIOA => (*ptr).clk_en_peri.modify(|_, w| w.fpioa_clk_en().bit(en)), + clock::TIMER0 => (*ptr).clk_en_peri.modify(|_, w| w.timer0_clk_en().bit(en)), + clock::TIMER1 => (*ptr).clk_en_peri.modify(|_, w| w.timer1_clk_en().bit(en)), + clock::TIMER2 => (*ptr).clk_en_peri.modify(|_, w| w.timer2_clk_en().bit(en)), + clock::SHA => (*ptr).clk_en_peri.modify(|_, w| w.sha_clk_en().bit(en)), + clock::AES => (*ptr).clk_en_peri.modify(|_, w| w.aes_clk_en().bit(en)), + clock::WDT0 => (*ptr).clk_en_peri.modify(|_, w| w.wdt0_clk_en().bit(en)), + clock::WDT1 => (*ptr).clk_en_peri.modify(|_, w| w.wdt1_clk_en().bit(en)), + clock::OTP => (*ptr).clk_en_peri.modify(|_, w| w.otp_clk_en().bit(en)), + clock::RTC => (*ptr).clk_en_peri.modify(|_, w| w.rtc_clk_en().bit(en)), + clock::SPI0 => (*ptr).clk_en_peri.modify(|_, w| w.spi0_clk_en().bit(en)), + clock::SPI1 => (*ptr).clk_en_peri.modify(|_, w| w.spi1_clk_en().bit(en)), + clock::ACLK | clock::HCLK | clock::IN0 => { /* no separate enables */ } + } + } +} + +pub fn clock_enable(clock: clock) { + clock_bus_en(clock, true); + clock_device_en(clock, true); +} + +pub fn sysctl_clock_disable(clock: clock) { + clock_bus_en(clock, false); + clock_device_en(clock, false); +} + +/// Set clock divider +pub fn clock_set_threshold(which: threshold, threshold: u32) { + // TODO: this should take a multiplier directly, not a peripheral specific value + unsafe { + let ptr = pac::SYSCTL::ptr(); + match which { + /* 2 bit wide */ + threshold::ACLK => (*ptr).clk_sel0.modify(|_, w| w.aclk_divider_sel().bits(threshold as u8)), + + /* 3 bit wide */ + threshold::APB0 => (*ptr).clk_sel0.modify(|_, w| w.apb0_clk_sel().bits(threshold as u8)), + threshold::APB1 => (*ptr).clk_sel0.modify(|_, w| w.apb1_clk_sel().bits(threshold as u8)), + threshold::APB2 => (*ptr).clk_sel0.modify(|_, w| w.apb2_clk_sel().bits(threshold as u8)), + + /* 4 bit wide */ + threshold::SRAM0 => (*ptr).clk_th0.modify(|_, w| w.sram0_gclk().bits(threshold as u8)), + threshold::SRAM1 => (*ptr).clk_th0.modify(|_, w| w.sram1_gclk().bits(threshold as u8)), + threshold::AI => (*ptr).clk_th0.modify(|_, w| w.ai_gclk().bits(threshold as u8)), + threshold::DVP => (*ptr).clk_th0.modify(|_, w| w.dvp_gclk().bits(threshold as u8)), + threshold::ROM => (*ptr).clk_th0.modify(|_, w| w.rom_gclk().bits(threshold as u8)), + + /* 8 bit wide */ + threshold::SPI0 => (*ptr).clk_th1.modify(|_, w| w.spi0_clk().bits(threshold as u8)), + threshold::SPI1 => (*ptr).clk_th1.modify(|_, w| w.spi1_clk().bits(threshold as u8)), + threshold::SPI2 => (*ptr).clk_th1.modify(|_, w| w.spi2_clk().bits(threshold as u8)), + threshold::SPI3 => (*ptr).clk_th1.modify(|_, w| w.spi3_clk().bits(threshold as u8)), + threshold::TIMER0 => (*ptr).clk_th2.modify(|_, w| w.timer0_clk().bits(threshold as u8)), + threshold::TIMER1 => (*ptr).clk_th2.modify(|_, w| w.timer1_clk().bits(threshold as u8)), + threshold::TIMER2 => (*ptr).clk_th2.modify(|_, w| w.timer2_clk().bits(threshold as u8)), + threshold::I2S0_M => (*ptr).clk_th4.modify(|_, w| w.i2s0_mclk().bits(threshold as u8)), + threshold::I2S1_M => (*ptr).clk_th4.modify(|_, w| w.i2s1_mclk().bits(threshold as u8)), + threshold::I2S2_M => (*ptr).clk_th5.modify(|_, w| w.i2s2_mclk().bits(threshold as u8)), + threshold::I2C0 => (*ptr).clk_th5.modify(|_, w| w.i2c0_clk().bits(threshold as u8)), + threshold::I2C1 => (*ptr).clk_th5.modify(|_, w| w.i2c1_clk().bits(threshold as u8)), + threshold::I2C2 => (*ptr).clk_th5.modify(|_, w| w.i2c2_clk().bits(threshold as u8)), + threshold::WDT0 => (*ptr).clk_th6.modify(|_, w| w.wdt0_clk().bits(threshold as u8)), + threshold::WDT1 => (*ptr).clk_th6.modify(|_, w| w.wdt1_clk().bits(threshold as u8)), + + /* 16 bit wide */ + threshold::I2S0 => (*ptr).clk_th3.modify(|_, w| w.i2s0_clk().bits(threshold as u16)), + threshold::I2S1 => (*ptr).clk_th3.modify(|_, w| w.i2s1_clk().bits(threshold as u16)), + threshold::I2S2 => (*ptr).clk_th4.modify(|_, w| w.i2s2_clk().bits(threshold as u16)), + } + } +} + +/// Get clock divider +pub fn clock_get_threshold(which: threshold) -> u32 { + unsafe { + // TODO: this should return a multiplier directly, not a peripheral specific value + let ptr = pac::SYSCTL::ptr(); + match which { + /* 2 bit wide */ + threshold::ACLK => (*ptr).clk_sel0.read().aclk_divider_sel().bits().into(), + + /* 3 bit wide */ + threshold::APB0 => (*ptr).clk_sel0.read().apb0_clk_sel().bits().into(), + threshold::APB1 => (*ptr).clk_sel0.read().apb1_clk_sel().bits().into(), + threshold::APB2 => (*ptr).clk_sel0.read().apb2_clk_sel().bits().into(), + + /* 4 bit wide */ + threshold::SRAM0 => (*ptr).clk_th0.read().sram0_gclk().bits().into(), + threshold::SRAM1 => (*ptr).clk_th0.read().sram1_gclk().bits().into(), + threshold::AI => (*ptr).clk_th0.read().ai_gclk().bits().into(), + threshold::DVP => (*ptr).clk_th0.read().dvp_gclk().bits().into(), + threshold::ROM => (*ptr).clk_th0.read().rom_gclk().bits().into(), + + /* 8 bit wide */ + threshold::SPI0 => (*ptr).clk_th1.read().spi0_clk().bits().into(), + threshold::SPI1 => (*ptr).clk_th1.read().spi1_clk().bits().into(), + threshold::SPI2 => (*ptr).clk_th1.read().spi2_clk().bits().into(), + threshold::SPI3 => (*ptr).clk_th1.read().spi3_clk().bits().into(), + threshold::TIMER0 => (*ptr).clk_th2.read().timer0_clk().bits().into(), + threshold::TIMER1 => (*ptr).clk_th2.read().timer1_clk().bits().into(), + threshold::TIMER2 => (*ptr).clk_th2.read().timer2_clk().bits().into(), + threshold::I2S0_M => (*ptr).clk_th4.read().i2s0_mclk().bits().into(), + threshold::I2S1_M => (*ptr).clk_th4.read().i2s1_mclk().bits().into(), + threshold::I2S2_M => (*ptr).clk_th5.read().i2s2_mclk().bits().into(), + threshold::I2C0 => (*ptr).clk_th5.read().i2c0_clk().bits().into(), + threshold::I2C1 => (*ptr).clk_th5.read().i2c1_clk().bits().into(), + threshold::I2C2 => (*ptr).clk_th5.read().i2c2_clk().bits().into(), + threshold::WDT0 => (*ptr).clk_th6.read().wdt0_clk().bits().into(), + threshold::WDT1 => (*ptr).clk_th6.read().wdt1_clk().bits().into(), + + /* 16 bit wide */ + threshold::I2S0 => (*ptr).clk_th3.read().i2s0_clk().bits().into(), + threshold::I2S1 => (*ptr).clk_th3.read().i2s1_clk().bits().into(), + threshold::I2S2 => (*ptr).clk_th4.read().i2s2_clk().bits().into(), + } + } +} + +pub fn set_power_mode(power_bank: power_bank, mode: io_power_mode) { + unsafe { + (*pac::SYSCTL::ptr()).power_sel.modify(|r, w| { + w.bits(set_bit( + r.bits(), + power_bank as u8, + match mode { + io_power_mode::V33 => false, + io_power_mode::V18 => true, + }, + )) + }); + } +} + +/** Route SPI0_D0-D7 DVP_D0-D7 functions to SPI and DVP data pins (bypassing FPIOA). */ +pub fn set_spi0_dvp_data(status: bool) { + unsafe { + (*pac::SYSCTL::ptr()) + .misc + .modify(|_, w| w.spi_dvp_data_enable().bit(status)); + } +} + +/** Map PLL2 cksel value to clock source */ +fn pll2_cksel_to_source(bits: u8) -> clock_source { + match bits { + 0 => clock_source::IN0, + 1 => clock_source::PLL0, + 2 => clock_source::PLL1, + _ => panic!("invalid value for PLL2 ckin_sel"), + } +} + +/** Map clock source to PLL2 cksel value */ +fn pll2_source_to_cksel(source: clock_source) -> u8 { + match source { + clock_source::IN0 => 0, + clock_source::PLL0 => 1, + clock_source::PLL1 => 2, + _ => panic!("unsupported clock source for PLL2"), + } +} + +pub fn pll_get_freq(pll: pll) -> u32 { + let freq_in; + let nr; + let nf; + let od; + + match pll { + pll::PLL0 => { + freq_in = clock_source_get_freq(clock_source::IN0); + unsafe { + let val = (*pac::SYSCTL::ptr()).pll0.read(); + nr = val.clkr().bits() + 1; + nf = val.clkf().bits() + 1; + od = val.clkod().bits() + 1; + } + } + pll::PLL1 => { + freq_in = clock_source_get_freq(clock_source::IN0); + unsafe { + let val = (*pac::SYSCTL::ptr()).pll1.read(); + nr = val.clkr().bits() + 1; + nf = val.clkf().bits() + 1; + od = val.clkod().bits() + 1; + } + } + pll::PLL2 => { + /* Get input freq accrording to select register. */ + freq_in = clock_source_get_freq(pll2_cksel_to_source(clock_get_clock_select(clock_select::PLL2))); + unsafe { + let val = (*pac::SYSCTL::ptr()).pll2.read(); + nr = val.clkr().bits() + 1; + nf = val.clkf().bits() + 1; + od = val.clkod().bits() + 1; + } + } + } + + /* + * Get final PLL output freq + * FOUT = FIN / NR * NF / OD + * (rewritten as integer expression) + */ + ((u64::from(freq_in) * u64::from(nf)) / (u64::from(nr) * u64::from(od))).try_into().unwrap() +} + +pub fn clock_source_get_freq(source: clock_source) -> u32 { + match source { + clock_source::IN0 => SYSCTRL_CLOCK_FREQ_IN0, + clock_source::PLL0 => pll_get_freq(pll::PLL0), + clock_source::PLL1 => pll_get_freq(pll::PLL1), + clock_source::PLL2 => pll_get_freq(pll::PLL2), + clock_source::ACLK => clock_get_freq(clock::ACLK), + } +} + +pub fn clock_set_clock_select(which: clock_select, select: u8) { + unsafe { + let ptr = pac::SYSCTL::ptr(); + // Seems that PLL2 is the only one that takes a non-boolean clock select + // TODO: take a clock_source directly when we know the meanings of these bits + match which { + clock_select::PLL0_BYPASS => (*ptr).pll0.modify(|_, w| w.bypass().bit(select != 0)), + clock_select::PLL1_BYPASS => (*ptr).pll1.modify(|_, w| w.bypass().bit(select != 0)), + clock_select::PLL2_BYPASS => (*ptr).pll2.modify(|_, w| w.bypass().bit(select != 0)), + clock_select::PLL2 => (*ptr).pll2.modify(|_, w| w.ckin_sel().bits(select)), + clock_select::ACLK => (*ptr).clk_sel0.modify(|_, w| w.aclk_sel().bit(select != 0)), + clock_select::SPI3 => (*ptr).clk_sel0.modify(|_, w| w.spi3_clk_sel().bit(select != 0)), + clock_select::TIMER0 => (*ptr).clk_sel0.modify(|_, w| w.timer0_clk_sel().bit(select != 0)), + clock_select::TIMER1 => (*ptr).clk_sel0.modify(|_, w| w.timer1_clk_sel().bit(select != 0)), + clock_select::TIMER2 => (*ptr).clk_sel0.modify(|_, w| w.timer2_clk_sel().bit(select != 0)), + clock_select::SPI3_SAMPLE => (*ptr).clk_sel1.modify(|_, w| w.spi3_sample_clk_sel().bit(select != 0)), + } + } +} + +pub fn clock_get_clock_select(which: clock_select) -> u8 { + unsafe { + let ptr = pac::SYSCTL::ptr(); + // Seems that PLL2 is the only one that has a non-boolean clock select + // TODO: return a clock_source directly when we know the meanings of these bits + // meaning seems to be usually: + // 0 IN0 + // 1 PLL0 + // (2 PLL1) + // it's likely different for _BYPASS, which, I suspect, wires the PLL output to the + // input (IN0 for PLL0 and PLL1, selectable for PLL2) + match which { + clock_select::PLL0_BYPASS => (*ptr).pll0.read().bypass().bit().into(), + clock_select::PLL1_BYPASS => (*ptr).pll1.read().bypass().bit().into(), + clock_select::PLL2_BYPASS => (*ptr).pll2.read().bypass().bit().into(), + clock_select::PLL2 => (*ptr).pll2.read().ckin_sel().bits().into(), + clock_select::ACLK => (*ptr).clk_sel0.read().aclk_sel().bit().into(), + clock_select::SPI3 => (*ptr).clk_sel0.read().spi3_clk_sel().bit().into(), + clock_select::TIMER0 => (*ptr).clk_sel0.read().timer0_clk_sel().bit().into(), + clock_select::TIMER1 => (*ptr).clk_sel0.read().timer1_clk_sel().bit().into(), + clock_select::TIMER2 => (*ptr).clk_sel0.read().timer2_clk_sel().bit().into(), + clock_select::SPI3_SAMPLE => (*ptr).clk_sel1.read().spi3_sample_clk_sel().bit().into(), + } + } +} + +pub fn clock_get_freq(clock: clock) -> u32 { + // TODO: all of these are source / threshold, where source can depend on clock_select: generalize this + // to some kind of clock tree + // TODO: clock_source_get_freq(ACLK) calls back into here, don't do this + match clock { + clock::IN0 => clock_source_get_freq(clock_source::IN0), + clock::PLL0 => clock_source_get_freq(clock_source::PLL0), + clock::PLL1 => clock_source_get_freq(clock_source::PLL1), + clock::PLL2 => clock_source_get_freq(clock_source::PLL2), + clock::CPU | clock::DMA | clock::FFT | clock::ACLK | clock::HCLK => match clock_get_clock_select(clock_select::ACLK) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => { + clock_source_get_freq(clock_source::PLL0) + / (2 << clock_get_threshold(threshold::ACLK)) + } + _ => panic!("invalid cpu clock select"), + }, + clock::SRAM0 => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::SRAM0) + 1), + clock::SRAM1 => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::SRAM1) + 1), + clock::ROM => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::ROM) + 1), + clock::DVP => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::DVP) + 1), + clock::APB0 | clock::GPIO | clock::UART1 | clock::UART2 | clock::UART3 | clock::FPIOA | clock::SHA => + clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::APB0) + 1), + clock::APB1 | clock::AES | clock::OTP => + clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::APB1) + 1), + clock::APB2 => clock_source_get_freq(clock_source::ACLK) / (clock_get_threshold(threshold::APB2) + 1), + clock::AI => clock_source_get_freq(clock_source::PLL1) / (clock_get_threshold(threshold::AI) + 1), + clock::I2S0 => clock_source_get_freq(clock_source::PLL2) / ((clock_get_threshold(threshold::I2S0) + 1) * 2), + clock::I2S1 => clock_source_get_freq(clock_source::PLL2) / ((clock_get_threshold(threshold::I2S1) + 1) * 2), + clock::I2S2 => clock_source_get_freq(clock_source::PLL2) / ((clock_get_threshold(threshold::I2S2) + 1) * 2), + clock::WDT0 => clock_source_get_freq(clock_source::IN0) / ((clock_get_threshold(threshold::WDT0) + 1) * 2), + clock::WDT1 => clock_source_get_freq(clock_source::IN0) / ((clock_get_threshold(threshold::WDT1) + 1) * 2), + clock::SPI0 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::SPI0) + 1) * 2), + clock::SPI1 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::SPI1) + 1) * 2), + clock::SPI2 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::SPI2) + 1) * 2), + clock::I2C0 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::I2C0) + 1) * 2), + clock::I2C1 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::I2C1) + 1) * 2), + clock::I2C2 => clock_source_get_freq(clock_source::PLL0) / ((clock_get_threshold(threshold::I2C2) + 1) * 2), + clock::SPI3 => { + let source = match clock_get_clock_select(clock_select::SPI3) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::SPI3) + 1) * 2) + } + clock::TIMER0 => { + let source = match clock_get_clock_select(clock_select::TIMER0) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::TIMER0) + 1) * 2) + } + clock::TIMER1 => { + let source = match clock_get_clock_select(clock_select::TIMER1) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::TIMER1) + 1) * 2) + } + clock::TIMER2 => { + let source = match clock_get_clock_select(clock_select::TIMER2) { + 0 => clock_source_get_freq(clock_source::IN0), + 1 => clock_source_get_freq(clock_source::PLL0), + _ => panic!("unimplemented clock source"), + }; + source / ((clock_get_threshold(threshold::TIMER2) + 1) * 2) + } + clock::RTC => clock_source_get_freq(clock_source::IN0), + } +} + +fn reset_ctl(reset: reset, rst_value: bool) { + unsafe { + let ptr = pac::SYSCTL::ptr(); + match reset { + reset::SOC => (*ptr).soft_reset.modify(|_, w| w.soft_reset().bit(rst_value)), + reset::ROM => (*ptr).peri_reset.modify(|_, w| w.rom_reset().bit(rst_value)), + reset::DMA => (*ptr).peri_reset.modify(|_, w| w.dma_reset().bit(rst_value)), + reset::AI => (*ptr).peri_reset.modify(|_, w| w.ai_reset().bit(rst_value)), + reset::DVP => (*ptr).peri_reset.modify(|_, w| w.dvp_reset().bit(rst_value)), + reset::FFT => (*ptr).peri_reset.modify(|_, w| w.fft_reset().bit(rst_value)), + reset::GPIO => (*ptr).peri_reset.modify(|_, w| w.gpio_reset().bit(rst_value)), + reset::SPI0 => (*ptr).peri_reset.modify(|_, w| w.spi0_reset().bit(rst_value)), + reset::SPI1 => (*ptr).peri_reset.modify(|_, w| w.spi1_reset().bit(rst_value)), + reset::SPI2 => (*ptr).peri_reset.modify(|_, w| w.spi2_reset().bit(rst_value)), + reset::SPI3 => (*ptr).peri_reset.modify(|_, w| w.spi3_reset().bit(rst_value)), + reset::I2S0 => (*ptr).peri_reset.modify(|_, w| w.i2s0_reset().bit(rst_value)), + reset::I2S1 => (*ptr).peri_reset.modify(|_, w| w.i2s1_reset().bit(rst_value)), + reset::I2S2 => (*ptr).peri_reset.modify(|_, w| w.i2s2_reset().bit(rst_value)), + reset::I2C0 => (*ptr).peri_reset.modify(|_, w| w.i2c0_reset().bit(rst_value)), + reset::I2C1 => (*ptr).peri_reset.modify(|_, w| w.i2c1_reset().bit(rst_value)), + reset::I2C2 => (*ptr).peri_reset.modify(|_, w| w.i2c2_reset().bit(rst_value)), + reset::UART1 => (*ptr).peri_reset.modify(|_, w| w.uart1_reset().bit(rst_value)), + reset::UART2 => (*ptr).peri_reset.modify(|_, w| w.uart2_reset().bit(rst_value)), + reset::UART3 => (*ptr).peri_reset.modify(|_, w| w.uart3_reset().bit(rst_value)), + reset::AES => (*ptr).peri_reset.modify(|_, w| w.aes_reset().bit(rst_value)), + reset::FPIOA => (*ptr).peri_reset.modify(|_, w| w.fpioa_reset().bit(rst_value)), + reset::TIMER0 => (*ptr).peri_reset.modify(|_, w| w.timer0_reset().bit(rst_value)), + reset::TIMER1 => (*ptr).peri_reset.modify(|_, w| w.timer1_reset().bit(rst_value)), + reset::TIMER2 => (*ptr).peri_reset.modify(|_, w| w.timer2_reset().bit(rst_value)), + reset::WDT0 => (*ptr).peri_reset.modify(|_, w| w.wdt0_reset().bit(rst_value)), + reset::WDT1 => (*ptr).peri_reset.modify(|_, w| w.wdt1_reset().bit(rst_value)), + reset::SHA => (*ptr).peri_reset.modify(|_, w| w.sha_reset().bit(rst_value)), + reset::RTC => (*ptr).peri_reset.modify(|_, w| w.rtc_reset().bit(rst_value)), + } + } +} + +pub fn reset(reset: reset) { + reset_ctl(reset, true); + usleep(10); + reset_ctl(reset, false); +} + +/** Select DMA handshake for a channel */ +pub fn dma_select(channel: dma_channel, select: dma_select) +{ + unsafe { + use dma_channel::*; + let ptr = pac::SYSCTL::ptr(); + match channel { + CHANNEL0 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel0().variant(select)), + CHANNEL1 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel1().variant(select)), + CHANNEL2 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel2().variant(select)), + CHANNEL3 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel3().variant(select)), + CHANNEL4 => (*ptr).dma_sel0.modify(|_,w| w.dma_sel4().variant(select)), + CHANNEL5 => (*ptr).dma_sel1.modify(|_,w| w.dma_sel5().variant(select)), + } + } +} + +/** Return whether the selected PLL has achieved lock */ +fn pll_is_lock(pll: pll) -> bool { + let ptr = pac::SYSCTL::ptr(); + let pll_lock = unsafe { (*ptr).pll_lock.read() }; + match pll { + pll::PLL0 => pll_lock.pll_lock0().bits() == 3, + pll::PLL1 => (pll_lock.pll_lock1().bits() & 1) == 1, + pll::PLL2 => (pll_lock.pll_lock2().bits() & 1) == 1, + } +} + +/** Clear PLL slip, this is done repeatedly until lock is achieved */ +fn pll_clear_slip(pll: pll) -> bool { + let ptr = pac::SYSCTL::ptr(); + unsafe { + (*ptr).pll_lock.modify(|_,w| + match pll { + pll::PLL0 => w.pll_slip_clear0().set_bit(), + pll::PLL1 => w.pll_slip_clear1().set_bit(), + pll::PLL2 => w.pll_slip_clear2().set_bit(), + } + ); + } + pll_is_lock(pll) +} + +fn pll_source_set_freq(pll: pll, source: clock_source, freq: u32) -> Result { + use pll::*; + /* PLL0 and 1 can only source from IN0 */ + if (pll == PLL0 || pll == PLL1) && source != clock_source::IN0 { + return Err(()); + } + let freq_in = clock_source_get_freq(source); + if freq_in == 0 { + return Err(()); + } + if let Some(found) = pll_compute::compute_params(freq_in, freq) { + let ptr = pac::SYSCTL::ptr(); + unsafe { + match pll { + PLL0 => { + (*ptr).pll0.modify(|_,w| + w.clkr().bits(found.clkr) + .clkf().bits(found.clkf) + .clkod().bits(found.clkod) + .bwadj().bits(found.bwadj) + ); + } + PLL1 => { + (*ptr).pll1.modify(|_,w| + w.clkr().bits(found.clkr) + .clkf().bits(found.clkf) + .clkod().bits(found.clkod) + .bwadj().bits(found.bwadj) + ); + } + PLL2 => { + (*ptr).pll2.modify(|_,w| + w.ckin_sel().bits(pll2_source_to_cksel(source)) + .clkr().bits(found.clkr) + .clkf().bits(found.clkf) + .clkod().bits(found.clkod) + .bwadj().bits(found.bwadj) + ); + } + } + } + Ok(pll_get_freq(pll)) + } else { + Err(()) + } +} + +/** + * @brief Init PLL freqency + * @param[in] pll The PLL id + * @param[in] pll_freq The desired frequency in Hz + + */ +pub fn pll_set_freq(pll: pll, freq: u32) -> Result { + let ptr = pac::SYSCTL::ptr(); + use pll::*; + + /* 1. Change CPU CLK to XTAL */ + if pll == PLL0 { + clock_set_clock_select(clock_select::ACLK, 0 /* clock_source::IN0 */); + } + + /* 2. Disable PLL output */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.out_en().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.out_en().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.out_en().clear_bit()), + }; + } + /* 3. Turn off PLL */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.pwrd().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.pwrd().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.pwrd().clear_bit()), + }; + } + /* 4. Set PLL to new value */ + let result = if pll == PLL2 { + pll_source_set_freq(pll, pll2_cksel_to_source(clock_get_clock_select(clock_select::PLL2)), freq) + } else { + pll_source_set_freq(pll, clock_source::IN0, freq) + }; + + /* 5. Power on PLL */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.pwrd().set_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.pwrd().set_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.pwrd().set_bit()), + }; + } + + + /* wait >100ns */ + usleep(1); + + /* 6. Reset PLL then Release Reset*/ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.reset().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.reset().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.reset().clear_bit()), + }; + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.reset().set_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.reset().set_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.reset().set_bit()), + }; + } + /* wait >100ns */ + usleep(1); + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.reset().clear_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.reset().clear_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.reset().clear_bit()), + }; + } + + /* 7. Get lock status, wait PLL stable */ + while !pll_is_lock(pll) { + pll_clear_slip(pll); + } + + /* 8. Enable PLL output */ + unsafe { + match pll { + PLL0 => (*ptr).pll0.modify(|_,w| w.out_en().set_bit()), + PLL1 => (*ptr).pll1.modify(|_,w| w.out_en().set_bit()), + PLL2 => (*ptr).pll2.modify(|_,w| w.out_en().set_bit()), + }; + } + + /* 9. Change CPU CLK to PLL */ + if pll == PLL0 { + clock_set_clock_select(clock_select::ACLK, 1 /*clock_source::PLL0*/); + } + result +} diff --git a/third-party/k210-soc/src/sysctl/pll_compute.rs b/third-party/k210-soc/src/sysctl/pll_compute.rs new file mode 100644 index 00000000..349038ac --- /dev/null +++ b/third-party/k210-soc/src/sysctl/pll_compute.rs @@ -0,0 +1,569 @@ +/** PLL configuration */ +#[derive(Debug, PartialEq, Eq)] +pub struct Params { + pub clkr: u8, + pub clkf: u8, + pub clkod: u8, + pub bwadj: u8, +} + +/* + * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc. + * General-Purpose PLL. The logical layout of the PLL with internal feedback is + * approximately the following: + * + * +---------------+ + * |reference clock| + * +---------------+ + * | + * v + * +--+ + * |/r| + * +--+ + * | + * v + * +-------------+ + * |divided clock| + * +-------------+ + * | + * v + * +--------------+ + * |phase detector|<---+ + * +--------------+ | + * | | + * v +--------------+ + * +---+ |feedback clock| + * |VCO| +--------------+ + * +---+ ^ + * | +--+ | + * +--->|/f|---+ + * | +--+ + * v + * +---+ + * |/od| + * +---+ + * | + * v + * +------+ + * |output| + * +------+ + * + * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode, + * the effect of the division by f is to multiply the input frequency. The + * equation for the output rate is + * rate = (rate_in * f) / (r * od). + * Moving knowns to one side of the equation, we get + * rate / rate_in = f / (r * od) + * Rearranging slightly, + * abs_error = abs((rate / rate_in) - (f / (r * od))). + * To get relative, error, we divide by the expected ratio + * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in). + * Simplifying, + * error = abs(1 - f / (r * od)) / (rate / rate_in) + * error = abs(1 - (f * rate_in) / (r * od * rate)) + * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate, + * error = abs((f * inv_ratio) / (r * od) - 1) + * This is the error used in evaluating parameters. + * + * r and od are four bits each, while f is six bits. Because r and od are + * multiplied together, instead of the full 256 values possible if both bits + * were used fully, there are only 97 distinct products. Combined with f, there + * are 6208 theoretical settings for the PLL. However, most of these settings + * can be ruled out immediately because they do not have the correct ratio. + * + * In addition to the constraint of approximating the desired ratio, parameters + * must also keep internal pll frequencies within acceptable ranges. The divided + * clock's minimum and maximum frequencies have a ratio of around 128. This + * leaves fairly substantial room to work with, especially since the only + * affected parameter is r. The VCO's minimum and maximum frequency have a ratio + * of 5, which is considerably more restrictive. + * + * The r and od factors are stored in a table. This is to make it easy to find + * the next-largest product. Some products have multiple factorizations, but + * only when one factor has at least a 2.5x ratio to the factors of the other + * factorization. This is because any smaller ratio would not make a difference + * when ensuring the VCO's frequency is within spec. + * + * Throughout the calculation function, fixed point arithmetic is used. Because + * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit + * 32.32 fixed-point numbers are used to represent ratios. In general, to + * implement division, the numerator is first multiplied by 2^32. This gives a + * result where the whole number part is in the upper 32 bits, and the fraction + * is in the lower 32 bits. + * + * In general, rounding is done to the closest integer. This helps find the best + * approximation for the ratio. Rounding in one direction (e.g down) could cause + * the function to miss a better ratio with one of the parameters increased by + * one. + */ + +const VCO_MIN: u64 = 340_000_000; +const VCO_MAX: u64 = 1_750_000_000; +const DIV_MIN: u32 = 13_300_000; +const DIV_MAX: u32 = 1_750_000_000; +const R_MIN: u32 = 1; +const R_MAX: u32 = 16; +const F_MIN: u32 = 1; +const F_MAX: u32 = 64; +const OD_MIN: u32 = 1; +const OD_MAX: u32 = 16; +const OUT_MIN: u32 = (VCO_MIN as u32) / OD_MAX; /* 21_250_000 */ +const OUT_MAX: u32 = (VCO_MAX as u32) / OD_MIN; /* 1_750_000_000 */ +const IN_MIN: u32 = DIV_MIN * R_MIN; /* 13_300_000 */ +const IN_MAX: u32 = OUT_MAX; /* 1_750_000_000 */ + +/* + * The factors table was generated with the following python code: + * + * def p(x, y): + * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5) + * + * factors = {} + * for i in range(1, 17): + * for j in range(1, 17): + * fs = factors.get(i*j) or [] + * if fs == [] or all([ + * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y)) + * for (x, y) in fs]): + * fs.append((i, j)) + * factors[i*j] = fs + * + * for k, l in sorted(factors.items()): + * for v in l: + * print("pack(%s, %s)," % v) + */ +struct Factor { + packed: u8, +} + +/* Apologies, but there are no native bitfields (yet) afaik */ +const fn pack(r: u32, od: u32) -> Factor { + Factor { packed: (((((r as u8) - 1) & 0xF) << 4) | (((od as u8) - 1) & 0xF)) } +} + +const fn unpack_r(factor: &&Factor) -> u32 { + (((factor.packed as u32) >> 4) & 0xF) + 1 +} + +const fn unpack_od(factor: &&Factor) -> u32 { + ((factor.packed as u32) & 0xF) + 1 +} + +static FACTORS: &'static [Factor] = &[ + pack(1, 1), + pack(1, 2), + pack(1, 3), + pack(1, 4), + pack(1, 5), + pack(1, 6), + pack(1, 7), + pack(1, 8), + pack(1, 9), + pack(3, 3), + pack(1, 10), + pack(1, 11), + pack(1, 12), + pack(3, 4), + pack(1, 13), + pack(1, 14), + pack(1, 15), + pack(3, 5), + pack(1, 16), + pack(4, 4), + pack(2, 9), + pack(2, 10), + pack(3, 7), + pack(2, 11), + pack(2, 12), + pack(5, 5), + pack(2, 13), + pack(3, 9), + pack(2, 14), + pack(2, 15), + pack(2, 16), + pack(3, 11), + pack(5, 7), + pack(3, 12), + pack(3, 13), + pack(4, 10), + pack(3, 14), + pack(4, 11), + pack(3, 15), + pack(3, 16), + pack(7, 7), + pack(5, 10), + pack(4, 13), + pack(6, 9), + pack(5, 11), + pack(4, 14), + pack(4, 15), + pack(7, 9), + pack(4, 16), + pack(5, 13), + pack(6, 11), + pack(5, 14), + pack(6, 12), + pack(5, 15), + pack(7, 11), + pack(6, 13), + pack(5, 16), + pack(9, 9), + pack(6, 14), + pack(8, 11), + pack(6, 15), + pack(7, 13), + pack(6, 16), + pack(7, 14), + pack(9, 11), + pack(10, 10), + pack(8, 13), + pack(7, 15), + pack(9, 12), + pack(10, 11), + pack(7, 16), + pack(9, 13), + pack(8, 15), + pack(11, 11), + pack(9, 14), + pack(8, 16), + pack(10, 13), + pack(11, 12), + pack(9, 15), + pack(10, 14), + pack(11, 13), + pack(9, 16), + pack(10, 15), + pack(11, 14), + pack(12, 13), + pack(10, 16), + pack(11, 15), + pack(12, 14), + pack(13, 13), + pack(11, 16), + pack(12, 15), + pack(13, 14), + pack(12, 16), + pack(13, 15), + pack(14, 14), + pack(13, 16), + pack(14, 15), + pack(14, 16), + pack(15, 15), + pack(15, 16), + pack(16, 16), +]; + +/* Divide and round to the closest integer */ +fn div_round_closest(n: u64, d: u32) -> u64 { + let _d: u64 = d as u64; + + (n + (_d / 2)) / _d +} + +/* Integer with that bit set */ +fn bit(bit: u8) -> u64 { + 1 << bit +} + +/* | a - b | */ +fn abs_diff(a: u32, b: u32) -> u32 { + if a > b { + a - b + } else { + b - a + } +} + +pub fn compute_params(freq_in: u32, freq_out: u32) -> Option { + let mut best: Option = None; + let mut factors = FACTORS.iter().peekable(); + let (mut error, mut best_error): (i64, i64); + let (ratio, inv_ratio): (u64, u64); /* fixed point 32.32 ratio of the freqs */ + let max_r: u32; + let (mut r, mut f, mut od): (u32, u32, u32); + + /* + * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the + * VCO frequency. These are not the same limits as below because od can + * reduce the output frequency by 16. + */ + if freq_out > OUT_MAX || freq_out < OUT_MIN { + return None; + } + + /* Similar restrictions on the input ratio */ + if freq_in > IN_MAX || freq_in < IN_MIN { + return None; + } + + ratio = div_round_closest((freq_out as u64) << 32, freq_in); + inv_ratio = div_round_closest((freq_in as u64) << 32, freq_out); + /* Can't increase by more than 64 or reduce by more than 256 */ + if freq_out > freq_in && ratio > (64 << 32) { + return None; + } else if freq_out <= freq_in && inv_ratio > (256 << 32) { + return None; + } + + /* + * The divided clock (freq_in / r) must stay between 1.75 GHz and 13.3 + * MHz. There is no minimum, since the only way to get a higher input + * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs + * cannot output frequencies greater than 1.75 GHz, the minimum would + * never be greater than one. + */ + max_r = freq_in / DIV_MIN; + + /* Variables get immediately incremented, so start at -1th iteration */ + f = 0; + r = 0; + od = 0; + best_error = i64::max_value(); + error = best_error; + /* Always try at least one ratio */ + 'outer: loop { + /* + * Whether we swapped r and od while enforcing frequency limits + */ + let mut swapped: bool = false; + let last_od: u32 = od; + let last_r: u32 = r; + + /* + * Try the next largest value for f (or r and od) and + * recalculate the other parameters based on that + */ + if freq_out > freq_in { + /* + * Skip factors of the same product if we already tried + * out that product + */ + while r * od == last_r * last_od { + match factors.next() { + Some(factor) => { + r = unpack_r(&factor); + od = unpack_od(&factor); + }, + None => break 'outer, + } + } + + /* Round close */ + f = ((((r * od) as u64) * ratio + bit(31)) >> 32) as u32; + if f > F_MAX { + f = F_MAX; + } + } else { + f += 1; + let tmp: u64 = (f as u64) * inv_ratio; + let round_up: bool = tmp & bit(31) != 0; + let goal: u32 = ((tmp >> 32) as u32) + (round_up as u32); + let (err, last_err): (u32, u32); + + /* + * Get the next r/od pair in factors. If the last_* pair is better, + * then we will use it instead, so don't call next until after we're + * sure we won't need this pair. + */ + loop { + match factors.peek() { + Some(factor) => { + r = unpack_r(factor); + od = unpack_od(factor) + }, + None => break 'outer, + } + + if r * od < goal { + factors.next(); + } else { + break; + } + } + + /* + * This is a case of double rounding. If we rounded up + * above, we need to round down (in cases of ties) here. + * This prevents off-by-one errors resulting from + * choosing X+2 over X when X.Y rounds up to X+1 and + * there is no r * od = X+1. For the converse, when X.Y + * is rounded down to X, we should choose X+1 over X-1. + */ + err = abs_diff(r * od, goal); + last_err = abs_diff(last_r * last_od, goal); + if last_err < err || (round_up && last_err == err) { + r = last_r; + od = last_od; + } else { + factors.next(); + } + } + + /* + * Enforce limits on internal clock frequencies. If we + * aren't in spec, try swapping r and od. If everything is + * in-spec, calculate the relative error. + */ + loop { + /* + * Whether the intermediate frequencies are out-of-spec + */ + let mut out_of_spec: bool = false; + + if r > max_r { + out_of_spec = true; + } else { + /* + * There is no way to only divide once; we need + * to examine the frequency with and without the + * effect of od. + */ + let vco: u64 = div_round_closest((freq_in as u64) * (f as u64), r); + + if vco > VCO_MAX || vco < VCO_MIN { + out_of_spec = true; + } + } + + if out_of_spec { + if !swapped { + let tmp: u32 = r; + + r = od; + od = tmp; + swapped = true; + continue; + } else { + /* + * Try looking ahead to see if there are + * additional factors for the same + * product. + */ + match factors.peek() { + Some(factor) => { + let new_r: u32 = unpack_r(factor); + let new_od: u32 = unpack_od(factor); + + if r * od == new_r * new_od { + factors.next(); + r = new_r; + od = new_od; + swapped = false; + continue; + } else { + break; + } + }, + None => break 'outer, + } + } + } + + error = div_round_closest((f as u64) * inv_ratio, r * od) as i64; + /* The lower 16 bits are spurious */ + error = i64::abs(error - (bit(32) as i64)) >> 16; + + if error < best_error { + best_error = error; + best = Some(Params { + clkr: (r - 1) as u8, + clkf: (f - 1) as u8, + clkod: (od - 1) as u8, + bwadj: (f - 1) as u8, + }); + } + break; + } + + if error == 0 { + break; + } + } + + return best; +} + +#[cfg(test)] +mod tests { + use super::*; + + fn brute_force_params(freq_in: u32, freq_out: u32) -> Option { + let mut best: Option = None; + let (mut error, mut best_error): (i64, i64); + let (max_r, inv_ratio): (u32, u64); + + best_error = i64::max_value(); + max_r = u32::min(R_MAX, (freq_in / DIV_MIN) as u32); + inv_ratio = div_round_closest((freq_in as u64) << 32, freq_out); + + /* Brute force it */ + for r in R_MIN..=max_r { + for f in F_MIN..=F_MAX { + for od in OD_MIN..=OD_MAX { + let vco: u64 = div_round_closest((freq_in as u64) * (f as u64), r); + + if vco > VCO_MAX || vco < VCO_MIN { + continue; + } + + error = div_round_closest((f as u64) * inv_ratio, r * od) as i64; + /* The lower 16 bits are spurious */ + error = i64::abs(error - (bit(32) as i64)) >> 16; + if error < best_error { + best_error = error; + best = Some(Params { + clkr: (r - 1) as u8, + clkf: (f - 1) as u8, + clkod: (od - 1) as u8, + bwadj: (f - 1) as u8, + }); + } + } + } + } + + return best; + } + + fn params_equal(_a: Option, _b: Option) -> bool { + match (_a, _b) { + (None, None) => true, + (Some(_), None) => false, + (None, Some(_)) => false, + (Some(a), Some(b)) => { + let ar: u32 = (a.clkr + 1) as u32; + let af: u32 = (a.clkf + 1) as u32; + let aod: u32 = (a.clkod + 1) as u32; + let br: u32 = (b.clkr + 1) as u32; + let bf: u32 = (b.clkf + 1) as u32; + let bod: u32 = (b.clkod + 1) as u32; + + af * br * bod == bf * ar * aod + } + } + } + + fn verify_compute_params(freq_in: u32, freq_out: u32) -> bool { + params_equal(compute_params(freq_in, freq_out), brute_force_params(freq_in, freq_out)) + } + + #[test] + fn test_compute_params() { + assert_eq!(compute_params(26_000_000, 0), None); + assert_eq!(compute_params(0, 390_000_000), None); + assert_eq!(compute_params(26_000_000, 2_000_000_000), None); + assert_eq!(compute_params(2_000_000_000, 390_000_000), None); + assert_eq!(compute_params(20_000_000, 1_500_000_000), None); + + assert!(verify_compute_params(26_000_000, 1_500_000_000)); + assert!(verify_compute_params(26_000_000, 1_000_000_000)); + assert!(verify_compute_params(26_000_000, 800_000_000)); + assert!(verify_compute_params(26_000_000, 700_000_000)); + assert!(verify_compute_params(26_000_000, 300_000_000)); + assert!(verify_compute_params(26_000_000, 45_158_400)); + assert!(verify_compute_params(26_000_000, 27_000_000)); + assert!(verify_compute_params(27_000_000, 26_000_000)); + assert!(verify_compute_params(390_000_000, 26_000_000)); + assert!(verify_compute_params(390_000_000, 383_846_400)); + } +} \ No newline at end of file diff --git a/third-party/k210-soc/src/utils.rs b/third-party/k210-soc/src/utils.rs new file mode 100644 index 00000000..94154ff2 --- /dev/null +++ b/third-party/k210-soc/src/utils.rs @@ -0,0 +1,15 @@ +#![allow(unused)] + +//! Miscelleneous utilities for SoC functions (private) + +pub fn set_bit(inval: u32, bit: u8, state: bool) -> u32 { + if state { + inval | (1 << u32::from(bit)) + } else { + inval & !(1 << u32::from(bit)) + } +} + +pub fn get_bit(inval: u32, bit: u8) -> bool { + (inval & (1 << u32::from(bit))) != 0 +} \ No newline at end of file diff --git a/third-party/riscv/.github/CODEOWNERS b/third-party/riscv/.github/CODEOWNERS new file mode 100644 index 00000000..87f6c03f --- /dev/null +++ b/third-party/riscv/.github/CODEOWNERS @@ -0,0 +1 @@ +* @rust-embedded/riscv \ No newline at end of file diff --git a/third-party/riscv/.github/bors.toml b/third-party/riscv/.github/bors.toml new file mode 100644 index 00000000..ca42be0a --- /dev/null +++ b/third-party/riscv/.github/bors.toml @@ -0,0 +1,4 @@ +block_labels = ["needs-decision"] +delete_merged_branches = true +required_approvals = 1 +status = ["continuous-integration/travis-ci/push"] diff --git a/third-party/riscv/.gitignore b/third-party/riscv/.gitignore new file mode 100644 index 00000000..e38997ad --- /dev/null +++ b/third-party/riscv/.gitignore @@ -0,0 +1,5 @@ +Cargo.lock +target/ +bin/*.after +bin/*.before +bin/*.o diff --git a/third-party/riscv/.travis.yml b/third-party/riscv/.travis.yml new file mode 100644 index 00000000..b70d20ab --- /dev/null +++ b/third-party/riscv/.travis.yml @@ -0,0 +1,51 @@ +language: rust + +env: + - TARGET=x86_64-unknown-linux-gnu + - TARGET=riscv32imac-unknown-none-elf + - TARGET=riscv64imac-unknown-none-elf + - TARGET=riscv64gc-unknown-none-elf + +rust: + - nightly + - stable + - 1.42.0 # MSRV + +if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + +matrix: + allow_failures: + - rust: nightly + + include: + - env: CHECK_BLOBS=1 + rust: + language: bash + if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + + - env: RUSTFMT=1 + rust: stable + if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) + + +install: + - ci/install.sh + +script: + - ci/script.sh + + +cache: + cargo: true + directories: + - gcc + +branches: + only: + - master + - staging + - trying + +notifications: + email: + on_success: never diff --git a/third-party/riscv/CHANGELOG.md b/third-party/riscv/CHANGELOG.md new file mode 100644 index 00000000..e4d7b23d --- /dev/null +++ b/third-party/riscv/CHANGELOG.md @@ -0,0 +1,45 @@ +# Change Log + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [Unreleased] + +## [v0.6.0] - 2020-06-20 + +### Changed + +- `Mtvec::trap_mode()`, `Stvec::trap_mode()` and `Utvec::trap_mode()` functions now return `Option` (breaking change) +- Updated Minimum Supported Rust Version to 1.42.0 +- Use `llvm_asm!` instead of `asm!` + +### Removed + +- vexriscv-specific registers were moved to the `vexriscv` crate + +## [v0.5.6] - 2020-03-14 + +### Added + +- Added vexriscv-specific registers + +## [v0.5.5] - 2020-02-28 + +### Added + +- Added `riscv32i-unknown-none-elf` target support +- Added user trap setup and handling registers +- Added write methods for the `mip` and `satp` registers +- Added `mideleg` register +- Added Changelog + +### Changed + +- Fixed MSRV by restricting the upper bound of `bare-metal` version + +[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.6.0...HEAD +[v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0 +[v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6 +[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5 diff --git a/third-party/riscv/CODE_OF_CONDUCT.md b/third-party/riscv/CODE_OF_CONDUCT.md new file mode 100644 index 00000000..fccadf9a --- /dev/null +++ b/third-party/riscv/CODE_OF_CONDUCT.md @@ -0,0 +1,37 @@ +# The Rust Code of Conduct + +## Conduct + +**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team) + +* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic. +* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all. +* Please be kind and courteous. There's no need to be mean or rude. +* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer. +* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works. +* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups. +* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back. +* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome. + +## Moderation + +These are the policies for upholding our community's standards of conduct. + +1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.) +2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed. +3. Moderators will first respond to such remarks with a warning. +4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off. +5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded. +6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology. +7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed. +8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others. + +In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely. + +And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust. + +The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org). + +*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).* + +[team]: https://github.com/rust-embedded/wg#the-riscv-team diff --git a/third-party/riscv/Cargo.toml b/third-party/riscv/Cargo.toml new file mode 100644 index 00000000..4e231932 --- /dev/null +++ b/third-party/riscv/Cargo.toml @@ -0,0 +1,21 @@ +[package] +name = "riscv" +version = "0.6.0" +repository = "https://github.com/rust-embedded/riscv" +authors = ["The RISC-V Team "] +categories = ["embedded", "hardware-support", "no-std"] +description = "Low level access to RISC-V processors" +keywords = ["riscv", "register", "peripheral"] +license = "ISC" + +[dependencies] +bare-metal = "0.2.5" +bitflags = "1.0" +bit_field = "0.10.0" +log = "0.4" + +[build-dependencies] +riscv-target = "0.1.2" + +[features] +inline-asm = [] diff --git a/third-party/riscv/README.md b/third-party/riscv/README.md new file mode 100644 index 00000000..98c7a42c --- /dev/null +++ b/third-party/riscv/README.md @@ -0,0 +1,41 @@ +[![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv) +[![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv) +[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv) + +# `riscv` + +> Low level access to RISC-V processors + +This project is developed and maintained by the [RISC-V team][team]. + +## [Documentation](https://docs.rs/crate/riscv) + +## Minimum Supported Rust Version (MSRV) + +This crate is guaranteed to compile on stable Rust 1.42.0 and up. It *might* +compile with older versions but that may change in any new patch release. + +## License + +Copyright 2019-2020 [RISC-V team][team] + +Permission to use, copy, modify, and/or distribute this software for any purpose +with or without fee is hereby granted, provided that the above copyright notice +and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH +REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND +FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, +INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS +OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +## Code of Conduct + +Contribution to this crate is organized under the terms of the [Rust Code of +Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises +to intervene to uphold that code of conduct. + +[CoC]: CODE_OF_CONDUCT.md +[team]: https://github.com/rust-embedded/wg#the-riscv-team diff --git a/third-party/riscv/asm.S b/third-party/riscv/asm.S new file mode 100644 index 00000000..9ae7aaa8 --- /dev/null +++ b/third-party/riscv/asm.S @@ -0,0 +1,454 @@ +#include "asm.h" + +.section .text.__ebreak +.global __ebreak +__ebreak: + ebreak + ret + +.section .text.__wfi +.global __wfi +__wfi: + wfi + ret + +.section .text.__sfence_vma_all +.global __sfence_vma_all +__sfence_vma_all: + sfence.vma + ret + +.section .text.__sfence_vma +.global __sfence_vma +__sfence_vma: + sfence.vma a0, a1 + ret + +// RISC-V hypervisor instructions. + +// The switch for enabling LLVM support for asm generation. +// #define LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + + +.section .text.__hfence_gvma +.global __hfence_gvma +__hfence_gvma: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hfence.gvma a0, a1 +#else + .word 1656029299 +#endif + ret +.section .text.__hfence_vvma +.global __hfence_vvma +__hfence_vvma: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hfence.vvma a0, a1 +#else + .word 582287475 +#endif + ret +.section .text.__hlv_b +.global __hlv_b +__hlv_b: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.b a0, a0 +#else + .word 1610958195 +#endif + ret +.section .text.__hlv_bu +.global __hlv_bu +__hlv_bu: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.bu a0, a0 +#else + .word 1612006771 +#endif + ret +.section .text.__hlv_h +.global __hlv_h +__hlv_h: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.h a0, a0 +#else + .word 1678067059 +#endif + ret +.section .text.__hlv_hu +.global __hlv_hu +__hlv_hu: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.hu a0, a0 +#else + .word 1679115635 +#endif + ret +.section .text.__hlvx_hu +.global __hlvx_hu +__hlvx_hu: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlvx.hu a0, a0 +#else + .word 1681212787 +#endif + ret +.section .text.__hlv_w +.global __hlv_w +__hlv_w: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.w a0, a0 +#else + .word 1745175923 +#endif + ret +.section .text.__hlvx_wu +.global __hlvx_wu +__hlvx_wu: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlvx.wu a0, a0 +#else + .word 1748321651 +#endif + ret +.section .text.__hsv_b +.global __hsv_b +__hsv_b: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hsv.b a0, a1 +#else + .word 1656045683 +#endif + ret +.section .text.__hsv_h +.global __hsv_h +__hsv_h: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hsv.h a0, a1 +#else + .word 1723154547 +#endif + ret +.section .text.__hsv_w +.global __hsv_w +__hsv_w: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hsv.w a0, a1 +#else + .word 1790263411 +#endif + ret +.section .text.__hlv_wu +.global __hlv_wu +__hlv_wu: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.wu a0, a0 +#else + .word 1746224499 +#endif + ret +.section .text.__hlv_d +.global __hlv_d +__hlv_d: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hlv.d a0, a0 +#else + .word 1812284787 +#endif + ret +.section .text.__hsv_d +.global __hsv_d +__hsv_d: +#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT + hsv.d a0, a1 +#else + .word 1857372275 +#endif + ret + + +// User Trap Setup +RW(0x000, ustatus) // User status register +RW(0x004, uie) // User interrupt-enable register +RW(0x005, utvec) // User trap handler base address + +// User Trap Handling +RW(0x040, uscratch) // Scratch register for user trap handlers +RW(0x041, uepc) // User exception program counter +RW(0x042, ucause) // User trap cause +RW(0x043, utval) // User bad address or instruction +RW(0x044, uip) // User interrupt pending + +// User Floating-Point CSRs +RW(0x001, fflags) // Floating-Point Accrued Exceptions +RW(0x002, frm) // Floating-Point Dynamic Rounding Mode +RW(0x003, fcsr) // Floating-Point Control and Status Register (frm + fflags) + +// User Counter/Timers +RO( 0xC00, cycle) // Cycle counter for RDCYCLE instruction +RO( 0xC01, time) // Timer for RDTIME instruction +RO( 0xC02, instret) // Instructions-retired counter for RDINSTRET instruction +RO( 0xC03, hpmcounter3) // Performance-monitoring counter +RO( 0xC04, hpmcounter4) // Performance-monitoring counter +RO( 0xC05, hpmcounter5) // Performance-monitoring counter +RO( 0xC06, hpmcounter6) // Performance-monitoring counter +RO( 0xC07, hpmcounter7) // Performance-monitoring counter +RO( 0xC08, hpmcounter8) // Performance-monitoring counter +RO( 0xC09, hpmcounter9) // Performance-monitoring counter +RO( 0xC0A, hpmcounter10) // Performance-monitoring counter +RO( 0xC0B, hpmcounter11) // Performance-monitoring counter +RO( 0xC0C, hpmcounter12) // Performance-monitoring counter +RO( 0xC0D, hpmcounter13) // Performance-monitoring counter +RO( 0xC0E, hpmcounter14) // Performance-monitoring counter +RO( 0xC0F, hpmcounter15) // Performance-monitoring counter +RO( 0xC10, hpmcounter16) // Performance-monitoring counter +RO( 0xC11, hpmcounter17) // Performance-monitoring counter +RO( 0xC12, hpmcounter18) // Performance-monitoring counter +RO( 0xC13, hpmcounter19) // Performance-monitoring counter +RO( 0xC14, hpmcounter20) // Performance-monitoring counter +RO( 0xC15, hpmcounter21) // Performance-monitoring counter +RO( 0xC16, hpmcounter22) // Performance-monitoring counter +RO( 0xC17, hpmcounter23) // Performance-monitoring counter +RO( 0xC18, hpmcounter24) // Performance-monitoring counter +RO( 0xC19, hpmcounter25) // Performance-monitoring counter +RO( 0xC1A, hpmcounter26) // Performance-monitoring counter +RO( 0xC1B, hpmcounter27) // Performance-monitoring counter +RO( 0xC1C, hpmcounter28) // Performance-monitoring counter +RO( 0xC1D, hpmcounter29) // Performance-monitoring counter +RO( 0xC1E, hpmcounter30) // Performance-monitoring counter +RO( 0xC1F, hpmcounter31) // Performance-monitoring counter +RO32(0xC80, cycleh) // Upper 32 bits of cycle, RV32I only +RO32(0xC81, timeh) // Upper 32 bits of time, RV32I only +RO32(0xC82, instreth) // Upper 32 bits of instret, RV32I only +RO32(0xC83, hpmcounter3h) // Upper 32 bits of hpmcounter3, RV32I only +RO32(0xC84, hpmcounter4h) +RO32(0xC85, hpmcounter5h) +RO32(0xC86, hpmcounter6h) +RO32(0xC87, hpmcounter7h) +RO32(0xC88, hpmcounter8h) +RO32(0xC89, hpmcounter9h) +RO32(0xC8A, hpmcounter10h) +RO32(0xC8B, hpmcounter11h) +RO32(0xC8C, hpmcounter12h) +RO32(0xC8D, hpmcounter13h) +RO32(0xC8E, hpmcounter14h) +RO32(0xC8F, hpmcounter15h) +RO32(0xC90, hpmcounter16h) +RO32(0xC91, hpmcounter17h) +RO32(0xC92, hpmcounter18h) +RO32(0xC93, hpmcounter19h) +RO32(0xC94, hpmcounter20h) +RO32(0xC95, hpmcounter21h) +RO32(0xC96, hpmcounter22h) +RO32(0xC97, hpmcounter23h) +RO32(0xC98, hpmcounter24h) +RO32(0xC99, hpmcounter25h) +RO32(0xC9A, hpmcounter26h) +RO32(0xC9B, hpmcounter27h) +RO32(0xC9C, hpmcounter28h) +RO32(0xC9D, hpmcounter29h) +RO32(0xC9E, hpmcounter30h) +RO32(0xC9F, hpmcounter31h) + +// Supervisor Trap Setup +RW(0x100, sstatus) // Supervisor status register +RW(0x102, sedeleg) // Supervisor exception delegation register +RW(0x103, sideleg) // Supervisor interrupt delegation register +RW(0x104, sie) // Supervisor interrupt-enable register +RW(0x105, stvec) // Supervisor trap handler base address +RW(0x106, scounteren) // Supervisor counter enable + +// Supervisor Trap Handling +RW(0x140, sscratch) // Scratch register for supervisor trap handlers +RW(0x141, sepc) // Supervisor exception program counter +RW(0x142, scause) // Supervisor trap cause +RW(0x143, stval) // Supervisor bad address or instruction +RW(0x144, sip) // Supervisor interrupt pending + +// Supervisor Protection and Translation +RW(0x180, satp) // Supervisor address translation and protection + +// Machine Information Registers +RO(0xF11, mvendorid) // Vendor ID +RO(0xF12, marchid) // Architecture ID +RO(0xF13, mimpid) // Implementation ID +RO(0xF14, mhartid) // Hardware thread ID + +// Machine Trap Setup +RW(0x300, mstatus) // Machine status register +RW(0x301, misa) // ISA and extensions +RW(0x302, medeleg) // Machine exception delegation register +RW(0x303, mideleg) // Machine interrupt delegation register +RW(0x304, mie) // Machine interrupt-enable register +RW(0x305, mtvec) // Machine trap handler base address +RW(0x306, mcounteren) // Machine counter enable + +// Machine Trap Handling +RW(0x340, mscratch) // Scratch register for machine trap handlers +RW(0x341, mepc) // Machine exception program counter +RW(0x342, mcause) // Machine trap cause +RW(0x343, mtval) // Machine bad address or instruction +RW(0x344, mip) // Machine interrupt pending + +// Machine Protection and Translation +RW( 0x3A0, pmpcfg0) // Physical memory protection configuration +RW32(0x3A1, pmpcfg1) // Physical memory protection configuration, RV32 only +RW( 0x3A2, pmpcfg2) // Physical memory protection configuration +RW32(0x3A3, pmpcfg3) // Physical memory protection configuration, RV32 only +RW( 0x3B0, pmpaddr0) // Physical memory protection address register +RW( 0x3B1, pmpaddr1) // Physical memory protection address register +RW( 0x3B2, pmpaddr2) // Physical memory protection address register +RW( 0x3B3, pmpaddr3) // Physical memory protection address register +RW( 0x3B4, pmpaddr4) // Physical memory protection address register +RW( 0x3B5, pmpaddr5) // Physical memory protection address register +RW( 0x3B6, pmpaddr6) // Physical memory protection address register +RW( 0x3B7, pmpaddr7) // Physical memory protection address register +RW( 0x3B8, pmpaddr8) // Physical memory protection address register +RW( 0x3B9, pmpaddr9) // Physical memory protection address register +RW( 0x3BA, pmpaddr10) // Physical memory protection address register +RW( 0x3BB, pmpaddr11) // Physical memory protection address register +RW( 0x3BC, pmpaddr12) // Physical memory protection address register +RW( 0x3BD, pmpaddr13) // Physical memory protection address register +RW( 0x3BE, pmpaddr14) // Physical memory protection address register +RW( 0x3BF, pmpaddr15) // Physical memory protection address register + +// Machine Counter/Timers +RO( 0xB00, mcycle) // Machine cycle counter +RO( 0xB02, minstret) // Machine instructions-retired counter +RO( 0xB03, mhpmcounter3) // Machine performance-monitoring counter +RO( 0xB04, mhpmcounter4) // Machine performance-monitoring counter +RO( 0xB05, mhpmcounter5) // Machine performance-monitoring counter +RO( 0xB06, mhpmcounter6) // Machine performance-monitoring counter +RO( 0xB07, mhpmcounter7) // Machine performance-monitoring counter +RO( 0xB08, mhpmcounter8) // Machine performance-monitoring counter +RO( 0xB09, mhpmcounter9) // Machine performance-monitoring counter +RO( 0xB0A, mhpmcounter10) // Machine performance-monitoring counter +RO( 0xB0B, mhpmcounter11) // Machine performance-monitoring counter +RO( 0xB0C, mhpmcounter12) // Machine performance-monitoring counter +RO( 0xB0D, mhpmcounter13) // Machine performance-monitoring counter +RO( 0xB0E, mhpmcounter14) // Machine performance-monitoring counter +RO( 0xB0F, mhpmcounter15) // Machine performance-monitoring counter +RO( 0xB10, mhpmcounter16) // Machine performance-monitoring counter +RO( 0xB11, mhpmcounter17) // Machine performance-monitoring counter +RO( 0xB12, mhpmcounter18) // Machine performance-monitoring counter +RO( 0xB13, mhpmcounter19) // Machine performance-monitoring counter +RO( 0xB14, mhpmcounter20) // Machine performance-monitoring counter +RO( 0xB15, mhpmcounter21) // Machine performance-monitoring counter +RO( 0xB16, mhpmcounter22) // Machine performance-monitoring counter +RO( 0xB17, mhpmcounter23) // Machine performance-monitoring counter +RO( 0xB18, mhpmcounter24) // Machine performance-monitoring counter +RO( 0xB19, mhpmcounter25) // Machine performance-monitoring counter +RO( 0xB1A, mhpmcounter26) // Machine performance-monitoring counter +RO( 0xB1B, mhpmcounter27) // Machine performance-monitoring counter +RO( 0xB1C, mhpmcounter28) // Machine performance-monitoring counter +RO( 0xB1D, mhpmcounter29) // Machine performance-monitoring counter +RO( 0xB1E, mhpmcounter30) // Machine performance-monitoring counter +RO( 0xB1F, mhpmcounter31) // Machine performance-monitoring counter +RO32(0xB80, mcycleh) // Upper 32 bits of mcycle, RV32I only +RO32(0xB82, minstreth) // Upper 32 bits of minstret, RV32I only +RO32(0xB83, mhpmcounter3h) // Upper 32 bits of mhpmcounter3, RV32I only +RO32(0xB84, mhpmcounter4h) +RO32(0xB85, mhpmcounter5h) +RO32(0xB86, mhpmcounter6h) +RO32(0xB87, mhpmcounter7h) +RO32(0xB88, mhpmcounter8h) +RO32(0xB89, mhpmcounter9h) +RO32(0xB8A, mhpmcounter10h) +RO32(0xB8B, mhpmcounter11h) +RO32(0xB8C, mhpmcounter12h) +RO32(0xB8D, mhpmcounter13h) +RO32(0xB8E, mhpmcounter14h) +RO32(0xB8F, mhpmcounter15h) +RO32(0xB90, mhpmcounter16h) +RO32(0xB91, mhpmcounter17h) +RO32(0xB92, mhpmcounter18h) +RO32(0xB93, mhpmcounter19h) +RO32(0xB94, mhpmcounter20h) +RO32(0xB95, mhpmcounter21h) +RO32(0xB96, mhpmcounter22h) +RO32(0xB97, mhpmcounter23h) +RO32(0xB98, mhpmcounter24h) +RO32(0xB99, mhpmcounter25h) +RO32(0xB9A, mhpmcounter26h) +RO32(0xB9B, mhpmcounter27h) +RO32(0xB9C, mhpmcounter28h) +RO32(0xB9D, mhpmcounter29h) +RO32(0xB9E, mhpmcounter30h) +RO32(0xB9F, mhpmcounter31h) + +RW(0x323, mhpmevent3) // Machine performance-monitoring event selector +RW(0x324, mhpmevent4) // Machine performance-monitoring event selector +RW(0x325, mhpmevent5) // Machine performance-monitoring event selector +RW(0x326, mhpmevent6) // Machine performance-monitoring event selector +RW(0x327, mhpmevent7) // Machine performance-monitoring event selector +RW(0x328, mhpmevent8) // Machine performance-monitoring event selector +RW(0x329, mhpmevent9) // Machine performance-monitoring event selector +RW(0x32A, mhpmevent10) // Machine performance-monitoring event selector +RW(0x32B, mhpmevent11) // Machine performance-monitoring event selector +RW(0x32C, mhpmevent12) // Machine performance-monitoring event selector +RW(0x32D, mhpmevent13) // Machine performance-monitoring event selector +RW(0x32E, mhpmevent14) // Machine performance-monitoring event selector +RW(0x32F, mhpmevent15) // Machine performance-monitoring event selector +RW(0x330, mhpmevent16) // Machine performance-monitoring event selector +RW(0x331, mhpmevent17) // Machine performance-monitoring event selector +RW(0x332, mhpmevent18) // Machine performance-monitoring event selector +RW(0x333, mhpmevent19) // Machine performance-monitoring event selector +RW(0x334, mhpmevent20) // Machine performance-monitoring event selector +RW(0x335, mhpmevent21) // Machine performance-monitoring event selector +RW(0x336, mhpmevent22) // Machine performance-monitoring event selector +RW(0x337, mhpmevent23) // Machine performance-monitoring event selector +RW(0x338, mhpmevent24) // Machine performance-monitoring event selector +RW(0x339, mhpmevent25) // Machine performance-monitoring event selector +RW(0x33A, mhpmevent26) // Machine performance-monitoring event selector +RW(0x33B, mhpmevent27) // Machine performance-monitoring event selector +RW(0x33C, mhpmevent28) // Machine performance-monitoring event selector +RW(0x33D, mhpmevent29) // Machine performance-monitoring event selector +RW(0x33E, mhpmevent30) // Machine performance-monitoring event selector +RW(0x33F, mhpmevent31) // Machine performance-monitoring event selector + +// Debug/Trace Registers (shared with Debug Mode) +RW(0x7A0, tselect) // Debug/Trace trigger register select +RW(0x7A1, tdata1) // First Debug/Trace trigger data register +RW(0x7A2, tdata2) // Second Debug/Trace trigger data register +RW(0x7A3, tdata3) // Third Debug/Trace trigger data register + +// Debug Mode Registers +RW(0x7B0, dcsr) // Debug control and status register +RW(0x7B1, dpc) // Debug PC +RW(0x7B2, dscratch) // Debug scratch register + +// Hypervisor Trap Setup +RW(0x600, hstatus) // Hypervisor status register +RW(0x602, hedeleg) // Hypervisor exception delegation register +RW(0x603, hideleg) // Hypervisor interrupt delegation register +RW(0x604, hie) // Hypervisor interrupt-enable register +RW(0x606, hcounteren) // Hypervisor counter enable +RW(0x607, hgeie) // Hypervisor guest external interrupt-enable register + +// Hypervisor Trap Handling +RW(0x643, htval) // Hypervisor bad guest physical address +RW(0x644, hip) // Hypervisor interrupt pending +RW(0x645, hvip) // Hypervisor virtual interrupt pending +RW(0x64a, htinst) // Hypervisor trap instruction (transformed) +RW(0xe12, hgeip) // Hypervisor guest external interrupt pending + +// Hypervisor Protection and Translation +RO(0x680, hgatp) // Hypervisor guest address translation and protection + +// Debug/Trace Registers +RW(0x6a8, hcontext) // Hypervisor-mode context register + +// Hypervisor Counter/Timer Virtualization Registers +RW(0x605, htimedelta) // Delta for VS/VU-mode timer +RW32(0x615, htimedeltah) // Upper 32 bits of {\tt htimedelta}, RV32 only + +// Virtual Supervisor Registers +RW(0x200, vsstatus) // Virtual supervisor status register +RW(0x204, vsie) // Virtual supervisor interrupt-enable register +RW(0x205, vstvec) // Virtual supervisor trap handler base address +RW(0x240, vsscratch) // Virtual supervisor scratch register +RW(0x241, vsepc) // Virtual supervisor exception program counter +RW(0x242, vscause) // Virtual supervisor trap cause +RW(0x243, vstval) // Virtual supervisor bad address or instruction +RW(0x244, vsip) // Virtual supervisor interrupt pending +RW(0x280, vsatp) // Virtual supervisor address translation and protection diff --git a/third-party/riscv/asm.h b/third-party/riscv/asm.h new file mode 100644 index 00000000..2b675e7c --- /dev/null +++ b/third-party/riscv/asm.h @@ -0,0 +1,48 @@ +#ifndef __ASM_H +#define __ASM_H + +#define REG_READ(name, offset) \ +.section .text.__read_ ## name; \ +.global __read_ ## name; \ +__read_ ## name: \ + csrrs a0, offset, x0; \ + ret + +#define REG_WRITE(name, offset) \ +.section .text.__write_ ## name; \ +.global __write_ ## name; \ +__write_ ## name: \ + csrrw x0, offset, a0; \ + ret + +#define REG_SET(name, offset) \ +.section .text.__set_ ## name; \ +.global __set_ ## name; \ +__set_ ## name: \ + csrrs x0, offset, a0; \ + ret + +#define REG_CLEAR(name, offset) \ +.section .text.__clear_ ## name; \ +.global __clear_ ## name; \ +__clear_ ## name: \ + csrrc x0, offset, a0; \ + ret + + +#define REG_READ_WRITE(name, offset) REG_READ(name, offset); REG_WRITE(name, offset) +#define REG_SET_CLEAR(name, offset) REG_SET(name, offset); REG_CLEAR(name, offset) + +#define RW(offset, name) REG_READ_WRITE(name, offset); REG_SET_CLEAR(name, offset) +#define RO(offset, name) REG_READ(name, offset) + +#if __riscv_xlen == 32 +#define RW32(offset, name) RW(offset, name) +#define RO32(offset, name) RO(offset, name) +#else +#define RW32(offset, name) +#define RO32(offset, name) +#endif + +#endif /* __ASM_H */ + diff --git a/third-party/riscv/assemble.ps1 b/third-party/riscv/assemble.ps1 new file mode 100644 index 00000000..1bfc2656 --- /dev/null +++ b/third-party/riscv/assemble.ps1 @@ -0,0 +1,20 @@ +New-Item -Force -Name bin -Type Directory + +# remove existing blobs because otherwise this will append object files to the old blobs +Remove-Item -Force bin/*.a + +$crate = "riscv" + +riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o +riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o + +riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic asm.S -o bin/$crate.o +riscv64-unknown-elf-ar crs bin/riscv32ic-unknown-none-elf.a bin/$crate.o + +riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64i asm.S -o bin/$crate.o +riscv64-unknown-elf-ar crs bin/riscv64i-unknown-none-elf.a bin/$crate.o + +riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64ic asm.S -o bin/$crate.o +riscv64-unknown-elf-ar crs bin/riscv64ic-unknown-none-elf.a bin/$crate.o + +Remove-Item bin/$crate.o diff --git a/third-party/riscv/assemble.sh b/third-party/riscv/assemble.sh new file mode 100755 index 00000000..217131dc --- /dev/null +++ b/third-party/riscv/assemble.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +set -euxo pipefail + +crate=riscv + +# remove existing blobs because otherwise this will append object files to the old blobs +rm -f bin/*.a + +riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o +ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o + +riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic asm.S -o bin/$crate.o +ar crs bin/riscv32ic-unknown-none-elf.a bin/$crate.o + +riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64i asm.S -o bin/$crate.o +ar crs bin/riscv64i-unknown-none-elf.a bin/$crate.o + +riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64ic asm.S -o bin/$crate.o +ar crs bin/riscv64ic-unknown-none-elf.a bin/$crate.o + +rm bin/$crate.o diff --git a/third-party/riscv/bin/riscv32i-unknown-none-elf.a b/third-party/riscv/bin/riscv32i-unknown-none-elf.a new file mode 100644 index 00000000..883d6556 Binary files /dev/null and b/third-party/riscv/bin/riscv32i-unknown-none-elf.a differ diff --git a/third-party/riscv/bin/riscv32ic-unknown-none-elf.a b/third-party/riscv/bin/riscv32ic-unknown-none-elf.a new file mode 100644 index 00000000..be6352dc Binary files /dev/null and b/third-party/riscv/bin/riscv32ic-unknown-none-elf.a differ diff --git a/third-party/riscv/bin/riscv64i-unknown-none-elf.a b/third-party/riscv/bin/riscv64i-unknown-none-elf.a new file mode 100644 index 00000000..a4117f11 Binary files /dev/null and b/third-party/riscv/bin/riscv64i-unknown-none-elf.a differ diff --git a/third-party/riscv/bin/riscv64ic-unknown-none-elf.a b/third-party/riscv/bin/riscv64ic-unknown-none-elf.a new file mode 100644 index 00000000..3201ce3c Binary files /dev/null and b/third-party/riscv/bin/riscv64ic-unknown-none-elf.a differ diff --git a/third-party/riscv/build.rs b/third-party/riscv/build.rs new file mode 100644 index 00000000..d1c33289 --- /dev/null +++ b/third-party/riscv/build.rs @@ -0,0 +1,35 @@ +extern crate riscv_target; + +use riscv_target::Target; +use std::path::PathBuf; +use std::{env, fs}; + +fn main() { + let target = env::var("TARGET").unwrap(); + let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); + let name = env::var("CARGO_PKG_NAME").unwrap(); + + if target.starts_with("riscv") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() { + let mut target = Target::from_target_str(&target); + target.retain_extensions("ic"); + + let target = target.to_string(); + + fs::copy( + format!("bin/{}.a", target), + out_dir.join(format!("lib{}.a", name)), + ) + .unwrap(); + + println!("cargo:rustc-link-lib=static={}", name); + println!("cargo:rustc-link-search={}", out_dir.display()); + } + + if target.contains("riscv32") { + println!("cargo:rustc-cfg=riscv"); + println!("cargo:rustc-cfg=riscv32"); + } else if target.contains("riscv64") { + println!("cargo:rustc-cfg=riscv"); + println!("cargo:rustc-cfg=riscv64"); + } +} diff --git a/third-party/riscv/check-blobs.sh b/third-party/riscv/check-blobs.sh new file mode 100755 index 00000000..36d885e6 --- /dev/null +++ b/third-party/riscv/check-blobs.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +# Checks that the blobs are up to date with the committed assembly files + +set -euxo pipefail + +for lib in $(ls bin/*.a); do + filename=$(basename $lib) + riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before +done + +./assemble.sh + +for lib in $(ls bin/*.a); do + filename=$(basename $lib) + riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after +done + +for cksum in $(ls bin/*.after); do + diff -u $cksum ${cksum%.after}.before +done diff --git a/third-party/riscv/ci/install.sh b/third-party/riscv/ci/install.sh new file mode 100755 index 00000000..2378704d --- /dev/null +++ b/third-party/riscv/ci/install.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +set -euxo pipefail + +if [ -n "${TARGET:-}" ]; then + rustup target add $TARGET +fi + +if [ -n "${CHECK_BLOBS:-}" ]; then + if [ ! -d gcc/bin ]; then + mkdir -p gcc + curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz + fi +fi + +if [ -n "${RUSTFMT:-}" ]; then + rustup component add rustfmt +fi diff --git a/third-party/riscv/ci/script.sh b/third-party/riscv/ci/script.sh new file mode 100755 index 00000000..be42e3da --- /dev/null +++ b/third-party/riscv/ci/script.sh @@ -0,0 +1,22 @@ +#!/usr/bin/env bash + +set -euxo pipefail + +export PATH=$PATH:~/.cargo/bin + +if [ -n "${TARGET:-}" ]; then + cargo check --target $TARGET + + if [ $TRAVIS_RUST_VERSION = nightly ]; then + cargo check --target $TARGET --features inline-asm + fi +fi + +if [ -n "${CHECK_BLOBS:-}" ]; then + PATH="$PATH:$PWD/gcc/bin" + ./check-blobs.sh +fi + +if [ -n "${RUSTFMT:-}" ]; then + cargo fmt -- --check +fi diff --git a/third-party/riscv/descriptor/generate_hypervisor_csr.sh b/third-party/riscv/descriptor/generate_hypervisor_csr.sh new file mode 100755 index 00000000..d6e009aa --- /dev/null +++ b/third-party/riscv/descriptor/generate_hypervisor_csr.sh @@ -0,0 +1,8 @@ +#!/bin/bash +rustc generator.rs +rm -f ../src/register/hypervisorx64/mod.rs; +for i in *.txt; do + ./generator <$i > ../src/register/hypervisorx64/`basename -s .txt $i`.rs; + echo "pub mod $(basename -s .txt $i);" >> ../src/register/hypervisorx64/mod.rs; +done +rm -f generator \ No newline at end of file diff --git a/third-party/riscv/descriptor/generator.rs b/third-party/riscv/descriptor/generator.rs new file mode 100644 index 00000000..35d69b5e --- /dev/null +++ b/third-party/riscv/descriptor/generator.rs @@ -0,0 +1,355 @@ +use std::fmt::*; +macro_rules! CSR_ACCESSOR { + () => { + r#" +pub mod csr {{ + pub const CSR_ID: usize = {}; + #[inline] + pub unsafe fn csrrw(rs1: usize)->usize{{ + let mut rd; + llvm_asm!("csrrw $0, $2, $1" :"=r"(rd): "r"(rs1), "i"(CSR_ID) :: "volatile"); + rd + }} + #[inline] + pub unsafe fn csrrw_x0(rs1: usize){{ + llvm_asm!("csrrw x0, $1, $0" :: "r"(rs1), "i"(CSR_ID) :: "volatile"); + }} + #[inline] + pub unsafe fn csrrs(rs1: usize)->usize{{ + let mut rd; + llvm_asm!("csrrs $0, $2, $1" :"=r"(rd): "r"(rs1), "i"(CSR_ID) :: "volatile"); + rd + }} + #[inline] + pub unsafe fn csrrs_x0()->usize{{ + let mut rd; + llvm_asm!("csrrs $0, $1, x0" :"=r"(rd): "i"(CSR_ID) :: "volatile"); + rd + }} + #[inline] + pub unsafe fn csrrc(rs1: usize)->usize{{ + let mut rd; + llvm_asm!("csrrc $0, $2, $1" :"=r"(rd): "r"(rs1), "i"(CSR_ID) :: "volatile"); + rd + }} + #[inline] + pub unsafe fn csrrc_x0()->usize{{ + let mut rd; + llvm_asm!("csrrc $0, $1, x0" :"=r"(rd): "i"(CSR_ID) :: "volatile"); + rd + }} +}} +"# + }; +} + +macro_rules! as_str_polyfill { + ($x: expr, $r: expr) => {{ + let mut y = $x.clone(); + if let Some(x) = y.next() { + $r.split_at(x.as_ptr() as usize - $r.as_ptr() as usize).1 + } else { + "" + } + }}; +} +#[derive(Debug, Clone)] +struct EnumerationDescriptor<'a> { + enumerations: Vec<(&'a str, usize)>, +} +impl<'a> EnumerationDescriptor<'a> { + pub fn parse(enums: &'a str) -> Self { + let mut counter = 0; + let list = enums.split(";"); + let mut e = Vec::new(); + for tup in list { + let mut t = tup.split("="); + let n = t.next().unwrap(); + if let Some(new_id) = t.next() { + counter = new_id.parse().unwrap(); + } + e.push((n, counter)); + counter += 1; + } + EnumerationDescriptor { enumerations: e } + } + fn generate_enum(&self, name: &str) -> String { + let mut ret = String::new(); + write!( + &mut ret, + "#[derive(Copy, Clone, Debug)] +#[repr(usize)] +" + ) + .unwrap(); + write!(&mut ret, "pub enum {}{{\n", name).unwrap(); + let mut branches = String::new(); + for e in self.enumerations.iter() { + write!(&mut ret, " {} = {},\n", e.0, e.1).unwrap(); + write!(&mut branches, " {} => Self::{},\n", e.1, e.0).unwrap(); + } + + write!( + &mut ret, + "}} +impl {}{{ + fn from(x: usize)->Self{{ + match x{{ +{} _ => unreachable!() + }} + }} +}} +", + name, branches + ) + .unwrap(); + return ret; + } +} +#[derive(Debug, Clone)] +struct BitFieldDescriptor<'a> { + name: &'a str, + description: &'a str, + lo: usize, + hi: usize, + ed: Option<(&'a str, EnumerationDescriptor<'a>)>, +} + +impl<'a> BitFieldDescriptor<'a> { + pub fn parse(desc: &'a str) -> Self { + let mut parts = desc.split(","); + let name = parts.next().unwrap(); + let hi = parts.next().unwrap().parse::().unwrap(); + let lo = parts.next().unwrap().parse::().unwrap(); + let (lo, hi) = if lo < hi { (lo, hi) } else { (hi, lo) }; + let use_enum = parts.next().unwrap(); + let ed = if use_enum != "number" { + let opts = parts.next().unwrap(); + Some((use_enum, EnumerationDescriptor::parse(opts))) + } else { + None + }; + let description = as_str_polyfill!(parts, desc); + BitFieldDescriptor { + name, + lo, + hi, + description, + ed, + } + } + pub fn generate_enum(&self) -> Option { + if let Some((n, e)) = &self.ed { + Some(e.generate_enum(n)) + } else { + None + } + } + pub fn flag_type(&self) -> &str { + if let Some((n, _)) = self.ed { + n + } else { + if self.lo == self.hi { + "bool" + } else { + "usize" + } + } + } + fn mask(&self) -> String { + format!("{}", (1usize << (self.hi - self.lo + 1)) - 1) + } + fn getter(&self) -> String { + if self.lo == self.hi { + return format!("self.bits.get_bit({})", self.lo); + } else if self.flag_type() != "usize" { + return format!( + "{}::from(self.bits.get_bits({}..{}))", + self.flag_type(), + self.lo, + self.hi + 1 + ); + } else { + return format!("self.bits.get_bits({}..{})", self.lo, self.hi + 1); + } + } + fn setter(&self) -> String { + if self.lo == self.hi { + return format!("self.bits.set_bit({}, val);", self.lo); + } else if self.flag_type() != "usize" { + return format!( + "self.bits.set_bits({}..{}, val as usize);", + self.lo, + self.hi + 1 + ); + } else { + return format!("self.bits.set_bits({}..{}, val);", self.lo, self.hi + 1); + } + } + fn generate_read_write(&self) -> String { + format!( + " /// {} + #[inline] + pub fn {}(&self)->{}{{ + {} + }} + #[inline] + pub fn set_{}(&mut self, val: {}){{ + {} + }}\n", + self.description, + self.name, + self.flag_type(), + self.getter(), + self.name, + self.flag_type(), + self.setter() + ) + } + + fn generate_bit_set(&self) -> String { + format!( + " pub fn set_{}()->bool{{ + unsafe {{csr::csrrc({}) & {} !=0}} + }} + pub fn clear_{}()->bool{{ + unsafe {{csr::csrrs({}) & {} !=0 }} + }}\n", + self.name, + 1usize << self.lo, + 1usize << self.lo, + self.name, + 1usize << self.lo, + 1usize << self.lo + ) + } + fn generate_bitops(&self) -> String { + format!( + " set_clear_csr!( + ///{} + , set_{}, clear_{}, 1 << {});\n", + self.description, self.name, self.name, self.lo + ) + } +} + +#[derive(Debug, Clone)] +struct CSRDescriptor<'a> { + name: &'a str, + id: usize, + description: &'a str, + bfs: Vec>, +} + +impl<'a> CSRDescriptor<'a> { + fn canonical_name(&self) -> String { + self.name.to_lowercase() + } + pub fn parse(d: &'a str) -> Self { + let mut parts = d.split("\n"); + let name = parts.next().unwrap(); + let id = parts.next().unwrap().parse::().unwrap(); + let mut bfs = Vec::new(); + while let Some(x) = parts.next() { + if x == "end" { + break; + } else { + bfs.push(BitFieldDescriptor::parse(x)); + } + } + CSRDescriptor { + name, + id, + description: as_str_polyfill!(parts, d), + bfs, + } + } + pub fn generate(&self) -> String { + let mut trait_impls = String::new(); + let mut bit_sets = String::new(); + let mut enums = String::new(); + for bf in self.bfs.iter() { + if bf.lo == bf.hi { + write!(&mut bit_sets, "{}", bf.generate_bitops()).unwrap(); + //write!(&mut trait_impls, "{}",bf.generate_bit_set()).unwrap(); + } + write!(&mut trait_impls, "{}", bf.generate_read_write()).unwrap(); + if let Some(x) = bf.generate_enum() { + write!(&mut enums, "{}", x).unwrap(); + } + } + if &trait_impls == "" && &bit_sets == "" { + format!( + " +//! {} +read_csr_as_usize!({}, __read_{}); +write_csr_as_usize!({}, __write_{}); +", + self.description, + self.id, + self.canonical_name(), + self.id, + self.canonical_name() + ) + } else { + format!( + " +//! {} + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct {}{{\n bits: usize,\n}} +impl {}{{ + #[inline] + pub fn bits(&self) -> usize{{ + return self.bits; + }} + #[inline] + pub fn from_bits(x: usize) -> Self{{ + return {}{{bits: x}}; + }} + #[inline] + pub unsafe fn write(&self){{ + _write(self.bits); + }} +{} +}} +read_csr_as!({}, {}, __read_{}); +write_csr!({}, __write_{}); +set!({}, __set_{}); +clear!({}, __clear_{}); +// bit ops +{} +// enums +{} + +", + self.description, + self.name, + self.name, + self.name, + trait_impls, + self.name, + self.id, + self.canonical_name(), + self.id, + self.canonical_name(), + self.id, + self.canonical_name(), + self.id, + self.canonical_name(), + bit_sets, + enums, + ) + } + } +} + +fn main() { + use std::io::Read; + let mut buffer = String::new(); + std::io::stdin().read_to_string(&mut buffer).unwrap(); + let csr = CSRDescriptor::parse(&buffer); + println!("{}", csr.generate()); +} diff --git a/third-party/riscv/descriptor/hcounteren.txt b/third-party/riscv/descriptor/hcounteren.txt new file mode 100644 index 00000000..2df37ba4 --- /dev/null +++ b/third-party/riscv/descriptor/hcounteren.txt @@ -0,0 +1,36 @@ +Hcounteren +3602 +cy,0,0,number, +tm,1,1,number, +ir,2,2,number, +hpm3,3,3,number, +hpm4,4,4,number, +hpm5,5,5,number, +hpm6,6,6,number, +hpm7,7,7,number, +hpm8,8,8,number, +hpm9,9,9,number, +hpm10,10,10,number, +hpm11,11,11,number, +hpm12,12,12,number, +hpm13,13,13,number, +hpm14,14,14,number, +hpm15,15,15,number, +hpm16,16,16,number, +hpm17,17,17,number, +hpm18,18,18,number, +hpm19,19,19,number, +hpm20,20,20,number, +hpm21,21,21,number, +hpm22,22,22,number, +hpm23,23,23,number, +hpm24,24,24,number, +hpm25,25,25,number, +hpm26,26,26,number, +hpm27,27,27,number, +hpm28,28,28,number, +hpm29,29,29,number, +hpm30,30,30,number, +hpm31,31,31,number, +end +Hypervisor Guest External Interrupt Pending Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hedeleg.txt b/third-party/riscv/descriptor/hedeleg.txt new file mode 100644 index 00000000..988f5f9c --- /dev/null +++ b/third-party/riscv/descriptor/hedeleg.txt @@ -0,0 +1,16 @@ +Hedeleg +1538 +ex0,0,0,number,Instruction address misaligned +ex1,1,1,number,Instruction access fault +ex2,2,2,number,Illegal instruction +ex3,3,3,number,Breakpoint +ex4,4,4,number,Load address misaligned +ex5,5,5,number,Load access fault +ex6,6,6,number,Store/AMO address misaligned +ex7,7,7,number,Store/AMO access fault +ex8,8,8,number,Environment call from U-mode or VU-mode +ex12,12,12,number,Instruction page fault +ex13,13,13,number,Load page fault +ex15,15,15,number,Store/AMO page fault +end +Hypervisor Exception Delegation Register. diff --git a/third-party/riscv/descriptor/hgatp.txt b/third-party/riscv/descriptor/hgatp.txt new file mode 100644 index 00000000..3763903d --- /dev/null +++ b/third-party/riscv/descriptor/hgatp.txt @@ -0,0 +1,7 @@ +Hgatp +1664 +mode,63,60,HgatpValues,Bare=0;Sv39x4=8;Sv48x4=9,Guest address translation mode. +vmid,57,44,number,Virtual machine ID. +ppn,43,0,number,Physical Page Number for root page table. +end +Hypervisor Guest Address Translation and Protection Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hgeie.txt b/third-party/riscv/descriptor/hgeie.txt new file mode 100644 index 00000000..c5af3c04 --- /dev/null +++ b/third-party/riscv/descriptor/hgeie.txt @@ -0,0 +1,4 @@ +Hgeie +1543 +end +Hypervisor Guest External Interrupt Enable Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hgeip.txt b/third-party/riscv/descriptor/hgeip.txt new file mode 100644 index 00000000..3b354d28 --- /dev/null +++ b/third-party/riscv/descriptor/hgeip.txt @@ -0,0 +1,4 @@ +Hgeip +3602 +end +Hypervisor Guest External Interrupt Pending Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hideleg.txt b/third-party/riscv/descriptor/hideleg.txt new file mode 100644 index 00000000..ea8f5ea5 --- /dev/null +++ b/third-party/riscv/descriptor/hideleg.txt @@ -0,0 +1,7 @@ +Hideleg +1539 +sip,2,2,number,Software Interrupt +tip,6,6,number,Timer Interrupt +eip,10,10,number,External Interrupt +end +Hypervisor Interrupt Delegation Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hie.txt b/third-party/riscv/descriptor/hie.txt new file mode 100644 index 00000000..f67ffc6a --- /dev/null +++ b/third-party/riscv/descriptor/hie.txt @@ -0,0 +1,8 @@ +Hie +1540 +vssie,2,2,number,Software Interrupt +vstie,6,6,number,Timer Interrupt +vseie,10,10,number,External Interrupt +sgeie,12,12,number,Guest External Interrupt +end +Hypervisor Interrupt Enable Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hip.txt b/third-party/riscv/descriptor/hip.txt new file mode 100644 index 00000000..e067ef14 --- /dev/null +++ b/third-party/riscv/descriptor/hip.txt @@ -0,0 +1,8 @@ +Hip +1604 +vssip,2,2,number,Software Interrupt +vstip,6,6,number,Timer Interrupt +vseip,10,10,number,External Interrupt +sgeip,12,12,number,Guest External Interrupt +end +Hypervisor Interrupt Pending Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hstatus.txt b/third-party/riscv/descriptor/hstatus.txt new file mode 100644 index 00000000..11ee9855 --- /dev/null +++ b/third-party/riscv/descriptor/hstatus.txt @@ -0,0 +1,14 @@ +Hstatus +1536 +vsxl,33,32,VsxlValues,Vsxl32=1;Vsxl64;Vsxl128,Effective XLEN for VM. +vtsr,22,22,number,TSR for VM. +vtw,21,21,number,TW for VM. +vtvm,20,20,number,TVM for VM. +vgein,17,12,number,Virtual Guest External Interrupt Number. +hu,9,9,number,Hypervisor User mode. +spvp,8,8,number,Supervisor Previous Virtual Privilege. +spv,7,7,number,Supervisor Previous Virtualization mode. +gva,6,6,number,Guest Virtual Address. +vsbe,5,5,number,VS access endianness. +end +HStatus Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/htimedelta.txt b/third-party/riscv/descriptor/htimedelta.txt new file mode 100644 index 00000000..d850625f --- /dev/null +++ b/third-party/riscv/descriptor/htimedelta.txt @@ -0,0 +1,5 @@ +Htimedelta +1541 +end +Hypervisor Time Delta Register. +read_composite_csr!(super::htimedeltah::read(), read()); \ No newline at end of file diff --git a/third-party/riscv/descriptor/htimedeltah.txt b/third-party/riscv/descriptor/htimedeltah.txt new file mode 100644 index 00000000..1b6147f6 --- /dev/null +++ b/third-party/riscv/descriptor/htimedeltah.txt @@ -0,0 +1,4 @@ +Htimedeltah +1557 +end +Hypervisor Time Delta Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/htinst.txt b/third-party/riscv/descriptor/htinst.txt new file mode 100644 index 00000000..b3efc33b --- /dev/null +++ b/third-party/riscv/descriptor/htinst.txt @@ -0,0 +1,4 @@ +Htinst +1610 +end +Hypervisor Trap Instruction Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/htval.txt b/third-party/riscv/descriptor/htval.txt new file mode 100644 index 00000000..eec176f0 --- /dev/null +++ b/third-party/riscv/descriptor/htval.txt @@ -0,0 +1,4 @@ +Htval +1603 +end +Hypervisor Trap Value Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/hvip.txt b/third-party/riscv/descriptor/hvip.txt new file mode 100644 index 00000000..5f8dfbea --- /dev/null +++ b/third-party/riscv/descriptor/hvip.txt @@ -0,0 +1,7 @@ +Hvip +1605 +vssip,2,2,number,Software Interrupt +vstip,6,6,number,Timer Interrupt +vseip,10,10,number,External Interrupt +end +Hypervisor Virtual Interrupt Pending Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vsatp.txt b/third-party/riscv/descriptor/vsatp.txt new file mode 100644 index 00000000..789ecfb8 --- /dev/null +++ b/third-party/riscv/descriptor/vsatp.txt @@ -0,0 +1,7 @@ +Vsatp +640 +mode,63,60,HgatpValues,Bare=0;Sv39x4=8;Sv48x4=9,Guest address translation mode. +asid,59,44,number,ASID. +ppn,43,0,number,Physical Page Number for root page table. +end +Virtual Supervisor Guest Address Translation and Protection Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vscause.txt b/third-party/riscv/descriptor/vscause.txt new file mode 100644 index 00000000..fabf4b4c --- /dev/null +++ b/third-party/riscv/descriptor/vscause.txt @@ -0,0 +1,6 @@ +Vscause +578 +interrupt,63,63,number,Is cause interrupt. +code,62,0,number,Exception code +end +Virtual Supervisor Cause Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vsepc.txt b/third-party/riscv/descriptor/vsepc.txt new file mode 100644 index 00000000..c1db586c --- /dev/null +++ b/third-party/riscv/descriptor/vsepc.txt @@ -0,0 +1,4 @@ +Vsepc +577 +end +Virtual Supervisor Exception Program Counter. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vsie.txt b/third-party/riscv/descriptor/vsie.txt new file mode 100644 index 00000000..b3dfaae2 --- /dev/null +++ b/third-party/riscv/descriptor/vsie.txt @@ -0,0 +1,7 @@ +Vsie +516 +ssie,1,1,number,Software Interrupt +stie,5,5,number,Timer Interrupt +seie,9,9,number,External Interrupt +end +Virtual Supevisor Interrupt Enable Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vsip.txt b/third-party/riscv/descriptor/vsip.txt new file mode 100644 index 00000000..14d7245f --- /dev/null +++ b/third-party/riscv/descriptor/vsip.txt @@ -0,0 +1,7 @@ +Vsip +580 +ssip,1,1,number,Software Interrupt +stip,5,5,number,Timer Interrupt +seip,9,9,number,External Interrupt +end +Virtual Supevisor Interrupt Pending Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vsscratch.txt b/third-party/riscv/descriptor/vsscratch.txt new file mode 100644 index 00000000..9f1f5aec --- /dev/null +++ b/third-party/riscv/descriptor/vsscratch.txt @@ -0,0 +1,4 @@ +Vsscratch +576 +end +Virtual Supervisor Scratch Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vsstatus.txt b/third-party/riscv/descriptor/vsstatus.txt new file mode 100644 index 00000000..02577f15 --- /dev/null +++ b/third-party/riscv/descriptor/vsstatus.txt @@ -0,0 +1,14 @@ +Vsstatus +512 +sd,63,60,number, +uxl,33,32,UxlValues,Uxl32=1;Uxl64;Uxl128,Effective User XLEN. +mxr,19,19,number, +sum,18,18,number, +xs,16,15,number, +fs,14,13,number, +spp,8,8,number, +ube,6,6,number, +spie,5,5,number, +sie,1,1,number, +end +Hypervisor Guest External Interrupt Pending Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vstval.txt b/third-party/riscv/descriptor/vstval.txt new file mode 100644 index 00000000..c3a9e461 --- /dev/null +++ b/third-party/riscv/descriptor/vstval.txt @@ -0,0 +1,4 @@ +Vstval +579 +end +Virtual Supervisor Trap Value Register. \ No newline at end of file diff --git a/third-party/riscv/descriptor/vstvec.txt b/third-party/riscv/descriptor/vstvec.txt new file mode 100644 index 00000000..c2c4a578 --- /dev/null +++ b/third-party/riscv/descriptor/vstvec.txt @@ -0,0 +1,6 @@ +Vstvec +517 +base,63,2,number, +mode,1,0,number, +end +Virtual Supervisor Trap Vector Base Address Register. \ No newline at end of file diff --git a/third-party/riscv/src/addr/gpax4.rs b/third-party/riscv/src/addr/gpax4.rs new file mode 100644 index 00000000..c7bc7344 --- /dev/null +++ b/third-party/riscv/src/addr/gpax4.rs @@ -0,0 +1,211 @@ +use super::*; +use bit_field::BitField; +use core::convert::TryInto; + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct GPAddrSv32X4(u64); + +impl Address for GPAddrSv32X4 { + fn new(addr: usize) -> Self { + Self::new_u64(addr as u64) + } + fn as_usize(&self) -> usize { + self.0 as usize + } + fn page_number(&self) -> usize { + self.0.get_bits(12..34) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + GPAddrSv32X4((self.0 >> 12) << 12) + } +} + +impl VirtualAddress for GPAddrSv32X4 { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T { + &mut *(self.0 as *mut T) + } +} + +impl AddressL2 for GPAddrSv32X4 { + fn p2_index(&self) -> usize { + self.0.get_bits(22..34) as usize + } + fn p1_index(&self) -> usize { + self.0.get_bits(12..22) as usize + } + fn from_page_table_indices(p2_index: usize, p1_index: usize, offset: usize) -> Self { + let p2_index = p2_index as u64; + let p1_index = p1_index as u64; + let offset = offset as u64; + assert!(p2_index.get_bits(12..) == 0, "p2_index exceeding 12 bits"); + assert!(p1_index.get_bits(10..) == 0, "p1_index exceeding 10 bits"); + assert!(offset.get_bits(12..) == 0, "offset exceeding 12 bits"); + GPAddrSv32X4::new_u64((p2_index << 22) | (p1_index << 12) | offset) + } +} + +impl AddressX64 for GPAddrSv32X4 { + fn new_u64(addr: u64) -> Self { + assert!( + addr.get_bits(34..64) == 0, + "Sv32x4 does not allow pa 34..64!=0" + ); + GPAddrSv32X4(addr) + } + fn as_u64(&self) -> u64 { + self.0 + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct GPAddrSv39X4(u64); + +impl Address for GPAddrSv39X4 { + fn new(addr: usize) -> Self { + GPAddrSv39X4(addr.try_into().unwrap()) + } + fn as_usize(&self) -> usize { + self.0 as usize + } + fn page_number(&self) -> usize { + self.0.get_bits(12..41) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + GPAddrSv39X4((self.0 >> 12) << 12) + } +} + +impl VirtualAddress for GPAddrSv39X4 { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T { + &mut *(self.0 as *mut T) + } +} + +impl AddressL3 for GPAddrSv39X4 { + fn p3_index(&self) -> usize { + self.0.get_bits(30..41) as usize + } + fn p2_index(&self) -> usize { + self.0.get_bits(21..30) as usize + } + fn p1_index(&self) -> usize { + self.0.get_bits(12..21) as usize + } + fn from_page_table_indices( + p3_index: usize, + p2_index: usize, + p1_index: usize, + offset: usize, + ) -> Self { + let p3_index = p3_index as u64; + let p2_index = p2_index as u64; + let p1_index = p1_index as u64; + let offset = offset as u64; + assert!(p3_index.get_bits(11..) == 0, "p3_index exceeding 11 bits"); + assert!(p2_index.get_bits(9..) == 0, "p2_index exceeding 9 bits"); + assert!(p1_index.get_bits(9..) == 0, "p1_index exceeding 9 bits"); + assert!(offset.get_bits(12..) == 0, "offset exceeding 12 bits"); + GPAddrSv39X4::new_u64( + (p3_index << 12 << 9 << 9) | (p2_index << 12 << 9) | (p1_index << 12) | offset, + ) + } +} + +impl AddressX64 for GPAddrSv39X4 { + fn new_u64(addr: u64) -> Self { + assert!( + addr.get_bits(41..64) == 0, + "Sv39x4 does not allow pa 41..64!=0" + ); + GPAddrSv39X4(addr) + } + fn as_u64(&self) -> u64 { + self.0 + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct GPAddrSv48X4(u64); + +impl Address for GPAddrSv48X4 { + fn new(addr: usize) -> Self { + GPAddrSv48X4(addr.try_into().unwrap()) + } + fn as_usize(&self) -> usize { + self.0 as usize + } + fn page_number(&self) -> usize { + self.0.get_bits(12..50) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + GPAddrSv48X4((self.0 >> 12) << 12) + } +} + +impl VirtualAddress for GPAddrSv48X4 { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T { + &mut *(self.0 as *mut T) + } +} + +impl AddressL4 for GPAddrSv48X4 { + fn p4_index(&self) -> usize { + self.0.get_bits(39..50) as usize + } + fn p3_index(&self) -> usize { + self.0.get_bits(30..39) as usize + } + fn p2_index(&self) -> usize { + self.0.get_bits(21..30) as usize + } + fn p1_index(&self) -> usize { + self.0.get_bits(12..21) as usize + } + fn from_page_table_indices( + p4_index: usize, + p3_index: usize, + p2_index: usize, + p1_index: usize, + offset: usize, + ) -> Self { + let p4_index = p4_index as u64; + let p3_index = p3_index as u64; + let p2_index = p2_index as u64; + let p1_index = p1_index as u64; + let offset = offset as u64; + assert!(p4_index.get_bits(11..) == 0, "p4_index exceeding 11 bits"); + assert!(p3_index.get_bits(9..) == 0, "p3_index exceeding 9 bits"); + assert!(p2_index.get_bits(9..) == 0, "p2_index exceeding 9 bits"); + assert!(p1_index.get_bits(9..) == 0, "p1_index exceeding 9 bits"); + assert!(offset.get_bits(12..) == 0, "offset exceeding 12 bits"); + GPAddrSv48X4::new_u64( + (p4_index << 12 << 9 << 9 << 9) + | (p3_index << 12 << 9 << 9) + | (p2_index << 12 << 9) + | (p1_index << 12) + | offset, + ) + } +} + +impl AddressX64 for GPAddrSv48X4 { + fn new_u64(addr: u64) -> Self { + assert!( + addr.get_bits(50..64) == 0, + "Sv48x4 does not allow pa 50..64!=0" + ); + GPAddrSv48X4(addr) + } + fn as_u64(&self) -> u64 { + self.0 + } +} diff --git a/third-party/riscv/src/addr/mod.rs b/third-party/riscv/src/addr/mod.rs new file mode 100644 index 00000000..9b33ce8a --- /dev/null +++ b/third-party/riscv/src/addr/mod.rs @@ -0,0 +1,98 @@ +pub trait Address: core::fmt::Debug + Copy + Clone + PartialEq + Eq + PartialOrd + Ord { + fn new(addr: usize) -> Self; + fn page_number(&self) -> usize; + fn page_offset(&self) -> usize; + fn to_4k_aligned(&self) -> Self; + fn as_usize(&self) -> usize; +} + +pub trait VirtualAddress: Address { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T; +} + +pub trait AddressX32: Address { + fn new_u32(addr: u32) -> Self; + fn as_u32(&self) -> u32; +} +pub trait AddressX64: Address { + fn new_u64(addr: u64) -> Self; + fn as_u64(&self) -> u64; +} + +pub trait PhysicalAddress: AddressX64 {} + +pub trait AddressL3: Address { + fn p3_index(&self) -> usize; + fn p2_index(&self) -> usize; + fn p1_index(&self) -> usize; + fn from_page_table_indices( + p3_index: usize, + p2_index: usize, + p1_index: usize, + offset: usize, + ) -> Self; +} + +pub trait AddressL4: Address { + fn p4_index(&self) -> usize; + fn p3_index(&self) -> usize; + fn p2_index(&self) -> usize; + fn p1_index(&self) -> usize; + fn from_page_table_indices( + p4_index: usize, + p3_index: usize, + p2_index: usize, + p1_index: usize, + offset: usize, + ) -> Self; +} + +pub trait AddressL2: Address { + fn p2_index(&self) -> usize; + fn p1_index(&self) -> usize; + fn from_page_table_indices(p2_index: usize, p1_index: usize, offset: usize) -> Self; +} +pub mod gpax4; +pub mod page; +pub mod sv32; +pub mod sv39; +pub mod sv48; + +pub use self::gpax4::*; +pub use self::page::*; +pub use self::sv32::*; +pub use self::sv39::*; +pub use self::sv48::*; + +#[macro_export] +macro_rules! use_sv32 { + () => { + pub type VirtAddr = VirtAddrSv32; + pub type PhysAddr = PhysAddrSv32; + pub type Page = PageWith; + pub type Frame = FrameWith; + }; +} +#[macro_export] +macro_rules! use_sv39 { + () => { + pub type VirtAddr = VirtAddrSv39; + pub type PhysAddr = PhysAddrSv39; + pub type Page = PageWith; + pub type Frame = FrameWith; + }; +} +#[macro_export] +macro_rules! use_sv48 { + () => { + pub type VirtAddr = VirtAddrSv48; + pub type PhysAddr = PhysAddrSv48; + pub type Page = PageWith; + pub type Frame = FrameWith; + }; +} +#[cfg(target_arch = "riscv64")] +use_sv48!(); + +#[cfg(target_arch = "riscv32")] +use_sv32!(); diff --git a/third-party/riscv/src/addr/page.rs b/third-party/riscv/src/addr/page.rs new file mode 100644 index 00000000..2c36f9b5 --- /dev/null +++ b/third-party/riscv/src/addr/page.rs @@ -0,0 +1,174 @@ +pub use super::*; +pub use bit_field::BitField; + +pub trait PageWithL4 { + fn p4_index(&self) -> usize; + fn p3_index(&self) -> usize; + fn p2_index(&self) -> usize; + fn p1_index(&self) -> usize; + fn from_page_table_indices( + p4_index: usize, + p3_index: usize, + p2_index: usize, + p1_index: usize, + ) -> Self; +} + +pub trait PageWithL3 { + fn p3_index(&self) -> usize; + fn p2_index(&self) -> usize; + fn p1_index(&self) -> usize; + fn from_page_table_indices(p3_index: usize, p2_index: usize, p1_index: usize) -> Self; +} + +pub trait PageWithL2 { + fn p2_index(&self) -> usize; + fn p1_index(&self) -> usize; + fn from_page_table_indices(p2_index: usize, p1_index: usize) -> Self; +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub struct PageWith(T); + +impl PageWithL4 for PageWith { + fn p4_index(&self) -> usize { + self.0.p4_index() + } + fn p3_index(&self) -> usize { + self.0.p3_index() + } + fn p2_index(&self) -> usize { + self.0.p2_index() + } + fn p1_index(&self) -> usize { + self.0.p1_index() + } + fn from_page_table_indices( + p4_index: usize, + p3_index: usize, + p2_index: usize, + p1_index: usize, + ) -> Self { + PageWith::of_addr(T::from_page_table_indices( + p4_index, p3_index, p2_index, p1_index, 0, + )) + } +} +impl PageWithL3 for PageWith { + fn p3_index(&self) -> usize { + self.0.p3_index() + } + fn p2_index(&self) -> usize { + self.0.p2_index() + } + fn p1_index(&self) -> usize { + self.0.p1_index() + } + fn from_page_table_indices(p3_index: usize, p2_index: usize, p1_index: usize) -> Self { + PageWith::of_addr(T::from_page_table_indices(p3_index, p2_index, p1_index, 0)) + } +} +impl PageWithL2 for PageWith { + fn p2_index(&self) -> usize { + self.0.p2_index() + } + fn p1_index(&self) -> usize { + self.0.p1_index() + } + fn from_page_table_indices(p2_index: usize, p1_index: usize) -> Self { + PageWith::of_addr(T::from_page_table_indices(p2_index, p1_index, 0)) + } +} +impl PageWith { + pub fn of_addr(addr: T) -> Self { + PageWith(addr.to_4k_aligned()) + } + + pub fn of_vpn(vpn: usize) -> Self { + PageWith(T::new(vpn << 12)) + } + + pub fn start_address(&self) -> T { + self.0.clone() + } + + pub fn number(&self) -> usize { + self.0.page_number() + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub struct FrameWith(T); + +impl PageWithL4 for FrameWith { + fn p4_index(&self) -> usize { + self.0.p4_index() + } + fn p3_index(&self) -> usize { + self.0.p3_index() + } + fn p2_index(&self) -> usize { + self.0.p2_index() + } + fn p1_index(&self) -> usize { + self.0.p1_index() + } + fn from_page_table_indices( + p4_index: usize, + p3_index: usize, + p2_index: usize, + p1_index: usize, + ) -> Self { + FrameWith::of_addr(T::from_page_table_indices( + p4_index, p3_index, p2_index, p1_index, 0, + )) + } +} +impl PageWithL3 for FrameWith { + fn p3_index(&self) -> usize { + self.0.p3_index() + } + fn p2_index(&self) -> usize { + self.0.p2_index() + } + fn p1_index(&self) -> usize { + self.0.p1_index() + } + fn from_page_table_indices(p3_index: usize, p2_index: usize, p1_index: usize) -> Self { + FrameWith::of_addr(T::from_page_table_indices(p3_index, p2_index, p1_index, 0)) + } +} +impl PageWithL2 for FrameWith { + fn p2_index(&self) -> usize { + self.0.p2_index() + } + fn p1_index(&self) -> usize { + self.0.p1_index() + } + fn from_page_table_indices(p2_index: usize, p1_index: usize) -> Self { + FrameWith::of_addr(T::from_page_table_indices(p2_index, p1_index, 0)) + } +} + +impl FrameWith { + pub fn of_addr(addr: T) -> Self { + FrameWith(addr.to_4k_aligned()) + } + + #[inline(always)] + pub fn of_ppn(ppn: usize) -> Self { + FrameWith(T::new_u64((ppn as u64) << 12)) + } + + pub fn start_address(&self) -> T { + self.0.clone() + } + + pub fn number(&self) -> usize { + self.0.page_number() + } + + pub unsafe fn as_kernel_mut<'a, 'b, U>(&'a self, linear_offset: u64) -> &'b mut U { + &mut *(((self.0).as_u64() + linear_offset) as *mut U) + } +} diff --git a/third-party/riscv/src/addr/sv32.rs b/third-party/riscv/src/addr/sv32.rs new file mode 100644 index 00000000..193b7f6d --- /dev/null +++ b/third-party/riscv/src/addr/sv32.rs @@ -0,0 +1,91 @@ +use super::*; +use bit_field::BitField; +use core::convert::TryInto; +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct VirtAddrSv32(u32); +impl Address for VirtAddrSv32 { + fn new(addr: usize) -> Self { + VirtAddrSv32(addr.try_into().unwrap()) + } + fn as_usize(&self) -> usize { + self.0 as usize + } + fn page_number(&self) -> usize { + self.0.get_bits(12..32) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + VirtAddrSv32((self.0 >> 12) << 12) + } +} +impl VirtualAddress for VirtAddrSv32 { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T { + &mut *(self.0 as *mut T) + } +} + +impl AddressL2 for VirtAddrSv32 { + fn p2_index(&self) -> usize { + self.0.get_bits(22..32) as usize + } + + fn p1_index(&self) -> usize { + self.0.get_bits(12..22) as usize + } + fn from_page_table_indices(p2_index: usize, p1_index: usize, offset: usize) -> Self { + assert!(p2_index.get_bits(10..) == 0, "p2_index exceeding 10 bits"); + assert!(p1_index.get_bits(10..) == 0, "p1_index exceeding 10 bits"); + assert!(offset.get_bits(12..) == 0, "offset exceeding 12 bits"); + VirtAddrSv32::new((p2_index << 22) | (p1_index << 12) | offset) + } +} + +impl AddressX32 for VirtAddrSv32 { + fn new_u32(addr: u32) -> Self { + VirtAddrSv32(addr) + } + fn as_u32(&self) -> u32 { + self.0 + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub struct PhysAddrSv32(u64); +impl Address for PhysAddrSv32 { + fn new(addr: usize) -> Self { + Self::new_u64(addr as u64) + } + fn as_usize(&self) -> usize { + assert!( + self.0.get_bits(32..34) == 0, + "Downcasting an Sv32 pa >4GB (32..34!=0) will cause address loss." + ); + self.0 as usize + } + fn page_number(&self) -> usize { + self.0.get_bits(12..34) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + PhysAddrSv32((self.0 >> 12) << 12) + } +} + +impl AddressX64 for PhysAddrSv32 { + fn new_u64(addr: u64) -> Self { + assert!( + addr.get_bits(34..64) == 0, + "Sv32 does not allow pa 34..64!=0" + ); + PhysAddrSv32(addr) + } + fn as_u64(&self) -> u64 { + self.0 + } +} + +impl PhysicalAddress for PhysAddrSv32 {} diff --git a/third-party/riscv/src/addr/sv39.rs b/third-party/riscv/src/addr/sv39.rs new file mode 100644 index 00000000..b059192d --- /dev/null +++ b/third-party/riscv/src/addr/sv39.rs @@ -0,0 +1,115 @@ +use super::*; +use bit_field::BitField; +use core::convert::TryInto; +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct VirtAddrSv39(u64); + +impl VirtualAddress for VirtAddrSv39 { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T { + &mut *(self.0 as *mut T) + } +} +impl Address for VirtAddrSv39 { + fn new(addr: usize) -> Self { + Self::new_u64(addr as u64) + } + fn as_usize(&self) -> usize { + self.0.try_into().unwrap() + } + fn page_number(&self) -> usize { + self.0.get_bits(12..39).try_into().unwrap() + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + VirtAddrSv39((self.0 >> 12) << 12) + } +} + +impl AddressL3 for VirtAddrSv39 { + fn p3_index(&self) -> usize { + self.0.get_bits(30..39) as usize + } + + fn p2_index(&self) -> usize { + self.0.get_bits(21..30) as usize + } + fn p1_index(&self) -> usize { + self.0.get_bits(12..21) as usize + } + fn from_page_table_indices( + p3_index: usize, + p2_index: usize, + p1_index: usize, + offset: usize, + ) -> Self { + let p3_index = p3_index as u64; + let p2_index = p2_index as u64; + let p1_index = p1_index as u64; + let offset = offset as u64; + assert!(p3_index.get_bits(11..) == 0, "p3_index exceeding 11 bits"); + assert!(p2_index.get_bits(9..) == 0, "p2_index exceeding 9 bits"); + assert!(p1_index.get_bits(9..) == 0, "p1_index exceeding 9 bits"); + assert!(offset.get_bits(12..) == 0, "offset exceeding 12 bits"); + let mut addr = + (p3_index << 12 << 9 << 9) | (p2_index << 12 << 9) | (p1_index << 12) | offset; + if addr.get_bit(38) { + addr.set_bits(39..64, (1 << (64 - 39)) - 1); + } else { + addr.set_bits(39..64, 0x0000); + } + VirtAddrSv39::new_u64(addr) + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub struct PhysAddrSv39(u64); +impl Address for PhysAddrSv39 { + fn new(addr: usize) -> Self { + Self::new_u64(addr as u64) + } + fn as_usize(&self) -> usize { + self.0.try_into().unwrap() + } + fn page_number(&self) -> usize { + self.0.get_bits(12..56) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + PhysAddrSv39((self.0 >> 12) << 12) + } +} + +impl AddressX64 for VirtAddrSv39 { + fn new_u64(addr: u64) -> Self { + if addr.get_bit(38) { + assert!( + addr.get_bits(39..64) == (1 << (64 - 39)) - 1, + "va 39..64 is not sext" + ); + } else { + assert!(addr.get_bits(39..64) == 0x0000, "va 39..64 is not sext"); + } + VirtAddrSv39(addr as u64) + } + fn as_u64(&self) -> u64 { + self.0 + } +} +impl AddressX64 for PhysAddrSv39 { + fn new_u64(addr: u64) -> Self { + assert!( + addr.get_bits(56..64) == 0, + "Sv39 does not allow pa 56..64!=0" + ); + PhysAddrSv39(addr) + } + fn as_u64(&self) -> u64 { + self.0 + } +} + +impl PhysicalAddress for PhysAddrSv39 {} diff --git a/third-party/riscv/src/addr/sv48.rs b/third-party/riscv/src/addr/sv48.rs new file mode 100644 index 00000000..880bd3e9 --- /dev/null +++ b/third-party/riscv/src/addr/sv48.rs @@ -0,0 +1,125 @@ +use super::*; +use bit_field::BitField; +use core::convert::TryInto; +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct VirtAddrSv48(u64); + +impl VirtualAddress for VirtAddrSv48 { + unsafe fn as_mut<'a, 'b, T>(&'a self) -> &'b mut T { + &mut *(self.0 as *mut T) + } +} +impl Address for VirtAddrSv48 { + fn new(addr: usize) -> Self { + Self::new_u64(addr as u64) + } + fn as_usize(&self) -> usize { + self.0.try_into().unwrap() + } + fn page_number(&self) -> usize { + self.0.get_bits(12..48).try_into().unwrap() + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + VirtAddrSv48((self.0 >> 12) << 12) + } +} + +impl AddressL4 for VirtAddrSv48 { + fn p4_index(&self) -> usize { + self.0.get_bits(39..48) as usize + } + + fn p3_index(&self) -> usize { + self.0.get_bits(30..39) as usize + } + + fn p2_index(&self) -> usize { + self.0.get_bits(21..30) as usize + } + fn p1_index(&self) -> usize { + self.0.get_bits(12..21) as usize + } + fn from_page_table_indices( + p4_index: usize, + p3_index: usize, + p2_index: usize, + p1_index: usize, + offset: usize, + ) -> Self { + let p4_index = p4_index as u64; + let p3_index = p3_index as u64; + let p2_index = p2_index as u64; + let p1_index = p1_index as u64; + let offset = offset as u64; + assert!(p4_index.get_bits(9..) == 0, "p4_index exceeding 9 bits"); + assert!(p3_index.get_bits(9..) == 0, "p3_index exceeding 9 bits"); + assert!(p2_index.get_bits(9..) == 0, "p2_index exceeding 9 bits"); + assert!(p1_index.get_bits(9..) == 0, "p1_index exceeding 9 bits"); + assert!(offset.get_bits(12..) == 0, "offset exceeding 12 bits"); + let mut addr = (p4_index << 12 << 9 << 9 << 9) + | (p3_index << 12 << 9 << 9) + | (p2_index << 12 << 9) + | (p1_index << 12) + | offset; + if addr.get_bit(47) { + addr.set_bits(48..64, (1 << (64 - 48)) - 1); + } else { + addr.set_bits(48..64, 0x0000); + } + VirtAddrSv48::new_u64(addr) + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub struct PhysAddrSv48(u64); +impl Address for PhysAddrSv48 { + fn new(addr: usize) -> Self { + Self::new_u64(addr as u64) + } + fn as_usize(&self) -> usize { + self.0.try_into().unwrap() + } + fn page_number(&self) -> usize { + self.0.get_bits(12..56) as usize + } + fn page_offset(&self) -> usize { + self.0.get_bits(0..12) as usize + } + fn to_4k_aligned(&self) -> Self { + PhysAddrSv48((self.0 >> 12) << 12) + } +} + +impl AddressX64 for VirtAddrSv48 { + fn new_u64(addr: u64) -> Self { + if addr.get_bit(47) { + assert!( + addr.get_bits(48..64) == (1 << (64 - 48)) - 1, + "va 48..64 is not sext" + ); + } else { + assert!(addr.get_bits(48..64) == 0x0000, "va 48..64 is not sext"); + } + VirtAddrSv48(addr as u64) + } + fn as_u64(&self) -> u64 { + self.0 + } +} +impl AddressX64 for PhysAddrSv48 { + fn new_u64(addr: u64) -> Self { + assert!( + addr.get_bits(56..64) == 0, + "Sv48 does not allow pa 56..64!=0" + ); + PhysAddrSv48(addr) + } + fn as_u64(&self) -> u64 { + self.0 + } +} + +impl PhysicalAddress for PhysAddrSv48 {} diff --git a/third-party/riscv/src/asm.rs b/third-party/riscv/src/asm.rs new file mode 100644 index 00000000..ca007d99 --- /dev/null +++ b/third-party/riscv/src/asm.rs @@ -0,0 +1,152 @@ +//! Assembly instructions + +macro_rules! instruction { + ($(#[$attr:meta])*, $fnname:ident, $asm:expr, $asm_fn:ident) => ( + $(#[$attr])* + #[inline] + pub unsafe fn $fnname() { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => core::arch::asm!($asm), + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(); + } + + $asm_fn(); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + ) +} + +instruction!( + /// `EBREAK` instruction wrapper + /// + /// Generates a breakpoint exception. + , ebreak, "ebreak", __ebreak); +instruction!( + /// `WFI` instruction wrapper + /// + /// Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing. + /// The WFI instruction is just a hint, and a legal implementation is to implement WFI as a NOP. + , wfi, "wfi", __wfi); +instruction!( + /// `SFENCE.VMA` instruction wrapper (all address spaces and page table levels) + /// + /// Synchronizes updates to in-memory memory-management data structures with current execution. + /// Instruction execution causes implicit reads and writes to these data structures; however, these implicit references + /// are ordinarily not ordered with respect to loads and stores in the instruction stream. + /// Executing an `SFENCE.VMA` instruction guarantees that any stores in the instruction stream prior to the + /// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`. + , sfence_vma_all, "sfence.vma", __sfence_vma_all); + +/// `SFENCE.VMA` instruction wrapper +/// +/// Synchronizes updates to in-memory memory-management data structures with current execution. +/// Instruction execution causes implicit reads and writes to these data structures; however, these implicit references +/// are ordinarily not ordered with respect to loads and stores in the instruction stream. +/// Executing an `SFENCE.VMA` instruction guarantees that any stores in the instruction stream prior to the +/// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`. +#[inline] +#[allow(unused_variables)] +pub unsafe fn sfence_vma(asid: usize, addr: usize) { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => core::arch::asm!("sfence.vma {0}, {1}", in(reg) addr, in(reg) asid), + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn __sfence_vma(asid: usize, addr: usize); + } + + __sfence_vma(asid, addr); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } +} + +mod hypervisor_extension { + // Generating instructions for Hypervisor extension. + // There are two kinds of instructions: rs1/rs2 type and rs1/rd type. + // Also special register handling is required before LLVM could generate inline assembly for extended instructions. + macro_rules! instruction_hypervisor_extension { + (RS1_RS2, $(#[$attr:meta])*, $fnname:ident, $asm:expr, $asm_fn:ident) => ( + $(#[$attr])* + #[inline] + #[allow(unused_variables)] + pub unsafe fn $fnname(rs1: usize, rs2: usize) { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + // Since LLVM does not recognize the two registers, we assume they are placed in a0 and a1, correspondingly. + () => core::arch::asm!($asm, in("x10") rs1, in("x11") rs2), + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(rs1: usize, rs2: usize); + } + + $asm_fn(rs1, rs2); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + ); + (RS1_RD, $(#[$attr:meta])*, $fnname:ident, $asm:expr, $asm_fn:ident) => ( + $(#[$attr])* + #[inline] + #[allow(unused_variables)] + pub unsafe fn $fnname(rs1: usize)->usize { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => { + let mut result : usize; + core::arch::asm!($asm, inlateout("x10") rs1 => result); + return result; + } + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(rs1: usize)->usize; + } + + return $asm_fn(rs1); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + ) + } + + instruction_hypervisor_extension!(RS1_RS2,,hfence_gvma,".word 1656029299",__hfence_gvma); + instruction_hypervisor_extension!(RS1_RS2,,hfence_vvma,".word 582287475",__hfence_vvma); + instruction_hypervisor_extension!(RS1_RD,,hlv_b,".word 1610958195",__hlv_b); + instruction_hypervisor_extension!(RS1_RD,,hlv_bu,".word 1612006771",__hlv_bu); + instruction_hypervisor_extension!(RS1_RD,,hlv_h,".word 1678067059",__hlv_h); + instruction_hypervisor_extension!(RS1_RD,,hlv_hu,".word 1679115635",__hlv_hu); + instruction_hypervisor_extension!(RS1_RD,,hlvx_hu,".word 1681212787",__hlvx_hu); + instruction_hypervisor_extension!(RS1_RD,,hlv_w,".word 1745175923",__hlv_w); + instruction_hypervisor_extension!(RS1_RD,,hlvx_wu,".word 1748321651",__hlvx_wu); + instruction_hypervisor_extension!(RS1_RS2,,hsv_b,".word 1656045683",__hsv_b); + instruction_hypervisor_extension!(RS1_RS2,,hsv_h,".word 1723154547",__hsv_h); + instruction_hypervisor_extension!(RS1_RS2,,hsv_w,".word 1790263411",__hsv_w); + instruction_hypervisor_extension!(RS1_RD,,hlv_wu,".word 1746224499",__hlv_wu); + instruction_hypervisor_extension!(RS1_RD,,hlv_d,".word 1812284787",__hlv_d); + instruction_hypervisor_extension!(RS1_RS2,,hsv_d,".word 1857372275",__hsv_d); +} + +pub use self::hypervisor_extension::*; diff --git a/third-party/riscv/src/interrupt.rs b/third-party/riscv/src/interrupt.rs new file mode 100644 index 00000000..9b8598d8 --- /dev/null +++ b/third-party/riscv/src/interrupt.rs @@ -0,0 +1,58 @@ +//! Interrupts + +// NOTE: Adapted from cortex-m/src/interrupt.rs +pub use bare_metal::{CriticalSection, Mutex, Nr}; +use register::mstatus; + +/// Disables all interrupts +#[inline] +pub unsafe fn disable() { + match () { + #[cfg(riscv)] + () => mstatus::clear_mie(), + #[cfg(not(riscv))] + () => unimplemented!(), + } +} + +/// Enables all the interrupts +/// +/// # Safety +/// +/// - Do not call this function inside an `interrupt::free` critical section +#[inline] +pub unsafe fn enable() { + match () { + #[cfg(riscv)] + () => mstatus::set_mie(), + #[cfg(not(riscv))] + () => unimplemented!(), + } +} + +/// Execute closure `f` in an interrupt-free context. +/// +/// This as also known as a "critical section". +pub fn free(f: F) -> R +where + F: FnOnce(&CriticalSection) -> R, +{ + let mstatus = mstatus::read(); + + // disable interrupts + unsafe { + disable(); + } + + let r = f(unsafe { &CriticalSection::new() }); + + // If the interrupts were active before our `disable` call, then re-enable + // them. Otherwise, keep them disabled + if mstatus.mie() { + unsafe { + enable(); + } + } + + r +} diff --git a/third-party/riscv/src/lib.rs b/third-party/riscv/src/lib.rs new file mode 100644 index 00000000..27b53287 --- /dev/null +++ b/third-party/riscv/src/lib.rs @@ -0,0 +1,28 @@ +//! Low level access to RISC-V processors +//! +//! # Minimum Supported Rust Version (MSRV) +//! +//! This crate is guaranteed to compile on stable Rust 1.42 and up. It *might* +//! compile with older versions but that may change in any new patch release. +//! +//! # Features +//! +//! This crate provides: +//! +//! - Access to core registers like `mstatus` or `mcause`. +//! - Interrupt manipulation mechanisms. +//! - Wrappers around assembly instructions like `WFI`. + + +#![no_std] +#![cfg_attr(feature = "inline-asm", feature(asm_const))] +extern crate bare_metal; +#[macro_use] +extern crate bitflags; +extern crate bit_field; + +pub mod addr; +pub mod asm; +pub mod interrupt; +pub mod paging; +pub mod register; diff --git a/third-party/riscv/src/paging/frame_alloc.rs b/third-party/riscv/src/paging/frame_alloc.rs new file mode 100644 index 00000000..89b4ada6 --- /dev/null +++ b/third-party/riscv/src/paging/frame_alloc.rs @@ -0,0 +1,40 @@ +//! Traits for abstracting away frame allocation and deallocation. + +use addr::*; +/// A trait for types that can allocate a frame of memory. +pub trait FrameAllocatorFor { + /// Allocate a frame of the appropriate size and return it if possible. + fn alloc(&mut self) -> Option>; +} + +/// A trait for types that can deallocate a frame of memory. +pub trait FrameDeallocatorFor { + /// Deallocate the given frame of memory. + fn dealloc(&mut self, frame: FrameWith

); +} + +/// Polyfill for default use cases. + +#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] +pub trait FrameAllocator { + fn alloc(&mut self) -> Option; +} +#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] +pub trait FrameDeallocator { + fn dealloc(&mut self, frame: Frame); +} + +#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] +impl FrameAllocatorFor for T { + #[inline] + fn alloc(&mut self) -> Option { + FrameAllocator::alloc(self) + } +} +#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] +impl FrameDeallocatorFor for T { + #[inline] + fn dealloc(&mut self, frame: Frame) { + FrameDeallocator::dealloc(self, frame) + } +} diff --git a/third-party/riscv/src/paging/mapper.rs b/third-party/riscv/src/paging/mapper.rs new file mode 100644 index 00000000..6e477303 --- /dev/null +++ b/third-party/riscv/src/paging/mapper.rs @@ -0,0 +1,136 @@ +use super::frame_alloc::*; +use super::page_table::*; +use addr::*; + +pub trait Mapper { + type P: PhysicalAddress; + type V: VirtualAddress; + type MapperFlush: MapperFlushable; + type Entry: PTE; + + /// Creates a new mapping in the page table. + /// + /// This function might need additional physical frames to create new page tables. These + /// frames are allocated from the `allocator` argument. At most three frames are required. + fn map_to( + &mut self, + page: PageWith, + frame: FrameWith, + flags: PageTableFlags, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result; + + /// Removes a mapping from the page table and returns the frame that used to be mapped. + /// + /// Note that no page tables or pages are deallocated. + fn unmap( + &mut self, + page: PageWith, + ) -> Result<(FrameWith, Self::MapperFlush), UnmapError<::P>>; + + /// Get the reference of the specified `page` entry + fn ref_entry(&mut self, page: PageWith) -> Result<&mut Self::Entry, FlagUpdateError>; + + /// Updates the flags of an existing mapping. + fn update_flags( + &mut self, + page: PageWith, + flags: PageTableFlags, + ) -> Result { + self.ref_entry(page).map(|e| { + e.set(e.frame::(), flags); + Self::MapperFlush::new(page) + }) + } + + /// Return the frame that the specified page is mapped to. + fn translate_page(&mut self, page: PageWith) -> Option> { + match self.ref_entry(page) { + Ok(e) => { + if e.is_unused() { + None + } else { + Some(e.frame()) + } + } + Err(_) => None, + } + } + + /// Maps the given frame to the virtual page with the same address. + fn identity_map( + &mut self, + frame: FrameWith, + flags: PageTableFlags, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result { + let page = PageWith::of_addr(Self::V::new(frame.start_address().as_usize())); + self.map_to(page, frame, flags, allocator) + } +} + +pub trait MapperFlushable { + /// Create a new flush promise + fn new(page: PageWith) -> Self; + /// Flush the page from the TLB to ensure that the newest mapping is used. + fn flush(self); + /// Don't flush the TLB and silence the “must be used” warning. + fn ignore(self); +} + +#[must_use = "Page Table changes must be flushed or ignored."] +pub struct MapperFlush(usize); + +impl MapperFlushable for MapperFlush { + fn new(page: PageWith) -> Self { + MapperFlush(page.start_address().as_usize()) + } + fn flush(self) { + unsafe { + crate::asm::sfence_vma(0, self.0); + } + } + fn ignore(self) {} +} + +/// This error is returned from `map_to` and similar methods. +#[derive(Debug)] +pub enum MapToError { + /// An additional frame was needed for the mapping process, but the frame allocator + /// returned `None`. + FrameAllocationFailed, + /// An upper level page table entry has the `HUGE_PAGE` flag set, which means that the + /// given page is part of an already mapped huge page. + ParentEntryHugePage, + /// The given page is already mapped to a physical frame. + PageAlreadyMapped, +} + +/// An error indicating that an `unmap` call failed. +#[derive(Debug)] +pub enum UnmapError { + /// An upper level page table entry has the `HUGE_PAGE` flag set, which means that the + /// given page is part of a huge page and can't be freed individually. + ParentEntryHugePage, + /// The given page is not mapped to a physical frame. + PageNotMapped, + /// The page table entry for the given page points to an invalid physical address. + InvalidFrameAddress(P), +} + +/// An error indicating that an `update_flags` call failed. +#[derive(Debug)] +pub enum FlagUpdateError { + /// The given page is not mapped to a physical frame. + PageNotMapped, +} + +pub trait MapperExt { + type Page; + type Frame; +} + +impl MapperExt for T { + type Page = PageWith<::V>; + type Frame = FrameWith<::P>; +} diff --git a/third-party/riscv/src/paging/mod.rs b/third-party/riscv/src/paging/mod.rs new file mode 100644 index 00000000..7df9b062 --- /dev/null +++ b/third-party/riscv/src/paging/mod.rs @@ -0,0 +1,13 @@ +mod frame_alloc; +mod mapper; +mod multi_level; +mod multi_level_x4; +mod page_table; +mod page_table_x4; + +pub use self::frame_alloc::*; +pub use self::mapper::*; +pub use self::multi_level::*; +pub use self::multi_level_x4::*; +pub use self::page_table::*; +pub use self::page_table_x4::*; diff --git a/third-party/riscv/src/paging/multi_level.rs b/third-party/riscv/src/paging/multi_level.rs new file mode 100644 index 00000000..ae1a114d --- /dev/null +++ b/third-party/riscv/src/paging/multi_level.rs @@ -0,0 +1,354 @@ +use super::frame_alloc::*; +use super::mapper::*; +use super::page_table::{PageTableFlags as F, *}; +use crate::addr::*; +use core::marker::PhantomData; + +/// This struct is a two level page table with `Mapper` trait implemented. +pub struct Rv32PageTableWith<'a, V: VirtualAddress + AddressL2, FL: MapperFlushable> { + root_table: &'a mut PageTableX32, + linear_offset: u64, // VA = PA + linear_offset + phantom: PhantomData<(V, FL)>, +} + +impl<'a, V: VirtualAddress + AddressL2, FL: MapperFlushable> Rv32PageTableWith<'a, V, FL> { + pub fn new(table: &'a mut PageTableX32, linear_offset: usize) -> Self { + Rv32PageTableWith { + root_table: table, + linear_offset: linear_offset as u64, + phantom: PhantomData, + } + } + + fn create_p1_if_not_exist( + &mut self, + p2_index: usize, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result<&mut PageTableX32, MapToError> { + if self.root_table[p2_index].is_unused() { + let frame = allocator.alloc().ok_or(MapToError::FrameAllocationFailed)?; + self.root_table[p2_index].set(frame.clone(), F::VALID); + let p1_table: &mut PageTableX32 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + p1_table.zero(); + Ok(p1_table) + } else { + let frame = self.root_table[p2_index].frame::(); + let p1_table: &mut PageTableX32 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + Ok(p1_table) + } + } +} + +impl<'a, V: VirtualAddress + AddressL2, FL: MapperFlushable> Mapper + for Rv32PageTableWith<'a, V, FL> +{ + type P = PhysAddrSv32; + type V = V; + type MapperFlush = FL; + type Entry = PageTableEntryX32; + fn map_to( + &mut self, + page: ::Page, + frame: ::Frame, + flags: PageTableFlags, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result { + let p1_table = self.create_p1_if_not_exist(page.p2_index(), allocator)?; + if !p1_table[page.p1_index()].is_unused() { + return Err(MapToError::PageAlreadyMapped); + } + p1_table[page.p1_index()].set(frame, flags); + Ok(Self::MapperFlush::new(page)) + } + + fn unmap( + &mut self, + page: ::Page, + ) -> Result<(::Frame, Self::MapperFlush), UnmapError<::P>> + { + if self.root_table[page.p2_index()].is_unused() { + return Err(UnmapError::PageNotMapped); + } + let p1_frame = self.root_table[page.p2_index()].frame::(); + let p1_table: &mut PageTableX32 = unsafe { p1_frame.as_kernel_mut(self.linear_offset) }; + let p1_entry = &mut p1_table[page.p1_index()]; + if !p1_entry.flags().contains(F::VALID) { + return Err(UnmapError::PageNotMapped); + } + let frame = p1_entry.frame(); + p1_entry.set_unused(); + Ok((frame, Self::MapperFlush::new(page))) + } + + fn ref_entry( + &mut self, + page: ::Page, + ) -> Result<&mut PageTableEntryX32, FlagUpdateError> { + if self.root_table[page.p2_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + let p1_frame = self.root_table[page.p2_index()].frame::(); + let p1_table: &mut PageTableX32 = unsafe { p1_frame.as_kernel_mut(self.linear_offset) }; + Ok(&mut p1_table[page.p1_index()]) + } +} + +/// This struct is a three level page table with `Mapper` trait implemented. + +pub struct Rv39PageTableWith<'a, V: VirtualAddress + AddressL3, FL: MapperFlushable> { + root_table: &'a mut PageTableX64, + linear_offset: u64, // VA = PA + linear_offset + phantom: PhantomData<(V, FL)>, +} + +impl<'a, V: VirtualAddress + AddressL3, FL: MapperFlushable> Rv39PageTableWith<'a, V, FL> { + pub fn new(table: &'a mut PageTableX64, linear_offset: usize) -> Self { + Rv39PageTableWith { + root_table: table, + linear_offset: linear_offset as u64, + phantom: PhantomData, + } + } + + fn create_p1_if_not_exist( + &mut self, + p3_index: usize, + p2_index: usize, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result<&mut PageTableX64, MapToError> { + let p2_table = if self.root_table[p3_index].is_unused() { + let frame = allocator.alloc().ok_or(MapToError::FrameAllocationFailed)?; + self.root_table[p3_index].set(frame.clone(), F::VALID); + let p2_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + p2_table.zero(); + p2_table + } else { + let frame = self.root_table[p3_index].frame::(); + unsafe { frame.as_kernel_mut(self.linear_offset) } + }; + if p2_table[p2_index].is_unused() { + let frame = allocator.alloc().ok_or(MapToError::FrameAllocationFailed)?; + p2_table[p2_index].set(frame.clone(), F::VALID); + let p1_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + p1_table.zero(); + Ok(p1_table) + } else { + let frame = p2_table[p2_index].frame::(); + let p1_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + Ok(p1_table) + } + } +} + +impl<'a, V: VirtualAddress + AddressL3, FL: MapperFlushable> Mapper + for Rv39PageTableWith<'a, V, FL> +{ + type P = PhysAddrSv39; + type V = V; + type MapperFlush = FL; + type Entry = PageTableEntryX64; + fn map_to( + &mut self, + page: ::Page, + frame: ::Frame, + flags: PageTableFlags, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result { + let p1_table = self.create_p1_if_not_exist(page.p3_index(), page.p2_index(), allocator)?; + if !p1_table[page.p1_index()].is_unused() { + return Err(MapToError::PageAlreadyMapped); + } + p1_table[page.p1_index()].set(frame, flags); + Ok(Self::MapperFlush::new(page)) + } + + fn unmap( + &mut self, + page: ::Page, + ) -> Result<(::Frame, Self::MapperFlush), UnmapError<::P>> + { + if self.root_table[page.p3_index()].is_unused() { + return Err(UnmapError::PageNotMapped); + } + let p2_frame = self.root_table[page.p3_index()].frame::(); + let p2_table: &mut PageTableX64 = unsafe { p2_frame.as_kernel_mut(self.linear_offset) }; + + if p2_table[page.p2_index()].is_unused() { + return Err(UnmapError::PageNotMapped); + } + let p1_frame = p2_table[page.p2_index()].frame::(); + let p1_table: &mut PageTableX64 = unsafe { p1_frame.as_kernel_mut(self.linear_offset) }; + let p1_entry = &mut p1_table[page.p1_index()]; + if !p1_entry.flags().contains(F::VALID) { + return Err(UnmapError::PageNotMapped); + } + let frame = p1_entry.frame(); + p1_entry.set_unused(); + Ok((frame, Self::MapperFlush::new(page))) + } + + fn ref_entry( + &mut self, + page: ::Page, + ) -> Result<&mut PageTableEntryX64, FlagUpdateError> { + if self.root_table[page.p3_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + let p2_frame = self.root_table[page.p3_index()].frame::(); + let p2_table: &mut PageTableX64 = unsafe { p2_frame.as_kernel_mut(self.linear_offset) }; + if p2_table[page.p2_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p1_frame = p2_table[page.p2_index()].frame::(); + let p1_table: &mut PageTableX64 = unsafe { p1_frame.as_kernel_mut(self.linear_offset) }; + Ok(&mut p1_table[page.p1_index()]) + } +} + +/// This struct is a four level page table with `Mapper` trait implemented. + +pub struct Rv48PageTableWith<'a, V: VirtualAddress + AddressL4, FL: MapperFlushable> { + root_table: &'a mut PageTableX64, + linear_offset: u64, // VA = PA + linear_offset + phantom: PhantomData<(V, FL)>, +} + +impl<'a, V: VirtualAddress + AddressL4, FL: MapperFlushable> Rv48PageTableWith<'a, V, FL> { + pub fn new(table: &'a mut PageTableX64, linear_offset: usize) -> Self { + Rv48PageTableWith { + root_table: table, + linear_offset: linear_offset as u64, + phantom: PhantomData, + } + } + + fn create_p1_if_not_exist( + &mut self, + p4_index: usize, + p3_index: usize, + p2_index: usize, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result<&mut PageTableX64, MapToError> { + let p3_table = if self.root_table[p4_index].is_unused() { + let frame = allocator.alloc().ok_or(MapToError::FrameAllocationFailed)?; + self.root_table[p4_index].set(frame.clone(), F::VALID); + let p3_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + p3_table.zero(); + p3_table + } else { + let frame = self.root_table[p4_index].frame::(); + unsafe { frame.as_kernel_mut(self.linear_offset) } + }; + + let p2_table = if p3_table[p3_index].is_unused() { + let frame = allocator.alloc().ok_or(MapToError::FrameAllocationFailed)?; + p3_table[p3_index].set(frame.clone(), F::VALID); + let p2_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + p2_table.zero(); + p2_table + } else { + let frame = p3_table[p3_index].frame::(); + unsafe { frame.as_kernel_mut(self.linear_offset) } + }; + + if p2_table[p2_index].is_unused() { + let frame = allocator.alloc().ok_or(MapToError::FrameAllocationFailed)?; + p2_table[p2_index].set(frame.clone(), F::VALID); + let p1_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + p1_table.zero(); + Ok(p1_table) + } else { + let frame = p2_table[p2_index].frame::(); + let p1_table: &mut PageTableX64 = unsafe { frame.as_kernel_mut(self.linear_offset) }; + Ok(p1_table) + } + } +} + +impl<'a, V: VirtualAddress + AddressL4, FL: MapperFlushable> Mapper + for Rv48PageTableWith<'a, V, FL> +{ + type P = PhysAddrSv48; + type V = V; + type MapperFlush = FL; + type Entry = PageTableEntryX64; + fn map_to( + &mut self, + page: ::Page, + frame: ::Frame, + flags: PageTableFlags, + allocator: &mut impl FrameAllocatorFor<::P>, + ) -> Result { + let p1_table = self.create_p1_if_not_exist( + page.p4_index(), + page.p3_index(), + page.p2_index(), + allocator, + )?; + if !p1_table[page.p1_index()].is_unused() { + return Err(MapToError::PageAlreadyMapped); + } + p1_table[page.p1_index()].set(frame, flags); + Ok(Self::MapperFlush::new(page)) + } + + fn unmap( + &mut self, + page: ::Page, + ) -> Result<(::Frame, Self::MapperFlush), UnmapError<::P>> + { + if self.root_table[page.p4_index()].is_unused() { + return Err(UnmapError::PageNotMapped); + } + let p3_frame = self.root_table[page.p4_index()].frame::(); + let p3_table: &mut PageTableX64 = unsafe { p3_frame.as_kernel_mut(self.linear_offset) }; + + if p3_table[page.p3_index()].is_unused() { + return Err(UnmapError::PageNotMapped); + } + let p2_frame = p3_table[page.p3_index()].frame::(); + let p2_table: &mut PageTableX64 = unsafe { p2_frame.as_kernel_mut(self.linear_offset) }; + + if p2_table[page.p2_index()].is_unused() { + return Err(UnmapError::PageNotMapped); + } + let p1_frame = p2_table[page.p2_index()].frame::(); + let p1_table: &mut PageTableX64 = unsafe { p1_frame.as_kernel_mut(self.linear_offset) }; + let p1_entry = &mut p1_table[page.p1_index()]; + if !p1_entry.flags().contains(F::VALID) { + return Err(UnmapError::PageNotMapped); + } + let frame = p1_entry.frame::(); + p1_entry.set_unused(); + Ok((frame, Self::MapperFlush::new(page))) + } + + fn ref_entry( + &mut self, + page: ::Page, + ) -> Result<&mut PageTableEntryX64, FlagUpdateError> { + if self.root_table[page.p4_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + let p3_frame = self.root_table[page.p4_index()].frame::(); + let p3_table: &mut PageTableX64 = unsafe { p3_frame.as_kernel_mut(self.linear_offset) }; + + if p3_table[page.p3_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + let p2_frame = p3_table[page.p3_index()].frame::(); + let p2_table: &mut PageTableX64 = unsafe { p2_frame.as_kernel_mut(self.linear_offset) }; + if p2_table[page.p2_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p1_frame = p2_table[page.p2_index()].frame::(); + let p1_table: &mut PageTableX64 = unsafe { p1_frame.as_kernel_mut(self.linear_offset) }; + Ok(&mut p1_table[page.p1_index()]) + } +} + +pub type Rv32PageTable<'a> = Rv32PageTableWith<'a, VirtAddrSv32, MapperFlush>; +pub type Rv39PageTable<'a> = Rv39PageTableWith<'a, VirtAddrSv39, MapperFlush>; +pub type Rv48PageTable<'a> = Rv48PageTableWith<'a, VirtAddrSv48, MapperFlush>; diff --git a/third-party/riscv/src/paging/multi_level_x4.rs b/third-party/riscv/src/paging/multi_level_x4.rs new file mode 100644 index 00000000..a719e041 --- /dev/null +++ b/third-party/riscv/src/paging/multi_level_x4.rs @@ -0,0 +1,42 @@ +use crate::addr::*; +use crate::asm::{hfence_gvma, hfence_vvma}; +use crate::paging::mapper::MapperFlushable; +use crate::paging::multi_level::Rv32PageTableWith; +use crate::paging::multi_level::{Rv39PageTableWith, Rv48PageTableWith}; + +#[must_use = "Guest Physical Address Table changes must be flushed or ignored."] +pub struct MapperFlushGPA(usize); + +impl MapperFlushable for MapperFlushGPA { + fn new(page: PageWith) -> Self { + MapperFlushGPA(page.start_address().as_usize()) + } + fn flush(self) { + unsafe { + hfence_gvma(self.0, 0); + } + } + fn ignore(self) {} +} + +#[must_use = "Guest Page Table changes must be flushed or ignored."] +pub struct MapperFlushGPT(usize); + +impl MapperFlushable for MapperFlushGPT { + fn new(page: PageWith) -> Self { + MapperFlushGPT(page.start_address().as_usize()) + } + fn flush(self) { + unsafe { + hfence_vvma(self.0, 0); + } + } + fn ignore(self) {} +} + +pub type Rv32PageTableX4<'a> = Rv32PageTableWith<'a, GPAddrSv32X4, MapperFlushGPA>; +pub type Rv39PageTableX4<'a> = Rv39PageTableWith<'a, GPAddrSv39X4, MapperFlushGPA>; +pub type Rv48PageTableX4<'a> = Rv48PageTableWith<'a, GPAddrSv48X4, MapperFlushGPA>; +pub type Rv32PageTableGuest<'a> = Rv32PageTableWith<'a, VirtAddrSv32, MapperFlushGPT>; +pub type Rv39PageTableGuest<'a> = Rv39PageTableWith<'a, VirtAddrSv39, MapperFlushGPT>; +pub type Rv48PageTableGuest<'a> = Rv48PageTableWith<'a, VirtAddrSv48, MapperFlushGPT>; diff --git a/third-party/riscv/src/paging/page_table.rs b/third-party/riscv/src/paging/page_table.rs new file mode 100644 index 00000000..56896fe2 --- /dev/null +++ b/third-party/riscv/src/paging/page_table.rs @@ -0,0 +1,252 @@ +use addr::*; +use core::convert::TryInto; +use core::fmt::{Debug, Error, Formatter}; +use core::marker::PhantomData; +use core::ops::{Index, IndexMut}; + +pub type Entries32 = [PageTableEntryX32; RV32_ENTRY_COUNT]; +pub type Entries64 = [PageTableEntryX64; RV64_ENTRY_COUNT]; + +// To avoid const generic. +pub trait PTEIterableSlice { + fn to_pte_slice<'a>(&'a self) -> &'a [T]; + fn to_pte_slice_mut<'a>(&'a mut self) -> &'a mut [T]; + fn pte_index(&self, index: usize) -> &T; + fn pte_index_mut(&mut self, index: usize) -> &mut T; +} + +impl PTEIterableSlice for Entries32 { + fn to_pte_slice(&self) -> &[PageTableEntryX32] { + self + } + fn to_pte_slice_mut(&mut self) -> &mut [PageTableEntryX32] { + self + } + fn pte_index(&self, index: usize) -> &PageTableEntryX32 { + &self[index] + } + fn pte_index_mut(&mut self, index: usize) -> &mut PageTableEntryX32 { + &mut self[index] + } +} +impl PTEIterableSlice for Entries64 { + fn to_pte_slice(&self) -> &[PageTableEntryX64] { + self + } + fn to_pte_slice_mut(&mut self) -> &mut [PageTableEntryX64] { + self + } + fn pte_index(&self, index: usize) -> &PageTableEntryX64 { + &self[index] + } + fn pte_index_mut(&mut self, index: usize) -> &mut PageTableEntryX64 { + &mut self[index] + } +} + +#[repr(C)] +pub struct PageTableWith, E: PTE> { + entries: T, + phantom: PhantomData, +} + +impl, E: PTE> PageTableWith { + /// Clears all entries. + pub fn zero(&mut self) { + for entry in self.entries.to_pte_slice_mut().iter_mut() { + entry.set_unused(); + } + } +} + +impl, E: PTE> Index for PageTableWith { + type Output = E; + + fn index(&self, index: usize) -> &Self::Output { + self.entries.pte_index(index) + } +} + +impl, E: PTE> IndexMut for PageTableWith { + fn index_mut(&mut self, index: usize) -> &mut Self::Output { + self.entries.pte_index_mut(index) + } +} + +impl, E: PTE + Debug> Debug for PageTableWith { + fn fmt(&self, f: &mut Formatter) -> Result<(), Error> { + f.debug_map() + .entries( + self.entries + .to_pte_slice() + .iter() + .enumerate() + .filter(|p| !p.1.is_unused()), + ) + .finish() + } +} + +pub trait PTE { + fn is_unused(&self) -> bool; + fn set_unused(&mut self); + fn flags(&self) -> PageTableFlags; + fn ppn(&self) -> usize; + fn ppn_u64(&self) -> u64; + fn addr(&self) -> T; + fn frame(&self) -> FrameWith; + fn set(&mut self, frame: FrameWith, flags: PageTableFlags); + fn flags_mut(&mut self) -> &mut PageTableFlags; +} + +#[derive(Copy, Clone)] +#[repr(C)] +pub struct PageTableEntryX32(u32); + +impl PTE for PageTableEntryX32 { + fn is_unused(&self) -> bool { + self.0 == 0 + } + fn set_unused(&mut self) { + self.0 = 0; + } + fn flags(&self) -> PageTableFlags { + PageTableFlags::from_bits_truncate(self.0 as usize) + } + fn ppn(&self) -> usize { + self.ppn_u64().try_into().unwrap() + } + fn ppn_u64(&self) -> u64 { + (self.0 >> 10) as u64 + } + fn addr(&self) -> T { + T::new_u64((self.ppn() as u64) << 12) + } + fn frame(&self) -> FrameWith { + FrameWith::of_addr(self.addr()) + } + fn set(&mut self, frame: FrameWith, mut flags: PageTableFlags) { + // U540 will raise page fault when accessing page with A=0 or D=0 + flags |= EF::ACCESSED | EF::DIRTY; + self.0 = ((frame.number() << 10) | flags.bits()) as u32; + } + fn flags_mut(&mut self) -> &mut PageTableFlags { + unsafe { &mut *(self as *mut _ as *mut PageTableFlags) } + } +} + +impl Debug for PageTableEntryX32 { + fn fmt(&self, f: &mut Formatter) -> Result<(), Error> { + f.debug_struct("PageTableEntryX32") + .field("frame", &self.frame::()) + .field("flags", &self.flags()) + .finish() + } +} + +#[derive(Copy, Clone)] +pub struct PageTableEntryX64(u64); + +impl PTE for PageTableEntryX64 { + fn is_unused(&self) -> bool { + self.0 == 0 + } + fn set_unused(&mut self) { + self.0 = 0; + } + fn flags(&self) -> PageTableFlags { + PageTableFlags::from_bits_truncate(self.0 as usize) + } + fn ppn(&self) -> usize { + self.ppn_u64().try_into().unwrap() + } + fn ppn_u64(&self) -> u64 { + (self.0 >> 10) as u64 + } + fn addr(&self) -> T { + T::new_u64((self.ppn() as u64) << 12) + } + fn frame(&self) -> FrameWith { + FrameWith::of_addr(self.addr()) + } + fn set(&mut self, frame: FrameWith, mut flags: PageTableFlags) { + // U540 will raise page fault when accessing page with A=0 or D=0 + flags |= EF::ACCESSED | EF::DIRTY; + self.0 = ((frame.number() << 10) | flags.bits()) as u64; + } + fn flags_mut(&mut self) -> &mut PageTableFlags { + unsafe { &mut *(self as *mut _ as *mut PageTableFlags) } + } +} + +pub struct PageTableEntryX64Printer<'a, P: PhysicalAddress>( + &'a PageTableEntryX64, + PhantomData<*const P>, +); + +impl<'a, P: PhysicalAddress> Debug for PageTableEntryX64Printer<'a, P> { + fn fmt(&self, f: &mut Formatter) -> Result<(), Error> { + f.debug_struct("PageTableEntryX64") + .field("frame", &self.0.frame::

()) + .field("flags", &self.0.flags()) + .finish() + } +} + +impl PageTableEntryX64 { + pub fn debug_sv39<'a>(&'a self) -> PageTableEntryX64Printer<'a, PhysAddrSv39> { + PageTableEntryX64Printer(self, PhantomData) + } + pub fn debug_sv48<'a>(&'a self) -> PageTableEntryX64Printer<'a, PhysAddrSv48> { + PageTableEntryX64Printer(self, PhantomData) + } +} + +impl Debug for PageTableEntryX64 { + fn fmt(&self, f: &mut Formatter) -> Result<(), Error> { + self.debug_sv48().fmt(f) + } +} + +pub const RV64_ENTRY_COUNT: usize = 1 << 9; +pub const RV32_ENTRY_COUNT: usize = 1 << 10; +#[cfg(riscv64)] +pub const ENTRY_COUNT: usize = RV64_ENTRY_COUNT; +#[cfg(riscv32)] +pub const ENTRY_COUNT: usize = RV32_ENTRY_COUNT; +#[cfg(riscv64)] +pub type PageTableEntry = PageTableEntryX64; +#[cfg(riscv32)] +pub type PageTableEntry = PageTableEntryX32; +#[cfg(riscv64)] +pub type Entries = Entries64; +#[cfg(riscv32)] +pub type Entries = Entries32; +#[cfg(not(any(riscv32, riscv64)))] +pub const ENTRY_COUNT: usize = 1 << 0; +#[cfg(not(any(riscv32, riscv64)))] +pub type Entries = Entries64; + +pub type PageTableX32 = PageTableWith; +pub type PageTableX64 = PageTableWith; +#[cfg(riscv64)] +pub type PageTable = PageTableX64; +#[cfg(riscv32)] +pub type PageTable = PageTableX32; +bitflags! { + /// Possible flags for a page table entry. + pub struct PageTableFlags: usize { + const VALID = 1 << 0; + const READABLE = 1 << 1; + const WRITABLE = 1 << 2; + const EXECUTABLE = 1 << 3; + const USER = 1 << 4; + const GLOBAL = 1 << 5; + const ACCESSED = 1 << 6; + const DIRTY = 1 << 7; + const RESERVED1 = 1 << 8; + const RESERVED2 = 1 << 9; + } +} + +type EF = PageTableFlags; diff --git a/third-party/riscv/src/paging/page_table_x4.rs b/third-party/riscv/src/paging/page_table_x4.rs new file mode 100644 index 00000000..0d24193c --- /dev/null +++ b/third-party/riscv/src/paging/page_table_x4.rs @@ -0,0 +1,44 @@ +/// This file is for Hypervisor-related x4 page tables, including Sv32x4, Sv39x4 and Sv48x4. +/// In fact, these x4 page tables are Phys-to-Phys page tables from GPAs to real PAs. +use super::page_table::{ + PTEIterableSlice, PageTableEntryX32, PageTableEntryX64, PageTableWith, RV32_ENTRY_COUNT, + RV64_ENTRY_COUNT, +}; + +// The root page table is 4 times larger. +pub const RV32_X4_ENTRY_COUNT: usize = RV32_ENTRY_COUNT << 2; +pub const RV64_X4_ENTRY_COUNT: usize = RV64_ENTRY_COUNT << 2; + +pub type Entries32X4 = [PageTableEntryX32; RV32_X4_ENTRY_COUNT]; +pub type Entries64X4 = [PageTableEntryX64; RV64_X4_ENTRY_COUNT]; + +impl PTEIterableSlice for Entries32X4 { + fn to_pte_slice(&self) -> &[PageTableEntryX32] { + self + } + fn to_pte_slice_mut(&mut self) -> &mut [PageTableEntryX32] { + self + } + fn pte_index(&self, index: usize) -> &PageTableEntryX32 { + &self[index] + } + fn pte_index_mut(&mut self, index: usize) -> &mut PageTableEntryX32 { + &mut self[index] + } +} +impl PTEIterableSlice for Entries64X4 { + fn to_pte_slice(&self) -> &[PageTableEntryX64] { + self + } + fn to_pte_slice_mut(&mut self) -> &mut [PageTableEntryX64] { + self + } + fn pte_index(&self, index: usize) -> &PageTableEntryX64 { + &self[index] + } + fn pte_index_mut(&mut self, index: usize) -> &mut PageTableEntryX64 { + &mut self[index] + } +} +pub type PageTable32X4 = PageTableWith; +pub type PageTable64X4 = PageTableWith; diff --git a/third-party/riscv/src/register/fcsr.rs b/third-party/riscv/src/register/fcsr.rs new file mode 100644 index 00000000..855eb5d6 --- /dev/null +++ b/third-party/riscv/src/register/fcsr.rs @@ -0,0 +1,134 @@ +//! Floating-point control and status register + +use bit_field::BitField; + +/// Floating-point control and status register +#[derive(Clone, Copy, Debug)] +pub struct FCSR { + bits: u32, +} + +/// Accrued Exception Flags +#[derive(Clone, Copy, Debug)] +pub struct Flags(u32); + +/// Accrued Exception Flag +#[derive(Clone, Copy, Debug)] +pub enum Flag { + /// Inexact + NX = 0b00001, + + /// Underflow + UF = 0b00010, + + /// Overflow + OF = 0b00100, + + /// Divide by Zero + DZ = 0b01000, + + /// Invalid Operation + NV = 0b10000, +} + +impl Flags { + /// Inexact + #[inline] + pub fn nx(&self) -> bool { + self.0.get_bit(0) + } + + /// Underflow + #[inline] + pub fn uf(&self) -> bool { + self.0.get_bit(1) + } + + /// Overflow + #[inline] + pub fn of(&self) -> bool { + self.0.get_bit(2) + } + + /// Divide by Zero + #[inline] + pub fn dz(&self) -> bool { + self.0.get_bit(3) + } + + /// Invalid Operation + #[inline] + pub fn nv(&self) -> bool { + self.0.get_bit(4) + } +} + +/// Rounding Mode +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum RoundingMode { + RoundToNearestEven = 0b000, + RoundTowardsZero = 0b001, + RoundDown = 0b010, + RoundUp = 0b011, + RoundToNearestMaxMagnitude = 0b100, + Invalid = 0b111, +} + +impl FCSR { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> u32 { + self.bits + } + + /// Accrued Exception Flags + #[inline] + pub fn fflags(&self) -> Flags { + Flags(self.bits.get_bits(0..5)) + } + + /// Rounding Mode + #[inline] + pub fn frm(&self) -> RoundingMode { + match self.bits.get_bits(5..8) { + 0b000 => RoundingMode::RoundToNearestEven, + 0b001 => RoundingMode::RoundTowardsZero, + 0b010 => RoundingMode::RoundDown, + 0b011 => RoundingMode::RoundUp, + 0b100 => RoundingMode::RoundToNearestMaxMagnitude, + _ => RoundingMode::Invalid, + } + } +} + +read_csr!(0x003, __read_fcsr); +write_csr!(0x003, __write_fcsr); +clear!(0x003, __clear_fcsr); + +/// Reads the CSR +#[inline] +pub fn read() -> FCSR { + FCSR { + bits: unsafe { _read() as u32 }, + } +} + +/// Writes the CSR +#[inline] +pub unsafe fn set_rounding_mode(frm: RoundingMode) { + let old = read(); + let bits = ((frm as u32) << 5) | old.fflags().0; + _write(bits as usize); +} + +/// Resets `fflags` field bits +#[inline] +pub unsafe fn clear_flags() { + let mask = 0b11111; + _clear(mask); +} + +/// Resets `fflags` field bit +#[inline] +pub unsafe fn clear_flag(flag: Flag) { + _clear(flag as usize); +} diff --git a/third-party/riscv/src/register/hpmcounterx.rs b/third-party/riscv/src/register/hpmcounterx.rs new file mode 100644 index 00000000..5eb15b07 --- /dev/null +++ b/third-party/riscv/src/register/hpmcounterx.rs @@ -0,0 +1,82 @@ +macro_rules! reg { + ( + $addr:expr, $csrl:ident, $csrh:ident, $readf:ident, $writef:ident + ) => { + /// Performance-monitoring counter + pub mod $csrl { + read_csr_as_usize!($addr, $readf); + read_composite_csr!(super::$csrh::read(), read()); + } + } +} + +macro_rules! regh { + ( + $addr:expr, $csrh:ident, $readf:ident, $writef:ident + ) => { + /// Upper 32 bits of performance-monitoring counter (RV32I only) + pub mod $csrh { + read_csr_as_usize_rv32!($addr, $readf); + } + } +} + +reg!(0xC03, hpmcounter3, hpmcounter3h, __read_hpmcounter3, __write_hpmcounter3); +reg!(0xC04, hpmcounter4, hpmcounter4h, __read_hpmcounter4, __write_hpmcounter4); +reg!(0xC05, hpmcounter5, hpmcounter5h, __read_hpmcounter5, __write_hpmcounter5); +reg!(0xC06, hpmcounter6, hpmcounter6h, __read_hpmcounter6, __write_hpmcounter6); +reg!(0xC07, hpmcounter7, hpmcounter7h, __read_hpmcounter7, __write_hpmcounter7); +reg!(0xC08, hpmcounter8, hpmcounter8h, __read_hpmcounter8, __write_hpmcounter8); +reg!(0xC09, hpmcounter9, hpmcounter9h, __read_hpmcounter9, __write_hpmcounter9); +reg!(0xC0A, hpmcounter10, hpmcounter10h, __read_hpmcounter10, __write_hpmcounter10); +reg!(0xC0B, hpmcounter11, hpmcounter11h, __read_hpmcounter11, __write_hpmcounter11); +reg!(0xC0C, hpmcounter12, hpmcounter12h, __read_hpmcounter12, __write_hpmcounter12); +reg!(0xC0D, hpmcounter13, hpmcounter13h, __read_hpmcounter13, __write_hpmcounter13); +reg!(0xC0E, hpmcounter14, hpmcounter14h, __read_hpmcounter14, __write_hpmcounter14); +reg!(0xC0F, hpmcounter15, hpmcounter15h, __read_hpmcounter15, __write_hpmcounter15); +reg!(0xC10, hpmcounter16, hpmcounter16h, __read_hpmcounter16, __write_hpmcounter16); +reg!(0xC11, hpmcounter17, hpmcounter17h, __read_hpmcounter17, __write_hpmcounter17); +reg!(0xC12, hpmcounter18, hpmcounter18h, __read_hpmcounter18, __write_hpmcounter18); +reg!(0xC13, hpmcounter19, hpmcounter19h, __read_hpmcounter19, __write_hpmcounter19); +reg!(0xC14, hpmcounter20, hpmcounter20h, __read_hpmcounter20, __write_hpmcounter20); +reg!(0xC15, hpmcounter21, hpmcounter21h, __read_hpmcounter21, __write_hpmcounter21); +reg!(0xC16, hpmcounter22, hpmcounter22h, __read_hpmcounter22, __write_hpmcounter22); +reg!(0xC17, hpmcounter23, hpmcounter23h, __read_hpmcounter23, __write_hpmcounter23); +reg!(0xC18, hpmcounter24, hpmcounter24h, __read_hpmcounter24, __write_hpmcounter24); +reg!(0xC19, hpmcounter25, hpmcounter25h, __read_hpmcounter25, __write_hpmcounter25); +reg!(0xC1A, hpmcounter26, hpmcounter26h, __read_hpmcounter26, __write_hpmcounter26); +reg!(0xC1B, hpmcounter27, hpmcounter27h, __read_hpmcounter27, __write_hpmcounter27); +reg!(0xC1C, hpmcounter28, hpmcounter28h, __read_hpmcounter28, __write_hpmcounter28); +reg!(0xC1D, hpmcounter29, hpmcounter29h, __read_hpmcounter29, __write_hpmcounter29); +reg!(0xC1E, hpmcounter30, hpmcounter30h, __read_hpmcounter30, __write_hpmcounter30); +reg!(0xC1F, hpmcounter31, hpmcounter31h, __read_hpmcounter31, __write_hpmcounter31); + +regh!(0xC83, hpmcounter3h, __read_hpmcounter3h, __write_hpmcounter3h); +regh!(0xC84, hpmcounter4h, __read_hpmcounter4h, __write_hpmcounter4h); +regh!(0xC85, hpmcounter5h, __read_hpmcounter5h, __write_hpmcounter5h); +regh!(0xC86, hpmcounter6h, __read_hpmcounter6h, __write_hpmcounter6h); +regh!(0xC87, hpmcounter7h, __read_hpmcounter7h, __write_hpmcounter7h); +regh!(0xC88, hpmcounter8h, __read_hpmcounter8h, __write_hpmcounter8h); +regh!(0xC89, hpmcounter9h, __read_hpmcounter9h, __write_hpmcounter9h); +regh!(0xC8A, hpmcounter10h, __read_hpmcounter10h, __write_hpmcounter10h); +regh!(0xC8B, hpmcounter11h, __read_hpmcounter11h, __write_hpmcounter11h); +regh!(0xC8C, hpmcounter12h, __read_hpmcounter12h, __write_hpmcounter12h); +regh!(0xC8D, hpmcounter13h, __read_hpmcounter13h, __write_hpmcounter13h); +regh!(0xC8E, hpmcounter14h, __read_hpmcounter14h, __write_hpmcounter14h); +regh!(0xC8F, hpmcounter15h, __read_hpmcounter15h, __write_hpmcounter15h); +regh!(0xC90, hpmcounter16h, __read_hpmcounter16h, __write_hpmcounter16h); +regh!(0xC91, hpmcounter17h, __read_hpmcounter17h, __write_hpmcounter17h); +regh!(0xC92, hpmcounter18h, __read_hpmcounter18h, __write_hpmcounter18h); +regh!(0xC93, hpmcounter19h, __read_hpmcounter19h, __write_hpmcounter19h); +regh!(0xC94, hpmcounter20h, __read_hpmcounter20h, __write_hpmcounter20h); +regh!(0xC95, hpmcounter21h, __read_hpmcounter21h, __write_hpmcounter21h); +regh!(0xC96, hpmcounter22h, __read_hpmcounter22h, __write_hpmcounter22h); +regh!(0xC97, hpmcounter23h, __read_hpmcounter23h, __write_hpmcounter23h); +regh!(0xC98, hpmcounter24h, __read_hpmcounter24h, __write_hpmcounter24h); +regh!(0xC99, hpmcounter25h, __read_hpmcounter25h, __write_hpmcounter25h); +regh!(0xC9A, hpmcounter26h, __read_hpmcounter26h, __write_hpmcounter26h); +regh!(0xC9B, hpmcounter27h, __read_hpmcounter27h, __write_hpmcounter27h); +regh!(0xC9C, hpmcounter28h, __read_hpmcounter28h, __write_hpmcounter28h); +regh!(0xC9D, hpmcounter29h, __read_hpmcounter29h, __write_hpmcounter29h); +regh!(0xC9E, hpmcounter30h, __read_hpmcounter30h, __write_hpmcounter30h); +regh!(0xC9F, hpmcounter31h, __read_hpmcounter31h, __write_hpmcounter31h); diff --git a/third-party/riscv/src/register/hypervisorx64/hcounteren.rs b/third-party/riscv/src/register/hypervisorx64/hcounteren.rs new file mode 100644 index 00000000..7f846900 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hcounteren.rs @@ -0,0 +1,413 @@ +//! Hypervisor Guest External Interrupt Pending Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hcounteren { + bits: usize, +} +impl Hcounteren { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hcounteren { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// + #[inline] + pub fn cy(&self) -> bool { + self.bits.get_bit(0) + } + #[inline] + pub fn set_cy(&mut self, val: bool) { + self.bits.set_bit(0, val); + } + /// + #[inline] + pub fn tm(&self) -> bool { + self.bits.get_bit(1) + } + #[inline] + pub fn set_tm(&mut self, val: bool) { + self.bits.set_bit(1, val); + } + /// + #[inline] + pub fn ir(&self) -> bool { + self.bits.get_bit(2) + } + #[inline] + pub fn set_ir(&mut self, val: bool) { + self.bits.set_bit(2, val); + } + /// + #[inline] + pub fn hpm3(&self) -> bool { + self.bits.get_bit(3) + } + #[inline] + pub fn set_hpm3(&mut self, val: bool) { + self.bits.set_bit(3, val); + } + /// + #[inline] + pub fn hpm4(&self) -> bool { + self.bits.get_bit(4) + } + #[inline] + pub fn set_hpm4(&mut self, val: bool) { + self.bits.set_bit(4, val); + } + /// + #[inline] + pub fn hpm5(&self) -> bool { + self.bits.get_bit(5) + } + #[inline] + pub fn set_hpm5(&mut self, val: bool) { + self.bits.set_bit(5, val); + } + /// + #[inline] + pub fn hpm6(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_hpm6(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// + #[inline] + pub fn hpm7(&self) -> bool { + self.bits.get_bit(7) + } + #[inline] + pub fn set_hpm7(&mut self, val: bool) { + self.bits.set_bit(7, val); + } + /// + #[inline] + pub fn hpm8(&self) -> bool { + self.bits.get_bit(8) + } + #[inline] + pub fn set_hpm8(&mut self, val: bool) { + self.bits.set_bit(8, val); + } + /// + #[inline] + pub fn hpm9(&self) -> bool { + self.bits.get_bit(9) + } + #[inline] + pub fn set_hpm9(&mut self, val: bool) { + self.bits.set_bit(9, val); + } + /// + #[inline] + pub fn hpm10(&self) -> bool { + self.bits.get_bit(10) + } + #[inline] + pub fn set_hpm10(&mut self, val: bool) { + self.bits.set_bit(10, val); + } + /// + #[inline] + pub fn hpm11(&self) -> bool { + self.bits.get_bit(11) + } + #[inline] + pub fn set_hpm11(&mut self, val: bool) { + self.bits.set_bit(11, val); + } + /// + #[inline] + pub fn hpm12(&self) -> bool { + self.bits.get_bit(12) + } + #[inline] + pub fn set_hpm12(&mut self, val: bool) { + self.bits.set_bit(12, val); + } + /// + #[inline] + pub fn hpm13(&self) -> bool { + self.bits.get_bit(13) + } + #[inline] + pub fn set_hpm13(&mut self, val: bool) { + self.bits.set_bit(13, val); + } + /// + #[inline] + pub fn hpm14(&self) -> bool { + self.bits.get_bit(14) + } + #[inline] + pub fn set_hpm14(&mut self, val: bool) { + self.bits.set_bit(14, val); + } + /// + #[inline] + pub fn hpm15(&self) -> bool { + self.bits.get_bit(15) + } + #[inline] + pub fn set_hpm15(&mut self, val: bool) { + self.bits.set_bit(15, val); + } + /// + #[inline] + pub fn hpm16(&self) -> bool { + self.bits.get_bit(16) + } + #[inline] + pub fn set_hpm16(&mut self, val: bool) { + self.bits.set_bit(16, val); + } + /// + #[inline] + pub fn hpm17(&self) -> bool { + self.bits.get_bit(17) + } + #[inline] + pub fn set_hpm17(&mut self, val: bool) { + self.bits.set_bit(17, val); + } + /// + #[inline] + pub fn hpm18(&self) -> bool { + self.bits.get_bit(18) + } + #[inline] + pub fn set_hpm18(&mut self, val: bool) { + self.bits.set_bit(18, val); + } + /// + #[inline] + pub fn hpm19(&self) -> bool { + self.bits.get_bit(19) + } + #[inline] + pub fn set_hpm19(&mut self, val: bool) { + self.bits.set_bit(19, val); + } + /// + #[inline] + pub fn hpm20(&self) -> bool { + self.bits.get_bit(20) + } + #[inline] + pub fn set_hpm20(&mut self, val: bool) { + self.bits.set_bit(20, val); + } + /// + #[inline] + pub fn hpm21(&self) -> bool { + self.bits.get_bit(21) + } + #[inline] + pub fn set_hpm21(&mut self, val: bool) { + self.bits.set_bit(21, val); + } + /// + #[inline] + pub fn hpm22(&self) -> bool { + self.bits.get_bit(22) + } + #[inline] + pub fn set_hpm22(&mut self, val: bool) { + self.bits.set_bit(22, val); + } + /// + #[inline] + pub fn hpm23(&self) -> bool { + self.bits.get_bit(23) + } + #[inline] + pub fn set_hpm23(&mut self, val: bool) { + self.bits.set_bit(23, val); + } + /// + #[inline] + pub fn hpm24(&self) -> bool { + self.bits.get_bit(24) + } + #[inline] + pub fn set_hpm24(&mut self, val: bool) { + self.bits.set_bit(24, val); + } + /// + #[inline] + pub fn hpm25(&self) -> bool { + self.bits.get_bit(25) + } + #[inline] + pub fn set_hpm25(&mut self, val: bool) { + self.bits.set_bit(25, val); + } + /// + #[inline] + pub fn hpm26(&self) -> bool { + self.bits.get_bit(26) + } + #[inline] + pub fn set_hpm26(&mut self, val: bool) { + self.bits.set_bit(26, val); + } + /// + #[inline] + pub fn hpm27(&self) -> bool { + self.bits.get_bit(27) + } + #[inline] + pub fn set_hpm27(&mut self, val: bool) { + self.bits.set_bit(27, val); + } + /// + #[inline] + pub fn hpm28(&self) -> bool { + self.bits.get_bit(28) + } + #[inline] + pub fn set_hpm28(&mut self, val: bool) { + self.bits.set_bit(28, val); + } + /// + #[inline] + pub fn hpm29(&self) -> bool { + self.bits.get_bit(29) + } + #[inline] + pub fn set_hpm29(&mut self, val: bool) { + self.bits.set_bit(29, val); + } + /// + #[inline] + pub fn hpm30(&self) -> bool { + self.bits.get_bit(30) + } + #[inline] + pub fn set_hpm30(&mut self, val: bool) { + self.bits.set_bit(30, val); + } + /// + #[inline] + pub fn hpm31(&self) -> bool { + self.bits.get_bit(31) + } + #[inline] + pub fn set_hpm31(&mut self, val: bool) { + self.bits.set_bit(31, val); + } +} +read_csr_as!(Hcounteren, 3602, __read_hcounteren); +write_csr!(3602, __write_hcounteren); +set!(3602, __set_hcounteren); +clear!(3602, __clear_hcounteren); +// bit ops +set_clear_csr!( + /// + , set_cy, clear_cy, 1 << 0); +set_clear_csr!( + /// + , set_tm, clear_tm, 1 << 1); +set_clear_csr!( + /// + , set_ir, clear_ir, 1 << 2); +set_clear_csr!( + /// + , set_hpm3, clear_hpm3, 1 << 3); +set_clear_csr!( + /// + , set_hpm4, clear_hpm4, 1 << 4); +set_clear_csr!( + /// + , set_hpm5, clear_hpm5, 1 << 5); +set_clear_csr!( + /// + , set_hpm6, clear_hpm6, 1 << 6); +set_clear_csr!( + /// + , set_hpm7, clear_hpm7, 1 << 7); +set_clear_csr!( + /// + , set_hpm8, clear_hpm8, 1 << 8); +set_clear_csr!( + /// + , set_hpm9, clear_hpm9, 1 << 9); +set_clear_csr!( + /// + , set_hpm10, clear_hpm10, 1 << 10); +set_clear_csr!( + /// + , set_hpm11, clear_hpm11, 1 << 11); +set_clear_csr!( + /// + , set_hpm12, clear_hpm12, 1 << 12); +set_clear_csr!( + /// + , set_hpm13, clear_hpm13, 1 << 13); +set_clear_csr!( + /// + , set_hpm14, clear_hpm14, 1 << 14); +set_clear_csr!( + /// + , set_hpm15, clear_hpm15, 1 << 15); +set_clear_csr!( + /// + , set_hpm16, clear_hpm16, 1 << 16); +set_clear_csr!( + /// + , set_hpm17, clear_hpm17, 1 << 17); +set_clear_csr!( + /// + , set_hpm18, clear_hpm18, 1 << 18); +set_clear_csr!( + /// + , set_hpm19, clear_hpm19, 1 << 19); +set_clear_csr!( + /// + , set_hpm20, clear_hpm20, 1 << 20); +set_clear_csr!( + /// + , set_hpm21, clear_hpm21, 1 << 21); +set_clear_csr!( + /// + , set_hpm22, clear_hpm22, 1 << 22); +set_clear_csr!( + /// + , set_hpm23, clear_hpm23, 1 << 23); +set_clear_csr!( + /// + , set_hpm24, clear_hpm24, 1 << 24); +set_clear_csr!( + /// + , set_hpm25, clear_hpm25, 1 << 25); +set_clear_csr!( + /// + , set_hpm26, clear_hpm26, 1 << 26); +set_clear_csr!( + /// + , set_hpm27, clear_hpm27, 1 << 27); +set_clear_csr!( + /// + , set_hpm28, clear_hpm28, 1 << 28); +set_clear_csr!( + /// + , set_hpm29, clear_hpm29, 1 << 29); +set_clear_csr!( + /// + , set_hpm30, clear_hpm30, 1 << 30); +set_clear_csr!( + /// + , set_hpm31, clear_hpm31, 1 << 31); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/hedeleg.rs b/third-party/riscv/src/register/hypervisorx64/hedeleg.rs new file mode 100644 index 00000000..aac1eb93 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hedeleg.rs @@ -0,0 +1,173 @@ +//! Hypervisor Exception Delegation Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hedeleg { + bits: usize, +} +impl Hedeleg { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hedeleg { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Instruction address misaligned + #[inline] + pub fn ex0(&self) -> bool { + self.bits.get_bit(0) + } + #[inline] + pub fn set_ex0(&mut self, val: bool) { + self.bits.set_bit(0, val); + } + /// Instruction access fault + #[inline] + pub fn ex1(&self) -> bool { + self.bits.get_bit(1) + } + #[inline] + pub fn set_ex1(&mut self, val: bool) { + self.bits.set_bit(1, val); + } + /// Illegal instruction + #[inline] + pub fn ex2(&self) -> bool { + self.bits.get_bit(2) + } + #[inline] + pub fn set_ex2(&mut self, val: bool) { + self.bits.set_bit(2, val); + } + /// Breakpoint + #[inline] + pub fn ex3(&self) -> bool { + self.bits.get_bit(3) + } + #[inline] + pub fn set_ex3(&mut self, val: bool) { + self.bits.set_bit(3, val); + } + /// Load address misaligned + #[inline] + pub fn ex4(&self) -> bool { + self.bits.get_bit(4) + } + #[inline] + pub fn set_ex4(&mut self, val: bool) { + self.bits.set_bit(4, val); + } + /// Load access fault + #[inline] + pub fn ex5(&self) -> bool { + self.bits.get_bit(5) + } + #[inline] + pub fn set_ex5(&mut self, val: bool) { + self.bits.set_bit(5, val); + } + /// Store/AMO address misaligned + #[inline] + pub fn ex6(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_ex6(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// Store/AMO access fault + #[inline] + pub fn ex7(&self) -> bool { + self.bits.get_bit(7) + } + #[inline] + pub fn set_ex7(&mut self, val: bool) { + self.bits.set_bit(7, val); + } + /// Environment call from U-mode or VU-mode + #[inline] + pub fn ex8(&self) -> bool { + self.bits.get_bit(8) + } + #[inline] + pub fn set_ex8(&mut self, val: bool) { + self.bits.set_bit(8, val); + } + /// Instruction page fault + #[inline] + pub fn ex12(&self) -> bool { + self.bits.get_bit(12) + } + #[inline] + pub fn set_ex12(&mut self, val: bool) { + self.bits.set_bit(12, val); + } + /// Load page fault + #[inline] + pub fn ex13(&self) -> bool { + self.bits.get_bit(13) + } + #[inline] + pub fn set_ex13(&mut self, val: bool) { + self.bits.set_bit(13, val); + } + /// Store/AMO page fault + #[inline] + pub fn ex15(&self) -> bool { + self.bits.get_bit(15) + } + #[inline] + pub fn set_ex15(&mut self, val: bool) { + self.bits.set_bit(15, val); + } +} +read_csr_as!(Hedeleg, 1538, __read_hedeleg); +write_csr!(1538, __write_hedeleg); +set!(1538, __set_hedeleg); +clear!(1538, __clear_hedeleg); +// bit ops +set_clear_csr!( + ///Instruction address misaligned + , set_ex0, clear_ex0, 1 << 0); +set_clear_csr!( + ///Instruction access fault + , set_ex1, clear_ex1, 1 << 1); +set_clear_csr!( + ///Illegal instruction + , set_ex2, clear_ex2, 1 << 2); +set_clear_csr!( + ///Breakpoint + , set_ex3, clear_ex3, 1 << 3); +set_clear_csr!( + ///Load address misaligned + , set_ex4, clear_ex4, 1 << 4); +set_clear_csr!( + ///Load access fault + , set_ex5, clear_ex5, 1 << 5); +set_clear_csr!( + ///Store/AMO address misaligned + , set_ex6, clear_ex6, 1 << 6); +set_clear_csr!( + ///Store/AMO access fault + , set_ex7, clear_ex7, 1 << 7); +set_clear_csr!( + ///Environment call from U-mode or VU-mode + , set_ex8, clear_ex8, 1 << 8); +set_clear_csr!( + ///Instruction page fault + , set_ex12, clear_ex12, 1 << 12); +set_clear_csr!( + ///Load page fault + , set_ex13, clear_ex13, 1 << 13); +set_clear_csr!( + ///Store/AMO page fault + , set_ex15, clear_ex15, 1 << 15); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/hgatp.rs b/third-party/riscv/src/register/hypervisorx64/hgatp.rs new file mode 100644 index 00000000..798b55c8 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hgatp.rs @@ -0,0 +1,73 @@ +//! Hypervisor Guest Address Translation and Protection Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hgatp { + bits: usize, +} +impl Hgatp { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hgatp { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Guest address translation mode. + #[inline] + pub fn mode(&self) -> HgatpValues { + HgatpValues::from(self.bits.get_bits(60..64)) + } + #[inline] + pub fn set_mode(&mut self, val: HgatpValues) { + self.bits.set_bits(60..64, val as usize); + } + /// Virtual machine ID. + #[inline] + pub fn vmid(&self) -> usize { + self.bits.get_bits(44..58) + } + #[inline] + pub fn set_vmid(&mut self, val: usize) { + self.bits.set_bits(44..58, val); + } + /// Physical Page Number for root page table. + #[inline] + pub fn ppn(&self) -> usize { + self.bits.get_bits(0..44) + } + #[inline] + pub fn set_ppn(&mut self, val: usize) { + self.bits.set_bits(0..44, val); + } +} +read_csr_as!(Hgatp, 1664, __read_hgatp); +write_csr!(1664, __write_hgatp); +set!(1664, __set_hgatp); +clear!(1664, __clear_hgatp); +// bit ops + +// enums +#[derive(Copy, Clone, Debug)] +#[repr(usize)] +pub enum HgatpValues { + Bare = 0, + Sv39x4 = 8, + Sv48x4 = 9, +} +impl HgatpValues { + fn from(x: usize) -> Self { + match x { + 0 => Self::Bare, + 8 => Self::Sv39x4, + 9 => Self::Sv48x4, + _ => unreachable!(), + } + } +} diff --git a/third-party/riscv/src/register/hypervisorx64/hgeie.rs b/third-party/riscv/src/register/hypervisorx64/hgeie.rs new file mode 100644 index 00000000..09d97256 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hgeie.rs @@ -0,0 +1,3 @@ +//! Hypervisor Guest External Interrupt Enable Register. +read_csr_as_usize!(1543, __read_hgeie); +write_csr_as_usize!(1543, __write_hgeie); diff --git a/third-party/riscv/src/register/hypervisorx64/hgeip.rs b/third-party/riscv/src/register/hypervisorx64/hgeip.rs new file mode 100644 index 00000000..75f1cab7 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hgeip.rs @@ -0,0 +1,3 @@ +//! Hypervisor Guest External Interrupt Pending Register. +read_csr_as_usize!(3602, __read_hgeip); +write_csr_as_usize!(3602, __write_hgeip); diff --git a/third-party/riscv/src/register/hypervisorx64/hideleg.rs b/third-party/riscv/src/register/hypervisorx64/hideleg.rs new file mode 100644 index 00000000..f138ab0c --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hideleg.rs @@ -0,0 +1,65 @@ +//! Hypervisor Interrupt Delegation Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hideleg { + bits: usize, +} +impl Hideleg { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hideleg { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Software Interrupt + #[inline] + pub fn sip(&self) -> bool { + self.bits.get_bit(2) + } + #[inline] + pub fn set_sip(&mut self, val: bool) { + self.bits.set_bit(2, val); + } + /// Timer Interrupt + #[inline] + pub fn tip(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_tip(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// External Interrupt + #[inline] + pub fn eip(&self) -> bool { + self.bits.get_bit(10) + } + #[inline] + pub fn set_eip(&mut self, val: bool) { + self.bits.set_bit(10, val); + } +} +read_csr_as!(Hideleg, 1539, __read_hideleg); +write_csr!(1539, __write_hideleg); +set!(1539, __set_hideleg); +clear!(1539, __clear_hideleg); +// bit ops +set_clear_csr!( + ///Software Interrupt + , set_sip, clear_sip, 1 << 2); +set_clear_csr!( + ///Timer Interrupt + , set_tip, clear_tip, 1 << 6); +set_clear_csr!( + ///External Interrupt + , set_eip, clear_eip, 1 << 10); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/hie.rs b/third-party/riscv/src/register/hypervisorx64/hie.rs new file mode 100644 index 00000000..64d1d0c8 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hie.rs @@ -0,0 +1,77 @@ +//! Hypervisor Interrupt Enable Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hie { + bits: usize, +} +impl Hie { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hie { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Software Interrupt + #[inline] + pub fn vssie(&self) -> bool { + self.bits.get_bit(2) + } + #[inline] + pub fn set_vssie(&mut self, val: bool) { + self.bits.set_bit(2, val); + } + /// Timer Interrupt + #[inline] + pub fn vstie(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_vstie(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// External Interrupt + #[inline] + pub fn vseie(&self) -> bool { + self.bits.get_bit(10) + } + #[inline] + pub fn set_vseie(&mut self, val: bool) { + self.bits.set_bit(10, val); + } + /// Guest External Interrupt + #[inline] + pub fn sgeie(&self) -> bool { + self.bits.get_bit(12) + } + #[inline] + pub fn set_sgeie(&mut self, val: bool) { + self.bits.set_bit(12, val); + } +} +read_csr_as!(Hie, 1540, __read_hie); +write_csr!(1540, __write_hie); +set!(1540, __set_hie); +clear!(1540, __clear_hie); +// bit ops +set_clear_csr!( + ///Software Interrupt + , set_vssie, clear_vssie, 1 << 2); +set_clear_csr!( + ///Timer Interrupt + , set_vstie, clear_vstie, 1 << 6); +set_clear_csr!( + ///External Interrupt + , set_vseie, clear_vseie, 1 << 10); +set_clear_csr!( + ///Guest External Interrupt + , set_sgeie, clear_sgeie, 1 << 12); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/hip.rs b/third-party/riscv/src/register/hypervisorx64/hip.rs new file mode 100644 index 00000000..dd297639 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hip.rs @@ -0,0 +1,77 @@ +//! Hypervisor Interrupt Pending Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hip { + bits: usize, +} +impl Hip { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hip { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Software Interrupt + #[inline] + pub fn vssip(&self) -> bool { + self.bits.get_bit(2) + } + #[inline] + pub fn set_vssip(&mut self, val: bool) { + self.bits.set_bit(2, val); + } + /// Timer Interrupt + #[inline] + pub fn vstip(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_vstip(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// External Interrupt + #[inline] + pub fn vseip(&self) -> bool { + self.bits.get_bit(10) + } + #[inline] + pub fn set_vseip(&mut self, val: bool) { + self.bits.set_bit(10, val); + } + /// Guest External Interrupt + #[inline] + pub fn sgeip(&self) -> bool { + self.bits.get_bit(12) + } + #[inline] + pub fn set_sgeip(&mut self, val: bool) { + self.bits.set_bit(12, val); + } +} +read_csr_as!(Hip, 1604, __read_hip); +write_csr!(1604, __write_hip); +set!(1604, __set_hip); +clear!(1604, __clear_hip); +// bit ops +set_clear_csr!( + ///Software Interrupt + , set_vssip, clear_vssip, 1 << 2); +set_clear_csr!( + ///Timer Interrupt + , set_vstip, clear_vstip, 1 << 6); +set_clear_csr!( + ///External Interrupt + , set_vseip, clear_vseip, 1 << 10); +set_clear_csr!( + ///Guest External Interrupt + , set_sgeip, clear_sgeip, 1 << 12); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/hstatus.rs b/third-party/riscv/src/register/hypervisorx64/hstatus.rs new file mode 100644 index 00000000..386c1a68 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hstatus.rs @@ -0,0 +1,160 @@ +//! HStatus Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hstatus { + bits: usize, +} +impl Hstatus { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hstatus { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Effective XLEN for VM. + #[inline] + pub fn vsxl(&self) -> VsxlValues { + VsxlValues::from(self.bits.get_bits(32..34)) + } + #[inline] + pub fn set_vsxl(&mut self, val: VsxlValues) { + self.bits.set_bits(32..34, val as usize); + } + /// TSR for VM. + #[inline] + pub fn vtsr(&self) -> bool { + self.bits.get_bit(22) + } + #[inline] + pub fn set_vtsr(&mut self, val: bool) { + self.bits.set_bit(22, val); + } + /// TW for VM. + #[inline] + pub fn vtw(&self) -> bool { + self.bits.get_bit(21) + } + #[inline] + pub fn set_vtw(&mut self, val: bool) { + self.bits.set_bit(21, val); + } + /// TVM for VM. + #[inline] + pub fn vtvm(&self) -> bool { + self.bits.get_bit(20) + } + #[inline] + pub fn set_vtvm(&mut self, val: bool) { + self.bits.set_bit(20, val); + } + /// Virtual Guest External Interrupt Number. + #[inline] + pub fn vgein(&self) -> usize { + self.bits.get_bits(12..18) + } + #[inline] + pub fn set_vgein(&mut self, val: usize) { + self.bits.set_bits(12..18, val); + } + /// Hypervisor User mode. + #[inline] + pub fn hu(&self) -> bool { + self.bits.get_bit(9) + } + #[inline] + pub fn set_hu(&mut self, val: bool) { + self.bits.set_bit(9, val); + } + /// Supervisor Previous Virtual Privilege. + #[inline] + pub fn spvp(&self) -> bool { + self.bits.get_bit(8) + } + #[inline] + pub fn set_spvp(&mut self, val: bool) { + self.bits.set_bit(8, val); + } + /// Supervisor Previous Virtualization mode. + #[inline] + pub fn spv(&self) -> bool { + self.bits.get_bit(7) + } + #[inline] + pub fn set_spv(&mut self, val: bool) { + self.bits.set_bit(7, val); + } + /// Guest Virtual Address. + #[inline] + pub fn gva(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_gva(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// VS access endianness. + #[inline] + pub fn vsbe(&self) -> bool { + self.bits.get_bit(5) + } + #[inline] + pub fn set_vsbe(&mut self, val: bool) { + self.bits.set_bit(5, val); + } +} +read_csr_as!(Hstatus, 1536, __read_hstatus); +write_csr!(1536, __write_hstatus); +set!(1536, __set_hstatus); +clear!(1536, __clear_hstatus); +// bit ops +set_clear_csr!( + ///TSR for VM. + , set_vtsr, clear_vtsr, 1 << 22); +set_clear_csr!( + ///TW for VM. + , set_vtw, clear_vtw, 1 << 21); +set_clear_csr!( + ///TVM for VM. + , set_vtvm, clear_vtvm, 1 << 20); +set_clear_csr!( + ///Hypervisor User mode. + , set_hu, clear_hu, 1 << 9); +set_clear_csr!( + ///Supervisor Previous Virtual Privilege. + , set_spvp, clear_spvp, 1 << 8); +set_clear_csr!( + ///Supervisor Previous Virtualization mode. + , set_spv, clear_spv, 1 << 7); +set_clear_csr!( + ///Guest Virtual Address. + , set_gva, clear_gva, 1 << 6); +set_clear_csr!( + ///VS access endianness. + , set_vsbe, clear_vsbe, 1 << 5); + +// enums +#[derive(Copy, Clone, Debug)] +#[repr(usize)] +pub enum VsxlValues { + Vsxl32 = 1, + Vsxl64 = 2, + Vsxl128 = 3, +} +impl VsxlValues { + fn from(x: usize) -> Self { + match x { + 1 => Self::Vsxl32, + 2 => Self::Vsxl64, + 3 => Self::Vsxl128, + _ => unreachable!(), + } + } +} diff --git a/third-party/riscv/src/register/hypervisorx64/htimedelta.rs b/third-party/riscv/src/register/hypervisorx64/htimedelta.rs new file mode 100644 index 00000000..c3874b22 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/htimedelta.rs @@ -0,0 +1,4 @@ +//! Hypervisor Time Delta Register. +read_composite_csr!(super::htimedeltah::read(), read()); +read_csr_as_usize!(1541, __read_htimedelta); +write_csr_as_usize!(1541, __write_htimedelta); diff --git a/third-party/riscv/src/register/hypervisorx64/htimedeltah.rs b/third-party/riscv/src/register/hypervisorx64/htimedeltah.rs new file mode 100644 index 00000000..8d7d2188 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/htimedeltah.rs @@ -0,0 +1,3 @@ +//! Hypervisor Time Delta Register. +read_csr_as_usize!(1557, __read_htimedeltah); +write_csr_as_usize!(1557, __write_htimedeltah); diff --git a/third-party/riscv/src/register/hypervisorx64/htinst.rs b/third-party/riscv/src/register/hypervisorx64/htinst.rs new file mode 100644 index 00000000..0619ccb5 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/htinst.rs @@ -0,0 +1,3 @@ +//! Hypervisor Trap Instruction Register. +read_csr_as_usize!(1610, __read_htinst); +write_csr_as_usize!(1610, __write_htinst); diff --git a/third-party/riscv/src/register/hypervisorx64/htval.rs b/third-party/riscv/src/register/hypervisorx64/htval.rs new file mode 100644 index 00000000..89694e4c --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/htval.rs @@ -0,0 +1,3 @@ +//! Hypervisor Trap Value Register. +read_csr_as_usize!(1603, __read_htval); +write_csr_as_usize!(1603, __write_htval); diff --git a/third-party/riscv/src/register/hypervisorx64/hvip.rs b/third-party/riscv/src/register/hypervisorx64/hvip.rs new file mode 100644 index 00000000..fcfb8c31 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/hvip.rs @@ -0,0 +1,65 @@ +//! Hypervisor Virtual Interrupt Pending Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Hvip { + bits: usize, +} +impl Hvip { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Hvip { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Software Interrupt + #[inline] + pub fn vssip(&self) -> bool { + self.bits.get_bit(2) + } + #[inline] + pub fn set_vssip(&mut self, val: bool) { + self.bits.set_bit(2, val); + } + /// Timer Interrupt + #[inline] + pub fn vstip(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_vstip(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// External Interrupt + #[inline] + pub fn vseip(&self) -> bool { + self.bits.get_bit(10) + } + #[inline] + pub fn set_vseip(&mut self, val: bool) { + self.bits.set_bit(10, val); + } +} +read_csr_as!(Hvip, 1605, __read_hvip); +write_csr!(1605, __write_hvip); +set!(1605, __set_hvip); +clear!(1605, __clear_hvip); +// bit ops +set_clear_csr!( + ///Software Interrupt + , set_vssip, clear_vssip, 1 << 2); +set_clear_csr!( + ///Timer Interrupt + , set_vstip, clear_vstip, 1 << 6); +set_clear_csr!( + ///External Interrupt + , set_vseip, clear_vseip, 1 << 10); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/mod.rs b/third-party/riscv/src/register/hypervisorx64/mod.rs new file mode 100644 index 00000000..06706b12 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/mod.rs @@ -0,0 +1,23 @@ +pub mod hcounteren; +pub mod hedeleg; +pub mod hgatp; +pub mod hgeie; +pub mod hgeip; +pub mod hideleg; +pub mod hie; +pub mod hip; +pub mod hstatus; +pub mod htimedelta; +pub mod htimedeltah; +pub mod htinst; +pub mod htval; +pub mod hvip; +pub mod vsatp; +pub mod vscause; +pub mod vsepc; +pub mod vsie; +pub mod vsip; +pub mod vsscratch; +pub mod vsstatus; +pub mod vstval; +pub mod vstvec; diff --git a/third-party/riscv/src/register/hypervisorx64/vsatp.rs b/third-party/riscv/src/register/hypervisorx64/vsatp.rs new file mode 100644 index 00000000..0781acce --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vsatp.rs @@ -0,0 +1,73 @@ +//! Virtual Supervisor Guest Address Translation and Protection Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Vsatp { + bits: usize, +} +impl Vsatp { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Vsatp { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Guest address translation mode. + #[inline] + pub fn mode(&self) -> HgatpValues { + HgatpValues::from(self.bits.get_bits(60..64)) + } + #[inline] + pub fn set_mode(&mut self, val: HgatpValues) { + self.bits.set_bits(60..64, val as usize); + } + /// ASID. + #[inline] + pub fn asid(&self) -> usize { + self.bits.get_bits(44..60) + } + #[inline] + pub fn set_asid(&mut self, val: usize) { + self.bits.set_bits(44..60, val); + } + /// Physical Page Number for root page table. + #[inline] + pub fn ppn(&self) -> usize { + self.bits.get_bits(0..44) + } + #[inline] + pub fn set_ppn(&mut self, val: usize) { + self.bits.set_bits(0..44, val); + } +} +read_csr_as!(Vsatp, 640, __read_vsatp); +write_csr!(640, __write_vsatp); +set!(640, __set_vsatp); +clear!(640, __clear_vsatp); +// bit ops + +// enums +#[derive(Copy, Clone, Debug)] +#[repr(usize)] +pub enum HgatpValues { + Bare = 0, + Sv39x4 = 8, + Sv48x4 = 9, +} +impl HgatpValues { + fn from(x: usize) -> Self { + match x { + 0 => Self::Bare, + 8 => Self::Sv39x4, + 9 => Self::Sv48x4, + _ => unreachable!(), + } + } +} diff --git a/third-party/riscv/src/register/hypervisorx64/vscause.rs b/third-party/riscv/src/register/hypervisorx64/vscause.rs new file mode 100644 index 00000000..cab545f8 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vscause.rs @@ -0,0 +1,50 @@ +//! Virtual Supervisor Cause Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Vscause { + bits: usize, +} +impl Vscause { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Vscause { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Is cause interrupt. + #[inline] + pub fn interrupt(&self) -> bool { + self.bits.get_bit(63) + } + #[inline] + pub fn set_interrupt(&mut self, val: bool) { + self.bits.set_bit(63, val); + } + /// Exception code + #[inline] + pub fn code(&self) -> usize { + self.bits.get_bits(0..63) + } + #[inline] + pub fn set_code(&mut self, val: usize) { + self.bits.set_bits(0..63, val); + } +} +read_csr_as!(Vscause, 578, __read_vscause); +write_csr!(578, __write_vscause); +set!(578, __set_vscause); +clear!(578, __clear_vscause); +// bit ops +set_clear_csr!( + ///Is cause interrupt. + , set_interrupt, clear_interrupt, 1 << 63); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/vsepc.rs b/third-party/riscv/src/register/hypervisorx64/vsepc.rs new file mode 100644 index 00000000..c5b56707 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vsepc.rs @@ -0,0 +1,3 @@ +//! Virtual Supervisor Exception Program Counter. +read_csr_as_usize!(577, __read_vsepc); +write_csr_as_usize!(577, __write_vsepc); diff --git a/third-party/riscv/src/register/hypervisorx64/vsie.rs b/third-party/riscv/src/register/hypervisorx64/vsie.rs new file mode 100644 index 00000000..7a8891d8 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vsie.rs @@ -0,0 +1,65 @@ +//! Virtual Supevisor Interrupt Enable Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Vsie { + bits: usize, +} +impl Vsie { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Vsie { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Software Interrupt + #[inline] + pub fn ssie(&self) -> bool { + self.bits.get_bit(1) + } + #[inline] + pub fn set_ssie(&mut self, val: bool) { + self.bits.set_bit(1, val); + } + /// Timer Interrupt + #[inline] + pub fn stie(&self) -> bool { + self.bits.get_bit(5) + } + #[inline] + pub fn set_stie(&mut self, val: bool) { + self.bits.set_bit(5, val); + } + /// External Interrupt + #[inline] + pub fn seie(&self) -> bool { + self.bits.get_bit(9) + } + #[inline] + pub fn set_seie(&mut self, val: bool) { + self.bits.set_bit(9, val); + } +} +read_csr_as!(Vsie, 516, __read_vsie); +write_csr!(516, __write_vsie); +set!(516, __set_vsie); +clear!(516, __clear_vsie); +// bit ops +set_clear_csr!( + ///Software Interrupt + , set_ssie, clear_ssie, 1 << 1); +set_clear_csr!( + ///Timer Interrupt + , set_stie, clear_stie, 1 << 5); +set_clear_csr!( + ///External Interrupt + , set_seie, clear_seie, 1 << 9); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/vsip.rs b/third-party/riscv/src/register/hypervisorx64/vsip.rs new file mode 100644 index 00000000..0989e798 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vsip.rs @@ -0,0 +1,65 @@ +//! Virtual Supevisor Interrupt Pending Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Vsip { + bits: usize, +} +impl Vsip { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Vsip { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// Software Interrupt + #[inline] + pub fn ssip(&self) -> bool { + self.bits.get_bit(1) + } + #[inline] + pub fn set_ssip(&mut self, val: bool) { + self.bits.set_bit(1, val); + } + /// Timer Interrupt + #[inline] + pub fn stip(&self) -> bool { + self.bits.get_bit(5) + } + #[inline] + pub fn set_stip(&mut self, val: bool) { + self.bits.set_bit(5, val); + } + /// External Interrupt + #[inline] + pub fn seip(&self) -> bool { + self.bits.get_bit(9) + } + #[inline] + pub fn set_seip(&mut self, val: bool) { + self.bits.set_bit(9, val); + } +} +read_csr_as!(Vsip, 580, __read_vsip); +write_csr!(580, __write_vsip); +set!(580, __set_vsip); +clear!(580, __clear_vsip); +// bit ops +set_clear_csr!( + ///Software Interrupt + , set_ssip, clear_ssip, 1 << 1); +set_clear_csr!( + ///Timer Interrupt + , set_stip, clear_stip, 1 << 5); +set_clear_csr!( + ///External Interrupt + , set_seip, clear_seip, 1 << 9); + +// enums diff --git a/third-party/riscv/src/register/hypervisorx64/vsscratch.rs b/third-party/riscv/src/register/hypervisorx64/vsscratch.rs new file mode 100644 index 00000000..e297575f --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vsscratch.rs @@ -0,0 +1,3 @@ +//! Virtual Supervisor Scratch Register. +read_csr_as_usize!(576, __read_vsscratch); +write_csr_as_usize!(576, __write_vsscratch); diff --git a/third-party/riscv/src/register/hypervisorx64/vsstatus.rs b/third-party/riscv/src/register/hypervisorx64/vsstatus.rs new file mode 100644 index 00000000..c2585b87 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vsstatus.rs @@ -0,0 +1,154 @@ +//! Hypervisor Guest External Interrupt Pending Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Vsstatus { + bits: usize, +} +impl Vsstatus { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Vsstatus { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// + #[inline] + pub fn sd(&self) -> usize { + self.bits.get_bits(60..64) + } + #[inline] + pub fn set_sd(&mut self, val: usize) { + self.bits.set_bits(60..64, val); + } + /// Effective User XLEN. + #[inline] + pub fn uxl(&self) -> UxlValues { + UxlValues::from(self.bits.get_bits(32..34)) + } + #[inline] + pub fn set_uxl(&mut self, val: UxlValues) { + self.bits.set_bits(32..34, val as usize); + } + /// + #[inline] + pub fn mxr(&self) -> bool { + self.bits.get_bit(19) + } + #[inline] + pub fn set_mxr(&mut self, val: bool) { + self.bits.set_bit(19, val); + } + /// + #[inline] + pub fn sum(&self) -> bool { + self.bits.get_bit(18) + } + #[inline] + pub fn set_sum(&mut self, val: bool) { + self.bits.set_bit(18, val); + } + /// + #[inline] + pub fn xs(&self) -> usize { + self.bits.get_bits(15..17) + } + #[inline] + pub fn set_xs(&mut self, val: usize) { + self.bits.set_bits(15..17, val); + } + /// + #[inline] + pub fn fs(&self) -> usize { + self.bits.get_bits(13..15) + } + #[inline] + pub fn set_fs(&mut self, val: usize) { + self.bits.set_bits(13..15, val); + } + /// + #[inline] + pub fn spp(&self) -> bool { + self.bits.get_bit(8) + } + #[inline] + pub fn set_spp(&mut self, val: bool) { + self.bits.set_bit(8, val); + } + /// + #[inline] + pub fn ube(&self) -> bool { + self.bits.get_bit(6) + } + #[inline] + pub fn set_ube(&mut self, val: bool) { + self.bits.set_bit(6, val); + } + /// + #[inline] + pub fn spie(&self) -> bool { + self.bits.get_bit(5) + } + #[inline] + pub fn set_spie(&mut self, val: bool) { + self.bits.set_bit(5, val); + } + /// + #[inline] + pub fn sie(&self) -> bool { + self.bits.get_bit(1) + } + #[inline] + pub fn set_sie(&mut self, val: bool) { + self.bits.set_bit(1, val); + } +} +read_csr_as!(Vsstatus, 512, __read_vsstatus); +write_csr!(512, __write_vsstatus); +set!(512, __set_vsstatus); +clear!(512, __clear_vsstatus); +// bit ops +set_clear_csr!( + /// + , set_mxr, clear_mxr, 1 << 19); +set_clear_csr!( + /// + , set_sum, clear_sum, 1 << 18); +set_clear_csr!( + /// + , set_spp, clear_spp, 1 << 8); +set_clear_csr!( + /// + , set_ube, clear_ube, 1 << 6); +set_clear_csr!( + /// + , set_spie, clear_spie, 1 << 5); +set_clear_csr!( + /// + , set_sie, clear_sie, 1 << 1); + +// enums +#[derive(Copy, Clone, Debug)] +#[repr(usize)] +pub enum UxlValues { + Uxl32 = 1, + Uxl64 = 2, + Uxl128 = 3, +} +impl UxlValues { + fn from(x: usize) -> Self { + match x { + 1 => Self::Uxl32, + 2 => Self::Uxl64, + 3 => Self::Uxl128, + _ => unreachable!(), + } + } +} diff --git a/third-party/riscv/src/register/hypervisorx64/vstval.rs b/third-party/riscv/src/register/hypervisorx64/vstval.rs new file mode 100644 index 00000000..95866469 --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vstval.rs @@ -0,0 +1,3 @@ +//! Virtual Supervisor Trap Value Register. +read_csr_as_usize!(579, __read_vstval); +write_csr_as_usize!(579, __write_vstval); diff --git a/third-party/riscv/src/register/hypervisorx64/vstvec.rs b/third-party/riscv/src/register/hypervisorx64/vstvec.rs new file mode 100644 index 00000000..adece54c --- /dev/null +++ b/third-party/riscv/src/register/hypervisorx64/vstvec.rs @@ -0,0 +1,47 @@ +//! Virtual Supervisor Trap Vector Base Address Register. + +use bit_field::BitField; + +#[derive(Copy, Clone, Debug)] +pub struct Vstvec { + bits: usize, +} +impl Vstvec { + #[inline] + pub fn bits(&self) -> usize { + return self.bits; + } + #[inline] + pub fn from_bits(x: usize) -> Self { + return Vstvec { bits: x }; + } + #[inline] + pub unsafe fn write(&self) { + _write(self.bits); + } + /// + #[inline] + pub fn base(&self) -> usize { + self.bits.get_bits(2..64) + } + #[inline] + pub fn set_base(&mut self, val: usize) { + self.bits.set_bits(2..64, val); + } + /// + #[inline] + pub fn mode(&self) -> usize { + self.bits.get_bits(0..2) + } + #[inline] + pub fn set_mode(&mut self, val: usize) { + self.bits.set_bits(0..2, val); + } +} +read_csr_as!(Vstvec, 517, __read_vstvec); +write_csr!(517, __write_vstvec); +set!(517, __set_vstvec); +clear!(517, __clear_vstvec); +// bit ops + +// enums diff --git a/third-party/riscv/src/register/macros.rs b/third-party/riscv/src/register/macros.rs new file mode 100644 index 00000000..543f7092 --- /dev/null +++ b/third-party/riscv/src/register/macros.rs @@ -0,0 +1,273 @@ +macro_rules! read_csr { + ($csr_number:expr, $asm_fn: ident) => { + /// Reads the CSR + #[inline] + unsafe fn _read() -> usize { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => { + let r: usize; + core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number); + r + } + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn() -> usize; + } + + $asm_fn() + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! read_csr_rv32 { + ($csr_number:expr, $asm_fn: ident) => { + /// Reads the CSR + #[inline] + unsafe fn _read() -> usize { + match () { + #[cfg(all(riscv32, feature = "inline-asm"))] + () => { + let r: usize; + core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number); + r + } + + #[cfg(all(riscv32, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn() -> usize; + } + + $asm_fn() + } + + #[cfg(not(riscv32))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! read_csr_as { + ($register:ident, $csr_number:expr, $asm_fn: ident) => { + read_csr!($csr_number, $asm_fn); + + /// Reads the CSR + #[inline] + pub fn read() -> $register { + $register { + bits: unsafe { _read() }, + } + } + }; +} + +macro_rules! read_csr_as_usize { + ($csr_number:expr, $asm_fn: ident) => { + read_csr!($csr_number, $asm_fn); + + /// Reads the CSR + #[inline] + pub fn read() -> usize { + unsafe { _read() } + } + }; +} + +macro_rules! read_csr_as_usize_rv32 { + ($csr_number:expr, $asm_fn: ident) => { + read_csr_rv32!($csr_number, $asm_fn); + + /// Reads the CSR + #[inline] + pub fn read() -> usize { + unsafe { _read() } + } + }; +} + +macro_rules! write_csr { + ($csr_number:expr, $asm_fn: ident) => { + /// Writes the CSR + #[inline] + #[allow(unused_variables)] + unsafe fn _write(bits: usize) { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number), + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(bits: usize); + } + + $asm_fn(bits); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! write_csr_rv32 { + ($csr_number:expr, $asm_fn: ident) => { + /// Writes the CSR + #[inline] + #[allow(unused_variables)] + unsafe fn _write(bits: usize) { + match () { + #[cfg(all(riscv32, feature = "inline-asm"))] + () => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number), + + #[cfg(all(riscv32, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(bits: usize); + } + + $asm_fn(bits); + } + + #[cfg(not(riscv32))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! write_csr_as_usize { + ($csr_number:expr, $asm_fn: ident) => { + write_csr!($csr_number, $asm_fn); + + /// Writes the CSR + #[inline] + pub fn write(bits: usize) { + unsafe { _write(bits) } + } + }; +} + +macro_rules! write_csr_as_usize_rv32 { + ($csr_number:expr, $asm_fn: ident) => { + write_csr_rv32!($csr_number, $asm_fn); + + /// Writes the CSR + #[inline] + pub fn write(bits: usize) { + unsafe { _write(bits) } + } + }; +} + +macro_rules! set { + ($csr_number:expr, $asm_fn: ident) => { + /// Set the CSR + #[inline] + #[allow(unused_variables)] + unsafe fn _set(bits: usize) { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => core::arch::asm!("csrrs x0, {1}, {0}", in(reg) bits, const $csr_number), + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(bits: usize); + } + + $asm_fn(bits); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! clear { + ($csr_number:expr, $asm_fn: ident) => { + /// Clear the CSR + #[inline] + #[allow(unused_variables)] + unsafe fn _clear(bits: usize) { + match () { + #[cfg(all(riscv, feature = "inline-asm"))] + () => core::arch::asm!("csrrc x0, {1}, {0}", in(reg) bits, const $csr_number), + + #[cfg(all(riscv, not(feature = "inline-asm")))] + () => { + extern "C" { + fn $asm_fn(bits: usize); + } + + $asm_fn(bits); + } + + #[cfg(not(riscv))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! set_csr { + ($(#[$attr:meta])*, $set_field:ident, $e:expr) => { + $(#[$attr])* + #[inline] + pub unsafe fn $set_field() { + _set($e); + } + }; +} + +macro_rules! clear_csr { + ($(#[$attr:meta])*, $clear_field:ident, $e:expr) => { + $(#[$attr])* + #[inline] + pub unsafe fn $clear_field() { + _clear($e); + } + }; +} + +macro_rules! set_clear_csr { + ($(#[$attr:meta])*, $set_field:ident, $clear_field:ident, $e:expr) => { + set_csr!($(#[$attr])*, $set_field, $e); + clear_csr!($(#[$attr])*, $clear_field, $e); + } +} + +macro_rules! read_composite_csr { + ($hi:expr, $lo:expr) => { + /// Reads the CSR as a 64-bit value + #[inline] + pub fn read64() -> u64 { + match () { + #[cfg(riscv32)] + () => loop { + let hi = $hi; + let lo = $lo; + if hi == $hi { + return ((hi as u64) << 32) | lo as u64; + } + }, + + #[cfg(not(riscv32))] + () => $lo as u64, + } + } + }; +} + diff --git a/third-party/riscv/src/register/marchid.rs b/third-party/riscv/src/register/marchid.rs new file mode 100644 index 00000000..a5e3fb9c --- /dev/null +++ b/third-party/riscv/src/register/marchid.rs @@ -0,0 +1,27 @@ +//! marchid register + +use core::num::NonZeroUsize; + +/// marchid register +#[derive(Clone, Copy, Debug)] +pub struct Marchid { + bits: NonZeroUsize, +} + +impl Marchid { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits.get() + } +} + +read_csr!(0xF11, __read_marchid); + +/// Reads the CSR +#[inline] +pub fn read() -> Option { + let r = unsafe { _read() }; + // When marchid is hardwired to zero it means that the marchid + // csr isn't implemented. + NonZeroUsize::new(r).map(|bits| Marchid { bits }) +} diff --git a/third-party/riscv/src/register/mcause.rs b/third-party/riscv/src/register/mcause.rs new file mode 100644 index 00000000..068266b2 --- /dev/null +++ b/third-party/riscv/src/register/mcause.rs @@ -0,0 +1,138 @@ +//! mcause register + +/// mcause register +#[derive(Clone, Copy, Debug)] +pub struct Mcause { + bits: usize, +} + +/// Trap Cause +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum Trap { + Interrupt(Interrupt), + Exception(Exception), +} + +/// Interrupt +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum Interrupt { + UserSoft, + SupervisorSoft, + MachineSoft, + UserTimer, + SupervisorTimer, + MachineTimer, + UserExternal, + SupervisorExternal, + MachineExternal, + Unknown, +} + +/// Exception +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum Exception { + InstructionMisaligned, + InstructionFault, + IllegalInstruction, + Breakpoint, + LoadMisaligned, + LoadFault, + StoreMisaligned, + StoreFault, + UserEnvCall, + SupervisorEnvCall, + MachineEnvCall, + InstructionPageFault, + LoadPageFault, + StorePageFault, + Unknown, +} + +impl Interrupt { + pub fn from(nr: usize) -> Self { + match nr { + 0 => Interrupt::UserSoft, + 1 => Interrupt::SupervisorSoft, + 3 => Interrupt::MachineSoft, + 4 => Interrupt::UserTimer, + 5 => Interrupt::SupervisorTimer, + 7 => Interrupt::MachineTimer, + 8 => Interrupt::UserExternal, + 9 => Interrupt::SupervisorExternal, + 11 => Interrupt::MachineExternal, + _ => Interrupt::Unknown, + } + } +} + +impl Exception { + pub fn from(nr: usize) -> Self { + match nr { + 0 => Exception::InstructionMisaligned, + 1 => Exception::InstructionFault, + 2 => Exception::IllegalInstruction, + 3 => Exception::Breakpoint, + 4 => Exception::LoadMisaligned, + 5 => Exception::LoadFault, + 6 => Exception::StoreMisaligned, + 7 => Exception::StoreFault, + 8 => Exception::UserEnvCall, + 9 => Exception::SupervisorEnvCall, + 11 => Exception::MachineEnvCall, + 12 => Exception::InstructionPageFault, + 13 => Exception::LoadPageFault, + 15 => Exception::StorePageFault, + _ => Exception::Unknown, + } + } +} +impl Mcause { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// Returns the code field + pub fn code(&self) -> usize { + match () { + #[cfg(target_pointer_width = "32")] + () => self.bits & !(1 << 31), + #[cfg(target_pointer_width = "64")] + () => self.bits & !(1 << 63), + #[cfg(target_pointer_width = "128")] + () => self.bits & !(1 << 127), + } + } + + /// Trap Cause + #[inline] + pub fn cause(&self) -> Trap { + if self.is_interrupt() { + Trap::Interrupt(Interrupt::from(self.code())) + } else { + Trap::Exception(Exception::from(self.code())) + } + } + + /// Is trap cause an interrupt. + #[inline] + pub fn is_interrupt(&self) -> bool { + match () { + #[cfg(target_pointer_width = "32")] + () => self.bits & (1 << 31) == 1 << 31, + #[cfg(target_pointer_width = "64")] + () => self.bits & (1 << 63) == 1 << 63, + #[cfg(target_pointer_width = "128")] + () => self.bits & (1 << 127) == 1 << 127, + } + } + + /// Is trap cause an exception. + #[inline] + pub fn is_exception(&self) -> bool { + !self.is_interrupt() + } +} + +read_csr_as!(Mcause, 0x342, __read_mcause); diff --git a/third-party/riscv/src/register/mcycle.rs b/third-party/riscv/src/register/mcycle.rs new file mode 100644 index 00000000..95d172b2 --- /dev/null +++ b/third-party/riscv/src/register/mcycle.rs @@ -0,0 +1,4 @@ +//! mcycle register + +read_csr_as_usize!(0xB00, __read_mcycle); +read_composite_csr!(super::mcycleh::read(), read()); diff --git a/third-party/riscv/src/register/mcycleh.rs b/third-party/riscv/src/register/mcycleh.rs new file mode 100644 index 00000000..784dca4f --- /dev/null +++ b/third-party/riscv/src/register/mcycleh.rs @@ -0,0 +1,3 @@ +//! mcycleh register + +read_csr_as_usize_rv32!(0xB80, __read_mcycleh); diff --git a/third-party/riscv/src/register/medeleg.rs b/third-party/riscv/src/register/medeleg.rs new file mode 100644 index 00000000..6b86641d --- /dev/null +++ b/third-party/riscv/src/register/medeleg.rs @@ -0,0 +1,148 @@ +//! medeleg register + +use bit_field::BitField; + +/// medeleg register +#[derive(Clone, Copy, Debug)] +pub struct Medeleg { + bits: usize, +} + +impl Medeleg { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// Instruction Address Misaligned Delegate + #[inline] + pub fn instruction_misaligned(&self) -> bool { + self.bits.get_bit(0) + } + + /// Instruction Access Fault Delegate + #[inline] + pub fn instruction_fault(&self) -> bool { + self.bits.get_bit(1) + } + + /// Illegal Instruction Delegate + #[inline] + pub fn illegal_instruction(&self) -> bool { + self.bits.get_bit(2) + } + + /// Breakpoint Delegate + #[inline] + pub fn breakpoint(&self) -> bool { + self.bits.get_bit(3) + } + + /// Load Address Misaligned Delegate + #[inline] + pub fn load_misaligned(&self) -> bool { + self.bits.get_bit(4) + } + + /// Load Access Fault Delegate + #[inline] + pub fn load_fault(&self) -> bool { + self.bits.get_bit(5) + } + + /// Store/AMO Address Misaligned Delegate + #[inline] + pub fn store_misaligned(&self) -> bool { + self.bits.get_bit(6) + } + + /// Store/AMO Access Fault Delegate + #[inline] + pub fn store_fault(&self) -> bool { + self.bits.get_bit(7) + } + + /// Environment Call from U-mode Delegate + #[inline] + pub fn user_env_call(&self) -> bool { + self.bits.get_bit(8) + } + + /// Environment Call from S-mode Delegate + #[inline] + pub fn supervisor_env_call(&self) -> bool { + self.bits.get_bit(9) + } + + /// Environment Call from M-mode Delegate + #[inline] + pub fn machine_env_call(&self) -> bool { + self.bits.get_bit(11) + } + + /// Instruction Page Fault Delegate + #[inline] + pub fn instruction_page_fault(&self) -> bool { + self.bits.get_bit(12) + } + + /// Load Page Fault Delegate + #[inline] + pub fn load_page_fault(&self) -> bool { + self.bits.get_bit(13) + } + + /// Store/AMO Page Fault Delegate + #[inline] + pub fn store_page_fault(&self) -> bool { + self.bits.get_bit(15) + } +} + +read_csr_as!(Medeleg, 0x302, __read_medeleg); +set!(0x302, __set_medeleg); +clear!(0x302, __clear_medeleg); + +set_clear_csr!( + /// Instruction Address Misaligned Delegate + , set_instruction_misaligned, clear_instruction_misaligned, 1 << 0); +set_clear_csr!( + /// Instruction Access Fault Delegate + , set_instruction_fault, clear_instruction_fault, 1 << 1); +set_clear_csr!( + /// Illegal Instruction Delegate + , set_illegal_instruction, clear_illegal_instruction, 1 << 2); +set_clear_csr!( + /// Breakpoint Delegate + , set_breakpoint, clear_breakpoint, 1 << 3); +set_clear_csr!( + /// Load Address Misaligned Delegate + , set_load_misaligned, clear_load_misaligned, 1 << 4); +set_clear_csr!( + /// Load Access Fault Delegate + , set_load_fault, clear_load_fault, 1 << 5); +set_clear_csr!( + /// Store/AMO Address Misaligned Delegate + , set_store_misaligned, clear_store_misaligned, 1 << 6); +set_clear_csr!( + /// Store/AMO Access fault + , set_store_fault, clear_store_fault, 1 << 7); +set_clear_csr!( + /// Environment Call from U-mode Delegate + , set_user_env_call, clear_user_env_call, 1 << 8); +set_clear_csr!( + /// Environment Call from S-mode Delegate + , set_supervisor_env_call, clear_supervisor_env_call, 1 << 9); +set_clear_csr!( + /// Environment Call from M-mode Delegate + , set_machine_env_call, clear_machine_env_call, 1 << 11); +set_clear_csr!( + /// Instruction Page Fault Delegate + , set_instruction_page_fault, clear_instruction_page_fault, 1 << 12); +set_clear_csr!( + /// Load Page Fault Delegate + , set_load_page_fault, clear_load_page_fault, 1 << 13); +set_clear_csr!( + /// Store/AMO Page Fault Delegate + , set_store_page_fault, clear_store_page_fault, 1 << 15); diff --git a/third-party/riscv/src/register/mepc.rs b/third-party/riscv/src/register/mepc.rs new file mode 100644 index 00000000..160dff56 --- /dev/null +++ b/third-party/riscv/src/register/mepc.rs @@ -0,0 +1,4 @@ +//! mepc register + +read_csr_as_usize!(0x341, __read_mepc); +write_csr_as_usize!(0x341, __write_mepc); diff --git a/third-party/riscv/src/register/mhartid.rs b/third-party/riscv/src/register/mhartid.rs new file mode 100644 index 00000000..39603882 --- /dev/null +++ b/third-party/riscv/src/register/mhartid.rs @@ -0,0 +1,3 @@ +//! mhartid register + +read_csr_as_usize!(0xf14, __read_mhartid); diff --git a/third-party/riscv/src/register/mhpmcounterx.rs b/third-party/riscv/src/register/mhpmcounterx.rs new file mode 100644 index 00000000..df3b6c42 --- /dev/null +++ b/third-party/riscv/src/register/mhpmcounterx.rs @@ -0,0 +1,84 @@ +macro_rules! reg { + ( + $addr:expr, $csrl:ident, $csrh:ident, $readf:ident, $writef:ident + ) => { + /// Machine performance-monitoring counter + pub mod $csrl { + read_csr_as_usize!($addr, $readf); + write_csr_as_usize!($addr, $writef); + read_composite_csr!(super::$csrh::read(), read()); + } + } +} + +macro_rules! regh { + ( + $addr:expr, $csrh:ident, $readf:ident, $writef:ident + ) => { + /// Upper 32 bits of machine performance-monitoring counter (RV32I only) + pub mod $csrh { + read_csr_as_usize_rv32!($addr, $readf); + write_csr_as_usize_rv32!($addr, $writef); + } + } +} + +reg!(0xB03, mhpmcounter3, mhpmcounter3h, __read_mhpmcounter3, __write_mhpmcounter3); +reg!(0xB04, mhpmcounter4, mhpmcounter4h, __read_mhpmcounter4, __write_mhpmcounter4); +reg!(0xB05, mhpmcounter5, mhpmcounter5h, __read_mhpmcounter5, __write_mhpmcounter5); +reg!(0xB06, mhpmcounter6, mhpmcounter6h, __read_mhpmcounter6, __write_mhpmcounter6); +reg!(0xB07, mhpmcounter7, mhpmcounter7h, __read_mhpmcounter7, __write_mhpmcounter7); +reg!(0xB08, mhpmcounter8, mhpmcounter8h, __read_mhpmcounter8, __write_mhpmcounter8); +reg!(0xB09, mhpmcounter9, mhpmcounter9h, __read_mhpmcounter9, __write_mhpmcounter9); +reg!(0xB0A, mhpmcounter10, mhpmcounter10h, __read_mhpmcounter10, __write_mhpmcounter10); +reg!(0xB0B, mhpmcounter11, mhpmcounter11h, __read_mhpmcounter11, __write_mhpmcounter11); +reg!(0xB0C, mhpmcounter12, mhpmcounter12h, __read_mhpmcounter12, __write_mhpmcounter12); +reg!(0xB0D, mhpmcounter13, mhpmcounter13h, __read_mhpmcounter13, __write_mhpmcounter13); +reg!(0xB0E, mhpmcounter14, mhpmcounter14h, __read_mhpmcounter14, __write_mhpmcounter14); +reg!(0xB0F, mhpmcounter15, mhpmcounter15h, __read_mhpmcounter15, __write_mhpmcounter15); +reg!(0xB10, mhpmcounter16, mhpmcounter16h, __read_mhpmcounter16, __write_mhpmcounter16); +reg!(0xB11, mhpmcounter17, mhpmcounter17h, __read_mhpmcounter17, __write_mhpmcounter17); +reg!(0xB12, mhpmcounter18, mhpmcounter18h, __read_mhpmcounter18, __write_mhpmcounter18); +reg!(0xB13, mhpmcounter19, mhpmcounter19h, __read_mhpmcounter19, __write_mhpmcounter19); +reg!(0xB14, mhpmcounter20, mhpmcounter20h, __read_mhpmcounter20, __write_mhpmcounter20); +reg!(0xB15, mhpmcounter21, mhpmcounter21h, __read_mhpmcounter21, __write_mhpmcounter21); +reg!(0xB16, mhpmcounter22, mhpmcounter22h, __read_mhpmcounter22, __write_mhpmcounter22); +reg!(0xB17, mhpmcounter23, mhpmcounter23h, __read_mhpmcounter23, __write_mhpmcounter23); +reg!(0xB18, mhpmcounter24, mhpmcounter24h, __read_mhpmcounter24, __write_mhpmcounter24); +reg!(0xB19, mhpmcounter25, mhpmcounter25h, __read_mhpmcounter25, __write_mhpmcounter25); +reg!(0xB1A, mhpmcounter26, mhpmcounter26h, __read_mhpmcounter26, __write_mhpmcounter26); +reg!(0xB1B, mhpmcounter27, mhpmcounter27h, __read_mhpmcounter27, __write_mhpmcounter27); +reg!(0xB1C, mhpmcounter28, mhpmcounter28h, __read_mhpmcounter28, __write_mhpmcounter28); +reg!(0xB1D, mhpmcounter29, mhpmcounter29h, __read_mhpmcounter29, __write_mhpmcounter29); +reg!(0xB1E, mhpmcounter30, mhpmcounter30h, __read_mhpmcounter30, __write_mhpmcounter30); +reg!(0xB1F, mhpmcounter31, mhpmcounter31h, __read_mhpmcounter31, __write_mhpmcounter31); + +regh!(0xB83, mhpmcounter3h, __read_mhpmcounter3h, __write_mhpmcounter3h); +regh!(0xB84, mhpmcounter4h, __read_mhpmcounter4h, __write_mhpmcounter4h); +regh!(0xB85, mhpmcounter5h, __read_mhpmcounter5h, __write_mhpmcounter5h); +regh!(0xB86, mhpmcounter6h, __read_mhpmcounter6h, __write_mhpmcounter6h); +regh!(0xB87, mhpmcounter7h, __read_mhpmcounter7h, __write_mhpmcounter7h); +regh!(0xB88, mhpmcounter8h, __read_mhpmcounter8h, __write_mhpmcounter8h); +regh!(0xB89, mhpmcounter9h, __read_mhpmcounter9h, __write_mhpmcounter9h); +regh!(0xB8A, mhpmcounter10h, __read_mhpmcounter10h, __write_mhpmcounter10h); +regh!(0xB8B, mhpmcounter11h, __read_mhpmcounter11h, __write_mhpmcounter11h); +regh!(0xB8C, mhpmcounter12h, __read_mhpmcounter12h, __write_mhpmcounter12h); +regh!(0xB8D, mhpmcounter13h, __read_mhpmcounter13h, __write_mhpmcounter13h); +regh!(0xB8E, mhpmcounter14h, __read_mhpmcounter14h, __write_mhpmcounter14h); +regh!(0xB8F, mhpmcounter15h, __read_mhpmcounter15h, __write_mhpmcounter15h); +regh!(0xB90, mhpmcounter16h, __read_mhpmcounter16h, __write_mhpmcounter16h); +regh!(0xB91, mhpmcounter17h, __read_mhpmcounter17h, __write_mhpmcounter17h); +regh!(0xB92, mhpmcounter18h, __read_mhpmcounter18h, __write_mhpmcounter18h); +regh!(0xB93, mhpmcounter19h, __read_mhpmcounter19h, __write_mhpmcounter19h); +regh!(0xB94, mhpmcounter20h, __read_mhpmcounter20h, __write_mhpmcounter20h); +regh!(0xB95, mhpmcounter21h, __read_mhpmcounter21h, __write_mhpmcounter21h); +regh!(0xB96, mhpmcounter22h, __read_mhpmcounter22h, __write_mhpmcounter22h); +regh!(0xB97, mhpmcounter23h, __read_mhpmcounter23h, __write_mhpmcounter23h); +regh!(0xB98, mhpmcounter24h, __read_mhpmcounter24h, __write_mhpmcounter24h); +regh!(0xB99, mhpmcounter25h, __read_mhpmcounter25h, __write_mhpmcounter25h); +regh!(0xB9A, mhpmcounter26h, __read_mhpmcounter26h, __write_mhpmcounter26h); +regh!(0xB9B, mhpmcounter27h, __read_mhpmcounter27h, __write_mhpmcounter27h); +regh!(0xB9C, mhpmcounter28h, __read_mhpmcounter28h, __write_mhpmcounter28h); +regh!(0xB9D, mhpmcounter29h, __read_mhpmcounter29h, __write_mhpmcounter29h); +regh!(0xB9E, mhpmcounter30h, __read_mhpmcounter30h, __write_mhpmcounter30h); +regh!(0xB9F, mhpmcounter31h, __read_mhpmcounter31h, __write_mhpmcounter31h); diff --git a/third-party/riscv/src/register/mhpmeventx.rs b/third-party/riscv/src/register/mhpmeventx.rs new file mode 100644 index 00000000..db7d4b0f --- /dev/null +++ b/third-party/riscv/src/register/mhpmeventx.rs @@ -0,0 +1,41 @@ +macro_rules! reg { + ( + $addr:expr, $csr:ident, $readf:ident, $writef:ident + ) => { + /// Machine performance-monitoring event selector + pub mod $csr { + read_csr_as_usize!($addr, $readf); + write_csr_as_usize!($addr, $writef); + } + }; +} + +reg!(0x323, mhpmevent3, __read_mhpmevent3, __write_mhpmevent3); +reg!(0x324, mhpmevent4, __read_mhpmevent4, __write_mhpmevent4); +reg!(0x325, mhpmevent5, __read_mhpmevent5, __write_mhpmevent5); +reg!(0x326, mhpmevent6, __read_mhpmevent6, __write_mhpmevent6); +reg!(0x327, mhpmevent7, __read_mhpmevent7, __write_mhpmevent7); +reg!(0x328, mhpmevent8, __read_mhpmevent8, __write_mhpmevent8); +reg!(0x329, mhpmevent9, __read_mhpmevent9, __write_mhpmevent9); +reg!(0x32A, mhpmevent10, __read_mhpmevent10, __write_mhpmevent10); +reg!(0x32B, mhpmevent11, __read_mhpmevent11, __write_mhpmevent11); +reg!(0x32C, mhpmevent12, __read_mhpmevent12, __write_mhpmevent12); +reg!(0x32D, mhpmevent13, __read_mhpmevent13, __write_mhpmevent13); +reg!(0x32E, mhpmevent14, __read_mhpmevent14, __write_mhpmevent14); +reg!(0x32F, mhpmevent15, __read_mhpmevent15, __write_mhpmevent15); +reg!(0x330, mhpmevent16, __read_mhpmevent16, __write_mhpmevent16); +reg!(0x331, mhpmevent17, __read_mhpmevent17, __write_mhpmevent17); +reg!(0x332, mhpmevent18, __read_mhpmevent18, __write_mhpmevent18); +reg!(0x333, mhpmevent19, __read_mhpmevent19, __write_mhpmevent19); +reg!(0x334, mhpmevent20, __read_mhpmevent20, __write_mhpmevent20); +reg!(0x335, mhpmevent21, __read_mhpmevent21, __write_mhpmevent21); +reg!(0x336, mhpmevent22, __read_mhpmevent22, __write_mhpmevent22); +reg!(0x337, mhpmevent23, __read_mhpmevent23, __write_mhpmevent23); +reg!(0x338, mhpmevent24, __read_mhpmevent24, __write_mhpmevent24); +reg!(0x339, mhpmevent25, __read_mhpmevent25, __write_mhpmevent25); +reg!(0x33A, mhpmevent26, __read_mhpmevent26, __write_mhpmevent26); +reg!(0x33B, mhpmevent27, __read_mhpmevent27, __write_mhpmevent27); +reg!(0x33C, mhpmevent28, __read_mhpmevent28, __write_mhpmevent28); +reg!(0x33D, mhpmevent29, __read_mhpmevent29, __write_mhpmevent29); +reg!(0x33E, mhpmevent30, __read_mhpmevent30, __write_mhpmevent30); +reg!(0x33F, mhpmevent31, __read_mhpmevent31, __write_mhpmevent31); diff --git a/third-party/riscv/src/register/mideleg.rs b/third-party/riscv/src/register/mideleg.rs new file mode 100644 index 00000000..207c18eb --- /dev/null +++ b/third-party/riscv/src/register/mideleg.rs @@ -0,0 +1,76 @@ +//! mideleg register + +use bit_field::BitField; + +/// mideleg register +#[derive(Clone, Copy, Debug)] +pub struct Mideleg { + bits: usize, +} + +impl Mideleg { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Delegate + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Software Interrupt Delegate + #[inline] + pub fn ssoft(&self) -> bool { + self.bits.get_bit(1) + } + + /// User Timer Interrupt Delegate + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Timer Interrupt Delegate + #[inline] + pub fn stimer(&self) -> bool { + self.bits.get_bit(5) + } + + /// User External Interrupt Delegate + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } + + /// Supervisor External Interrupt Delegate + #[inline] + pub fn sext(&self) -> bool { + self.bits.get_bit(9) + } +} + +read_csr_as!(Mideleg, 0x303, __read_mideleg); +set!(0x303, __set_mideleg); +clear!(0x303, __clear_mideleg); + +set_clear_csr!( + /// User Software Interrupt Delegate + , set_usoft, clear_usoft, 1 << 0); +set_clear_csr!( + /// Supervisor Software Interrupt Delegate + , set_ssoft, clear_ssoft, 1 << 1); +set_clear_csr!( + /// User Timer Interrupt Delegate + , set_utimer, clear_utimer, 1 << 4); +set_clear_csr!( + /// Supervisor Timer Interrupt Delegate + , set_stimer, clear_stimer, 1 << 5); +set_clear_csr!( + /// User External Interrupt Delegate + , set_uext, clear_uext, 1 << 8); +set_clear_csr!( + /// Supervisor External Interrupt Delegate + , set_sext, clear_sext, 1 << 9); diff --git a/third-party/riscv/src/register/mie.rs b/third-party/riscv/src/register/mie.rs new file mode 100644 index 00000000..121a5b5b --- /dev/null +++ b/third-party/riscv/src/register/mie.rs @@ -0,0 +1,103 @@ +//! mie register + +use bit_field::BitField; + +/// mie register +#[derive(Clone, Copy, Debug)] +pub struct Mie { + bits: usize, +} + +impl Mie { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Enable + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Software Interrupt Enable + #[inline] + pub fn ssoft(&self) -> bool { + self.bits.get_bit(1) + } + + /// Machine Software Interrupt Enable + #[inline] + pub fn msoft(&self) -> bool { + self.bits.get_bit(3) + } + + /// User Timer Interrupt Enable + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Timer Interrupt Enable + #[inline] + pub fn stimer(&self) -> bool { + self.bits.get_bit(5) + } + + /// Machine Timer Interrupt Enable + #[inline] + pub fn mtimer(&self) -> bool { + self.bits.get_bit(7) + } + + /// User External Interrupt Enable + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } + + /// Supervisor External Interrupt Enable + #[inline] + pub fn sext(&self) -> bool { + self.bits.get_bit(9) + } + + /// Machine External Interrupt Enable + #[inline] + pub fn mext(&self) -> bool { + self.bits.get_bit(11) + } +} + +read_csr_as!(Mie, 0x304, __read_mie); +set!(0x304, __set_mie); +clear!(0x304, __clear_mie); + +set_clear_csr!( + /// User Software Interrupt Enable + , set_usoft, clear_usoft, 1 << 0); +set_clear_csr!( + /// Supervisor Software Interrupt Enable + , set_ssoft, clear_ssoft, 1 << 1); +set_clear_csr!( + /// Machine Software Interrupt Enable + , set_msoft, clear_msoft, 1 << 3); +set_clear_csr!( + /// User Timer Interrupt Enable + , set_utimer, clear_utimer, 1 << 4); +set_clear_csr!( + /// Supervisor Timer Interrupt Enable + , set_stimer, clear_stimer, 1 << 5); +set_clear_csr!( + /// Machine Timer Interrupt Enable + , set_mtimer, clear_mtimer, 1 << 7); +set_clear_csr!( + /// User External Interrupt Enable + , set_uext, clear_uext, 1 << 8); +set_clear_csr!( + /// Supervisor External Interrupt Enable + , set_sext, clear_sext, 1 << 9); +set_clear_csr!( + /// Machine External Interrupt Enable + , set_mext, clear_mext, 1 << 11); diff --git a/third-party/riscv/src/register/mimpid.rs b/third-party/riscv/src/register/mimpid.rs new file mode 100644 index 00000000..39555a87 --- /dev/null +++ b/third-party/riscv/src/register/mimpid.rs @@ -0,0 +1,27 @@ +//! mimpid register + +use core::num::NonZeroUsize; + +/// mimpid register +#[derive(Clone, Copy, Debug)] +pub struct Mimpid { + bits: NonZeroUsize, +} + +impl Mimpid { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits.get() + } +} + +read_csr!(0xF11, __read_mimpid); + +/// Reads the CSR +#[inline] +pub fn read() -> Option { + let r = unsafe { _read() }; + // When mimpid is hardwired to zero it means that the mimpid + // csr isn't implemented. + NonZeroUsize::new(r).map(|bits| Mimpid { bits }) +} diff --git a/third-party/riscv/src/register/minstret.rs b/third-party/riscv/src/register/minstret.rs new file mode 100644 index 00000000..d553dd8f --- /dev/null +++ b/third-party/riscv/src/register/minstret.rs @@ -0,0 +1,4 @@ +//! minstret register + +read_csr_as_usize!(0xB02, __read_minstret); +read_composite_csr!(super::minstreth::read(), read()); diff --git a/third-party/riscv/src/register/minstreth.rs b/third-party/riscv/src/register/minstreth.rs new file mode 100644 index 00000000..56bc54ef --- /dev/null +++ b/third-party/riscv/src/register/minstreth.rs @@ -0,0 +1,3 @@ +//! minstreth register + +read_csr_as_usize_rv32!(0xB82, __read_minstreth); diff --git a/third-party/riscv/src/register/mip.rs b/third-party/riscv/src/register/mip.rs new file mode 100644 index 00000000..1a4cf82c --- /dev/null +++ b/third-party/riscv/src/register/mip.rs @@ -0,0 +1,100 @@ +//! mip register + +use bit_field::BitField; + +/// mip register +#[derive(Clone, Copy, Debug)] +pub struct Mip { + bits: usize, +} + +impl Mip { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Pending + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Software Interrupt Pending + #[inline] + pub fn ssoft(&self) -> bool { + self.bits.get_bit(1) + } + + /// Machine Software Interrupt Pending + #[inline] + pub fn msoft(&self) -> bool { + self.bits.get_bit(3) + } + + /// User Timer Interrupt Pending + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Timer Interrupt Pending + #[inline] + pub fn stimer(&self) -> bool { + self.bits.get_bit(5) + } + + /// Machine Timer Interrupt Pending + #[inline] + pub fn mtimer(&self) -> bool { + self.bits.get_bit(7) + } + + /// User External Interrupt Pending + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } + + /// Supervisor External Interrupt Pending + #[inline] + pub fn sext(&self) -> bool { + self.bits.get_bit(9) + } + + /// Machine External Interrupt Pending + #[inline] + pub fn mext(&self) -> bool { + self.bits.get_bit(11) + } +} + +read_csr_as!(Mip, 0x344, __read_mip); +set!(0x344, __set_mip); +clear!(0x344, __clear_mip); + +set_clear_csr!( + /// User Software Interrupt Pending + , set_usoft, clear_usoft, 1 << 0); +set_clear_csr!( + /// Supervisor Software Interrupt Pending + , set_ssoft, clear_ssoft, 1 << 1); +set_clear_csr!( + /// Machine Software Interrupt Pending + , set_msoft, clear_msoft, 1 << 3); +set_clear_csr!( + /// User Timer Interrupt Pending + , set_utimer, clear_utimer, 1 << 4); +set_clear_csr!( + /// Supervisor Timer Interrupt Pending + , set_stimer, clear_stimer, 1 << 5); +set_clear_csr!( + /// Machine Timer Interrupt Pending + , set_mtimer, clear_mtimer, 1 << 7); +set_clear_csr!( + /// User External Interrupt Pending + , set_uext, clear_uext, 1 << 8); +set_clear_csr!( + /// Supervisor External Interrupt Pending + , set_sext, clear_sext, 1 << 9); diff --git a/third-party/riscv/src/register/misa.rs b/third-party/riscv/src/register/misa.rs new file mode 100644 index 00000000..6c3d860e --- /dev/null +++ b/third-party/riscv/src/register/misa.rs @@ -0,0 +1,60 @@ +//! misa register + +use core::num::NonZeroUsize; + +/// misa register +#[derive(Clone, Copy, Debug)] +pub struct Misa { + bits: NonZeroUsize, +} + +/// Machine XLEN +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum MXL { + XLEN32, + XLEN64, + XLEN128, +} + +impl Misa { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits.get() + } + + /// Returns the machine xlen. + pub fn mxl(&self) -> MXL { + let value = match () { + #[cfg(target_pointer_width = "32")] + () => (self.bits() >> 30) as u8, + #[cfg(target_pointer_width = "64")] + () => (self.bits() >> 62) as u8, + }; + match value { + 1 => MXL::XLEN32, + 2 => MXL::XLEN64, + 3 => MXL::XLEN128, + _ => unreachable!(), + } + } + + /// Returns true when the atomic extension is implemented. + pub fn has_extension(&self, extension: char) -> bool { + let bit = extension as u8 - 65; + if bit > 25 { + return false; + } + self.bits() & (1 << bit) == (1 << bit) + } +} + +read_csr!(0x301, __read_misa); + +/// Reads the CSR +#[inline] +pub fn read() -> Option { + let r = unsafe { _read() }; + // When misa is hardwired to zero it means that the misa csr + // isn't implemented. + NonZeroUsize::new(r).map(|bits| Misa { bits }) +} diff --git a/third-party/riscv/src/register/mod.rs b/third-party/riscv/src/register/mod.rs new file mode 100644 index 00000000..d0804c10 --- /dev/null +++ b/third-party/riscv/src/register/mod.rs @@ -0,0 +1,104 @@ +//! RISC-V CSR's +//! +//! The following registers are not available on 64-bit implementations. +//! +//! - cycleh +//! - timeh +//! - instreth +//! - hpmcounter[3-31]h +//! - mcycleh +//! - minstreth +//! - mhpmcounter[3-31]h + +#[macro_use] +mod macros; + +// User Trap Setup +pub mod uie; +pub mod ustatus; +pub mod utvec; + +// User Trap Handling +pub mod ucause; +pub mod uepc; +pub mod uip; +pub mod uscratch; +pub mod utval; + +// User Floating-Point CSRs +// TODO: frm, fflags +pub mod fcsr; + +// User Counter/Timers +// TODO: cycle[h], instret[h] +pub mod time; +#[rustfmt::skip] // long macro use +mod hpmcounterx; +pub use self::hpmcounterx::*; +pub mod timeh; + +// Supervisor Trap Setup +// TODO: sedeleg, sideleg +pub mod sie; +pub mod sstatus; +pub mod stvec; +// TODO: scounteren + +// Supervisor Trap Handling +pub mod scause; +pub mod sepc; +pub mod sip; +pub mod sscratch; +pub mod stval; + +// Supervisor Protection and Translation +pub mod satp; + +// Machine Information Registers +pub mod marchid; +pub mod mhartid; +pub mod mimpid; +pub mod mvendorid; + +// Machine Trap Setup +pub mod medeleg; +pub mod mideleg; +pub mod mie; +pub mod misa; +pub mod mstatus; +pub mod mtvec; +// TODO: mcounteren + +// Machine Trap Handling +pub mod mcause; +pub mod mepc; +pub mod mip; +pub mod mscratch; +pub mod mtval; + +// Machine Protection and Translation +mod pmpcfgx; +pub use self::pmpcfgx::*; +mod pmpaddrx; +pub use self::pmpaddrx::*; + +// Machine Counter/Timers +pub mod mcycle; +#[rustfmt::skip] // long macro use +mod mhpmcounterx; +pub mod minstret; +pub use self::mhpmcounterx::*; +pub mod mcycleh; +pub mod minstreth; + +// Machine Counter Setup +mod mhpmeventx; +pub use self::mhpmeventx::*; + +// TODO: Debug/Trace Registers (shared with Debug Mode) + +// TODO: Debug Mode Registers + +// Hypervisor Extension Registers +mod hypervisorx64; +pub use self::hypervisorx64::*; diff --git a/third-party/riscv/src/register/mscratch.rs b/third-party/riscv/src/register/mscratch.rs new file mode 100644 index 00000000..c5ef9fec --- /dev/null +++ b/third-party/riscv/src/register/mscratch.rs @@ -0,0 +1,4 @@ +//! mscratch register + +read_csr_as_usize!(0x340, __read_mscratch); +write_csr_as_usize!(0x340, __write_mscratch); diff --git a/third-party/riscv/src/register/mstatus.rs b/third-party/riscv/src/register/mstatus.rs new file mode 100644 index 00000000..97b7b713 --- /dev/null +++ b/third-party/riscv/src/register/mstatus.rs @@ -0,0 +1,214 @@ +//! mstatus register +// TODO: Virtualization, Memory Privilege and Extension Context Fields + +use bit_field::BitField; +use core::mem::size_of; + +/// mstatus register +#[derive(Clone, Copy, Debug)] +pub struct Mstatus { + bits: usize, +} + +/// Additional extension state +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum XS { + /// All off + AllOff = 0, + + /// None dirty or clean, some on + NoneDirtyOrClean = 1, + + /// None dirty, some clean + NoneDirtySomeClean = 2, + + /// Some dirty + SomeDirty = 3, +} + +/// Floating-point extension state +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum FS { + Off = 0, + Initial = 1, + Clean = 2, + Dirty = 3, +} + +/// Machine Previous Privilege Mode +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum MPP { + Machine = 3, + Supervisor = 1, + User = 0, +} + +/// Supervisor Previous Privilege Mode +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum SPP { + Supervisor = 1, + User = 0, +} + +impl Mstatus { + /// User Interrupt Enable + #[inline] + pub fn uie(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Interrupt Enable + #[inline] + pub fn sie(&self) -> bool { + self.bits.get_bit(1) + } + + /// Machine Interrupt Enable + #[inline] + pub fn mie(&self) -> bool { + self.bits.get_bit(3) + } + + /// User Previous Interrupt Enable + #[inline] + pub fn upie(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Previous Interrupt Enable + #[inline] + pub fn spie(&self) -> bool { + self.bits.get_bit(5) + } + + /// Machine Previous Interrupt Enable + #[inline] + pub fn mpie(&self) -> bool { + self.bits.get_bit(7) + } + + /// Supervisor Previous Privilege Mode + #[inline] + pub fn spp(&self) -> SPP { + match self.bits.get_bit(8) { + true => SPP::Supervisor, + false => SPP::User, + } + } + + /// Machine Previous Privilege Mode + #[inline] + pub fn mpp(&self) -> MPP { + match self.bits.get_bits(11..13) { + 0b00 => MPP::User, + 0b01 => MPP::Supervisor, + 0b11 => MPP::Machine, + _ => unreachable!(), + } + } + + #[inline] + pub fn set_mpie(&mut self, val: bool) { + self.bits.set_bit(7, val); + } + + #[inline] + pub fn set_mie(&mut self, val: bool) { + self.bits.set_bit(3, val); + } + + #[inline] + pub fn set_mpp(&mut self, val: MPP) { + self.bits.set_bits(11..13, val as usize); + } + + /// Floating-point extension state + /// + /// Encodes the status of the floating-point unit, + /// including the CSR `fcsr` and floating-point data registers `f0–f31`. + #[inline] + pub fn fs(&self) -> FS { + match self.bits.get_bits(13..15) { + 0b00 => FS::Off, + 0b01 => FS::Initial, + 0b10 => FS::Clean, + 0b11 => FS::Dirty, + _ => unreachable!(), + } + } + + /// Additional extension state + /// + /// Encodes the status of additional user-mode extensions and associated state. + #[inline] + pub fn xs(&self) -> XS { + match self.bits.get_bits(15..17) { + 0b00 => XS::AllOff, + 0b01 => XS::NoneDirtyOrClean, + 0b10 => XS::NoneDirtySomeClean, + 0b11 => XS::SomeDirty, + _ => unreachable!(), + } + } + + /// Whether either the FS field or XS field + /// signals the presence of some dirty state + #[inline] + pub fn sd(&self) -> bool { + self.bits.get_bit(size_of::() * 8 - 1) + } +} + +read_csr_as!(Mstatus, 0x300, __read_mstatus); +write_csr!(0x300, __write_mstatus); +set!(0x300, __set_mstatus); +clear!(0x300, __clear_mstatus); + +set_clear_csr!( + /// User Interrupt Enable + , set_uie, clear_uie, 1 << 0); + +set_clear_csr!( + /// Supervisor Interrupt Enable + , set_sie, clear_sie, 1 << 1); + +set_clear_csr!( + /// Machine Interrupt Enable + , set_mie, clear_mie, 1 << 3); + +set_csr!( + /// User Previous Interrupt Enable + , set_upie, 1 << 4); + +set_csr!( + /// Supervisor Previous Interrupt Enable + , set_spie, 1 << 5); + +set_csr!( + /// Machine Previous Interrupt Enable + , set_mpie, 1 << 7); + +/// Supervisor Previous Privilege Mode +#[inline] +pub unsafe fn set_spp(spp: SPP) { + match spp { + SPP::Supervisor => _set(1 << 8), + SPP::User => _clear(1 << 8), + } +} + +/// Machine Previous Privilege Mode +#[inline] +pub unsafe fn set_mpp(mpp: MPP) { + let mut value = _read(); + value.set_bits(11..13, mpp as usize); + _write(value); +} + +/// Floating-point extension state +#[inline] +pub unsafe fn set_fs(fs: FS) { + let mut value = _read(); + value.set_bits(13..15, fs as usize); + _write(value); +} diff --git a/third-party/riscv/src/register/mtval.rs b/third-party/riscv/src/register/mtval.rs new file mode 100644 index 00000000..2afb7cb6 --- /dev/null +++ b/third-party/riscv/src/register/mtval.rs @@ -0,0 +1,3 @@ +//! mtval register + +read_csr_as_usize!(0x343, __read_mtval); diff --git a/third-party/riscv/src/register/mtvec.rs b/third-party/riscv/src/register/mtvec.rs new file mode 100644 index 00000000..6a069d1c --- /dev/null +++ b/third-party/riscv/src/register/mtvec.rs @@ -0,0 +1,47 @@ +//! mtvec register + +/// mtvec register +#[derive(Clone, Copy, Debug)] +pub struct Mtvec { + bits: usize, +} + +/// Trap mode +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum TrapMode { + Direct = 0, + Vectored = 1, +} + +impl Mtvec { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits + } + + /// Returns the trap-vector base-address + pub fn address(&self) -> usize { + self.bits - (self.bits & 0b11) + } + + /// Returns the trap-vector mode + pub fn trap_mode(&self) -> Option { + let mode = self.bits & 0b11; + match mode { + 0 => Some(TrapMode::Direct), + 1 => Some(TrapMode::Vectored), + _ => None, + } + } +} + +read_csr_as!(Mtvec, 0x305, __read_mtvec); + +write_csr!(0x305, __write_mtvec); + +/// Writes the CSR +#[inline] +pub unsafe fn write(addr: usize, mode: TrapMode) { + let bits = addr + mode as usize; + _write(bits); +} diff --git a/third-party/riscv/src/register/mvendorid.rs b/third-party/riscv/src/register/mvendorid.rs new file mode 100644 index 00000000..9b99d478 --- /dev/null +++ b/third-party/riscv/src/register/mvendorid.rs @@ -0,0 +1,32 @@ +//! mvendorid register + +use core::num::NonZeroUsize; + +/// mvendorid register +#[derive(Clone, Copy, Debug)] +pub struct Mvendorid { + bits: NonZeroUsize, +} + +impl Mvendorid { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits.get() + } + + /// Returns the JEDEC manufacturer ID + pub fn jedec_manufacturer(&self) -> usize { + self.bits() >> 7 + } +} + +read_csr!(0xF11, __read_mvendorid); + +/// Reads the CSR +#[inline] +pub fn read() -> Option { + let r = unsafe { _read() }; + // When mvendorid is hardwired to zero it means that the mvendorid + // csr isn't implemented. + NonZeroUsize::new(r).map(|bits| Mvendorid { bits }) +} diff --git a/third-party/riscv/src/register/pmpaddrx.rs b/third-party/riscv/src/register/pmpaddrx.rs new file mode 100644 index 00000000..cfa43fcb --- /dev/null +++ b/third-party/riscv/src/register/pmpaddrx.rs @@ -0,0 +1,28 @@ +macro_rules! reg { + ( + $addr:expr, $csr:ident, $readf:ident, $writef:ident + ) => { + /// Physical memory protection address register + pub mod $csr { + read_csr_as_usize!($addr, $readf); + write_csr_as_usize!($addr, $writef); + } + }; +} + +reg!(0x3B0, pmpaddr0, __read_pmpaddr0, __write_pmpaddr0); +reg!(0x3B1, pmpaddr1, __read_pmpaddr1, __write_pmpaddr1); +reg!(0x3B2, pmpaddr2, __read_pmpaddr2, __write_pmpaddr2); +reg!(0x3B3, pmpaddr3, __read_pmpaddr3, __write_pmpaddr3); +reg!(0x3B4, pmpaddr4, __read_pmpaddr4, __write_pmpaddr4); +reg!(0x3B5, pmpaddr5, __read_pmpaddr5, __write_pmpaddr5); +reg!(0x3B6, pmpaddr6, __read_pmpaddr6, __write_pmpaddr6); +reg!(0x3B7, pmpaddr7, __read_pmpaddr7, __write_pmpaddr7); +reg!(0x3B8, pmpaddr8, __read_pmpaddr8, __write_pmpaddr8); +reg!(0x3B9, pmpaddr9, __read_pmpaddr9, __write_pmpaddr9); +reg!(0x3BA, pmpaddr10, __read_pmpaddr10, __write_pmpaddr10); +reg!(0x3BB, pmpaddr11, __read_pmpaddr11, __write_pmpaddr11); +reg!(0x3BC, pmpaddr12, __read_pmpaddr12, __write_pmpaddr12); +reg!(0x3BD, pmpaddr13, __read_pmpaddr13, __write_pmpaddr13); +reg!(0x3BE, pmpaddr14, __read_pmpaddr14, __write_pmpaddr14); +reg!(0x3BF, pmpaddr15, __read_pmpaddr15, __write_pmpaddr15); diff --git a/third-party/riscv/src/register/pmpcfgx.rs b/third-party/riscv/src/register/pmpcfgx.rs new file mode 100644 index 00000000..ec27251c --- /dev/null +++ b/third-party/riscv/src/register/pmpcfgx.rs @@ -0,0 +1,23 @@ +/// Physical memory protection configuration +pub mod pmpcfg0 { + read_csr_as_usize!(0x3A0, __read_pmpcfg0); + write_csr_as_usize!(0x3A0, __write_pmpcfg0); +} + +/// Physical memory protection configuration, RV32 only +pub mod pmpcfg1 { + read_csr_as_usize_rv32!(0x3A1, __read_pmpcfg1); + write_csr_as_usize_rv32!(0x3A1, __write_pmpcfg1); +} + +/// Physical memory protection configuration +pub mod pmpcfg2 { + read_csr_as_usize!(0x3A2, __read_pmpcfg2); + write_csr_as_usize!(0x3A2, __write_pmpcfg2); +} + +/// Physical memory protection configuration, RV32 only +pub mod pmpcfg3 { + read_csr_as_usize_rv32!(0x3A3, __read_pmpcfg3); + write_csr_as_usize_rv32!(0x3A3, __write_pmpcfg3); +} diff --git a/third-party/riscv/src/register/satp.rs b/third-party/riscv/src/register/satp.rs new file mode 100644 index 00000000..481c8ca7 --- /dev/null +++ b/third-party/riscv/src/register/satp.rs @@ -0,0 +1,119 @@ +//! satp register + +#[cfg(riscv)] +use addr::Frame; +#[cfg(riscv)] +use bit_field::BitField; + +/// satp register +#[derive(Clone, Copy, Debug)] +pub struct Satp { + bits: usize, +} + +impl Satp { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// Current address-translation scheme + #[inline] + #[cfg(riscv32)] + pub fn mode(&self) -> Mode { + match self.bits.get_bit(31) { + false => Mode::Bare, + true => Mode::Sv32, + } + } + + /// Current address-translation scheme + #[inline] + #[cfg(riscv64)] + pub fn mode(&self) -> Mode { + match self.bits.get_bits(60..64) { + 0 => Mode::Bare, + 8 => Mode::Sv39, + 9 => Mode::Sv48, + 10 => Mode::Sv57, + 11 => Mode::Sv64, + _ => unreachable!(), + } + } + + /// Address space identifier + #[inline] + #[cfg(riscv32)] + pub fn asid(&self) -> usize { + self.bits.get_bits(22..31) + } + + /// Address space identifier + #[inline] + #[cfg(riscv64)] + pub fn asid(&self) -> usize { + self.bits.get_bits(44..60) + } + + /// Physical page number + #[inline] + #[cfg(riscv32)] + pub fn ppn(&self) -> usize { + self.bits.get_bits(0..22) + } + + /// Physical page number + #[inline] + #[cfg(riscv64)] + pub fn ppn(&self) -> usize { + self.bits.get_bits(0..44) + } + + /// Physical frame + #[inline] + #[cfg(riscv)] + pub fn frame(&self) -> Frame { + Frame::of_ppn(self.ppn()) + } +} + +#[cfg(riscv32)] +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum Mode { + Bare = 0, + Sv32 = 1, +} + +#[cfg(riscv64)] +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum Mode { + Bare = 0, + Sv39 = 8, + Sv48 = 9, + Sv57 = 10, + Sv64 = 11, +} + +read_csr_as!(Satp, 0x180, __read_satp); +write_csr_as_usize!(0x180, __write_satp); + +#[inline] +#[cfg(riscv32)] +pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) { + let mut bits = 0usize; + bits.set_bits(31..32, mode as usize); + bits.set_bits(22..31, asid); + bits.set_bits(0..22, ppn); + _write(bits); +} + +#[inline] +#[cfg(riscv64)] +pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) { + let mut bits = 0usize; + bits.set_bits(60..64, mode as usize); + bits.set_bits(44..60, asid); + bits.set_bits(0..44, ppn); + _write(bits); +} diff --git a/third-party/riscv/src/register/scause.rs b/third-party/riscv/src/register/scause.rs new file mode 100644 index 00000000..5117c15d --- /dev/null +++ b/third-party/riscv/src/register/scause.rs @@ -0,0 +1,133 @@ +//! scause register + +use bit_field::BitField; +use core::mem::size_of; + +/// scause register +#[derive(Clone, Copy)] +pub struct Scause { + bits: usize, +} + +/// Trap Cause +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum Trap { + Interrupt(Interrupt), + Exception(Exception), +} + +/// Interrupt +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum Interrupt { + UserSoft, + VirtualSupervisorSoft, + SupervisorSoft, + UserTimer, + VirtualSupervisorTimer, + SupervisorTimer, + UserExternal, + VirtualSupervisorExternal, + SupervisorExternal, + Unknown, +} + +/// Exception +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum Exception { + InstructionMisaligned, + InstructionFault, + IllegalInstruction, + Breakpoint, + LoadFault, + StoreMisaligned, + StoreFault, + UserEnvCall, + VirtualSupervisorEnvCall, + InstructionPageFault, + LoadPageFault, + StorePageFault, + InstructionGuestPageFault, + LoadGuestPageFault, + VirtualInstruction, + StoreGuestPageFault, + Unknown, +} + +impl Interrupt { + pub fn from(nr: usize) -> Self { + match nr { + 0 => Interrupt::UserSoft, + 1 => Interrupt::SupervisorSoft, + 2 => Interrupt::VirtualSupervisorSoft, + 4 => Interrupt::UserTimer, + 5 => Interrupt::SupervisorTimer, + 6 => Interrupt::VirtualSupervisorTimer, + 8 => Interrupt::UserExternal, + 9 => Interrupt::SupervisorExternal, + 10 => Interrupt::VirtualSupervisorExternal, + _ => Interrupt::Unknown, + } + } +} + +impl Exception { + pub fn from(nr: usize) -> Self { + match nr { + 0 => Exception::InstructionMisaligned, + 1 => Exception::InstructionFault, + 2 => Exception::IllegalInstruction, + 3 => Exception::Breakpoint, + 5 => Exception::LoadFault, + 6 => Exception::StoreMisaligned, + 7 => Exception::StoreFault, + 8 => Exception::UserEnvCall, + 10 => Exception::VirtualSupervisorEnvCall, + 12 => Exception::InstructionPageFault, + 13 => Exception::LoadPageFault, + 15 => Exception::StorePageFault, + 20 => Exception::InstructionGuestPageFault, + 21 => Exception::LoadGuestPageFault, + 22 => Exception::VirtualInstruction, + 23 => Exception::StoreGuestPageFault, + _ => Exception::Unknown, + } + } +} + +impl Scause { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// Returns the code field + pub fn code(&self) -> usize { + let bit = 1 << (size_of::() * 8 - 1); + self.bits & !bit + } + + /// Trap Cause + #[inline] + pub fn cause(&self) -> Trap { + if self.is_interrupt() { + Trap::Interrupt(Interrupt::from(self.code())) + } else { + Trap::Exception(Exception::from(self.code())) + } + } + + /// Is trap cause an interrupt. + #[inline] + pub fn is_interrupt(&self) -> bool { + self.bits.get_bit(size_of::() * 8 - 1) + } + + /// Is trap cause an exception. + #[inline] + pub fn is_exception(&self) -> bool { + !self.is_interrupt() + } +} + +read_csr_as!(Scause, 0x142, __read_scause); diff --git a/third-party/riscv/src/register/sepc.rs b/third-party/riscv/src/register/sepc.rs new file mode 100644 index 00000000..aba69dfc --- /dev/null +++ b/third-party/riscv/src/register/sepc.rs @@ -0,0 +1,4 @@ +//! sepc register + +read_csr_as_usize!(0x141, __read_sepc); +write_csr_as_usize!(0x141, __write_sepc); diff --git a/third-party/riscv/src/register/sie.rs b/third-party/riscv/src/register/sie.rs new file mode 100644 index 00000000..b6521109 --- /dev/null +++ b/third-party/riscv/src/register/sie.rs @@ -0,0 +1,76 @@ +//! sie register + +use bit_field::BitField; + +/// sie register +#[derive(Clone, Copy, Debug)] +pub struct Sie { + bits: usize, +} + +impl Sie { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Enable + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Software Interrupt Enable + #[inline] + pub fn ssoft(&self) -> bool { + self.bits.get_bit(1) + } + + /// User Timer Interrupt Enable + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Timer Interrupt Enable + #[inline] + pub fn stimer(&self) -> bool { + self.bits.get_bit(5) + } + + /// User External Interrupt Enable + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } + + /// Supervisor External Interrupt Enable + #[inline] + pub fn sext(&self) -> bool { + self.bits.get_bit(9) + } +} + +read_csr_as!(Sie, 0x104, __read_sie); +set!(0x104, __set_sie); +clear!(0x104, __clear_sie); + +set_clear_csr!( + /// User Software Interrupt Enable + , set_usoft, clear_usoft, 1 << 0); +set_clear_csr!( + /// Supervisor Software Interrupt Enable + , set_ssoft, clear_ssoft, 1 << 1); +set_clear_csr!( + /// User Timer Interrupt Enable + , set_utimer, clear_utimer, 1 << 4); +set_clear_csr!( + /// Supervisor Timer Interrupt Enable + , set_stimer, clear_stimer, 1 << 5); +set_clear_csr!( + /// User External Interrupt Enable + , set_uext, clear_uext, 1 << 8); +set_clear_csr!( + /// Supervisor External Interrupt Enable + , set_sext, clear_sext, 1 << 9); diff --git a/third-party/riscv/src/register/sip.rs b/third-party/riscv/src/register/sip.rs new file mode 100644 index 00000000..f625661a --- /dev/null +++ b/third-party/riscv/src/register/sip.rs @@ -0,0 +1,55 @@ +//! sip register + +use bit_field::BitField; + +/// sip register +#[derive(Clone, Copy, Debug)] +pub struct Sip { + bits: usize, +} + +impl Sip { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Pending + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Software Interrupt Pending + #[inline] + pub fn ssoft(&self) -> bool { + self.bits.get_bit(1) + } + + /// User Timer Interrupt Pending + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Timer Interrupt Pending + #[inline] + pub fn stimer(&self) -> bool { + self.bits.get_bit(5) + } + + /// User External Interrupt Pending + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } + + /// Supervisor External Interrupt Pending + #[inline] + pub fn sext(&self) -> bool { + self.bits.get_bit(9) + } +} + +read_csr_as!(Sip, 0x144, __read_sip); diff --git a/third-party/riscv/src/register/sscratch.rs b/third-party/riscv/src/register/sscratch.rs new file mode 100644 index 00000000..349812c1 --- /dev/null +++ b/third-party/riscv/src/register/sscratch.rs @@ -0,0 +1,4 @@ +//! sscratch register + +read_csr_as_usize!(0x140, __read_sscratch); +write_csr_as_usize!(0x140, __write_sscratch); diff --git a/third-party/riscv/src/register/sstatus.rs b/third-party/riscv/src/register/sstatus.rs new file mode 100644 index 00000000..37a17534 --- /dev/null +++ b/third-party/riscv/src/register/sstatus.rs @@ -0,0 +1,161 @@ +//! sstatus register + +pub use super::mstatus::FS; +use bit_field::BitField; +use core::mem::size_of; + +/// Supervisor Status Register +#[derive(Clone, Copy, Debug)] +pub struct Sstatus { + bits: usize, +} + +/// Supervisor Previous Privilege Mode +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum SPP { + Supervisor = 1, + User = 0, +} + +impl Sstatus { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Interrupt Enable + #[inline] + pub fn uie(&self) -> bool { + self.bits.get_bit(0) + } + + /// Supervisor Interrupt Enable + #[inline] + pub fn sie(&self) -> bool { + self.bits.get_bit(1) + } + + /// User Previous Interrupt Enable + #[inline] + pub fn upie(&self) -> bool { + self.bits.get_bit(4) + } + + /// Supervisor Previous Interrupt Enable + #[inline] + pub fn spie(&self) -> bool { + self.bits.get_bit(5) + } + + /// Supervisor Previous Privilege Mode + #[inline] + pub fn spp(&self) -> SPP { + match self.bits.get_bit(8) { + true => SPP::Supervisor, + false => SPP::User, + } + } + + /// The status of the floating-point unit + #[inline] + pub fn fs(&self) -> FS { + match self.bits.get_bits(13..15) { + 0 => FS::Off, + 1 => FS::Initial, + 2 => FS::Clean, + 3 => FS::Dirty, + _ => unreachable!(), + } + } + + /// The status of additional user-mode extensions + /// and associated state + #[inline] + pub fn xs(&self) -> FS { + match self.bits.get_bits(15..17) { + 0 => FS::Off, + 1 => FS::Initial, + 2 => FS::Clean, + 3 => FS::Dirty, + _ => unreachable!(), + } + } + + /// Permit Supervisor User Memory access + #[inline] + pub fn sum(&self) -> bool { + self.bits.get_bit(18) + } + + /// Make eXecutable Readable + #[inline] + pub fn mxr(&self) -> bool { + self.bits.get_bit(19) + } + + /// Whether either the FS field or XS field + /// signals the presence of some dirty state + #[inline] + pub fn sd(&self) -> bool { + self.bits.get_bit(size_of::() * 8 - 1) + } + + #[inline] + pub fn set_spie(&mut self, val: bool) { + self.bits.set_bit(5, val); + } + + #[inline] + pub fn set_sie(&mut self, val: bool) { + self.bits.set_bit(1, val); + } + + #[inline] + pub fn set_spp(&mut self, val: SPP) { + self.bits.set_bit(8, val == SPP::Supervisor); + } +} + +read_csr_as!(Sstatus, 0x100, __read_sstatus); +write_csr!(0x100, __write_sstatus); +set!(0x100, __set_sstatus); +clear!(0x100, __clear_sstatus); + +set_clear_csr!( + /// User Interrupt Enable + , set_uie, clear_uie, 1 << 0); +set_clear_csr!( + /// Supervisor Interrupt Enable + , set_sie, clear_sie, 1 << 1); +set_csr!( + /// User Previous Interrupt Enable + , set_upie, 1 << 4); +set_csr!( + /// Supervisor Previous Interrupt Enable + , set_spie, 1 << 5); +set_clear_csr!( + /// Make eXecutable Readable + , set_mxr, clear_mxr, 1 << 19); +set_clear_csr!( + /// Permit Supervisor User Memory access + , set_sum, clear_sum, 1 << 18); + +/// Supervisor Previous Privilege Mode +#[inline] +#[cfg(riscv)] +pub unsafe fn set_spp(spp: SPP) { + match spp { + SPP::Supervisor => _set(1 << 8), + SPP::User => _clear(1 << 8), + } +} + +/// The status of the floating-point unit +#[inline] +#[cfg(riscv)] +pub unsafe fn set_fs(fs: FS) { + let mut value = _read(); + value.set_bits(13..15, fs as usize); + _write(value); +} diff --git a/third-party/riscv/src/register/stval.rs b/third-party/riscv/src/register/stval.rs new file mode 100644 index 00000000..722cc194 --- /dev/null +++ b/third-party/riscv/src/register/stval.rs @@ -0,0 +1,3 @@ +//! stval register + +read_csr_as_usize!(0x143, __read_stval); diff --git a/third-party/riscv/src/register/stvec.rs b/third-party/riscv/src/register/stvec.rs new file mode 100644 index 00000000..7df0027e --- /dev/null +++ b/third-party/riscv/src/register/stvec.rs @@ -0,0 +1,40 @@ +//! stvec register + +pub use crate::register::mtvec::TrapMode; + +/// stvec register +#[derive(Clone, Copy, Debug)] +pub struct Stvec { + bits: usize, +} + +impl Stvec { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits + } + + /// Returns the trap-vector base-address + pub fn address(&self) -> usize { + self.bits - (self.bits & 0b11) + } + + /// Returns the trap-vector mode + pub fn trap_mode(&self) -> Option { + let mode = self.bits & 0b11; + match mode { + 0 => Some(TrapMode::Direct), + 1 => Some(TrapMode::Vectored), + _ => None, + } + } +} + +read_csr_as!(Stvec, 0x105, __read_stvec); +write_csr!(0x105, __write_stvec); + +/// Writes the CSR +#[inline] +pub unsafe fn write(addr: usize, mode: TrapMode) { + _write(addr + mode as usize); +} diff --git a/third-party/riscv/src/register/time.rs b/third-party/riscv/src/register/time.rs new file mode 100644 index 00000000..665b5079 --- /dev/null +++ b/third-party/riscv/src/register/time.rs @@ -0,0 +1,4 @@ +//! time register + +read_csr_as_usize!(0xC01, __read_time); +read_composite_csr!(super::timeh::read(), read()); diff --git a/third-party/riscv/src/register/timeh.rs b/third-party/riscv/src/register/timeh.rs new file mode 100644 index 00000000..ff725dbe --- /dev/null +++ b/third-party/riscv/src/register/timeh.rs @@ -0,0 +1,3 @@ +//! timeh register + +read_csr_as_usize_rv32!(0xC81, __read_timeh); diff --git a/third-party/riscv/src/register/ucause.rs b/third-party/riscv/src/register/ucause.rs new file mode 100644 index 00000000..06dd8a33 --- /dev/null +++ b/third-party/riscv/src/register/ucause.rs @@ -0,0 +1,17 @@ +//! ucause register + +/// ucause register +#[derive(Clone, Copy, Debug)] +pub struct Ucause { + bits: usize, +} + +impl Ucause { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } +} + +read_csr_as!(Ucause, 0x042, __read_ucause); diff --git a/third-party/riscv/src/register/uepc.rs b/third-party/riscv/src/register/uepc.rs new file mode 100644 index 00000000..1c9fa0e3 --- /dev/null +++ b/third-party/riscv/src/register/uepc.rs @@ -0,0 +1,4 @@ +//! uepc register + +read_csr_as_usize!(0x041, __read_uepc); +write_csr_as_usize!(0x041, __write_uepc); diff --git a/third-party/riscv/src/register/uie.rs b/third-party/riscv/src/register/uie.rs new file mode 100644 index 00000000..4a5e9e03 --- /dev/null +++ b/third-party/riscv/src/register/uie.rs @@ -0,0 +1,49 @@ +//! uie register + +use bit_field::BitField; + +/// uie register +#[derive(Clone, Copy, Debug)] +pub struct Uie { + bits: usize, +} + +impl Uie { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Enable + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// User Timer Interrupt Enable + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// User External Interrupt Enable + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } +} + +read_csr_as!(Uie, 0x004, __read_uie); +set!(0x004, __set_uie); +clear!(0x004, __clear_uie); + +set_clear_csr!( + /// User Software Interrupt Enable + , set_usoft, clear_usoft, 1 << 0); +set_clear_csr!( + /// User Timer Interrupt Enable + , set_utimer, clear_utimer, 1 << 4); +set_clear_csr!( + /// User External Interrupt Enable + , set_uext, clear_uext, 1 << 8); diff --git a/third-party/riscv/src/register/uip.rs b/third-party/riscv/src/register/uip.rs new file mode 100644 index 00000000..ec92ad87 --- /dev/null +++ b/third-party/riscv/src/register/uip.rs @@ -0,0 +1,37 @@ +//! uip register + +use bit_field::BitField; + +/// uip register +#[derive(Clone, Copy, Debug)] +pub struct Uip { + bits: usize, +} + +impl Uip { + /// Returns the contents of the register as raw bits + #[inline] + pub fn bits(&self) -> usize { + self.bits + } + + /// User Software Interrupt Pending + #[inline] + pub fn usoft(&self) -> bool { + self.bits.get_bit(0) + } + + /// User Timer Interrupt Pending + #[inline] + pub fn utimer(&self) -> bool { + self.bits.get_bit(4) + } + + /// User External Interrupt Pending + #[inline] + pub fn uext(&self) -> bool { + self.bits.get_bit(8) + } +} + +read_csr_as!(Uip, 0x044, __read_uip); diff --git a/third-party/riscv/src/register/uscratch.rs b/third-party/riscv/src/register/uscratch.rs new file mode 100644 index 00000000..2bc22539 --- /dev/null +++ b/third-party/riscv/src/register/uscratch.rs @@ -0,0 +1,4 @@ +//! uscratch register + +read_csr_as_usize!(0x040, __read_uscratch); +write_csr_as_usize!(0x040, __write_uscratch); diff --git a/third-party/riscv/src/register/ustatus.rs b/third-party/riscv/src/register/ustatus.rs new file mode 100644 index 00000000..81890bad --- /dev/null +++ b/third-party/riscv/src/register/ustatus.rs @@ -0,0 +1,37 @@ +//! ustatus register +// TODO: Virtualization, Memory Privilege and Extension Context Fields + +use bit_field::BitField; + +/// ustatus register +#[derive(Clone, Copy, Debug)] +pub struct Ustatus { + bits: usize, +} + +impl Ustatus { + /// User Interrupt Enable + #[inline] + pub fn uie(&self) -> bool { + self.bits.get_bit(0) + } + + /// User Previous Interrupt Enable + #[inline] + pub fn upie(&self) -> bool { + self.bits.get_bit(4) + } +} + +read_csr_as!(Ustatus, 0x000, __read_ustatus); +write_csr!(0x000, __write_ustatus); +set!(0x000, __set_ustatus); +clear!(0x000, __clear_ustatus); + +set_clear_csr!( + /// User Interrupt Enable + , set_uie, clear_uie, 1 << 0); + +set_csr!( + /// User Previous Interrupt Enable + , set_upie, 1 << 4); diff --git a/third-party/riscv/src/register/utval.rs b/third-party/riscv/src/register/utval.rs new file mode 100644 index 00000000..b87dca63 --- /dev/null +++ b/third-party/riscv/src/register/utval.rs @@ -0,0 +1,3 @@ +//! utval register + +read_csr_as_usize!(0x043, __read_utval); diff --git a/third-party/riscv/src/register/utvec.rs b/third-party/riscv/src/register/utvec.rs new file mode 100644 index 00000000..7111078a --- /dev/null +++ b/third-party/riscv/src/register/utvec.rs @@ -0,0 +1,40 @@ +//! stvec register + +pub use crate::register::mtvec::TrapMode; + +/// stvec register +#[derive(Clone, Copy, Debug)] +pub struct Utvec { + bits: usize, +} + +impl Utvec { + /// Returns the contents of the register as raw bits + pub fn bits(&self) -> usize { + self.bits + } + + /// Returns the trap-vector base-address + pub fn address(&self) -> usize { + self.bits - (self.bits & 0b11) + } + + /// Returns the trap-vector mode + pub fn trap_mode(&self) -> Option { + let mode = self.bits & 0b11; + match mode { + 0 => Some(TrapMode::Direct), + 1 => Some(TrapMode::Vectored), + _ => None, + } + } +} + +read_csr_as!(Utvec, 0x005, __read_utvec); +write_csr!(0x005, __write_utvec); + +/// Writes the CSR +#[inline] +pub unsafe fn write(addr: usize, mode: TrapMode) { + _write(addr + mode as usize); +} diff --git a/third-party/virtio-drivers/.github/workflows/main.yml b/third-party/virtio-drivers/.github/workflows/main.yml new file mode 100644 index 00000000..9993f02f --- /dev/null +++ b/third-party/virtio-drivers/.github/workflows/main.yml @@ -0,0 +1,41 @@ +name: CI + +on: [push, pull_request] + +jobs: + check: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + components: rustfmt, clippy + - name: Check code format + uses: actions-rs/cargo@v1 + with: + command: fmt + args: --all -- --check + - name: Clippy + uses: actions-rs/cargo@v1 + with: + command: clippy + + build: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + - name: Build + uses: actions-rs/cargo@v1 + with: + command: build + args: --all-features + - name: Docs + uses: actions-rs/cargo@v1 + with: + command: doc diff --git a/third-party/virtio-drivers/.gitignore b/third-party/virtio-drivers/.gitignore new file mode 100644 index 00000000..96ef6c0b --- /dev/null +++ b/third-party/virtio-drivers/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/third-party/virtio-drivers/Cargo.toml b/third-party/virtio-drivers/Cargo.toml new file mode 100644 index 00000000..24a185ae --- /dev/null +++ b/third-party/virtio-drivers/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "virtio-drivers" +version = "0.1.0" +authors = ["Jiajie Chen ", "Runji Wang ", "Yuekai Jia "] +edition = "2018" +description = "VirtIO guest drivers." + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +volatile = "0.3" +log = "0.4" +bitflags = "1.3" diff --git a/third-party/virtio-drivers/LICENSE b/third-party/virtio-drivers/LICENSE new file mode 100644 index 00000000..39a8831b --- /dev/null +++ b/third-party/virtio-drivers/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2019-2020 rCore Developers + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/third-party/virtio-drivers/README.md b/third-party/virtio-drivers/README.md new file mode 100644 index 00000000..87c4a9ea --- /dev/null +++ b/third-party/virtio-drivers/README.md @@ -0,0 +1,23 @@ +# VirtIO-drivers-rs + +[![CI](https://github.com/rcore-os/virtio-drivers/workflows/CI/badge.svg?branch=master)](https://github.com/rcore-os/virtio-drivers/actions) + +VirtIO guest drivers in Rust. For **no_std** environment. + +## Components + +| Device | Status | +| -------- | ------------------- | +| Queue | ✅ | +| Block | ✅ | +| Net | ✅ | +| GPU | ✅ | +| Input | ✅ | +| Console | ✅ | +| ... | ❌ Not implemented | + +## Examples & Tests + +* x86_64 (TODO) + +* [RISCV](./examples/riscv) diff --git a/third-party/virtio-drivers/examples/riscv/.cargo/config b/third-party/virtio-drivers/examples/riscv/.cargo/config new file mode 100644 index 00000000..bbd8ec99 --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/.cargo/config @@ -0,0 +1,12 @@ +[build] +target = "riscv64imac-unknown-none-elf" + +[target.riscv32imac-unknown-none-elf] +rustflags = [ + "-C", "link-arg=-Tlinker32.ld", +] + +[target.riscv64imac-unknown-none-elf] +rustflags = [ + "-C", "link-arg=-Tlinker64.ld", +] diff --git a/third-party/virtio-drivers/examples/riscv/.gitignore b/third-party/virtio-drivers/examples/riscv/.gitignore new file mode 100644 index 00000000..96ef6c0b --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/third-party/virtio-drivers/examples/riscv/Cargo.toml b/third-party/virtio-drivers/examples/riscv/Cargo.toml new file mode 100644 index 00000000..fb7be4eb --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/Cargo.toml @@ -0,0 +1,15 @@ +[package] +name = "riscv" +version = "0.1.0" +authors = ["Runji Wang "] +edition = "2018" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +log = "0.4" +riscv = "0.6" +opensbi-rt = { git = "https://github.com/rcore-os/opensbi-rt.git", rev = "1308cc5" } +device_tree = { git = "https://github.com/rcore-os/device_tree-rs", rev = "2fa8411" } +virtio-drivers = { path = "../.." } +lazy_static = { version = "1.4", features = ["spin_no_std"] } diff --git a/third-party/virtio-drivers/examples/riscv/Makefile b/third-party/virtio-drivers/examples/riscv/Makefile new file mode 100644 index 00000000..0ac89796 --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/Makefile @@ -0,0 +1,55 @@ +arch ?= riscv64 +target := $(arch)imac-unknown-none-elf +mode := release +kernel := target/$(target)/$(mode)/riscv +img := target/$(target)/$(mode)/img + +sysroot := $(shell rustc --print sysroot) +objdump := $(shell find $(sysroot) -name llvm-objdump) --arch-name=$(arch) +objcopy := $(shell find $(sysroot) -name llvm-objcopy) + +BUILD_ARGS += --target $(target) +ifeq ($(mode), release) + BUILD_ARGS += --release +endif + +.PHONY: kernel build clean qemu run env + +build: $(bin) + +env: + rustup component add llvm-tools-preview rustfmt + rustup target add $(target) + +kernel: + cargo build $(BUILD_ARGS) + +asm: + $(objdump) -d $(kernel) | less + +sym: + $(objdump) -t $(kernel) | less + +header: + $(objdump) -x $(kernel) | less + +clean: + cargo clean + +qemu: kernel $(img) + qemu-system-$(arch) \ + -machine virt \ + -serial mon:stdio \ + -bios default \ + -kernel $(kernel) \ + -drive file=$(img),if=none,format=raw,id=x0 \ + -device virtio-blk-device,drive=x0 \ + -device virtio-gpu-device \ + -device virtio-mouse-device \ + # -netdev type=tap,id=net0,script=no,downscript=no \ + # -device virtio-net-device,netdev=net0 + +$(img): + dd if=/dev/zero of=$@ bs=512 count=32 + +run: build qemu diff --git a/third-party/virtio-drivers/examples/riscv/linker32.ld b/third-party/virtio-drivers/examples/riscv/linker32.ld new file mode 100644 index 00000000..7d2d89ec --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/linker32.ld @@ -0,0 +1,47 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) + +BASE_ADDRESS = 0x80400000; + +SECTIONS +{ + /* Load the kernel at this address: "." means the current address */ + . = BASE_ADDRESS; + start = .; + + .text : { + stext = .; + *(.text.entry) + *(.text .text.*) + . = ALIGN(4K); + etext = .; + } + + .rodata : { + srodata = .; + *(.rodata .rodata.*) + . = ALIGN(4K); + erodata = .; + } + + .data : { + sdata = .; + *(.data .data.*) + *(.sdata .sdata.*) + edata = .; + } + + .stack : { + *(.bss.stack) + } + + .bss : { + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + ebss = .; + } + + . = ALIGN(4K); + PROVIDE(end = .); +} diff --git a/third-party/virtio-drivers/examples/riscv/linker64.ld b/third-party/virtio-drivers/examples/riscv/linker64.ld new file mode 100644 index 00000000..cf96832c --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/linker64.ld @@ -0,0 +1,47 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) + +BASE_ADDRESS = 0x80200000; + +SECTIONS +{ + /* Load the kernel at this address: "." means the current address */ + . = BASE_ADDRESS; + start = .; + + .text : { + stext = .; + *(.text.entry) + *(.text .text.*) + . = ALIGN(4K); + etext = .; + } + + .rodata : { + srodata = .; + *(.rodata .rodata.*) + . = ALIGN(4K); + erodata = .; + } + + .data : { + sdata = .; + *(.data .data.*) + *(.sdata .sdata.*) + edata = .; + } + + .stack : { + *(.bss.stack) + } + + .bss : { + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + ebss = .; + } + + . = ALIGN(4K); + PROVIDE(end = .); +} diff --git a/third-party/virtio-drivers/examples/riscv/rust-toolchain b/third-party/virtio-drivers/examples/riscv/rust-toolchain new file mode 100644 index 00000000..c3912e15 --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/rust-toolchain @@ -0,0 +1 @@ +nightly-2021-03-01 \ No newline at end of file diff --git a/third-party/virtio-drivers/examples/riscv/src/main.rs b/third-party/virtio-drivers/examples/riscv/src/main.rs new file mode 100644 index 00000000..e723a30d --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/src/main.rs @@ -0,0 +1,124 @@ +#![no_std] +#![no_main] +#![deny(warnings)] + +#[macro_use] +extern crate alloc; +#[macro_use] +extern crate log; +// #[macro_use] +extern crate opensbi_rt; + +use device_tree::util::SliceRead; +use device_tree::{DeviceTree, Node}; +use log::LevelFilter; +use virtio_drivers::*; + +mod virtio_impl; + +#[no_mangle] +extern "C" fn main(_hartid: usize, device_tree_paddr: usize) { + log::set_max_level(LevelFilter::Info); + init_dt(device_tree_paddr); + info!("test end"); +} + +fn init_dt(dtb: usize) { + info!("device tree @ {:#x}", dtb); + #[repr(C)] + struct DtbHeader { + be_magic: u32, + be_size: u32, + } + let header = unsafe { &*(dtb as *const DtbHeader) }; + let magic = u32::from_be(header.be_magic); + const DEVICE_TREE_MAGIC: u32 = 0xd00dfeed; + assert_eq!(magic, DEVICE_TREE_MAGIC); + let size = u32::from_be(header.be_size); + let dtb_data = unsafe { core::slice::from_raw_parts(dtb as *const u8, size as usize) }; + let dt = DeviceTree::load(dtb_data).expect("failed to parse device tree"); + walk_dt_node(&dt.root); +} + +fn walk_dt_node(dt: &Node) { + if let Ok(compatible) = dt.prop_str("compatible") { + if compatible == "virtio,mmio" { + virtio_probe(dt); + } + } + for child in dt.children.iter() { + walk_dt_node(child); + } +} + +fn virtio_probe(node: &Node) { + if let Some(reg) = node.prop_raw("reg") { + let paddr = reg.as_slice().read_be_u64(0).unwrap(); + let size = reg.as_slice().read_be_u64(8).unwrap(); + let vaddr = paddr; + info!("walk dt addr={:#x}, size={:#x}", paddr, size); + let header = unsafe { &mut *(vaddr as *mut VirtIOHeader) }; + info!( + "Detected virtio device with vendor id {:#X}", + header.vendor_id() + ); + info!("Device tree node {:?}", node); + match header.device_type() { + DeviceType::Block => virtio_blk(header), + DeviceType::GPU => virtio_gpu(header), + DeviceType::Input => virtio_input(header), + DeviceType::Network => virtio_net(header), + t => warn!("Unrecognized virtio device: {:?}", t), + } + } +} + +fn virtio_blk(header: &'static mut VirtIOHeader) { + let mut blk = VirtIOBlk::new(header).expect("failed to create blk driver"); + let mut input = vec![0xffu8; 512]; + let mut output = vec![0; 512]; + for i in 0..32 { + for x in input.iter_mut() { + *x = i as u8; + } + blk.write_block(i, &input).expect("failed to write"); + blk.read_block(i, &mut output).expect("failed to read"); + assert_eq!(input, output); + } + info!("virtio-blk test finished"); +} + +fn virtio_gpu(header: &'static mut VirtIOHeader) { + let mut gpu = VirtIOGpu::new(header).expect("failed to create gpu driver"); + let fb = gpu.setup_framebuffer().expect("failed to get fb"); + for y in 0..768 { + for x in 0..1024 { + let idx = (y * 1024 + x) * 4; + fb[idx] = x as u8; + fb[idx + 1] = y as u8; + fb[idx + 2] = (x + y) as u8; + } + } + gpu.flush().expect("failed to flush"); + info!("virtio-gpu test finished"); +} + +fn virtio_input(header: &'static mut VirtIOHeader) { + let mut event_buf = [0u64; 32]; + let mut _input = + VirtIOInput::new(header, &mut event_buf).expect("failed to create input driver"); + // loop { + // input.ack_interrupt().expect("failed to ack"); + // info!("mouse: {:?}", input.mouse_xy()); + // } + // TODO: handle external interrupt +} + +fn virtio_net(header: &'static mut VirtIOHeader) { + let mut net = VirtIONet::new(header).expect("failed to create net driver"); + let mut buf = [0u8; 0x100]; + let len = net.recv(&mut buf).expect("failed to recv"); + info!("recv: {:?}", &buf[..len]); + net.send(&buf[..len]).expect("failed to send"); + info!("virtio-net test finished"); +} diff --git a/third-party/virtio-drivers/examples/riscv/src/virtio_impl.rs b/third-party/virtio-drivers/examples/riscv/src/virtio_impl.rs new file mode 100644 index 00000000..2fa5561d --- /dev/null +++ b/third-party/virtio-drivers/examples/riscv/src/virtio_impl.rs @@ -0,0 +1,36 @@ +use core::sync::atomic::*; +use lazy_static::lazy_static; + +extern "C" { + fn end(); +} + +lazy_static! { + static ref DMA_PADDR: AtomicUsize = AtomicUsize::new(end as usize); +} + +#[no_mangle] +extern "C" fn virtio_dma_alloc(pages: usize) -> PhysAddr { + let paddr = DMA_PADDR.fetch_add(0x1000 * pages, Ordering::SeqCst); + trace!("alloc DMA: paddr={:#x}, pages={}", paddr, pages); + paddr +} + +#[no_mangle] +extern "C" fn virtio_dma_dealloc(paddr: PhysAddr, pages: usize) -> i32 { + trace!("dealloc DMA: paddr={:#x}, pages={}", paddr, pages); + 0 +} + +#[no_mangle] +extern "C" fn virtio_phys_to_virt(paddr: PhysAddr) -> VirtAddr { + paddr +} + +#[no_mangle] +extern "C" fn virtio_virt_to_phys(vaddr: VirtAddr) -> PhysAddr { + vaddr +} + +type VirtAddr = usize; +type PhysAddr = usize; diff --git a/third-party/virtio-drivers/src/blk.rs b/third-party/virtio-drivers/src/blk.rs new file mode 100644 index 00000000..d2135049 --- /dev/null +++ b/third-party/virtio-drivers/src/blk.rs @@ -0,0 +1,312 @@ +use super::*; +use crate::header::VirtIOHeader; +use crate::queue::VirtQueue; +use bitflags::*; +use core::hint::spin_loop; +use log::*; +use volatile::Volatile; + +/// The virtio block device is a simple virtual block device (ie. disk). +/// +/// Read and write requests (and other exotic requests) are placed in the queue, +/// and serviced (probably out of order) by the device except where noted. +pub struct VirtIOBlk<'a> { + header: &'static mut VirtIOHeader, + queue: VirtQueue<'a>, + capacity: usize, +} + +impl VirtIOBlk<'_> { + /// Create a new VirtIO-Blk driver. + pub fn new(header: &'static mut VirtIOHeader) -> Result { + header.begin_init(|features| { + let features = BlkFeature::from_bits_truncate(features); + info!("device features: {:?}", features); + // negotiate these flags only + let supported_features = BlkFeature::empty(); + (features & supported_features).bits() + }); + + // read configuration space + let config = unsafe { &mut *(header.config_space() as *mut BlkConfig) }; + info!("config: {:?}", config); + info!( + "found a block device of size {}KB", + config.capacity.read() / 2 + ); + + let queue = VirtQueue::new(header, 0, 16)?; + header.finish_init(); + + Ok(VirtIOBlk { + header, + queue, + capacity: config.capacity.read() as usize, + }) + } + + /// Acknowledge interrupt. + pub fn ack_interrupt(&mut self) -> bool { + self.header.ack_interrupt() + } + + /// Read a block. + pub fn read_block(&mut self, block_id: usize, buf: &mut [u8]) -> Result { + assert_eq!(buf.len(), BLK_SIZE); + let req = BlkReq { + type_: ReqType::In, + reserved: 0, + sector: block_id as u64, + }; + let mut resp = BlkResp::default(); + self.queue.add(&[req.as_buf()], &[buf, resp.as_buf_mut()])?; + self.header.notify(0); + while !self.queue.can_pop() { + spin_loop(); + } + self.queue.pop_used()?; + match resp.status { + RespStatus::Ok => Ok(()), + _ => Err(Error::IoError), + } + } + + /// Read a block in a non-blocking way which means that it returns immediately. + /// + /// # Arguments + /// + /// * `block_id` - The identifier of the block to read. + /// * `buf` - The buffer in the memory which the block is read into. + /// * `resp` - A mutable reference to a variable provided by the caller + /// which contains the status of the requests. The caller can safely + /// read the variable only after the request is ready. + /// + /// # Usage + /// + /// It will submit request to the virtio block device and return a token identifying + /// the position of the first Descriptor in the chain. If there are not enough + /// Descriptors to allocate, then it returns [Error::BufferTooSmall]. + /// + /// After the request is ready, `resp` will be updated and the caller can get the + /// status of the request(e.g. succeed or failed) through it. However, the caller + /// **must not** spin on `resp` to wait for it to change. A safe way is to read it + /// after the same token as this method returns is fetched through [VirtIOBlk::pop_used()], + /// which means that the request has been ready. + /// + /// # Safety + /// + /// `buf` is still borrowed by the underlying virtio block device even if this + /// method returns. Thus, it is the caller's responsibility to guarantee that + /// `buf` is not accessed before the request is completed in order to avoid + /// data races. + pub unsafe fn read_block_nb( + &mut self, + block_id: usize, + buf: &mut [u8], + resp: &mut BlkResp, + ) -> Result { + assert_eq!(buf.len(), BLK_SIZE); + let req = BlkReq { + type_: ReqType::In, + reserved: 0, + sector: block_id as u64, + }; + let token = self.queue.add(&[req.as_buf()], &[buf, resp.as_buf_mut()])?; + self.header.notify(0); + Ok(token) + } + + /// Write a block. + pub fn write_block(&mut self, block_id: usize, buf: &[u8]) -> Result { + assert_eq!(buf.len(), BLK_SIZE); + let req = BlkReq { + type_: ReqType::Out, + reserved: 0, + sector: block_id as u64, + }; + let mut resp = BlkResp::default(); + self.queue.add(&[req.as_buf(), buf], &[resp.as_buf_mut()])?; + self.header.notify(0); + while !self.queue.can_pop() { + spin_loop(); + } + self.queue.pop_used()?; + match resp.status { + RespStatus::Ok => Ok(()), + _ => Err(Error::IoError), + } + } + + //// Write a block in a non-blocking way which means that it returns immediately. + /// + /// # Arguments + /// + /// * `block_id` - The identifier of the block to write. + /// * `buf` - The buffer in the memory containing the data to write to the block. + /// * `resp` - A mutable reference to a variable provided by the caller + /// which contains the status of the requests. The caller can safely + /// read the variable only after the request is ready. + /// + /// # Usage + /// + /// See also [VirtIOBlk::read_block_nb()]. + /// + /// # Safety + /// + /// See also [VirtIOBlk::read_block_nb()]. + pub unsafe fn write_block_nb( + &mut self, + block_id: usize, + buf: &[u8], + resp: &mut BlkResp, + ) -> Result { + assert_eq!(buf.len(), BLK_SIZE); + let req = BlkReq { + type_: ReqType::Out, + reserved: 0, + sector: block_id as u64, + }; + let token = self.queue.add(&[req.as_buf(), buf], &[resp.as_buf_mut()])?; + self.header.notify(0); + Ok(token) + } + + /// During an interrupt, it fetches a token of a completed request from the used + /// ring and return it. If all completed requests have already been fetched, return + /// Err(Error::NotReady). + pub fn pop_used(&mut self) -> Result { + self.queue.pop_used().map(|p| p.0) + } + + /// Return size of its VirtQueue. + /// It can be used to tell the caller how many channels he should monitor on. + pub fn virt_queue_size(&self) -> u16 { + self.queue.size() + } +} + +#[repr(C)] +#[derive(Debug)] +struct BlkConfig { + /// Number of 512 Bytes sectors + capacity: Volatile, + size_max: Volatile, + seg_max: Volatile, + cylinders: Volatile, + heads: Volatile, + sectors: Volatile, + blk_size: Volatile, + physical_block_exp: Volatile, + alignment_offset: Volatile, + min_io_size: Volatile, + opt_io_size: Volatile, + // ... ignored +} + +#[repr(C)] +#[derive(Debug)] +struct BlkReq { + type_: ReqType, + reserved: u32, + sector: u64, +} + +/// Response of a VirtIOBlk request. +#[repr(C)] +#[derive(Debug)] +pub struct BlkResp { + status: RespStatus, +} + +impl BlkResp { + /// Return the status of a VirtIOBlk request. + pub fn status(&self) -> RespStatus { + self.status + } +} + +#[repr(u32)] +#[derive(Debug)] +enum ReqType { + In = 0, + Out = 1, + Flush = 4, + Discard = 11, + WriteZeroes = 13, +} + +/// Status of a VirtIOBlk request. +#[repr(u8)] +#[derive(Debug, Eq, PartialEq, Copy, Clone)] +pub enum RespStatus { + /// Ok. + Ok = 0, + /// IoErr. + IoErr = 1, + /// Unsupported yet. + Unsupported = 2, + /// Not ready. + _NotReady = 3, +} + +impl Default for BlkResp { + fn default() -> Self { + BlkResp { + status: RespStatus::_NotReady, + } + } +} + +const BLK_SIZE: usize = 512; + +bitflags! { + struct BlkFeature: u64 { + /// Device supports request barriers. (legacy) + const BARRIER = 1 << 0; + /// Maximum size of any single segment is in `size_max`. + const SIZE_MAX = 1 << 1; + /// Maximum number of segments in a request is in `seg_max`. + const SEG_MAX = 1 << 2; + /// Disk-style geometry specified in geometry. + const GEOMETRY = 1 << 4; + /// Device is read-only. + const RO = 1 << 5; + /// Block size of disk is in `blk_size`. + const BLK_SIZE = 1 << 6; + /// Device supports scsi packet commands. (legacy) + const SCSI = 1 << 7; + /// Cache flush command support. + const FLUSH = 1 << 9; + /// Device exports information on optimal I/O alignment. + const TOPOLOGY = 1 << 10; + /// Device can toggle its cache between writeback and writethrough modes. + const CONFIG_WCE = 1 << 11; + /// Device can support discard command, maximum discard sectors size in + /// `max_discard_sectors` and maximum discard segment number in + /// `max_discard_seg`. + const DISCARD = 1 << 13; + /// Device can support write zeroes command, maximum write zeroes sectors + /// size in `max_write_zeroes_sectors` and maximum write zeroes segment + /// number in `max_write_zeroes_seg`. + const WRITE_ZEROES = 1 << 14; + + // device independent + const NOTIFY_ON_EMPTY = 1 << 24; // legacy + const ANY_LAYOUT = 1 << 27; // legacy + const RING_INDIRECT_DESC = 1 << 28; + const RING_EVENT_IDX = 1 << 29; + const UNUSED = 1 << 30; // legacy + const VERSION_1 = 1 << 32; // detect legacy + + // the following since virtio v1.1 + const ACCESS_PLATFORM = 1 << 33; + const RING_PACKED = 1 << 34; + const IN_ORDER = 1 << 35; + const ORDER_PLATFORM = 1 << 36; + const SR_IOV = 1 << 37; + const NOTIFICATION_DATA = 1 << 38; + } +} + +unsafe impl AsBuf for BlkReq {} +unsafe impl AsBuf for BlkResp {} diff --git a/third-party/virtio-drivers/src/console.rs b/third-party/virtio-drivers/src/console.rs new file mode 100644 index 00000000..2e798c99 --- /dev/null +++ b/third-party/virtio-drivers/src/console.rs @@ -0,0 +1,139 @@ +use super::*; +use crate::queue::VirtQueue; +use bitflags::*; +use core::{fmt, hint::spin_loop}; +use log::*; +use volatile::{ReadOnly, WriteOnly}; + +const QUEUE_RECEIVEQ_PORT_0: usize = 0; +const QUEUE_TRANSMITQ_PORT_0: usize = 1; + +/// Virtio console. Only one single port is allowed since ``alloc'' is disabled. +/// Emergency and cols/rows unimplemented. +pub struct VirtIOConsole<'a> { + header: &'static mut VirtIOHeader, + receiveq: VirtQueue<'a>, + transmitq: VirtQueue<'a>, + queue_buf_dma: DMA, + queue_buf_rx: &'a mut [u8], + cursor: usize, + pending_len: usize, +} + +impl<'a> VirtIOConsole<'a> { + /// Create a new VirtIO-Console driver. + pub fn new(header: &'static mut VirtIOHeader) -> Result { + header.begin_init(|features| { + let features = Features::from_bits_truncate(features); + info!("Device features {:?}", features); + let supported_features = Features::empty(); + (features & supported_features).bits() + }); + let config = unsafe { &mut *(header.config_space() as *mut Config) }; + info!("Config: {:?}", config); + let receiveq = VirtQueue::new(header, QUEUE_RECEIVEQ_PORT_0, 2)?; + let transmitq = VirtQueue::new(header, QUEUE_TRANSMITQ_PORT_0, 2)?; + let queue_buf_dma = DMA::new(1)?; + let queue_buf_rx = unsafe { &mut queue_buf_dma.as_buf()[0..] }; + header.finish_init(); + let mut console = VirtIOConsole { + header, + receiveq, + transmitq, + queue_buf_dma, + queue_buf_rx, + cursor: 0, + pending_len: 0, + }; + console.poll_retrieve()?; + Ok(console) + } + fn poll_retrieve(&mut self) -> Result<()> { + self.receiveq.add(&[], &[self.queue_buf_rx])?; + Ok(()) + } + /// Acknowledge interrupt. + pub fn ack_interrupt(&mut self) -> Result { + let ack = self.header.ack_interrupt(); + if !ack { + return Ok(false); + } + let mut flag = false; + while let Ok((_token, len)) = self.receiveq.pop_used() { + assert_eq!(flag, false); + flag = true; + assert_ne!(len, 0); + self.cursor = 0; + self.pending_len = len as usize; + } + Ok(flag) + } + + /// Try get char. + pub fn recv(&mut self, pop: bool) -> Result> { + if self.cursor == self.pending_len { + return Ok(None); + } + let ch = self.queue_buf_rx[self.cursor]; + if pop { + self.cursor += 1; + if self.cursor == self.pending_len { + self.poll_retrieve()?; + } + } + Ok(Some(ch)) + } + /// Put a char onto the device. + pub fn send(&mut self, chr: u8) -> Result<()> { + let buf: [u8; 1] = [chr]; + self.transmitq.add(&[&buf], &[])?; + self.header.notify(QUEUE_TRANSMITQ_PORT_0 as u32); + while !self.transmitq.can_pop() { + spin_loop(); + } + self.transmitq.pop_used()?; + Ok(()) + } +} + +#[repr(C)] +struct Config { + cols: ReadOnly, + rows: ReadOnly, + max_nr_ports: ReadOnly, + emerg_wr: WriteOnly, +} + +impl fmt::Debug for Config { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("Config") + .field("cols", &self.cols) + .field("rows", &self.rows) + .field("max_nr_ports", &self.max_nr_ports) + .finish() + } +} + +bitflags! { + struct Features: u64 { + const SIZE = 1 << 0; + const MULTIPORT = 1 << 1; + const EMERG_WRITE = 1 << 2; + + // device independent + const NOTIFY_ON_EMPTY = 1 << 24; // legacy + const ANY_LAYOUT = 1 << 27; // legacy + const RING_INDIRECT_DESC = 1 << 28; + const RING_EVENT_IDX = 1 << 29; + const UNUSED = 1 << 30; // legacy + const VERSION_1 = 1 << 32; // detect legacy + + // since virtio v1.1 + const ACCESS_PLATFORM = 1 << 33; + const RING_PACKED = 1 << 34; + const IN_ORDER = 1 << 35; + const ORDER_PLATFORM = 1 << 36; + const SR_IOV = 1 << 37; + const NOTIFICATION_DATA = 1 << 38; + } +} diff --git a/third-party/virtio-drivers/src/gpu.rs b/third-party/virtio-drivers/src/gpu.rs new file mode 100644 index 00000000..868e1e20 --- /dev/null +++ b/third-party/virtio-drivers/src/gpu.rs @@ -0,0 +1,496 @@ +use super::*; +use crate::queue::VirtQueue; +use bitflags::*; +use core::{fmt, hint::spin_loop}; +use log::*; +use volatile::{ReadOnly, Volatile, WriteOnly}; + +/// A virtio based graphics adapter. +/// +/// It can operate in 2D mode and in 3D (virgl) mode. +/// 3D mode will offload rendering ops to the host gpu and therefore requires +/// a gpu with 3D support on the host machine. +/// In 2D mode the virtio-gpu device provides support for ARGB Hardware cursors +/// and multiple scanouts (aka heads). +pub struct VirtIOGpu<'a> { + header: &'static mut VirtIOHeader, + rect: Rect, + /// DMA area of frame buffer. + frame_buffer_dma: Option, + /// DMA area of cursor image buffer. + cursor_buffer_dma: Option, + /// Queue for sending control commands. + control_queue: VirtQueue<'a>, + /// Queue for sending cursor commands. + cursor_queue: VirtQueue<'a>, + /// Queue buffer DMA + queue_buf_dma: DMA, + /// Send buffer for queue. + queue_buf_send: &'a mut [u8], + /// Recv buffer for queue. + queue_buf_recv: &'a mut [u8], +} + +impl VirtIOGpu<'_> { + /// Create a new VirtIO-Gpu driver. + pub fn new(header: &'static mut VirtIOHeader) -> Result { + header.begin_init(|features| { + let features = Features::from_bits_truncate(features); + info!("Device features {:?}", features); + let supported_features = Features::empty(); + (features & supported_features).bits() + }); + + // read configuration space + let config = unsafe { &mut *(header.config_space() as *mut Config) }; + info!("Config: {:?}", config); + + let control_queue = VirtQueue::new(header, QUEUE_TRANSMIT, 2)?; + let cursor_queue = VirtQueue::new(header, QUEUE_CURSOR, 2)?; + + let queue_buf_dma = DMA::new(2)?; + let queue_buf_send = unsafe { &mut queue_buf_dma.as_buf()[..PAGE_SIZE] }; + let queue_buf_recv = unsafe { &mut queue_buf_dma.as_buf()[PAGE_SIZE..] }; + + header.finish_init(); + + Ok(VirtIOGpu { + header, + frame_buffer_dma: None, + cursor_buffer_dma: None, + rect: Rect::default(), + control_queue, + cursor_queue, + queue_buf_dma, + queue_buf_send, + queue_buf_recv, + }) + } + + /// Acknowledge interrupt. + pub fn ack_interrupt(&mut self) -> bool { + self.header.ack_interrupt() + } + + /// Get the resolution (width, height). + pub fn resolution(&self) -> (u32, u32) { + (self.rect.width, self.rect.height) + } + + /// Setup framebuffer + pub fn setup_framebuffer(&mut self) -> Result<&mut [u8]> { + // get display info + let display_info = self.get_display_info()?; + info!("=> {:?}", display_info); + self.rect = display_info.rect; + + // create resource 2d + self.resource_create_2d( + RESOURCE_ID_FB, + display_info.rect.width, + display_info.rect.height, + )?; + + // alloc continuous pages for the frame buffer + let size = display_info.rect.width * display_info.rect.height * 4; + let frame_buffer_dma = DMA::new(pages(size as usize))?; + + // resource_attach_backing + self.resource_attach_backing(RESOURCE_ID_FB, frame_buffer_dma.paddr() as u64, size)?; + + // map frame buffer to screen + self.set_scanout(display_info.rect, SCANOUT_ID, RESOURCE_ID_FB)?; + + let buf = unsafe { frame_buffer_dma.as_buf() }; + self.frame_buffer_dma = Some(frame_buffer_dma); + Ok(buf) + } + + /// Flush framebuffer to screen. + pub fn flush(&mut self) -> Result { + // copy data from guest to host + self.transfer_to_host_2d(self.rect, 0, RESOURCE_ID_FB)?; + // flush data to screen + self.resource_flush(self.rect, RESOURCE_ID_FB)?; + Ok(()) + } + + /// Set the pointer shape and position. + pub fn setup_cursor( + &mut self, + cursor_image: &[u8], + pos_x: u32, + pos_y: u32, + hot_x: u32, + hot_y: u32, + ) -> Result { + let size = CURSOR_RECT.width * CURSOR_RECT.height * 4; + if cursor_image.len() != size as usize { + return Err(Error::InvalidParam); + } + let cursor_buffer_dma = DMA::new(pages(size as usize))?; + let buf = unsafe { cursor_buffer_dma.as_buf() }; + buf.copy_from_slice(cursor_image); + + self.resource_create_2d(RESOURCE_ID_CURSOR, CURSOR_RECT.width, CURSOR_RECT.height)?; + self.resource_attach_backing(RESOURCE_ID_CURSOR, cursor_buffer_dma.paddr() as u64, size)?; + self.transfer_to_host_2d(CURSOR_RECT, 0, RESOURCE_ID_CURSOR)?; + self.update_cursor( + RESOURCE_ID_CURSOR, + SCANOUT_ID, + pos_x, + pos_y, + hot_x, + hot_y, + false, + )?; + self.cursor_buffer_dma = Some(cursor_buffer_dma); + Ok(()) + } + + /// Move the pointer without updating the shape. + pub fn move_cursor(&mut self, pos_x: u32, pos_y: u32) -> Result { + self.update_cursor(RESOURCE_ID_CURSOR, SCANOUT_ID, pos_x, pos_y, 0, 0, true)?; + Ok(()) + } +} + +impl VirtIOGpu<'_> { + /// Send a request to the device and block for a response. + fn request(&mut self, req: Req) -> Result { + unsafe { + (self.queue_buf_send.as_mut_ptr() as *mut Req).write(req); + } + self.control_queue + .add(&[self.queue_buf_send], &[self.queue_buf_recv])?; + self.header.notify(QUEUE_TRANSMIT as u32); + while !self.control_queue.can_pop() { + spin_loop(); + } + self.control_queue.pop_used()?; + Ok(unsafe { (self.queue_buf_recv.as_ptr() as *const Rsp).read() }) + } + + /// Send a mouse cursor operation request to the device and block for a response. + fn cursor_request(&mut self, req: Req) -> Result { + unsafe { + (self.queue_buf_send.as_mut_ptr() as *mut Req).write(req); + } + self.cursor_queue.add(&[self.queue_buf_send], &[])?; + self.header.notify(QUEUE_CURSOR as u32); + while !self.cursor_queue.can_pop() { + spin_loop(); + } + self.cursor_queue.pop_used()?; + Ok(()) + } + + fn get_display_info(&mut self) -> Result { + let info: RespDisplayInfo = self.request(CtrlHeader::with_type(Command::GetDisplayInfo))?; + info.header.check_type(Command::OkDisplayInfo)?; + Ok(info) + } + + fn resource_create_2d(&mut self, resource_id: u32, width: u32, height: u32) -> Result { + let rsp: CtrlHeader = self.request(ResourceCreate2D { + header: CtrlHeader::with_type(Command::ResourceCreate2d), + resource_id, + format: Format::B8G8R8A8UNORM, + width, + height, + })?; + rsp.check_type(Command::OkNodata) + } + + fn set_scanout(&mut self, rect: Rect, scanout_id: u32, resource_id: u32) -> Result { + let rsp: CtrlHeader = self.request(SetScanout { + header: CtrlHeader::with_type(Command::SetScanout), + rect, + scanout_id, + resource_id, + })?; + rsp.check_type(Command::OkNodata) + } + + fn resource_flush(&mut self, rect: Rect, resource_id: u32) -> Result { + let rsp: CtrlHeader = self.request(ResourceFlush { + header: CtrlHeader::with_type(Command::ResourceFlush), + rect, + resource_id, + _padding: 0, + })?; + rsp.check_type(Command::OkNodata) + } + + fn transfer_to_host_2d(&mut self, rect: Rect, offset: u64, resource_id: u32) -> Result { + let rsp: CtrlHeader = self.request(TransferToHost2D { + header: CtrlHeader::with_type(Command::TransferToHost2d), + rect, + offset, + resource_id, + _padding: 0, + })?; + rsp.check_type(Command::OkNodata) + } + + fn resource_attach_backing(&mut self, resource_id: u32, paddr: u64, length: u32) -> Result { + let rsp: CtrlHeader = self.request(ResourceAttachBacking { + header: CtrlHeader::with_type(Command::ResourceAttachBacking), + resource_id, + nr_entries: 1, + addr: paddr, + length, + _padding: 0, + })?; + rsp.check_type(Command::OkNodata) + } + + fn update_cursor( + &mut self, + resource_id: u32, + scanout_id: u32, + pos_x: u32, + pos_y: u32, + hot_x: u32, + hot_y: u32, + is_move: bool, + ) -> Result { + self.cursor_request(UpdateCursor { + header: if is_move { + CtrlHeader::with_type(Command::MoveCursor) + } else { + CtrlHeader::with_type(Command::UpdateCursor) + }, + pos: CursorPos { + scanout_id, + x: pos_x, + y: pos_y, + _padding: 0, + }, + resource_id, + hot_x, + hot_y, + _padding: 0, + }) + } +} + +#[repr(C)] +struct Config { + /// Signals pending events to the driver。 + events_read: ReadOnly, + + /// Clears pending events in the device. + events_clear: WriteOnly, + + /// Specifies the maximum number of scanouts supported by the device. + /// + /// Minimum value is 1, maximum value is 16. + num_scanouts: Volatile, +} + +impl fmt::Debug for Config { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("Config") + .field("events_read", &self.events_read) + .field("num_scanouts", &self.num_scanouts) + .finish() + } +} + +/// Display configuration has changed. +const EVENT_DISPLAY: u32 = 1 << 0; + +bitflags! { + struct Features: u64 { + /// virgl 3D mode is supported. + const VIRGL = 1 << 0; + /// EDID is supported. + const EDID = 1 << 1; + + // device independent + const NOTIFY_ON_EMPTY = 1 << 24; // legacy + const ANY_LAYOUT = 1 << 27; // legacy + const RING_INDIRECT_DESC = 1 << 28; + const RING_EVENT_IDX = 1 << 29; + const UNUSED = 1 << 30; // legacy + const VERSION_1 = 1 << 32; // detect legacy + + // since virtio v1.1 + const ACCESS_PLATFORM = 1 << 33; + const RING_PACKED = 1 << 34; + const IN_ORDER = 1 << 35; + const ORDER_PLATFORM = 1 << 36; + const SR_IOV = 1 << 37; + const NOTIFICATION_DATA = 1 << 38; + } +} + +#[repr(u32)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Command { + GetDisplayInfo = 0x100, + ResourceCreate2d = 0x101, + ResourceUnref = 0x102, + SetScanout = 0x103, + ResourceFlush = 0x104, + TransferToHost2d = 0x105, + ResourceAttachBacking = 0x106, + ResourceDetachBacking = 0x107, + GetCapsetInfo = 0x108, + GetCapset = 0x109, + GetEdid = 0x10a, + + UpdateCursor = 0x300, + MoveCursor = 0x301, + + OkNodata = 0x1100, + OkDisplayInfo = 0x1101, + OkCapsetInfo = 0x1102, + OkCapset = 0x1103, + OkEdid = 0x1104, + + ErrUnspec = 0x1200, + ErrOutOfMemory = 0x1201, + ErrInvalidScanoutId = 0x1202, +} + +const GPU_FLAG_FENCE: u32 = 1 << 0; + +#[repr(C)] +#[derive(Debug, Clone, Copy)] +struct CtrlHeader { + hdr_type: Command, + flags: u32, + fence_id: u64, + ctx_id: u32, + _padding: u32, +} + +impl CtrlHeader { + fn with_type(hdr_type: Command) -> CtrlHeader { + CtrlHeader { + hdr_type, + flags: 0, + fence_id: 0, + ctx_id: 0, + _padding: 0, + } + } + + /// Return error if the type is not same as expected. + fn check_type(&self, expected: Command) -> Result { + if self.hdr_type == expected { + Ok(()) + } else { + Err(Error::IoError) + } + } +} + +#[repr(C)] +#[derive(Debug, Copy, Clone, Default)] +struct Rect { + x: u32, + y: u32, + width: u32, + height: u32, +} + +#[repr(C)] +#[derive(Debug)] +struct RespDisplayInfo { + header: CtrlHeader, + rect: Rect, + enabled: u32, + flags: u32, +} + +#[repr(C)] +#[derive(Debug)] +struct ResourceCreate2D { + header: CtrlHeader, + resource_id: u32, + format: Format, + width: u32, + height: u32, +} + +#[repr(u32)] +#[derive(Debug)] +enum Format { + B8G8R8A8UNORM = 1, +} + +#[repr(C)] +#[derive(Debug)] +struct ResourceAttachBacking { + header: CtrlHeader, + resource_id: u32, + nr_entries: u32, // always 1 + addr: u64, + length: u32, + _padding: u32, +} + +#[repr(C)] +#[derive(Debug)] +struct SetScanout { + header: CtrlHeader, + rect: Rect, + scanout_id: u32, + resource_id: u32, +} + +#[repr(C)] +#[derive(Debug)] +struct TransferToHost2D { + header: CtrlHeader, + rect: Rect, + offset: u64, + resource_id: u32, + _padding: u32, +} + +#[repr(C)] +#[derive(Debug)] +struct ResourceFlush { + header: CtrlHeader, + rect: Rect, + resource_id: u32, + _padding: u32, +} + +#[repr(C)] +#[derive(Debug, Clone, Copy)] +struct CursorPos { + scanout_id: u32, + x: u32, + y: u32, + _padding: u32, +} + +#[repr(C)] +#[derive(Debug, Clone, Copy)] +struct UpdateCursor { + header: CtrlHeader, + pos: CursorPos, + resource_id: u32, + hot_x: u32, + hot_y: u32, + _padding: u32, +} + +const QUEUE_TRANSMIT: usize = 0; +const QUEUE_CURSOR: usize = 1; + +const SCANOUT_ID: u32 = 0; +const RESOURCE_ID_FB: u32 = 0xbabe; +const RESOURCE_ID_CURSOR: u32 = 0xdade; + +const CURSOR_RECT: Rect = Rect { + x: 0, + y: 0, + width: 64, + height: 64, +}; diff --git a/third-party/virtio-drivers/src/hal.rs b/third-party/virtio-drivers/src/hal.rs new file mode 100644 index 00000000..47159d3f --- /dev/null +++ b/third-party/virtio-drivers/src/hal.rs @@ -0,0 +1,62 @@ +use super::*; + +type VirtAddr = usize; +type PhysAddr = usize; + +pub struct DMA { + paddr: u32, + pages: u32, +} + +impl DMA { + pub fn new(pages: usize) -> Result { + let paddr = unsafe { virtio_dma_alloc(pages) }; + if paddr == 0 { + return Err(Error::DmaError); + } + Ok(DMA { + paddr: paddr as u32, + pages: pages as u32, + }) + } + + pub fn paddr(&self) -> usize { + self.paddr as usize + } + + pub fn vaddr(&self) -> usize { + phys_to_virt(self.paddr as usize) + } + + /// Page frame number + pub fn pfn(&self) -> u32 { + self.paddr >> 12 + } + + /// Convert to a buffer + pub unsafe fn as_buf(&self) -> &'static mut [u8] { + core::slice::from_raw_parts_mut(self.vaddr() as _, PAGE_SIZE * self.pages as usize) + } +} + +impl Drop for DMA { + fn drop(&mut self) { + let err = unsafe { virtio_dma_dealloc(self.paddr as usize, self.pages as usize) }; + assert_eq!(err, 0, "failed to deallocate DMA"); + } +} + +pub fn phys_to_virt(paddr: PhysAddr) -> VirtAddr { + unsafe { virtio_phys_to_virt(paddr) } +} + +pub fn virt_to_phys(vaddr: VirtAddr) -> PhysAddr { + unsafe { virtio_virt_to_phys(vaddr) } +} + +extern "C" { + fn virtio_dma_alloc(pages: usize) -> PhysAddr; + fn virtio_dma_dealloc(paddr: PhysAddr, pages: usize) -> i32; + fn virtio_phys_to_virt(paddr: PhysAddr) -> VirtAddr; + fn virtio_virt_to_phys(vaddr: VirtAddr) -> PhysAddr; +} diff --git a/third-party/virtio-drivers/src/header.rs b/third-party/virtio-drivers/src/header.rs new file mode 100644 index 00000000..e00d1681 --- /dev/null +++ b/third-party/virtio-drivers/src/header.rs @@ -0,0 +1,308 @@ +use crate::PAGE_SIZE; +use bitflags::*; +use volatile::{ReadOnly, Volatile, WriteOnly}; + +/// MMIO Device Legacy Register Interface. +/// +/// Ref: 4.2.4 Legacy interface +#[repr(C)] +pub struct VirtIOHeader { + /// Magic value + magic: ReadOnly, + + /// Device version number + /// + /// Legacy device returns value 0x1. + version: ReadOnly, + + /// Virtio Subsystem Device ID + device_id: ReadOnly, + + /// Virtio Subsystem Vendor ID + vendor_id: ReadOnly, + + /// Flags representing features the device supports + device_features: ReadOnly, + + /// Device (host) features word selection + device_features_sel: WriteOnly, + + /// Reserved + __r1: [ReadOnly; 2], + + /// Flags representing device features understood and activated by the driver + driver_features: WriteOnly, + + /// Activated (guest) features word selection + driver_features_sel: WriteOnly, + + /// Guest page size + /// + /// The driver writes the guest page size in bytes to the register during + /// initialization, before any queues are used. This value should be a + /// power of 2 and is used by the device to calculate the Guest address + /// of the first queue page (see QueuePFN). + guest_page_size: WriteOnly, + + /// Reserved + __r2: ReadOnly, + + /// Virtual queue index + /// + /// Writing to this register selects the virtual queue that the following + /// operations on the QueueNumMax, QueueNum, QueueAlign and QueuePFN + /// registers apply to. The index number of the first queue is zero (0x0). + queue_sel: WriteOnly, + + /// Maximum virtual queue size + /// + /// Reading from the register returns the maximum size of the queue the + /// device is ready to process or zero (0x0) if the queue is not available. + /// This applies to the queue selected by writing to QueueSel and is + /// allowed only when QueuePFN is set to zero (0x0), so when the queue is + /// not actively used. + queue_num_max: ReadOnly, + + /// Virtual queue size + /// + /// Queue size is the number of elements in the queue. Writing to this + /// register notifies the device what size of the queue the driver will use. + /// This applies to the queue selected by writing to QueueSel. + queue_num: WriteOnly, + + /// Used Ring alignment in the virtual queue + /// + /// Writing to this register notifies the device about alignment boundary + /// of the Used Ring in bytes. This value should be a power of 2 and + /// applies to the queue selected by writing to QueueSel. + queue_align: WriteOnly, + + /// Guest physical page number of the virtual queue + /// + /// Writing to this register notifies the device about location of the + /// virtual queue in the Guest’s physical address space. This value is + /// the index number of a page starting with the queue Descriptor Table. + /// Value zero (0x0) means physical address zero (0x00000000) and is illegal. + /// When the driver stops using the queue it writes zero (0x0) to this + /// register. Reading from this register returns the currently used page + /// number of the queue, therefore a value other than zero (0x0) means that + /// the queue is in use. Both read and write accesses apply to the queue + /// selected by writing to QueueSel. + queue_pfn: Volatile, + + /// new interface only + queue_ready: Volatile, + + /// Reserved + __r3: [ReadOnly; 2], + + /// Queue notifier + queue_notify: WriteOnly, + + /// Reserved + __r4: [ReadOnly; 3], + + /// Interrupt status + interrupt_status: ReadOnly, + + /// Interrupt acknowledge + interrupt_ack: WriteOnly, + + /// Reserved + __r5: [ReadOnly; 2], + + /// Device status + /// + /// Reading from this register returns the current device status flags. + /// Writing non-zero values to this register sets the status flags, + /// indicating the OS/driver progress. Writing zero (0x0) to this register + /// triggers a device reset. The device sets QueuePFN to zero (0x0) for + /// all queues in the device. Also see 3.1 Device Initialization. + status: Volatile, + + /// Reserved + __r6: [ReadOnly; 3], + + // new interface only since here + queue_desc_low: WriteOnly, + queue_desc_high: WriteOnly, + + /// Reserved + __r7: [ReadOnly; 2], + + queue_avail_low: WriteOnly, + queue_avail_high: WriteOnly, + + /// Reserved + __r8: [ReadOnly; 2], + + queue_used_low: WriteOnly, + queue_used_high: WriteOnly, + + /// Reserved + __r9: [ReadOnly; 21], + + config_generation: ReadOnly, +} + +impl VirtIOHeader { + /// Verify a valid header. + pub fn verify(&self) -> bool { + self.magic.read() == 0x7472_6976 && self.version.read() == 1 && self.device_id.read() != 0 + } + + /// Get the device type. + pub fn device_type(&self) -> DeviceType { + match self.device_id.read() { + x @ 1..=13 | x @ 16..=24 => unsafe { core::mem::transmute(x as u8) }, + _ => DeviceType::Invalid, + } + } + + /// Get the vendor ID. + pub fn vendor_id(&self) -> u32 { + self.vendor_id.read() + } + + /// Begin initializing the device. + /// + /// Ref: virtio 3.1.1 Device Initialization + pub fn begin_init(&mut self, negotiate_features: impl FnOnce(u64) -> u64) { + self.status.write(DeviceStatus::ACKNOWLEDGE); + self.status.write(DeviceStatus::DRIVER); + + let features = self.read_device_features(); + self.write_driver_features(negotiate_features(features)); + self.status.write(DeviceStatus::FEATURES_OK); + + self.guest_page_size.write(PAGE_SIZE as u32); + } + + /// Finish initializing the device. + pub fn finish_init(&mut self) { + self.status.write(DeviceStatus::DRIVER_OK); + } + + /// Read device features. + fn read_device_features(&mut self) -> u64 { + self.device_features_sel.write(0); // device features [0, 32) + let mut device_features_bits = self.device_features.read().into(); + self.device_features_sel.write(1); // device features [32, 64) + device_features_bits += (self.device_features.read() as u64) << 32; + device_features_bits + } + + /// Write device features. + fn write_driver_features(&mut self, driver_features: u64) { + self.driver_features_sel.write(0); // driver features [0, 32) + self.driver_features.write(driver_features as u32); + self.driver_features_sel.write(1); // driver features [32, 64) + self.driver_features.write((driver_features >> 32) as u32); + } + + /// Set queue. + pub fn queue_set(&mut self, queue: u32, size: u32, align: u32, pfn: u32) { + self.queue_sel.write(queue); + self.queue_num.write(size); + self.queue_align.write(align); + self.queue_pfn.write(pfn); + } + + /// Get guest physical page number of the virtual queue. + pub fn queue_physical_page_number(&mut self, queue: u32) -> u32 { + self.queue_sel.write(queue); + self.queue_pfn.read() + } + + /// Whether the queue is in used. + pub fn queue_used(&mut self, queue: u32) -> bool { + self.queue_physical_page_number(queue) != 0 + } + + /// Get the max size of queue. + pub fn max_queue_size(&self) -> u32 { + self.queue_num_max.read() + } + + /// Notify device. + pub fn notify(&mut self, queue: u32) { + self.queue_notify.write(queue); + } + + /// Acknowledge interrupt and return true if success. + pub fn ack_interrupt(&mut self) -> bool { + let interrupt = self.interrupt_status.read(); + if interrupt != 0 { + self.interrupt_ack.write(interrupt); + true + } else { + false + } + } + + /// Get the pointer to config space (at offset 0x100) + pub fn config_space(&self) -> *mut u64 { + (self as *const _ as usize + CONFIG_SPACE_OFFSET) as _ + } +} + +bitflags! { + /// The device status field. + struct DeviceStatus: u32 { + /// Indicates that the guest OS has found the device and recognized it + /// as a valid virtio device. + const ACKNOWLEDGE = 1; + + /// Indicates that the guest OS knows how to drive the device. + const DRIVER = 2; + + /// Indicates that something went wrong in the guest, and it has given + /// up on the device. This could be an internal error, or the driver + /// didn’t like the device for some reason, or even a fatal error + /// during device operation. + const FAILED = 128; + + /// Indicates that the driver has acknowledged all the features it + /// understands, and feature negotiation is complete. + const FEATURES_OK = 8; + + /// Indicates that the driver is set up and ready to drive the device. + const DRIVER_OK = 4; + + /// Indicates that the device has experienced an error from which it + /// can’t recover. + const DEVICE_NEEDS_RESET = 64; + } +} + +const CONFIG_SPACE_OFFSET: usize = 0x100; + +/// Types of virtio devices. +#[repr(u8)] +#[derive(Debug, Eq, PartialEq)] +#[allow(missing_docs)] +pub enum DeviceType { + Invalid = 0, + Network = 1, + Block = 2, + Console = 3, + EntropySource = 4, + MemoryBallooning = 5, + IoMemory = 6, + Rpmsg = 7, + ScsiHost = 8, + _9P = 9, + Mac80211 = 10, + RprocSerial = 11, + VirtioCAIF = 12, + MemoryBalloon = 13, + GPU = 16, + Timer = 17, + Input = 18, + Socket = 19, + Crypto = 20, + SignalDistributionModule = 21, + Pstore = 22, + IOMMU = 23, + Memory = 24, +} diff --git a/third-party/virtio-drivers/src/input.rs b/third-party/virtio-drivers/src/input.rs new file mode 100644 index 00000000..b2b905cf --- /dev/null +++ b/third-party/virtio-drivers/src/input.rs @@ -0,0 +1,175 @@ +use super::*; +use alloc::boxed::Box; +use bitflags::*; +use log::*; +use volatile::{ReadOnly, WriteOnly}; + +/// Virtual human interface devices such as keyboards, mice and tablets. +/// +/// An instance of the virtio device represents one such input device. +/// Device behavior mirrors that of the evdev layer in Linux, +/// making pass-through implementations on top of evdev easy. +pub struct VirtIOInput<'a> { + header: &'static mut VirtIOHeader, + event_queue: VirtQueue<'a>, + status_queue: VirtQueue<'a>, + event_buf: Box<[InputEvent; 32]>, +} + +impl<'a> VirtIOInput<'a> { + /// Create a new VirtIO-Input driver. + pub fn new(header: &'static mut VirtIOHeader) -> Result { + let mut event_buf = Box::new([InputEvent::default(); QUEUE_SIZE]); + header.begin_init(|features| { + let features = Feature::from_bits_truncate(features); + info!("Device features: {:?}", features); + // negotiate these flags only + let supported_features = Feature::empty(); + (features & supported_features).bits() + }); + + let mut event_queue = VirtQueue::new(header, QUEUE_EVENT, QUEUE_SIZE as u16)?; + let status_queue = VirtQueue::new(header, QUEUE_STATUS, QUEUE_SIZE as u16)?; + for (i, event) in event_buf.as_mut().iter_mut().enumerate() { + let token = event_queue.add(&[], &[event.as_buf_mut()])?; + assert_eq!(token, i as u16); + } + + header.finish_init(); + + Ok(VirtIOInput { + header, + event_queue, + status_queue, + event_buf, + }) + } + + /// Acknowledge interrupt and process events. + pub fn ack_interrupt(&mut self) -> bool { + self.header.ack_interrupt() + } + + /// Pop the pending event. + pub fn pop_pending_event(&mut self) -> Option { + if let Ok((token, _)) = self.event_queue.pop_used() { + let event = &mut self.event_buf[token as usize]; + // requeue + if self.event_queue.add(&[], &[event.as_buf_mut()]).is_ok() { + return Some(*event); + } + } + None + } + + /// Query a specific piece of information by `select` and `subsel`, and write + /// result to `out`, return the result size. + pub fn query_config_select( + &mut self, + select: InputConfigSelect, + subsel: u8, + out: &mut [u8], + ) -> u8 { + let config = unsafe { &mut *(self.header.config_space() as *mut Config) }; + config.select.write(select as u8); + config.subsel.write(subsel); + let size = config.size.read(); + let data = config.data.read(); + out[..size as usize].copy_from_slice(&data[..size as usize]); + size + } +} + +/// Select value used for [`VirtIOInput::query_config_select()`]. +#[repr(u8)] +#[derive(Debug, Clone, Copy)] +pub enum InputConfigSelect { + /// Returns the name of the device, in u.string. subsel is zero. + IdName = 0x01, + /// Returns the serial number of the device, in u.string. subsel is zero. + IdSerial = 0x02, + /// Returns ID information of the device, in u.ids. subsel is zero. + IdDevids = 0x03, + /// Returns input properties of the device, in u.bitmap. subsel is zero. + /// Individual bits in the bitmap correspond to INPUT_PROP_* constants used + /// by the underlying evdev implementation. + PropBits = 0x10, + /// subsel specifies the event type using EV_* constants in the underlying + /// evdev implementation. If size is non-zero the event type is supported + /// and a bitmap of supported event codes is returned in u.bitmap. Individual + /// bits in the bitmap correspond to implementation-defined input event codes, + /// for example keys or pointing device axes. + EvBits = 0x11, + /// subsel specifies the absolute axis using ABS_* constants in the underlying + /// evdev implementation. Information about the axis will be returned in u.abs. + AbsInfo = 0x12, +} + +#[repr(C)] +struct Config { + select: WriteOnly, + subsel: WriteOnly, + size: ReadOnly, + _reversed: [ReadOnly; 5], + data: ReadOnly<[u8; 128]>, +} + +#[repr(C)] +#[derive(Debug)] +struct AbsInfo { + min: u32, + max: u32, + fuzz: u32, + flat: u32, + res: u32, +} + +#[repr(C)] +#[derive(Debug)] +struct DevIDs { + bustype: u16, + vendor: u16, + product: u16, + version: u16, +} + +/// Both queues use the same `virtio_input_event` struct. `type`, `code` and `value` +/// are filled according to the Linux input layer (evdev) interface. +#[repr(C)] +#[derive(Clone, Copy, Debug, Default)] +pub struct InputEvent { + /// Event type. + pub event_type: u16, + /// Event code. + pub code: u16, + /// Event value. + pub value: u32, +} + +unsafe impl AsBuf for InputEvent {} + +bitflags! { + struct Feature: u64 { + // device independent + const NOTIFY_ON_EMPTY = 1 << 24; // legacy + const ANY_LAYOUT = 1 << 27; // legacy + const RING_INDIRECT_DESC = 1 << 28; + const RING_EVENT_IDX = 1 << 29; + const UNUSED = 1 << 30; // legacy + const VERSION_1 = 1 << 32; // detect legacy + + // since virtio v1.1 + const ACCESS_PLATFORM = 1 << 33; + const RING_PACKED = 1 << 34; + const IN_ORDER = 1 << 35; + const ORDER_PLATFORM = 1 << 36; + const SR_IOV = 1 << 37; + const NOTIFICATION_DATA = 1 << 38; + } +} + +const QUEUE_EVENT: usize = 0; +const QUEUE_STATUS: usize = 1; + +// a parameter that can change +const QUEUE_SIZE: usize = 32; diff --git a/third-party/virtio-drivers/src/lib.rs b/third-party/virtio-drivers/src/lib.rs new file mode 100644 index 00000000..48c7118b --- /dev/null +++ b/third-party/virtio-drivers/src/lib.rs @@ -0,0 +1,78 @@ +//! VirtIO guest drivers. + +#![no_std] +#![deny(unused_must_use, missing_docs)] +#![allow(clippy::identity_op)] +#![allow(dead_code)] +#![feature(renamed_spin_loop)] // cause core::hint::spin_loop need this feature eenabled. + +// #[macro_use] +extern crate log; + +extern crate alloc; + +mod blk; +mod console; +mod gpu; +mod hal; +mod header; +mod input; +mod net; +mod queue; + +pub use self::blk::{BlkResp, RespStatus, VirtIOBlk}; +pub use self::console::VirtIOConsole; +pub use self::gpu::VirtIOGpu; +pub use self::header::*; +pub use self::input::{InputConfigSelect, InputEvent, VirtIOInput}; +pub use self::net::VirtIONet; +use self::queue::VirtQueue; +use core::mem::size_of; +use hal::*; + +const PAGE_SIZE: usize = 0x1000; + +/// The type returned by driver methods. +pub type Result = core::result::Result; + +// pub struct Error { +// kind: ErrorKind, +// reason: &'static str, +// } + +/// The error type of VirtIO drivers. +#[derive(Debug, Eq, PartialEq)] +pub enum Error { + /// The buffer is too small. + BufferTooSmall, + /// The device is not ready. + NotReady, + /// The queue is already in use. + AlreadyUsed, + /// Invalid parameter. + InvalidParam, + /// Failed to alloc DMA memory. + DmaError, + /// I/O Error + IoError, +} + +/// Align `size` up to a page. +fn align_up(size: usize) -> usize { + (size + PAGE_SIZE) & !(PAGE_SIZE - 1) +} + +/// Pages of `size`. +fn pages(size: usize) -> usize { + (size + PAGE_SIZE - 1) / PAGE_SIZE +} + +/// Convert a struct into buffer. +unsafe trait AsBuf: Sized { + fn as_buf(&self) -> &[u8] { + unsafe { core::slice::from_raw_parts(self as *const _ as _, size_of::()) } + } + fn as_buf_mut(&mut self) -> &mut [u8] { + unsafe { core::slice::from_raw_parts_mut(self as *mut _ as _, size_of::()) } + } +} diff --git a/third-party/virtio-drivers/src/net.rs b/third-party/virtio-drivers/src/net.rs new file mode 100644 index 00000000..195fc56a --- /dev/null +++ b/third-party/virtio-drivers/src/net.rs @@ -0,0 +1,217 @@ +use core::mem::{size_of, MaybeUninit}; + +use super::*; +use bitflags::*; +use core::hint::spin_loop; +use log::*; +use volatile::{ReadOnly, Volatile}; + +/// The virtio network device is a virtual ethernet card. +/// +/// It has enhanced rapidly and demonstrates clearly how support for new +/// features are added to an existing device. +/// Empty buffers are placed in one virtqueue for receiving packets, and +/// outgoing packets are enqueued into another for transmission in that order. +/// A third command queue is used to control advanced filtering features. +pub struct VirtIONet<'a> { + header: &'static mut VirtIOHeader, + mac: EthernetAddress, + recv_queue: VirtQueue<'a>, + send_queue: VirtQueue<'a>, +} + +impl VirtIONet<'_> { + /// Create a new VirtIO-Net driver. + pub fn new(header: &'static mut VirtIOHeader) -> Result { + header.begin_init(|features| { + let features = Features::from_bits_truncate(features); + info!("Device features {:?}", features); + let supported_features = Features::MAC | Features::STATUS; + (features & supported_features).bits() + }); + // read configuration space + let config = unsafe { &mut *(header.config_space() as *mut Config) }; + let mac = config.mac.read(); + debug!("Got MAC={:?}, status={:?}", mac, config.status.read()); + + let queue_num = 2; // for simplicity + let recv_queue = VirtQueue::new(header, QUEUE_RECEIVE, queue_num)?; + let send_queue = VirtQueue::new(header, QUEUE_TRANSMIT, queue_num)?; + + header.finish_init(); + + Ok(VirtIONet { + header, + mac, + recv_queue, + send_queue, + }) + } + + /// Acknowledge interrupt. + pub fn ack_interrupt(&mut self) -> bool { + self.header.ack_interrupt() + } + + /// Get MAC address. + pub fn mac(&self) -> EthernetAddress { + self.mac + } + + /// Whether can send packet. + pub fn can_send(&self) -> bool { + self.send_queue.available_desc() >= 2 + } + + /// Whether can receive packet. + pub fn can_recv(&self) -> bool { + self.recv_queue.can_pop() + } + + /// Receive a packet. + pub fn recv(&mut self, buf: &mut [u8]) -> Result { + let mut header = MaybeUninit::

::uninit(); + let header_buf = unsafe { (*header.as_mut_ptr()).as_buf_mut() }; + self.recv_queue.add(&[], &[header_buf, buf])?; + self.header.notify(QUEUE_RECEIVE as u32); + while !self.recv_queue.can_pop() { + spin_loop(); + } + + let (_, len) = self.recv_queue.pop_used()?; + // let header = unsafe { header.assume_init() }; + Ok(len as usize - size_of::
()) + } + + /// Send a packet. + pub fn send(&mut self, buf: &[u8]) -> Result { + let header = unsafe { MaybeUninit::
::zeroed().assume_init() }; + self.send_queue.add(&[header.as_buf(), buf], &[])?; + self.header.notify(QUEUE_TRANSMIT as u32); + while !self.send_queue.can_pop() { + spin_loop(); + } + self.send_queue.pop_used()?; + Ok(()) + } +} + +bitflags! { + struct Features: u64 { + /// Device handles packets with partial checksum. + /// This "checksum offload" is a common feature on modern network cards. + const CSUM = 1 << 0; + /// Driver handles packets with partial checksum. + const GUEST_CSUM = 1 << 1; + /// Control channel offloads reconfiguration support. + const CTRL_GUEST_OFFLOADS = 1 << 2; + /// Device maximum MTU reporting is supported. + /// + /// If offered by the device, device advises driver about the value of + /// its maximum MTU. If negotiated, the driver uses mtu as the maximum + /// MTU value. + const MTU = 1 << 3; + /// Device has given MAC address. + const MAC = 1 << 5; + /// Device handles packets with any GSO type. (legacy) + const GSO = 1 << 6; + /// Driver can receive TSOv4. + const GUEST_TSO4 = 1 << 7; + /// Driver can receive TSOv6. + const GUEST_TSO6 = 1 << 8; + /// Driver can receive TSO with ECN. + const GUEST_ECN = 1 << 9; + /// Driver can receive UFO. + const GUEST_UFO = 1 << 10; + /// Device can receive TSOv4. + const HOST_TSO4 = 1 << 11; + /// Device can receive TSOv6. + const HOST_TSO6 = 1 << 12; + /// Device can receive TSO with ECN. + const HOST_ECN = 1 << 13; + /// Device can receive UFO. + const HOST_UFO = 1 << 14; + /// Driver can merge receive buffers. + const MRG_RXBUF = 1 << 15; + /// Configuration status field is available. + const STATUS = 1 << 16; + /// Control channel is available. + const CTRL_VQ = 1 << 17; + /// Control channel RX mode support. + const CTRL_RX = 1 << 18; + /// Control channel VLAN filtering. + const CTRL_VLAN = 1 << 19; + /// + const CTRL_RX_EXTRA = 1 << 20; + /// Driver can send gratuitous packets. + const GUEST_ANNOUNCE = 1 << 21; + /// Device supports multiqueue with automatic receive steering. + const MQ = 1 << 22; + /// Set MAC address through control channel. + const CTL_MAC_ADDR = 1 << 23; + + // device independent + const RING_INDIRECT_DESC = 1 << 28; + const RING_EVENT_IDX = 1 << 29; + const VERSION_1 = 1 << 32; // legacy + } +} + +bitflags! { + struct Status: u16 { + const LINK_UP = 1; + const ANNOUNCE = 2; + } +} + +bitflags! { + struct InterruptStatus : u32 { + const USED_RING_UPDATE = 1 << 0; + const CONFIGURATION_CHANGE = 1 << 1; + } +} + +#[repr(C)] +#[derive(Debug)] +struct Config { + mac: ReadOnly, + status: ReadOnly, +} + +type EthernetAddress = [u8; 6]; + +// virtio 5.1.6 Device Operation +#[repr(C)] +#[derive(Debug)] +struct Header { + flags: Volatile, + gso_type: Volatile, + hdr_len: Volatile, // cannot rely on this + gso_size: Volatile, + csum_start: Volatile, + csum_offset: Volatile, + // payload starts from here +} + +unsafe impl AsBuf for Header {} + +bitflags! { + struct Flags: u8 { + const NEEDS_CSUM = 1; + const DATA_VALID = 2; + const RSC_INFO = 4; + } +} + +#[repr(u8)] +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +enum GsoType { + NONE = 0, + TCPV4 = 1, + UDP = 3, + TCPV6 = 4, + ECN = 0x80, +} + +const QUEUE_RECEIVE: usize = 0; +const QUEUE_TRANSMIT: usize = 1; diff --git a/third-party/virtio-drivers/src/queue.rs b/third-party/virtio-drivers/src/queue.rs new file mode 100644 index 00000000..586760dc --- /dev/null +++ b/third-party/virtio-drivers/src/queue.rs @@ -0,0 +1,261 @@ +use core::mem::size_of; +use core::slice; +use core::sync::atomic::{fence, Ordering}; + +use super::*; +use crate::header::VirtIOHeader; +use bitflags::*; + +use volatile::Volatile; + +/// The mechanism for bulk data transport on virtio devices. +/// +/// Each device can have zero or more virtqueues. +#[repr(C)] +pub struct VirtQueue<'a> { + /// DMA guard + dma: DMA, + /// Descriptor table + desc: &'a mut [Descriptor], + /// Available ring + avail: &'a mut AvailRing, + /// Used ring + used: &'a mut UsedRing, + + /// The index of queue + queue_idx: u32, + /// The size of queue + queue_size: u16, + /// The number of used queues. + num_used: u16, + /// The head desc index of the free list. + free_head: u16, + avail_idx: u16, + last_used_idx: u16, +} + +impl VirtQueue<'_> { + /// Create a new VirtQueue. + pub fn new(header: &mut VirtIOHeader, idx: usize, size: u16) -> Result { + if header.queue_used(idx as u32) { + return Err(Error::AlreadyUsed); + } + if !size.is_power_of_two() || header.max_queue_size() < size as u32 { + return Err(Error::InvalidParam); + } + let layout = VirtQueueLayout::new(size); + // alloc continuous pages + let dma = DMA::new(layout.size / PAGE_SIZE)?; + + header.queue_set(idx as u32, size as u32, PAGE_SIZE as u32, dma.pfn()); + + let desc = + unsafe { slice::from_raw_parts_mut(dma.vaddr() as *mut Descriptor, size as usize) }; + let avail = unsafe { &mut *((dma.vaddr() + layout.avail_offset) as *mut AvailRing) }; + let used = unsafe { &mut *((dma.vaddr() + layout.used_offset) as *mut UsedRing) }; + + // link descriptors together + for i in 0..(size - 1) { + desc[i as usize].next.write(i + 1); + } + + Ok(VirtQueue { + dma, + desc, + avail, + used, + queue_size: size, + queue_idx: idx as u32, + num_used: 0, + free_head: 0, + avail_idx: 0, + last_used_idx: 0, + }) + } + + /// Add buffers to the virtqueue, return a token. + /// + /// Ref: linux virtio_ring.c virtqueue_add + pub fn add(&mut self, inputs: &[&[u8]], outputs: &[&mut [u8]]) -> Result { + if inputs.is_empty() && outputs.is_empty() { + return Err(Error::InvalidParam); + } + if inputs.len() + outputs.len() + self.num_used as usize > self.queue_size as usize { + return Err(Error::BufferTooSmall); + } + + // allocate descriptors from free list + let head = self.free_head; + let mut last = self.free_head; + for input in inputs.iter() { + let desc = &mut self.desc[self.free_head as usize]; + desc.set_buf(input); + desc.flags.write(DescFlags::NEXT); + last = self.free_head; + self.free_head = desc.next.read(); + } + for output in outputs.iter() { + let desc = &mut self.desc[self.free_head as usize]; + desc.set_buf(output); + desc.flags.write(DescFlags::NEXT | DescFlags::WRITE); + last = self.free_head; + self.free_head = desc.next.read(); + } + // set last_elem.next = NULL + { + let desc = &mut self.desc[last as usize]; + let mut flags = desc.flags.read(); + flags.remove(DescFlags::NEXT); + desc.flags.write(flags); + } + self.num_used += (inputs.len() + outputs.len()) as u16; + + let avail_slot = self.avail_idx & (self.queue_size - 1); + self.avail.ring[avail_slot as usize].write(head); + + // write barrier + fence(Ordering::SeqCst); + + // increase head of avail ring + self.avail_idx = self.avail_idx.wrapping_add(1); + self.avail.idx.write(self.avail_idx); + Ok(head) + } + + /// Whether there is a used element that can pop. + pub fn can_pop(&self) -> bool { + self.last_used_idx != self.used.idx.read() + } + + /// The number of free descriptors. + pub fn available_desc(&self) -> usize { + (self.queue_size - self.num_used) as usize + } + + /// Recycle descriptors in the list specified by head. + /// + /// This will push all linked descriptors at the front of the free list. + fn recycle_descriptors(&mut self, mut head: u16) { + let origin_free_head = self.free_head; + self.free_head = head; + loop { + let desc = &mut self.desc[head as usize]; + let flags = desc.flags.read(); + self.num_used -= 1; + if flags.contains(DescFlags::NEXT) { + head = desc.next.read(); + } else { + desc.next.write(origin_free_head); + return; + } + } + } + + /// Get a token from device used buffers, return (token, len). + /// + /// Ref: linux virtio_ring.c virtqueue_get_buf_ctx + pub fn pop_used(&mut self) -> Result<(u16, u32)> { + if !self.can_pop() { + return Err(Error::NotReady); + } + // read barrier + fence(Ordering::SeqCst); + + let last_used_slot = self.last_used_idx & (self.queue_size - 1); + let index = self.used.ring[last_used_slot as usize].id.read() as u16; + let len = self.used.ring[last_used_slot as usize].len.read(); + + self.recycle_descriptors(index); + self.last_used_idx = self.last_used_idx.wrapping_add(1); + + Ok((index, len)) + } + + /// Return size of the queue. + pub fn size(&self) -> u16 { + self.queue_size + } +} + +/// The inner layout of a VirtQueue. +/// +/// Ref: 2.6.2 Legacy Interfaces: A Note on Virtqueue Layout +struct VirtQueueLayout { + avail_offset: usize, + used_offset: usize, + size: usize, +} + +impl VirtQueueLayout { + fn new(queue_size: u16) -> Self { + assert!( + queue_size.is_power_of_two(), + "queue size should be a power of 2" + ); + let queue_size = queue_size as usize; + let desc = size_of::() * queue_size; + let avail = size_of::() * (3 + queue_size); + let used = size_of::() * 3 + size_of::() * queue_size; + VirtQueueLayout { + avail_offset: desc, + used_offset: align_up(desc + avail), + size: align_up(desc + avail) + align_up(used), + } + } +} + +#[repr(C, align(16))] +#[derive(Debug)] +struct Descriptor { + addr: Volatile, + len: Volatile, + flags: Volatile, + next: Volatile, +} + +impl Descriptor { + fn set_buf(&mut self, buf: &[u8]) { + self.addr.write(virt_to_phys(buf.as_ptr() as usize) as u64); + self.len.write(buf.len() as u32); + } +} + +bitflags! { + /// Descriptor flags + struct DescFlags: u16 { + const NEXT = 1; + const WRITE = 2; + const INDIRECT = 4; + } +} + +/// The driver uses the available ring to offer buffers to the device: +/// each ring entry refers to the head of a descriptor chain. +/// It is only written by the driver and read by the device. +#[repr(C)] +#[derive(Debug)] +struct AvailRing { + flags: Volatile, + /// A driver MUST NOT decrement the idx. + idx: Volatile, + ring: [Volatile; 32], // actual size: queue_size + used_event: Volatile, // unused +} + +/// The used ring is where the device returns buffers once it is done with them: +/// it is only written to by the device, and read by the driver. +#[repr(C)] +#[derive(Debug)] +struct UsedRing { + flags: Volatile, + idx: Volatile, + ring: [UsedElem; 32], // actual size: queue_size + avail_event: Volatile, // unused +} + +#[repr(C)] +#[derive(Debug)] +struct UsedElem { + id: Volatile, + len: Volatile, +}