init commit of lab1_2

Makefile

@@ -69,8 +69,8 @@ USER_CPPS 		:= user/*.c
 USER_CPPS  		:= $(wildcard $(USER_CPPS))
 USER_OBJS  		:= $(addprefix $(OBJ_DIR)/, $(patsubst %.c,%.o,$(USER_CPPS)))
 
-USER_TARGET 	:= $(OBJ_DIR)/app_helloworld
 
+USER_TARGET 	:= $(OBJ_DIR)/app_illegal_instruction
 #------------------------targets------------------------
 $(OBJ_DIR):
 	@-mkdir -p $(OBJ_DIR)	

kernel/machine/minit.c

@@ -19,11 +19,16 @@ __attribute__((aligned(16))) char stack0[4096 * NCPU];
 
 // sstart() is the supervisor state entry point defined in kernel/kernel.c
 extern void s_start();
+// M-mode trap entry point, added @lab1_2
+extern void mtrapvec();
 
 // htif is defined in spike_interface/spike_htif.c, marks the availability of HTIF
 extern uint64 htif;
 // g_mem_size is defined in spike_interface/spike_memory.c, size of the emulated memory
 extern uint64 g_mem_size;
+// struct riscv_regs is define in kernel/riscv.h, and g_itrframe is used to save
+// registers when interrupt hapens in M mode. added @lab1_2
+riscv_regs g_itrframe;
 
 //
 // get the information of HTIF (calling interface) and the emulated memory by
@@ -85,6 +90,9 @@ void m_start(uintptr_t hartid, uintptr_t dtb) {
   // init_dtb() is defined above.
   init_dtb(dtb);
 
+  // save the address of trap frame for interrupt in M mode to "mscratch". added @lab1_2
+  write_csr(mscratch, &g_itrframe);
+
   // set previous privilege mode to S (Supervisor), and will enter S mode after 'mret'
   // write_csr is a macro defined in kernel/riscv.h
   write_csr(mstatus, ((read_csr(mstatus) & ~MSTATUS_MPP_MASK) | MSTATUS_MPP_S));
@@ -92,6 +100,9 @@ void m_start(uintptr_t hartid, uintptr_t dtb) {
   // set M Exception Program Counter to sstart, for mret (requires gcc -mcmodel=medany)
   write_csr(mepc, (uint64)s_start);
 
+  // setup trap handling vector for machine mode. added @lab1_2
+  write_csr(mtvec, (uint64)mtrapvec);
+
   // delegate all interrupts and exceptions to supervisor mode.
   // delegate_traps() is defined above.
   delegate_traps();

kernel/machine/mtrap.c

@@ -0,0 +1,50 @@
+#include "kernel/riscv.h"
+#include "kernel/process.h"
+#include "spike_interface/spike_utils.h"
+
+static void handle_instruction_access_fault() { panic("Instruction access fault!"); }
+
+static void handle_load_access_fault() { panic("Load access fault!"); }
+
+static void handle_store_access_fault() { panic("Store/AMO access fault!"); }
+
+static void handle_illegal_instruction() { panic("Illegal instruction!"); }
+
+static void handle_misaligned_load() { panic("Misaligned Load!"); }
+
+static void handle_misaligned_store() { panic("Misaligned AMO!"); }
+
+//
+// handle_mtrap calls a handling function according to the type of a machine mode interrupt (trap).
+//
+void handle_mtrap() {
+  uint64 mcause = read_csr(mcause);
+  switch (mcause) {
+    case CAUSE_FETCH_ACCESS:
+      handle_instruction_access_fault();
+      break;
+    case CAUSE_LOAD_ACCESS:
+      handle_load_access_fault();
+    case CAUSE_STORE_ACCESS:
+      handle_store_access_fault();
+      break;
+    case CAUSE_ILLEGAL_INSTRUCTION:
+      // TODO (lab1_2): call handle_illegal_instruction to implement illegal instruction
+      // interception, and finish lab1_2.
+      panic( "call handle_illegal_instruction to accomplish illegal instruction interception for lab1_2.\n" );
+
+      break;
+    case CAUSE_MISALIGNED_LOAD:
+      handle_misaligned_load();
+      break;
+    case CAUSE_MISALIGNED_STORE:
+      handle_misaligned_store();
+      break;
+
+    default:
+      sprint("machine trap(): unexpected mscause %p\n", mcause);
+      sprint("            mepc=%p mtval=%p\n", read_csr(mepc), read_csr(mtval));
+      panic( "unexpected exception happened in M-mode.\n" );
+      break;
+  }
+}

kernel/machine/mtrap_vector.S

@@ -0,0 +1,41 @@
+#include "util/load_store.S"
+
+#
+# M-mode trap entry point
+#
+.globl mtrapvec
+.align 4
+mtrapvec:
+    # mscratch -> g_itrframe (cf. kernel/machine/minit.c line 94)
+    # swap a0 and mscratch, so that a0 points to interrupt frame,
+    # i.e., [a0] = &g_itrframe
+    csrrw a0, mscratch, a0
+
+    # save the registers in g_itrframe
+    addi t6, a0, 0
+    store_all_registers
+    # save the original content of a0 in g_itrframe
+    csrr t0, mscratch
+    sd t0, 72(a0)
+
+    # switch stack (to use stack0) for the rest of machine mode
+    # trap handling.
+    la sp, stack0
+    li a3, 4096
+    csrr a4, mhartid
+    addi a4, a4, 1
+    mul a3, a3, a4
+    add sp, sp, a3
+
+    # pointing mscratch back to g_itrframe
+    csrw mscratch, a0
+
+    # call machine mode trap handling function
+    call handle_mtrap
+
+    # restore all registers, come back to the status before entering
+    # machine mode handling.
+    csrr t6, mscratch
+    restore_all_registers
+
+    mret

user/app_helloworld.c

@@ -1,17 +0,0 @@
-/*
- * Below is the given application for lab1_1. 
- * 
- * You can build this app (as well as our PKE OS kernel) by command:
- * $ make
- *
- * Or run this app (with the support from PKE OS kernel) by command:
- * $ make run 
- */
-
-#include "user_lib.h"
-
-int main(void) {
-  printu("Hello world!\n");
-
-  exit(0);
-}

user/app_illegal_instruction.c

@@ -0,0 +1,15 @@
+/*
+ * Below is the given application for lab1_2.
+ * This app attempts to issue M-mode instruction in U-mode, and consequently raises an exception.
+ */
+
+#include "user_lib.h"
+#include "util/types.h"
+
+int main(void) {
+  printu("Going to hack the system by running privilege instructions.\n");
+  // we are now in U(user)-mode, but the "csrw" instruction requires M-mode privilege.
+  // Attempting to execute such instruction will raise illegal instruction exception.
+  asm volatile("csrw sscratch, 0");
+  exit(0);
+}