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133 lines
4.8 KiB
133 lines
4.8 KiB
/*
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* Machine-mode C startup codes
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*/
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#include "util/types.h"
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#include "kernel/riscv.h"
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#include "kernel/config.h"
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#include "spike_interface/spike_utils.h"
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//
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// global variables are placed in the .data section.
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// stack0 is the privilege mode stack(s) of the proxy kernel on CPU(s)
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// allocates 4KB stack space for each processor (hart)
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//
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// NCPU is defined to be 1 in kernel/config.h, as we consider only one HART in basic
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// labs.
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//
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__attribute__((aligned(16))) char stack0[4096 * NCPU];
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// sstart() is the supervisor state entry point defined in kernel/kernel.c
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extern void s_start();
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// M-mode trap entry point, added @lab1_2
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extern void mtrapvec();
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// htif is defined in spike_interface/spike_htif.c, marks the availability of HTIF
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extern uint64 htif;
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// g_mem_size is defined in spike_interface/spike_memory.c, size of the emulated memory
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extern uint64 g_mem_size;
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// struct riscv_regs is define in kernel/riscv.h, and g_itrframe is used to save
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// registers when interrupt hapens in M mode. added @lab1_2
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riscv_regs g_itrframe;
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//
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// get the information of HTIF (calling interface) and the emulated memory by
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// parsing the Device Tree Blog (DTB, actually DTS) stored in memory.
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//
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// the role of DTB is similar to that of Device Address Resolution Table (DART)
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// in Intel series CPUs. it records the details of devices and memory of the
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// platform simulated using Spike.
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//
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void init_dtb(uint64 dtb) {
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// defined in spike_interface/spike_htif.c, enabling Host-Target InterFace (HTIF)
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query_htif(dtb);
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if (htif) sprint("HTIF is available!\r\n");
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// defined in spike_interface/spike_memory.c, obtain information about emulated memory
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query_mem(dtb);
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sprint("(Emulated) memory size: %ld MB\n", g_mem_size >> 20);
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}
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//
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// delegate (almost all) interrupts and most exceptions to S-mode.
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// after delegation, syscalls will handled by the PKE OS kernel running in S-mode.
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//
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static void delegate_traps() {
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// supports_extension macro is defined in kernel/riscv.h
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if (!supports_extension('S')) {
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// confirm that our processor supports supervisor mode. abort if it does not.
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sprint("S mode is not supported.\n");
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return;
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}
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// macros used in following two statements are defined in kernel/riscv.h
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uintptr_t interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
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uintptr_t exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_FETCH_PAGE_FAULT) |
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(1U << CAUSE_BREAKPOINT) | (1U << CAUSE_LOAD_PAGE_FAULT) |
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(1U << CAUSE_STORE_PAGE_FAULT) | (1U << CAUSE_USER_ECALL);
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// writes 64-bit values (interrupts and exceptions) to 'mideleg' and 'medeleg' (two
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// priviledged registers of RV64G machine) respectively.
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//
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// write_csr and read_csr are macros defined in kernel/riscv.h
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write_csr(mideleg, interrupts);
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write_csr(medeleg, exceptions);
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assert(read_csr(mideleg) == interrupts);
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assert(read_csr(medeleg) == exceptions);
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}
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//
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// enabling timer interrupt (irq) in Machine mode. added @lab1_3
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//
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void timerinit(uintptr_t hartid) {
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// fire timer irq after TIMER_INTERVAL from now.
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*(uint64*)CLINT_MTIMECMP(hartid) = *(uint64*)CLINT_MTIME + TIMER_INTERVAL;
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// enable machine-mode timer irq in MIE (Machine Interrupt Enable) csr.
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write_csr(mie, read_csr(mie) | MIE_MTIE);
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}
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//
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// m_start: machine mode C entry point.
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//
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void m_start(uintptr_t hartid, uintptr_t dtb) {
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// init the spike file interface (stdin,stdout,stderr)
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// functions with "spike_" prefix are all defined in codes under spike_interface/,
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// sprint is also defined in spike_interface/spike_utils.c
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spike_file_init();
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sprint("In m_start, hartid:%d\n", hartid);
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// init HTIF (Host-Target InterFace) and memory by using the Device Table Blob (DTB)
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// init_dtb() is defined above.
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init_dtb(dtb);
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// save the address of trap frame for interrupt in M mode to "mscratch". added @lab1_2
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write_csr(mscratch, &g_itrframe);
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// set previous privilege mode to S (Supervisor), and will enter S mode after 'mret'
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// write_csr is a macro defined in kernel/riscv.h
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write_csr(mstatus, ((read_csr(mstatus) & ~MSTATUS_MPP_MASK) | MSTATUS_MPP_S));
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// set M Exception Program Counter to sstart, for mret (requires gcc -mcmodel=medany)
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write_csr(mepc, (uint64)s_start);
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// setup trap handling vector for machine mode. added @lab1_2
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write_csr(mtvec, (uint64)mtrapvec);
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// enable machine-mode interrupts. added @lab1_3
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write_csr(mstatus, read_csr(mstatus) | MSTATUS_MIE);
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// delegate all interrupts and exceptions to supervisor mode.
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// delegate_traps() is defined above.
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delegate_traps();
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// also enables interrupt handling in supervisor mode. added @lab1_3
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write_csr(sie, read_csr(sie) | SIE_SEIE | SIE_STIE | SIE_SSIE);
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// init timing. added @lab1_3
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timerinit(hartid);
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// switch to supervisor mode (S mode) and jump to s_start(), i.e., set pc to mepc
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asm volatile("mret");
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}
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