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64 lines
2.0 KiB
64 lines
2.0 KiB
#include "kernel/riscv.h"
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#include "kernel/process.h"
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#include "spike_interface/spike_utils.h"
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static void handle_instruction_access_fault() { panic("Instruction access fault!"); }
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static void handle_load_access_fault() { panic("Load access fault!"); }
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static void handle_store_access_fault() { panic("Store/AMO access fault!"); }
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static void handle_illegal_instruction() { panic("Illegal instruction!"); }
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static void handle_misaligned_load() { panic("Misaligned Load!"); }
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static void handle_misaligned_store() { panic("Misaligned AMO!"); }
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// added @lab1_3
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static void handle_timer() {
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int cpuid = 0;
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// setup the timer fired at next time (TIMER_INTERVAL from now)
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*(uint64*)CLINT_MTIMECMP(cpuid) = *(uint64*)CLINT_MTIMECMP(cpuid) + TIMER_INTERVAL;
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// setup a soft interrupt in sip (S-mode Interrupt Pending) to be handled in S-mode
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write_csr(sip, SIP_SSIP);
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}
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//
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// handle_mtrap calls a handling function according to the type of a machine mode interrupt (trap).
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//
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void handle_mtrap() {
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uint64 mcause = read_csr(mcause);
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switch (mcause) {
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case CAUSE_MTIMER:
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handle_timer();
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break;
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case CAUSE_FETCH_ACCESS:
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handle_instruction_access_fault();
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break;
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case CAUSE_LOAD_ACCESS:
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handle_load_access_fault();
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case CAUSE_STORE_ACCESS:
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handle_store_access_fault();
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break;
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case CAUSE_ILLEGAL_INSTRUCTION:
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// TODO (lab1_2): call handle_illegal_instruction to implement illegal instruction
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// interception, and finish lab1_2.
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panic( "call handle_illegal_instruction to accomplish illegal instruction interception for lab1_2.\n" );
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break;
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case CAUSE_MISALIGNED_LOAD:
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handle_misaligned_load();
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break;
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case CAUSE_MISALIGNED_STORE:
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handle_misaligned_store();
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break;
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default:
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sprint("machine trap(): unexpected mscause %p\n", mcause);
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sprint(" mepc=%p mtval=%p\n", read_csr(mepc), read_csr(mtval));
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panic( "unexpected exception happened in M-mode.\n" );
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break;
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}
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}
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