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@ -1,7 +1,15 @@
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// IR -> MIR 指令选择（Lab5）：
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// - 为每个 IR 值分配虚拟寄存器（GPR / FPR 两类）
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// - alloca -> 栈对象；gep/global -> 地址计算
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// - 完整覆盖算术、比较、分支、调用、访存、类型转换、浮点
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#include "mir/MIR.h"
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#include <cstring>
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#include <functional>
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#include <stdexcept>
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#include <string>
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#include <unordered_map>
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#include <vector>
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#include "ir/IR.h"
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#include "utils/Log.h"
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@ -9,123 +17,509 @@
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namespace mir {
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namespace {
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using ValueSlotMap = std::unordered_map<const ir::Value*, int>;
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int TypeSize(const ir::Type& t) {
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switch (t.GetKind()) {
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case ir::Type::Kind::Int1:
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case ir::Type::Kind::Int32:
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case ir::Type::Kind::Float:
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return 4;
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case ir::Type::Kind::Pointer:
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return 8;
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case ir::Type::Kind::Array:
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return static_cast<int>(t.GetArraySize()) *
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TypeSize(*t.GetElementType());
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default:
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return 8;
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}
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}
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RegClass ClassOf(const ir::Type& t) {
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return t.IsFloat() ? RegClass::FPR : RegClass::GPR;
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}
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int BytesOf(const ir::Type& t) { return t.IsPointer() ? 8 : 4; }
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bool IsPow2(long long v) { return v > 0 && (v & (v - 1)) == 0; }
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int Log2(long long v) {
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int n = 0;
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while ((1LL << n) < v) ++n;
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return n;
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}
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class Lowerer {
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public:
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Lowerer(const ir::Module& m, MachineModule& out) : ir_(m), out_(out) {}
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void Run();
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private:
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const ir::Module& ir_;
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MachineModule& out_;
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MachineFunction* mf_ = nullptr;
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MachineBasicBlock* mbb_ = nullptr;
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std::unordered_map<const ir::Value*, Operand> vmap_;
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std::unordered_map<const ir::BasicBlock*, MachineBasicBlock*> bmap_;
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std::unordered_map<const ir::AllocaInst*, int> allocas_;
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int label_id_ = 0;
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void EmitValueToReg(const ir::Value* value, PhysReg target,
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const ValueSlotMap& slots, MachineBasicBlock& block) {
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if (auto* constant = dynamic_cast<const ir::ConstantInt*>(value)) {
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block.Append(Opcode::MovImm,
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{Operand::Reg(target), Operand::Imm(constant->GetValue())});
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return;
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void Emit(Opcode op, std::vector<Operand> ops, int defs, Cond c = Cond::AL) {
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mbb_->Add(MachineInstr(op, std::move(ops), defs, c));
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}
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Operand NewG(int bytes = 4) { return mf_->NewVRegOp(RegClass::GPR, bytes); }
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Operand NewF() { return mf_->NewVRegOp(RegClass::FPR, 4); }
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auto it = slots.find(value);
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if (it == slots.end()) {
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throw std::runtime_error(
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FormatError("mir", "找不到值对应的栈槽: " + value->GetName()));
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void LowerFunction(const ir::Function& f);
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void LowerBlock(const ir::BasicBlock& bb);
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void LowerInst(const ir::Instruction& inst);
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void LowerInstMem(const ir::Instruction& inst);
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Operand GetReg(const ir::Value* v); // 取值（必要时物化常量/地址）
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Operand MaterializeInt(int v);
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Operand AddressOf(const ir::Value* ptr);
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long long GepConst(const ir::GepInst& gep, Operand* out_base);
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void LowerGlobals();
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Cond ICmpCond(ir::ICmpPredicate p);
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Cond FCmpCond(ir::FCmpPredicate p);
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};
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void Lowerer::Run() {
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LowerGlobals();
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for (const auto& f : ir_.GetFunctions()) {
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if (f->IsDeclaration()) continue;
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LowerFunction(*f);
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}
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}
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block.Append(Opcode::LoadStack,
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{Operand::Reg(target), Operand::FrameIndex(it->second)});
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void Lowerer::LowerGlobals() {
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for (const auto& g : ir_.GetGlobals()) {
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MachineGlobal mg;
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mg.name = g->GetName();
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const ir::Type& vt = *g->GetValueType();
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mg.size = TypeSize(vt);
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mg.align = vt.IsArray() ? 16 : 4;
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mg.is_const = g->IsConst();
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ir::ConstantValue* init = g->GetInitializer();
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mg.zero_init = true;
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int nwords = (mg.size + 3) / 4;
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mg.words.assign(nwords, 0u);
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// 收集初始化位（递归展开数组）。
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std::vector<unsigned> flat;
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std::function<void(ir::ConstantValue*)> walk = [&](ir::ConstantValue* c) {
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if (!c) return;
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if (auto* ci = dynamic_cast<ir::ConstantInt*>(c)) {
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flat.push_back(static_cast<unsigned>(ci->GetValue()));
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} else if (auto* cf = dynamic_cast<ir::ConstantFloat*>(c)) {
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float v = cf->GetValue();
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unsigned bits;
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std::memcpy(&bits, &v, 4);
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flat.push_back(bits);
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} else if (auto* ca = dynamic_cast<ir::ConstantArray*>(c)) {
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for (auto* e : ca->GetElements()) walk(e);
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}
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};
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walk(init);
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for (size_t i = 0; i < flat.size() && i < mg.words.size(); ++i) {
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mg.words[i] = flat[i];
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if (flat[i] != 0) mg.zero_init = false;
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}
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out_.Globals().push_back(std::move(mg));
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}
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}
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void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
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ValueSlotMap& slots) {
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auto& block = function.GetEntry();
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void Lowerer::LowerFunction(const ir::Function& f) {
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out_.Functions().push_back(std::make_unique<MachineFunction>(f.GetName()));
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mf_ = out_.Functions().back().get();
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vmap_.clear();
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bmap_.clear();
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allocas_.clear();
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switch (inst.GetOpcode()) {
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case ir::Opcode::Alloca: {
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slots.emplace(&inst, function.CreateFrameIndex());
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return;
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}
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case ir::Opcode::Store: {
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auto& store = static_cast<const ir::StoreInst&>(inst);
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auto dst = slots.find(store.GetPtr());
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if (dst == slots.end()) {
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throw std::runtime_error(
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FormatError("mir", "暂不支持对非栈变量地址进行写入"));
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}
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EmitValueToReg(store.GetValue(), PhysReg::W8, slots, block);
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block.Append(Opcode::StoreStack,
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{Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst->second)});
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return;
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}
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case ir::Opcode::Load: {
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auto& load = static_cast<const ir::LoadInst&>(inst);
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auto src = slots.find(load.GetPtr());
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if (src == slots.end()) {
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throw std::runtime_error(
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FormatError("mir", "暂不支持对非栈变量地址进行读取"));
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}
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int dst_slot = function.CreateFrameIndex();
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block.Append(Opcode::LoadStack,
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{Operand::Reg(PhysReg::W8), Operand::FrameIndex(src->second)});
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block.Append(Opcode::StoreStack,
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{Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst_slot)});
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slots.emplace(&inst, dst_slot);
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return;
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}
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case ir::Opcode::Add: {
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auto& bin = static_cast<const ir::BinaryInst&>(inst);
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int dst_slot = function.CreateFrameIndex();
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EmitValueToReg(bin.GetLhs(), PhysReg::W8, slots, block);
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EmitValueToReg(bin.GetRhs(), PhysReg::W9, slots, block);
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block.Append(Opcode::AddRR, {Operand::Reg(PhysReg::W8),
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Operand::Reg(PhysReg::W8),
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Operand::Reg(PhysReg::W9)});
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block.Append(Opcode::StoreStack,
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{Operand::Reg(PhysReg::W8), Operand::FrameIndex(dst_slot)});
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slots.emplace(&inst, dst_slot);
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return;
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}
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case ir::Opcode::Ret: {
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auto& ret = static_cast<const ir::ReturnInst&>(inst);
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EmitValueToReg(ret.GetValue(), PhysReg::W0, slots, block);
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block.Append(Opcode::Ret);
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return;
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}
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case ir::Opcode::Sub:
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case ir::Opcode::Mul:
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case ir::Opcode::SDiv:
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case ir::Opcode::SRem:
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case ir::Opcode::FAdd:
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case ir::Opcode::FSub:
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case ir::Opcode::FMul:
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case ir::Opcode::FDiv:
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throw std::runtime_error(FormatError("mir", "暂不支持该二元运算"));
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default:
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break;
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for (const auto& bb : f.GetBlocks()) {
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bmap_[bb.get()] = mf_->CreateBlock(bb->GetName());
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}
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// 记录后继，便于活跃性分析。
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for (const auto& bb : f.GetBlocks()) {
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MachineBasicBlock* mb = bmap_[bb.get()];
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for (auto* s : bb->GetSuccessors()) mb->Succs().push_back(bmap_[s]);
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}
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mbb_ = bmap_[f.GetEntry()];
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// 形参：整型走 x0.., 浮点走 s0..，超过 8 个的从栈读取（测试未用，简化）。
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int ig = 0, fg = 0;
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std::vector<MachineInstr> arg_copies;
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for (size_t i = 0; i < f.GetNumArgs(); ++i) {
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ir::Argument* a = const_cast<ir::Function&>(f).GetArg(i);
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const ir::Type& at = *a->GetType();
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if (at.IsFloat()) {
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Operand dst = NewF();
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arg_copies.push_back(MachineInstr(
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Opcode::FMov,
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{dst, Operand::PReg(fg++, RegClass::FPR, 4)}, 1));
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vmap_[a] = dst;
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} else {
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int bytes = at.IsPointer() ? 8 : 4;
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Operand dst = NewG(bytes);
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arg_copies.push_back(MachineInstr(
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Opcode::Mov, {dst, Operand::PReg(ig++, RegClass::GPR, bytes)}, 1));
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vmap_[a] = dst;
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}
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}
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mf_->SetArgCounts(ig, fg);
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for (auto& mi : arg_copies) mbb_->Add(std::move(mi));
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throw std::runtime_error(FormatError("mir", "暂不支持该 IR 指令"));
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for (const auto& bb : f.GetBlocks()) {
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mbb_ = bmap_[bb.get()];
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LowerBlock(*bb);
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}
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}
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} // namespace
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void Lowerer::LowerBlock(const ir::BasicBlock& bb) {
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for (const auto& inst : bb.GetInstructions()) {
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LowerInst(*inst);
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}
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}
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Operand Lowerer::MaterializeInt(int v) {
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Operand d = NewG(4);
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Emit(Opcode::MovImm, {d, Operand::Imm(v)}, 1);
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return d;
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}
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Operand Lowerer::GetReg(const ir::Value* v) {
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auto it = vmap_.find(v);
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if (it != vmap_.end()) return it->second;
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if (auto* ci = dynamic_cast<const ir::ConstantInt*>(v)) {
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return MaterializeInt(ci->GetValue());
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}
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if (auto* cf = dynamic_cast<const ir::ConstantFloat*>(v)) {
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float f = cf->GetValue();
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unsigned bits;
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std::memcpy(&bits, &f, 4);
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Operand d = NewF();
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Emit(Opcode::FMovImm, {d, Operand::Imm(bits)}, 1);
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return d;
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}
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// 兜底：未知值视为 0。
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return MaterializeInt(0);
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}
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std::unique_ptr<MachineFunction> LowerToMIR(const ir::Module& module) {
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DefaultContext();
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// 计算 gep 的常量字节偏移；返回偏移并把基址写入 *out_base。
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// 若存在变量下标，直接生成地址计算指令并把最终地址放入 *out_base、返回 0。
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long long Lowerer::GepConst(const ir::GepInst& gep, Operand* out_base) {
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Operand base = AddressOf(gep.GetBasePtr());
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// 推断逐层元素类型：基址指针指向的类型。
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std::shared_ptr<ir::Type> cur = gep.GetBasePtr()->GetType()->GetElementType();
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long long const_off = 0;
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Operand addr = base;
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bool addr_dirty = false;
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const auto& idxs = gep.GetIndices();
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for (size_t i = 0; i < idxs.size(); ++i) {
|
|
|
|
|
int elem_size = cur ? TypeSize(*cur) : 4;
|
|
|
|
|
ir::Value* iv = idxs[i];
|
|
|
|
|
if (auto* ci = dynamic_cast<ir::ConstantInt*>(iv)) {
|
|
|
|
|
const_off += static_cast<long long>(ci->GetValue()) * elem_size;
|
|
|
|
|
} else {
|
|
|
|
|
// addr += index * elem_size
|
|
|
|
|
Operand idx = GetReg(iv);
|
|
|
|
|
Operand idx64 = NewG(8);
|
|
|
|
|
Emit(Opcode::Sxtw, {idx64, idx}, 1);
|
|
|
|
|
Operand scaled = NewG(8);
|
|
|
|
|
if (IsPow2(elem_size)) {
|
|
|
|
|
Emit(Opcode::LslImm, {scaled, idx64, Operand::Imm(Log2(elem_size))}, 1);
|
|
|
|
|
} else {
|
|
|
|
|
Operand sz = NewG(8);
|
|
|
|
|
Emit(Opcode::MovImm, {sz, Operand::Imm(elem_size)}, 1);
|
|
|
|
|
Emit(Opcode::Mul, {scaled, idx64, sz}, 1);
|
|
|
|
|
}
|
|
|
|
|
Operand na = NewG(8);
|
|
|
|
|
Emit(Opcode::Add, {na, addr, scaled}, 1);
|
|
|
|
|
addr = na;
|
|
|
|
|
addr_dirty = true;
|
|
|
|
|
}
|
|
|
|
|
if (cur && cur->IsArray()) cur = cur->GetElementType();
|
|
|
|
|
}
|
|
|
|
|
if (addr_dirty) {
|
|
|
|
|
*out_base = addr;
|
|
|
|
|
return const_off;
|
|
|
|
|
}
|
|
|
|
|
*out_base = base;
|
|
|
|
|
return const_off;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// 返回某个指针型 IR 值对应的“地址”寄存器。
|
|
|
|
|
Operand Lowerer::AddressOf(const ir::Value* ptr) {
|
|
|
|
|
auto it = vmap_.find(ptr);
|
|
|
|
|
if (it != vmap_.end()) return it->second;
|
|
|
|
|
if (auto* a = dynamic_cast<const ir::AllocaInst*>(ptr)) {
|
|
|
|
|
int idx;
|
|
|
|
|
auto ai = allocas_.find(a);
|
|
|
|
|
if (ai == allocas_.end()) {
|
|
|
|
|
idx = mf_->CreateStackObject(TypeSize(*a->GetAllocatedType()),
|
|
|
|
|
a->GetAllocatedType()->IsArray() ? 16 : 4);
|
|
|
|
|
allocas_[a] = idx;
|
|
|
|
|
} else {
|
|
|
|
|
idx = ai->second;
|
|
|
|
|
}
|
|
|
|
|
Operand d = NewG(8);
|
|
|
|
|
Emit(Opcode::AddrFrame, {d, Operand::Frame(idx)}, 1);
|
|
|
|
|
vmap_[ptr] = d;
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
// 全局变量
|
|
|
|
|
Operand d = NewG(8);
|
|
|
|
|
Emit(Opcode::AddrGlobal, {d, Operand::Global(ptr->GetName())}, 1);
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (module.GetFunctions().size() != 1) {
|
|
|
|
|
throw std::runtime_error(FormatError("mir", "暂不支持多个函数"));
|
|
|
|
|
Cond Lowerer::ICmpCond(ir::ICmpPredicate p) {
|
|
|
|
|
switch (p) {
|
|
|
|
|
case ir::ICmpPredicate::Eq: return Cond::EQ;
|
|
|
|
|
case ir::ICmpPredicate::Ne: return Cond::NE;
|
|
|
|
|
case ir::ICmpPredicate::Slt: return Cond::LT;
|
|
|
|
|
case ir::ICmpPredicate::Sle: return Cond::LE;
|
|
|
|
|
case ir::ICmpPredicate::Sgt: return Cond::GT;
|
|
|
|
|
case ir::ICmpPredicate::Sge: return Cond::GE;
|
|
|
|
|
}
|
|
|
|
|
return Cond::EQ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const auto& func = *module.GetFunctions().front();
|
|
|
|
|
if (func.GetName() != "main") {
|
|
|
|
|
throw std::runtime_error(FormatError("mir", "暂不支持非 main 函数"));
|
|
|
|
|
Cond Lowerer::FCmpCond(ir::FCmpPredicate p) {
|
|
|
|
|
switch (p) {
|
|
|
|
|
case ir::FCmpPredicate::Oeq: return Cond::EQ;
|
|
|
|
|
case ir::FCmpPredicate::One: return Cond::NE;
|
|
|
|
|
case ir::FCmpPredicate::Olt: return Cond::MI;
|
|
|
|
|
case ir::FCmpPredicate::Ole: return Cond::LS;
|
|
|
|
|
case ir::FCmpPredicate::Ogt: return Cond::GT;
|
|
|
|
|
case ir::FCmpPredicate::Oge: return Cond::GE;
|
|
|
|
|
}
|
|
|
|
|
return Cond::EQ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
auto machine_func = std::make_unique<MachineFunction>(func.GetName());
|
|
|
|
|
ValueSlotMap slots;
|
|
|
|
|
const auto* entry = func.GetEntry();
|
|
|
|
|
if (!entry) {
|
|
|
|
|
throw std::runtime_error(FormatError("mir", "IR 函数缺少入口基本块"));
|
|
|
|
|
void Lowerer::LowerInst(const ir::Instruction& inst) {
|
|
|
|
|
using ir::Opcode;
|
|
|
|
|
switch (inst.GetOpcode()) {
|
|
|
|
|
case Opcode::Add:
|
|
|
|
|
case Opcode::Sub:
|
|
|
|
|
case Opcode::Mul:
|
|
|
|
|
case Opcode::SDiv:
|
|
|
|
|
case Opcode::SRem: {
|
|
|
|
|
auto& b = static_cast<const ir::BinaryInst&>(inst);
|
|
|
|
|
Operand l = GetReg(b.GetLhs());
|
|
|
|
|
Operand r = GetReg(b.GetRhs());
|
|
|
|
|
Operand d = NewG(4);
|
|
|
|
|
mir::Opcode mop = mir::Opcode::Add;
|
|
|
|
|
if (inst.GetOpcode() == Opcode::Add) mop = mir::Opcode::Add;
|
|
|
|
|
else if (inst.GetOpcode() == Opcode::Sub) mop = mir::Opcode::Sub;
|
|
|
|
|
else if (inst.GetOpcode() == Opcode::Mul) mop = mir::Opcode::Mul;
|
|
|
|
|
else mop = mir::Opcode::SDiv;
|
|
|
|
|
if (inst.GetOpcode() == Opcode::SRem) {
|
|
|
|
|
Operand q = NewG(4);
|
|
|
|
|
Emit(mir::Opcode::SDiv, {q, l, r}, 1);
|
|
|
|
|
Emit(mir::Opcode::MSub, {d, q, r, l}, 1); // d = l - q*r
|
|
|
|
|
} else {
|
|
|
|
|
Emit(mop, {d, l, r}, 1);
|
|
|
|
|
}
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::FAdd:
|
|
|
|
|
case Opcode::FSub:
|
|
|
|
|
case Opcode::FMul:
|
|
|
|
|
case Opcode::FDiv: {
|
|
|
|
|
auto& b = static_cast<const ir::BinaryInst&>(inst);
|
|
|
|
|
Operand l = GetReg(b.GetLhs());
|
|
|
|
|
Operand r = GetReg(b.GetRhs());
|
|
|
|
|
Operand d = NewF();
|
|
|
|
|
mir::Opcode mop = mir::Opcode::FAdd;
|
|
|
|
|
if (inst.GetOpcode() == Opcode::FSub) mop = mir::Opcode::FSub;
|
|
|
|
|
else if (inst.GetOpcode() == Opcode::FMul) mop = mir::Opcode::FMul;
|
|
|
|
|
else if (inst.GetOpcode() == Opcode::FDiv) mop = mir::Opcode::FDiv;
|
|
|
|
|
Emit(mop, {d, l, r}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::SIToFP: {
|
|
|
|
|
auto& c = static_cast<const ir::CastInst&>(inst);
|
|
|
|
|
Operand s = GetReg(c.GetValue());
|
|
|
|
|
Operand d = NewF();
|
|
|
|
|
Emit(mir::Opcode::SCvtF, {d, s}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::FPToSI: {
|
|
|
|
|
auto& c = static_cast<const ir::CastInst&>(inst);
|
|
|
|
|
Operand s = GetReg(c.GetValue());
|
|
|
|
|
Operand d = NewG(4);
|
|
|
|
|
Emit(mir::Opcode::FCvtZS, {d, s}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::ZExt: {
|
|
|
|
|
auto& c = static_cast<const ir::CastInst&>(inst);
|
|
|
|
|
Operand s = GetReg(c.GetValue());
|
|
|
|
|
Operand d = NewG(4);
|
|
|
|
|
Emit(mir::Opcode::Mov, {d, s}, 1); // i1->i32：cset 已产出 0/1
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::ICmp: {
|
|
|
|
|
auto& c = static_cast<const ir::ICmpInst&>(inst);
|
|
|
|
|
Operand l = GetReg(c.GetLhs());
|
|
|
|
|
Operand r = GetReg(c.GetRhs());
|
|
|
|
|
Emit(mir::Opcode::Cmp, {l, r}, 0);
|
|
|
|
|
Operand d = NewG(4);
|
|
|
|
|
Emit(mir::Opcode::CSet, {d}, 1, ICmpCond(c.GetPredicate()));
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::FCmp: {
|
|
|
|
|
auto& c = static_cast<const ir::FCmpInst&>(inst);
|
|
|
|
|
Operand l = GetReg(c.GetLhs());
|
|
|
|
|
Operand r = GetReg(c.GetRhs());
|
|
|
|
|
Emit(mir::Opcode::FCmp, {l, r}, 0);
|
|
|
|
|
Operand d = NewG(4);
|
|
|
|
|
Emit(mir::Opcode::CSet, {d}, 1, FCmpCond(c.GetPredicate()));
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default:
|
|
|
|
|
LowerInstMem(inst);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (const auto& inst : entry->GetInstructions()) {
|
|
|
|
|
LowerInstruction(*inst, *machine_func, slots);
|
|
|
|
|
void Lowerer::LowerInstMem(const ir::Instruction& inst) {
|
|
|
|
|
using ir::Opcode;
|
|
|
|
|
switch (inst.GetOpcode()) {
|
|
|
|
|
case Opcode::Alloca: {
|
|
|
|
|
auto& a = static_cast<const ir::AllocaInst&>(inst);
|
|
|
|
|
int idx = mf_->CreateStackObject(TypeSize(*a.GetAllocatedType()),
|
|
|
|
|
a.GetAllocatedType()->IsArray() ? 16 : 4);
|
|
|
|
|
allocas_[&a] = idx;
|
|
|
|
|
Operand d = NewG(8);
|
|
|
|
|
Emit(mir::Opcode::AddrFrame, {d, Operand::Frame(idx)}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::Load: {
|
|
|
|
|
auto& ld = static_cast<const ir::LoadInst&>(inst);
|
|
|
|
|
Operand base;
|
|
|
|
|
long long off = 0;
|
|
|
|
|
if (auto* gep = dynamic_cast<const ir::GepInst*>(ld.GetPtr())) {
|
|
|
|
|
off = GepConst(*gep, &base);
|
|
|
|
|
} else {
|
|
|
|
|
base = AddressOf(ld.GetPtr());
|
|
|
|
|
}
|
|
|
|
|
bool is_f = inst.GetType()->IsFloat();
|
|
|
|
|
Operand d = is_f ? NewF() : NewG(BytesOf(*inst.GetType()));
|
|
|
|
|
Emit(mir::Opcode::Ldr, {d, base, Operand::Imm(off)}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::Store: {
|
|
|
|
|
auto& st = static_cast<const ir::StoreInst&>(inst);
|
|
|
|
|
Operand val = GetReg(st.GetValue());
|
|
|
|
|
Operand base;
|
|
|
|
|
long long off = 0;
|
|
|
|
|
if (auto* gep = dynamic_cast<const ir::GepInst*>(st.GetPtr())) {
|
|
|
|
|
off = GepConst(*gep, &base);
|
|
|
|
|
} else {
|
|
|
|
|
base = AddressOf(st.GetPtr());
|
|
|
|
|
}
|
|
|
|
|
Emit(mir::Opcode::Str, {val, base, Operand::Imm(off)}, 0);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::Gep: {
|
|
|
|
|
auto& gep = static_cast<const ir::GepInst&>(inst);
|
|
|
|
|
Operand base;
|
|
|
|
|
long long off = GepConst(gep, &base);
|
|
|
|
|
Operand d = NewG(8);
|
|
|
|
|
if (off == 0) {
|
|
|
|
|
Emit(mir::Opcode::Mov, {d, base}, 1);
|
|
|
|
|
} else {
|
|
|
|
|
Emit(mir::Opcode::AddImm, {d, base, Operand::Imm(off)}, 1);
|
|
|
|
|
}
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::Call: {
|
|
|
|
|
auto& call = static_cast<const ir::CallInst&>(inst);
|
|
|
|
|
// 先把所有实参算入虚拟寄存器，再连续搬入物理参数寄存器，
|
|
|
|
|
// 避免计算后续实参时分配器复用 x0..x7 破坏已就绪的参数。
|
|
|
|
|
std::vector<Operand> vals;
|
|
|
|
|
for (auto* arg : call.GetArgs()) vals.push_back(GetReg(arg));
|
|
|
|
|
int ig = 0, fg = 0;
|
|
|
|
|
std::vector<Operand> arg_uses;
|
|
|
|
|
for (size_t i = 0; i < call.GetArgs().size(); ++i) {
|
|
|
|
|
ir::Value* arg = call.GetArgs()[i];
|
|
|
|
|
if (arg->GetType()->IsFloat()) {
|
|
|
|
|
Operand p = Operand::PReg(fg++, RegClass::FPR, 4);
|
|
|
|
|
Emit(mir::Opcode::FMov, {p, vals[i]}, 1);
|
|
|
|
|
arg_uses.push_back(p);
|
|
|
|
|
} else {
|
|
|
|
|
int bytes = arg->GetType()->IsPointer() ? 8 : 4;
|
|
|
|
|
Operand p = Operand::PReg(ig++, RegClass::GPR, bytes);
|
|
|
|
|
Emit(mir::Opcode::Mov, {p, vals[i]}, 1);
|
|
|
|
|
arg_uses.push_back(p);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
std::vector<Operand> ops;
|
|
|
|
|
ops.push_back(Operand::Global(call.GetCallee()->GetName()));
|
|
|
|
|
for (auto& u : arg_uses) ops.push_back(u);
|
|
|
|
|
Emit(mir::Opcode::Bl, ops, 0);
|
|
|
|
|
if (!inst.GetType()->IsVoid()) {
|
|
|
|
|
if (inst.GetType()->IsFloat()) {
|
|
|
|
|
Operand d = NewF();
|
|
|
|
|
Emit(mir::Opcode::FMov, {d, Operand::PReg(0, RegClass::FPR, 4)}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
} else {
|
|
|
|
|
Operand d = NewG(BytesOf(*inst.GetType()));
|
|
|
|
|
Emit(mir::Opcode::Mov,
|
|
|
|
|
{d, Operand::PReg(0, RegClass::GPR, d.GetBytes())}, 1);
|
|
|
|
|
vmap_[&inst] = d;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::Br: {
|
|
|
|
|
auto& br = static_cast<const ir::BranchInst&>(inst);
|
|
|
|
|
Emit(mir::Opcode::B, {Operand::Label(br.GetDest()->GetName())}, 0);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case Opcode::CondBr: {
|
|
|
|
|
auto& cbr = static_cast<const ir::CondBrInst&>(inst);
|
|
|
|
|
Operand c = GetReg(cbr.GetCond());
|
|
|
|
|
Emit(mir::Opcode::CmpImm, {c, Operand::Imm(0)}, 0);
|
|
|
|
|
Emit(mir::Opcode::BCond, {Operand::Label(cbr.GetTrueDest()->GetName())}, 0,
|
|
|
|
|
Cond::NE);
|
|
|
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Emit(mir::Opcode::B, {Operand::Label(cbr.GetFalseDest()->GetName())}, 0);
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break;
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}
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case Opcode::Ret: {
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auto& ret = static_cast<const ir::ReturnInst&>(inst);
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if (ret.HasReturnValue()) {
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Operand v = GetReg(ret.GetValue());
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|
if (ret.GetValue()->GetType()->IsFloat()) {
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|
Emit(mir::Opcode::FMov, {Operand::PReg(0, RegClass::FPR, 4), v}, 1);
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} else {
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|
Emit(mir::Opcode::Mov,
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{Operand::PReg(0, RegClass::GPR, v.GetBytes()), v}, 1);
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}
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}
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|
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Emit(mir::Opcode::Ret, {}, 0);
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|
|
|
|
break;
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|
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}
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|
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|
default:
|
|
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|
|
break;
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|
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}
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|
|
}
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return machine_func;
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|
} // namespace
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std::unique_ptr<MachineModule> LowerToMIR(const ir::Module& module) {
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|
|
auto out = std::make_unique<MachineModule>();
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|
|
|
|
Lowerer lo(module, *out);
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lo.Run();
|
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|
return out;
|
|
|
|
|
}
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} // namespace mir
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毕恩凯
7 days ago