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#include "mir/MIR.h"
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#include <stdexcept>
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#include "utils/Log.h"
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namespace mir {
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namespace {
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bool IsAllowedReg(PhysReg reg) {
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switch (reg) {
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case PhysReg::W0:
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case PhysReg::W1:
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case PhysReg::W2:
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case PhysReg::W3:
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case PhysReg::W4:
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case PhysReg::W5:
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case PhysReg::W6:
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case PhysReg::W7:
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case PhysReg::W8:
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case PhysReg::W9:
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case PhysReg::W10:
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case PhysReg::X0:
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case PhysReg::X1:
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case PhysReg::X2:
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case PhysReg::X3:
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case PhysReg::X4:
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case PhysReg::X5:
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case PhysReg::X6:
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case PhysReg::X7:
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case PhysReg::X8:
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case PhysReg::X9:
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case PhysReg::X10:
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case PhysReg::X29:
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case PhysReg::X30:
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case PhysReg::SP:
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case PhysReg::S0:
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case PhysReg::S1:
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case PhysReg::S2:
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case PhysReg::S3:
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case PhysReg::S4:
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case PhysReg::S5:
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case PhysReg::S6:
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case PhysReg::S7:
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case PhysReg::S8:
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case PhysReg::S9:
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case PhysReg::S10:
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return true;
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}
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return false;
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}
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} // namespace
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void RunRegAlloc(MachineFunction& function) {
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for (const auto& bb_ptr : function.GetBlocks()) {
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for (const auto& inst : bb_ptr->GetInstructions()) {
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for (const auto& operand : inst.GetOperands()) {
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if (operand.GetKind() == Operand::Kind::Reg &&
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!IsAllowedReg(operand.GetReg())) {
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throw std::runtime_error(FormatError("mir", "寄存器分配失败"));
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}
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}
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}
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}
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}
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} // namespace mir
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