From f966869fb196b0428e0a0765e67545ce1e4da1ba Mon Sep 17 00:00:00 2001
From: mxr <>
Date: Wed, 8 Apr 2026 22:38:36 +0800
Subject: [PATCH] =?UTF-8?q?feat(mir)=E6=89=A9=E5=B1=95=E6=B1=87=E7=BC=96?=
 =?UTF-8?q?=E6=8C=87=E4=BB=A4=E7=94=9F=E6=88=90?=
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---
 src/mir/AsmPrinter.cpp | 133 +++++++++++++++++++++++++++++++++++++++++
 src/mir/RegAlloc.cpp   |   4 +-
 2 files changed, 135 insertions(+), 2 deletions(-)

diff --git a/src/mir/AsmPrinter.cpp b/src/mir/AsmPrinter.cpp
index 4d1f65f..089e055 100644
--- a/src/mir/AsmPrinter.cpp
+++ b/src/mir/AsmPrinter.cpp
@@ -22,6 +22,12 @@ void PrintStackAccess(std::ostream& os, const char* mnemonic, PhysReg reg,
      << "]\n";
 }
 
+void PrintStackPairAccess(std::ostream& os, const char* mnemonic, PhysReg reg0, PhysReg reg1,
+                      int offset) {
+  os << "  " << mnemonic << " " << PhysRegName(reg0) << " " << PhysRegName(reg1) << ", [x29, #" << offset
+     << "]\n";
+}
+
 }  // namespace
 
 void PrintAsm(const MachineFunction& function, std::ostream& os) {
@@ -50,6 +56,10 @@ void PrintAsm(const MachineFunction& function, std::ostream& os) {
         os << "  mov " << PhysRegName(ops.at(0).GetReg()) << ", #"
            << ops.at(1).GetImm() << "\n";
         break;
+      case Opcode::MovReg:
+        os << "  mov " << PhysRegName(ops.at(0).GetReg())
+           << PhysRegName(ops.at(1).GetReg()) << "\n";
+        break;
       case Opcode::LoadStack: {
         const auto& slot = GetFrameSlot(function, ops.at(1));
         PrintStackAccess(os, "ldur", ops.at(0).GetReg(), slot.offset);
@@ -60,14 +70,137 @@ void PrintAsm(const MachineFunction& function, std::ostream& os) {
         PrintStackAccess(os, "stur", ops.at(0).GetReg(), slot.offset);
         break;
       }
+      case Opcode::LoadStackPair: {
+        PrintStackPairAccess(os, "ldp", ops.at(0).GetReg(), ops.at(1).GetReg(), 16);
+        break;
+      }
+      case Opcode::StoreStackPair: {
+        PrintStackPairAccess(os, "stp", ops.at(0).GetReg(), ops.at(1).GetReg(), -16);
+        break;
+      }
       case Opcode::AddRR:
         os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", "
            << PhysRegName(ops.at(1).GetReg()) << ", "
            << PhysRegName(ops.at(2).GetReg()) << "\n";
         break;
+      case Opcode::AddRI:
+        os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", #"
+           << ops.at(2).GetImm() << "\n";
+        break;
+      case Opcode::SubRR:
+        os << "  sub " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::SubRI:
+        os << "  sub " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", #"
+           << ops.at(2).GetImm() << "\n";
+        break;
+      case Opcode::MulRR:
+        os << "  mul " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::SDivRR:
+        os << "  sdiv " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;      
+      case Opcode::UDivRR:
+        os << "  udiv " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::FAddRR:
+        os << "  fadd " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::FSubRR:
+        os << "  fsub " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::FMulRR:
+        os << "  fmul " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::FDivRR:
+        os << "  fdiv " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break; 
+      case Opcode::CmpRR:
+        os << "  cmp " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << "\n";
+        break;
+      case Opcode::CmpRI:
+        os << "  cmp " << PhysRegName(ops.at(0).GetReg()) << ", #"
+           << ops.at(1).GetImm() << "\n";
+        break;
+      case Opcode::FCmpRR:
+        os << "  fcmp " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << "\n";
+        break;
+      case Opcode::SIToFP:
+        os << "  scvtf " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << "\n";
+        break;
+      case Opcode::FPToSI:
+        os << "  fcvtzs " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << "\n";
+        break;
+      case Opcode::ZExt:
+        os << "  and " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", #1\n";
+        break;
+      case Opcode::AndRR:
+        os << "  and " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::OrRR:
+        os << "  orr " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::EorRR:
+        os << "  eor " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::LslRR:
+        os << "  lsl " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::LsrRR:
+        os << "  lsr " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::AsrRR:
+        os << "  asr " << PhysRegName(ops.at(0).GetReg()) << ", "
+           << PhysRegName(ops.at(1).GetReg()) << ", "
+           << PhysRegName(ops.at(2).GetReg()) << "\n";
+        break;
+      case Opcode::Nop:
+        os << "  nop \n";
+        break;
+      // TODO: 控制流
+      case Opcode::B:
+        break;
+      case Opcode::BCond:
+        break;
+      case Opcode::Call:
+        break;
       case Opcode::Ret:
         os << "  ret\n";
         break;
+      
     }
   }
 
diff --git a/src/mir/RegAlloc.cpp b/src/mir/RegAlloc.cpp
index 5dc5d2b..972eac5 100644
--- a/src/mir/RegAlloc.cpp
+++ b/src/mir/RegAlloc.cpp
@@ -12,8 +12,8 @@ bool IsAllowedReg(PhysReg reg) {
     case PhysReg::W0:
     case PhysReg::W8:
     case PhysReg::W9:
-    case PhysReg::X29:
-    case PhysReg::X30:
+    case PhysReg::X29:  //FP = X29 帧指针
+    case PhysReg::X30:  //LR = X30 链接寄存器
     case PhysReg::SP:
       return true;
   }