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#include "mir/MIR.h"
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#include <cstring>
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#include <stdexcept>
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#include <unordered_map>
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#include <set>
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#include "ir/IR.h"
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#include "utils/Log.h"
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//#define DEBUG_Lower
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#ifdef DEBUG_Lower
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#include <iostream>
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#define DEBUG_MSG(msg) std::cerr << "[Lower Debug] " << msg << std::endl
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#else
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#define DEBUG_MSG(msg) ((void)0)
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#endif
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namespace mir {
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namespace {
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// ========== VReg 类型 ==========
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enum class VRegType { kInt32, kInt64, kFloat32 };
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// ========== VReg 上下文：管理虚拟寄存器分配和 IR Value 映射 ==========
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struct VRegContext {
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int next_vreg = 1;
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std::unordered_map<const ir::Value*, int> value_to_vreg;
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std::unordered_map<int, VRegType> vreg_types;
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int NewVReg(VRegType type) {
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int id = next_vreg++;
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vreg_types[id] = type;
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return id;
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}
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VRegType GetType(int vreg) const {
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auto it = vreg_types.find(vreg);
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return it != vreg_types.end() ? it->second : VRegType::kInt32;
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}
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bool IsFloat(int vreg) const {
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auto it = vreg_types.find(vreg);
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return it != vreg_types.end() && it->second == VRegType::kFloat32;
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}
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bool IsPointer(int vreg) const {
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auto it = vreg_types.find(vreg);
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return it != vreg_types.end() && it->second == VRegType::kInt64;
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}
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void SetVReg(const ir::Value* value, int vreg) {
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value_to_vreg[value] = vreg;
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}
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int GetVReg(const ir::Value* value) const {
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auto it = value_to_vreg.find(value);
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return it != value_to_vreg.end() ? it->second : -1;
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}
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bool HasVReg(const ir::Value* value) const {
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return value_to_vreg.count(value) > 0;
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}
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};
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// ========== 辅助：判断类型 ==========
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inline bool IsInt32Type(const ir::Type* type) {
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return type && type->IsInt32() && type->Size() == 4;
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}
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static uint32_t FloatToBits(float f) {
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uint32_t bits;
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memcpy(&bits, &f, sizeof(bits));
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return bits;
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}
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int GetTypeSize(const ir::Type* type) {
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if (!type) return 4;
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size_t size = type->Size();
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return size > 0 ? static_cast<int>(size) : 4;
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}
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VRegType GetVRegTypeForIRType(const ir::Type* type) {
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if (!type) return VRegType::kInt32;
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if (type->IsFloat()) return VRegType::kFloat32;
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if (type->IsPtrInt32() || type->IsPtrFloat() || type->IsPtrInt1() || type->IsArray())
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return VRegType::kInt64;
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return VRegType::kInt32;
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}
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// ========== 辅助：记录 MachineInstr 的 def/use ==========
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void RecordDefUse(MachineInstr& instr, int def, std::initializer_list<int> uses) {
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if (def > 0) instr.AddDef(def);
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for (int u : uses) {
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if (u > 0) instr.AddUse(u);
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}
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}
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void RecordDefUseVec(MachineInstr& instr, const std::vector<int>& defs,
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const std::vector<int>& uses) {
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for (int d : defs) instr.AddDef(d);
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for (int u : uses) instr.AddUse(u);
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}
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// ========== 辅助：发射立即数到虚拟寄存器 ==========
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void EmitMovImm(int vreg, uint32_t imm, MachineBasicBlock& block) {
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auto isLegalMovImm = [](uint32_t v) -> bool {
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return (v & 0xFFFF) == v || (v & 0xFFFF0000) == v;
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};
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if (isLegalMovImm(imm)) {
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auto& instr = block.Append(Opcode::MovImm,
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{Operand::VReg(vreg), Operand::Imm(static_cast<int64_t>(imm))});
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instr.AddDef(vreg);
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} else {
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uint16_t low = imm & 0xFFFF;
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uint16_t high = (imm >> 16) & 0xFFFF;
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auto& i1 = block.Append(Opcode::MovImm,
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{Operand::VReg(vreg), Operand::Imm(low)});
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i1.AddDef(vreg);
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if (high != 0) {
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auto& i2 = block.Append(Opcode::Movk,
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{Operand::VReg(vreg), Operand::Imm(high), Operand::Imm(16)});
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i2.AddDef(vreg);
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i2.AddUse(vreg);
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}
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}
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}
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void EmitMovImm64(int vreg, uint64_t imm, MachineBasicBlock& block) {
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uint16_t part0 = imm & 0xFFFF;
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uint16_t part1 = (imm >> 16) & 0xFFFF;
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uint16_t part2 = (imm >> 32) & 0xFFFF;
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uint16_t part3 = (imm >> 48) & 0xFFFF;
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auto& i1 = block.Append(Opcode::MovImm,
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{Operand::VReg(vreg), Operand::Imm(part0)});
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i1.AddDef(vreg);
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if (part1 != 0) {
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auto& i2 = block.Append(Opcode::Movk,
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{Operand::VReg(vreg), Operand::Imm(part1), Operand::Imm(16)});
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i2.AddDef(vreg);
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i2.AddUse(vreg);
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}
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if (part2 != 0) {
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auto& i3 = block.Append(Opcode::Movk,
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{Operand::VReg(vreg), Operand::Imm(part2), Operand::Imm(32)});
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i3.AddDef(vreg);
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i3.AddUse(vreg);
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}
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if (part3 != 0) {
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auto& i4 = block.Append(Opcode::Movk,
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{Operand::VReg(vreg), Operand::Imm(part3), Operand::Imm(48)});
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i4.AddDef(vreg);
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i4.AddUse(vreg);
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}
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}
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// ========== 核心：将 IR Value 转换为虚拟寄存器 ==========
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int EmitValueToVReg(const ir::Value* value, VRegContext& ctx,
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MachineBasicBlock& block, MachineFunction& function) {
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// 整数常量：每次都生成新的 MovImm（不缓存）
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// 缓存会导致常量在某个条件块中定义，但其他控制流路径上的使用
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// 可能不经过该定义，导致寄存器残留过期值。
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if (auto* constant = dynamic_cast<const ir::ConstantInt*>(value)) {
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uint32_t imm = static_cast<uint32_t>(constant->GetValue());
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int vreg = ctx.NewVReg(VRegType::kInt32);
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EmitMovImm(vreg, imm, block);
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return vreg;
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}
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// 浮点常量：每次都走栈槽加载（不缓存）
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if (auto* fconstant = dynamic_cast<const ir::ConstantFloat*>(value)) {
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float fval = fconstant->GetValue();
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uint32_t bits = FloatToBits(fval);
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int slot = function.CreateFrameIndex(4);
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int tmp = ctx.NewVReg(VRegType::kInt32);
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EmitMovImm(tmp, bits, block);
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auto& s = block.Append(Opcode::StoreStack,
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{Operand::VReg(tmp), Operand::FrameIndex(slot)});
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s.AddUse(tmp);
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int fvreg = ctx.NewVReg(VRegType::kFloat32);
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auto& l = block.Append(Opcode::LoadStack,
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{Operand::VReg(fvreg), Operand::FrameIndex(slot)});
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l.AddDef(fvreg);
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return fvreg;
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}
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// 零常量 / 聚合零：每次都生成新 MovImm（不缓存）
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if (dynamic_cast<const ir::ConstantZero*>(value) ||
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dynamic_cast<const ir::ConstantAggregateZero*>(value)) {
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int vreg = ctx.NewVReg(VRegType::kInt32);
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auto& instr = block.Append(Opcode::MovImm,
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{Operand::VReg(vreg), Operand::Imm(0)});
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instr.AddDef(vreg);
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return vreg;
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}
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// 全局变量：每次都生成新的 adrp+add（不缓存）
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// 与常量同理：缓存会导致全局变量在某条件块中定义，但其他控制流路径
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// 上的使用可能不经过该定义，导致寄存器残留过期值。
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if (auto* global = dynamic_cast<const ir::GlobalValue*>(value)) {
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int vreg = ctx.NewVReg(VRegType::kInt64);
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auto& i1 = block.Append(Opcode::Adrp,
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{Operand::VReg(vreg), Operand::Label(global->GetName())});
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i1.AddDef(vreg);
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auto& i2 = block.Append(Opcode::AddLabel,
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{Operand::VReg(vreg), Operand::VReg(vreg), Operand::Label(global->GetName())});
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i2.AddDef(vreg);
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i2.AddUse(vreg);
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return vreg;
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}
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// 非常量值：检查是否已有映射
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if (ctx.HasVReg(value)) {
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return ctx.GetVReg(value);
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}
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// 未找到
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std::string name = value->GetName();
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if (name.empty()) name = "(anonymous)";
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throw std::runtime_error(
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FormatError("mir", "EmitValueToVReg: 找不到值对应的 vreg: " + name));
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}
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// ========== IR 比较谓词 → ARMv8 条件码 ==========
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CondCode IcmpToCondCode(ir::IcmpInst::Predicate pred) {
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switch (pred) {
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case ir::IcmpInst::Predicate::EQ: return CondCode::EQ;
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case ir::IcmpInst::Predicate::NE: return CondCode::NE;
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case ir::IcmpInst::Predicate::LT: return CondCode::LT;
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case ir::IcmpInst::Predicate::GT: return CondCode::GT;
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case ir::IcmpInst::Predicate::LE: return CondCode::LE;
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case ir::IcmpInst::Predicate::GE: return CondCode::GE;
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default: return CondCode::AL;
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}
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}
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CondCode FcmpToCondCode(ir::FcmpInst::Predicate pred, bool& isOrdered) {
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isOrdered = true;
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switch (pred) {
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case ir::FcmpInst::Predicate::OEQ: return CondCode::EQ;
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case ir::FcmpInst::Predicate::ONE: return CondCode::NE;
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case ir::FcmpInst::Predicate::OLT: return CondCode::LT;
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case ir::FcmpInst::Predicate::OGT: return CondCode::GT;
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case ir::FcmpInst::Predicate::OLE: return CondCode::LE;
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case ir::FcmpInst::Predicate::OGE: return CondCode::GE;
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case ir::FcmpInst::Predicate::UEQ: isOrdered = false; return CondCode::EQ;
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case ir::FcmpInst::Predicate::UNE: isOrdered = false; return CondCode::NE;
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case ir::FcmpInst::Predicate::ULT: isOrdered = false; return CondCode::LT;
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case ir::FcmpInst::Predicate::UGT: isOrdered = false; return CondCode::GT;
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case ir::FcmpInst::Predicate::ULE: isOrdered = false; return CondCode::LE;
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case ir::FcmpInst::Predicate::UGE: isOrdered = false; return CondCode::GE;
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default: return CondCode::AL;
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}
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}
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std::string GetBlockLabel(const ir::BasicBlock* bb) {
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if (!bb || !bb->GetParent()) return ".Lunknown";
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std::string funcName = bb->GetParent()->GetName();
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std::string blockName = bb->GetName();
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if (blockName.empty())
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blockName = std::to_string(reinterpret_cast<uintptr_t>(bb));
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return ".L" + funcName + "_" + blockName;
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}
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// ========== LowerInstruction：将单条 IR 指令转换为 MIR 指令 ==========
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void LowerInstruction(const ir::Instruction& inst, MachineFunction& function,
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VRegContext& ctx, MachineBasicBlock& block,
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std::unordered_map<const ir::BasicBlock*,
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MachineBasicBlock*>& blockMap) {
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DEBUG_MSG("Processing instruction: " << inst.GetName()
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<< " (opcode: " << static_cast<int>(inst.GetOpcode()) << ")");
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switch (inst.GetOpcode()) {
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// ---- Alloca：在栈上分配空间，返回指针 ----
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case ir::Opcode::Alloca: {
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int arraySlot = function.CreateFrameIndex(GetTypeSize(inst.GetType().get()));
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int ptrVreg = ctx.NewVReg(VRegType::kInt64);
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auto& instr = block.Append(Opcode::LoadStackAddr,
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{Operand::VReg(ptrVreg), Operand::FrameIndex(arraySlot)});
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instr.AddDef(ptrVreg);
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ctx.SetVReg(&inst, ptrVreg);
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return;
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}
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// ---- Store：将值存储到指针指向的地址 ----
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case ir::Opcode::Store: {
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auto& store = static_cast<const ir::StoreInst&>(inst);
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const ir::Value* ptr = store.GetPtr();
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const ir::Value* val = store.GetValue();
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int ptrVreg = EmitValueToVReg(ptr, ctx, block, function);
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int valVreg = EmitValueToVReg(val, ctx, block, function);
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auto& instr = block.Append(Opcode::StoreStack,
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{Operand::VReg(valVreg), Operand::VReg(ptrVreg)});
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instr.AddUse(valVreg);
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instr.AddUse(ptrVreg);
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return;
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}
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// ---- Load：从指针指向的地址加载值 ----
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case ir::Opcode::Load: {
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auto& load = static_cast<const ir::LoadInst&>(inst);
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const ir::Value* ptr = load.GetPtr();
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int ptrVreg = EmitValueToVReg(ptr, ctx, block, function);
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VRegType resultType = GetVRegTypeForIRType(inst.GetType().get());
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int dstVreg = ctx.NewVReg(resultType);
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auto& instr = block.Append(Opcode::LoadStack,
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{Operand::VReg(dstVreg), Operand::VReg(ptrVreg)});
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instr.AddDef(dstVreg);
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instr.AddUse(ptrVreg);
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ctx.SetVReg(&inst, dstVreg);
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return;
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}
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// ---- Add ----
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case ir::Opcode::Add: {
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auto& bin = static_cast<const ir::BinaryInst&>(inst);
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const ir::Type* lhsTy = bin.GetLhs()->GetType().get();
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const ir::Type* rhsTy = bin.GetRhs()->GetType().get();
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const ir::Type* resultTy = inst.GetType().get();
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bool isPointer = (lhsTy->IsPtrInt32() || lhsTy->IsPtrFloat() || lhsTy->IsPtrInt1() || lhsTy->IsArray()) ||
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(rhsTy->IsPtrInt32() || rhsTy->IsPtrFloat() || rhsTy->IsPtrInt1() || rhsTy->IsArray()) ||
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resultTy->IsPtrInt32() || resultTy->IsPtrFloat() || resultTy->IsPtrInt1() || resultTy->IsArray();
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bool isI32 = !isPointer && IsInt32Type(lhsTy) && IsInt32Type(rhsTy) && IsInt32Type(resultTy);
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if (isI32) {
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// i32 加法：用 64 位运算避免溢出
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int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
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int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
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int vxl = ctx.NewVReg(VRegType::kInt64);
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int vxr = ctx.NewVReg(VRegType::kInt64);
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int vxd = ctx.NewVReg(VRegType::kInt64);
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auto& s1 = block.Append(Opcode::Sxtw, {Operand::VReg(vxl), Operand::VReg(vl)});
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s1.AddDef(vxl); s1.AddUse(vl);
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auto& s2 = block.Append(Opcode::Sxtw, {Operand::VReg(vxr), Operand::VReg(vr)});
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s2.AddDef(vxr); s2.AddUse(vr);
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auto& a = block.Append(Opcode::AddRR, {Operand::VReg(vxd), Operand::VReg(vxl), Operand::VReg(vxr)});
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a.AddDef(vxd); a.AddUse(vxl); a.AddUse(vxr);
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// 结果用 32 位 vreg（低 32 位正确）
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int vd = ctx.NewVReg(VRegType::kInt32);
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auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(vd), Operand::VReg(vxd)});
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mv.AddDef(vd); mv.AddUse(vxd);
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ctx.SetVReg(&inst, vd);
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} else {
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VRegType ty = isPointer ? VRegType::kInt64 : VRegType::kInt32;
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int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
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int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
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int vd = ctx.NewVReg(ty);
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auto& a = block.Append(Opcode::AddRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Sub ----
|
|
|
case ir::Opcode::Sub: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
// 浮点减法
|
|
|
if (bin.GetLhs()->GetType()->IsFloat() && bin.GetRhs()->GetType()->IsFloat()) {
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& a = block.Append(Opcode::FSubRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
const ir::Type* lhsTy = bin.GetLhs()->GetType().get();
|
|
|
const ir::Type* rhsTy = bin.GetRhs()->GetType().get();
|
|
|
const ir::Type* resultTy = inst.GetType().get();
|
|
|
bool isPointer = (lhsTy->IsPtrInt32() || lhsTy->IsPtrFloat() || lhsTy->IsPtrInt1() || lhsTy->IsArray()) ||
|
|
|
(rhsTy->IsPtrInt32() || rhsTy->IsPtrFloat() || rhsTy->IsPtrInt1() || rhsTy->IsArray()) ||
|
|
|
resultTy->IsPtrInt32() || resultTy->IsPtrFloat() || resultTy->IsPtrInt1() || resultTy->IsArray();
|
|
|
bool isI32 = !isPointer && IsInt32Type(lhsTy) && IsInt32Type(rhsTy) && IsInt32Type(resultTy);
|
|
|
|
|
|
if (isI32) {
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vxl = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxr = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxd = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& s1 = block.Append(Opcode::Sxtw, {Operand::VReg(vxl), Operand::VReg(vl)});
|
|
|
s1.AddDef(vxl); s1.AddUse(vl);
|
|
|
auto& s2 = block.Append(Opcode::Sxtw, {Operand::VReg(vxr), Operand::VReg(vr)});
|
|
|
s2.AddDef(vxr); s2.AddUse(vr);
|
|
|
auto& a = block.Append(Opcode::SubRR, {Operand::VReg(vxd), Operand::VReg(vxl), Operand::VReg(vxr)});
|
|
|
a.AddDef(vxd); a.AddUse(vxl); a.AddUse(vxr);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(vd), Operand::VReg(vxd)});
|
|
|
mv.AddDef(vd); mv.AddUse(vxd);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
} else {
|
|
|
VRegType ty = isPointer ? VRegType::kInt64 : VRegType::kInt32;
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(ty);
|
|
|
auto& a = block.Append(Opcode::SubRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Mul ----
|
|
|
case ir::Opcode::Mul: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
const ir::Type* lhsTy = bin.GetLhs()->GetType().get();
|
|
|
const ir::Type* rhsTy = bin.GetRhs()->GetType().get();
|
|
|
const ir::Type* resultTy = inst.GetType().get();
|
|
|
bool isPointer = (lhsTy->IsPtrInt32() || lhsTy->IsPtrFloat() || lhsTy->IsPtrInt1()) ||
|
|
|
(rhsTy->IsPtrInt32() || rhsTy->IsPtrFloat() || rhsTy->IsPtrInt1()) ||
|
|
|
resultTy->IsPtrInt32() || resultTy->IsPtrFloat() || resultTy->IsPtrInt1();
|
|
|
bool isI32 = !isPointer && IsInt32Type(lhsTy) && IsInt32Type(rhsTy) && IsInt32Type(resultTy);
|
|
|
|
|
|
if (isI32) {
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vxl = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxr = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxd = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& s1 = block.Append(Opcode::Sxtw, {Operand::VReg(vxl), Operand::VReg(vl)});
|
|
|
s1.AddDef(vxl); s1.AddUse(vl);
|
|
|
auto& s2 = block.Append(Opcode::Sxtw, {Operand::VReg(vxr), Operand::VReg(vr)});
|
|
|
s2.AddDef(vxr); s2.AddUse(vr);
|
|
|
auto& a = block.Append(Opcode::MulRR, {Operand::VReg(vxd), Operand::VReg(vxl), Operand::VReg(vxr)});
|
|
|
a.AddDef(vxd); a.AddUse(vxl); a.AddUse(vxr);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(vd), Operand::VReg(vxd)});
|
|
|
mv.AddDef(vd); mv.AddUse(vxd);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
} else {
|
|
|
VRegType ty = isPointer ? VRegType::kInt64 : VRegType::kInt32;
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(ty);
|
|
|
auto& a = block.Append(Opcode::MulRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Div ----
|
|
|
case ir::Opcode::Div: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
const ir::Type* lhsTy = bin.GetLhs()->GetType().get();
|
|
|
const ir::Type* rhsTy = bin.GetRhs()->GetType().get();
|
|
|
const ir::Type* resultTy = inst.GetType().get();
|
|
|
bool isPointer = (lhsTy->IsPtrInt32() || lhsTy->IsPtrFloat() || lhsTy->IsPtrInt1()) ||
|
|
|
(rhsTy->IsPtrInt32() || rhsTy->IsPtrFloat() || rhsTy->IsPtrInt1()) ||
|
|
|
resultTy->IsPtrInt32() || resultTy->IsPtrFloat() || resultTy->IsPtrInt1();
|
|
|
bool isI32 = !isPointer && IsInt32Type(lhsTy) && IsInt32Type(rhsTy) && IsInt32Type(resultTy);
|
|
|
|
|
|
if (isI32) {
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vxl = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxr = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxd = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& s1 = block.Append(Opcode::Sxtw, {Operand::VReg(vxl), Operand::VReg(vl)});
|
|
|
s1.AddDef(vxl); s1.AddUse(vl);
|
|
|
auto& s2 = block.Append(Opcode::Sxtw, {Operand::VReg(vxr), Operand::VReg(vr)});
|
|
|
s2.AddDef(vxr); s2.AddUse(vr);
|
|
|
auto& a = block.Append(Opcode::SDivRR, {Operand::VReg(vxd), Operand::VReg(vxl), Operand::VReg(vxr)});
|
|
|
a.AddDef(vxd); a.AddUse(vxl); a.AddUse(vxr);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(vd), Operand::VReg(vxd)});
|
|
|
mv.AddDef(vd); mv.AddUse(vxd);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
} else {
|
|
|
VRegType ty = isPointer ? VRegType::kInt64 : VRegType::kInt32;
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(ty);
|
|
|
auto& a = block.Append(Opcode::SDivRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Mod: a % b = a - (a / b) * b ----
|
|
|
case ir::Opcode::Mod: {
|
|
|
const ir::Value* lhs = inst.GetOperand(0);
|
|
|
const ir::Value* rhs = inst.GetOperand(1);
|
|
|
const ir::Type* lhsTy = lhs->GetType().get();
|
|
|
const ir::Type* rhsTy = rhs->GetType().get();
|
|
|
const ir::Type* resultTy = inst.GetType().get();
|
|
|
bool isI32 = IsInt32Type(lhsTy) && IsInt32Type(rhsTy) && IsInt32Type(resultTy);
|
|
|
|
|
|
if (isI32) {
|
|
|
int vl = EmitValueToVReg(lhs, ctx, block, function);
|
|
|
int vr = EmitValueToVReg(rhs, ctx, block, function);
|
|
|
int vxl = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxr = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& s1 = block.Append(Opcode::Sxtw, {Operand::VReg(vxl), Operand::VReg(vl)});
|
|
|
s1.AddDef(vxl); s1.AddUse(vl);
|
|
|
auto& s2 = block.Append(Opcode::Sxtw, {Operand::VReg(vxr), Operand::VReg(vr)});
|
|
|
s2.AddDef(vxr); s2.AddUse(vr);
|
|
|
int vxdiv = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxtmp = ctx.NewVReg(VRegType::kInt64);
|
|
|
int vxd = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& d = block.Append(Opcode::SDivRR, {Operand::VReg(vxdiv), Operand::VReg(vxl), Operand::VReg(vxr)});
|
|
|
d.AddDef(vxdiv); d.AddUse(vxl); d.AddUse(vxr);
|
|
|
auto& m = block.Append(Opcode::MulRR, {Operand::VReg(vxtmp), Operand::VReg(vxdiv), Operand::VReg(vxr)});
|
|
|
m.AddDef(vxtmp); m.AddUse(vxdiv); m.AddUse(vxr);
|
|
|
auto& sub = block.Append(Opcode::SubRR, {Operand::VReg(vxd), Operand::VReg(vxl), Operand::VReg(vxtmp)});
|
|
|
sub.AddDef(vxd); sub.AddUse(vxl); sub.AddUse(vxtmp);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(vd), Operand::VReg(vxd)});
|
|
|
mv.AddDef(vd); mv.AddUse(vxd);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
} else {
|
|
|
int vl = EmitValueToVReg(lhs, ctx, block, function);
|
|
|
int vr = EmitValueToVReg(rhs, ctx, block, function);
|
|
|
int vdiv = ctx.NewVReg(VRegType::kInt32);
|
|
|
int vtmp = ctx.NewVReg(VRegType::kInt32);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& d = block.Append(Opcode::SDivRR, {Operand::VReg(vdiv), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
d.AddDef(vdiv); d.AddUse(vl); d.AddUse(vr);
|
|
|
auto& m = block.Append(Opcode::MulRR, {Operand::VReg(vtmp), Operand::VReg(vdiv), Operand::VReg(vr)});
|
|
|
m.AddDef(vtmp); m.AddUse(vdiv); m.AddUse(vr);
|
|
|
auto& s = block.Append(Opcode::SubRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vtmp)});
|
|
|
s.AddDef(vd); s.AddUse(vl); s.AddUse(vtmp);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Ret ----
|
|
|
case ir::Opcode::Ret: {
|
|
|
auto& ret = static_cast<const ir::ReturnInst&>(inst);
|
|
|
const ir::Value* retVal = ret.GetValue();
|
|
|
if (retVal != nullptr) {
|
|
|
const ir::Type* retType = retVal->GetType().get();
|
|
|
int valVreg = EmitValueToVReg(retVal, ctx, block, function);
|
|
|
PhysReg retReg = PhysReg::W0;
|
|
|
if (retType->IsFloat()) retReg = PhysReg::S0;
|
|
|
else if (retType->IsPtrInt32() || retType->IsPtrFloat() || retType->IsPtrInt1())
|
|
|
retReg = PhysReg::X0;
|
|
|
auto& mv = block.Append(Opcode::MovReg,
|
|
|
{Operand::Reg(retReg), Operand::VReg(valVreg)});
|
|
|
mv.AddUse(valVreg);
|
|
|
}
|
|
|
auto& r = block.Append(Opcode::Ret);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- FAdd ----
|
|
|
case ir::Opcode::FAdd: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& a = block.Append(Opcode::FAddRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
case ir::Opcode::FSub: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& a = block.Append(Opcode::FSubRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
case ir::Opcode::FMul: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& a = block.Append(Opcode::FMulRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
case ir::Opcode::FDiv: {
|
|
|
auto& bin = static_cast<const ir::BinaryInst&>(inst);
|
|
|
int vl = EmitValueToVReg(bin.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(bin.GetRhs(), ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& a = block.Append(Opcode::FDivRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Icmp（整数比较） ----
|
|
|
case ir::Opcode::Icmp: {
|
|
|
auto& icmp = static_cast<const ir::IcmpInst&>(inst);
|
|
|
int vl = EmitValueToVReg(icmp.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(icmp.GetRhs(), ctx, block, function);
|
|
|
CondCode cc = IcmpToCondCode(icmp.GetPredicate());
|
|
|
|
|
|
auto& cmp = block.Append(Opcode::CmpRR, {Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
cmp.AddUse(vl); cmp.AddUse(vr);
|
|
|
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& set1 = block.Append(Opcode::MovImm, {Operand::VReg(vd), Operand::Imm(1)});
|
|
|
set1.AddDef(vd);
|
|
|
|
|
|
std::string trueLabel = ".L_cset_true_" + std::to_string(reinterpret_cast<uintptr_t>(&icmp));
|
|
|
std::string endLabel = ".L_cset_end_" + std::to_string(reinterpret_cast<uintptr_t>(&icmp));
|
|
|
|
|
|
auto& bc = block.Append(Opcode::BCond, {Operand::Cond(cc), Operand::Label(trueLabel)});
|
|
|
auto& mv0 = block.Append(Opcode::MovImm, {Operand::VReg(vd), Operand::Imm(0)});
|
|
|
mv0.AddDef(vd);
|
|
|
auto& b = block.Append(Opcode::B, {Operand::Label(endLabel)});
|
|
|
auto& lt = block.Append(Opcode::Label, {Operand::Label(trueLabel)});
|
|
|
auto& le = block.Append(Opcode::Label, {Operand::Label(endLabel)});
|
|
|
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- FCmp（浮点比较） ----
|
|
|
case ir::Opcode::FCmp: {
|
|
|
auto& fcmp = static_cast<const ir::FcmpInst&>(inst);
|
|
|
int vl = EmitValueToVReg(fcmp.GetLhs(), ctx, block, function);
|
|
|
int vr = EmitValueToVReg(fcmp.GetRhs(), ctx, block, function);
|
|
|
bool isOrdered;
|
|
|
CondCode cc = FcmpToCondCode(fcmp.GetPredicate(), isOrdered);
|
|
|
|
|
|
auto& cmp = block.Append(Opcode::FCmpRR, {Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
cmp.AddUse(vl); cmp.AddUse(vr);
|
|
|
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& zero = block.Append(Opcode::MovImm, {Operand::VReg(vd), Operand::Imm(0)});
|
|
|
zero.AddDef(vd);
|
|
|
|
|
|
std::string set1Label = ".L_fcset_true_" + std::to_string(reinterpret_cast<uintptr_t>(&fcmp));
|
|
|
std::string endLabel = ".L_fcset_end_" + std::to_string(reinterpret_cast<uintptr_t>(&fcmp));
|
|
|
|
|
|
if (isOrdered) {
|
|
|
auto& bc_vs = block.Append(Opcode::BCond, {Operand::Cond(CondCode::VS), Operand::Label(endLabel)});
|
|
|
} else {
|
|
|
auto& bc_vs = block.Append(Opcode::BCond, {Operand::Cond(CondCode::VS), Operand::Label(set1Label)});
|
|
|
}
|
|
|
auto& bc = block.Append(Opcode::BCond, {Operand::Cond(cc), Operand::Label(set1Label)});
|
|
|
auto& b = block.Append(Opcode::B, {Operand::Label(endLabel)});
|
|
|
auto& lt = block.Append(Opcode::Label, {Operand::Label(set1Label)});
|
|
|
auto& s1 = block.Append(Opcode::MovImm, {Operand::VReg(vd), Operand::Imm(1)});
|
|
|
s1.AddDef(vd);
|
|
|
auto& le = block.Append(Opcode::Label, {Operand::Label(endLabel)});
|
|
|
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Br / CondBr ----
|
|
|
case ir::Opcode::Br:
|
|
|
case ir::Opcode::CondBr: {
|
|
|
auto& br = static_cast<const ir::BranchInst&>(inst);
|
|
|
if (br.IsConditional()) {
|
|
|
int condVreg = EmitValueToVReg(br.GetCondition(), ctx, block, function);
|
|
|
auto& cmp = block.Append(Opcode::CmpRI, {Operand::VReg(condVreg), Operand::Imm(0)});
|
|
|
cmp.AddUse(condVreg);
|
|
|
|
|
|
std::string trueLabel = GetBlockLabel(br.GetTrueTarget());
|
|
|
std::string falseLabel = GetBlockLabel(br.GetFalseTarget());
|
|
|
|
|
|
auto& bc = block.Append(Opcode::BCond, {Operand::Cond(CondCode::NE), Operand::Label(trueLabel)});
|
|
|
auto& b = block.Append(Opcode::B, {Operand::Label(falseLabel)});
|
|
|
} else {
|
|
|
std::string targetLabel = GetBlockLabel(br.GetTarget());
|
|
|
auto& b = block.Append(Opcode::B, {Operand::Label(targetLabel)});
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Call ----
|
|
|
case ir::Opcode::Call: {
|
|
|
auto& call = static_cast<const ir::CallInst&>(inst);
|
|
|
const ir::Function* callee = call.GetCallee();
|
|
|
const std::string& calleeName = callee->GetName();
|
|
|
|
|
|
// 传递参数（vreg → 物理寄存器）
|
|
|
const auto& args = call.GetArgs();
|
|
|
size_t intArgCount = 0;
|
|
|
size_t fpArgCount = 0;
|
|
|
for (size_t i = 0; i < args.size(); ++i) {
|
|
|
const auto* arg = args[i];
|
|
|
const ir::Type* argType = arg->GetType().get();
|
|
|
int argVreg = EmitValueToVReg(arg, ctx, block, function);
|
|
|
|
|
|
if (argType->IsFloat()) {
|
|
|
PhysReg reg = static_cast<PhysReg>(static_cast<int>(PhysReg::S0) + fpArgCount);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::Reg(reg), Operand::VReg(argVreg)});
|
|
|
mv.AddUse(argVreg);
|
|
|
fpArgCount++;
|
|
|
} else if (argType->IsPtrInt32() || argType->IsPtrFloat() || argType->IsPtrInt1()) {
|
|
|
PhysReg reg = static_cast<PhysReg>(static_cast<int>(PhysReg::X0) + intArgCount);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::Reg(reg), Operand::VReg(argVreg)});
|
|
|
mv.AddUse(argVreg);
|
|
|
intArgCount++;
|
|
|
} else {
|
|
|
PhysReg reg = static_cast<PhysReg>(static_cast<int>(PhysReg::W0) + intArgCount);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::Reg(reg), Operand::VReg(argVreg)});
|
|
|
mv.AddUse(argVreg);
|
|
|
intArgCount++;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
auto& callInst = block.Append(Opcode::Call, {Operand::Label(calleeName)});
|
|
|
|
|
|
// 返回值：物理寄存器 → vreg
|
|
|
if (!inst.GetType()->IsVoid()) {
|
|
|
const ir::Type* retType = inst.GetType().get();
|
|
|
VRegType vtype = GetVRegTypeForIRType(retType);
|
|
|
int dstVreg = ctx.NewVReg(vtype);
|
|
|
PhysReg srcReg = PhysReg::W0;
|
|
|
if (retType->IsFloat()) srcReg = PhysReg::S0;
|
|
|
else if (retType->IsPtrInt32() || retType->IsPtrFloat() || retType->IsPtrInt1())
|
|
|
srcReg = PhysReg::X0;
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(dstVreg), Operand::Reg(srcReg)});
|
|
|
mv.AddDef(dstVreg);
|
|
|
ctx.SetVReg(&inst, dstVreg);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- ZExt (i1 → i32) ----
|
|
|
case ir::Opcode::ZExt: {
|
|
|
auto& zext = static_cast<const ir::ZExtInst&>(inst);
|
|
|
int src = EmitValueToVReg(zext.GetValue(), ctx, block, function);
|
|
|
int dst = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(dst), Operand::VReg(src)});
|
|
|
mv.AddDef(dst); mv.AddUse(src);
|
|
|
ctx.SetVReg(&inst, dst);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- SIToFP ----
|
|
|
case ir::Opcode::SIToFP: {
|
|
|
auto& sitofp = static_cast<const ir::SIToFPInst&>(inst);
|
|
|
int src = EmitValueToVReg(sitofp.GetValue(), ctx, block, function);
|
|
|
int dst = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& cvt = block.Append(Opcode::SIToFP, {Operand::VReg(dst), Operand::VReg(src)});
|
|
|
cvt.AddDef(dst); cvt.AddUse(src);
|
|
|
ctx.SetVReg(&inst, dst);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- FPToSI ----
|
|
|
case ir::Opcode::FPToSI: {
|
|
|
auto& fptosi = static_cast<const ir::FPToSIInst&>(inst);
|
|
|
int src = EmitValueToVReg(fptosi.GetValue(), ctx, block, function);
|
|
|
int dst = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& cvt = block.Append(Opcode::FPToSI, {Operand::VReg(dst), Operand::VReg(src)});
|
|
|
cvt.AddDef(dst); cvt.AddUse(src);
|
|
|
ctx.SetVReg(&inst, dst);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Trunc ----
|
|
|
case ir::Opcode::Trunc: {
|
|
|
const ir::Value* srcVal = inst.GetNumOperands() > 0 ? inst.GetOperand(0) : nullptr;
|
|
|
if (srcVal) {
|
|
|
int src = EmitValueToVReg(srcVal, ctx, block, function);
|
|
|
int dst = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(dst), Operand::VReg(src)});
|
|
|
mv.AddDef(dst); mv.AddUse(src);
|
|
|
ctx.SetVReg(&inst, dst);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- And ----
|
|
|
case ir::Opcode::And: {
|
|
|
const ir::Value* lhs = inst.GetNumOperands() >= 2 ? inst.GetOperand(0) : nullptr;
|
|
|
const ir::Value* rhs = inst.GetNumOperands() >= 2 ? inst.GetOperand(1) : nullptr;
|
|
|
if (lhs && rhs) {
|
|
|
int vl = EmitValueToVReg(lhs, ctx, block, function);
|
|
|
int vr = EmitValueToVReg(rhs, ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& a = block.Append(Opcode::AndRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Or ----
|
|
|
case ir::Opcode::Or: {
|
|
|
const ir::Value* lhs = inst.GetNumOperands() >= 2 ? inst.GetOperand(0) : nullptr;
|
|
|
const ir::Value* rhs = inst.GetNumOperands() >= 2 ? inst.GetOperand(1) : nullptr;
|
|
|
if (lhs && rhs) {
|
|
|
int vl = EmitValueToVReg(lhs, ctx, block, function);
|
|
|
int vr = EmitValueToVReg(rhs, ctx, block, function);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& a = block.Append(Opcode::OrRR, {Operand::VReg(vd), Operand::VReg(vl), Operand::VReg(vr)});
|
|
|
a.AddDef(vd); a.AddUse(vl); a.AddUse(vr);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- Not ----
|
|
|
case ir::Opcode::Not: {
|
|
|
const ir::Value* srcVal = inst.GetNumOperands() > 0 ? inst.GetOperand(0) : nullptr;
|
|
|
if (srcVal) {
|
|
|
int src = EmitValueToVReg(srcVal, ctx, block, function);
|
|
|
int m1 = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& mv1 = block.Append(Opcode::MovImm, {Operand::VReg(m1), Operand::Imm(-1)});
|
|
|
mv1.AddDef(m1);
|
|
|
int vd = ctx.NewVReg(VRegType::kInt32);
|
|
|
auto& eor = block.Append(Opcode::EorRR, {Operand::VReg(vd), Operand::VReg(src), Operand::VReg(m1)});
|
|
|
eor.AddDef(vd); eor.AddUse(src); eor.AddUse(m1);
|
|
|
ctx.SetVReg(&inst, vd);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- FPExt ----
|
|
|
case ir::Opcode::FPExt: {
|
|
|
const ir::Value* srcVal = inst.GetNumOperands() > 0 ? inst.GetOperand(0) : nullptr;
|
|
|
if (srcVal) {
|
|
|
int src = EmitValueToVReg(srcVal, ctx, block, function);
|
|
|
int dst = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(dst), Operand::VReg(src)});
|
|
|
mv.AddDef(dst); mv.AddUse(src);
|
|
|
ctx.SetVReg(&inst, dst);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- FPTrunc ----
|
|
|
case ir::Opcode::FPTrunc: {
|
|
|
const ir::Value* srcVal = inst.GetNumOperands() > 0 ? inst.GetOperand(0) : nullptr;
|
|
|
if (srcVal) {
|
|
|
int src = EmitValueToVReg(srcVal, ctx, block, function);
|
|
|
int dst = ctx.NewVReg(VRegType::kFloat32);
|
|
|
auto& mv = block.Append(Opcode::MovReg, {Operand::VReg(dst), Operand::VReg(src)});
|
|
|
mv.AddDef(dst); mv.AddUse(src);
|
|
|
ctx.SetVReg(&inst, dst);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
// ---- GEP ----
|
|
|
case ir::Opcode::GEP: {
|
|
|
auto& gep = static_cast<const ir::GEPInst&>(inst);
|
|
|
ir::Value* base = gep.GetBase();
|
|
|
const auto& indices = gep.GetIndices();
|
|
|
|
|
|
int baseVreg = EmitValueToVReg(base, ctx, block, function);
|
|
|
|
|
|
if (indices.empty()) {
|
|
|
ctx.SetVReg(&inst, baseVreg);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
const ir::Type* baseType = base->GetType().get();
|
|
|
size_t startIndex = 0;
|
|
|
if (baseType->IsArray()) {
|
|
|
startIndex = 1; // 跳过数组解码的第一个索引
|
|
|
}
|
|
|
|
|
|
if (baseType->IsArray() && indices.size() > startIndex) {
|
|
|
const ir::ArrayType* arrayType = static_cast<const ir::ArrayType*>(baseType);
|
|
|
const std::vector<int>& dims = arrayType->GetDimensions();
|
|
|
|
|
|
std::vector<int> strides(dims.size());
|
|
|
int elementSize = 4;
|
|
|
for (int i = static_cast<int>(dims.size()) - 1; i >= 0; --i) {
|
|
|
if (i == static_cast<int>(dims.size()) - 1)
|
|
|
strides[i] = elementSize;
|
|
|
else
|
|
|
strides[i] = strides[i + 1] * dims[i + 1];
|
|
|
}
|
|
|
|
|
|
size_t numIndices = indices.size();
|
|
|
size_t effectiveIndices = numIndices - startIndex;
|
|
|
if (effectiveIndices > dims.size()) effectiveIndices = dims.size();
|
|
|
|
|
|
// 偏移累加器初始化为 0
|
|
|
int offsetVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& zero = block.Append(Opcode::MovImm, {Operand::VReg(offsetVreg), Operand::Imm(0)});
|
|
|
zero.AddDef(offsetVreg);
|
|
|
|
|
|
for (size_t i = 0; i < effectiveIndices; ++i) {
|
|
|
size_t idxPos = startIndex + i;
|
|
|
int idxVreg = EmitValueToVReg(indices[idxPos], ctx, block, function);
|
|
|
// 确保索引是 Int64（地址计算必须是 64 位）
|
|
|
if (ctx.GetType(idxVreg) == VRegType::kInt32) {
|
|
|
int idxVreg64 = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& sxt = block.Append(Opcode::Sxtw,
|
|
|
{Operand::VReg(idxVreg64), Operand::VReg(idxVreg)});
|
|
|
sxt.AddDef(idxVreg64); sxt.AddUse(idxVreg);
|
|
|
idxVreg = idxVreg64;
|
|
|
}
|
|
|
int strideVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& stride = block.Append(Opcode::MovImm,
|
|
|
{Operand::VReg(strideVreg), Operand::Imm(strides[i])});
|
|
|
stride.AddDef(strideVreg);
|
|
|
int prodVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& mul = block.Append(Opcode::MulRR,
|
|
|
{Operand::VReg(prodVreg), Operand::VReg(idxVreg), Operand::VReg(strideVreg)});
|
|
|
mul.AddDef(prodVreg); mul.AddUse(idxVreg); mul.AddUse(strideVreg);
|
|
|
int newOff = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& add = block.Append(Opcode::AddRR,
|
|
|
{Operand::VReg(newOff), Operand::VReg(offsetVreg), Operand::VReg(prodVreg)});
|
|
|
add.AddDef(newOff); add.AddUse(offsetVreg); add.AddUse(prodVreg);
|
|
|
offsetVreg = newOff;
|
|
|
}
|
|
|
|
|
|
int resultVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& finalAdd = block.Append(Opcode::AddRR,
|
|
|
{Operand::VReg(resultVreg), Operand::VReg(baseVreg), Operand::VReg(offsetVreg)});
|
|
|
finalAdd.AddDef(resultVreg); finalAdd.AddUse(baseVreg); finalAdd.AddUse(offsetVreg);
|
|
|
ctx.SetVReg(&inst, resultVreg);
|
|
|
} else if (indices.size() >= 1) {
|
|
|
// 简单指针运算
|
|
|
int idxVreg = EmitValueToVReg(indices[0], ctx, block, function);
|
|
|
if (ctx.GetType(idxVreg) == VRegType::kInt32) {
|
|
|
int idxVreg64 = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& sxt = block.Append(Opcode::Sxtw,
|
|
|
{Operand::VReg(idxVreg64), Operand::VReg(idxVreg)});
|
|
|
sxt.AddDef(idxVreg64); sxt.AddUse(idxVreg);
|
|
|
idxVreg = idxVreg64;
|
|
|
}
|
|
|
int strideVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
int elemSize = 4;
|
|
|
if (baseType->IsArray()) {
|
|
|
const ir::ArrayType* arrType = static_cast<const ir::ArrayType*>(baseType);
|
|
|
elemSize = GetTypeSize(arrType->GetElementType().get());
|
|
|
}
|
|
|
auto& stride = block.Append(Opcode::MovImm, {Operand::VReg(strideVreg), Operand::Imm(elemSize)});
|
|
|
stride.AddDef(strideVreg);
|
|
|
int prodVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& mul = block.Append(Opcode::MulRR,
|
|
|
{Operand::VReg(prodVreg), Operand::VReg(idxVreg), Operand::VReg(strideVreg)});
|
|
|
mul.AddDef(prodVreg); mul.AddUse(idxVreg); mul.AddUse(strideVreg);
|
|
|
int resultVreg = ctx.NewVReg(VRegType::kInt64);
|
|
|
auto& add = block.Append(Opcode::AddRR,
|
|
|
{Operand::VReg(resultVreg), Operand::VReg(baseVreg), Operand::VReg(prodVreg)});
|
|
|
add.AddDef(resultVreg); add.AddUse(baseVreg); add.AddUse(prodVreg);
|
|
|
ctx.SetVReg(&inst, resultVreg);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
default:
|
|
|
throw std::runtime_error(FormatError("mir", "暂不支持该 IR 指令，opcode: "
|
|
|
+ std::to_string(static_cast<int>(inst.GetOpcode()))));
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// ========== LowerFunction：将 IR 函数转换为 MachineFunction ==========
|
|
|
std::unique_ptr<MachineFunction> LowerFunction(const ir::Function& func) {
|
|
|
auto machineFunc = std::make_unique<MachineFunction>(func.GetName());
|
|
|
VRegContext ctx;
|
|
|
|
|
|
// 为函数参数分配 vreg
|
|
|
struct ParamInfo {
|
|
|
const ir::Value* arg;
|
|
|
int vreg;
|
|
|
bool isFloat;
|
|
|
bool isPointer;
|
|
|
};
|
|
|
std::vector<ParamInfo> paramInfos;
|
|
|
|
|
|
for (const auto& arg : func.GetArguments()) {
|
|
|
bool isFloat = arg->GetType()->IsFloat();
|
|
|
bool isPointer = arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat()
|
|
|
|| arg->GetType()->IsPtrInt1();
|
|
|
VRegType ty = isFloat ? VRegType::kFloat32
|
|
|
: (isPointer ? VRegType::kInt64 : VRegType::kInt32);
|
|
|
int vreg = ctx.NewVReg(ty);
|
|
|
ctx.SetVReg(arg.get(), vreg);
|
|
|
paramInfos.push_back({arg.get(), vreg, isFloat, isPointer});
|
|
|
}
|
|
|
|
|
|
// IR 基本块 → MIR 基本块 映射
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std::unordered_map<const ir::BasicBlock*, MachineBasicBlock*> blockMap;
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std::string funcName = func.GetName();
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for (const auto& bb : func.GetBlocks()) {
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auto mirBB = std::make_unique<MachineBasicBlock>(".L" + funcName + "_" + bb->GetName());
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blockMap[bb.get()] = mirBB.get();
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machineFunc->AddBasicBlock(std::move(mirBB));
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}
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// 在入口基本块开头：从物理参数寄存器加载参数到 vreg
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if (!func.GetBlocks().empty()) {
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MachineBasicBlock* entryBB = blockMap[func.GetEntry()];
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if (entryBB) {
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size_t intArgIdx = 0;
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size_t fpArgIdx = 0;
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for (const auto& param : paramInfos) {
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if (param.isFloat) {
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if (fpArgIdx < 8) {
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PhysReg reg = static_cast<PhysReg>(
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static_cast<int>(PhysReg::S0) + fpArgIdx);
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auto& mv = entryBB->Append(Opcode::MovReg,
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{Operand::VReg(param.vreg), Operand::Reg(reg)});
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mv.AddDef(param.vreg);
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}
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fpArgIdx++;
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} else if (param.isPointer) {
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if (intArgIdx < 8) {
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PhysReg reg = static_cast<PhysReg>(
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static_cast<int>(PhysReg::X0) + intArgIdx);
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auto& mv = entryBB->Append(Opcode::MovReg,
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{Operand::VReg(param.vreg), Operand::Reg(reg)});
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mv.AddDef(param.vreg);
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}
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intArgIdx++;
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} else {
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if (intArgIdx < 8) {
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PhysReg reg = static_cast<PhysReg>(
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static_cast<int>(PhysReg::W0) + intArgIdx);
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auto& mv = entryBB->Append(Opcode::MovReg,
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{Operand::VReg(param.vreg), Operand::Reg(reg)});
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mv.AddDef(param.vreg);
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}
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intArgIdx++;
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}
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}
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}
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}
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// 转换每个基本块的指令
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for (const auto& bb : func.GetBlocks()) {
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MachineBasicBlock* mirBB = blockMap[bb.get()];
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if (!mirBB)
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throw std::runtime_error(FormatError("mir", "找不到基本块对应的 MIR 基本块"));
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for (const auto& inst : bb->GetInstructions()) {
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LowerInstruction(*inst, *machineFunc, ctx, *mirBB, blockMap);
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}
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}
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// 将 vreg 类型信息存入 MachineFunction（RA 阶段使用）
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for (const auto& [vreg, type] : ctx.vreg_types) {
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switch (type) {
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case VRegType::kInt32:
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machineFunc->SetVRegType(vreg, MachineFunction::VRegType::kInt32);
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break;
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case VRegType::kInt64:
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machineFunc->SetVRegType(vreg, MachineFunction::VRegType::kInt64);
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break;
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case VRegType::kFloat32:
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machineFunc->SetVRegType(vreg, MachineFunction::VRegType::kFloat32);
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break;
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}
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}
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// 构建 CFG 边（解析 B/BCond 中的 Label 目标）
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for (const auto& bb : func.GetBlocks()) {
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MachineBasicBlock* mirBB = blockMap[bb.get()];
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auto& insts = mirBB->GetInstructions();
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if (insts.empty()) continue;
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// 辅助：从指令中提取 Label 操作数并添加边
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auto addLabelSuccessors = [&](const MachineInstr& inst) {
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for (const auto& op : inst.GetOperands()) {
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if (op.GetKind() == Operand::Kind::Label) {
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MachineBasicBlock* target = machineFunc->GetBlockByName(op.GetLabel());
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if (target) {
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mirBB->AddSuccessor(target);
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target->AddPredecessor(mirBB);
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}
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}
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|
}
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};
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// 辅助：添加 fallthrough 到下一个 IR 基本块
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|
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auto addFallthrough = [&]() {
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for (size_t i = 0; i + 1 < func.GetBlocks().size(); ++i) {
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if (func.GetBlocks()[i].get() == bb.get()) {
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|
const auto* nextBB = func.GetBlocks()[i + 1].get();
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|
|
MachineBasicBlock* nextMIR = blockMap[nextBB];
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|
|
if (nextMIR) {
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|
|
mirBB->AddSuccessor(nextMIR);
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|
|
nextMIR->AddPredecessor(mirBB);
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|
|
}
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
};
|
|
|
|
|
|
const auto& last = insts.back();
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|
|
if (last.GetOpcode() == Opcode::B) {
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|
|
// B 为最后一条指令：添加 B 的目标
|
|
|
addLabelSuccessors(last);
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|
|
// 若倒数第二条是 BCond，则 BCond 的目标也是后继（BCond; B 模式）
|
|
|
if (insts.size() >= 2) {
|
|
|
const auto& prev = insts[insts.size() - 2];
|
|
|
if (prev.GetOpcode() == Opcode::BCond) {
|
|
|
addLabelSuccessors(prev);
|
|
|
}
|
|
|
}
|
|
|
} else if (last.GetOpcode() == Opcode::BCond) {
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|
|
// BCond 为最后一条指令：添加 BCond 目标 + fallthrough
|
|
|
addLabelSuccessors(last);
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|
|
// 若倒数第二条是 B（罕见：B; BCond），也添加 B 目标
|
|
|
if (insts.size() >= 2) {
|
|
|
const auto& prev = insts[insts.size() - 2];
|
|
|
if (prev.GetOpcode() == Opcode::B) {
|
|
|
addLabelSuccessors(prev);
|
|
|
}
|
|
|
}
|
|
|
// BCond 之后无 B，则 false 分支 fallthrough
|
|
|
addFallthrough();
|
|
|
} else if (last.GetOpcode() == Opcode::Ret) {
|
|
|
// Ret 无后继
|
|
|
} else {
|
|
|
// 非终结指令：fall-through 到下一个基本块
|
|
|
addFallthrough();
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return machineFunc;
|
|
|
}
|
|
|
|
|
|
} // namespace
|
|
|
|
|
|
// ========== LowerToMIR：入口函数 ==========
|
|
|
std::unique_ptr<MachineModule> LowerToMIR(const ir::Module& module) {
|
|
|
DefaultContext();
|
|
|
auto machineModule = std::make_unique<MachineModule>();
|
|
|
|
|
|
// 收集全局变量信息
|
|
|
for (const auto& global : module.GetGlobals()) {
|
|
|
int size = GetTypeSize(global->GetType().get());
|
|
|
int alignment = global->GetType()->Alignment();
|
|
|
bool isZeroInit = !global->HasInitializer();
|
|
|
bool hasInitData = false;
|
|
|
uint64_t initData = 0;
|
|
|
|
|
|
if (!isZeroInit) {
|
|
|
const auto& init = global->GetInitializer();
|
|
|
if (init.size() == 1) {
|
|
|
if (auto* cf = dynamic_cast<const ir::ConstantFloat*>(init[0])) {
|
|
|
float fval = cf->GetValue();
|
|
|
uint32_t bits;
|
|
|
memcpy(&bits, &fval, sizeof(bits));
|
|
|
initData = bits;
|
|
|
hasInitData = true;
|
|
|
} else if (auto* ci = dynamic_cast<const ir::ConstantInt*>(init[0])) {
|
|
|
initData = static_cast<uint64_t>(ci->GetValue());
|
|
|
hasInitData = true;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
machineModule->AddGlobal(global->GetName(), size, alignment,
|
|
|
isZeroInit, hasInitData, initData);
|
|
|
}
|
|
|
|
|
|
// 转换所有函数
|
|
|
for (const auto& func : module.GetFunctions()) {
|
|
|
try {
|
|
|
auto machineFunc = LowerFunction(*func);
|
|
|
machineModule->AddFunction(std::move(machineFunc));
|
|
|
} catch (const std::runtime_error& e) {
|
|
|
throw std::runtime_error(
|
|
|
FormatError("mir", "转换函数失败: " + func->GetName() + " - " + e.what()));
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (machineModule->GetFunctions().empty()) {
|
|
|
throw std::runtime_error(FormatError("mir", "模块中没有成功转换的函数"));
|
|
|
}
|
|
|
|
|
|
return machineModule;
|
|
|
}
|
|
|
|
|
|
} // namespace mir
|
