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refactor(backend):删除对后端对全局变量的处理

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master
nanfeng1212 1 month ago
parent 7cc7ce8c37
commit 2c8a64c763
6 changed files with 32 additions and 359 deletions
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33
src/backend/asm2string.rs
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@ -34,21 +34,7 @@ impl Display for MirFunction {
impl Display for PReg {
fn display(self, _mctx: &MirContext) -> String {
let mut asm = String::new();
let str = match self.kind() {
RegKind::Address => match self.num() {
0 => "x0",
10 => "x10",
11 => "x11",
12 => "x12",
13 => "x13",
14 => "x14",
15 => "x15",
16 => "x16",
17 => "x17",
31 => "sp",
32 => "xzr",
_ => "<invalid>",
},
let str = match self.kind() {
RegKind::Integer => match self.num() {
0 => "w0",
9 => "w9",
@ -107,9 +93,6 @@ impl Display for MirInst {
MirInstKind::Movz{ rd, imm } => {
asm += format!("movz {}, #{}", rd.display(mctx), imm).as_str();
}
MirInstKind::Movk{ rd, imm } => {
asm += format!("movk {}, #{}, lsl #16", rd.display(mctx),imm).as_str();
}
MirInstKind::MovReg { rd, rn } => {
asm += format!("mov {}, {}", rd.display(mctx), rn.display(mctx)).as_str()
}
@ -128,12 +111,6 @@ impl Display for MirInst {
MirInstKind::Subi {rd,rn,imm} => {
asm += format!("sub {}, {}, #{}", rd.display(mctx), rn.display(mctx), imm).as_str();
}
MirInstKind::Adrp { rd, label } => {
asm += format!("adrp {}, {}", rd.display(mctx), label.clone().display(mctx)).as_str();
}
MirInstKind::AddLabel { rd, rn, label } => {
asm += format!("add {}, {}, :lo12:{}",rd.display(mctx), rn.display(mctx), label.clone().display(mctx)).as_str()
}
}
asm
}
@ -154,13 +131,7 @@ impl Display for MemLoc {
asm += format!("[{}, #{}]", base.display(mctx), offset).as_str()
}
}
MemLoc::Reg2Offset { base, offset } => {
if offset.is_address() {
asm += format!("[{}, {}]", base.display(mctx), offset.display(mctx)).as_str()
} else {
asm += format!("[{}, {}, SXTW]", base.display(mctx), offset.display(mctx)).as_str()
}
}
_ => todo!(),
}
asm
}

4
src/backend/mir/mir_function.rs
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@ -13,8 +13,6 @@ pub struct MirFunctionData {
label: MirLabel,
storage_stack_size: i32,
current_stack_size: i32,
calleeargs_stack_size: i32,
callee_regs: BTreeSet<PReg>,
is_external: bool,
start: Option<MirBlock>,
end: Option<MirBlock>,
@ -34,8 +32,6 @@ impl MirFunction {
label: label.into(),
storage_stack_size: 0,
current_stack_size: 0,
calleeargs_stack_size: 0,
callee_regs: BTreeSet::default(),
is_external,
start: None,
end: None,

65
src/backend/mir/mir_inst.rs
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@ -22,15 +22,11 @@ pub enum MirInstKind {
// 移动指令
Movz { rd: Reg, imm: i32},
Movk { rd: Reg, imm: i32},
MovReg {rd: Reg, rn: Reg}, // 寄存器移动
// 分支指令
B { target: MirBlock }, // 无条件分支
Ret, // 函数返回
Adrp {rd: Reg, label: MirLabel}, // 加载全局变量标签
AddLabel {rd: Reg, rn: Reg, label: MirLabel},
}
pub struct MirInstData {
@ -109,17 +105,6 @@ impl MirInst {
};
ctx.alloc(data)
}
pub fn movk(ctx: &mut MirContext, rd: Reg, imm: i32) -> Self {
let kind = MirInstKind::Movk { rd, imm};
let data = MirInstData {
kind,
succ: None,
pre: None,
parent: None,
};
ctx.alloc(data)
}
pub fn b(ctx: &mut MirContext, target: MirBlock) -> Self {
let kind = MirInstKind::B { target };
@ -142,28 +127,6 @@ impl MirInst {
};
ctx.alloc(data)
}
pub fn adrp(ctx: &mut MirContext, rd: Reg, label: MirLabel) -> Self {
let kind = MirInstKind::Adrp { rd, label };
let data = MirInstData {
kind,
succ: None,
pre: None,
parent: None,
};
ctx.alloc(data)
}
pub fn add_label(ctx: &mut MirContext, rd: Reg, rn: Reg, label: MirLabel) -> Self {
let kind = MirInstKind::AddLabel { rd, rn, label };
let data = MirInstData {
kind,
succ: None,
pre: None,
parent: None,
};
ctx.alloc(data)
}
pub fn mov_reg(ctx: &mut MirContext, rd: Reg, rn: Reg) -> Self {
let kind = MirInstKind::MovReg { rd, rn };
@ -197,13 +160,10 @@ impl MirInst {
}
uses
}
MirInstKind::Movk { rd, imm:_ } => vec![*rd],
MirInstKind::MovReg { rd:_, rn } => vec![*rn],
MirInstKind::Movz { .. } => vec![],
MirInstKind::B { .. } => vec![],
MirInstKind::Ret => vec![],
MirInstKind::Adrp { .. } => vec![],
MirInstKind::AddLabel { rn, ..} => vec![*rn],
}
}
@ -214,12 +174,9 @@ impl MirInst {
MirInstKind::Ldr { rd, .. } => vec![*rd],
MirInstKind::Str { .. } => vec![],
MirInstKind::Movz { rd, imm:_ } => vec![*rd],
MirInstKind::Movk { rd, imm:_ } => vec![*rd],
MirInstKind::MovReg { rd, rn:_ } => vec![*rd],
MirInstKind::B { ..} => vec![],
MirInstKind::Ret => vec![],
MirInstKind::Adrp { rd, .. } => vec![*rd],
MirInstKind::AddLabel{ rd, .. } => vec![*rd],
}
}
@ -245,12 +202,9 @@ impl MirInst {
regs
}
MirInstKind::Movz { rd, .. } => vec![*rd],
MirInstKind::Movk { rd, .. } => vec![*rd],
MirInstKind::MovReg { rd, rn } => vec![*rd, *rn],
MirInstKind::B { .. } => vec![],
MirInstKind::Ret => vec![],
MirInstKind::Adrp { rd, .. } => vec![*rd],
MirInstKind::AddLabel { rd, rn, .. } => vec![*rd, *rn],
}
}
@ -311,11 +265,6 @@ impl MirInst {
*rd = to;
}
}
MirInstKind::Movk { rd, .. } => {
if *rd == from {
*rd = to;
}
}
MirInstKind::MovReg { rd, rn } => {
if *rd == from {
*rd = to;
@ -345,20 +294,6 @@ impl MirInst {
}
MirInstKind::B { .. } => {},
MirInstKind::Ret => {},
MirInstKind::Adrp { rd, .. } => {
if *rd == from {
*rd = to;
}
}
MirInstKind::AddLabel { rd, rn, ..} => {
if *rd == from {
*rd = to;
}
if *rn == from {
*rn = to;
}
}
}
}
}

44
src/backend/mir/regs.rs
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@ -1,7 +1,6 @@
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, PartialOrd, Ord)]
pub enum RegKind {
Integer,
Address,
}
@ -29,14 +28,6 @@ impl Reg {
}
pub fn is_vreg(&self) -> bool { matches!(self, Reg::V(_)) }
pub fn is_address(&self) -> bool {
match self {
Reg::P(preg) => preg.kind() == RegKind::Address,
Reg::V(vreg) => vreg.kind() == RegKind::Address,
}
}
}
// 手动实现PartialEq和Eq
@ -47,12 +38,8 @@ impl PartialEq for Reg {
(Reg::P(a), Reg::P(b)) => {
// 判断是否属于同一寄存器文件
match (a.kind(), b.kind()) {
// 通用寄存器文件（Integer和Address共享）
(RegKind::Integer, RegKind::Address)
| (RegKind::Address, RegKind::Integer)
| (RegKind::Integer, RegKind::Integer)
| (RegKind::Address, RegKind::Address) => a.0 == b.0,
// 通用寄存器文件（Integer共享）
(RegKind::Integer, RegKind::Integer) => a.0 == b.0,
// 不同寄存器文件（通用 vs 浮点）
_ => false,
}
@ -72,9 +59,9 @@ impl std::hash::Hash for Reg {
fn hash<H: std::hash::Hasher>(&self, state: &mut H) {
match self {
Reg::P(p) => {
// 通用寄存器（Integer/Address）和浮点寄存器使用不同的哈希域
// 通用寄存器（Integer）和浮点寄存器使用不同的哈希域
let domain = match p.kind() {
RegKind::Integer | RegKind::Address => 0u8,
RegKind::Integer => 0u8,
};
domain.hash(state);
p.0.hash(state);
@ -102,12 +89,6 @@ impl PReg {
_ => false,
}
}
pub const fn is_address(&self) -> bool {
match self.1 {
RegKind::Address => true,
_ => false,
}
}
pub fn hw_index(&self) -> u8 { self.0}
}
@ -132,21 +113,8 @@ impl From<PReg> for Reg {
fn from(preg: PReg) -> Self { Self::P(preg) }
}
#[rustfmt::skip]
// ARMV8-A64地址寄存器
pub const fn x_reg(index: u8) -> PReg { PReg::new(index, RegKind::Address) }
pub const fn x0() -> PReg { PReg::new(0, RegKind::Address) }
pub const fn x9() -> PReg { PReg::new(9, RegKind::Address) }
pub const fn x10() -> PReg { PReg::new(10, RegKind::Address) }
pub const fn x11() -> PReg { PReg::new(11, RegKind::Address) }
pub const fn x12() -> PReg { PReg::new(12, RegKind::Address) }
pub const fn x13() -> PReg { PReg::new(13, RegKind::Address) }
pub const fn x14() -> PReg { PReg::new(14, RegKind::Address) }
pub const fn x15() -> PReg { PReg::new(15, RegKind::Address) }
pub const fn x16() -> PReg { PReg::new(16, RegKind::Address) }
pub const fn x17() -> PReg { PReg::new(17, RegKind::Address) }
pub const fn sp() -> PReg { PReg::new(31, RegKind::Address) }
pub const fn xzr() -> PReg { PReg::new(32, RegKind::Address) }
pub const fn sp() -> PReg { PReg::new(31, RegKind::Integer) }
// ARMV8-A64整数寄存器
pub const fn w_reg(index: u8) -> PReg { PReg::new(index, RegKind::Integer) }
pub const fn w0() -> PReg { PReg::new(0, RegKind::Integer) }

233
src/backend/mirgen.rs
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@ -27,8 +27,6 @@ pub struct MirgenContext<'s> {
pub(super) curr_func: Option<MirFunction>,
pub(super) curr_block: Option<MirBlock>,
pub func_map: HashMap<MirFunction, Function>,
pub release: HashSet<Value>,
pub curr_cond: Option<(Value, InstructionKind)>,
}
pub trait MirGen {
@ -44,17 +42,7 @@ impl MirGen for GlobalData {
mirgen.globals.insert(name.clone(), label.clone());
match global.value(mirgen.ctx) {
ConstantValue::Int32 { value, .. } => {
let new_label = MirLabel::from(label_name.clone());
mirgen.mctx.add_raw_data(new_label, RawData::Bytes(vec![*value], 4));
}
ConstantValue::Zero {typ} | ConstantValue::Undef { typ }=> {
let size = typ.bytewidth(mirgen.ctx);
mirgen.mctx.add_raw_data(label.clone(), RawData::Bss(size));
}
ConstantValue::GlobalPtr { name: global_name, .. } => {
mirgen.globals.insert(global_name.clone(), MirLabel::from(global_name));
}
_ => todo!(),
}
}
}
@ -110,84 +98,15 @@ impl MirGen for ir::instruction::Instruction {
let lhs = self.get_operand(mirgen.ctx, 0).unwrap();
let rhs = self.get_operand(mirgen.ctx, 1).unwrap();
let temp_reg = mirgen.mctx.generate_vreg(regs::RegKind::Integer).into();
if !lhs.is_constant(mirgen.ctx) && !rhs.is_constant(mirgen.ctx) {
let lhs_reg = mirgen.generate_opd_reg(lhs);
let rhs_reg = mirgen.generate_opd_reg(rhs);
match op {
ir::instruction::BinaryOp::Add => {
let add = MirInst::add(&mut mirgen.mctx, temp_reg, lhs_reg, rhs_reg);
let _ = mirgen.curr_block.as_ref().unwrap().push_back(&mut mirgen.mctx, add);
}
_ => todo!("Unsupported binary operation: {:?}", op),
}
} else if !lhs.is_constant(mirgen.ctx) && rhs.is_constant(mirgen.ctx) {
let lhs_reg = mirgen.generate_opd_reg(lhs);
if let ir::value::ValueKind::Constant { value } = &rhs.deref(mirgen.ctx).unwrap().kind {
if let ConstantValue::Int32 { value, .. } = value {
match op {
ir::instruction::BinaryOp::Add => {
let addi = MirInst::addi(&mut mirgen.mctx, temp_reg, lhs_reg, *value as i32);
let _ = mirgen.curr_block.as_ref().unwrap().push_back(&mut mirgen.mctx, addi);
},
_ => todo!("Unsupported binary operation: {:?}", op),
}
} else {
panic!("Expected int32 onstant for right operand");
}
} else {
todo!();
}
} else if lhs.is_constant(mirgen.ctx) && rhs.is_constant(mirgen.ctx) {
if lhs.kind(mirgen.ctx).is_int32(mirgen.ctx){
let l_value;
let r_value;
let imm: i32;
if let ir::value::ValueKind::Constant { value } = &lhs.deref(mirgen.ctx).unwrap().kind {
if let ConstantValue::Int32 { value, .. } = value {
l_value = *value;
} else {
panic!("Expected int32 constant for left operand");
}
} else {
panic!("Expected int32 constant for left operand");
}
if let ir::value::ValueKind::Constant { value } = &rhs.deref(mirgen.ctx).unwrap().kind {
if let ConstantValue::Int32 { value, .. } = value {
r_value = *value;
} else {
panic!("Expected int32 constant for left operand");
}
} else {
panic!("Expected int32 constant for left operand");
}
match op {
ir::instruction::BinaryOp::Add => imm = l_value + r_value,
_ => todo!("Unsupported binary operation: {:?}", op),
}
mirgen.generate_movimm(temp_reg, imm);
} else {
panic!("Expected i32 constant for left operand");
}
} else {
let rhs_reg = mirgen.generate_opd_reg(rhs);
if let ir::value::ValueKind::Constant { value } = &lhs.deref(mirgen.ctx).unwrap().kind {
if let ConstantValue::Int32 { value, .. } = value {
match op {
ir::instruction::BinaryOp::Add => {
let addi = MirInst::addi(&mut mirgen.mctx, temp_reg, rhs_reg, *value);
let _ = mirgen.curr_block.as_ref().unwrap().push_back(&mut mirgen.mctx, addi);
}
_ => todo!("Unsupported binary operation: {:?}", op),
}
} else {
panic!("Unsupported constant type: {:?}", value);
}
} else {
panic!("Expected int32 constant for left operand");
let lhs_reg = mirgen.generate_opd_reg(lhs);
let rhs_reg = mirgen.generate_opd_reg(rhs);
match op {
ir::instruction::BinaryOp::Add => {
let add = MirInst::add(&mut mirgen.mctx, temp_reg, lhs_reg, rhs_reg);
let _ = mirgen.curr_block.as_ref().unwrap().push_back(&mut mirgen.mctx, add);
}
_ => todo!("Unsupported binary operation: {:?}", op),
}
// 记录结果
mirgen.table.insert(result_val, MirOperand {
typ: result_val.kind(mirgen.ctx),
kind: MirOperandKind::Reg(temp_reg),
@ -198,10 +117,8 @@ impl MirGen for ir::instruction::Instruction {
MemAccessOp::Alloca { typ } => {
let mut size = typ.bitwidth(mirgen.ctx);
size = (size + 7) / 8;
let current_offset = mirgen.curr_func.unwrap().current_stack_size(&mirgen.mctx);
let mem_loc = MemLoc::RegOffset { base: regs::sp().into(), offset: mirgen.curr_func.unwrap().current_stack_size(&mirgen.mctx) };
let _ = mirgen.curr_func.unwrap().add_current_stack_size(&mut mirgen.mctx, size as i32);
let total_stack = 0;
let mem_loc = MemLoc::RegOffset { base: regs::sp().into(), offset: total_stack+current_offset };
let mopd = MirOperand {
typ,
kind: MirOperandKind::Mem(mem_loc),
@ -211,32 +128,9 @@ impl MirGen for ir::instruction::Instruction {
MemAccessOp::Store => {
let val = self.get_operand(mirgen.ctx, 0).unwrap();
let ptr = self.get_operand(mirgen.ctx, 1).unwrap();
let is_global_ptr =
if let ir::value::ValueKind::Constant { value} = &ptr.deref(mirgen.ctx).unwrap().kind {
matches!(value, ConstantValue::GlobalPtr { .. })
}
else {
false
};
let mem_loc = if is_global_ptr {
let name =
if let ir::value::ValueKind::Constant {
value: ConstantValue::GlobalPtr { name, .. }
} = &ptr.deref(mirgen.ctx).unwrap().kind {name.clone()}
else {
unreachable!()
};
let label = mirgen.globals[&name].clone();
let temp_reg = mirgen.mctx.generate_vreg(regs::RegKind::Address).into();
mirgen.generate_adrp(temp_reg, label);
let mem = MemLoc::RegOffset { base: temp_reg, offset: 0 };
mem
}else {
let mem = match mirgen.table[&ptr].kind {
MirOperandKind::Mem(m) => m,
_ => unreachable!(),
};
mem
let mem_loc = match mirgen.table[&ptr].kind {
MirOperandKind::Mem(m) => m,
_ => unreachable!(),
};
match &val.deref(mirgen.ctx).unwrap().kind {
ir::value::ValueKind::Constant { value } => {
@ -260,36 +154,7 @@ impl MirGen for ir::instruction::Instruction {
MirOperandKind::Reg(reg) => {
mirgen.generate_str(reg, mem_loc);
}
MirOperandKind::Mem(MemLoc::Reg { address }) => {
mirgen.generate_str(address, mem_loc);
}
MirOperandKind::Mem(MemLoc::RegOffset { base, offset }) => {
let new_reg = mirgen.mctx.generate_vreg(regs::RegKind::Address).into();
let add = MirInst::addi(&mut mirgen.mctx, new_reg, base, offset);
mirgen.curr_block.as_ref().unwrap().push_back(&mut mirgen.mctx, add).unwrap();
let mem_loc = MemLoc::Reg { address: new_reg };
mirgen.generate_str(new_reg, mem_loc);
mirgen.table.insert(val, MirOperand {
typ: val.kind(mirgen.ctx),
kind: MirOperandKind::Mem(mem_loc),
});
mirgen.release.insert(val);
}
MirOperandKind::Mem(MemLoc::Reg2Offset { base, offset }) => {
let new_reg = mirgen.mctx.generate_vreg(regs::RegKind::Address).into();
let add = MirInst::add(&mut mirgen.mctx, new_reg, base, offset);
mirgen.curr_block.as_ref().unwrap().push_back(&mut mirgen.mctx, add).unwrap();
mirgen.generate_str(new_reg, mem_loc);
let mem_loc = MemLoc::Reg { address: new_reg };
mirgen.table.insert(val, MirOperand {
typ: val.kind(mirgen.ctx),
kind: MirOperandKind::Mem(mem_loc),
});
mirgen.release.insert(val);
}
_ => todo!(),
}
}
_ => todo!()
@ -298,37 +163,11 @@ impl MirGen for ir::instruction::Instruction {
MemAccessOp::Load => {
let ptr_val = self.get_operand(mirgen.ctx, 0).unwrap();
let result_val = self.get_result(mirgen.ctx).unwrap();
// 检查是否是全局变量
let is_global_ptr =
if let ir::value::ValueKind::Constant { value} = &ptr_val.deref(mirgen.ctx).unwrap().kind {
matches!(value, ConstantValue::GlobalPtr { .. })
}
else {
false
};
let mem_loc = if is_global_ptr {
let name =
if let ir::value::ValueKind::Constant {
value: ConstantValue::GlobalPtr { name, .. }
} = &ptr_val.deref(mirgen.ctx).unwrap().kind {name.clone()}
else {
unreachable!()
};
let label = mirgen.globals[&name].clone();
let temp_reg = mirgen.mctx.generate_vreg(regs::RegKind::Address).into();
mirgen.generate_adrp(temp_reg, label);
let mem = MemLoc::RegOffset { base: temp_reg, offset: 0 };
mem
} else {
let mem = match mirgen.table[&ptr_val].kind {
MirOperandKind::Mem(m) => m,
_ => unreachable!(),
};
mem
let mem_loc = match mirgen.table[&ptr_val].kind {
MirOperandKind::Mem(m) => m,
_ => unreachable!(),
};
let temp_reg = mirgen.mctx.generate_vreg(regs::RegKind::Integer).into()
;
let temp_reg = mirgen.mctx.generate_vreg(regs::RegKind::Integer).into();
mirgen.generate_ldr(temp_reg, mem_loc);
let mem_loc = MirOperandKind::Reg(temp_reg);
@ -371,8 +210,6 @@ impl<'s> MirgenContext<'s> {
curr_func: None,
curr_block: None,
func_map: HashMap::default(),
release: HashSet::default(),
curr_cond: None,
}
}
@ -413,22 +250,10 @@ impl<'s> MirgenContext<'s> {
}
for block in blocks {
self.curr_cond = None;
self.curr_block = Some(self.blocks[&block]);
for inst in block.iter(self.ctx) {
inst.mirgen(self);
}
let mut temp_table = HashMap::default();
for (val, opd) in self.table.iter() {
if self.release.contains(val){
continue;
} else {
temp_table.insert(*val, *opd);
}
}
self.release = HashSet::default();
self.table = temp_table;
}
}
}
@ -457,10 +282,7 @@ impl<'s> MirgenContext<'s> {
}
}
MirOperandKind::Mem(mem_loc) => {
self.generate_ldr(regs::Reg::P(ret_reg), mem_loc);
}
_ => todo!(),
}
}
_ => todo!(),
@ -469,7 +291,7 @@ impl<'s> MirgenContext<'s> {
pub fn generate_ret_reg(&mut self, ty: ir::typ::Typ) -> PReg {
if ty.is_ptr(self.ctx) {
regs::x0().into()
todo!()
} else {
regs::w0().into()
}
@ -490,14 +312,8 @@ impl<'s> MirgenContext<'s> {
}
pub fn generate_movimm(&mut self, rn: Reg, imm: i32) {
let low = imm & 0xFFFF;
let high = (imm >> 16) & 0xFFFF;
let movz = MirInst::movz(&mut self.mctx, rn, low);
let movz = MirInst::movz(&mut self.mctx, rn, imm);
let _ = self.curr_block.as_ref().unwrap().push_back(&mut self.mctx, movz);
if high != 0 {
let movk = MirInst::movk(&mut self.mctx, rn, high);
let _ = self.curr_block.as_ref().unwrap().push_back(&mut self.mctx, movk);
}
}
pub fn generate_str(&mut self, rm: Reg, mem_loc: MemLoc) {
@ -509,12 +325,5 @@ impl<'s> MirgenContext<'s> {
let ldr = MirInst::ldr(&mut self.mctx, rd, mem_loc);
let _ = self.curr_block.as_ref().unwrap().push_back(&mut self.mctx, ldr);
}
pub fn generate_adrp(&mut self, rd: Reg, label: MirLabel ) {
let adrp = MirInst::adrp(&mut self.mctx, rd, label.clone());
let _ = self.curr_block.as_ref().unwrap().push_back(&mut self.mctx, adrp);
let add_label = MirInst::add_label(&mut self.mctx, rd, rd, label.clone());
let _ = self.curr_block.as_ref().unwrap().push_back(&mut self.mctx, add_label);
}
}

12
src/backend/regalloc/naive_alloc.rs
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@ -25,9 +25,6 @@ pub fn regalloc(mctx: &mut MirContext) {
let integer_candidates = vec![
regs::w9(), regs::w10(), regs::w11(), regs::w12(), regs::w13(), regs::w14(), regs::w15(), regs::w16(), regs::w17(),
];
let address_candidates = vec![
regs::x9(), regs::x10(), regs::x11(), regs::x12(), regs::x13(), regs::x14(), regs::x15(), regs::x16(), regs::x17(),
];
let mut func_info = Vec::new();
for func_data in mctx.funcs.iter() {
@ -63,10 +60,7 @@ pub fn regalloc(mctx: &mut MirContext) {
let vregs: Vec<_> = all_vregs.iter().collect();
for &vreg in &vregs {
let preg = match vreg.kind() {
regs::RegKind::Integer => allocate_reg(mctx, *vreg, &integer_candidates, &mut available_regs),
regs::RegKind::Address => allocate_reg(mctx, *vreg, &address_candidates, &mut available_regs),
};
let preg = allocate_reg(mctx, *vreg, &integer_candidates, &mut available_regs);
if let Some(preg) = preg {
reg_map.insert(vreg, preg);
}
@ -96,8 +90,8 @@ pub fn regalloc(mctx: &mut MirContext) {
pub fn generate_prologue(mctx: &mut MirContext, function: MirFunction) {
let mut stack_size = function.storage_stack_size(mctx);
stack_size = (stack_size + 15) & !15;
let sub = MirInst::subi(mctx, regs::sp().into(), regs::sp().into(), stack_size);
function.head(mctx).unwrap().push_front(mctx, sub).unwrap();
let subi = MirInst::subi(mctx, regs::sp().into(), regs::sp().into(), stack_size);
function.head(mctx).unwrap().push_front(mctx, subi).unwrap();
}
pub fn generate_epilogue(mctx: &mut MirContext, function: MirFunction) {

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