forked from ppg69fuwb/riscv-lab
Compare commits
3 Commits
| Author | SHA1 | Date |
|---|---|---|
 Liphen
|
30d128fa17 | 10 months ago |
|
Liphen
|
341476ed8d | 10 months ago |
|
Liphen
|
7f8fe89c78 | 10 months ago |
@ -1,54 +0,0 @@
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module top(
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input clock,
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input reset,
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// Interrupts
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input mei, // to PLIC
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input msi, // to CLINT
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input mti, // to CLINT
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input sei, // to PLIC
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// inst sram interface
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output inst_sram_en,
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output [ 3:0] inst_sram_wen,
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output [31:0] inst_sram_addr,
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output [31:0] inst_sram_wdata,
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input [31:0] inst_sram_rdata,
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// data sram interface
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output data_sram_en,
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output [ 7:0] data_sram_wen,
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output [31:0] data_sram_addr,
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output [63:0] data_sram_wdata,
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input [63:0] data_sram_rdata,
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// trace debug interface
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output debug_commit,
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output [63:0] debug_pc,
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output [4:0 ] debug_rf_wnum,
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output [63:0] debug_rf_wdata
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);
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PuaCpu core(
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.clock (clock),
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.reset (reset),
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// interrupts
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.io_ext_int_mei (mei),
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.io_ext_int_mti (mti),
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.io_ext_int_msi (msi),
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// inst sram interface
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.io_inst_sram_en (inst_sram_en),
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.io_inst_sram_wen (inst_sram_wen),
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.io_inst_sram_addr (inst_sram_addr),
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.io_inst_sram_wdata (inst_sram_wdata),
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.io_inst_sram_rdata (inst_sram_rdata),
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// data sram interface
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.io_data_sram_en (data_sram_en),
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.io_data_sram_wen (data_sram_wen),
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.io_data_sram_addr (data_sram_addr),
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.io_data_sram_wdata (data_sram_wdata),
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.io_data_sram_rdata (data_sram_rdata),
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// debug
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.io_debug_pc (debug_pc),
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.io_debug_commit (debug_commit),
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.io_debug_rf_wnum (debug_rf_wnum),
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.io_debug_rf_wdata (debug_rf_wdata)
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);
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endmodule
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@ -0,0 +1,68 @@
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package gcd
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import chisel3._
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import chisel3.util.Decoupled
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class GcdInputBundle(val w: Int) extends Bundle {
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val value1 = UInt(w.W)
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val value2 = UInt(w.W)
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}
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class GcdOutputBundle(val w: Int) extends Bundle {
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val value1 = UInt(w.W)
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val value2 = UInt(w.W)
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val gcd = UInt(w.W)
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}
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/** Compute Gcd using subtraction method. Subtracts the smaller from the larger until register y is zero. value input
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* register x is then the Gcd. Unless first input is zero then the Gcd is y. Can handle stalls on the producer or
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* consumer side
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*/
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class DecoupledGcd(width: Int) extends Module {
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val input = IO(Flipped(Decoupled(new GcdInputBundle(width))))
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val output = IO(Decoupled(new GcdOutputBundle(width)))
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val xInitial = Reg(UInt())
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val yInitial = Reg(UInt())
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val x = Reg(UInt())
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val y = Reg(UInt())
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val busy = RegInit(false.B)
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val resultValid = RegInit(false.B)
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input.ready := !busy
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output.valid := resultValid
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output.bits := DontCare
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when(busy) {
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when(x > y) {
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x := x - y
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}.otherwise {
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y := y - x
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}
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when(x === 0.U || y === 0.U) {
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when(x === 0.U) {
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output.bits.gcd := y
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}.otherwise {
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output.bits.gcd := x
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}
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output.bits.value1 := xInitial
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output.bits.value2 := yInitial
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resultValid := true.B
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when(output.ready && resultValid) {
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busy := false.B
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resultValid := false.B
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}
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}
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}.otherwise {
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when(input.valid) {
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val bundle = input.deq()
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x := bundle.value1
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y := bundle.value2
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xInitial := bundle.value1
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yInitial := bundle.value2
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busy := true.B
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}
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}
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}
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@ -1,9 +1,12 @@
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import cpu._
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import circt.stage._
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object Elaborate extends App {
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implicit val cpuConfig = new CpuConfig()
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def top = new PuaCpu()
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val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
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(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
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}
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val firtoolOptions = Array(
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"--lowering-options=" + List(
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// make yosys happy
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// see https://github.com/llvm/circt/blob/main/docs/VerilogGeneration.md
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"disallowLocalVariables",
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"disallowPackedArrays",
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"locationInfoStyle=wrapInAtSquareBracket"
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).reduce(_ + "," + _)
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)
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circt.stage.ChiselStage.emitSystemVerilogFile(new gcd.GCD(), args, firtoolOptions)
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}
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@ -0,0 +1,29 @@
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package gcd
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import chisel3._
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/** Compute GCD using subtraction method. Subtracts the smaller from the larger until register y is zero. value in
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* register x is then the GCD
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*/
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class GCD extends Module {
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val io = IO(new Bundle {
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val value1 = Input(UInt(16.W))
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val value2 = Input(UInt(16.W))
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val loadingValues = Input(Bool())
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val outputGCD = Output(UInt(16.W))
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val outputValid = Output(Bool())
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})
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val x = Reg(UInt())
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val y = Reg(UInt())
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when(x > y) { x := x - y }.otherwise { y := y - x }
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when(io.loadingValues) {
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x := io.value1
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y := io.value2
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}
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io.outputGCD := x
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io.outputValid := y === 0.U
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}
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@ -1,20 +0,0 @@
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import chisel3._
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import chisel3.util._
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import cpu._
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import cpu.defines._
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class PuaCpu extends Module {
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val inst_sram = new InstSram()
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val data_sram = new DataSram()
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val debug = new DEBUG()
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})
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val core = Module(new Core())
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io.ext_int <> core.io.interrupt
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io.inst_sram <> core.io.instSram
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io.data_sram <> core.io.dataSram
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io.debug <> core.io.debug
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}
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@ -1,42 +0,0 @@
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package cpu.defines
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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trait CoreParameter {
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def cpuConfig = new CpuConfig
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val XLEN = if (cpuConfig.isRV32) 32 else 64
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val VADDR_WID = if (cpuConfig.isRV32) 32 else 39
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val PADDR_WID = 32
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}
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trait Constants extends CoreParameter {
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// 全局
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val PC_INIT = "h80000000".U(XLEN.W)
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val INT_WID = 12
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val EXC_WID = 16
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// inst rom
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val INST_WID = 32
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// GPR RegFile
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val AREG_NUM = 32
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val REG_ADDR_WID = 5
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}
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trait SRAMConst extends Constants {
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val SRAM_ADDR_WID = PADDR_WID // 32
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val DATA_SRAM_DATA_WID = XLEN
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val DATA_SRAM_WEN_WID = XLEN / 8
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val INST_SRAM_DATA_WID = INST_WID
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val INST_SRAM_WEN_WID = INST_WID / 8
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}
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object Const extends Constants with SRAMConst
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object Instructions extends HasInstrType with CoreParameter {
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def NOP = 0x00000013.U
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val DecodeDefault = List(InstrN, FuType.alu, ALUOpType.add)
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def DecodeTable = RVIInstr.table
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}
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@ -1,29 +0,0 @@
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package cpu.defines
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import chisel3._
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import chisel3.util._
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object SignedExtend {
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def apply(a: UInt, len: Int) = {
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val aLen = a.getWidth
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val signBit = a(aLen - 1)
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if (aLen >= len) a(len - 1, 0) else Cat(Fill(len - aLen, signBit), a)
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}
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}
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object ZeroExtend {
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def apply(a: UInt, len: Int) = {
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val aLen = a.getWidth
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if (aLen >= len) a(len - 1, 0) else Cat(0.U((len - aLen).W), a)
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}
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}
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object LookupTree {
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def apply[T <: Data](key: UInt, mapping: Iterable[(UInt, T)]): T =
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Mux1H(mapping.map(p => (p._1 === key, p._2)))
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}
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object LookupTreeDefault {
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def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
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MuxLookup(key, default)(mapping.toSeq)
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}
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@ -1,36 +0,0 @@
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package cpu.defines
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import chisel3._
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import chisel3.util._
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// 指令类型
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trait HasInstrType {
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def InstrN = "b000".U
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def InstrI = "b100".U
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def InstrR = "b101".U
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def InstrS = "b010".U
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def InstrB = "b001".U
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def InstrU = "b110".U
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def InstrJ = "b111".U
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// I、R、U、J类型的指令都需要写寄存器
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def isRegWen(instrType: UInt): Bool = instrType(2)
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}
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// 功能单元类型 Function Unit Type
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object FuType {
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def num = 1
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def alu = 0.U // arithmetic logic unit
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def apply() = UInt(log2Up(num).W)
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}
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// 功能单元操作类型 Function Unit Operation Type
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object FuOpType {
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def apply() = UInt(5.W) // 宽度与最大的功能单元操作类型宽度一致
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}
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// 算术逻辑单元操作类型 Arithmetic Logic Unit Operation Type
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object ALUOpType {
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def add = "b00000".U
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// TODO: 定义更多的ALU操作类型
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}
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@ -1,30 +0,0 @@
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package cpu.pipeline
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class IfIdData extends Bundle {
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val inst = UInt(XLEN.W)
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val valid = Bool()
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val pc = UInt(XLEN.W)
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}
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class FetchUnitDecodeUnit extends Bundle {
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val data = Output(new IfIdData())
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}
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class DecodeStage extends Module {
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val io = IO(new Bundle {
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val fetchUnit = Flipped(new FetchUnitDecodeUnit())
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val decodeUnit = new FetchUnitDecodeUnit()
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})
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val data = RegInit(0.U.asTypeOf(new IfIdData()))
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data := io.fetchUnit.data
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io.decodeUnit.data := data
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}
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@ -1,38 +0,0 @@
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package cpu.pipeline
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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class DecodeUnit extends Module {
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val io = IO(new Bundle {
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// 输入
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val decodeStage = Flipped(new FetchUnitDecodeUnit())
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val regfile = new Src12Read()
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// 输出
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val executeStage = Output(new DecodeUnitExecuteUnit())
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})
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// 译码阶段完成指令的译码操作以及源操作数的准备
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val decoder = Module(new Decoder()).io
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decoder.in.inst := io.decodeStage.data.inst
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val pc = io.decodeStage.data.pc
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val info = Wire(new Info())
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info := decoder.out.info
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info.valid := io.decodeStage.data.valid
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// TODO:完成寄存器堆的读取
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// io.regfile.src1.raddr :=
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// io.regfile.src2.raddr :=
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// TODO: 完成DecodeUnit模块的逻辑
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// io.executeStage.data.pc :=
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// io.executeStage.data.info :=
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// io.executeStage.data.src_info.src1_data :=
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// io.executeStage.data.src_info.src2_data :=
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}
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@ -1,28 +0,0 @@
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package cpu.pipeline
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class IdExeData extends Bundle {
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val pc = UInt(XLEN.W)
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val info = new Info()
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val src_info = new SrcInfo()
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||||
}
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class DecodeUnitExecuteUnit extends Bundle {
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val data = new IdExeData()
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}
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class ExecuteStage extends Module {
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val io = IO(new Bundle {
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val decodeUnit = Input(new DecodeUnitExecuteUnit())
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val executeUnit = Output(new DecodeUnitExecuteUnit())
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})
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val data = RegInit(0.U.asTypeOf(new IdExeData()))
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// TODO: 完成ExecuteStage模块的逻辑
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}
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@ -1,31 +0,0 @@
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package cpu.pipeline
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||||
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import chisel3._
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import chisel3.util._
|
||||
import cpu.CpuConfig
|
||||
import cpu.defines._
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||||
import cpu.defines.Const._
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||||
import chisel3.util.experimental.BoringUtils
|
||||
|
||||
class ExecuteUnit extends Module {
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||||
val io = IO(new Bundle {
|
||||
val executeStage = Input(new DecodeUnitExecuteUnit())
|
||||
val memoryStage = Output(new ExecuteUnitMemoryUnit())
|
||||
val dataSram = new DataSram()
|
||||
})
|
||||
|
||||
// 执行阶段完成指令的执行操作
|
||||
|
||||
val fu = Module(new Fu()).io
|
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fu.data.pc := io.executeStage.data.pc
|
||||
fu.data.info := io.executeStage.data.info
|
||||
fu.data.src_info := io.executeStage.data.src_info
|
||||
|
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io.dataSram <> fu.dataSram
|
||||
|
||||
// TODO: 完成ExecuteUnit模块的逻辑
|
||||
// io.memoryStage.data.pc :=
|
||||
// io.memoryStage.data.info :=
|
||||
// io.memoryStage.data.src_info :=
|
||||
// io.memoryStage.data.rd_info :=
|
||||
}
|
||||
@ -1,32 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class Fu extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val data = new Bundle {
|
||||
val pc = Input(UInt(XLEN.W))
|
||||
val info = Input(new Info())
|
||||
val src_info = Input(new SrcInfo())
|
||||
val rd_info = Output(new RdInfo())
|
||||
}
|
||||
|
||||
val dataSram = new DataSram()
|
||||
})
|
||||
|
||||
val alu = Module(new Alu()).io
|
||||
|
||||
io.dataSram.en := false.B
|
||||
io.dataSram.addr := DontCare
|
||||
io.dataSram.wdata := DontCare
|
||||
io.dataSram.wen := 0.U
|
||||
|
||||
alu.info := io.data.info
|
||||
alu.src_info := io.data.src_info
|
||||
|
||||
io.data.rd_info.wdata := alu.result
|
||||
}
|
||||
@ -1,15 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
|
||||
class Alu extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val info = Input(new Info())
|
||||
val src_info = Input(new SrcInfo())
|
||||
val result = Output(UInt(XLEN.W))
|
||||
})
|
||||
// TODO: 完成ALU模块的逻辑
|
||||
}
|
||||
@ -1,41 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
import cpu.defines._
|
||||
|
||||
class FetchUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val decodeStage = new FetchUnitDecodeUnit()
|
||||
val instSram = new InstSram()
|
||||
})
|
||||
|
||||
val boot :: send :: receive :: Nil = Enum(3)
|
||||
val state = RegInit(boot)
|
||||
|
||||
switch(state) {
|
||||
is(boot) {
|
||||
state := send
|
||||
}
|
||||
is(send) {
|
||||
state := receive
|
||||
}
|
||||
is(receive) {}
|
||||
}
|
||||
|
||||
// 取指阶段完成指令的取指操作
|
||||
|
||||
val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), state =/= boot)
|
||||
|
||||
io.instSram.addr := pc + 4.U
|
||||
|
||||
io.decodeStage.data.valid := state === receive
|
||||
io.decodeStage.data.pc := pc
|
||||
io.decodeStage.data.inst := io.instSram.rdata
|
||||
|
||||
io.instSram.en := !reset.asBool
|
||||
io.instSram.wen := 0.U
|
||||
io.instSram.wdata := 0.U
|
||||
}
|
||||
@ -1,29 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class ExeMemData extends Bundle {
|
||||
val pc = UInt(XLEN.W)
|
||||
val info = new Info()
|
||||
val rd_info = new RdInfo()
|
||||
val src_info = new SrcInfo()
|
||||
}
|
||||
|
||||
class ExecuteUnitMemoryUnit extends Bundle {
|
||||
val data = new ExeMemData()
|
||||
}
|
||||
|
||||
class MemoryStage extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val executeUnit = Input(new ExecuteUnitMemoryUnit())
|
||||
val memoryUnit = Output(new ExecuteUnitMemoryUnit())
|
||||
})
|
||||
|
||||
val data = RegInit(0.U.asTypeOf(new ExeMemData()))
|
||||
|
||||
// TODO: 完成MemoryStage模块的逻辑
|
||||
}
|
||||
@ -1,21 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.util.experimental.BoringUtils
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class MemoryUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val memoryStage = Input(new ExecuteUnitMemoryUnit())
|
||||
val writeBackStage = Output(new MemoryUnitWriteBackUnit())
|
||||
})
|
||||
|
||||
// 访存阶段完成指令的访存操作
|
||||
|
||||
io.writeBackStage.data.pc := io.memoryStage.data.pc
|
||||
io.writeBackStage.data.info := io.memoryStage.data.info
|
||||
io.writeBackStage.data.rd_info.wdata := io.memoryStage.data.rd_info.wdata
|
||||
}
|
||||
@ -1,27 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class MemWbData extends Bundle {
|
||||
val pc = UInt(XLEN.W)
|
||||
val info = new Info()
|
||||
val rd_info = new RdInfo()
|
||||
}
|
||||
|
||||
class MemoryUnitWriteBackUnit extends Bundle {
|
||||
val data = new MemWbData()
|
||||
}
|
||||
class WriteBackStage extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val memoryUnit = Input(new MemoryUnitWriteBackUnit())
|
||||
val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
|
||||
})
|
||||
|
||||
val data = RegInit(0.U.asTypeOf(new MemWbData()))
|
||||
|
||||
// TODO: 完成WriteBackStage模块的逻辑
|
||||
}
|
||||
@ -1,19 +0,0 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class WriteBackUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val writeBackStage = Input(new MemoryUnitWriteBackUnit())
|
||||
val regfile = Output(new RegWrite())
|
||||
val debug = new DEBUG()
|
||||
})
|
||||
|
||||
// 写回阶段完成数据的写回操作
|
||||
// 同时该阶段还负责差分测试的比对工作
|
||||
// TODO: 完成WriteBackUnit模块的逻辑
|
||||
}
|
||||
@ -1,9 +1,68 @@
|
||||
// import cpu._
|
||||
// import circt.stage._
|
||||
|
||||
// object TestMain extends App {
|
||||
// implicit val cpuConfig = new CpuConfig()
|
||||
// def top = new Top()
|
||||
// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
|
||||
// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
|
||||
// }
|
||||
// See README.md for license details.
|
||||
|
||||
package gcd
|
||||
|
||||
import chisel3._
|
||||
import chisel3.experimental.BundleLiterals._
|
||||
import chisel3.simulator.EphemeralSimulator._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
import org.scalatest.matchers.must.Matchers
|
||||
|
||||
/** This is a trivial example of how to run this Specification From within sbt use:
|
||||
* {{{
|
||||
* testOnly gcd.GCDSpec
|
||||
* }}}
|
||||
* From a terminal shell use:
|
||||
* {{{
|
||||
* sbt 'testOnly gcd.GCDSpec'
|
||||
* }}}
|
||||
* Testing from mill:
|
||||
* {{{
|
||||
* mill %NAME%.test.testOnly gcd.GCDSpec
|
||||
* }}}
|
||||
*/
|
||||
class GCDSpec extends AnyFreeSpec with Matchers {
|
||||
"Gcd should calculate proper greatest common denominator" in {
|
||||
simulate(new DecoupledGcd(16)) { dut =>
|
||||
val testValues = for {
|
||||
x <- 0 to 10
|
||||
y <- 0 to 10
|
||||
} yield (x, y)
|
||||
val inputSeq = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) }
|
||||
val resultSeq = testValues.map { case (x, y) =>
|
||||
(new GcdOutputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U)
|
||||
}
|
||||
|
||||
dut.reset.poke(true.B)
|
||||
dut.clock.step()
|
||||
dut.reset.poke(false.B)
|
||||
dut.clock.step()
|
||||
|
||||
var sent, received, cycles: Int = 0
|
||||
while (sent != 100 && received != 100) {
|
||||
assert(cycles <= 1000, "timeout reached")
|
||||
|
||||
if (sent < 100) {
|
||||
dut.input.valid.poke(true.B)
|
||||
dut.input.bits.value1.poke(testValues(sent)._1.U)
|
||||
dut.input.bits.value2.poke(testValues(sent)._2.U)
|
||||
if (dut.input.ready.peek().litToBoolean) {
|
||||
sent += 1
|
||||
}
|
||||
}
|
||||
|
||||
if (received < 100) {
|
||||
dut.output.ready.poke(true.B)
|
||||
if (dut.output.valid.peekValue().asBigInt == 1) {
|
||||
dut.output.bits.gcd.expect(BigInt(testValues(received)._1).gcd(testValues(received)._2))
|
||||
received += 1
|
||||
}
|
||||
}
|
||||
|
||||
// Step the simulation forward.
|
||||
dut.clock.step()
|
||||
cycles += 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,7 +1,4 @@
|
||||
*.vcd
|
||||
obj_dir
|
||||
|
||||
core/*
|
||||
!core/top_sram_wrapper.v
|
||||
|
||||
trace.*
|
||||
|
||||
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