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3280 lines
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3280 lines
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<a href="#func-members">Functions</a> |
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<a href="#var-members">Variables</a> </div>
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<div class="headertitle">
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<div class="title">REG (specific to the IA-32 and Intel(R) 64 architectures)<div class="ingroups"><a class="el" href="group__REG__BASIC__API.html">REG: Register Object</a></div></div> </div>
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</div><!--header-->
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<div class="contents">
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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Classes</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structLEVEL__BASE_1_1REGDEF__ENTRY.html">LEVEL_BASE::REGDEF_ENTRY</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:ga1d2569f4080aa0e3aaa0939d9fe2dcff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga1d2569f4080aa0e3aaa0939d9fe2dcff">_REGSBIT</a>(regSubClass)   (REG_SUBCLASS_BITS(1) << (regSubClass))</td></tr>
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<tr class="separator:ga1d2569f4080aa0e3aaa0939d9fe2dcff"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr class="memitem:ga5b0b71675518f3b3e967334d71a967d4"><td class="memItemLeft" align="right" valign="top">typedef UINT64 </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">LEVEL_BASE::REG_CLASS_BITS</a></td></tr>
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<tr class="separator:ga5b0b71675518f3b3e967334d71a967d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae457153aab05650d6845e3553731ee63"><td class="memItemLeft" align="right" valign="top">typedef class <a class="el" href="classLEVEL__CORE_1_1REGISTER__SET.html">REGISTER_SET</a>< <a class="el" href="group__REG__CPU__IA32.html#ga106d11b76262e7d9efa0cce801cf8431">REG_FirstInRegset</a>, <a class="el" href="group__REG__CPU__IA32.html#gac3c3f8a822d40e53bc8c599368eb9a44">REG_LastInRegset</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">LEVEL_CORE::REGSET</a></td></tr>
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<tr class="separator:gae457153aab05650d6845e3553731ee63"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
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Enumerations</h2></td></tr>
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<tr class="memitem:ga0f57fb50e80d686a588694f73046f2aa"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">LEVEL_BASE::REG</a> { <br />
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  <b>REG_INVALID_</b> = 0,
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<br />
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  <b>REG_GR_BASE</b> = REG_RBASE,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa03e03ec8e94b01093af076b12f1f3475">LEVEL_BASE::REG_RDI</a> = REG_GR_BASE,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa337de7ddb5083c8150ecfd66f2320203">LEVEL_BASE::REG_GDI</a> = REG_RDI,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaae050d1f0a9ae69dcc0fb2b303f174d0f">LEVEL_BASE::REG_RSI</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa710b4b9dba626781fd61d7b08350973f">LEVEL_BASE::REG_GSI</a> = REG_RSI,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa5baaabaef51b5dd11f040640090e07cb">LEVEL_BASE::REG_RBP</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa9ac90dd9547c5c3bb9463924613f2a31">LEVEL_BASE::REG_GBP</a> = REG_RBP,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaeec98ba4f5e70e7edaf1a2ff009fb838">LEVEL_BASE::REG_RSP</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa2a6956c6a8b5a16cd95bf2f33586e10a">LEVEL_BASE::REG_STACK_PTR</a> = REG_RSP,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa2b24a77d9d484a3ff972dc177890b079">LEVEL_BASE::REG_RBX</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaafcbff5028eb036d075ce6bd9924e3290">LEVEL_BASE::REG_GBX</a> = REG_RBX,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa488d066ae5c50671c998593b454f8ebe">LEVEL_BASE::REG_RDX</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa3ee773f2e43a1ba875bb1bf483d74538">LEVEL_BASE::REG_GDX</a> = REG_RDX,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa6197f1f161d556e22841eb7abc34d6d9">LEVEL_BASE::REG_RCX</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaadfd07d546c44412017887acbcadd168e">LEVEL_BASE::REG_GCX</a> = REG_RCX,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa4f0ecf75bc9d4958868f226cf6f001a5">LEVEL_BASE::REG_RAX</a>,
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<br />
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  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaccca04b646ec41c6737d77a2c2369e86">LEVEL_BASE::REG_GAX</a> = REG_RAX,
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<br />
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  <b>REG_R8</b>,
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<br />
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  <b>REG_R9</b>,
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<br />
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  <b>REG_R10</b>,
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<br />
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  <b>REG_R11</b>,
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<br />
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  <b>REG_R12</b>,
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<br />
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  <b>REG_R13</b>,
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<br />
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  <b>REG_R14</b>,
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<br />
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  <b>REG_R15</b>,
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<br />
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  <b>REG_GR_LAST</b> = REG_R15,
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<br />
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  <b>REG_SEG_BASE</b>,
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<br />
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  <b>REG_SEG_CS</b> = REG_SEG_BASE,
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<br />
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  <b>REG_SEG_SS</b>,
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<br />
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  <b>REG_SEG_DS</b>,
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<br />
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  <b>REG_SEG_ES</b>,
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<br />
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  <b>REG_SEG_FS</b>,
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<br />
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  <b>REG_SEG_GS</b>,
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<br />
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  <b>REG_SEG_LAST</b> = REG_SEG_GS,
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<br />
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  <b>REG_RFLAGS</b>,
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<br />
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  <b>REG_GFLAGS</b> =REG_RFLAGS,
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<br />
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  <b>REG_RIP</b>,
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<br />
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  <b>REG_INST_PTR</b> = REG_RIP,
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<br />
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  <b>REG_AL</b>,
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<br />
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  <b>REG_AH</b>,
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<br />
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  <b>REG_AX</b>,
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<br />
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  <b>REG_CL</b>,
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<br />
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  <b>REG_CH</b>,
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<br />
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  <b>REG_CX</b>,
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<br />
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  <b>REG_DL</b>,
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<br />
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  <b>REG_DH</b>,
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<br />
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  <b>REG_DX</b>,
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<br />
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  <b>REG_BL</b>,
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<br />
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  <b>REG_BH</b>,
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<br />
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  <b>REG_BX</b>,
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<br />
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  <b>REG_BP</b>,
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<br />
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  <b>REG_SI</b>,
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<br />
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  <b>REG_DI</b>,
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<br />
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  <b>REG_SP</b>,
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<br />
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  <b>REG_FLAGS</b>,
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<br />
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  <b>REG_IP</b>,
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<br />
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  <b>REG_EDI</b>,
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<br />
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  <b>REG_DIL</b>,
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<br />
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  <b>REG_ESI</b>,
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<br />
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  <b>REG_SIL</b>,
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<br />
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  <b>REG_EBP</b>,
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<br />
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  <b>REG_BPL</b>,
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<br />
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  <b>REG_ESP</b>,
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<br />
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  <b>REG_SPL</b>,
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<br />
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  <b>REG_EBX</b>,
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<br />
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  <b>REG_EDX</b>,
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<br />
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  <b>REG_ECX</b>,
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<br />
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  <b>REG_EAX</b>,
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<br />
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  <b>REG_EFLAGS</b>,
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<br />
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  <b>REG_EIP</b>,
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<br />
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  <b>REG_R8B</b>,
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<br />
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  <b>REG_R8W</b>,
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<br />
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  <b>REG_R8D</b>,
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<br />
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  <b>REG_R9B</b>,
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<br />
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  <b>REG_R9W</b>,
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<br />
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  <b>REG_R9D</b>,
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<br />
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  <b>REG_R10B</b>,
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<br />
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  <b>REG_R10W</b>,
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<br />
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  <b>REG_R10D</b>,
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<br />
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  <b>REG_R11B</b>,
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<br />
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  <b>REG_R11W</b>,
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<br />
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  <b>REG_R11D</b>,
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<br />
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  <b>REG_R12B</b>,
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<br />
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  <b>REG_R12W</b>,
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<br />
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  <b>REG_R12D</b>,
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<br />
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  <b>REG_R13B</b>,
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<br />
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  <b>REG_R13W</b>,
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<br />
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  <b>REG_R13D</b>,
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<br />
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  <b>REG_R14B</b>,
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<br />
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  <b>REG_R14W</b>,
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<br />
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  <b>REG_R14D</b>,
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<br />
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  <b>REG_R15B</b>,
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<br />
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  <b>REG_R15W</b>,
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<br />
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  <b>REG_R15D</b>,
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<br />
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  <b>REG_MM_BASE</b>,
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<br />
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  <b>REG_MM0</b> = REG_MM_BASE,
|
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<br />
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  <b>REG_MM1</b>,
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<br />
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  <b>REG_MM2</b>,
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<br />
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  <b>REG_MM3</b>,
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<br />
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  <b>REG_MM4</b>,
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<br />
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  <b>REG_MM5</b>,
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<br />
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  <b>REG_MM6</b>,
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<br />
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  <b>REG_MM7</b>,
|
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<br />
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  <b>REG_MM_LAST</b> = REG_MM7,
|
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<br />
|
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  <b>REG_XMM_BASE</b>,
|
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<br />
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  <b>REG_FIRST_FP_REG</b> = REG_XMM_BASE,
|
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<br />
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  <b>REG_XMM0</b> = REG_XMM_BASE,
|
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<br />
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  <b>REG_XMM1</b>,
|
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<br />
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  <b>REG_XMM2</b>,
|
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<br />
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  <b>REG_XMM3</b>,
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<br />
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  <b>REG_XMM4</b>,
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<br />
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  <b>REG_XMM5</b>,
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<br />
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  <b>REG_XMM6</b>,
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<br />
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  <b>REG_XMM7</b>,
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<br />
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  <b>REG_XMM8</b>,
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<br />
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  <b>REG_XMM9</b>,
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<br />
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  <b>REG_XMM10</b>,
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<br />
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  <b>REG_XMM11</b>,
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<br />
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  <b>REG_XMM12</b>,
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<br />
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  <b>REG_XMM13</b>,
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<br />
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  <b>REG_XMM14</b>,
|
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<br />
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  <b>REG_XMM15</b>,
|
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<br />
|
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  <b>REG_XMM_SSE_LAST</b> = REG_XMM15,
|
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<br />
|
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  <b>REG_XMM_AVX_LAST</b> = REG_XMM_SSE_LAST,
|
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<br />
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  <b>REG_XMM_AVX512_HI16_FIRST</b>,
|
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<br />
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  <b>REG_XMM16</b> = REG_XMM_AVX512_HI16_FIRST,
|
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<br />
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  <b>REG_XMM17</b>,
|
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<br />
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  <b>REG_XMM18</b>,
|
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<br />
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  <b>REG_XMM19</b>,
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<br />
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  <b>REG_XMM20</b>,
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<br />
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  <b>REG_XMM21</b>,
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<br />
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  <b>REG_XMM22</b>,
|
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<br />
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  <b>REG_XMM23</b>,
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<br />
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  <b>REG_XMM24</b>,
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<br />
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  <b>REG_XMM25</b>,
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<br />
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  <b>REG_XMM26</b>,
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<br />
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  <b>REG_XMM27</b>,
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<br />
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  <b>REG_XMM28</b>,
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<br />
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  <b>REG_XMM29</b>,
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<br />
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|
  <b>REG_XMM30</b>,
|
|
<br />
|
|
  <b>REG_XMM31</b>,
|
|
<br />
|
|
  <b>REG_XMM_AVX512_HI16_LAST</b> = REG_XMM31,
|
|
<br />
|
|
  <b>REG_XMM_AVX512_LAST</b> = REG_XMM_AVX512_HI16_LAST,
|
|
<br />
|
|
  <b>REG_XMM_LAST</b> = REG_XMM_AVX512_LAST,
|
|
<br />
|
|
  <b>REG_YMM_BASE</b>,
|
|
<br />
|
|
  <b>REG_YMM0</b> = REG_YMM_BASE,
|
|
<br />
|
|
  <b>REG_YMM1</b>,
|
|
<br />
|
|
  <b>REG_YMM2</b>,
|
|
<br />
|
|
  <b>REG_YMM3</b>,
|
|
<br />
|
|
  <b>REG_YMM4</b>,
|
|
<br />
|
|
  <b>REG_YMM5</b>,
|
|
<br />
|
|
  <b>REG_YMM6</b>,
|
|
<br />
|
|
  <b>REG_YMM7</b>,
|
|
<br />
|
|
  <b>REG_YMM8</b>,
|
|
<br />
|
|
  <b>REG_YMM9</b>,
|
|
<br />
|
|
  <b>REG_YMM10</b>,
|
|
<br />
|
|
  <b>REG_YMM11</b>,
|
|
<br />
|
|
  <b>REG_YMM12</b>,
|
|
<br />
|
|
  <b>REG_YMM13</b>,
|
|
<br />
|
|
  <b>REG_YMM14</b>,
|
|
<br />
|
|
  <b>REG_YMM15</b>,
|
|
<br />
|
|
  <b>REG_YMM_AVX_LAST</b> = REG_YMM15,
|
|
<br />
|
|
  <b>REG_YMM_AVX512_HI16_FIRST</b>,
|
|
<br />
|
|
  <b>REG_YMM16</b> = REG_YMM_AVX512_HI16_FIRST,
|
|
<br />
|
|
  <b>REG_YMM17</b>,
|
|
<br />
|
|
  <b>REG_YMM18</b>,
|
|
<br />
|
|
  <b>REG_YMM19</b>,
|
|
<br />
|
|
  <b>REG_YMM20</b>,
|
|
<br />
|
|
  <b>REG_YMM21</b>,
|
|
<br />
|
|
  <b>REG_YMM22</b>,
|
|
<br />
|
|
  <b>REG_YMM23</b>,
|
|
<br />
|
|
  <b>REG_YMM24</b>,
|
|
<br />
|
|
  <b>REG_YMM25</b>,
|
|
<br />
|
|
  <b>REG_YMM26</b>,
|
|
<br />
|
|
  <b>REG_YMM27</b>,
|
|
<br />
|
|
  <b>REG_YMM28</b>,
|
|
<br />
|
|
  <b>REG_YMM29</b>,
|
|
<br />
|
|
  <b>REG_YMM30</b>,
|
|
<br />
|
|
  <b>REG_YMM31</b>,
|
|
<br />
|
|
  <b>REG_YMM_AVX512_HI16_LAST</b> = REG_YMM31,
|
|
<br />
|
|
  <b>REG_YMM_AVX512_LAST</b> = REG_YMM_AVX512_HI16_LAST,
|
|
<br />
|
|
  <b>REG_YMM_LAST</b> = REG_YMM_AVX512_LAST,
|
|
<br />
|
|
  <b>REG_ZMM_BASE</b>,
|
|
<br />
|
|
  <b>REG_ZMM0</b> = REG_ZMM_BASE,
|
|
<br />
|
|
  <b>REG_ZMM1</b>,
|
|
<br />
|
|
  <b>REG_ZMM2</b>,
|
|
<br />
|
|
  <b>REG_ZMM3</b>,
|
|
<br />
|
|
  <b>REG_ZMM4</b>,
|
|
<br />
|
|
  <b>REG_ZMM5</b>,
|
|
<br />
|
|
  <b>REG_ZMM6</b>,
|
|
<br />
|
|
  <b>REG_ZMM7</b>,
|
|
<br />
|
|
  <b>REG_ZMM8</b>,
|
|
<br />
|
|
  <b>REG_ZMM9</b>,
|
|
<br />
|
|
  <b>REG_ZMM10</b>,
|
|
<br />
|
|
  <b>REG_ZMM11</b>,
|
|
<br />
|
|
  <b>REG_ZMM12</b>,
|
|
<br />
|
|
  <b>REG_ZMM13</b>,
|
|
<br />
|
|
  <b>REG_ZMM14</b>,
|
|
<br />
|
|
  <b>REG_ZMM15</b>,
|
|
<br />
|
|
  <b>REG_ZMM_AVX512_SPLIT_LAST</b> = REG_ZMM15,
|
|
<br />
|
|
  <b>REG_ZMM_AVX512_HI16_FIRST</b>,
|
|
<br />
|
|
  <b>REG_ZMM16</b> = REG_ZMM_AVX512_HI16_FIRST,
|
|
<br />
|
|
  <b>REG_ZMM17</b>,
|
|
<br />
|
|
  <b>REG_ZMM18</b>,
|
|
<br />
|
|
  <b>REG_ZMM19</b>,
|
|
<br />
|
|
  <b>REG_ZMM20</b>,
|
|
<br />
|
|
  <b>REG_ZMM21</b>,
|
|
<br />
|
|
  <b>REG_ZMM22</b>,
|
|
<br />
|
|
  <b>REG_ZMM23</b>,
|
|
<br />
|
|
  <b>REG_ZMM24</b>,
|
|
<br />
|
|
  <b>REG_ZMM25</b>,
|
|
<br />
|
|
  <b>REG_ZMM26</b>,
|
|
<br />
|
|
  <b>REG_ZMM27</b>,
|
|
<br />
|
|
  <b>REG_ZMM28</b>,
|
|
<br />
|
|
  <b>REG_ZMM29</b>,
|
|
<br />
|
|
  <b>REG_ZMM30</b>,
|
|
<br />
|
|
  <b>REG_ZMM31</b>,
|
|
<br />
|
|
  <b>REG_ZMM_AVX512_HI16_LAST</b> = REG_ZMM31,
|
|
<br />
|
|
  <b>REG_ZMM_AVX512_LAST</b> = REG_ZMM_AVX512_HI16_LAST,
|
|
<br />
|
|
  <b>REG_ZMM_LAST</b> = REG_ZMM_AVX512_LAST,
|
|
<br />
|
|
  <b>REG_K_BASE</b>,
|
|
<br />
|
|
  <b>REG_K0</b> = REG_K_BASE,
|
|
<br />
|
|
  <b>REG_IMPLICIT_FULL_MASK</b> = REG_K0,
|
|
<br />
|
|
  <b>REG_K1</b>,
|
|
<br />
|
|
  <b>REG_K2</b>,
|
|
<br />
|
|
  <b>REG_K3</b>,
|
|
<br />
|
|
  <b>REG_K4</b>,
|
|
<br />
|
|
  <b>REG_K5</b>,
|
|
<br />
|
|
  <b>REG_K6</b>,
|
|
<br />
|
|
  <b>REG_K7</b>,
|
|
<br />
|
|
  <b>REG_K_LAST</b> = REG_K7,
|
|
<br />
|
|
  <b>REG_MXCSR</b>,
|
|
<br />
|
|
  <b>REG_MXCSRMASK</b>,
|
|
<br />
|
|
  <b>REG_ORIG_RAX</b>,
|
|
<br />
|
|
  <b>REG_ORIG_GAX</b> = REG_ORIG_RAX,
|
|
<br />
|
|
  <b>REG_FPST_BASE</b>,
|
|
<br />
|
|
  <b>REG_FPSTATUS_BASE</b> = REG_FPST_BASE,
|
|
<br />
|
|
  <b>REG_FPCW</b> = REG_FPSTATUS_BASE,
|
|
<br />
|
|
  <b>REG_FPSW</b>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaac92bf2494f7114c40cbbdff3d4b3071d">LEVEL_BASE::REG_FPTAG</a>,
|
|
<br />
|
|
  <b>REG_FPIP_OFF</b>,
|
|
<br />
|
|
  <b>REG_FPIP_SEL</b>,
|
|
<br />
|
|
  <b>REG_FPOPCODE</b>,
|
|
<br />
|
|
  <b>REG_FPDP_OFF</b>,
|
|
<br />
|
|
  <b>REG_FPDP_SEL</b>,
|
|
<br />
|
|
  <b>REG_FPSTATUS_LAST</b> = REG_FPDP_SEL,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa816e3365404549bcab2e4d0ba9625225">LEVEL_BASE::REG_FPTAG_FULL</a>,
|
|
<br />
|
|
  <b>REG_ST_BASE</b>,
|
|
<br />
|
|
  <b>REG_ST0</b> = REG_ST_BASE,
|
|
<br />
|
|
  <b>REG_ST1</b>,
|
|
<br />
|
|
  <b>REG_ST2</b>,
|
|
<br />
|
|
  <b>REG_ST3</b>,
|
|
<br />
|
|
  <b>REG_ST4</b>,
|
|
<br />
|
|
  <b>REG_ST5</b>,
|
|
<br />
|
|
  <b>REG_ST6</b>,
|
|
<br />
|
|
  <b>REG_ST7</b>,
|
|
<br />
|
|
  <b>REG_ST_LAST</b> = REG_ST7,
|
|
<br />
|
|
  <b>REG_FPST_LAST</b> = REG_ST_LAST,
|
|
<br />
|
|
  <b>REG_DR_BASE</b>,
|
|
<br />
|
|
  <b>REG_DR0</b> = REG_DR_BASE,
|
|
<br />
|
|
  <b>REG_DR1</b>,
|
|
<br />
|
|
  <b>REG_DR2</b>,
|
|
<br />
|
|
  <b>REG_DR3</b>,
|
|
<br />
|
|
  <b>REG_DR4</b>,
|
|
<br />
|
|
  <b>REG_DR5</b>,
|
|
<br />
|
|
  <b>REG_DR6</b>,
|
|
<br />
|
|
  <b>REG_DR7</b>,
|
|
<br />
|
|
  <b>REG_DR_LAST</b> = REG_DR7,
|
|
<br />
|
|
  <b>REG_CR_BASE</b>,
|
|
<br />
|
|
  <b>REG_CR0</b> = REG_CR_BASE,
|
|
<br />
|
|
  <b>REG_CR1</b>,
|
|
<br />
|
|
  <b>REG_CR2</b>,
|
|
<br />
|
|
  <b>REG_CR3</b>,
|
|
<br />
|
|
  <b>REG_CR4</b>,
|
|
<br />
|
|
  <b>REG_CR_LAST</b> = REG_CR4,
|
|
<br />
|
|
  <b>REG_TSSR</b>,
|
|
<br />
|
|
  <b>REG_LDTR</b>,
|
|
<br />
|
|
  <b>REG_TR_BASE</b>,
|
|
<br />
|
|
  <b>REG_TR</b> = REG_TR_BASE,
|
|
<br />
|
|
  <b>REG_TR3</b>,
|
|
<br />
|
|
  <b>REG_TR4</b>,
|
|
<br />
|
|
  <b>REG_TR5</b>,
|
|
<br />
|
|
  <b>REG_TR6</b>,
|
|
<br />
|
|
  <b>REG_TR7</b>,
|
|
<br />
|
|
  <b>REG_TR_LAST</b> = REG_TR7,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa0ed94219044b489ef7ec00b9aee1f997">LEVEL_BASE::REG_SEG_GS_BASE</a> = REG_TOOL_BASE,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaae06493e866ba2fcfe67f5cee7c9e0262">LEVEL_BASE::REG_SEG_FS_BASE</a>,
|
|
<br />
|
|
  <b>REG_INST_BASE</b>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaabffe023180c3055f8e337d0ee253ad44">LEVEL_BASE::REG_INST_SCRATCH_BASE</a> = REG_INST_BASE,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa0c74b67cf274f09260e3487e3e50fc8d">LEVEL_BASE::REG_INST_G0</a> = REG_INST_SCRATCH_BASE,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa7f36e2387bc4a1829178069800541ef9">LEVEL_BASE::REG_INST_G1</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaae4ea8dfff667c04c7fc1dc31ca58034c">LEVEL_BASE::REG_INST_G2</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa38ce8959771849b6d19666704cbde709">LEVEL_BASE::REG_INST_G3</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaf864b78729c325072880aaca91c4fc95">LEVEL_BASE::REG_INST_G4</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa0bf3c225420ed8b7efb4bdcf9cc96b7a">LEVEL_BASE::REG_INST_G5</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa7a495b5a550802bbfc2fe607347fe215">LEVEL_BASE::REG_INST_G6</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa9c5b06055777d4d2e9aec17bd12c23c8">LEVEL_BASE::REG_INST_G7</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa396783de27aaf9ad09d32b856f2a8470">LEVEL_BASE::REG_INST_G8</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa725ffa82752261f7e6d02f61f823e947">LEVEL_BASE::REG_INST_G9</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa95bd2a7996373994211f4abdca6fddd0">LEVEL_BASE::REG_INST_G10</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa6627b33852420083e7e1bf92ff9b0623">LEVEL_BASE::REG_INST_G11</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaf04944e9076e9486a2b3b041c53febac">LEVEL_BASE::REG_INST_G12</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaac345a6a2a3b09a8c3d904d1449ab1bea">LEVEL_BASE::REG_INST_G13</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa109cec4ef8f3a7cef69cd715f570aee7">LEVEL_BASE::REG_INST_G14</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa4cba02ec1f94e2108075f73542c61437">LEVEL_BASE::REG_INST_G15</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaae9c516698c3454b8affdd500f632693e">LEVEL_BASE::REG_INST_G16</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa2733a20abd14c288797c29496caf54c0">LEVEL_BASE::REG_INST_G17</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaf96e4e4238b1cdaa2e2698e79167827d">LEVEL_BASE::REG_INST_G18</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa190b77795e4b9f2deffb1b71f6b5e1db">LEVEL_BASE::REG_INST_G19</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa59acca29ce8ae55d494b25143e34f9d9">LEVEL_BASE::REG_INST_G20</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaf690aa538da5a908981ac893e1f4e161">LEVEL_BASE::REG_INST_G21</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa93e9ba0aefceb84674a5925b95419b81">LEVEL_BASE::REG_INST_G22</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaa59446ebc8910a87f43a2962d9346b47">LEVEL_BASE::REG_INST_G23</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaadfbfc0159ae81ed87d59b3adb70cab38">LEVEL_BASE::REG_INST_G24</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa6be65a34d0304c3e9825ae7cfbb7be5e">LEVEL_BASE::REG_INST_G25</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaa307f73d50cf2fdc59b71110ab6dfedf">LEVEL_BASE::REG_INST_G26</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa711d70383ecc473d6ac60e1307c405f3">LEVEL_BASE::REG_INST_G27</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa26c3d0b42cd2b43370836043e51d44db">LEVEL_BASE::REG_INST_G28</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa9d258abf4f7fe9fa6f39f0e5607d31c4">LEVEL_BASE::REG_INST_G29</a>,
|
|
<br />
|
|
  <b>REG_INST_TOOL_FIRST</b> = REG_INST_G0,
|
|
<br />
|
|
  <b>REG_INST_TOOL_LAST</b> = REG_INST_G29,
|
|
<br />
|
|
  <b>REG_BUF_BASE0</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE1</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE2</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE3</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE4</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE5</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE6</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE7</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE8</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE9</b>,
|
|
<br />
|
|
  <b>REG_BUF_BASE_LAST</b> = REG_BUF_BASE9,
|
|
<br />
|
|
  <b>REG_BUF_END0</b>,
|
|
<br />
|
|
  <b>REG_BUF_END1</b>,
|
|
<br />
|
|
  <b>REG_BUF_END2</b>,
|
|
<br />
|
|
  <b>REG_BUF_END3</b>,
|
|
<br />
|
|
  <b>REG_BUF_END4</b>,
|
|
<br />
|
|
  <b>REG_BUF_END5</b>,
|
|
<br />
|
|
  <b>REG_BUF_END6</b>,
|
|
<br />
|
|
  <b>REG_BUF_END7</b>,
|
|
<br />
|
|
  <b>REG_BUF_END8</b>,
|
|
<br />
|
|
  <b>REG_BUF_END9</b>,
|
|
<br />
|
|
  <b>REG_BUF_ENDLAST</b> = REG_BUF_END9,
|
|
<br />
|
|
  <b>REG_BUF_LAST</b> = REG_BUF_ENDLAST,
|
|
<br />
|
|
  <b>REG_INST_SCRATCH_LAST</b> = REG_BUF_LAST,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa680a1bfdef427ad22d9c06862ca8be39">LEVEL_BASE::REG_INST_G0D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa4384a63975e93079edbdf6f914c91732">LEVEL_BASE::REG_INST_G1D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaad3fec62dc380397b4cf41a514a3f6381">LEVEL_BASE::REG_INST_G2D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaab42714aeb5c33f414c6860fb1701ceb4">LEVEL_BASE::REG_INST_G3D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa9185ce9d3f47355f393f54e0c8268bf1">LEVEL_BASE::REG_INST_G4D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa5e3f60762c1e72653f9381e0a0250553">LEVEL_BASE::REG_INST_G5D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa8e45920c2fe6bec8ad40a7fbfc0c90ff">LEVEL_BASE::REG_INST_G6D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa7ecb1bf582da4d3336532c9774a50d58">LEVEL_BASE::REG_INST_G7D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa443b750b1dfcd746b22dc7c9bc1f3fb4">LEVEL_BASE::REG_INST_G8D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa6531c29aa82e400fe348f82ea3a3579b">LEVEL_BASE::REG_INST_G9D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa6569df93fe3d531d2ecf6ebab4d135f1">LEVEL_BASE::REG_INST_G10D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa4b6125afbf609af5e6627b5b491e6b5a">LEVEL_BASE::REG_INST_G11D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaab5eeb574296c5bb42155de0f59e4c21d">LEVEL_BASE::REG_INST_G12D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa367f555821f763a6ae6803d12c83a6c4">LEVEL_BASE::REG_INST_G13D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa1b2a30adcbad87161f6b6047d61bfa75">LEVEL_BASE::REG_INST_G14D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa49d95be2d2d1994558c6d9936ecbdd96">LEVEL_BASE::REG_INST_G15D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaa5bf9e9157c37c2487c5869abb1418db">LEVEL_BASE::REG_INST_G16D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa99e34eca2b534c4034912582b293892a">LEVEL_BASE::REG_INST_G17D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaacbb74d7b0dffce4df7fb6760bd6a2395">LEVEL_BASE::REG_INST_G18D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa401cb474591a1dae4b42c26b0877d0fe">LEVEL_BASE::REG_INST_G19D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa9aed97ea0abb130117bc059561ef247f">LEVEL_BASE::REG_INST_G20D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaf1721d92e36953871368eb3fa0b5e8de">LEVEL_BASE::REG_INST_G21D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa3d4c6db543fcaa093b859bcdaa85bd7d">LEVEL_BASE::REG_INST_G22D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaaa0b8ebb1eda36a8c3dce32deea7a6281">LEVEL_BASE::REG_INST_G23D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaab810110c5b5523798315394e3fb62782">LEVEL_BASE::REG_INST_G24D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa420162b67835d1eb2fd238c9abc824eb">LEVEL_BASE::REG_INST_G25D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa243b6406845f5cf683cac4277f6b060d">LEVEL_BASE::REG_INST_G26D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa52245952c7a0a7145b74d4c5bd63af9b">LEVEL_BASE::REG_INST_G27D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa2826c67e5eb083839961dab33b3d488d">LEVEL_BASE::REG_INST_G28D</a>,
|
|
<br />
|
|
  <a class="el" href="group__REG__CPU__IA32.html#gga0f57fb50e80d686a588694f73046f2aaa2e62148d88ea152ca22bc07960775bb5">LEVEL_BASE::REG_INST_G29D</a>,
|
|
<br />
|
|
  <b>REG_TOOL_LAST</b> = REG_INST_G29D,
|
|
<br />
|
|
  <b>REG_LAST</b>
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="separator:ga0f57fb50e80d686a588694f73046f2aa"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ga9df40496bf2f29c7a2c5980be42dcb78"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga9df40496bf2f29c7a2c5980be42dcb78">LEVEL_BASE::REG_ACCESS</a> { <br />
|
|
  <b>REG_ACCESS_READ</b>,
|
|
<br />
|
|
  <b>REG_ACCESS_WRITE</b>,
|
|
<br />
|
|
  <b>REG_ACCESS_OVERWRITE</b>
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="separator:ga9df40496bf2f29c7a2c5980be42dcb78"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:gacc81a8433e2f250fc341758e21611be6"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gacc81a8433e2f250fc341758e21611be6">LEVEL_BASE::REGNAME</a> { <b>REGNAME_LAST</b>
|
|
}</td></tr>
|
|
<tr class="separator:gacc81a8433e2f250fc341758e21611be6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ga92c4a19fb1078e9a7d9a54b42d3118e7"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga92c4a19fb1078e9a7d9a54b42d3118e7">LEVEL_BASE::REGWIDTH</a> { <br />
|
|
  <b>REGWIDTH_8</b> =0,
|
|
<br />
|
|
  <b>REGWIDTH_16</b> =1,
|
|
<br />
|
|
  <b>REGWIDTH_32</b> =2,
|
|
<br />
|
|
  <b>REGWIDTH_64</b> =3,
|
|
<br />
|
|
  <b>REGWIDTH_80</b>,
|
|
<br />
|
|
  <b>REGWIDTH_128</b>,
|
|
<br />
|
|
  <b>REGWIDTH_256</b>,
|
|
<br />
|
|
  <b>REGWIDTH_512</b>,
|
|
<br />
|
|
  <b>REGWIDTH_INVALID</b>,
|
|
<br />
|
|
  <b>REGWIDTH_NATIVE</b> =REGWIDTH_64
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="separator:ga92c4a19fb1078e9a7d9a54b42d3118e7"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ga99beb1f4b1dd69c64e5aff9591f7eb24"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga99beb1f4b1dd69c64e5aff9591f7eb24">LEVEL_BASE::REG_CLASS</a> { <br />
|
|
  <b>REG_CLASS_NONE</b> = 0,
|
|
<br />
|
|
  <b>REG_CLASS_PSEUDO</b>,
|
|
<br />
|
|
  <b>REG_CLASS_GR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_GRU8</b>,
|
|
<br />
|
|
  <b>REG_CLASS_GRL8</b>,
|
|
<br />
|
|
  <b>REG_CLASS_GRH16</b>,
|
|
<br />
|
|
  <b>REG_CLASS_GRH32</b>,
|
|
<br />
|
|
  <b>REG_CLASS_SEG</b>,
|
|
<br />
|
|
  <b>REG_CLASS_MM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_XMM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_YMM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_ZMM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_K</b>,
|
|
<br />
|
|
  <b>REG_CLASS_FPST</b>,
|
|
<br />
|
|
  <b>REG_CLASS_ST</b>,
|
|
<br />
|
|
  <b>REG_CLASS_CR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_DR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_TR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_FLAGS</b>,
|
|
<br />
|
|
  <b>REG_CLASS_FLAGS16</b>,
|
|
<br />
|
|
  <b>REG_CLASS_FLAGS32</b>,
|
|
<br />
|
|
  <b>REG_CLASS_STATUS_FLAGS</b>,
|
|
<br />
|
|
  <b>REG_CLASS_DFLAG</b>,
|
|
<br />
|
|
  <b>REG_CLASS_MXCSR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_MXCSRMASK</b>,
|
|
<br />
|
|
  <b>REG_CLASS_IP</b>,
|
|
<br />
|
|
  <b>REG_CLASS_IP16</b>,
|
|
<br />
|
|
  <b>REG_CLASS_IP32</b>,
|
|
<br />
|
|
  <b>REG_CLASS_ARCH</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_GR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_GRU8</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_GRL8</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_GRH16</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_GRH32</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_XMM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_YMM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_ZMM</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_K</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_MXCSR</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_FLAGS</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_STATUS_FLAGS</b>,
|
|
<br />
|
|
  <b>REG_CLASS_PIN_DFLAG</b>
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="separator:ga99beb1f4b1dd69c64e5aff9591f7eb24"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:gac3fde05e1d7397e8e525ac3f60872406"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gac3fde05e1d7397e8e525ac3f60872406">LEVEL_BASE::REG_SUBCLASS</a> { <br />
|
|
  <b>REG_SUBCLASS_NONE</b> = 0,
|
|
<br />
|
|
  <b>REG_SUBCLASS_REX</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_FULL_STACKPTR</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_PIN_FULL_STACKPTR</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_PIN_TMP</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_PIN_INST_GR</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_PIN_INST_GR_H32</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_PIN_INST_BUF</b>,
|
|
<br />
|
|
  <b>REG_SUBCLASS_PIN_INST_COND</b>
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="separator:gac3fde05e1d7397e8e525ac3f60872406"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ga2b1cf2faaa7fa5341a7b8ea382a0fadd"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga2b1cf2faaa7fa5341a7b8ea382a0fadd">LEVEL_BASE::REG_ALLOC_TYPE</a> { <br />
|
|
  <b>REG_ALLOC_NONE</b> = 0,
|
|
<br />
|
|
  <b>REG_ALLOC_PART</b>,
|
|
<br />
|
|
  <b>REG_ALLOC_ANY_GR</b>,
|
|
<br />
|
|
  <b>REG_ALLOC_IDENT</b>,
|
|
<br />
|
|
  <b>REG_ALLOC_CR</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_DR</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_TR</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_ST</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_MM</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_XMM</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_YMM</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_ZMM</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_K</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_SEG</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_STACK_PTR</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_X87</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_FLAGS</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_STATUS_FLAGS</b> = REG_ALLOC_IDENT,
|
|
<br />
|
|
  <b>REG_ALLOC_DFLAG</b> = REG_ALLOC_IDENT
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="separator:ga2b1cf2faaa7fa5341a7b8ea382a0fadd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
</table><table class="memberdecls">
|
|
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
|
|
Functions</h2></td></tr>
|
|
<tr class="memitem:gaa06646aa9ba317476807d4c5588400ec"><td class="memItemLeft" align="right" valign="top"><a id="gaa06646aa9ba317476807d4c5588400ec"></a>
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VOID </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::InitRegTables</b> ()</td></tr>
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<tr class="separator:gaa06646aa9ba317476807d4c5588400ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacad5be362797ba8fc511ed7b2243ea56"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gacad5be362797ba8fc511ed7b2243ea56">LEVEL_BASE::REG_is_fr_for_get_context</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gacad5be362797ba8fc511ed7b2243ea56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84e26c54a557be59d9939c89e9fd8ee9"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga84e26c54a557be59d9939c89e9fd8ee9">LEVEL_BASE::REG_is_mxcsr</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga84e26c54a557be59d9939c89e9fd8ee9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c6ce7d36d83ef56793585a413123667"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga3c6ce7d36d83ef56793585a413123667">LEVEL_BASE::REG_is_any_mxcsr</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga3c6ce7d36d83ef56793585a413123667"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad43d44806bd22c39078899f17a81b8b6"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gad43d44806bd22c39078899f17a81b8b6">LEVEL_BASE::REG_is_mm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gad43d44806bd22c39078899f17a81b8b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0ddaf16b2320ffcd0e41801906c4b04"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gad0ddaf16b2320ffcd0e41801906c4b04">LEVEL_BASE::REG_is_xmm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gad0ddaf16b2320ffcd0e41801906c4b04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3dc27099d5bb520216a50bd00b1db60"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gae3dc27099d5bb520216a50bd00b1db60">LEVEL_BASE::REG_is_ymm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gae3dc27099d5bb520216a50bd00b1db60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc16a50e8a5c6a91748c8d1f35d21440"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gabc16a50e8a5c6a91748c8d1f35d21440">LEVEL_BASE::REG_is_zmm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gabc16a50e8a5c6a91748c8d1f35d21440"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8efc75a83fc1476dbe69fb41019cb195"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga8efc75a83fc1476dbe69fb41019cb195">LEVEL_BASE::REG_is_xmm_ymm_zmm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga8efc75a83fc1476dbe69fb41019cb195"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8d1dddc8e3ecb847f01fe5fc5bed700"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gab8d1dddc8e3ecb847f01fe5fc5bed700">LEVEL_BASE::REG_is_any_vector_reg</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gab8d1dddc8e3ecb847f01fe5fc5bed700"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20f36aedce3f9950a8ce857de96fb869"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga20f36aedce3f9950a8ce857de96fb869">LEVEL_BASE::REG_is_k_mask</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga20f36aedce3f9950a8ce857de96fb869"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf4160e5284a5e993bdc87281ea1cd2e"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gadf4160e5284a5e993bdc87281ea1cd2e">LEVEL_BASE::REG_is_any_mask</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gadf4160e5284a5e993bdc87281ea1cd2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96237638ef307496aef198c3c64294eb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga96237638ef307496aef198c3c64294eb">LEVEL_BASE::REG_corresponding_ymm_reg</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga96237638ef307496aef198c3c64294eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3996eaec372864e8619522b28b20af5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gac3996eaec372864e8619522b28b20af5">LEVEL_BASE::REG_corresponding_zmm_reg</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gac3996eaec372864e8619522b28b20af5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5ce416e2c302776771a62e78b3bff3e"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gad5ce416e2c302776771a62e78b3bff3e">LEVEL_BASE::REG_is_st</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gad5ce416e2c302776771a62e78b3bff3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab69f78cae1b602686561a849b9d21eb9"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gab69f78cae1b602686561a849b9d21eb9">LEVEL_BASE::REG_is_machine</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gab69f78cae1b602686561a849b9d21eb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga107fe336a80ef8e0cdefeedd2af83b6e"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga107fe336a80ef8e0cdefeedd2af83b6e">LEVEL_BASE::REG_is_application</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga107fe336a80ef8e0cdefeedd2af83b6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6b2fc14f383b093a27097259305dfdc"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gae6b2fc14f383b093a27097259305dfdc">LEVEL_BASE::REG_is_pin</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gae6b2fc14f383b093a27097259305dfdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e292f4b7937a81fb41b5465dc1c467b"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga1e292f4b7937a81fb41b5465dc1c467b">LEVEL_BASE::REG_is_subclass_none</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga1e292f4b7937a81fb41b5465dc1c467b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4649f4bf511de60a8c38744f2b30d229"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga4649f4bf511de60a8c38744f2b30d229">LEVEL_BASE::REG_is_pin_gpr</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga4649f4bf511de60a8c38744f2b30d229"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c950bcf48a41d323154dbf13aa6f08f"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga5c950bcf48a41d323154dbf13aa6f08f">LEVEL_BASE::REG_is_seg_base</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga5c950bcf48a41d323154dbf13aa6f08f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0293eb62c56e47c0864c0a768e9ac0e"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gaa0293eb62c56e47c0864c0a768e9ac0e">LEVEL_BASE::REG_is_gs_or_fs</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gaa0293eb62c56e47c0864c0a768e9ac0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42d43c5a7062cb843a8914d4b20c003a"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga42d43c5a7062cb843a8914d4b20c003a">LEVEL_BASE::REG_valid_for_iarg_reg_value</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga42d43c5a7062cb843a8914d4b20c003a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12f19d16124b7d75f776cf03a7fb9b65"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga12f19d16124b7d75f776cf03a7fb9b65">LEVEL_BASE::REG_is_pin_xmm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga12f19d16124b7d75f776cf03a7fb9b65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37942a62b7634a2de68f0eaaf4d8f3ff"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga37942a62b7634a2de68f0eaaf4d8f3ff">LEVEL_BASE::REG_is_pin_ymm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga37942a62b7634a2de68f0eaaf4d8f3ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46fdc74702dfffd8458a1a7264deffb2"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga46fdc74702dfffd8458a1a7264deffb2">LEVEL_BASE::REG_is_pin_zmm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga46fdc74702dfffd8458a1a7264deffb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabccd8e7ec839504ba6899c56c5ed7d1"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gaabccd8e7ec839504ba6899c56c5ed7d1">LEVEL_BASE::REG_is_pin_xmm_ymm_zmm</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gaabccd8e7ec839504ba6899c56c5ed7d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ff7dcfeb1fb8e6b0795a3baff67b4f2"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga3ff7dcfeb1fb8e6b0795a3baff67b4f2">LEVEL_BASE::REG_is_pin_k_mask</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga3ff7dcfeb1fb8e6b0795a3baff67b4f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e0a8031d762afdf3216ab5542350a7b"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga9e0a8031d762afdf3216ab5542350a7b">LEVEL_BASE::REG_is_avx512_hi16_xmm</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> xmm)</td></tr>
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<tr class="separator:ga9e0a8031d762afdf3216ab5542350a7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd3d888174d3abb6d37bcd4f095fbe40"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gabd3d888174d3abb6d37bcd4f095fbe40">LEVEL_BASE::REG_is_avx512_hi16_ymm</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> ymm)</td></tr>
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<tr class="separator:gabd3d888174d3abb6d37bcd4f095fbe40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54d7b385d35f4771ba1222e8a5ca93a0"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga54d7b385d35f4771ba1222e8a5ca93a0">LEVEL_BASE::REG_is_gr_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga54d7b385d35f4771ba1222e8a5ca93a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c875987af64889967b8fcdce47cc0aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga0c875987af64889967b8fcdce47cc0aa">LEVEL_BASE::REG_AppFlags</a> ()</td></tr>
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<tr class="separator:ga0c875987af64889967b8fcdce47cc0aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga087cd367780291f3f0157b8a12ae4b3c"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga087cd367780291f3f0157b8a12ae4b3c">LEVEL_BASE::REG_is_flags</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga087cd367780291f3f0157b8a12ae4b3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90646665d884a896b3ad112712a13c2c"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga90646665d884a896b3ad112712a13c2c">LEVEL_BASE::REG_is_pin_flags</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga90646665d884a896b3ad112712a13c2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf430d3bb8a23fa507a8789eae73bc995"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gaf430d3bb8a23fa507a8789eae73bc995">LEVEL_BASE::REG_is_status_flags</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gaf430d3bb8a23fa507a8789eae73bc995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c3dc7ae6ba3baedc1c5cfc4a77d70ec"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga7c3dc7ae6ba3baedc1c5cfc4a77d70ec">LEVEL_BASE::REG_is_pin_status_flags</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga7c3dc7ae6ba3baedc1c5cfc4a77d70ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d2f4f32ab0759aee693e46f80f84c6b"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga1d2f4f32ab0759aee693e46f80f84c6b">LEVEL_BASE::REG_is_df_flag</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga1d2f4f32ab0759aee693e46f80f84c6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1871b77d94620cc6efef010ccce53d1f"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga1871b77d94620cc6efef010ccce53d1f">LEVEL_BASE::REG_is_pin_df_flag</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga1871b77d94620cc6efef010ccce53d1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8f8fcd44f901c4ccba9d942ac8daf61"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gae8f8fcd44f901c4ccba9d942ac8daf61">LEVEL_BASE::REG_is_flags_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gae8f8fcd44f901c4ccba9d942ac8daf61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga634c2b5fdd67a1a0df7fc1796279256a"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga634c2b5fdd67a1a0df7fc1796279256a">LEVEL_BASE::REG_is_flags_any_size_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga634c2b5fdd67a1a0df7fc1796279256a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3ee3646600609b04c8e7594d0373965"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gab3ee3646600609b04c8e7594d0373965">LEVEL_BASE::REG_is_status_flags_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gab3ee3646600609b04c8e7594d0373965"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf7bafd739169dd8c707f0657c4659a2"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gaaf7bafd739169dd8c707f0657c4659a2">LEVEL_BASE::REG_is_app_status_flags_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gaaf7bafd739169dd8c707f0657c4659a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8470c1e882b5abe9554f46cd2b546a76"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga8470c1e882b5abe9554f46cd2b546a76">LEVEL_BASE::REG_is_df_flag_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga8470c1e882b5abe9554f46cd2b546a76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bca059473be021381d5445e59a679d1"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga5bca059473be021381d5445e59a679d1">LEVEL_BASE::REG_is_app_df_flag_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga5bca059473be021381d5445e59a679d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga084c8aa78ffa2e723454ac723d163af8"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga084c8aa78ffa2e723454ac723d163af8">LEVEL_BASE::REG_is_any_flags_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga084c8aa78ffa2e723454ac723d163af8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b65cba2f06839c5950a464deccab0d8"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga4b65cba2f06839c5950a464deccab0d8">LEVEL_BASE::REG_is_any_pin_flags</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga4b65cba2f06839c5950a464deccab0d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50827a2b7e6d17ab3aa6ed0360c0855a"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga50827a2b7e6d17ab3aa6ed0360c0855a">LEVEL_BASE::REG_is_any_app_flags</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga50827a2b7e6d17ab3aa6ed0360c0855a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cdd646a3e668c22d46a8d71fafd15a4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga0cdd646a3e668c22d46a8d71fafd15a4">LEVEL_BASE::REG_get_status_flags_reg_of_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga0cdd646a3e668c22d46a8d71fafd15a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab16386559e6315c56e2f8673304c9db2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gab16386559e6315c56e2f8673304c9db2">LEVEL_BASE::REG_get_df_flag_reg_of_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gab16386559e6315c56e2f8673304c9db2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7683ee760514ceb26ba258899d86c68"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gab7683ee760514ceb26ba258899d86c68">LEVEL_BASE::REG_get_full_flags_reg_of_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gab7683ee760514ceb26ba258899d86c68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab815b1ed5561a011f918bcb0d90af257"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gab815b1ed5561a011f918bcb0d90af257">LEVEL_BASE::REG_is_stackptr_type</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gab815b1ed5561a011f918bcb0d90af257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga349ef4d923d81de6d8d5c48e4bc272e0"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga349ef4d923d81de6d8d5c48e4bc272e0">LEVEL_BASE::REG_is_representative_reg</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga349ef4d923d81de6d8d5c48e4bc272e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67014bc28ef11cffdd77303e65fae0ec"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga67014bc28ef11cffdd77303e65fae0ec">LEVEL_BASE::REG_is_pin_inst</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga67014bc28ef11cffdd77303e65fae0ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e514a3db62e6e091354cd32603e46e1"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga6e514a3db62e6e091354cd32603e46e1">LEVEL_BASE::REG_is_buffer</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga6e514a3db62e6e091354cd32603e46e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e8881e1755de23c4340c8cf8d1040b7"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga0e8881e1755de23c4340c8cf8d1040b7">LEVEL_BASE::REG_is_inst_scratch</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga0e8881e1755de23c4340c8cf8d1040b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e0a17685f3326079eb42bedb129d0a0"><td class="memItemLeft" align="right" valign="top">ADDRINT </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga4e0a17685f3326079eb42bedb129d0a0">LEVEL_BASE::REG_regSubClassBitMapTable</a> ()</td></tr>
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<tr class="separator:ga4e0a17685f3326079eb42bedb129d0a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb5d2041bfaef6560e7fdd2094d0d9df"><td class="memItemLeft" align="right" valign="top">ADDRINT </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gacb5d2041bfaef6560e7fdd2094d0d9df">LEVEL_BASE::REG_regDefTable</a> ()</td></tr>
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<tr class="separator:gacb5d2041bfaef6560e7fdd2094d0d9df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae43bac2e4d7245a1f6e911748ae6c3e5"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gae43bac2e4d7245a1f6e911748ae6c3e5">LEVEL_BASE::REG_is_pin_tmp</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gae43bac2e4d7245a1f6e911748ae6c3e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28676b9554c951c74a2f8b720a4b7ab2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga28676b9554c951c74a2f8b720a4b7ab2">LEVEL_BASE::REG_LastSupportedXmm</a> ()</td></tr>
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<tr class="separator:ga28676b9554c951c74a2f8b720a4b7ab2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2681487338ec6a41511bc49dea51849f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga2681487338ec6a41511bc49dea51849f">LEVEL_BASE::REG_LastSupportedYmm</a> ()</td></tr>
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<tr class="separator:ga2681487338ec6a41511bc49dea51849f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37dd352d87e8b1b793a9525f9ed08bda"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga37dd352d87e8b1b793a9525f9ed08bda">LEVEL_BASE::REG_LastSupportedZmm</a> ()</td></tr>
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<tr class="separator:ga37dd352d87e8b1b793a9525f9ed08bda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8744ba41569c7770f4aa41f8e2d0b4e6"><td class="memItemLeft" align="right" valign="top">UINT32 </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga8744ba41569c7770f4aa41f8e2d0b4e6">LEVEL_BASE::REG_Size</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga8744ba41569c7770f4aa41f8e2d0b4e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0838dab8af04897b565593f3d87bee1e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga0838dab8af04897b565593f3d87bee1e">LEVEL_BASE::REG_IdentityCopy</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga0838dab8af04897b565593f3d87bee1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c6504a4bfa4a1007a1f0b792f345091"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga2c6504a4bfa4a1007a1f0b792f345091">LEVEL_BASE::REG_is_Half16</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga2c6504a4bfa4a1007a1f0b792f345091"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86a3431be0730babc838c6fe87ee9c2c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__REG__CPU__IA32.html#ga92c4a19fb1078e9a7d9a54b42d3118e7">REGWIDTH</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga86a3431be0730babc838c6fe87ee9c2c">LEVEL_BASE::REG_Width</a> (<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga86a3431be0730babc838c6fe87ee9c2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7da10abdb51e61b11f791beaa5b2a8e7"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga7da10abdb51e61b11f791beaa5b2a8e7">LEVEL_BASE::REG_is_Half32</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga7da10abdb51e61b11f791beaa5b2a8e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae565098e5f19a2979173e15c823f049d"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gae565098e5f19a2979173e15c823f049d">LEVEL_BASE::REG_is_Lower8</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gae565098e5f19a2979173e15c823f049d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fae2ff2ecca2771b05d976f812241e8"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga6fae2ff2ecca2771b05d976f812241e8">LEVEL_BASE::REG_is_Upper8</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga6fae2ff2ecca2771b05d976f812241e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1123ed2e29dd34f3612e105790f7950"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gaa1123ed2e29dd34f3612e105790f7950">LEVEL_BASE::REG_is_Any8</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:gaa1123ed2e29dd34f3612e105790f7950"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e54ad3a41450c87d324ecac6d6da2ec"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga7e54ad3a41450c87d324ecac6d6da2ec">LEVEL_BASE::REG_is_partialreg</a> (const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> reg)</td></tr>
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<tr class="separator:ga7e54ad3a41450c87d324ecac6d6da2ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ed23b197782e88ec8dcda1efb04c7c3"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga8ed23b197782e88ec8dcda1efb04c7c3">LEVEL_CORE::REGSET_Contains</a> (const <a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset, REG reg)</td></tr>
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<tr class="separator:ga8ed23b197782e88ec8dcda1efb04c7c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d0aca55c4e11785153c4f4bd83328c2"><td class="memItemLeft" align="right" valign="top">VOID </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga7d0aca55c4e11785153c4f4bd83328c2">LEVEL_CORE::REGSET_Insert</a> (<a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset, REG reg)</td></tr>
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<tr class="separator:ga7d0aca55c4e11785153c4f4bd83328c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bc09e7fbd3f8ddad1e47c83c8ca6323"><td class="memItemLeft" align="right" valign="top">VOID </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga9bc09e7fbd3f8ddad1e47c83c8ca6323">LEVEL_CORE::REGSET_Remove</a> (<a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset, REG reg)</td></tr>
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<tr class="separator:ga9bc09e7fbd3f8ddad1e47c83c8ca6323"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8d6bc907483b84a882565de6a5025e6"><td class="memItemLeft" align="right" valign="top">VOID </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gaa8d6bc907483b84a882565de6a5025e6">LEVEL_CORE::REGSET_Clear</a> (<a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset)</td></tr>
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<tr class="separator:gaa8d6bc907483b84a882565de6a5025e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59b1d2e23d3de5edb229047382abfa22"><td class="memItemLeft" align="right" valign="top">VOID </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga59b1d2e23d3de5edb229047382abfa22">LEVEL_CORE::REGSET_AddAll</a> (<a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset)</td></tr>
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<tr class="separator:ga59b1d2e23d3de5edb229047382abfa22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21f89d33c92eb340dd1aaed30c7d6e72"><td class="memItemLeft" align="right" valign="top">REG </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga21f89d33c92eb340dd1aaed30c7d6e72">LEVEL_CORE::REGSET_PopNext</a> (<a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset)</td></tr>
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<tr class="separator:ga21f89d33c92eb340dd1aaed30c7d6e72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5530b1d15830b6e844f86d9d104606b"><td class="memItemLeft" align="right" valign="top">UINT32 </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gac5530b1d15830b6e844f86d9d104606b">LEVEL_CORE::REGSET_PopCount</a> (const <a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset)</td></tr>
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<tr class="separator:gac5530b1d15830b6e844f86d9d104606b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb4df67645a5af50e61c0b2bae9b7f62"><td class="memItemLeft" align="right" valign="top">BOOL </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gacb4df67645a5af50e61c0b2bae9b7f62">LEVEL_CORE::REGSET_PopCountIsZero</a> (const <a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset)</td></tr>
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<tr class="separator:gacb4df67645a5af50e61c0b2bae9b7f62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8cf49d0b0fa523059da94bca3fbf061"><td class="memItemLeft" align="right" valign="top">std::string </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gac8cf49d0b0fa523059da94bca3fbf061">LEVEL_CORE::REGSET_StringShort</a> (const <a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> &regset)</td></tr>
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<tr class="separator:gac8cf49d0b0fa523059da94bca3fbf061"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
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Variables</h2></td></tr>
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<tr class="memitem:gafe098bafa41995c53db7a915ee61922e"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="structLEVEL__BASE_1_1REGDEF__ENTRY.html">REGDEF_ENTRY</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gafe098bafa41995c53db7a915ee61922e">LEVEL_BASE::_regDefTable</a> []</td></tr>
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<tr class="separator:gafe098bafa41995c53db7a915ee61922e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2754c7698eff415b952f32b27adfc225"><td class="memItemLeft" align="right" valign="top"><a id="ga2754c7698eff415b952f32b27adfc225"></a>
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UINT64 </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regClassBitMapTable</b> [REG_LAST]</td></tr>
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<tr class="separator:ga2754c7698eff415b952f32b27adfc225"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001ef3c7362119ef19810c078c76452c"><td class="memItemLeft" align="right" valign="top"><a id="ga001ef3c7362119ef19810c078c76452c"></a>
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UINT64 </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regSubClassBitMapTable</b> [REG_LAST]</td></tr>
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<tr class="separator:ga001ef3c7362119ef19810c078c76452c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac569b3e6307e9d8abf9d691eb6245ed5"><td class="memItemLeft" align="right" valign="top"><a id="gac569b3e6307e9d8abf9d691eb6245ed5"></a>
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UINT32 </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regSpillSizeTable</b> [REG_LAST]</td></tr>
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<tr class="separator:gac569b3e6307e9d8abf9d691eb6245ed5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0b14ea5abda4165f1786045decebfd4"><td class="memItemLeft" align="right" valign="top"><a id="gaf0b14ea5abda4165f1786045decebfd4"></a>
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<a class="el" href="group__REG__CPU__IA32.html#ga92c4a19fb1078e9a7d9a54b42d3118e7">REGWIDTH</a> </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regWidthTable</b> [REG_LAST]</td></tr>
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<tr class="separator:gaf0b14ea5abda4165f1786045decebfd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbec3cb5e6d01dea7d753de2ae9896b4"><td class="memItemLeft" align="right" valign="top"><a id="gacbec3cb5e6d01dea7d753de2ae9896b4"></a>
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<a class="el" href="group__REG__CPU__IA32.html#ga2b1cf2faaa7fa5341a7b8ea382a0fadd">REG_ALLOC_TYPE</a> </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regAllocTypeTable</b> [REG_LAST]</td></tr>
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<tr class="separator:gacbec3cb5e6d01dea7d753de2ae9896b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fb3b5f74c683aa5270806842df9418d"><td class="memItemLeft" align="right" valign="top"><a id="ga4fb3b5f74c683aa5270806842df9418d"></a>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regFullNameTable</b> [REG_LAST]</td></tr>
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<tr class="separator:ga4fb3b5f74c683aa5270806842df9418d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf01cb25c41dd2d375225910a92bd97a"><td class="memItemLeft" align="right" valign="top"><a id="gabf01cb25c41dd2d375225910a92bd97a"></a>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regMachineNameTable</b> [REG_LAST]</td></tr>
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<tr class="separator:gabf01cb25c41dd2d375225910a92bd97a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga245079967fd59759a87fa52ce555701e"><td class="memItemLeft" align="right" valign="top"><a id="ga245079967fd59759a87fa52ce555701e"></a>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regPinNameTable</b> [REG_LAST]</td></tr>
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<tr class="separator:ga245079967fd59759a87fa52ce555701e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36e0b500918a2b869aecf6fbe2467189"><td class="memItemLeft" align="right" valign="top">INT32 </td><td class="memItemRight" valign="bottom"><b>LEVEL_BASE::_regWidthToBitWidth</b> []</td></tr>
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<tr class="separator:ga36e0b500918a2b869aecf6fbe2467189"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafef963c990ff2998f8a62044ca08f5af"><td class="memItemLeft" align="right" valign="top">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gafef963c990ff2998f8a62044ca08f5af">LEVEL_BASE::REGCBIT_APP_ALL</a></td></tr>
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<tr class="separator:gafef963c990ff2998f8a62044ca08f5af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0003ddbd5a31411cef15fe6adc6a1bf4"><td class="memItemLeft" align="right" valign="top">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga0003ddbd5a31411cef15fe6adc6a1bf4">LEVEL_BASE::REGCBIT_PIN_ALL</a></td></tr>
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<tr class="separator:ga0003ddbd5a31411cef15fe6adc6a1bf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dbb64324ec7e6cf592b3a007d637e41"><td class="memItemLeft" align="right" valign="top">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga3dbb64324ec7e6cf592b3a007d637e41">LEVEL_BASE::REGCBIT_ALL_REGS</a> = <a class="el" href="group__REG__CPU__IA32.html#gafef963c990ff2998f8a62044ca08f5af">REGCBIT_APP_ALL</a> | <a class="el" href="group__REG__CPU__IA32.html#ga0003ddbd5a31411cef15fe6adc6a1bf4">REGCBIT_PIN_ALL</a></td></tr>
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<tr class="separator:ga3dbb64324ec7e6cf592b3a007d637e41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga797c94104721a4d10c3375d92f8a977a"><td class="memItemLeft" align="right" valign="top">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga797c94104721a4d10c3375d92f8a977a">LEVEL_BASE::REGCBIT_APP_FLAGS</a></td></tr>
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<tr class="separator:ga797c94104721a4d10c3375d92f8a977a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42d784c0a1e776497acb405282fab148"><td class="memItemLeft" align="right" valign="top">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga42d784c0a1e776497acb405282fab148">LEVEL_BASE::REGCBIT_PIN_FLAGS</a></td></tr>
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<tr class="separator:ga42d784c0a1e776497acb405282fab148"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaec9333a54cfb71118ad03996943c69"><td class="memItemLeft" align="right" valign="top">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gadaec9333a54cfb71118ad03996943c69">LEVEL_BASE::REGCBIT_PARTIAL</a></td></tr>
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<tr class="separator:gadaec9333a54cfb71118ad03996943c69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga656d3616de3d5ae8d26f2b6252c686e3"><td class="memItemLeft" align="right" valign="top">GLOBALCONST REG_SUBCLASS_BITS </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga656d3616de3d5ae8d26f2b6252c686e3">LEVEL_BASE::REGSBIT_PIN_INST_ALL</a></td></tr>
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<tr class="separator:ga656d3616de3d5ae8d26f2b6252c686e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89097de642e222f3d0a0553464e2a584"><td class="memItemLeft" align="right" valign="top">GLOBALCONST REG_SUBCLASS_BITS </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga89097de642e222f3d0a0553464e2a584">LEVEL_BASE::REGSBIT_PIN_SCRATCH_ALL</a></td></tr>
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<tr class="separator:ga89097de642e222f3d0a0553464e2a584"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10bb628d479cc23033c4295ceb9e3823"><td class="memItemLeft" align="right" valign="top">GLOBALCONST REG_SUBCLASS_BITS </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga10bb628d479cc23033c4295ceb9e3823">LEVEL_BASE::REGSBIT_STACKPTR_ALL</a></td></tr>
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<tr class="separator:ga10bb628d479cc23033c4295ceb9e3823"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga106d11b76262e7d9efa0cce801cf8431"><td class="memItemLeft" align="right" valign="top"><a id="ga106d11b76262e7d9efa0cce801cf8431"></a>
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GLOBALCONST REG </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#ga106d11b76262e7d9efa0cce801cf8431">LEVEL_CORE::REG_FirstInRegset</a> = REG_RBASE</td></tr>
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<tr class="separator:ga106d11b76262e7d9efa0cce801cf8431"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3c3f8a822d40e53bc8c599368eb9a44"><td class="memItemLeft" align="right" valign="top">GLOBALCONST REG </td><td class="memItemRight" valign="bottom"><a class="el" href="group__REG__CPU__IA32.html#gac3c3f8a822d40e53bc8c599368eb9a44">LEVEL_CORE::REG_LastInRegset</a> = REG(REG_LAST-1)</td></tr>
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<tr class="separator:gac3c3f8a822d40e53bc8c599368eb9a44"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<dl class="section user"><dt>Availability:</dt><dd><b>Mode:</b> JIT & Probe<br />
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<b>O/S</b>: Linux & Windows<br />
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<b>CPU:</b> IA-32 and Intel(R) 64 architectures<br />
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</dd></dl>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<a id="ga1d2569f4080aa0e3aaa0939d9fe2dcff"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1d2569f4080aa0e3aaa0939d9fe2dcff">◆ </a></span>_REGSBIT</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define _REGSBIT</td>
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<td>(</td>
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<td class="paramtype"> </td>
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<td class="paramname">regSubClass</td><td>)</td>
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<td>   (REG_SUBCLASS_BITS(1) << (regSubClass))</td>
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</table>
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</div><div class="memdoc">
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<p>Bit flag that represents a REG_SUBCLASS value. </p>
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</div>
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</div>
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<h2 class="groupheader">Typedef Documentation</h2>
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<a id="ga5b0b71675518f3b3e967334d71a967d4"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga5b0b71675518f3b3e967334d71a967d4">◆ </a></span>REG_CLASS_BITS</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">typedef UINT64 <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">LEVEL_BASE::REG_CLASS_BITS</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Bit flag that represents a REG_CLASS value. </p>
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</div>
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</div>
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<a id="gae457153aab05650d6845e3553731ee63"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gae457153aab05650d6845e3553731ee63">◆ </a></span>REGSET</h2>
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">typedef class <a class="el" href="classLEVEL__CORE_1_1REGISTER__SET.html">REGISTER_SET</a>< <a class="el" href="group__REG__CPU__IA32.html#ga106d11b76262e7d9efa0cce801cf8431">REG_FirstInRegset</a>, <a class="el" href="group__REG__CPU__IA32.html#gac3c3f8a822d40e53bc8c599368eb9a44">REG_LastInRegset</a> > <a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">LEVEL_CORE::REGSET</a></td>
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</table>
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</div><div class="memdoc">
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<p>A regset type that contains all registers </p>
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</div>
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</div>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<a id="ga0f57fb50e80d686a588694f73046f2aa"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0f57fb50e80d686a588694f73046f2aa">◆ </a></span>REG</h2>
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">LEVEL_BASE::REG</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>The x86 register enum (for both IA-32 and Intel(R) 64 architectures) Note that each register added to this enum, must have a row in the _regDefTable. Note also that the _regDefTable is defined separately for Intel64 and for IA-32. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa03e03ec8e94b01093af076b12f1f3475"></a>REG_RDI </td><td class="fielddoc"><p>rdi </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa337de7ddb5083c8150ecfd66f2320203"></a>REG_GDI </td><td class="fielddoc"><p>edi on a 32 bit machine, rdi on 64 </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaae050d1f0a9ae69dcc0fb2b303f174d0f"></a>REG_RSI </td><td class="fielddoc"><p>rsi </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa710b4b9dba626781fd61d7b08350973f"></a>REG_GSI </td><td class="fielddoc"><p>esi on a 32 bit machine, rsi on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa5baaabaef51b5dd11f040640090e07cb"></a>REG_RBP </td><td class="fielddoc"><p>rbp </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa9ac90dd9547c5c3bb9463924613f2a31"></a>REG_GBP </td><td class="fielddoc"><p>ebp on a 32 bit machine, rbp on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaeec98ba4f5e70e7edaf1a2ff009fb838"></a>REG_RSP </td><td class="fielddoc"><p>rsp </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa2a6956c6a8b5a16cd95bf2f33586e10a"></a>REG_STACK_PTR </td><td class="fielddoc"><p>esp on a 32 bit machine, rsp on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa2b24a77d9d484a3ff972dc177890b079"></a>REG_RBX </td><td class="fielddoc"><p>rbx </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaafcbff5028eb036d075ce6bd9924e3290"></a>REG_GBX </td><td class="fielddoc"><p>ebx on a 32 bit machine, rbx on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa488d066ae5c50671c998593b454f8ebe"></a>REG_RDX </td><td class="fielddoc"><p>rdx </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa3ee773f2e43a1ba875bb1bf483d74538"></a>REG_GDX </td><td class="fielddoc"><p>edx on a 32 bit machine, rdx on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa6197f1f161d556e22841eb7abc34d6d9"></a>REG_RCX </td><td class="fielddoc"><p>rcx </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaadfd07d546c44412017887acbcadd168e"></a>REG_GCX </td><td class="fielddoc"><p>ecx on a 32 bit machine, rcx on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa4f0ecf75bc9d4958868f226cf6f001a5"></a>REG_RAX </td><td class="fielddoc"><p>rax </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaccca04b646ec41c6737d77a2c2369e86"></a>REG_GAX </td><td class="fielddoc"><p>eax on a 32 bit machine, rax on 64 </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaac92bf2494f7114c40cbbdff3d4b3071d"></a>REG_FPTAG </td><td class="fielddoc"><p>Abridged 8-bit version of x87 tag register. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa816e3365404549bcab2e4d0ba9625225"></a>REG_FPTAG_FULL </td><td class="fielddoc"><p>Full 16-bit version of x87 tag register. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa0ed94219044b489ef7ec00b9aee1f997"></a>REG_SEG_GS_BASE </td><td class="fielddoc"><p>Base address for GS segment. </p>
|
|
<p>*** Segment registers (FS/GS) handling in Pin ***</p>
|
|
<p>Background about segment virtualization support in Pin: Segment virtualization was introduced in Pin in the past in order to support Pin on OS's which didn't contain old (without segment usage) libc in a standard installation. Application and Pin were using 2 different TLS's, however access to them was done through segment registers (Also known as thread-self-pointer registers) (actually through their matching segment descriptor which contain the segment base address). Segment register (selector) can have one value at a time. Changing segment register value back and forth (from application to Pin and the other way around) is very costly performance wise (involve system calls). Also there may have been other limitations. Therefore it was decided to emulate application instructions which use segments registers. This is done by saving segment selector value and segment base address in the spill area (i.e REG_PIN_SEG_GS_VAL and REG_SEG_GS_BASE ) for each thread and performing all segment related instruction (of the application) using their values (by emulating instructions that set these registers and translate instructions that are accessing the memory using fs or gs prefix - we call this virtualizing segment). (This also help when passing effective address of memory operands to analysis routines) In Linux 32 bit the segment base address changes every time we write to a segment register (every time we load GS/FS, the hidden part is also loaded with the segment base address - it's kind of a cache for optimization, to save bus cycles) In order to support this beside emulating these in instructions we also tracked GDT/LDT tables (We store these tables inside Pin and update them every time needed).</p>
|
|
<p>Today we have PinCRT which doesn't use segment registers, therefore we don't have to virtualize application segment usage and just let application execute these instructions in their original form (without modifying them or without emulating them).</p>
|
|
<p>Linux In Linux we no longer virtualize application handling of segments: application instructions which uses segments or segments prefix now runs in their original form. In Linux 64 bits we now only track segment base address virtual register by emulating the system call which changes the segment base address (track application segment base address inside a virtual register in addition to updating the application one). In Linux 32 bits it's more complicated: It's hard to track the segment address without fully emulating all writes to segment registers + tracking the GDT/LDT which is a lot of work. Instead we're using GsBaseAddress()/FsBaseAddress() where needed including in PrecomputeSegBaseAddressIfNeeded() which is called from SetupArgumentEa() when needing to compute REG_SEG_FS_BASE/REG_SEG_GS_BASE value (holds the segment base address)</p>
|
|
<p>macOS In macOS, PIN still use (at least) the system loader which uses the GS segment register, therefore segment virtualization is still used.</p>
|
|
<p>Windows In Windows we compute segment base address at the beginning (assume it doens't change) and use its value when needed. REG_PIN_SEG_GS_VAL and REG_PIN_SEG_FS_VAL are unused in this platform </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaae06493e866ba2fcfe67f5cee7c9e0262"></a>REG_SEG_FS_BASE </td><td class="fielddoc"><p>Base address for FS segment. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaabffe023180c3055f8e337d0ee253ad44"></a>REG_INST_SCRATCH_BASE </td><td class="fielddoc"><p>First available scratch register. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa0c74b67cf274f09260e3487e3e50fc8d"></a>REG_INST_G0 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa7f36e2387bc4a1829178069800541ef9"></a>REG_INST_G1 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaae4ea8dfff667c04c7fc1dc31ca58034c"></a>REG_INST_G2 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa38ce8959771849b6d19666704cbde709"></a>REG_INST_G3 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaf864b78729c325072880aaca91c4fc95"></a>REG_INST_G4 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa0bf3c225420ed8b7efb4bdcf9cc96b7a"></a>REG_INST_G5 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa7a495b5a550802bbfc2fe607347fe215"></a>REG_INST_G6 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa9c5b06055777d4d2e9aec17bd12c23c8"></a>REG_INST_G7 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa396783de27aaf9ad09d32b856f2a8470"></a>REG_INST_G8 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa725ffa82752261f7e6d02f61f823e947"></a>REG_INST_G9 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa95bd2a7996373994211f4abdca6fddd0"></a>REG_INST_G10 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa6627b33852420083e7e1bf92ff9b0623"></a>REG_INST_G11 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaf04944e9076e9486a2b3b041c53febac"></a>REG_INST_G12 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaac345a6a2a3b09a8c3d904d1449ab1bea"></a>REG_INST_G13 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa109cec4ef8f3a7cef69cd715f570aee7"></a>REG_INST_G14 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa4cba02ec1f94e2108075f73542c61437"></a>REG_INST_G15 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaae9c516698c3454b8affdd500f632693e"></a>REG_INST_G16 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa2733a20abd14c288797c29496caf54c0"></a>REG_INST_G17 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaf96e4e4238b1cdaa2e2698e79167827d"></a>REG_INST_G18 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa190b77795e4b9f2deffb1b71f6b5e1db"></a>REG_INST_G19 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa59acca29ce8ae55d494b25143e34f9d9"></a>REG_INST_G20 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaf690aa538da5a908981ac893e1f4e161"></a>REG_INST_G21 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa93e9ba0aefceb84674a5925b95419b81"></a>REG_INST_G22 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaa59446ebc8910a87f43a2962d9346b47"></a>REG_INST_G23 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaadfbfc0159ae81ed87d59b3adb70cab38"></a>REG_INST_G24 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa6be65a34d0304c3e9825ae7cfbb7be5e"></a>REG_INST_G25 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaa307f73d50cf2fdc59b71110ab6dfedf"></a>REG_INST_G26 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa711d70383ecc473d6ac60e1307c405f3"></a>REG_INST_G27 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa26c3d0b42cd2b43370836043e51d44db"></a>REG_INST_G28 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa9d258abf4f7fe9fa6f39f0e5607d31c4"></a>REG_INST_G29 </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa680a1bfdef427ad22d9c06862ca8be39"></a>REG_INST_G0D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa4384a63975e93079edbdf6f914c91732"></a>REG_INST_G1D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaad3fec62dc380397b4cf41a514a3f6381"></a>REG_INST_G2D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaab42714aeb5c33f414c6860fb1701ceb4"></a>REG_INST_G3D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa9185ce9d3f47355f393f54e0c8268bf1"></a>REG_INST_G4D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa5e3f60762c1e72653f9381e0a0250553"></a>REG_INST_G5D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa8e45920c2fe6bec8ad40a7fbfc0c90ff"></a>REG_INST_G6D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa7ecb1bf582da4d3336532c9774a50d58"></a>REG_INST_G7D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa443b750b1dfcd746b22dc7c9bc1f3fb4"></a>REG_INST_G8D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa6531c29aa82e400fe348f82ea3a3579b"></a>REG_INST_G9D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa6569df93fe3d531d2ecf6ebab4d135f1"></a>REG_INST_G10D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa4b6125afbf609af5e6627b5b491e6b5a"></a>REG_INST_G11D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaab5eeb574296c5bb42155de0f59e4c21d"></a>REG_INST_G12D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa367f555821f763a6ae6803d12c83a6c4"></a>REG_INST_G13D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa1b2a30adcbad87161f6b6047d61bfa75"></a>REG_INST_G14D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa49d95be2d2d1994558c6d9936ecbdd96"></a>REG_INST_G15D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaa5bf9e9157c37c2487c5869abb1418db"></a>REG_INST_G16D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa99e34eca2b534c4034912582b293892a"></a>REG_INST_G17D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaacbb74d7b0dffce4df7fb6760bd6a2395"></a>REG_INST_G18D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa401cb474591a1dae4b42c26b0877d0fe"></a>REG_INST_G19D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa9aed97ea0abb130117bc059561ef247f"></a>REG_INST_G20D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaf1721d92e36953871368eb3fa0b5e8de"></a>REG_INST_G21D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa3d4c6db543fcaa093b859bcdaa85bd7d"></a>REG_INST_G22D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
|
|
</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaaa0b8ebb1eda36a8c3dce32deea7a6281"></a>REG_INST_G23D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaab810110c5b5523798315394e3fb62782"></a>REG_INST_G24D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa420162b67835d1eb2fd238c9abc824eb"></a>REG_INST_G25D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa243b6406845f5cf683cac4277f6b060d"></a>REG_INST_G26D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa52245952c7a0a7145b74d4c5bd63af9b"></a>REG_INST_G27D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa2826c67e5eb083839961dab33b3d488d"></a>REG_INST_G28D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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</td></tr>
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<tr><td class="fieldname"><a id="gga0f57fb50e80d686a588694f73046f2aaa2e62148d88ea152ca22bc07960775bb5"></a>REG_INST_G29D </td><td class="fielddoc"><p>Scratch register used in pintools. </p>
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<a id="ga9df40496bf2f29c7a2c5980be42dcb78"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga9df40496bf2f29c7a2c5980be42dcb78">◆ </a></span>REG_ACCESS</h2>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#ga9df40496bf2f29c7a2c5980be42dcb78">LEVEL_BASE::REG_ACCESS</a></td>
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<p>Registers access type in context via GetContextReg/SetContextReg </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2b1cf2faaa7fa5341a7b8ea382a0fadd">◆ </a></span>REG_ALLOC_TYPE</h2>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#ga2b1cf2faaa7fa5341a7b8ea382a0fadd">LEVEL_BASE::REG_ALLOC_TYPE</a></td>
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<p>Classification of registers under register allocation. Registers of the same allocation type can replace each other during register re-allocation. </p>
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<a id="ga99beb1f4b1dd69c64e5aff9591f7eb24"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga99beb1f4b1dd69c64e5aff9591f7eb24">◆ </a></span>REG_CLASS</h2>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#ga99beb1f4b1dd69c64e5aff9591f7eb24">LEVEL_BASE::REG_CLASS</a></td>
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</div><div class="memdoc">
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<p>Enumeration of register classes. Each register belongs to one and only one class. </p>
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<a id="gac3fde05e1d7397e8e525ac3f60872406"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gac3fde05e1d7397e8e525ac3f60872406">◆ </a></span>REG_SUBCLASS</h2>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#gac3fde05e1d7397e8e525ac3f60872406">LEVEL_BASE::REG_SUBCLASS</a></td>
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</div><div class="memdoc">
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<p>Additional classification of register. </p>
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<a id="gacc81a8433e2f250fc341758e21611be6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gacc81a8433e2f250fc341758e21611be6">◆ </a></span>REGNAME</h2>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#gacc81a8433e2f250fc341758e21611be6">LEVEL_BASE::REGNAME</a></td>
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<p>x </p>
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<a id="ga92c4a19fb1078e9a7d9a54b42d3118e7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga92c4a19fb1078e9a7d9a54b42d3118e7">◆ </a></span>REGWIDTH</h2>
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<td class="memname">enum <a class="el" href="group__REG__CPU__IA32.html#ga92c4a19fb1078e9a7d9a54b42d3118e7">LEVEL_BASE::REGWIDTH</a></td>
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<p>register widths </p>
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<h2 class="groupheader">Function Documentation</h2>
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<a id="ga0c875987af64889967b8fcdce47cc0aa"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0c875987af64889967b8fcdce47cc0aa">◆ </a></span>REG_AppFlags()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_AppFlags </td>
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<td>(</td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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<dl class="section return"><dt>Returns</dt><dd>the application flags register </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ga96237638ef307496aef198c3c64294eb">◆ </a></span>REG_corresponding_ymm_reg()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_corresponding_ymm_reg </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>the corresponding ymm reg to an xmm reg: e.g. if reg is xmm4 return ymm4 ASSUMES that REG_is_xmm returns TRUE on reg </dd></dl>
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<a id="gac3996eaec372864e8619522b28b20af5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gac3996eaec372864e8619522b28b20af5">◆ </a></span>REG_corresponding_zmm_reg()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_corresponding_zmm_reg </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>the corresponding zmm reg to an xmm reg: e.g. if reg is xmm4 return zmm4 ASSUMES that REG_is_xmm returns TRUE on reg </dd></dl>
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<a id="gab16386559e6315c56e2f8673304c9db2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gab16386559e6315c56e2f8673304c9db2">◆ </a></span>REG_get_df_flag_reg_of_type()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_get_df_flag_reg_of_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>TGiven that reg is either REG_GFLAGS or REG_PIN_FLAGS, return the corresponding *_DF_FLAG reg </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#gab7683ee760514ceb26ba258899d86c68">◆ </a></span>REG_get_full_flags_reg_of_type()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_get_full_flags_reg_of_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>the full flags reg of either the app or pin reg - depending on what type of reg reg is </dd></dl>
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<a id="ga0cdd646a3e668c22d46a8d71fafd15a4"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0cdd646a3e668c22d46a8d71fafd15a4">◆ </a></span>REG_get_status_flags_reg_of_type()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_get_status_flags_reg_of_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>Given that reg is either REG_GFLAGS or REG_PIN_FLAGS, return the corresponding *_STATUS_FLAGS reg </dd></dl>
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<a id="ga0838dab8af04897b565593f3d87bee1e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0838dab8af04897b565593f3d87bee1e">◆ </a></span>REG_IdentityCopy()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_IdentityCopy </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>the application register that is the counterpart of this Pin reg </dd></dl>
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<a id="gaa1123ed2e29dd34f3612e105790f7950"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa1123ed2e29dd34f3612e105790f7950">◆ </a></span>REG_is_Any8()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_Any8 </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>Return TRUE if reg is a upper or lower 8-bit register </p>
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<a id="ga50827a2b7e6d17ab3aa6ed0360c0855a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga50827a2b7e6d17ab3aa6ed0360c0855a">◆ </a></span>REG_is_any_app_flags()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_any_app_flags </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is Any of the app flag regs </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ga084c8aa78ffa2e723454ac723d163af8">◆ </a></span>REG_is_any_flags_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_any_flags_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is Any of the flag regs app or pin </dd></dl>
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<a id="gadf4160e5284a5e993bdc87281ea1cd2e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gadf4160e5284a5e993bdc87281ea1cd2e">◆ </a></span>REG_is_any_mask()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_any_mask </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a k-mask register or its Pin variant </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3c6ce7d36d83ef56793585a413123667">◆ </a></span>REG_is_any_mxcsr()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_any_mxcsr </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>true if reg is mxcsr or its Pin variant </dd></dl>
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<a id="ga4b65cba2f06839c5950a464deccab0d8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4b65cba2f06839c5950a464deccab0d8">◆ </a></span>REG_is_any_pin_flags()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_any_pin_flags </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is Any of the pinflag regs </dd></dl>
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<a id="gab8d1dddc8e3ecb847f01fe5fc5bed700"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gab8d1dddc8e3ecb847f01fe5fc5bed700">◆ </a></span>REG_is_any_vector_reg()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_any_vector_reg </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is an xmm,ymm, or zmm register, or their Pin variants. </dd></dl>
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<a id="ga5bca059473be021381d5445e59a679d1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga5bca059473be021381d5445e59a679d1">◆ </a></span>REG_is_app_df_flag_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_app_df_flag_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is REG_DF_FLAG or PIN_REG_DF_FLAG </dd></dl>
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</div>
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<a id="gaaf7bafd739169dd8c707f0657c4659a2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gaaf7bafd739169dd8c707f0657c4659a2">◆ </a></span>REG_is_app_status_flags_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_app_status_flags_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff REG_STATUS_FLAGS </dd></dl>
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</div>
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<a id="ga107fe336a80ef8e0cdefeedd2af83b6e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga107fe336a80ef8e0cdefeedd2af83b6e">◆ </a></span>REG_is_application()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_application </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is an application register </dd></dl>
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<a id="ga9e0a8031d762afdf3216ab5542350a7b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga9e0a8031d762afdf3216ab5542350a7b">◆ </a></span>REG_is_avx512_hi16_xmm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_avx512_hi16_xmm </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>xmm</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if the given xmm is one of xmm16-xmm31 </dd></dl>
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<a id="gabd3d888174d3abb6d37bcd4f095fbe40"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gabd3d888174d3abb6d37bcd4f095fbe40">◆ </a></span>REG_is_avx512_hi16_ymm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_avx512_hi16_ymm </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>ymm</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if the given ymm is one of ymm16-ymm31 </dd></dl>
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<a id="ga6e514a3db62e6e091354cd32603e46e1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga6e514a3db62e6e091354cd32603e46e1">◆ </a></span>REG_is_buffer()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_buffer </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app flags </dd></dl>
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</div>
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<a id="ga1d2f4f32ab0759aee693e46f80f84c6b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1d2f4f32ab0759aee693e46f80f84c6b">◆ </a></span>REG_is_df_flag()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_df_flag </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app df flag </dd></dl>
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<a id="ga8470c1e882b5abe9554f46cd2b546a76"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8470c1e882b5abe9554f46cd2b546a76">◆ </a></span>REG_is_df_flag_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_df_flag_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is REG_DF_FLAG or PIN_REG_DF_FLAG </dd></dl>
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<a id="ga087cd367780291f3f0157b8a12ae4b3c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga087cd367780291f3f0157b8a12ae4b3c">◆ </a></span>REG_is_flags()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_flags </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app flags </dd></dl>
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<a id="ga634c2b5fdd67a1a0df7fc1796279256a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga634c2b5fdd67a1a0df7fc1796279256a">◆ </a></span>REG_is_flags_any_size_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_flags_any_size_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff both app and pin (and redundant for both) flags regs </dd></dl>
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<a id="gae8f8fcd44f901c4ccba9d942ac8daf61"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gae8f8fcd44f901c4ccba9d942ac8daf61">◆ </a></span>REG_is_flags_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_flags_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff both app and pin (and redundant for both) flags regs </dd></dl>
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<a id="gacad5be362797ba8fc511ed7b2243ea56"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gacad5be362797ba8fc511ed7b2243ea56">◆ </a></span>REG_is_fr_for_get_context()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_fr_for_get_context </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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</table>
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a floating register appropriate for PIN_GetContextReg </dd></dl>
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<a id="ga54d7b385d35f4771ba1222e8a5ca93a0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga54d7b385d35f4771ba1222e8a5ca93a0">◆ </a></span>REG_is_gr_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_gr_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if it is a gr reg </dd></dl>
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<a id="gaa0293eb62c56e47c0864c0a768e9ac0e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa0293eb62c56e47c0864c0a768e9ac0e">◆ </a></span>REG_is_gs_or_fs()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_gs_or_fs </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>Return TRUE if the register a GS or FS register </p>
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<a id="ga2c6504a4bfa4a1007a1f0b792f345091"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2c6504a4bfa4a1007a1f0b792f345091">◆ </a></span>REG_is_Half16()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_Half16 </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>Return TRUE if reg is a lower 16-bit register </p>
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<a id="ga7da10abdb51e61b11f791beaa5b2a8e7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7da10abdb51e61b11f791beaa5b2a8e7">◆ </a></span>REG_is_Half32()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_Half32 </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>Return TRUE if reg is a lower 32-bit register, actually any 32 bit register </p>
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<a id="ga0e8881e1755de23c4340c8cf8d1040b7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0e8881e1755de23c4340c8cf8d1040b7">◆ </a></span>REG_is_inst_scratch()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_inst_scratch </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app flags </dd></dl>
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</div>
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<a id="ga20f36aedce3f9950a8ce857de96fb869"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga20f36aedce3f9950a8ce857de96fb869">◆ </a></span>REG_is_k_mask()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_k_mask </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a k-mask register </dd></dl>
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</div>
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<a id="gae565098e5f19a2979173e15c823f049d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gae565098e5f19a2979173e15c823f049d">◆ </a></span>REG_is_Lower8()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_Lower8 </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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<p>Return TRUE if reg is a lower 8-bit register </p>
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</div>
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<a id="gab69f78cae1b602686561a849b9d21eb9"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gab69f78cae1b602686561a849b9d21eb9">◆ </a></span>REG_is_machine()</h2>
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<div class="memitem">
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<td class="memname">BOOL LEVEL_BASE::REG_is_machine </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a machine register </dd></dl>
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</div>
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</div>
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<a id="gad43d44806bd22c39078899f17a81b8b6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gad43d44806bd22c39078899f17a81b8b6">◆ </a></span>REG_is_mm()</h2>
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<div class="memitem">
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<td class="memname">BOOL LEVEL_BASE::REG_is_mm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is an mmx register </dd></dl>
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</div>
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</div>
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<a id="ga84e26c54a557be59d9939c89e9fd8ee9"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga84e26c54a557be59d9939c89e9fd8ee9">◆ </a></span>REG_is_mxcsr()</h2>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">BOOL LEVEL_BASE::REG_is_mxcsr </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is the mxcsr </dd></dl>
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</div>
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</div>
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<a id="ga7e54ad3a41450c87d324ecac6d6da2ec"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7e54ad3a41450c87d324ecac6d6da2ec">◆ </a></span>REG_is_partialreg()</h2>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">BOOL LEVEL_BASE::REG_is_partialreg </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Return TRUE if reg is a partial register </p>
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</div>
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</div>
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<a id="gae6b2fc14f383b093a27097259305dfdc"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gae6b2fc14f383b093a27097259305dfdc">◆ </a></span>REG_is_pin()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a pin register </dd></dl>
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</div>
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</div>
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<a id="ga1871b77d94620cc6efef010ccce53d1f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1871b77d94620cc6efef010ccce53d1f">◆ </a></span>REG_is_pin_df_flag()</h2>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_df_flag </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is pin df flags </dd></dl>
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</div>
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</div>
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<a id="ga90646665d884a896b3ad112712a13c2c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga90646665d884a896b3ad112712a13c2c">◆ </a></span>REG_is_pin_flags()</h2>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_flags </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is pin flags </dd></dl>
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</div>
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</div>
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<a id="ga4649f4bf511de60a8c38744f2b30d229"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4649f4bf511de60a8c38744f2b30d229">◆ </a></span>REG_is_pin_gpr()</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_gpr </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff pin general purpose register </dd></dl>
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</div>
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</div>
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<a id="ga67014bc28ef11cffdd77303e65fae0ec"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga67014bc28ef11cffdd77303e65fae0ec">◆ </a></span>REG_is_pin_inst()</h2>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_inst </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app flags </dd></dl>
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</div>
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</div>
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<a id="ga3ff7dcfeb1fb8e6b0795a3baff67b4f2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3ff7dcfeb1fb8e6b0795a3baff67b4f2">◆ </a></span>REG_is_pin_k_mask()</h2>
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<div class="memitem">
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<table class="memname">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_k_mask </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a pin virtual mask register </dd></dl>
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</div>
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</div>
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<a id="ga7c3dc7ae6ba3baedc1c5cfc4a77d70ec"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7c3dc7ae6ba3baedc1c5cfc4a77d70ec">◆ </a></span>REG_is_pin_status_flags()</h2>
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<div class="memitem">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_status_flags </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is pin status flag </dd></dl>
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</div>
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</div>
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<a id="gae43bac2e4d7245a1f6e911748ae6c3e5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gae43bac2e4d7245a1f6e911748ae6c3e5">◆ </a></span>REG_is_pin_tmp()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_tmp </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff pin tmp regs </dd></dl>
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</div>
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<a id="ga12f19d16124b7d75f776cf03a7fb9b65"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga12f19d16124b7d75f776cf03a7fb9b65">◆ </a></span>REG_is_pin_xmm()</h2>
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<div class="memitem">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_xmm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a pin virtual sse register </dd></dl>
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</div>
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</div>
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<a id="gaabccd8e7ec839504ba6899c56c5ed7d1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gaabccd8e7ec839504ba6899c56c5ed7d1">◆ </a></span>REG_is_pin_xmm_ymm_zmm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_xmm_ymm_zmm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a Pin xmm, ymm or zmm register </dd></dl>
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</div>
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</div>
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<a id="ga37942a62b7634a2de68f0eaaf4d8f3ff"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga37942a62b7634a2de68f0eaaf4d8f3ff">◆ </a></span>REG_is_pin_ymm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_ymm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a pin virtual ymm register </dd></dl>
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</div>
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</div>
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<a id="ga46fdc74702dfffd8458a1a7264deffb2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga46fdc74702dfffd8458a1a7264deffb2">◆ </a></span>REG_is_pin_zmm()</h2>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">BOOL LEVEL_BASE::REG_is_pin_zmm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
|
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a pin virtual zmm register </dd></dl>
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</div>
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</div>
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<a id="ga349ef4d923d81de6d8d5c48e4bc272e0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga349ef4d923d81de6d8d5c48e4bc272e0">◆ </a></span>REG_is_representative_reg()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_representative_reg </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
|
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is representative register for internal purposes </dd></dl>
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</div>
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</div>
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<a id="ga5c950bcf48a41d323154dbf13aa6f08f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga5c950bcf48a41d323154dbf13aa6f08f">◆ </a></span>REG_is_seg_base()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_seg_base </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
|
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a segment base address virtual register (REG_SEG_GS_BASE/REG_SEG_FS_BASE) </dd></dl>
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</div>
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</div>
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<a id="gad5ce416e2c302776771a62e78b3bff3e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gad5ce416e2c302776771a62e78b3bff3e">◆ </a></span>REG_is_st()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_st </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a x87 FPU stack register </dd></dl>
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<a id="gab815b1ed5561a011f918bcb0d90af257"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gab815b1ed5561a011f918bcb0d90af257">◆ </a></span>REG_is_stackptr_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_stackptr_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE both app and pin stack ptrs </dd></dl>
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</div>
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</div>
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<a id="gaf430d3bb8a23fa507a8789eae73bc995"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gaf430d3bb8a23fa507a8789eae73bc995">◆ </a></span>REG_is_status_flags()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_status_flags </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is is app status flags </dd></dl>
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</div>
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<a id="gab3ee3646600609b04c8e7594d0373965"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gab3ee3646600609b04c8e7594d0373965">◆ </a></span>REG_is_status_flags_type()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_status_flags_type </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is REG_STATUS_FLAGS or PIN_REG_STATUS_FLAGS </dd></dl>
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</div>
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<a id="ga1e292f4b7937a81fb41b5465dc1c467b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1e292f4b7937a81fb41b5465dc1c467b">◆ </a></span>REG_is_subclass_none()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_subclass_none </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff subclass of reg is none </dd></dl>
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</div>
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<a id="ga6fae2ff2ecca2771b05d976f812241e8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga6fae2ff2ecca2771b05d976f812241e8">◆ </a></span>REG_is_Upper8()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_Upper8 </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>Return TRUE if reg is a upper 8-bit register </p>
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<a id="gad0ddaf16b2320ffcd0e41801906c4b04"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gad0ddaf16b2320ffcd0e41801906c4b04">◆ </a></span>REG_is_xmm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_xmm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is an sse register </dd></dl>
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<a id="ga8efc75a83fc1476dbe69fb41019cb195"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8efc75a83fc1476dbe69fb41019cb195">◆ </a></span>REG_is_xmm_ymm_zmm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_xmm_ymm_zmm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is an xmm,ymm, or zmm register </dd></dl>
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<a id="gae3dc27099d5bb520216a50bd00b1db60"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gae3dc27099d5bb520216a50bd00b1db60">◆ </a></span>REG_is_ymm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_ymm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a ymm register </dd></dl>
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<a id="gabc16a50e8a5c6a91748c8d1f35d21440"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gabc16a50e8a5c6a91748c8d1f35d21440">◆ </a></span>REG_is_zmm()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_is_zmm </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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</div><div class="memdoc">
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<dl class="section return"><dt>Returns</dt><dd>true if reg is a zmm register </dd></dl>
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<a id="ga28676b9554c951c74a2f8b720a4b7ab2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga28676b9554c951c74a2f8b720a4b7ab2">◆ </a></span>REG_LastSupportedXmm()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_LastSupportedXmm </td>
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<td>(</td>
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<td class="paramname"></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>the highest xmm register supported on the current CPU </dd></dl>
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<a id="ga2681487338ec6a41511bc49dea51849f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2681487338ec6a41511bc49dea51849f">◆ </a></span>REG_LastSupportedYmm()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_LastSupportedYmm </td>
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<td>(</td>
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<dl class="section return"><dt>Returns</dt><dd>the highest ymm register supported on the current CPU </dd></dl>
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<a id="ga37dd352d87e8b1b793a9525f9ed08bda"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga37dd352d87e8b1b793a9525f9ed08bda">◆ </a></span>REG_LastSupportedZmm()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> LEVEL_BASE::REG_LastSupportedZmm </td>
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<td>(</td>
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<td class="paramname"></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>the highest zmm register supported on the current CPU </dd></dl>
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<a id="gacb5d2041bfaef6560e7fdd2094d0d9df"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gacb5d2041bfaef6560e7fdd2094d0d9df">◆ </a></span>REG_regDefTable()</h2>
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<td class="memname">ADDRINT LEVEL_BASE::REG_regDefTable </td>
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<td>(</td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app flags </dd></dl>
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<a id="ga4e0a17685f3326079eb42bedb129d0a0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4e0a17685f3326079eb42bedb129d0a0">◆ </a></span>REG_regSubClassBitMapTable()</h2>
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<td class="memname">ADDRINT LEVEL_BASE::REG_regSubClassBitMapTable </td>
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<td>(</td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE iff is app flags </dd></dl>
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<a id="ga8744ba41569c7770f4aa41f8e2d0b4e6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8744ba41569c7770f4aa41f8e2d0b4e6">◆ </a></span>REG_Size()</h2>
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<td class="memname">UINT32 LEVEL_BASE::REG_Size </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>return the register size in bytes </p>
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<a id="ga42d43c5a7062cb843a8914d4b20c003a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga42d43c5a7062cb843a8914d4b20c003a">◆ </a></span>REG_valid_for_iarg_reg_value()</h2>
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<td class="memname">BOOL LEVEL_BASE::REG_valid_for_iarg_reg_value </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>true if reg value of reg can be requested by IARG_REG_VALUE </dd></dl>
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<a id="ga86a3431be0730babc838c6fe87ee9c2c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga86a3431be0730babc838c6fe87ee9c2c">◆ </a></span>REG_Width()</h2>
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<td class="memname"><a class="el" href="group__REG__CPU__IA32.html#ga92c4a19fb1078e9a7d9a54b42d3118e7">REGWIDTH</a> LEVEL_BASE::REG_Width </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td>
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<td class="paramname"><em>reg</em></td><td>)</td>
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<p>return the register width for all regs. </p>
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<a id="ga59b1d2e23d3de5edb229047382abfa22"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga59b1d2e23d3de5edb229047382abfa22">◆ </a></span>REGSET_AddAll()</h2>
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<td class="memname">VOID LEVEL_CORE::REGSET_AddAll </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> & </td>
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<td class="paramname"><em>regset</em></td><td>)</td>
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<p>Insert all registers into the specified regset </p>
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<a id="gaa8d6bc907483b84a882565de6a5025e6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa8d6bc907483b84a882565de6a5025e6">◆ </a></span>REGSET_Clear()</h2>
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<td class="memname">VOID LEVEL_CORE::REGSET_Clear </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> & </td>
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<td class="paramname"><em>regset</em></td><td>)</td>
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<p>Remove all registers from the specified regset </p>
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<a id="ga8ed23b197782e88ec8dcda1efb04c7c3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8ed23b197782e88ec8dcda1efb04c7c3">◆ </a></span>REGSET_Contains()</h2>
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<td class="memname">BOOL LEVEL_CORE::REGSET_Contains </td>
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<td>(</td>
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<td class="paramtype">const <a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> & </td>
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<td class="paramname"><em>regset</em>, </td>
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<td class="paramtype">REG </td>
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<td class="paramname"><em>reg</em> </td>
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<td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE if the specified reg is contained in the specified regset </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7d0aca55c4e11785153c4f4bd83328c2">◆ </a></span>REGSET_Insert()</h2>
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<td class="memname">VOID LEVEL_CORE::REGSET_Insert </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> & </td>
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<td class="paramname"><em>regset</em>, </td>
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<td class="paramname"><em>reg</em> </td>
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<p>Insert the specified reg into the specified regset </p>
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<h2 class="memtitle"><span class="permalink"><a href="#gac5530b1d15830b6e844f86d9d104606b">◆ </a></span>REGSET_PopCount()</h2>
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<td class="memname">UINT32 LEVEL_CORE::REGSET_PopCount </td>
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<dl class="section return"><dt>Returns</dt><dd>the number of registers in the specified regset </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#gacb4df67645a5af50e61c0b2bae9b7f62">◆ </a></span>REGSET_PopCountIsZero()</h2>
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<td class="memname">BOOL LEVEL_CORE::REGSET_PopCountIsZero </td>
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<td>(</td>
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<dl class="section return"><dt>Returns</dt><dd>TRUE if the number of registers in the specified regset is zero </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ga21f89d33c92eb340dd1aaed30c7d6e72">◆ </a></span>REGSET_PopNext()</h2>
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<td class="memname">REG LEVEL_CORE::REGSET_PopNext </td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> & </td>
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<p>Pop the next register from the specified regset </p><dl class="section return"><dt>Returns</dt><dd>the popped register </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ga9bc09e7fbd3f8ddad1e47c83c8ca6323">◆ </a></span>REGSET_Remove()</h2>
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<td class="memname">VOID LEVEL_CORE::REGSET_Remove </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__REG__CPU__IA32.html#gae457153aab05650d6845e3553731ee63">REGSET</a> & </td>
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<td class="paramname"><em>reg</em> </td>
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<p>Remove the specified reg from the specified regset </p>
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<h2 class="memtitle"><span class="permalink"><a href="#gac8cf49d0b0fa523059da94bca3fbf061">◆ </a></span>REGSET_StringShort()</h2>
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<td class="memname">std::string LEVEL_CORE::REGSET_StringShort </td>
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<td>(</td>
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<dl class="section return"><dt>Returns</dt><dd>a string with the names of all registers is the specified regset </dd></dl>
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<h2 class="groupheader">Variable Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#gafe098bafa41995c53db7a915ee61922e">◆ </a></span>_regDefTable</h2>
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<td class="memname">const <a class="el" href="structLEVEL__BASE_1_1REGDEF__ENTRY.html">REGDEF_ENTRY</a> LEVEL_BASE::_regDefTable[]</td>
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<p>The main register information table </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga36e0b500918a2b869aecf6fbe2467189">◆ </a></span>_regWidthToBitWidth</h2>
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<td class="memname">INT32 LEVEL_BASE::_regWidthToBitWidth[]</td>
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<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line">{</div><div class="line"> 8,</div><div class="line"> 16,</div><div class="line"> 32,</div><div class="line"> 64,</div><div class="line"> 80,</div><div class="line"> 128,</div><div class="line"> 256,</div><div class="line"> 512,</div><div class="line"> REG_X87_SIZE,</div><div class="line"> 0</div><div class="line">}</div></div><!-- fragment -->
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<h2 class="memtitle"><span class="permalink"><a href="#gac3c3f8a822d40e53bc8c599368eb9a44">◆ </a></span>REG_LastInRegset</h2>
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<td class="memname">GLOBALCONST REG LEVEL_CORE::REG_LastInRegset = REG(REG_LAST-1)</td>
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<p>REG represented by the last bit in the regset vector. Most of the code assumes that REG_LAST is not an actual register, so we should not include it in the set. We use REG_LAST-1 for the last registers. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3dbb64324ec7e6cf592b3a007d637e41">◆ </a></span>REGCBIT_ALL_REGS</h2>
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<td class="memname">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> LEVEL_BASE::REGCBIT_ALL_REGS = <a class="el" href="group__REG__CPU__IA32.html#gafef963c990ff2998f8a62044ca08f5af">REGCBIT_APP_ALL</a> | <a class="el" href="group__REG__CPU__IA32.html#ga0003ddbd5a31411cef15fe6adc6a1bf4">REGCBIT_PIN_ALL</a></td>
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<p>Mask of REG_CLASS_BITS values for all valid registers.xx </p>
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<h2 class="memtitle"><span class="permalink"><a href="#gafef963c990ff2998f8a62044ca08f5af">◆ </a></span>REGCBIT_APP_ALL</h2>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"> _REGCBIT(REG_CLASS_PSEUDO) |</div><div class="line"> (_REGCBIT(REG_CLASS_GR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRU8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRL8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRH16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRH32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_SEG) )|</div><div class="line"> (_REGCBIT(REG_CLASS_MM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_XMM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_YMM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_ZMM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_K) )|</div><div class="line"> (_REGCBIT(REG_CLASS_FPST) )|</div><div class="line"> (_REGCBIT(REG_CLASS_ST) )|</div><div class="line"> (_REGCBIT(REG_CLASS_CR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_DR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_TR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_FLAGS16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_FLAGS32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_STATUS_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_DFLAG) )|</div><div class="line"> (_REGCBIT(REG_CLASS_X87) )|</div><div class="line"> (_REGCBIT(REG_CLASS_MXCSR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_MXCSRMASK) )|</div><div class="line"> (_REGCBIT(REG_CLASS_IP) )|</div><div class="line"> (_REGCBIT(REG_CLASS_IP16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_IP32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_ARCH))</div></div><!-- fragment --><p>Mask of REG_CLASS_BITS values for all application registers. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga797c94104721a4d10c3375d92f8a977a">◆ </a></span>REGCBIT_APP_FLAGS</h2>
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<td class="memname">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> LEVEL_BASE::REGCBIT_APP_FLAGS</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"></div><div class="line"> (_REGCBIT(REG_CLASS_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_STATUS_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_DFLAG))</div></div><!-- fragment --><p>Mask of REG_CLASS_BITS values for all application flag registers. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#gadaec9333a54cfb71118ad03996943c69">◆ </a></span>REGCBIT_PARTIAL</h2>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"> (_REGCBIT(REG_CLASS_GRU8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRL8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRH16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_GRH32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_FLAGS16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_FLAGS32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_IP16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_IP32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRU8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRL8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRH16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRH32))</div></div><!-- fragment --><p>Mask of REG_CLASS_BITS values for partial registers (excluding XMM, even if AVX is present). </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0003ddbd5a31411cef15fe6adc6a1bf4">◆ </a></span>REGCBIT_PIN_ALL</h2>
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<td class="memname">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> LEVEL_BASE::REGCBIT_PIN_ALL</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"></div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRU8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRL8) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRH16) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_GRH32) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_XMM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_YMM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_ZMM) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_K) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_X87) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_MXCSR) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_STATUS_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_DFLAG))</div></div><!-- fragment --><p>Mask of REG_CLASS_BITS values for all Pin registers. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga42d784c0a1e776497acb405282fab148">◆ </a></span>REGCBIT_PIN_FLAGS</h2>
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<td class="memname">GLOBALCONST <a class="el" href="group__REG__CPU__IA32.html#ga5b0b71675518f3b3e967334d71a967d4">REG_CLASS_BITS</a> LEVEL_BASE::REGCBIT_PIN_FLAGS</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"> (_REGCBIT(REG_CLASS_PIN_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_STATUS_FLAGS) )|</div><div class="line"> (_REGCBIT(REG_CLASS_PIN_DFLAG))</div></div><!-- fragment --><p>Mask of REG_CLASS_BITS values for all Pin flag registers. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga656d3616de3d5ae8d26f2b6252c686e3">◆ </a></span>REGSBIT_PIN_INST_ALL</h2>
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<td class="memname">GLOBALCONST REG_SUBCLASS_BITS LEVEL_BASE::REGSBIT_PIN_INST_ALL</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_INST_GR) )|</div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_INST_GR_H32) )|</div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_INST_BUF) )|</div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_INST_COND))</div></div><!-- fragment --><p>Combination of REG_SUBCLASS_BITS flags of all instrumentation registers. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga89097de642e222f3d0a0553464e2a584">◆ </a></span>REGSBIT_PIN_SCRATCH_ALL</h2>
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<td class="memname">GLOBALCONST REG_SUBCLASS_BITS LEVEL_BASE::REGSBIT_PIN_SCRATCH_ALL</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_INST_GR) )|</div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_INST_BUF))</div></div><!-- fragment --><p>Combination of REG_SUBCLASS_BITS flags of all instrumentation scratch registers. </p>
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<a id="ga10bb628d479cc23033c4295ceb9e3823"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ga10bb628d479cc23033c4295ceb9e3823">◆ </a></span>REGSBIT_STACKPTR_ALL</h2>
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<td class="memname">GLOBALCONST REG_SUBCLASS_BITS LEVEL_BASE::REGSBIT_STACKPTR_ALL</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= </div><div class="line"> (_REGCBIT(REG_SUBCLASS_FULL_STACKPTR) )|</div><div class="line"> (_REGCBIT(REG_SUBCLASS_PIN_FULL_STACKPTR))</div></div><!-- fragment --><p>Combination of REG_SUBCLASS_BITS flags of stack registers (both app and pin). </p>
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