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117 lines
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<li class="navelem"><a class="el" href="namespaceLEVEL__BASE.html">LEVEL_BASE</a></li><li class="navelem"><a class="el" href="structLEVEL__BASE_1_1REGDEF__ENTRY.html">REGDEF_ENTRY</a></li> </ul>
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<div class="header">
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<a href="#pub-attribs">Public Attributes</a> |
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<a href="structLEVEL__BASE_1_1REGDEF__ENTRY-members.html">List of all members</a> </div>
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<div class="headertitle">
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<div class="title">LEVEL_BASE::REGDEF_ENTRY Struct Reference<div class="ingroups"><a class="el" href="group__REG__BASIC__API.html">REG: Register Object</a> » <a class="el" href="group__REG__CPU__IA32.html">REG (specific to the IA-32 and Intel(R) 64 architectures)</a></div></div> </div>
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<div class="contents">
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Public Attributes</h2></td></tr>
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<tr class="memitem:a516f40e0b4fcf74f4ef9edaf46d2f19a"><td class="memItemLeft" align="right" valign="top"><a id="a516f40e0b4fcf74f4ef9edaf46d2f19a"></a>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>reg</b></td></tr>
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UINT32 </td><td class="memItemRight" valign="bottom"><b>regSpillSize</b></td></tr>
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<a class="el" href="group__REG__CPU__IA32.html#ga92c4a19fb1078e9a7d9a54b42d3118e7">REGWIDTH</a> </td><td class="memItemRight" valign="bottom"><b>regWidth</b></td></tr>
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UINT64 </td><td class="memItemRight" valign="bottom"><b>regClassBitMap</b></td></tr>
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<tr class="separator:a1757c993f1bb2f391bf9ce685ac5c3d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a467a2c52d9900c0805f806c9d21131f3"><td class="memItemLeft" align="right" valign="top"><a id="a467a2c52d9900c0805f806c9d21131f3"></a>
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UINT64 </td><td class="memItemRight" valign="bottom"><b>regSubClassBitMap</b></td></tr>
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<a class="el" href="group__REG__CPU__IA32.html#ga2b1cf2faaa7fa5341a7b8ea382a0fadd">REG_ALLOC_TYPE</a> </td><td class="memItemRight" valign="bottom"><b>regAllocType</b></td></tr>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>regFullName</b></td></tr>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>regMachineName</b></td></tr>
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<a class="el" href="group__REG__CPU__IA32.html#ga0f57fb50e80d686a588694f73046f2aa">REG</a> </td><td class="memItemRight" valign="bottom"><b>regPinName</b></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Information about a register. The _regDefTable must contain one entry for each unique register defined in the REG enum. This entry must be in the same row of the _regDefTable as the register is in the REG enum. </p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>reg_ia32.cpp</li>
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</ul>
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