wjb/evaluation/pin-3.15-98253-gb56e429b1-gcc-linux/extras/xed-ia32/include/xed/xed-iform-enum.h

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Copyright 2002-2019 Intel Corporation.

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use of them is governed by the express license under which they were provided to
you ("License"). Unless the License provides otherwise, you may not use, modify,
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/// @file xed-iform-enum.h

// This file was automatically generated.
// Do not edit this file.

#if !defined(XED_IFORM_ENUM_H)
# define XED_IFORM_ENUM_H
#include "xed-common-hdrs.h"
#include "xed-iclass-enum.h"
#define XED_IFORM_INVALID_DEFINED 1
#define XED_IFORM_AAA_DEFINED 1
#define XED_IFORM_AAD_IMMb_DEFINED 1
#define XED_IFORM_AAM_IMMb_DEFINED 1
#define XED_IFORM_AAS_DEFINED 1
#define XED_IFORM_ADC_AL_IMMb_DEFINED 1
#define XED_IFORM_ADC_GPR8_GPR8_10_DEFINED 1
#define XED_IFORM_ADC_GPR8_GPR8_12_DEFINED 1
#define XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED 1
#define XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED 1
#define XED_IFORM_ADC_GPR8_MEMb_DEFINED 1
#define XED_IFORM_ADC_GPRv_GPRv_11_DEFINED 1
#define XED_IFORM_ADC_GPRv_GPRv_13_DEFINED 1
#define XED_IFORM_ADC_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ADC_GPRv_IMMz_DEFINED 1
#define XED_IFORM_ADC_GPRv_MEMv_DEFINED 1
#define XED_IFORM_ADC_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED 1
#define XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED 1
#define XED_IFORM_ADC_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADC_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADC_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADC_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED 1
#define XED_IFORM_ADCX_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED 1
#define XED_IFORM_ADCX_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADD_AL_IMMb_DEFINED 1
#define XED_IFORM_ADD_GPR8_GPR8_00_DEFINED 1
#define XED_IFORM_ADD_GPR8_GPR8_02_DEFINED 1
#define XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED 1
#define XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED 1
#define XED_IFORM_ADD_GPR8_MEMb_DEFINED 1
#define XED_IFORM_ADD_GPRv_GPRv_01_DEFINED 1
#define XED_IFORM_ADD_GPRv_GPRv_03_DEFINED 1
#define XED_IFORM_ADD_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ADD_GPRv_IMMz_DEFINED 1
#define XED_IFORM_ADD_GPRv_MEMv_DEFINED 1
#define XED_IFORM_ADD_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED 1
#define XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED 1
#define XED_IFORM_ADD_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADD_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADD_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADD_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_ADDPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_ADDPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_ADDSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_ADDSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED 1
#define XED_IFORM_ADOX_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED 1
#define XED_IFORM_ADOX_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_AND_AL_IMMb_DEFINED 1
#define XED_IFORM_AND_GPR8_GPR8_20_DEFINED 1
#define XED_IFORM_AND_GPR8_GPR8_22_DEFINED 1
#define XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED 1
#define XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED 1
#define XED_IFORM_AND_GPR8_MEMb_DEFINED 1
#define XED_IFORM_AND_GPRv_GPRv_21_DEFINED 1
#define XED_IFORM_AND_GPRv_GPRv_23_DEFINED 1
#define XED_IFORM_AND_GPRv_IMMb_DEFINED 1
#define XED_IFORM_AND_GPRv_IMMz_DEFINED 1
#define XED_IFORM_AND_GPRv_MEMv_DEFINED 1
#define XED_IFORM_AND_MEMb_GPR8_DEFINED 1
#define XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED 1
#define XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED 1
#define XED_IFORM_AND_MEMv_GPRv_DEFINED 1
#define XED_IFORM_AND_MEMv_IMMb_DEFINED 1
#define XED_IFORM_AND_MEMv_IMMz_DEFINED 1
#define XED_IFORM_AND_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ARPL_GPR16_GPR16_DEFINED 1
#define XED_IFORM_ARPL_MEMw_GPR16_DEFINED 1
#define XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd_DEFINED 1
#define XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd_DEFINED 1
#define XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd_DEFINED 1
#define XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd_DEFINED 1
#define XED_IFORM_BLCFILL_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLCFILL_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCFILL_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLCFILL_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCI_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLCI_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCI_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLCI_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCIC_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLCIC_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCIC_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLCIC_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCMSK_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLCMSK_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCMSK_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLCMSK_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCS_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLCS_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCS_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLCS_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_BLSFILL_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLSFILL_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSFILL_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLSFILL_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLSI_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSI_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSI_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_BLSI_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BLSIC_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_BLSIC_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSIC_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_BLSIC_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BLSR_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSR_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSR_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_BLSR_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BNDCL_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDCL_BND_GPR32_DEFINED 1
#define XED_IFORM_BNDCL_BND_GPR64_DEFINED 1
#define XED_IFORM_BNDCN_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDCN_BND_GPR32_DEFINED 1
#define XED_IFORM_BNDCN_BND_GPR64_DEFINED 1
#define XED_IFORM_BNDCU_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDCU_BND_GPR32_DEFINED 1
#define XED_IFORM_BNDCU_BND_GPR64_DEFINED 1
#define XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED 1
#define XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED 1
#define XED_IFORM_BNDMK_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDMOV_BND_BND_DEFINED 1
#define XED_IFORM_BNDMOV_BND_MEMdq_DEFINED 1
#define XED_IFORM_BNDMOV_BND_MEMq_DEFINED 1
#define XED_IFORM_BNDMOV_MEMdq_BND_DEFINED 1
#define XED_IFORM_BNDMOV_MEMq_BND_DEFINED 1
#define XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED 1
#define XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED 1
#define XED_IFORM_BOUND_GPRv_MEMa16_DEFINED 1
#define XED_IFORM_BOUND_GPRv_MEMa32_DEFINED 1
#define XED_IFORM_BSF_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BSF_GPRv_MEMv_DEFINED 1
#define XED_IFORM_BSR_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BSR_GPRv_MEMv_DEFINED 1
#define XED_IFORM_BSWAP_GPRv_DEFINED 1
#define XED_IFORM_BT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BT_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BT_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BT_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTC_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BTC_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BTC_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTC_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTR_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BTR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BTR_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTS_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BTS_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BTS_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTS_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_CALL_FAR_MEMp2_DEFINED 1
#define XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED 1
#define XED_IFORM_CALL_NEAR_GPRv_DEFINED 1
#define XED_IFORM_CALL_NEAR_MEMv_DEFINED 1
#define XED_IFORM_CALL_NEAR_RELBRd_DEFINED 1
#define XED_IFORM_CALL_NEAR_RELBRz_DEFINED 1
#define XED_IFORM_CBW_DEFINED 1
#define XED_IFORM_CDQ_DEFINED 1
#define XED_IFORM_CDQE_DEFINED 1
#define XED_IFORM_CLAC_DEFINED 1
#define XED_IFORM_CLC_DEFINED 1
#define XED_IFORM_CLD_DEFINED 1
#define XED_IFORM_CLDEMOTE_MEMu8_DEFINED 1
#define XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED 1
#define XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED 1
#define XED_IFORM_CLGI_DEFINED 1
#define XED_IFORM_CLI_DEFINED 1
#define XED_IFORM_CLRSSBSY_MEMu64_DEFINED 1
#define XED_IFORM_CLTS_DEFINED 1
#define XED_IFORM_CLWB_MEMmprefetch_DEFINED 1
#define XED_IFORM_CLZERO_DEFINED 1
#define XED_IFORM_CMC_DEFINED 1
#define XED_IFORM_CMOVB_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVL_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVL_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVO_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVO_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVP_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVP_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVS_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVS_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMP_AL_IMMb_DEFINED 1
#define XED_IFORM_CMP_GPR8_GPR8_38_DEFINED 1
#define XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED 1
#define XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED 1
#define XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED 1
#define XED_IFORM_CMP_GPR8_MEMb_DEFINED 1
#define XED_IFORM_CMP_GPRv_GPRv_39_DEFINED 1
#define XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED 1
#define XED_IFORM_CMP_GPRv_IMMb_DEFINED 1
#define XED_IFORM_CMP_GPRv_IMMz_DEFINED 1
#define XED_IFORM_CMP_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMP_MEMb_GPR8_DEFINED 1
#define XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED 1
#define XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED 1
#define XED_IFORM_CMP_MEMv_GPRv_DEFINED 1
#define XED_IFORM_CMP_MEMv_IMMb_DEFINED 1
#define XED_IFORM_CMP_MEMv_IMMz_DEFINED 1
#define XED_IFORM_CMP_OrAX_IMMz_DEFINED 1
#define XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED 1
#define XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED 1
#define XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED 1
#define XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_CMPSB_DEFINED 1
#define XED_IFORM_CMPSD_DEFINED 1
#define XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED 1
#define XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED 1
#define XED_IFORM_CMPSQ_DEFINED 1
#define XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED 1
#define XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED 1
#define XED_IFORM_CMPSW_DEFINED 1
#define XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED 1
#define XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED 1
#define XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED 1
#define XED_IFORM_CMPXCHG16B_MEMdq_DEFINED 1
#define XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED 1
#define XED_IFORM_CMPXCHG8B_MEMq_DEFINED 1
#define XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED 1
#define XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_COMISS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_COMISS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_CPUID_DEFINED 1
#define XED_IFORM_CQO_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_GPRv_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_MEMb_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_MEMv_DEFINED 1
#define XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED 1
#define XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED 1
#define XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED 1
#define XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED 1
#define XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED 1
#define XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED 1
#define XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED 1
#define XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED 1
#define XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED 1
#define XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED 1
#define XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED 1
#define XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED 1
#define XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED 1
#define XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED 1
#define XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED 1
#define XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED 1
#define XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED 1
#define XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED 1
#define XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED 1
#define XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED 1
#define XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED 1
#define XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED 1
#define XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED 1
#define XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED 1
#define XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED 1
#define XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED 1
#define XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED 1
#define XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED 1
#define XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED 1
#define XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED 1
#define XED_IFORM_CWD_DEFINED 1
#define XED_IFORM_CWDE_DEFINED 1
#define XED_IFORM_DAA_DEFINED 1
#define XED_IFORM_DAS_DEFINED 1
#define XED_IFORM_DEC_GPR8_DEFINED 1
#define XED_IFORM_DEC_GPRv_48_DEFINED 1
#define XED_IFORM_DEC_GPRv_FFr1_DEFINED 1
#define XED_IFORM_DEC_MEMb_DEFINED 1
#define XED_IFORM_DEC_MEMv_DEFINED 1
#define XED_IFORM_DEC_LOCK_MEMb_DEFINED 1
#define XED_IFORM_DEC_LOCK_MEMv_DEFINED 1
#define XED_IFORM_DIV_GPR8_DEFINED 1
#define XED_IFORM_DIV_GPRv_DEFINED 1
#define XED_IFORM_DIV_MEMb_DEFINED 1
#define XED_IFORM_DIV_MEMv_DEFINED 1
#define XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_DIVPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_DIVPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_DIVSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_DIVSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_EMMS_DEFINED 1
#define XED_IFORM_ENCLS_DEFINED 1
#define XED_IFORM_ENCLU_DEFINED 1
#define XED_IFORM_ENCLV_DEFINED 1
#define XED_IFORM_ENDBR32_DEFINED 1
#define XED_IFORM_ENDBR64_DEFINED 1
#define XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED 1
#define XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED 1
#define XED_IFORM_ENTER_IMMw_IMMb_DEFINED 1
#define XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED 1
#define XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED 1
#define XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED 1
#define XED_IFORM_F2XM1_DEFINED 1
#define XED_IFORM_FABS_DEFINED 1
#define XED_IFORM_FADD_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FADD_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FADD_ST0_X87_DEFINED 1
#define XED_IFORM_FADD_X87_ST0_DEFINED 1
#define XED_IFORM_FADDP_X87_ST0_DEFINED 1
#define XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED 1
#define XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED 1
#define XED_IFORM_FCHS_DEFINED 1
#define XED_IFORM_FCMOVB_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVBE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNB_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNBE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNU_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVU_ST0_X87_DEFINED 1
#define XED_IFORM_FCOM_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FCOM_ST0_X87_DEFINED 1
#define XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED 1
#define XED_IFORM_FCOMI_ST0_X87_DEFINED 1
#define XED_IFORM_FCOMIP_ST0_X87_DEFINED 1
#define XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FCOMP_ST0_X87_DEFINED 1
#define XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED 1
#define XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED 1
#define XED_IFORM_FCOMPP_DEFINED 1
#define XED_IFORM_FCOS_DEFINED 1
#define XED_IFORM_FDECSTP_DEFINED 1
#define XED_IFORM_FDISI8087_NOP_DEFINED 1
#define XED_IFORM_FDIV_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FDIV_ST0_X87_DEFINED 1
#define XED_IFORM_FDIV_X87_ST0_DEFINED 1
#define XED_IFORM_FDIVP_X87_ST0_DEFINED 1
#define XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FDIVR_ST0_X87_DEFINED 1
#define XED_IFORM_FDIVR_X87_ST0_DEFINED 1
#define XED_IFORM_FDIVRP_X87_ST0_DEFINED 1
#define XED_IFORM_FEMMS_DEFINED 1
#define XED_IFORM_FENI8087_NOP_DEFINED 1
#define XED_IFORM_FFREE_X87_DEFINED 1
#define XED_IFORM_FFREEP_X87_DEFINED 1
#define XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FILD_ST0_MEMm64int_DEFINED 1
#define XED_IFORM_FILD_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FILD_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FINCSTP_DEFINED 1
#define XED_IFORM_FIST_MEMmem16int_ST0_DEFINED 1
#define XED_IFORM_FIST_MEMmem32int_ST0_DEFINED 1
#define XED_IFORM_FISTP_MEMm64int_ST0_DEFINED 1
#define XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED 1
#define XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED 1
#define XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED 1
#define XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED 1
#define XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED 1
#define XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FLD_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FLD_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FLD_ST0_MEMmem80real_DEFINED 1
#define XED_IFORM_FLD_ST0_X87_DEFINED 1
#define XED_IFORM_FLD1_DEFINED 1
#define XED_IFORM_FLDCW_MEMmem16_DEFINED 1
#define XED_IFORM_FLDENV_MEMmem14_DEFINED 1
#define XED_IFORM_FLDENV_MEMmem28_DEFINED 1
#define XED_IFORM_FLDL2E_DEFINED 1
#define XED_IFORM_FLDL2T_DEFINED 1
#define XED_IFORM_FLDLG2_DEFINED 1
#define XED_IFORM_FLDLN2_DEFINED 1
#define XED_IFORM_FLDPI_DEFINED 1
#define XED_IFORM_FLDZ_DEFINED 1
#define XED_IFORM_FMUL_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FMUL_ST0_X87_DEFINED 1
#define XED_IFORM_FMUL_X87_ST0_DEFINED 1
#define XED_IFORM_FMULP_X87_ST0_DEFINED 1
#define XED_IFORM_FNCLEX_DEFINED 1
#define XED_IFORM_FNINIT_DEFINED 1
#define XED_IFORM_FNOP_DEFINED 1
#define XED_IFORM_FNSAVE_MEMmem108_DEFINED 1
#define XED_IFORM_FNSAVE_MEMmem94_DEFINED 1
#define XED_IFORM_FNSTCW_MEMmem16_DEFINED 1
#define XED_IFORM_FNSTENV_MEMmem14_DEFINED 1
#define XED_IFORM_FNSTENV_MEMmem28_DEFINED 1
#define XED_IFORM_FNSTSW_AX_DEFINED 1
#define XED_IFORM_FNSTSW_MEMmem16_DEFINED 1
#define XED_IFORM_FPATAN_DEFINED 1
#define XED_IFORM_FPREM_DEFINED 1
#define XED_IFORM_FPREM1_DEFINED 1
#define XED_IFORM_FPTAN_DEFINED 1
#define XED_IFORM_FRNDINT_DEFINED 1
#define XED_IFORM_FRSTOR_MEMmem108_DEFINED 1
#define XED_IFORM_FRSTOR_MEMmem94_DEFINED 1
#define XED_IFORM_FSCALE_DEFINED 1
#define XED_IFORM_FSETPM287_NOP_DEFINED 1
#define XED_IFORM_FSIN_DEFINED 1
#define XED_IFORM_FSINCOS_DEFINED 1
#define XED_IFORM_FSQRT_DEFINED 1
#define XED_IFORM_FST_MEMm64real_ST0_DEFINED 1
#define XED_IFORM_FST_MEMmem32real_ST0_DEFINED 1
#define XED_IFORM_FST_X87_ST0_DEFINED 1
#define XED_IFORM_FSTP_MEMm64real_ST0_DEFINED 1
#define XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED 1
#define XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED 1
#define XED_IFORM_FSTP_X87_ST0_DEFINED 1
#define XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED 1
#define XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED 1
#define XED_IFORM_FSTPNCE_X87_ST0_DEFINED 1
#define XED_IFORM_FSUB_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FSUB_ST0_X87_DEFINED 1
#define XED_IFORM_FSUB_X87_ST0_DEFINED 1
#define XED_IFORM_FSUBP_X87_ST0_DEFINED 1
#define XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FSUBR_ST0_X87_DEFINED 1
#define XED_IFORM_FSUBR_X87_ST0_DEFINED 1
#define XED_IFORM_FSUBRP_X87_ST0_DEFINED 1
#define XED_IFORM_FTST_DEFINED 1
#define XED_IFORM_FUCOM_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMI_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMIP_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMP_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMPP_DEFINED 1
#define XED_IFORM_FWAIT_DEFINED 1
#define XED_IFORM_FXAM_DEFINED 1
#define XED_IFORM_FXCH_ST0_X87_DEFINED 1
#define XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED 1
#define XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED 1
#define XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXTRACT_DEFINED 1
#define XED_IFORM_FYL2X_DEFINED 1
#define XED_IFORM_FYL2XP1_DEFINED 1
#define XED_IFORM_GETSEC_DEFINED 1
#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED 1
#define XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_HADDPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_HADDPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_HLT_DEFINED 1
#define XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_IDIV_GPR8_DEFINED 1
#define XED_IFORM_IDIV_GPRv_DEFINED 1
#define XED_IFORM_IDIV_MEMb_DEFINED 1
#define XED_IFORM_IDIV_MEMv_DEFINED 1
#define XED_IFORM_IMUL_GPR8_DEFINED 1
#define XED_IFORM_IMUL_GPRv_DEFINED 1
#define XED_IFORM_IMUL_GPRv_GPRv_DEFINED 1
#define XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED 1
#define XED_IFORM_IMUL_GPRv_MEMv_DEFINED 1
#define XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED 1
#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED 1
#define XED_IFORM_IMUL_MEMb_DEFINED 1
#define XED_IFORM_IMUL_MEMv_DEFINED 1
#define XED_IFORM_IN_AL_DX_DEFINED 1
#define XED_IFORM_IN_AL_IMMb_DEFINED 1
#define XED_IFORM_IN_OeAX_DX_DEFINED 1
#define XED_IFORM_IN_OeAX_IMMb_DEFINED 1
#define XED_IFORM_INC_GPR8_DEFINED 1
#define XED_IFORM_INC_GPRv_40_DEFINED 1
#define XED_IFORM_INC_GPRv_FFr0_DEFINED 1
#define XED_IFORM_INC_MEMb_DEFINED 1
#define XED_IFORM_INC_MEMv_DEFINED 1
#define XED_IFORM_INCSSPD_GPR32u8_DEFINED 1
#define XED_IFORM_INCSSPQ_GPR64u8_DEFINED 1
#define XED_IFORM_INC_LOCK_MEMb_DEFINED 1
#define XED_IFORM_INC_LOCK_MEMv_DEFINED 1
#define XED_IFORM_INSB_DEFINED 1
#define XED_IFORM_INSD_DEFINED 1
#define XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED 1
#define XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED 1
#define XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED 1
#define XED_IFORM_INSW_DEFINED 1
#define XED_IFORM_INT_IMMb_DEFINED 1
#define XED_IFORM_INT1_DEFINED 1
#define XED_IFORM_INT3_DEFINED 1
#define XED_IFORM_INTO_DEFINED 1
#define XED_IFORM_INVD_DEFINED 1
#define XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED 1
#define XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED 1
#define XED_IFORM_INVLPG_MEMb_DEFINED 1
#define XED_IFORM_INVLPGA_ArAX_ECX_DEFINED 1
#define XED_IFORM_INVLPGB_EAX_EDX_ECX_DEFINED 1
#define XED_IFORM_INVLPGB_RAX_EDX_ECX_DEFINED 1
#define XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED 1
#define XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED 1
#define XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED 1
#define XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED 1
#define XED_IFORM_IRET_DEFINED 1
#define XED_IFORM_IRETD_DEFINED 1
#define XED_IFORM_IRETQ_DEFINED 1
#define XED_IFORM_JB_RELBRb_DEFINED 1
#define XED_IFORM_JB_RELBRd_DEFINED 1
#define XED_IFORM_JB_RELBRz_DEFINED 1
#define XED_IFORM_JBE_RELBRb_DEFINED 1
#define XED_IFORM_JBE_RELBRd_DEFINED 1
#define XED_IFORM_JBE_RELBRz_DEFINED 1
#define XED_IFORM_JCXZ_RELBRb_DEFINED 1
#define XED_IFORM_JECXZ_RELBRb_DEFINED 1
#define XED_IFORM_JL_RELBRb_DEFINED 1
#define XED_IFORM_JL_RELBRd_DEFINED 1
#define XED_IFORM_JL_RELBRz_DEFINED 1
#define XED_IFORM_JLE_RELBRb_DEFINED 1
#define XED_IFORM_JLE_RELBRd_DEFINED 1
#define XED_IFORM_JLE_RELBRz_DEFINED 1
#define XED_IFORM_JMP_GPRv_DEFINED 1
#define XED_IFORM_JMP_MEMv_DEFINED 1
#define XED_IFORM_JMP_RELBRb_DEFINED 1
#define XED_IFORM_JMP_RELBRd_DEFINED 1
#define XED_IFORM_JMP_RELBRz_DEFINED 1
#define XED_IFORM_JMP_FAR_MEMp2_DEFINED 1
#define XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED 1
#define XED_IFORM_JNB_RELBRb_DEFINED 1
#define XED_IFORM_JNB_RELBRd_DEFINED 1
#define XED_IFORM_JNB_RELBRz_DEFINED 1
#define XED_IFORM_JNBE_RELBRb_DEFINED 1
#define XED_IFORM_JNBE_RELBRd_DEFINED 1
#define XED_IFORM_JNBE_RELBRz_DEFINED 1
#define XED_IFORM_JNL_RELBRb_DEFINED 1
#define XED_IFORM_JNL_RELBRd_DEFINED 1
#define XED_IFORM_JNL_RELBRz_DEFINED 1
#define XED_IFORM_JNLE_RELBRb_DEFINED 1
#define XED_IFORM_JNLE_RELBRd_DEFINED 1
#define XED_IFORM_JNLE_RELBRz_DEFINED 1
#define XED_IFORM_JNO_RELBRb_DEFINED 1
#define XED_IFORM_JNO_RELBRd_DEFINED 1
#define XED_IFORM_JNO_RELBRz_DEFINED 1
#define XED_IFORM_JNP_RELBRb_DEFINED 1
#define XED_IFORM_JNP_RELBRd_DEFINED 1
#define XED_IFORM_JNP_RELBRz_DEFINED 1
#define XED_IFORM_JNS_RELBRb_DEFINED 1
#define XED_IFORM_JNS_RELBRd_DEFINED 1
#define XED_IFORM_JNS_RELBRz_DEFINED 1
#define XED_IFORM_JNZ_RELBRb_DEFINED 1
#define XED_IFORM_JNZ_RELBRd_DEFINED 1
#define XED_IFORM_JNZ_RELBRz_DEFINED 1
#define XED_IFORM_JO_RELBRb_DEFINED 1
#define XED_IFORM_JO_RELBRd_DEFINED 1
#define XED_IFORM_JO_RELBRz_DEFINED 1
#define XED_IFORM_JP_RELBRb_DEFINED 1
#define XED_IFORM_JP_RELBRd_DEFINED 1
#define XED_IFORM_JP_RELBRz_DEFINED 1
#define XED_IFORM_JRCXZ_RELBRb_DEFINED 1
#define XED_IFORM_JS_RELBRb_DEFINED 1
#define XED_IFORM_JS_RELBRd_DEFINED 1
#define XED_IFORM_JS_RELBRz_DEFINED 1
#define XED_IFORM_JZ_RELBRb_DEFINED 1
#define XED_IFORM_JZ_RELBRd_DEFINED 1
#define XED_IFORM_JZ_RELBRz_DEFINED 1
#define XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_LAHF_DEFINED 1
#define XED_IFORM_LAR_GPRv_GPRv_DEFINED 1
#define XED_IFORM_LAR_GPRv_MEMw_DEFINED 1
#define XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED 1
#define XED_IFORM_LDMXCSR_MEMd_DEFINED 1
#define XED_IFORM_LDS_GPRz_MEMp_DEFINED 1
#define XED_IFORM_LEA_GPRv_AGEN_DEFINED 1
#define XED_IFORM_LEAVE_DEFINED 1
#define XED_IFORM_LES_GPRz_MEMp_DEFINED 1
#define XED_IFORM_LFENCE_DEFINED 1
#define XED_IFORM_LFS_GPRv_MEMp2_DEFINED 1
#define XED_IFORM_LGDT_MEMs_DEFINED 1
#define XED_IFORM_LGDT_MEMs64_DEFINED 1
#define XED_IFORM_LGS_GPRv_MEMp2_DEFINED 1
#define XED_IFORM_LIDT_MEMs_DEFINED 1
#define XED_IFORM_LIDT_MEMs64_DEFINED 1
#define XED_IFORM_LLDT_GPR16_DEFINED 1
#define XED_IFORM_LLDT_MEMw_DEFINED 1
#define XED_IFORM_LLWPCB_GPRyy_DEFINED 1
#define XED_IFORM_LMSW_GPR16_DEFINED 1
#define XED_IFORM_LMSW_MEMw_DEFINED 1
#define XED_IFORM_LODSB_DEFINED 1
#define XED_IFORM_LODSD_DEFINED 1
#define XED_IFORM_LODSQ_DEFINED 1
#define XED_IFORM_LODSW_DEFINED 1
#define XED_IFORM_LOOP_RELBRb_DEFINED 1
#define XED_IFORM_LOOPE_RELBRb_DEFINED 1
#define XED_IFORM_LOOPNE_RELBRb_DEFINED 1
#define XED_IFORM_LSL_GPRv_GPRz_DEFINED 1
#define XED_IFORM_LSL_GPRv_MEMw_DEFINED 1
#define XED_IFORM_LSS_GPRv_MEMp2_DEFINED 1
#define XED_IFORM_LTR_GPR16_DEFINED 1
#define XED_IFORM_LTR_MEMw_DEFINED 1
#define XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd_DEFINED 1
#define XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd_DEFINED 1
#define XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd_DEFINED 1
#define XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd_DEFINED 1
#define XED_IFORM_LZCNT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_LZCNT_GPRv_MEMv_DEFINED 1
#define XED_IFORM_MASKMOVDQU_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_MAXPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MAXPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_MAXSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_MAXSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_MCOMMIT_DEFINED 1
#define XED_IFORM_MFENCE_DEFINED 1
#define XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_MINPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MINPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_MINSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_MINSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_MONITOR_DEFINED 1
#define XED_IFORM_MONITORX_DEFINED 1
#define XED_IFORM_MOV_AL_MEMb_DEFINED 1
#define XED_IFORM_MOV_GPR8_GPR8_88_DEFINED 1
#define XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED 1
#define XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED 1
#define XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED 1
#define XED_IFORM_MOV_GPR8_MEMb_DEFINED 1
#define XED_IFORM_MOV_GPRv_GPRv_89_DEFINED 1
#define XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED 1
#define XED_IFORM_MOV_GPRv_IMMv_DEFINED 1
#define XED_IFORM_MOV_GPRv_IMMz_DEFINED 1
#define XED_IFORM_MOV_GPRv_MEMv_DEFINED 1
#define XED_IFORM_MOV_GPRv_SEG_DEFINED 1
#define XED_IFORM_MOV_MEMb_AL_DEFINED 1
#define XED_IFORM_MOV_MEMb_GPR8_DEFINED 1
#define XED_IFORM_MOV_MEMb_IMMb_DEFINED 1
#define XED_IFORM_MOV_MEMv_GPRv_DEFINED 1
#define XED_IFORM_MOV_MEMv_IMMz_DEFINED 1
#define XED_IFORM_MOV_MEMv_OrAX_DEFINED 1
#define XED_IFORM_MOV_MEMw_SEG_DEFINED 1
#define XED_IFORM_MOV_OrAX_MEMv_DEFINED 1
#define XED_IFORM_MOV_SEG_GPR16_DEFINED 1
#define XED_IFORM_MOV_SEG_MEMw_DEFINED 1
#define XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED 1
#define XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED 1
#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED 1
#define XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED 1
#define XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED 1
#define XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED 1
#define XED_IFORM_MOVBE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_MOVBE_MEMv_GPRv_DEFINED 1
#define XED_IFORM_MOVD_GPR32_MMXd_DEFINED 1
#define XED_IFORM_MOVD_GPR32_XMMd_DEFINED 1
#define XED_IFORM_MOVD_MEMd_MMXd_DEFINED 1
#define XED_IFORM_MOVD_MEMd_XMMd_DEFINED 1
#define XED_IFORM_MOVD_MMXq_GPR32_DEFINED 1
#define XED_IFORM_MOVD_MMXq_MEMd_DEFINED 1
#define XED_IFORM_MOVD_XMMdq_GPR32_DEFINED 1
#define XED_IFORM_MOVD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED 1
#define XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED 1
#define XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED 1
#define XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED 1
#define XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED 1
#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED 1
#define XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED 1
#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED 1
#define XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED 1
#define XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED 1
#define XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED 1
#define XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED 1
#define XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED 1
#define XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED 1
#define XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED 1
#define XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED 1
#define XED_IFORM_MOVLPS_MEMq_XMMps_DEFINED 1
#define XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED 1
#define XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED 1
#define XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED 1
#define XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED 1
#define XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED 1
#define XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED 1
#define XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED 1
#define XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED 1
#define XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED 1
#define XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED 1
#define XED_IFORM_MOVQ_GPR64_MMXq_DEFINED 1
#define XED_IFORM_MOVQ_GPR64_XMMq_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_GPR64_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED 1
#define XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED 1
#define XED_IFORM_MOVSB_DEFINED 1
#define XED_IFORM_MOVSD_DEFINED 1
#define XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED 1
#define XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED 1
#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED 1
#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED 1
#define XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MOVSQ_DEFINED 1
#define XED_IFORM_MOVSS_MEMss_XMMss_DEFINED 1
#define XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED 1
#define XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED 1
#define XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED 1
#define XED_IFORM_MOVSW_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_GPR16_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_GPR8_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_MEMb_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_MEMw_DEFINED 1
#define XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED 1
#define XED_IFORM_MOVSXD_GPRv_MEMz_DEFINED 1
#define XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED 1
#define XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED 1
#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED 1
#define XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED 1
#define XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED 1
#define XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_GPR16_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_GPR8_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_MEMb_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_MEMw_DEFINED 1
#define XED_IFORM_MOV_CR_CR_GPR32_DEFINED 1
#define XED_IFORM_MOV_CR_CR_GPR64_DEFINED 1
#define XED_IFORM_MOV_CR_GPR32_CR_DEFINED 1
#define XED_IFORM_MOV_CR_GPR64_CR_DEFINED 1
#define XED_IFORM_MOV_DR_DR_GPR32_DEFINED 1
#define XED_IFORM_MOV_DR_DR_GPR64_DEFINED 1
#define XED_IFORM_MOV_DR_GPR32_DR_DEFINED 1
#define XED_IFORM_MOV_DR_GPR64_DR_DEFINED 1
#define XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_MUL_GPR8_DEFINED 1
#define XED_IFORM_MUL_GPRv_DEFINED 1
#define XED_IFORM_MUL_MEMb_DEFINED 1
#define XED_IFORM_MUL_MEMv_DEFINED 1
#define XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_MULPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MULPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_MULSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_MULSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_MWAIT_DEFINED 1
#define XED_IFORM_MWAITX_DEFINED 1
#define XED_IFORM_NEG_GPR8_DEFINED 1
#define XED_IFORM_NEG_GPRv_DEFINED 1
#define XED_IFORM_NEG_MEMb_DEFINED 1
#define XED_IFORM_NEG_MEMv_DEFINED 1
#define XED_IFORM_NEG_LOCK_MEMb_DEFINED 1
#define XED_IFORM_NEG_LOCK_MEMv_DEFINED 1
#define XED_IFORM_NOP_90_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r0_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r1_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r2_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r3_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r4_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r5_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r6_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r7_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1F_DEFINED 1
#define XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED 1
#define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r5_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r6_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r7_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1F_DEFINED 1
#define XED_IFORM_NOT_GPR8_DEFINED 1
#define XED_IFORM_NOT_GPRv_DEFINED 1
#define XED_IFORM_NOT_MEMb_DEFINED 1
#define XED_IFORM_NOT_MEMv_DEFINED 1
#define XED_IFORM_NOT_LOCK_MEMb_DEFINED 1
#define XED_IFORM_NOT_LOCK_MEMv_DEFINED 1
#define XED_IFORM_OR_AL_IMMb_DEFINED 1
#define XED_IFORM_OR_GPR8_GPR8_08_DEFINED 1
#define XED_IFORM_OR_GPR8_GPR8_0A_DEFINED 1
#define XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED 1
#define XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED 1
#define XED_IFORM_OR_GPR8_MEMb_DEFINED 1
#define XED_IFORM_OR_GPRv_GPRv_09_DEFINED 1
#define XED_IFORM_OR_GPRv_GPRv_0B_DEFINED 1
#define XED_IFORM_OR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_OR_GPRv_IMMz_DEFINED 1
#define XED_IFORM_OR_GPRv_MEMv_DEFINED 1
#define XED_IFORM_OR_MEMb_GPR8_DEFINED 1
#define XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED 1
#define XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED 1
#define XED_IFORM_OR_MEMv_GPRv_DEFINED 1
#define XED_IFORM_OR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_OR_MEMv_IMMz_DEFINED 1
#define XED_IFORM_OR_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_OUT_DX_AL_DEFINED 1
#define XED_IFORM_OUT_DX_OeAX_DEFINED 1
#define XED_IFORM_OUT_IMMb_AL_DEFINED 1
#define XED_IFORM_OUT_IMMb_OeAX_DEFINED 1
#define XED_IFORM_OUTSB_DEFINED 1
#define XED_IFORM_OUTSD_DEFINED 1
#define XED_IFORM_OUTSW_DEFINED 1
#define XED_IFORM_PABSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PABSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PABSD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PABSD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PABSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PABSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PAND_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAND_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAND_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PAND_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PANDN_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PANDN_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PAUSE_DEFINED 1
#define XED_IFORM_PAVGB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAVGB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAVGW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAVGW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCONFIG_DEFINED 1
#define XED_IFORM_PCONFIG64_DEFINED 1
#define XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PF2ID_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PF2ID_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PF2IW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PF2IW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFACC_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFACC_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFADD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFADD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFMAX_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFMAX_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFMIN_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFMIN_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFMUL_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFMUL_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFNACC_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFNACC_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRCP_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRCP_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFSUB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFSUB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHADDD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHADDW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHADDW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PI2FD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PI2FD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PI2FW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PI2FW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED 1
#define XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED 1
#define XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED 1
#define XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMINSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINUB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMINUB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED 1
#define XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED 1
#define XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULHW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULLW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULLW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_POP_DS_DEFINED 1
#define XED_IFORM_POP_ES_DEFINED 1
#define XED_IFORM_POP_FS_DEFINED 1
#define XED_IFORM_POP_GPRv_58_DEFINED 1
#define XED_IFORM_POP_GPRv_8F_DEFINED 1
#define XED_IFORM_POP_GS_DEFINED 1
#define XED_IFORM_POP_MEMv_DEFINED 1
#define XED_IFORM_POP_SS_DEFINED 1
#define XED_IFORM_POPA_DEFINED 1
#define XED_IFORM_POPAD_DEFINED 1
#define XED_IFORM_POPCNT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_POPCNT_GPRv_MEMv_DEFINED 1
#define XED_IFORM_POPF_DEFINED 1
#define XED_IFORM_POPFD_DEFINED 1
#define XED_IFORM_POPFQ_DEFINED 1
#define XED_IFORM_POR_MMXq_MEMq_DEFINED 1
#define XED_IFORM_POR_MMXq_MMXq_DEFINED 1
#define XED_IFORM_POR_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_POR_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHW_0F0Dr1_DEFINED 1
#define XED_IFORM_PREFETCHW_0F0Dr3_DEFINED 1
#define XED_IFORM_PREFETCHWT1_MEMu8_DEFINED 1
#define XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED 1
#define XED_IFORM_PSADBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSADBW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSIGND_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSIGND_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSLLD_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSLLD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSLLD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSLLW_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSLLW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSLLW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSMASH_RAX_DEFINED 1
#define XED_IFORM_PSRAD_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRAD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRAD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRAW_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRAW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRAW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRLD_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRLD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRLD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRLW_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRLW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRLW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PTWRITE_GPRy_DEFINED 1
#define XED_IFORM_PTWRITE_MEMy_DEFINED 1
#define XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED 1
#define XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED 1
#define XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUSH_CS_DEFINED 1
#define XED_IFORM_PUSH_DS_DEFINED 1
#define XED_IFORM_PUSH_ES_DEFINED 1
#define XED_IFORM_PUSH_FS_DEFINED 1
#define XED_IFORM_PUSH_GPRv_50_DEFINED 1
#define XED_IFORM_PUSH_GPRv_FFr6_DEFINED 1
#define XED_IFORM_PUSH_GS_DEFINED 1
#define XED_IFORM_PUSH_IMMb_DEFINED 1
#define XED_IFORM_PUSH_IMMz_DEFINED 1
#define XED_IFORM_PUSH_MEMv_DEFINED 1
#define XED_IFORM_PUSH_SS_DEFINED 1
#define XED_IFORM_PUSHA_DEFINED 1
#define XED_IFORM_PUSHAD_DEFINED 1
#define XED_IFORM_PUSHF_DEFINED 1
#define XED_IFORM_PUSHFD_DEFINED 1
#define XED_IFORM_PUSHFQ_DEFINED 1
#define XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED 1
#define XED_IFORM_PXOR_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PXOR_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_RCL_GPR8_CL_DEFINED 1
#define XED_IFORM_RCL_GPR8_IMMb_DEFINED 1
#define XED_IFORM_RCL_GPR8_ONE_DEFINED 1
#define XED_IFORM_RCL_GPRv_CL_DEFINED 1
#define XED_IFORM_RCL_GPRv_IMMb_DEFINED 1
#define XED_IFORM_RCL_GPRv_ONE_DEFINED 1
#define XED_IFORM_RCL_MEMb_CL_DEFINED 1
#define XED_IFORM_RCL_MEMb_IMMb_DEFINED 1
#define XED_IFORM_RCL_MEMb_ONE_DEFINED 1
#define XED_IFORM_RCL_MEMv_CL_DEFINED 1
#define XED_IFORM_RCL_MEMv_IMMb_DEFINED 1
#define XED_IFORM_RCL_MEMv_ONE_DEFINED 1
#define XED_IFORM_RCPPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_RCPPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_RCPSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_RCPSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_RCR_GPR8_CL_DEFINED 1
#define XED_IFORM_RCR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_RCR_GPR8_ONE_DEFINED 1
#define XED_IFORM_RCR_GPRv_CL_DEFINED 1
#define XED_IFORM_RCR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_RCR_GPRv_ONE_DEFINED 1
#define XED_IFORM_RCR_MEMb_CL_DEFINED 1
#define XED_IFORM_RCR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_RCR_MEMb_ONE_DEFINED 1
#define XED_IFORM_RCR_MEMv_CL_DEFINED 1
#define XED_IFORM_RCR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_RCR_MEMv_ONE_DEFINED 1
#define XED_IFORM_RDFSBASE_GPRy_DEFINED 1
#define XED_IFORM_RDGSBASE_GPRy_DEFINED 1
#define XED_IFORM_RDMSR_DEFINED 1
#define XED_IFORM_RDPID_GPR32u32_DEFINED 1
#define XED_IFORM_RDPID_GPR64u64_DEFINED 1
#define XED_IFORM_RDPKRU_DEFINED 1
#define XED_IFORM_RDPMC_DEFINED 1
#define XED_IFORM_RDPRU_DEFINED 1
#define XED_IFORM_RDRAND_GPRv_DEFINED 1
#define XED_IFORM_RDSEED_GPRv_DEFINED 1
#define XED_IFORM_RDSSPD_GPR32u32_DEFINED 1
#define XED_IFORM_RDSSPQ_GPR64u64_DEFINED 1
#define XED_IFORM_RDTSC_DEFINED 1
#define XED_IFORM_RDTSCP_DEFINED 1
#define XED_IFORM_REPE_CMPSB_DEFINED 1
#define XED_IFORM_REPE_CMPSD_DEFINED 1
#define XED_IFORM_REPE_CMPSQ_DEFINED 1
#define XED_IFORM_REPE_CMPSW_DEFINED 1
#define XED_IFORM_REPE_SCASB_DEFINED 1
#define XED_IFORM_REPE_SCASD_DEFINED 1
#define XED_IFORM_REPE_SCASQ_DEFINED 1
#define XED_IFORM_REPE_SCASW_DEFINED 1
#define XED_IFORM_REPNE_CMPSB_DEFINED 1
#define XED_IFORM_REPNE_CMPSD_DEFINED 1
#define XED_IFORM_REPNE_CMPSQ_DEFINED 1
#define XED_IFORM_REPNE_CMPSW_DEFINED 1
#define XED_IFORM_REPNE_SCASB_DEFINED 1
#define XED_IFORM_REPNE_SCASD_DEFINED 1
#define XED_IFORM_REPNE_SCASQ_DEFINED 1
#define XED_IFORM_REPNE_SCASW_DEFINED 1
#define XED_IFORM_REP_INSB_DEFINED 1
#define XED_IFORM_REP_INSD_DEFINED 1
#define XED_IFORM_REP_INSW_DEFINED 1
#define XED_IFORM_REP_LODSB_DEFINED 1
#define XED_IFORM_REP_LODSD_DEFINED 1
#define XED_IFORM_REP_LODSQ_DEFINED 1
#define XED_IFORM_REP_LODSW_DEFINED 1
#define XED_IFORM_REP_MONTMUL_DEFINED 1
#define XED_IFORM_REP_MOVSB_DEFINED 1
#define XED_IFORM_REP_MOVSD_DEFINED 1
#define XED_IFORM_REP_MOVSQ_DEFINED 1
#define XED_IFORM_REP_MOVSW_DEFINED 1
#define XED_IFORM_REP_OUTSB_DEFINED 1
#define XED_IFORM_REP_OUTSD_DEFINED 1
#define XED_IFORM_REP_OUTSW_DEFINED 1
#define XED_IFORM_REP_STOSB_DEFINED 1
#define XED_IFORM_REP_STOSD_DEFINED 1
#define XED_IFORM_REP_STOSQ_DEFINED 1
#define XED_IFORM_REP_STOSW_DEFINED 1
#define XED_IFORM_REP_XCRYPTCBC_DEFINED 1
#define XED_IFORM_REP_XCRYPTCFB_DEFINED 1
#define XED_IFORM_REP_XCRYPTCTR_DEFINED 1
#define XED_IFORM_REP_XCRYPTECB_DEFINED 1
#define XED_IFORM_REP_XCRYPTOFB_DEFINED 1
#define XED_IFORM_REP_XSHA1_DEFINED 1
#define XED_IFORM_REP_XSHA256_DEFINED 1
#define XED_IFORM_REP_XSTORE_DEFINED 1
#define XED_IFORM_RET_FAR_DEFINED 1
#define XED_IFORM_RET_FAR_IMMw_DEFINED 1
#define XED_IFORM_RET_NEAR_DEFINED 1
#define XED_IFORM_RET_NEAR_IMMw_DEFINED 1
#define XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED 1
#define XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED 1
#define XED_IFORM_ROL_GPR8_CL_DEFINED 1
#define XED_IFORM_ROL_GPR8_IMMb_DEFINED 1
#define XED_IFORM_ROL_GPR8_ONE_DEFINED 1
#define XED_IFORM_ROL_GPRv_CL_DEFINED 1
#define XED_IFORM_ROL_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ROL_GPRv_ONE_DEFINED 1
#define XED_IFORM_ROL_MEMb_CL_DEFINED 1
#define XED_IFORM_ROL_MEMb_IMMb_DEFINED 1
#define XED_IFORM_ROL_MEMb_ONE_DEFINED 1
#define XED_IFORM_ROL_MEMv_CL_DEFINED 1
#define XED_IFORM_ROL_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ROL_MEMv_ONE_DEFINED 1
#define XED_IFORM_ROR_GPR8_CL_DEFINED 1
#define XED_IFORM_ROR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_ROR_GPR8_ONE_DEFINED 1
#define XED_IFORM_ROR_GPRv_CL_DEFINED 1
#define XED_IFORM_ROR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ROR_GPRv_ONE_DEFINED 1
#define XED_IFORM_ROR_MEMb_CL_DEFINED 1
#define XED_IFORM_ROR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_ROR_MEMb_ONE_DEFINED 1
#define XED_IFORM_ROR_MEMv_CL_DEFINED 1
#define XED_IFORM_ROR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ROR_MEMv_ONE_DEFINED 1
#define XED_IFORM_RORX_VGPR32d_MEMd_IMMb_DEFINED 1
#define XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb_DEFINED 1
#define XED_IFORM_RORX_VGPR64q_MEMq_IMMb_DEFINED 1
#define XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED 1
#define XED_IFORM_RSM_DEFINED 1
#define XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_RSTORSSP_MEMu64_DEFINED 1
#define XED_IFORM_SAHF_DEFINED 1
#define XED_IFORM_SALC_DEFINED 1
#define XED_IFORM_SAR_GPR8_CL_DEFINED 1
#define XED_IFORM_SAR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_SAR_GPR8_ONE_DEFINED 1
#define XED_IFORM_SAR_GPRv_CL_DEFINED 1
#define XED_IFORM_SAR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SAR_GPRv_ONE_DEFINED 1
#define XED_IFORM_SAR_MEMb_CL_DEFINED 1
#define XED_IFORM_SAR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_SAR_MEMb_ONE_DEFINED 1
#define XED_IFORM_SAR_MEMv_CL_DEFINED 1
#define XED_IFORM_SAR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SAR_MEMv_ONE_DEFINED 1
#define XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_SAVEPREVSSP_DEFINED 1
#define XED_IFORM_SBB_AL_IMMb_DEFINED 1
#define XED_IFORM_SBB_GPR8_GPR8_18_DEFINED 1
#define XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED 1
#define XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED 1
#define XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED 1
#define XED_IFORM_SBB_GPR8_MEMb_DEFINED 1
#define XED_IFORM_SBB_GPRv_GPRv_19_DEFINED 1
#define XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED 1
#define XED_IFORM_SBB_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SBB_GPRv_IMMz_DEFINED 1
#define XED_IFORM_SBB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_SBB_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED 1
#define XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED 1
#define XED_IFORM_SBB_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SBB_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SBB_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SBB_OrAX_IMMz_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SCASB_DEFINED 1
#define XED_IFORM_SCASD_DEFINED 1
#define XED_IFORM_SCASQ_DEFINED 1
#define XED_IFORM_SCASW_DEFINED 1
#define XED_IFORM_SERIALIZE_DEFINED 1
#define XED_IFORM_SETB_GPR8_DEFINED 1
#define XED_IFORM_SETB_MEMb_DEFINED 1
#define XED_IFORM_SETBE_GPR8_DEFINED 1
#define XED_IFORM_SETBE_MEMb_DEFINED 1
#define XED_IFORM_SETL_GPR8_DEFINED 1
#define XED_IFORM_SETL_MEMb_DEFINED 1
#define XED_IFORM_SETLE_GPR8_DEFINED 1
#define XED_IFORM_SETLE_MEMb_DEFINED 1
#define XED_IFORM_SETNB_GPR8_DEFINED 1
#define XED_IFORM_SETNB_MEMb_DEFINED 1
#define XED_IFORM_SETNBE_GPR8_DEFINED 1
#define XED_IFORM_SETNBE_MEMb_DEFINED 1
#define XED_IFORM_SETNL_GPR8_DEFINED 1
#define XED_IFORM_SETNL_MEMb_DEFINED 1
#define XED_IFORM_SETNLE_GPR8_DEFINED 1
#define XED_IFORM_SETNLE_MEMb_DEFINED 1
#define XED_IFORM_SETNO_GPR8_DEFINED 1
#define XED_IFORM_SETNO_MEMb_DEFINED 1
#define XED_IFORM_SETNP_GPR8_DEFINED 1
#define XED_IFORM_SETNP_MEMb_DEFINED 1
#define XED_IFORM_SETNS_GPR8_DEFINED 1
#define XED_IFORM_SETNS_MEMb_DEFINED 1
#define XED_IFORM_SETNZ_GPR8_DEFINED 1
#define XED_IFORM_SETNZ_MEMb_DEFINED 1
#define XED_IFORM_SETO_GPR8_DEFINED 1
#define XED_IFORM_SETO_MEMb_DEFINED 1
#define XED_IFORM_SETP_GPR8_DEFINED 1
#define XED_IFORM_SETP_MEMb_DEFINED 1
#define XED_IFORM_SETS_GPR8_DEFINED 1
#define XED_IFORM_SETS_MEMb_DEFINED 1
#define XED_IFORM_SETSSBSY_DEFINED 1
#define XED_IFORM_SETZ_GPR8_DEFINED 1
#define XED_IFORM_SETZ_MEMb_DEFINED 1
#define XED_IFORM_SFENCE_DEFINED 1
#define XED_IFORM_SGDT_MEMs_DEFINED 1
#define XED_IFORM_SGDT_MEMs64_DEFINED 1
#define XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED 1
#define XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED 1
#define XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED 1
#define XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED 1
#define XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED 1
#define XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED 1
#define XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED 1
#define XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED 1
#define XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED 1
#define XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED 1
#define XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED 1
#define XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED 1
#define XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED 1
#define XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED 1
#define XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED 1
#define XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED 1
#define XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED 1
#define XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED 1
#define XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED 1
#define XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED 1
#define XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED 1
#define XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED 1
#define XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED 1
#define XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED 1
#define XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED 1
#define XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_SHR_GPR8_CL_DEFINED 1
#define XED_IFORM_SHR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_SHR_GPR8_ONE_DEFINED 1
#define XED_IFORM_SHR_GPRv_CL_DEFINED 1
#define XED_IFORM_SHR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHR_GPRv_ONE_DEFINED 1
#define XED_IFORM_SHR_MEMb_CL_DEFINED 1
#define XED_IFORM_SHR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_SHR_MEMb_ONE_DEFINED 1
#define XED_IFORM_SHR_MEMv_CL_DEFINED 1
#define XED_IFORM_SHR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SHR_MEMv_ONE_DEFINED 1
#define XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED 1
#define XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED 1
#define XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED 1
#define XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_SIDT_MEMs_DEFINED 1
#define XED_IFORM_SIDT_MEMs64_DEFINED 1
#define XED_IFORM_SKINIT_EAX_DEFINED 1
#define XED_IFORM_SLDT_GPRv_DEFINED 1
#define XED_IFORM_SLDT_MEMw_DEFINED 1
#define XED_IFORM_SLWPCB_GPRyy_DEFINED 1
#define XED_IFORM_SMSW_GPRv_DEFINED 1
#define XED_IFORM_SMSW_MEMw_DEFINED 1
#define XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_STAC_DEFINED 1
#define XED_IFORM_STC_DEFINED 1
#define XED_IFORM_STD_DEFINED 1
#define XED_IFORM_STGI_DEFINED 1
#define XED_IFORM_STI_DEFINED 1
#define XED_IFORM_STMXCSR_MEMd_DEFINED 1
#define XED_IFORM_STOSB_DEFINED 1
#define XED_IFORM_STOSD_DEFINED 1
#define XED_IFORM_STOSQ_DEFINED 1
#define XED_IFORM_STOSW_DEFINED 1
#define XED_IFORM_STR_GPRv_DEFINED 1
#define XED_IFORM_STR_MEMw_DEFINED 1
#define XED_IFORM_SUB_AL_IMMb_DEFINED 1
#define XED_IFORM_SUB_GPR8_GPR8_28_DEFINED 1
#define XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED 1
#define XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED 1
#define XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED 1
#define XED_IFORM_SUB_GPR8_MEMb_DEFINED 1
#define XED_IFORM_SUB_GPRv_GPRv_29_DEFINED 1
#define XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED 1
#define XED_IFORM_SUB_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SUB_GPRv_IMMz_DEFINED 1
#define XED_IFORM_SUB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_SUB_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED 1
#define XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED 1
#define XED_IFORM_SUB_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SUB_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SUB_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SUB_OrAX_IMMz_DEFINED 1
#define XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_SUBPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_SUBPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_SUBSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_SUBSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SWAPGS_DEFINED 1
#define XED_IFORM_SYSCALL_DEFINED 1
#define XED_IFORM_SYSCALL_AMD_DEFINED 1
#define XED_IFORM_SYSENTER_DEFINED 1
#define XED_IFORM_SYSEXIT_DEFINED 1
#define XED_IFORM_SYSRET_DEFINED 1
#define XED_IFORM_SYSRET64_DEFINED 1
#define XED_IFORM_SYSRET_AMD_DEFINED 1
#define XED_IFORM_T1MSKC_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_T1MSKC_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_T1MSKC_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_T1MSKC_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_TEST_AL_IMMb_DEFINED 1
#define XED_IFORM_TEST_GPR8_GPR8_DEFINED 1
#define XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED 1
#define XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED 1
#define XED_IFORM_TEST_GPRv_GPRv_DEFINED 1
#define XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED 1
#define XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED 1
#define XED_IFORM_TEST_MEMb_GPR8_DEFINED 1
#define XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED 1
#define XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED 1
#define XED_IFORM_TEST_MEMv_GPRv_DEFINED 1
#define XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED 1
#define XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED 1
#define XED_IFORM_TEST_OrAX_IMMz_DEFINED 1
#define XED_IFORM_TLBSYNC_DEFINED 1
#define XED_IFORM_TPAUSE_GPR32u32_DEFINED 1
#define XED_IFORM_TPAUSE_GPR64u64_DEFINED 1
#define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_TZCNT_GPRv_MEMv_DEFINED 1
#define XED_IFORM_TZMSK_VGPR32d_GPR32d_DEFINED 1
#define XED_IFORM_TZMSK_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_TZMSK_VGPRyy_GPRyy_DEFINED 1
#define XED_IFORM_TZMSK_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_UD0_GPR32_GPR32_DEFINED 1
#define XED_IFORM_UD0_GPR32_MEMd_DEFINED 1
#define XED_IFORM_UD1_GPR32_GPR32_DEFINED 1
#define XED_IFORM_UD1_GPR32_MEMd_DEFINED 1
#define XED_IFORM_UD2_DEFINED 1
#define XED_IFORM_UMONITOR_GPRa_DEFINED 1
#define XED_IFORM_UMWAIT_GPR32_DEFINED 1
#define XED_IFORM_UMWAIT_GPR64_DEFINED 1
#define XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED 1
#define XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED 1
#define XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1
#define XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VERR_GPR16_DEFINED 1
#define XED_IFORM_VERR_MEMw_DEFINED 1
#define XED_IFORM_VERW_GPR16_DEFINED 1
#define XED_IFORM_VERW_MEMw_DEFINED 1
#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VLDMXCSR_MEMd_DEFINED 1
#define XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMCALL_DEFINED 1
#define XED_IFORM_VMCLEAR_MEMq_DEFINED 1
#define XED_IFORM_VMFUNC_DEFINED 1
#define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMLAUNCH_DEFINED 1
#define XED_IFORM_VMLOAD_ArAX_DEFINED 1
#define XED_IFORM_VMMCALL_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED 1
#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED 1
#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED 1
#define XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED 1
#define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED 1
#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED 1
#define XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED 1
#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED 1
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED 1
#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED 1
#define XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED 1
#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED 1
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED 1
#define XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED 1
#define XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED 1
#define XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED 1
#define XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED 1
#define XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED 1
#define XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED 1
#define XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED 1
#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED 1
#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED 1
#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED 1
#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED 1
#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED 1
#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VMPTRLD_MEMq_DEFINED 1
#define XED_IFORM_VMPTRST_MEMq_DEFINED 1
#define XED_IFORM_VMREAD_GPR32_GPR32_DEFINED 1
#define XED_IFORM_VMREAD_GPR64_GPR64_DEFINED 1
#define XED_IFORM_VMREAD_MEMd_GPR32_DEFINED 1
#define XED_IFORM_VMREAD_MEMq_GPR64_DEFINED 1
#define XED_IFORM_VMRESUME_DEFINED 1
#define XED_IFORM_VMRUN_ArAX_DEFINED 1
#define XED_IFORM_VMSAVE_DEFINED 1
#define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED 1
#define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED 1
#define XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED 1
#define XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED 1
#define XED_IFORM_VMXOFF_DEFINED 1
#define XED_IFORM_VMXON_MEMq_DEFINED 1
#define XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED 1
#define XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED 1
#define XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED 1
#define XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED 1
#define XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1
#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSTMXCSR_MEMd_DEFINED 1
#define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VZEROALL_DEFINED 1
#define XED_IFORM_VZEROUPPER_DEFINED 1
#define XED_IFORM_WBINVD_DEFINED 1
#define XED_IFORM_WBNOINVD_DEFINED 1
#define XED_IFORM_WRFSBASE_GPRy_DEFINED 1
#define XED_IFORM_WRGSBASE_GPRy_DEFINED 1
#define XED_IFORM_WRMSR_DEFINED 1
#define XED_IFORM_WRPKRU_DEFINED 1
#define XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED 1
#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED 1
#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED 1
#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED 1
#define XED_IFORM_XABORT_IMMb_DEFINED 1
#define XED_IFORM_XADD_GPR8_GPR8_DEFINED 1
#define XED_IFORM_XADD_GPRv_GPRv_DEFINED 1
#define XED_IFORM_XADD_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XADD_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XBEGIN_RELBRz_DEFINED 1
#define XED_IFORM_XCHG_GPR8_GPR8_DEFINED 1
#define XED_IFORM_XCHG_GPRv_GPRv_DEFINED 1
#define XED_IFORM_XCHG_GPRv_OrAX_DEFINED 1
#define XED_IFORM_XCHG_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XCHG_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XEND_DEFINED 1
#define XED_IFORM_XGETBV_DEFINED 1
#define XED_IFORM_XLAT_DEFINED 1
#define XED_IFORM_XOR_AL_IMMb_DEFINED 1
#define XED_IFORM_XOR_GPR8_GPR8_30_DEFINED 1
#define XED_IFORM_XOR_GPR8_GPR8_32_DEFINED 1
#define XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED 1
#define XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED 1
#define XED_IFORM_XOR_GPR8_MEMb_DEFINED 1
#define XED_IFORM_XOR_GPRv_GPRv_31_DEFINED 1
#define XED_IFORM_XOR_GPRv_GPRv_33_DEFINED 1
#define XED_IFORM_XOR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_XOR_GPRv_IMMz_DEFINED 1
#define XED_IFORM_XOR_GPRv_MEMv_DEFINED 1
#define XED_IFORM_XOR_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED 1
#define XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED 1
#define XED_IFORM_XOR_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XOR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_XOR_MEMv_IMMz_DEFINED 1
#define XED_IFORM_XOR_OrAX_IMMz_DEFINED 1
#define XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_XRESLDTRK_DEFINED 1
#define XED_IFORM_XRSTOR_MEMmxsave_DEFINED 1
#define XED_IFORM_XRSTOR64_MEMmxsave_DEFINED 1
#define XED_IFORM_XRSTORS_MEMmxsave_DEFINED 1
#define XED_IFORM_XRSTORS64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVE_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVE64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEC_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEC64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVES_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVES64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSETBV_DEFINED 1
#define XED_IFORM_XSTORE_DEFINED 1
#define XED_IFORM_XSUSLDTRK_DEFINED 1
#define XED_IFORM_XTEST_DEFINED 1
#define XED_IFORM_LAST_DEFINED 1
typedef enum {
  XED_IFORM_INVALID=0, 
  XED_IFORM_AAA=1, 
  XED_IFORM_AAD_IMMb=2, 
  XED_IFORM_AAM_IMMb=3, 
  XED_IFORM_AAS=4, 
  XED_IFORM_ADC_AL_IMMb=5, 
  XED_IFORM_ADC_GPR8_GPR8_10=6, 
  XED_IFORM_ADC_GPR8_GPR8_12=7, 
  XED_IFORM_ADC_GPR8_IMMb_80r2=8, 
  XED_IFORM_ADC_GPR8_IMMb_82r2=9, 
  XED_IFORM_ADC_GPR8_MEMb=10, 
  XED_IFORM_ADC_GPRv_GPRv_11=11, 
  XED_IFORM_ADC_GPRv_GPRv_13=12, 
  XED_IFORM_ADC_GPRv_IMMb=13, 
  XED_IFORM_ADC_GPRv_IMMz=14, 
  XED_IFORM_ADC_GPRv_MEMv=15, 
  XED_IFORM_ADC_MEMb_GPR8=16, 
  XED_IFORM_ADC_MEMb_IMMb_80r2=17, 
  XED_IFORM_ADC_MEMb_IMMb_82r2=18, 
  XED_IFORM_ADC_MEMv_GPRv=19, 
  XED_IFORM_ADC_MEMv_IMMb=20, 
  XED_IFORM_ADC_MEMv_IMMz=21, 
  XED_IFORM_ADC_OrAX_IMMz=22, 
  XED_IFORM_ADCX_GPR32d_GPR32d=23, 
  XED_IFORM_ADCX_GPR32d_MEMd=24, 
  XED_IFORM_ADCX_GPR64q_GPR64q=25, 
  XED_IFORM_ADCX_GPR64q_MEMq=26, 
  XED_IFORM_ADC_LOCK_MEMb_GPR8=27, 
  XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2=28, 
  XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2=29, 
  XED_IFORM_ADC_LOCK_MEMv_GPRv=30, 
  XED_IFORM_ADC_LOCK_MEMv_IMMb=31, 
  XED_IFORM_ADC_LOCK_MEMv_IMMz=32, 
  XED_IFORM_ADD_AL_IMMb=33, 
  XED_IFORM_ADD_GPR8_GPR8_00=34, 
  XED_IFORM_ADD_GPR8_GPR8_02=35, 
  XED_IFORM_ADD_GPR8_IMMb_80r0=36, 
  XED_IFORM_ADD_GPR8_IMMb_82r0=37, 
  XED_IFORM_ADD_GPR8_MEMb=38, 
  XED_IFORM_ADD_GPRv_GPRv_01=39, 
  XED_IFORM_ADD_GPRv_GPRv_03=40, 
  XED_IFORM_ADD_GPRv_IMMb=41, 
  XED_IFORM_ADD_GPRv_IMMz=42, 
  XED_IFORM_ADD_GPRv_MEMv=43, 
  XED_IFORM_ADD_MEMb_GPR8=44, 
  XED_IFORM_ADD_MEMb_IMMb_80r0=45, 
  XED_IFORM_ADD_MEMb_IMMb_82r0=46, 
  XED_IFORM_ADD_MEMv_GPRv=47, 
  XED_IFORM_ADD_MEMv_IMMb=48, 
  XED_IFORM_ADD_MEMv_IMMz=49, 
  XED_IFORM_ADD_OrAX_IMMz=50, 
  XED_IFORM_ADDPD_XMMpd_MEMpd=51, 
  XED_IFORM_ADDPD_XMMpd_XMMpd=52, 
  XED_IFORM_ADDPS_XMMps_MEMps=53, 
  XED_IFORM_ADDPS_XMMps_XMMps=54, 
  XED_IFORM_ADDSD_XMMsd_MEMsd=55, 
  XED_IFORM_ADDSD_XMMsd_XMMsd=56, 
  XED_IFORM_ADDSS_XMMss_MEMss=57, 
  XED_IFORM_ADDSS_XMMss_XMMss=58, 
  XED_IFORM_ADDSUBPD_XMMpd_MEMpd=59, 
  XED_IFORM_ADDSUBPD_XMMpd_XMMpd=60, 
  XED_IFORM_ADDSUBPS_XMMps_MEMps=61, 
  XED_IFORM_ADDSUBPS_XMMps_XMMps=62, 
  XED_IFORM_ADD_LOCK_MEMb_GPR8=63, 
  XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0=64, 
  XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0=65, 
  XED_IFORM_ADD_LOCK_MEMv_GPRv=66, 
  XED_IFORM_ADD_LOCK_MEMv_IMMb=67, 
  XED_IFORM_ADD_LOCK_MEMv_IMMz=68, 
  XED_IFORM_ADOX_GPR32d_GPR32d=69, 
  XED_IFORM_ADOX_GPR32d_MEMd=70, 
  XED_IFORM_ADOX_GPR64q_GPR64q=71, 
  XED_IFORM_ADOX_GPR64q_MEMq=72, 
  XED_IFORM_AESDEC_XMMdq_MEMdq=73, 
  XED_IFORM_AESDEC_XMMdq_XMMdq=74, 
  XED_IFORM_AESDECLAST_XMMdq_MEMdq=75, 
  XED_IFORM_AESDECLAST_XMMdq_XMMdq=76, 
  XED_IFORM_AESENC_XMMdq_MEMdq=77, 
  XED_IFORM_AESENC_XMMdq_XMMdq=78, 
  XED_IFORM_AESENCLAST_XMMdq_MEMdq=79, 
  XED_IFORM_AESENCLAST_XMMdq_XMMdq=80, 
  XED_IFORM_AESIMC_XMMdq_MEMdq=81, 
  XED_IFORM_AESIMC_XMMdq_XMMdq=82, 
  XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb=83, 
  XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb=84, 
  XED_IFORM_AND_AL_IMMb=85, 
  XED_IFORM_AND_GPR8_GPR8_20=86, 
  XED_IFORM_AND_GPR8_GPR8_22=87, 
  XED_IFORM_AND_GPR8_IMMb_80r4=88, 
  XED_IFORM_AND_GPR8_IMMb_82r4=89, 
  XED_IFORM_AND_GPR8_MEMb=90, 
  XED_IFORM_AND_GPRv_GPRv_21=91, 
  XED_IFORM_AND_GPRv_GPRv_23=92, 
  XED_IFORM_AND_GPRv_IMMb=93, 
  XED_IFORM_AND_GPRv_IMMz=94, 
  XED_IFORM_AND_GPRv_MEMv=95, 
  XED_IFORM_AND_MEMb_GPR8=96, 
  XED_IFORM_AND_MEMb_IMMb_80r4=97, 
  XED_IFORM_AND_MEMb_IMMb_82r4=98, 
  XED_IFORM_AND_MEMv_GPRv=99, 
  XED_IFORM_AND_MEMv_IMMb=100, 
  XED_IFORM_AND_MEMv_IMMz=101, 
  XED_IFORM_AND_OrAX_IMMz=102, 
  XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd=103, 
  XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d=104, 
  XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq=105, 
  XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q=106, 
  XED_IFORM_ANDNPD_XMMxuq_MEMxuq=107, 
  XED_IFORM_ANDNPD_XMMxuq_XMMxuq=108, 
  XED_IFORM_ANDNPS_XMMxud_MEMxud=109, 
  XED_IFORM_ANDNPS_XMMxud_XMMxud=110, 
  XED_IFORM_ANDPD_XMMxuq_MEMxuq=111, 
  XED_IFORM_ANDPD_XMMxuq_XMMxuq=112, 
  XED_IFORM_ANDPS_XMMxud_MEMxud=113, 
  XED_IFORM_ANDPS_XMMxud_XMMxud=114, 
  XED_IFORM_AND_LOCK_MEMb_GPR8=115, 
  XED_IFORM_AND_LOCK_MEMb_IMMb_80r4=116, 
  XED_IFORM_AND_LOCK_MEMb_IMMb_82r4=117, 
  XED_IFORM_AND_LOCK_MEMv_GPRv=118, 
  XED_IFORM_AND_LOCK_MEMv_IMMb=119, 
  XED_IFORM_AND_LOCK_MEMv_IMMz=120, 
  XED_IFORM_ARPL_GPR16_GPR16=121, 
  XED_IFORM_ARPL_MEMw_GPR16=122, 
  XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d=123, 
  XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d=124, 
  XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q=125, 
  XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q=126, 
  XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd=127, 
  XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd=128, 
  XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd=129, 
  XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd=130, 
  XED_IFORM_BLCFILL_VGPR32d_GPR32d=131, 
  XED_IFORM_BLCFILL_VGPR32d_MEMd=132, 
  XED_IFORM_BLCFILL_VGPRyy_GPRyy=133, 
  XED_IFORM_BLCFILL_VGPRyy_MEMy=134, 
  XED_IFORM_BLCI_VGPR32d_GPR32d=135, 
  XED_IFORM_BLCI_VGPR32d_MEMd=136, 
  XED_IFORM_BLCI_VGPRyy_GPRyy=137, 
  XED_IFORM_BLCI_VGPRyy_MEMy=138, 
  XED_IFORM_BLCIC_VGPR32d_GPR32d=139, 
  XED_IFORM_BLCIC_VGPR32d_MEMd=140, 
  XED_IFORM_BLCIC_VGPRyy_GPRyy=141, 
  XED_IFORM_BLCIC_VGPRyy_MEMy=142, 
  XED_IFORM_BLCMSK_VGPR32d_GPR32d=143, 
  XED_IFORM_BLCMSK_VGPR32d_MEMd=144, 
  XED_IFORM_BLCMSK_VGPRyy_GPRyy=145, 
  XED_IFORM_BLCMSK_VGPRyy_MEMy=146, 
  XED_IFORM_BLCS_VGPR32d_GPR32d=147, 
  XED_IFORM_BLCS_VGPR32d_MEMd=148, 
  XED_IFORM_BLCS_VGPRyy_GPRyy=149, 
  XED_IFORM_BLCS_VGPRyy_MEMy=150, 
  XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb=151, 
  XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb=152, 
  XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb=153, 
  XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb=154, 
  XED_IFORM_BLENDVPD_XMMdq_MEMdq=155, 
  XED_IFORM_BLENDVPD_XMMdq_XMMdq=156, 
  XED_IFORM_BLENDVPS_XMMdq_MEMdq=157, 
  XED_IFORM_BLENDVPS_XMMdq_XMMdq=158, 
  XED_IFORM_BLSFILL_VGPR32d_GPR32d=159, 
  XED_IFORM_BLSFILL_VGPR32d_MEMd=160, 
  XED_IFORM_BLSFILL_VGPRyy_GPRyy=161, 
  XED_IFORM_BLSFILL_VGPRyy_MEMy=162, 
  XED_IFORM_BLSI_VGPR32d_MEMd=163, 
  XED_IFORM_BLSI_VGPR32d_VGPR32d=164, 
  XED_IFORM_BLSI_VGPR64q_MEMq=165, 
  XED_IFORM_BLSI_VGPR64q_VGPR64q=166, 
  XED_IFORM_BLSIC_VGPR32d_GPR32d=167, 
  XED_IFORM_BLSIC_VGPR32d_MEMd=168, 
  XED_IFORM_BLSIC_VGPRyy_GPRyy=169, 
  XED_IFORM_BLSIC_VGPRyy_MEMy=170, 
  XED_IFORM_BLSMSK_VGPR32d_MEMd=171, 
  XED_IFORM_BLSMSK_VGPR32d_VGPR32d=172, 
  XED_IFORM_BLSMSK_VGPR64q_MEMq=173, 
  XED_IFORM_BLSMSK_VGPR64q_VGPR64q=174, 
  XED_IFORM_BLSR_VGPR32d_MEMd=175, 
  XED_IFORM_BLSR_VGPR32d_VGPR32d=176, 
  XED_IFORM_BLSR_VGPR64q_MEMq=177, 
  XED_IFORM_BLSR_VGPR64q_VGPR64q=178, 
  XED_IFORM_BNDCL_BND_AGEN=179, 
  XED_IFORM_BNDCL_BND_GPR32=180, 
  XED_IFORM_BNDCL_BND_GPR64=181, 
  XED_IFORM_BNDCN_BND_AGEN=182, 
  XED_IFORM_BNDCN_BND_GPR32=183, 
  XED_IFORM_BNDCN_BND_GPR64=184, 
  XED_IFORM_BNDCU_BND_AGEN=185, 
  XED_IFORM_BNDCU_BND_GPR32=186, 
  XED_IFORM_BNDCU_BND_GPR64=187, 
  XED_IFORM_BNDLDX_BND_MEMbnd32=188, 
  XED_IFORM_BNDLDX_BND_MEMbnd64=189, 
  XED_IFORM_BNDMK_BND_AGEN=190, 
  XED_IFORM_BNDMOV_BND_BND=191, 
  XED_IFORM_BNDMOV_BND_MEMdq=192, 
  XED_IFORM_BNDMOV_BND_MEMq=193, 
  XED_IFORM_BNDMOV_MEMdq_BND=194, 
  XED_IFORM_BNDMOV_MEMq_BND=195, 
  XED_IFORM_BNDSTX_MEMbnd32_BND=196, 
  XED_IFORM_BNDSTX_MEMbnd64_BND=197, 
  XED_IFORM_BOUND_GPRv_MEMa16=198, 
  XED_IFORM_BOUND_GPRv_MEMa32=199, 
  XED_IFORM_BSF_GPRv_GPRv=200, 
  XED_IFORM_BSF_GPRv_MEMv=201, 
  XED_IFORM_BSR_GPRv_GPRv=202, 
  XED_IFORM_BSR_GPRv_MEMv=203, 
  XED_IFORM_BSWAP_GPRv=204, 
  XED_IFORM_BT_GPRv_GPRv=205, 
  XED_IFORM_BT_GPRv_IMMb=206, 
  XED_IFORM_BT_MEMv_GPRv=207, 
  XED_IFORM_BT_MEMv_IMMb=208, 
  XED_IFORM_BTC_GPRv_GPRv=209, 
  XED_IFORM_BTC_GPRv_IMMb=210, 
  XED_IFORM_BTC_MEMv_GPRv=211, 
  XED_IFORM_BTC_MEMv_IMMb=212, 
  XED_IFORM_BTC_LOCK_MEMv_GPRv=213, 
  XED_IFORM_BTC_LOCK_MEMv_IMMb=214, 
  XED_IFORM_BTR_GPRv_GPRv=215, 
  XED_IFORM_BTR_GPRv_IMMb=216, 
  XED_IFORM_BTR_MEMv_GPRv=217, 
  XED_IFORM_BTR_MEMv_IMMb=218, 
  XED_IFORM_BTR_LOCK_MEMv_GPRv=219, 
  XED_IFORM_BTR_LOCK_MEMv_IMMb=220, 
  XED_IFORM_BTS_GPRv_GPRv=221, 
  XED_IFORM_BTS_GPRv_IMMb=222, 
  XED_IFORM_BTS_MEMv_GPRv=223, 
  XED_IFORM_BTS_MEMv_IMMb=224, 
  XED_IFORM_BTS_LOCK_MEMv_GPRv=225, 
  XED_IFORM_BTS_LOCK_MEMv_IMMb=226, 
  XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d=227, 
  XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d=228, 
  XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q=229, 
  XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q=230, 
  XED_IFORM_CALL_FAR_MEMp2=231, 
  XED_IFORM_CALL_FAR_PTRp_IMMw=232, 
  XED_IFORM_CALL_NEAR_GPRv=233, 
  XED_IFORM_CALL_NEAR_MEMv=234, 
  XED_IFORM_CALL_NEAR_RELBRd=235, 
  XED_IFORM_CALL_NEAR_RELBRz=236, 
  XED_IFORM_CBW=237, 
  XED_IFORM_CDQ=238, 
  XED_IFORM_CDQE=239, 
  XED_IFORM_CLAC=240, 
  XED_IFORM_CLC=241, 
  XED_IFORM_CLD=242, 
  XED_IFORM_CLDEMOTE_MEMu8=243, 
  XED_IFORM_CLFLUSH_MEMmprefetch=244, 
  XED_IFORM_CLFLUSHOPT_MEMmprefetch=245, 
  XED_IFORM_CLGI=246, 
  XED_IFORM_CLI=247, 
  XED_IFORM_CLRSSBSY_MEMu64=248, 
  XED_IFORM_CLTS=249, 
  XED_IFORM_CLWB_MEMmprefetch=250, 
  XED_IFORM_CLZERO=251, 
  XED_IFORM_CMC=252, 
  XED_IFORM_CMOVB_GPRv_GPRv=253, 
  XED_IFORM_CMOVB_GPRv_MEMv=254, 
  XED_IFORM_CMOVBE_GPRv_GPRv=255, 
  XED_IFORM_CMOVBE_GPRv_MEMv=256, 
  XED_IFORM_CMOVL_GPRv_GPRv=257, 
  XED_IFORM_CMOVL_GPRv_MEMv=258, 
  XED_IFORM_CMOVLE_GPRv_GPRv=259, 
  XED_IFORM_CMOVLE_GPRv_MEMv=260, 
  XED_IFORM_CMOVNB_GPRv_GPRv=261, 
  XED_IFORM_CMOVNB_GPRv_MEMv=262, 
  XED_IFORM_CMOVNBE_GPRv_GPRv=263, 
  XED_IFORM_CMOVNBE_GPRv_MEMv=264, 
  XED_IFORM_CMOVNL_GPRv_GPRv=265, 
  XED_IFORM_CMOVNL_GPRv_MEMv=266, 
  XED_IFORM_CMOVNLE_GPRv_GPRv=267, 
  XED_IFORM_CMOVNLE_GPRv_MEMv=268, 
  XED_IFORM_CMOVNO_GPRv_GPRv=269, 
  XED_IFORM_CMOVNO_GPRv_MEMv=270, 
  XED_IFORM_CMOVNP_GPRv_GPRv=271, 
  XED_IFORM_CMOVNP_GPRv_MEMv=272, 
  XED_IFORM_CMOVNS_GPRv_GPRv=273, 
  XED_IFORM_CMOVNS_GPRv_MEMv=274, 
  XED_IFORM_CMOVNZ_GPRv_GPRv=275, 
  XED_IFORM_CMOVNZ_GPRv_MEMv=276, 
  XED_IFORM_CMOVO_GPRv_GPRv=277, 
  XED_IFORM_CMOVO_GPRv_MEMv=278, 
  XED_IFORM_CMOVP_GPRv_GPRv=279, 
  XED_IFORM_CMOVP_GPRv_MEMv=280, 
  XED_IFORM_CMOVS_GPRv_GPRv=281, 
  XED_IFORM_CMOVS_GPRv_MEMv=282, 
  XED_IFORM_CMOVZ_GPRv_GPRv=283, 
  XED_IFORM_CMOVZ_GPRv_MEMv=284, 
  XED_IFORM_CMP_AL_IMMb=285, 
  XED_IFORM_CMP_GPR8_GPR8_38=286, 
  XED_IFORM_CMP_GPR8_GPR8_3A=287, 
  XED_IFORM_CMP_GPR8_IMMb_80r7=288, 
  XED_IFORM_CMP_GPR8_IMMb_82r7=289, 
  XED_IFORM_CMP_GPR8_MEMb=290, 
  XED_IFORM_CMP_GPRv_GPRv_39=291, 
  XED_IFORM_CMP_GPRv_GPRv_3B=292, 
  XED_IFORM_CMP_GPRv_IMMb=293, 
  XED_IFORM_CMP_GPRv_IMMz=294, 
  XED_IFORM_CMP_GPRv_MEMv=295, 
  XED_IFORM_CMP_MEMb_GPR8=296, 
  XED_IFORM_CMP_MEMb_IMMb_80r7=297, 
  XED_IFORM_CMP_MEMb_IMMb_82r7=298, 
  XED_IFORM_CMP_MEMv_GPRv=299, 
  XED_IFORM_CMP_MEMv_IMMb=300, 
  XED_IFORM_CMP_MEMv_IMMz=301, 
  XED_IFORM_CMP_OrAX_IMMz=302, 
  XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb=303, 
  XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb=304, 
  XED_IFORM_CMPPS_XMMps_MEMps_IMMb=305, 
  XED_IFORM_CMPPS_XMMps_XMMps_IMMb=306, 
  XED_IFORM_CMPSB=307, 
  XED_IFORM_CMPSD=308, 
  XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb=309, 
  XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb=310, 
  XED_IFORM_CMPSQ=311, 
  XED_IFORM_CMPSS_XMMss_MEMss_IMMb=312, 
  XED_IFORM_CMPSS_XMMss_XMMss_IMMb=313, 
  XED_IFORM_CMPSW=314, 
  XED_IFORM_CMPXCHG_GPR8_GPR8=315, 
  XED_IFORM_CMPXCHG_GPRv_GPRv=316, 
  XED_IFORM_CMPXCHG_MEMb_GPR8=317, 
  XED_IFORM_CMPXCHG_MEMv_GPRv=318, 
  XED_IFORM_CMPXCHG16B_MEMdq=319, 
  XED_IFORM_CMPXCHG16B_LOCK_MEMdq=320, 
  XED_IFORM_CMPXCHG8B_MEMq=321, 
  XED_IFORM_CMPXCHG8B_LOCK_MEMq=322, 
  XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8=323, 
  XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv=324, 
  XED_IFORM_COMISD_XMMsd_MEMsd=325, 
  XED_IFORM_COMISD_XMMsd_XMMsd=326, 
  XED_IFORM_COMISS_XMMss_MEMss=327, 
  XED_IFORM_COMISS_XMMss_XMMss=328, 
  XED_IFORM_CPUID=329, 
  XED_IFORM_CQO=330, 
  XED_IFORM_CRC32_GPRyy_GPR8b=331, 
  XED_IFORM_CRC32_GPRyy_GPRv=332, 
  XED_IFORM_CRC32_GPRyy_MEMb=333, 
  XED_IFORM_CRC32_GPRyy_MEMv=334, 
  XED_IFORM_CVTDQ2PD_XMMpd_MEMq=335, 
  XED_IFORM_CVTDQ2PD_XMMpd_XMMq=336, 
  XED_IFORM_CVTDQ2PS_XMMps_MEMdq=337, 
  XED_IFORM_CVTDQ2PS_XMMps_XMMdq=338, 
  XED_IFORM_CVTPD2DQ_XMMdq_MEMpd=339, 
  XED_IFORM_CVTPD2DQ_XMMdq_XMMpd=340, 
  XED_IFORM_CVTPD2PI_MMXq_MEMpd=341, 
  XED_IFORM_CVTPD2PI_MMXq_XMMpd=342, 
  XED_IFORM_CVTPD2PS_XMMps_MEMpd=343, 
  XED_IFORM_CVTPD2PS_XMMps_XMMpd=344, 
  XED_IFORM_CVTPI2PD_XMMpd_MEMq=345, 
  XED_IFORM_CVTPI2PD_XMMpd_MMXq=346, 
  XED_IFORM_CVTPI2PS_XMMq_MEMq=347, 
  XED_IFORM_CVTPI2PS_XMMq_MMXq=348, 
  XED_IFORM_CVTPS2DQ_XMMdq_MEMps=349, 
  XED_IFORM_CVTPS2DQ_XMMdq_XMMps=350, 
  XED_IFORM_CVTPS2PD_XMMpd_MEMq=351, 
  XED_IFORM_CVTPS2PD_XMMpd_XMMq=352, 
  XED_IFORM_CVTPS2PI_MMXq_MEMq=353, 
  XED_IFORM_CVTPS2PI_MMXq_XMMq=354, 
  XED_IFORM_CVTSD2SI_GPR32d_MEMsd=355, 
  XED_IFORM_CVTSD2SI_GPR32d_XMMsd=356, 
  XED_IFORM_CVTSD2SI_GPR64q_MEMsd=357, 
  XED_IFORM_CVTSD2SI_GPR64q_XMMsd=358, 
  XED_IFORM_CVTSD2SS_XMMss_MEMsd=359, 
  XED_IFORM_CVTSD2SS_XMMss_XMMsd=360, 
  XED_IFORM_CVTSI2SD_XMMsd_GPR32d=361, 
  XED_IFORM_CVTSI2SD_XMMsd_GPR64q=362, 
  XED_IFORM_CVTSI2SD_XMMsd_MEMd=363, 
  XED_IFORM_CVTSI2SD_XMMsd_MEMq=364, 
  XED_IFORM_CVTSI2SS_XMMss_GPR32d=365, 
  XED_IFORM_CVTSI2SS_XMMss_GPR64q=366, 
  XED_IFORM_CVTSI2SS_XMMss_MEMd=367, 
  XED_IFORM_CVTSI2SS_XMMss_MEMq=368, 
  XED_IFORM_CVTSS2SD_XMMsd_MEMss=369, 
  XED_IFORM_CVTSS2SD_XMMsd_XMMss=370, 
  XED_IFORM_CVTSS2SI_GPR32d_MEMss=371, 
  XED_IFORM_CVTSS2SI_GPR32d_XMMss=372, 
  XED_IFORM_CVTSS2SI_GPR64q_MEMss=373, 
  XED_IFORM_CVTSS2SI_GPR64q_XMMss=374, 
  XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd=375, 
  XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd=376, 
  XED_IFORM_CVTTPD2PI_MMXq_MEMpd=377, 
  XED_IFORM_CVTTPD2PI_MMXq_XMMpd=378, 
  XED_IFORM_CVTTPS2DQ_XMMdq_MEMps=379, 
  XED_IFORM_CVTTPS2DQ_XMMdq_XMMps=380, 
  XED_IFORM_CVTTPS2PI_MMXq_MEMq=381, 
  XED_IFORM_CVTTPS2PI_MMXq_XMMq=382, 
  XED_IFORM_CVTTSD2SI_GPR32d_MEMsd=383, 
  XED_IFORM_CVTTSD2SI_GPR32d_XMMsd=384, 
  XED_IFORM_CVTTSD2SI_GPR64q_MEMsd=385, 
  XED_IFORM_CVTTSD2SI_GPR64q_XMMsd=386, 
  XED_IFORM_CVTTSS2SI_GPR32d_MEMss=387, 
  XED_IFORM_CVTTSS2SI_GPR32d_XMMss=388, 
  XED_IFORM_CVTTSS2SI_GPR64q_MEMss=389, 
  XED_IFORM_CVTTSS2SI_GPR64q_XMMss=390, 
  XED_IFORM_CWD=391, 
  XED_IFORM_CWDE=392, 
  XED_IFORM_DAA=393, 
  XED_IFORM_DAS=394, 
  XED_IFORM_DEC_GPR8=395, 
  XED_IFORM_DEC_GPRv_48=396, 
  XED_IFORM_DEC_GPRv_FFr1=397, 
  XED_IFORM_DEC_MEMb=398, 
  XED_IFORM_DEC_MEMv=399, 
  XED_IFORM_DEC_LOCK_MEMb=400, 
  XED_IFORM_DEC_LOCK_MEMv=401, 
  XED_IFORM_DIV_GPR8=402, 
  XED_IFORM_DIV_GPRv=403, 
  XED_IFORM_DIV_MEMb=404, 
  XED_IFORM_DIV_MEMv=405, 
  XED_IFORM_DIVPD_XMMpd_MEMpd=406, 
  XED_IFORM_DIVPD_XMMpd_XMMpd=407, 
  XED_IFORM_DIVPS_XMMps_MEMps=408, 
  XED_IFORM_DIVPS_XMMps_XMMps=409, 
  XED_IFORM_DIVSD_XMMsd_MEMsd=410, 
  XED_IFORM_DIVSD_XMMsd_XMMsd=411, 
  XED_IFORM_DIVSS_XMMss_MEMss=412, 
  XED_IFORM_DIVSS_XMMss_XMMss=413, 
  XED_IFORM_DPPD_XMMdq_MEMdq_IMMb=414, 
  XED_IFORM_DPPD_XMMdq_XMMdq_IMMb=415, 
  XED_IFORM_DPPS_XMMdq_MEMdq_IMMb=416, 
  XED_IFORM_DPPS_XMMdq_XMMdq_IMMb=417, 
  XED_IFORM_EMMS=418, 
  XED_IFORM_ENCLS=419, 
  XED_IFORM_ENCLU=420, 
  XED_IFORM_ENCLV=421, 
  XED_IFORM_ENDBR32=422, 
  XED_IFORM_ENDBR64=423, 
  XED_IFORM_ENQCMD_GPRa_MEMu32=424, 
  XED_IFORM_ENQCMDS_GPRa_MEMu32=425, 
  XED_IFORM_ENTER_IMMw_IMMb=426, 
  XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb=427, 
  XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb=428, 
  XED_IFORM_EXTRQ_XMMq_IMMb_IMMb=429, 
  XED_IFORM_EXTRQ_XMMq_XMMdq=430, 
  XED_IFORM_F2XM1=431, 
  XED_IFORM_FABS=432, 
  XED_IFORM_FADD_ST0_MEMm64real=433, 
  XED_IFORM_FADD_ST0_MEMmem32real=434, 
  XED_IFORM_FADD_ST0_X87=435, 
  XED_IFORM_FADD_X87_ST0=436, 
  XED_IFORM_FADDP_X87_ST0=437, 
  XED_IFORM_FBLD_ST0_MEMmem80dec=438, 
  XED_IFORM_FBSTP_MEMmem80dec_ST0=439, 
  XED_IFORM_FCHS=440, 
  XED_IFORM_FCMOVB_ST0_X87=441, 
  XED_IFORM_FCMOVBE_ST0_X87=442, 
  XED_IFORM_FCMOVE_ST0_X87=443, 
  XED_IFORM_FCMOVNB_ST0_X87=444, 
  XED_IFORM_FCMOVNBE_ST0_X87=445, 
  XED_IFORM_FCMOVNE_ST0_X87=446, 
  XED_IFORM_FCMOVNU_ST0_X87=447, 
  XED_IFORM_FCMOVU_ST0_X87=448, 
  XED_IFORM_FCOM_ST0_MEMm64real=449, 
  XED_IFORM_FCOM_ST0_MEMmem32real=450, 
  XED_IFORM_FCOM_ST0_X87=451, 
  XED_IFORM_FCOM_ST0_X87_DCD0=452, 
  XED_IFORM_FCOMI_ST0_X87=453, 
  XED_IFORM_FCOMIP_ST0_X87=454, 
  XED_IFORM_FCOMP_ST0_MEMm64real=455, 
  XED_IFORM_FCOMP_ST0_MEMmem32real=456, 
  XED_IFORM_FCOMP_ST0_X87=457, 
  XED_IFORM_FCOMP_ST0_X87_DCD1=458, 
  XED_IFORM_FCOMP_ST0_X87_DED0=459, 
  XED_IFORM_FCOMPP=460, 
  XED_IFORM_FCOS=461, 
  XED_IFORM_FDECSTP=462, 
  XED_IFORM_FDISI8087_NOP=463, 
  XED_IFORM_FDIV_ST0_MEMm64real=464, 
  XED_IFORM_FDIV_ST0_MEMmem32real=465, 
  XED_IFORM_FDIV_ST0_X87=466, 
  XED_IFORM_FDIV_X87_ST0=467, 
  XED_IFORM_FDIVP_X87_ST0=468, 
  XED_IFORM_FDIVR_ST0_MEMm64real=469, 
  XED_IFORM_FDIVR_ST0_MEMmem32real=470, 
  XED_IFORM_FDIVR_ST0_X87=471, 
  XED_IFORM_FDIVR_X87_ST0=472, 
  XED_IFORM_FDIVRP_X87_ST0=473, 
  XED_IFORM_FEMMS=474, 
  XED_IFORM_FENI8087_NOP=475, 
  XED_IFORM_FFREE_X87=476, 
  XED_IFORM_FFREEP_X87=477, 
  XED_IFORM_FIADD_ST0_MEMmem16int=478, 
  XED_IFORM_FIADD_ST0_MEMmem32int=479, 
  XED_IFORM_FICOM_ST0_MEMmem16int=480, 
  XED_IFORM_FICOM_ST0_MEMmem32int=481, 
  XED_IFORM_FICOMP_ST0_MEMmem16int=482, 
  XED_IFORM_FICOMP_ST0_MEMmem32int=483, 
  XED_IFORM_FIDIV_ST0_MEMmem16int=484, 
  XED_IFORM_FIDIV_ST0_MEMmem32int=485, 
  XED_IFORM_FIDIVR_ST0_MEMmem16int=486, 
  XED_IFORM_FIDIVR_ST0_MEMmem32int=487, 
  XED_IFORM_FILD_ST0_MEMm64int=488, 
  XED_IFORM_FILD_ST0_MEMmem16int=489, 
  XED_IFORM_FILD_ST0_MEMmem32int=490, 
  XED_IFORM_FIMUL_ST0_MEMmem16int=491, 
  XED_IFORM_FIMUL_ST0_MEMmem32int=492, 
  XED_IFORM_FINCSTP=493, 
  XED_IFORM_FIST_MEMmem16int_ST0=494, 
  XED_IFORM_FIST_MEMmem32int_ST0=495, 
  XED_IFORM_FISTP_MEMm64int_ST0=496, 
  XED_IFORM_FISTP_MEMmem16int_ST0=497, 
  XED_IFORM_FISTP_MEMmem32int_ST0=498, 
  XED_IFORM_FISTTP_MEMm64int_ST0=499, 
  XED_IFORM_FISTTP_MEMmem16int_ST0=500, 
  XED_IFORM_FISTTP_MEMmem32int_ST0=501, 
  XED_IFORM_FISUB_ST0_MEMmem16int=502, 
  XED_IFORM_FISUB_ST0_MEMmem32int=503, 
  XED_IFORM_FISUBR_ST0_MEMmem16int=504, 
  XED_IFORM_FISUBR_ST0_MEMmem32int=505, 
  XED_IFORM_FLD_ST0_MEMm64real=506, 
  XED_IFORM_FLD_ST0_MEMmem32real=507, 
  XED_IFORM_FLD_ST0_MEMmem80real=508, 
  XED_IFORM_FLD_ST0_X87=509, 
  XED_IFORM_FLD1=510, 
  XED_IFORM_FLDCW_MEMmem16=511, 
  XED_IFORM_FLDENV_MEMmem14=512, 
  XED_IFORM_FLDENV_MEMmem28=513, 
  XED_IFORM_FLDL2E=514, 
  XED_IFORM_FLDL2T=515, 
  XED_IFORM_FLDLG2=516, 
  XED_IFORM_FLDLN2=517, 
  XED_IFORM_FLDPI=518, 
  XED_IFORM_FLDZ=519, 
  XED_IFORM_FMUL_ST0_MEMm64real=520, 
  XED_IFORM_FMUL_ST0_MEMmem32real=521, 
  XED_IFORM_FMUL_ST0_X87=522, 
  XED_IFORM_FMUL_X87_ST0=523, 
  XED_IFORM_FMULP_X87_ST0=524, 
  XED_IFORM_FNCLEX=525, 
  XED_IFORM_FNINIT=526, 
  XED_IFORM_FNOP=527, 
  XED_IFORM_FNSAVE_MEMmem108=528, 
  XED_IFORM_FNSAVE_MEMmem94=529, 
  XED_IFORM_FNSTCW_MEMmem16=530, 
  XED_IFORM_FNSTENV_MEMmem14=531, 
  XED_IFORM_FNSTENV_MEMmem28=532, 
  XED_IFORM_FNSTSW_AX=533, 
  XED_IFORM_FNSTSW_MEMmem16=534, 
  XED_IFORM_FPATAN=535, 
  XED_IFORM_FPREM=536, 
  XED_IFORM_FPREM1=537, 
  XED_IFORM_FPTAN=538, 
  XED_IFORM_FRNDINT=539, 
  XED_IFORM_FRSTOR_MEMmem108=540, 
  XED_IFORM_FRSTOR_MEMmem94=541, 
  XED_IFORM_FSCALE=542, 
  XED_IFORM_FSETPM287_NOP=543, 
  XED_IFORM_FSIN=544, 
  XED_IFORM_FSINCOS=545, 
  XED_IFORM_FSQRT=546, 
  XED_IFORM_FST_MEMm64real_ST0=547, 
  XED_IFORM_FST_MEMmem32real_ST0=548, 
  XED_IFORM_FST_X87_ST0=549, 
  XED_IFORM_FSTP_MEMm64real_ST0=550, 
  XED_IFORM_FSTP_MEMmem32real_ST0=551, 
  XED_IFORM_FSTP_MEMmem80real_ST0=552, 
  XED_IFORM_FSTP_X87_ST0=553, 
  XED_IFORM_FSTP_X87_ST0_DFD0=554, 
  XED_IFORM_FSTP_X87_ST0_DFD1=555, 
  XED_IFORM_FSTPNCE_X87_ST0=556, 
  XED_IFORM_FSUB_ST0_MEMm64real=557, 
  XED_IFORM_FSUB_ST0_MEMmem32real=558, 
  XED_IFORM_FSUB_ST0_X87=559, 
  XED_IFORM_FSUB_X87_ST0=560, 
  XED_IFORM_FSUBP_X87_ST0=561, 
  XED_IFORM_FSUBR_ST0_MEMm64real=562, 
  XED_IFORM_FSUBR_ST0_MEMmem32real=563, 
  XED_IFORM_FSUBR_ST0_X87=564, 
  XED_IFORM_FSUBR_X87_ST0=565, 
  XED_IFORM_FSUBRP_X87_ST0=566, 
  XED_IFORM_FTST=567, 
  XED_IFORM_FUCOM_ST0_X87=568, 
  XED_IFORM_FUCOMI_ST0_X87=569, 
  XED_IFORM_FUCOMIP_ST0_X87=570, 
  XED_IFORM_FUCOMP_ST0_X87=571, 
  XED_IFORM_FUCOMPP=572, 
  XED_IFORM_FWAIT=573, 
  XED_IFORM_FXAM=574, 
  XED_IFORM_FXCH_ST0_X87=575, 
  XED_IFORM_FXCH_ST0_X87_DDC1=576, 
  XED_IFORM_FXCH_ST0_X87_DFC1=577, 
  XED_IFORM_FXRSTOR_MEMmfpxenv=578, 
  XED_IFORM_FXRSTOR64_MEMmfpxenv=579, 
  XED_IFORM_FXSAVE_MEMmfpxenv=580, 
  XED_IFORM_FXSAVE64_MEMmfpxenv=581, 
  XED_IFORM_FXTRACT=582, 
  XED_IFORM_FYL2X=583, 
  XED_IFORM_FYL2XP1=584, 
  XED_IFORM_GETSEC=585, 
  XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8=586, 
  XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8=587, 
  XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8=588, 
  XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8=589, 
  XED_IFORM_GF2P8MULB_XMMu8_MEMu8=590, 
  XED_IFORM_GF2P8MULB_XMMu8_XMMu8=591, 
  XED_IFORM_HADDPD_XMMpd_MEMpd=592, 
  XED_IFORM_HADDPD_XMMpd_XMMpd=593, 
  XED_IFORM_HADDPS_XMMps_MEMps=594, 
  XED_IFORM_HADDPS_XMMps_XMMps=595, 
  XED_IFORM_HLT=596, 
  XED_IFORM_HSUBPD_XMMpd_MEMpd=597, 
  XED_IFORM_HSUBPD_XMMpd_XMMpd=598, 
  XED_IFORM_HSUBPS_XMMps_MEMps=599, 
  XED_IFORM_HSUBPS_XMMps_XMMps=600, 
  XED_IFORM_IDIV_GPR8=601, 
  XED_IFORM_IDIV_GPRv=602, 
  XED_IFORM_IDIV_MEMb=603, 
  XED_IFORM_IDIV_MEMv=604, 
  XED_IFORM_IMUL_GPR8=605, 
  XED_IFORM_IMUL_GPRv=606, 
  XED_IFORM_IMUL_GPRv_GPRv=607, 
  XED_IFORM_IMUL_GPRv_GPRv_IMMb=608, 
  XED_IFORM_IMUL_GPRv_GPRv_IMMz=609, 
  XED_IFORM_IMUL_GPRv_MEMv=610, 
  XED_IFORM_IMUL_GPRv_MEMv_IMMb=611, 
  XED_IFORM_IMUL_GPRv_MEMv_IMMz=612, 
  XED_IFORM_IMUL_MEMb=613, 
  XED_IFORM_IMUL_MEMv=614, 
  XED_IFORM_IN_AL_DX=615, 
  XED_IFORM_IN_AL_IMMb=616, 
  XED_IFORM_IN_OeAX_DX=617, 
  XED_IFORM_IN_OeAX_IMMb=618, 
  XED_IFORM_INC_GPR8=619, 
  XED_IFORM_INC_GPRv_40=620, 
  XED_IFORM_INC_GPRv_FFr0=621, 
  XED_IFORM_INC_MEMb=622, 
  XED_IFORM_INC_MEMv=623, 
  XED_IFORM_INCSSPD_GPR32u8=624, 
  XED_IFORM_INCSSPQ_GPR64u8=625, 
  XED_IFORM_INC_LOCK_MEMb=626, 
  XED_IFORM_INC_LOCK_MEMv=627, 
  XED_IFORM_INSB=628, 
  XED_IFORM_INSD=629, 
  XED_IFORM_INSERTPS_XMMps_MEMd_IMMb=630, 
  XED_IFORM_INSERTPS_XMMps_XMMps_IMMb=631, 
  XED_IFORM_INSERTQ_XMMq_XMMdq=632, 
  XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb=633, 
  XED_IFORM_INSW=634, 
  XED_IFORM_INT_IMMb=635, 
  XED_IFORM_INT1=636, 
  XED_IFORM_INT3=637, 
  XED_IFORM_INTO=638, 
  XED_IFORM_INVD=639, 
  XED_IFORM_INVEPT_GPR32_MEMdq=640, 
  XED_IFORM_INVEPT_GPR64_MEMdq=641, 
  XED_IFORM_INVLPG_MEMb=642, 
  XED_IFORM_INVLPGA_ArAX_ECX=643, 
  XED_IFORM_INVLPGB_EAX_EDX_ECX=644, 
  XED_IFORM_INVLPGB_RAX_EDX_ECX=645, 
  XED_IFORM_INVPCID_GPR32_MEMdq=646, 
  XED_IFORM_INVPCID_GPR64_MEMdq=647, 
  XED_IFORM_INVVPID_GPR32_MEMdq=648, 
  XED_IFORM_INVVPID_GPR64_MEMdq=649, 
  XED_IFORM_IRET=650, 
  XED_IFORM_IRETD=651, 
  XED_IFORM_IRETQ=652, 
  XED_IFORM_JB_RELBRb=653, 
  XED_IFORM_JB_RELBRd=654, 
  XED_IFORM_JB_RELBRz=655, 
  XED_IFORM_JBE_RELBRb=656, 
  XED_IFORM_JBE_RELBRd=657, 
  XED_IFORM_JBE_RELBRz=658, 
  XED_IFORM_JCXZ_RELBRb=659, 
  XED_IFORM_JECXZ_RELBRb=660, 
  XED_IFORM_JL_RELBRb=661, 
  XED_IFORM_JL_RELBRd=662, 
  XED_IFORM_JL_RELBRz=663, 
  XED_IFORM_JLE_RELBRb=664, 
  XED_IFORM_JLE_RELBRd=665, 
  XED_IFORM_JLE_RELBRz=666, 
  XED_IFORM_JMP_GPRv=667, 
  XED_IFORM_JMP_MEMv=668, 
  XED_IFORM_JMP_RELBRb=669, 
  XED_IFORM_JMP_RELBRd=670, 
  XED_IFORM_JMP_RELBRz=671, 
  XED_IFORM_JMP_FAR_MEMp2=672, 
  XED_IFORM_JMP_FAR_PTRp_IMMw=673, 
  XED_IFORM_JNB_RELBRb=674, 
  XED_IFORM_JNB_RELBRd=675, 
  XED_IFORM_JNB_RELBRz=676, 
  XED_IFORM_JNBE_RELBRb=677, 
  XED_IFORM_JNBE_RELBRd=678, 
  XED_IFORM_JNBE_RELBRz=679, 
  XED_IFORM_JNL_RELBRb=680, 
  XED_IFORM_JNL_RELBRd=681, 
  XED_IFORM_JNL_RELBRz=682, 
  XED_IFORM_JNLE_RELBRb=683, 
  XED_IFORM_JNLE_RELBRd=684, 
  XED_IFORM_JNLE_RELBRz=685, 
  XED_IFORM_JNO_RELBRb=686, 
  XED_IFORM_JNO_RELBRd=687, 
  XED_IFORM_JNO_RELBRz=688, 
  XED_IFORM_JNP_RELBRb=689, 
  XED_IFORM_JNP_RELBRd=690, 
  XED_IFORM_JNP_RELBRz=691, 
  XED_IFORM_JNS_RELBRb=692, 
  XED_IFORM_JNS_RELBRd=693, 
  XED_IFORM_JNS_RELBRz=694, 
  XED_IFORM_JNZ_RELBRb=695, 
  XED_IFORM_JNZ_RELBRd=696, 
  XED_IFORM_JNZ_RELBRz=697, 
  XED_IFORM_JO_RELBRb=698, 
  XED_IFORM_JO_RELBRd=699, 
  XED_IFORM_JO_RELBRz=700, 
  XED_IFORM_JP_RELBRb=701, 
  XED_IFORM_JP_RELBRd=702, 
  XED_IFORM_JP_RELBRz=703, 
  XED_IFORM_JRCXZ_RELBRb=704, 
  XED_IFORM_JS_RELBRb=705, 
  XED_IFORM_JS_RELBRd=706, 
  XED_IFORM_JS_RELBRz=707, 
  XED_IFORM_JZ_RELBRb=708, 
  XED_IFORM_JZ_RELBRd=709, 
  XED_IFORM_JZ_RELBRz=710, 
  XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512=711, 
  XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512=712, 
  XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=713, 
  XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512=714, 
  XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512=715, 
  XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512=716, 
  XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512=717, 
  XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512=718, 
  XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512=719, 
  XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512=720, 
  XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=721, 
  XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512=722, 
  XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512=723, 
  XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512=724, 
  XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512=725, 
  XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512=726, 
  XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512=727, 
  XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512=728, 
  XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512=729, 
  XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512=730, 
  XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512=731, 
  XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512=732, 
  XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512=733, 
  XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512=734, 
  XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512=735, 
  XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512=736, 
  XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512=737, 
  XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512=738, 
  XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512=739, 
  XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512=740, 
  XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512=741, 
  XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512=742, 
  XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512=743, 
  XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512=744, 
  XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512=745, 
  XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512=746, 
  XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512=747, 
  XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512=748, 
  XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=749, 
  XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512=750, 
  XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512=751, 
  XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512=752, 
  XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512=753, 
  XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512=754, 
  XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512=755, 
  XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512=756, 
  XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512=757, 
  XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512=758, 
  XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512=759, 
  XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512=760, 
  XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512=761, 
  XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512=762, 
  XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512=763, 
  XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512=764, 
  XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512=765, 
  XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512=766, 
  XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512=767, 
  XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=768, 
  XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512=769, 
  XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512=770, 
  XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512=771, 
  XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=772, 
  XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512=773, 
  XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512=774, 
  XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512=775, 
  XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=776, 
  XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512=777, 
  XED_IFORM_LAHF=778, 
  XED_IFORM_LAR_GPRv_GPRv=779, 
  XED_IFORM_LAR_GPRv_MEMw=780, 
  XED_IFORM_LDDQU_XMMpd_MEMdq=781, 
  XED_IFORM_LDMXCSR_MEMd=782, 
  XED_IFORM_LDS_GPRz_MEMp=783, 
  XED_IFORM_LEA_GPRv_AGEN=784, 
  XED_IFORM_LEAVE=785, 
  XED_IFORM_LES_GPRz_MEMp=786, 
  XED_IFORM_LFENCE=787, 
  XED_IFORM_LFS_GPRv_MEMp2=788, 
  XED_IFORM_LGDT_MEMs=789, 
  XED_IFORM_LGDT_MEMs64=790, 
  XED_IFORM_LGS_GPRv_MEMp2=791, 
  XED_IFORM_LIDT_MEMs=792, 
  XED_IFORM_LIDT_MEMs64=793, 
  XED_IFORM_LLDT_GPR16=794, 
  XED_IFORM_LLDT_MEMw=795, 
  XED_IFORM_LLWPCB_GPRyy=796, 
  XED_IFORM_LMSW_GPR16=797, 
  XED_IFORM_LMSW_MEMw=798, 
  XED_IFORM_LODSB=799, 
  XED_IFORM_LODSD=800, 
  XED_IFORM_LODSQ=801, 
  XED_IFORM_LODSW=802, 
  XED_IFORM_LOOP_RELBRb=803, 
  XED_IFORM_LOOPE_RELBRb=804, 
  XED_IFORM_LOOPNE_RELBRb=805, 
  XED_IFORM_LSL_GPRv_GPRz=806, 
  XED_IFORM_LSL_GPRv_MEMw=807, 
  XED_IFORM_LSS_GPRv_MEMp2=808, 
  XED_IFORM_LTR_GPR16=809, 
  XED_IFORM_LTR_MEMw=810, 
  XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd=811, 
  XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd=812, 
  XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd=813, 
  XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd=814, 
  XED_IFORM_LZCNT_GPRv_GPRv=815, 
  XED_IFORM_LZCNT_GPRv_MEMv=816, 
  XED_IFORM_MASKMOVDQU_XMMdq_XMMdq=817, 
  XED_IFORM_MASKMOVQ_MMXq_MMXq=818, 
  XED_IFORM_MAXPD_XMMpd_MEMpd=819, 
  XED_IFORM_MAXPD_XMMpd_XMMpd=820, 
  XED_IFORM_MAXPS_XMMps_MEMps=821, 
  XED_IFORM_MAXPS_XMMps_XMMps=822, 
  XED_IFORM_MAXSD_XMMsd_MEMsd=823, 
  XED_IFORM_MAXSD_XMMsd_XMMsd=824, 
  XED_IFORM_MAXSS_XMMss_MEMss=825, 
  XED_IFORM_MAXSS_XMMss_XMMss=826, 
  XED_IFORM_MCOMMIT=827, 
  XED_IFORM_MFENCE=828, 
  XED_IFORM_MINPD_XMMpd_MEMpd=829, 
  XED_IFORM_MINPD_XMMpd_XMMpd=830, 
  XED_IFORM_MINPS_XMMps_MEMps=831, 
  XED_IFORM_MINPS_XMMps_XMMps=832, 
  XED_IFORM_MINSD_XMMsd_MEMsd=833, 
  XED_IFORM_MINSD_XMMsd_XMMsd=834, 
  XED_IFORM_MINSS_XMMss_MEMss=835, 
  XED_IFORM_MINSS_XMMss_XMMss=836, 
  XED_IFORM_MONITOR=837, 
  XED_IFORM_MONITORX=838, 
  XED_IFORM_MOV_AL_MEMb=839, 
  XED_IFORM_MOV_GPR8_GPR8_88=840, 
  XED_IFORM_MOV_GPR8_GPR8_8A=841, 
  XED_IFORM_MOV_GPR8_IMMb_B0=842, 
  XED_IFORM_MOV_GPR8_IMMb_C6r0=843, 
  XED_IFORM_MOV_GPR8_MEMb=844, 
  XED_IFORM_MOV_GPRv_GPRv_89=845, 
  XED_IFORM_MOV_GPRv_GPRv_8B=846, 
  XED_IFORM_MOV_GPRv_IMMv=847, 
  XED_IFORM_MOV_GPRv_IMMz=848, 
  XED_IFORM_MOV_GPRv_MEMv=849, 
  XED_IFORM_MOV_GPRv_SEG=850, 
  XED_IFORM_MOV_MEMb_AL=851, 
  XED_IFORM_MOV_MEMb_GPR8=852, 
  XED_IFORM_MOV_MEMb_IMMb=853, 
  XED_IFORM_MOV_MEMv_GPRv=854, 
  XED_IFORM_MOV_MEMv_IMMz=855, 
  XED_IFORM_MOV_MEMv_OrAX=856, 
  XED_IFORM_MOV_MEMw_SEG=857, 
  XED_IFORM_MOV_OrAX_MEMv=858, 
  XED_IFORM_MOV_SEG_GPR16=859, 
  XED_IFORM_MOV_SEG_MEMw=860, 
  XED_IFORM_MOVAPD_MEMpd_XMMpd=861, 
  XED_IFORM_MOVAPD_XMMpd_MEMpd=862, 
  XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28=863, 
  XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29=864, 
  XED_IFORM_MOVAPS_MEMps_XMMps=865, 
  XED_IFORM_MOVAPS_XMMps_MEMps=866, 
  XED_IFORM_MOVAPS_XMMps_XMMps_0F28=867, 
  XED_IFORM_MOVAPS_XMMps_XMMps_0F29=868, 
  XED_IFORM_MOVBE_GPRv_MEMv=869, 
  XED_IFORM_MOVBE_MEMv_GPRv=870, 
  XED_IFORM_MOVD_GPR32_MMXd=871, 
  XED_IFORM_MOVD_GPR32_XMMd=872, 
  XED_IFORM_MOVD_MEMd_MMXd=873, 
  XED_IFORM_MOVD_MEMd_XMMd=874, 
  XED_IFORM_MOVD_MMXq_GPR32=875, 
  XED_IFORM_MOVD_MMXq_MEMd=876, 
  XED_IFORM_MOVD_XMMdq_GPR32=877, 
  XED_IFORM_MOVD_XMMdq_MEMd=878, 
  XED_IFORM_MOVDDUP_XMMdq_MEMq=879, 
  XED_IFORM_MOVDDUP_XMMdq_XMMq=880, 
  XED_IFORM_MOVDIR64B_GPRa_MEM=881, 
  XED_IFORM_MOVDIRI_MEMu32_GPR32u32=882, 
  XED_IFORM_MOVDIRI_MEMu64_GPR64u64=883, 
  XED_IFORM_MOVDQ2Q_MMXq_XMMq=884, 
  XED_IFORM_MOVDQA_MEMdq_XMMdq=885, 
  XED_IFORM_MOVDQA_XMMdq_MEMdq=886, 
  XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F=887, 
  XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F=888, 
  XED_IFORM_MOVDQU_MEMdq_XMMdq=889, 
  XED_IFORM_MOVDQU_XMMdq_MEMdq=890, 
  XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F=891, 
  XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F=892, 
  XED_IFORM_MOVHLPS_XMMq_XMMq=893, 
  XED_IFORM_MOVHPD_MEMq_XMMsd=894, 
  XED_IFORM_MOVHPD_XMMsd_MEMq=895, 
  XED_IFORM_MOVHPS_MEMq_XMMps=896, 
  XED_IFORM_MOVHPS_XMMq_MEMq=897, 
  XED_IFORM_MOVLHPS_XMMq_XMMq=898, 
  XED_IFORM_MOVLPD_MEMq_XMMsd=899, 
  XED_IFORM_MOVLPD_XMMsd_MEMq=900, 
  XED_IFORM_MOVLPS_MEMq_XMMps=901, 
  XED_IFORM_MOVLPS_XMMq_MEMq=902, 
  XED_IFORM_MOVMSKPD_GPR32_XMMpd=903, 
  XED_IFORM_MOVMSKPS_GPR32_XMMps=904, 
  XED_IFORM_MOVNTDQ_MEMdq_XMMdq=905, 
  XED_IFORM_MOVNTDQA_XMMdq_MEMdq=906, 
  XED_IFORM_MOVNTI_MEMd_GPR32=907, 
  XED_IFORM_MOVNTI_MEMq_GPR64=908, 
  XED_IFORM_MOVNTPD_MEMdq_XMMpd=909, 
  XED_IFORM_MOVNTPS_MEMdq_XMMps=910, 
  XED_IFORM_MOVNTQ_MEMq_MMXq=911, 
  XED_IFORM_MOVNTSD_MEMq_XMMq=912, 
  XED_IFORM_MOVNTSS_MEMd_XMMd=913, 
  XED_IFORM_MOVQ_GPR64_MMXq=914, 
  XED_IFORM_MOVQ_GPR64_XMMq=915, 
  XED_IFORM_MOVQ_MEMq_MMXq_0F7E=916, 
  XED_IFORM_MOVQ_MEMq_MMXq_0F7F=917, 
  XED_IFORM_MOVQ_MEMq_XMMq_0F7E=918, 
  XED_IFORM_MOVQ_MEMq_XMMq_0FD6=919, 
  XED_IFORM_MOVQ_MMXq_GPR64=920, 
  XED_IFORM_MOVQ_MMXq_MEMq_0F6E=921, 
  XED_IFORM_MOVQ_MMXq_MEMq_0F6F=922, 
  XED_IFORM_MOVQ_MMXq_MMXq_0F6F=923, 
  XED_IFORM_MOVQ_MMXq_MMXq_0F7F=924, 
  XED_IFORM_MOVQ_XMMdq_GPR64=925, 
  XED_IFORM_MOVQ_XMMdq_MEMq_0F6E=926, 
  XED_IFORM_MOVQ_XMMdq_MEMq_0F7E=927, 
  XED_IFORM_MOVQ_XMMdq_XMMq_0F7E=928, 
  XED_IFORM_MOVQ_XMMdq_XMMq_0FD6=929, 
  XED_IFORM_MOVQ2DQ_XMMdq_MMXq=930, 
  XED_IFORM_MOVSB=931, 
  XED_IFORM_MOVSD=932, 
  XED_IFORM_MOVSD_XMM_MEMsd_XMMsd=933, 
  XED_IFORM_MOVSD_XMM_XMMdq_MEMsd=934, 
  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10=935, 
  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11=936, 
  XED_IFORM_MOVSHDUP_XMMps_MEMps=937, 
  XED_IFORM_MOVSHDUP_XMMps_XMMps=938, 
  XED_IFORM_MOVSLDUP_XMMps_MEMps=939, 
  XED_IFORM_MOVSLDUP_XMMps_XMMps=940, 
  XED_IFORM_MOVSQ=941, 
  XED_IFORM_MOVSS_MEMss_XMMss=942, 
  XED_IFORM_MOVSS_XMMdq_MEMss=943, 
  XED_IFORM_MOVSS_XMMss_XMMss_0F10=944, 
  XED_IFORM_MOVSS_XMMss_XMMss_0F11=945, 
  XED_IFORM_MOVSW=946, 
  XED_IFORM_MOVSX_GPRv_GPR16=947, 
  XED_IFORM_MOVSX_GPRv_GPR8=948, 
  XED_IFORM_MOVSX_GPRv_MEMb=949, 
  XED_IFORM_MOVSX_GPRv_MEMw=950, 
  XED_IFORM_MOVSXD_GPRv_GPRz=951, 
  XED_IFORM_MOVSXD_GPRv_MEMz=952, 
  XED_IFORM_MOVUPD_MEMpd_XMMpd=953, 
  XED_IFORM_MOVUPD_XMMpd_MEMpd=954, 
  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10=955, 
  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11=956, 
  XED_IFORM_MOVUPS_MEMps_XMMps=957, 
  XED_IFORM_MOVUPS_XMMps_MEMps=958, 
  XED_IFORM_MOVUPS_XMMps_XMMps_0F10=959, 
  XED_IFORM_MOVUPS_XMMps_XMMps_0F11=960, 
  XED_IFORM_MOVZX_GPRv_GPR16=961, 
  XED_IFORM_MOVZX_GPRv_GPR8=962, 
  XED_IFORM_MOVZX_GPRv_MEMb=963, 
  XED_IFORM_MOVZX_GPRv_MEMw=964, 
  XED_IFORM_MOV_CR_CR_GPR32=965, 
  XED_IFORM_MOV_CR_CR_GPR64=966, 
  XED_IFORM_MOV_CR_GPR32_CR=967, 
  XED_IFORM_MOV_CR_GPR64_CR=968, 
  XED_IFORM_MOV_DR_DR_GPR32=969, 
  XED_IFORM_MOV_DR_DR_GPR64=970, 
  XED_IFORM_MOV_DR_GPR32_DR=971, 
  XED_IFORM_MOV_DR_GPR64_DR=972, 
  XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb=973, 
  XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb=974, 
  XED_IFORM_MUL_GPR8=975, 
  XED_IFORM_MUL_GPRv=976, 
  XED_IFORM_MUL_MEMb=977, 
  XED_IFORM_MUL_MEMv=978, 
  XED_IFORM_MULPD_XMMpd_MEMpd=979, 
  XED_IFORM_MULPD_XMMpd_XMMpd=980, 
  XED_IFORM_MULPS_XMMps_MEMps=981, 
  XED_IFORM_MULPS_XMMps_XMMps=982, 
  XED_IFORM_MULSD_XMMsd_MEMsd=983, 
  XED_IFORM_MULSD_XMMsd_XMMsd=984, 
  XED_IFORM_MULSS_XMMss_MEMss=985, 
  XED_IFORM_MULSS_XMMss_XMMss=986, 
  XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd=987, 
  XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d=988, 
  XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq=989, 
  XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q=990, 
  XED_IFORM_MWAIT=991, 
  XED_IFORM_MWAITX=992, 
  XED_IFORM_NEG_GPR8=993, 
  XED_IFORM_NEG_GPRv=994, 
  XED_IFORM_NEG_MEMb=995, 
  XED_IFORM_NEG_MEMv=996, 
  XED_IFORM_NEG_LOCK_MEMb=997, 
  XED_IFORM_NEG_LOCK_MEMv=998, 
  XED_IFORM_NOP_90=999, 
  XED_IFORM_NOP_GPRv_0F18r0=1000, 
  XED_IFORM_NOP_GPRv_0F18r1=1001, 
  XED_IFORM_NOP_GPRv_0F18r2=1002, 
  XED_IFORM_NOP_GPRv_0F18r3=1003, 
  XED_IFORM_NOP_GPRv_0F18r4=1004, 
  XED_IFORM_NOP_GPRv_0F18r5=1005, 
  XED_IFORM_NOP_GPRv_0F18r6=1006, 
  XED_IFORM_NOP_GPRv_0F18r7=1007, 
  XED_IFORM_NOP_GPRv_GPRv_0F0D=1008, 
  XED_IFORM_NOP_GPRv_GPRv_0F19=1009, 
  XED_IFORM_NOP_GPRv_GPRv_0F1A=1010, 
  XED_IFORM_NOP_GPRv_GPRv_0F1B=1011, 
  XED_IFORM_NOP_GPRv_GPRv_0F1C=1012, 
  XED_IFORM_NOP_GPRv_GPRv_0F1D=1013, 
  XED_IFORM_NOP_GPRv_GPRv_0F1E=1014, 
  XED_IFORM_NOP_GPRv_GPRv_0F1F=1015, 
  XED_IFORM_NOP_GPRv_MEM_0F1B=1016, 
  XED_IFORM_NOP_GPRv_MEMv_0F1A=1017, 
  XED_IFORM_NOP_MEMv_0F18r4=1018, 
  XED_IFORM_NOP_MEMv_0F18r5=1019, 
  XED_IFORM_NOP_MEMv_0F18r6=1020, 
  XED_IFORM_NOP_MEMv_0F18r7=1021, 
  XED_IFORM_NOP_MEMv_GPRv_0F19=1022, 
  XED_IFORM_NOP_MEMv_GPRv_0F1C=1023, 
  XED_IFORM_NOP_MEMv_GPRv_0F1D=1024, 
  XED_IFORM_NOP_MEMv_GPRv_0F1E=1025, 
  XED_IFORM_NOP_MEMv_GPRv_0F1F=1026, 
  XED_IFORM_NOT_GPR8=1027, 
  XED_IFORM_NOT_GPRv=1028, 
  XED_IFORM_NOT_MEMb=1029, 
  XED_IFORM_NOT_MEMv=1030, 
  XED_IFORM_NOT_LOCK_MEMb=1031, 
  XED_IFORM_NOT_LOCK_MEMv=1032, 
  XED_IFORM_OR_AL_IMMb=1033, 
  XED_IFORM_OR_GPR8_GPR8_08=1034, 
  XED_IFORM_OR_GPR8_GPR8_0A=1035, 
  XED_IFORM_OR_GPR8_IMMb_80r1=1036, 
  XED_IFORM_OR_GPR8_IMMb_82r1=1037, 
  XED_IFORM_OR_GPR8_MEMb=1038, 
  XED_IFORM_OR_GPRv_GPRv_09=1039, 
  XED_IFORM_OR_GPRv_GPRv_0B=1040, 
  XED_IFORM_OR_GPRv_IMMb=1041, 
  XED_IFORM_OR_GPRv_IMMz=1042, 
  XED_IFORM_OR_GPRv_MEMv=1043, 
  XED_IFORM_OR_MEMb_GPR8=1044, 
  XED_IFORM_OR_MEMb_IMMb_80r1=1045, 
  XED_IFORM_OR_MEMb_IMMb_82r1=1046, 
  XED_IFORM_OR_MEMv_GPRv=1047, 
  XED_IFORM_OR_MEMv_IMMb=1048, 
  XED_IFORM_OR_MEMv_IMMz=1049, 
  XED_IFORM_OR_OrAX_IMMz=1050, 
  XED_IFORM_ORPD_XMMxuq_MEMxuq=1051, 
  XED_IFORM_ORPD_XMMxuq_XMMxuq=1052, 
  XED_IFORM_ORPS_XMMxud_MEMxud=1053, 
  XED_IFORM_ORPS_XMMxud_XMMxud=1054, 
  XED_IFORM_OR_LOCK_MEMb_GPR8=1055, 
  XED_IFORM_OR_LOCK_MEMb_IMMb_80r1=1056, 
  XED_IFORM_OR_LOCK_MEMb_IMMb_82r1=1057, 
  XED_IFORM_OR_LOCK_MEMv_GPRv=1058, 
  XED_IFORM_OR_LOCK_MEMv_IMMb=1059, 
  XED_IFORM_OR_LOCK_MEMv_IMMz=1060, 
  XED_IFORM_OUT_DX_AL=1061, 
  XED_IFORM_OUT_DX_OeAX=1062, 
  XED_IFORM_OUT_IMMb_AL=1063, 
  XED_IFORM_OUT_IMMb_OeAX=1064, 
  XED_IFORM_OUTSB=1065, 
  XED_IFORM_OUTSD=1066, 
  XED_IFORM_OUTSW=1067, 
  XED_IFORM_PABSB_MMXq_MEMq=1068, 
  XED_IFORM_PABSB_MMXq_MMXq=1069, 
  XED_IFORM_PABSB_XMMdq_MEMdq=1070, 
  XED_IFORM_PABSB_XMMdq_XMMdq=1071, 
  XED_IFORM_PABSD_MMXq_MEMq=1072, 
  XED_IFORM_PABSD_MMXq_MMXq=1073, 
  XED_IFORM_PABSD_XMMdq_MEMdq=1074, 
  XED_IFORM_PABSD_XMMdq_XMMdq=1075, 
  XED_IFORM_PABSW_MMXq_MEMq=1076, 
  XED_IFORM_PABSW_MMXq_MMXq=1077, 
  XED_IFORM_PABSW_XMMdq_MEMdq=1078, 
  XED_IFORM_PABSW_XMMdq_XMMdq=1079, 
  XED_IFORM_PACKSSDW_MMXq_MEMq=1080, 
  XED_IFORM_PACKSSDW_MMXq_MMXq=1081, 
  XED_IFORM_PACKSSDW_XMMdq_MEMdq=1082, 
  XED_IFORM_PACKSSDW_XMMdq_XMMdq=1083, 
  XED_IFORM_PACKSSWB_MMXq_MEMq=1084, 
  XED_IFORM_PACKSSWB_MMXq_MMXq=1085, 
  XED_IFORM_PACKSSWB_XMMdq_MEMdq=1086, 
  XED_IFORM_PACKSSWB_XMMdq_XMMdq=1087, 
  XED_IFORM_PACKUSDW_XMMdq_MEMdq=1088, 
  XED_IFORM_PACKUSDW_XMMdq_XMMdq=1089, 
  XED_IFORM_PACKUSWB_MMXq_MEMq=1090, 
  XED_IFORM_PACKUSWB_MMXq_MMXq=1091, 
  XED_IFORM_PACKUSWB_XMMdq_MEMdq=1092, 
  XED_IFORM_PACKUSWB_XMMdq_XMMdq=1093, 
  XED_IFORM_PADDB_MMXq_MEMq=1094, 
  XED_IFORM_PADDB_MMXq_MMXq=1095, 
  XED_IFORM_PADDB_XMMdq_MEMdq=1096, 
  XED_IFORM_PADDB_XMMdq_XMMdq=1097, 
  XED_IFORM_PADDD_MMXq_MEMq=1098, 
  XED_IFORM_PADDD_MMXq_MMXq=1099, 
  XED_IFORM_PADDD_XMMdq_MEMdq=1100, 
  XED_IFORM_PADDD_XMMdq_XMMdq=1101, 
  XED_IFORM_PADDQ_MMXq_MEMq=1102, 
  XED_IFORM_PADDQ_MMXq_MMXq=1103, 
  XED_IFORM_PADDQ_XMMdq_MEMdq=1104, 
  XED_IFORM_PADDQ_XMMdq_XMMdq=1105, 
  XED_IFORM_PADDSB_MMXq_MEMq=1106, 
  XED_IFORM_PADDSB_MMXq_MMXq=1107, 
  XED_IFORM_PADDSB_XMMdq_MEMdq=1108, 
  XED_IFORM_PADDSB_XMMdq_XMMdq=1109, 
  XED_IFORM_PADDSW_MMXq_MEMq=1110, 
  XED_IFORM_PADDSW_MMXq_MMXq=1111, 
  XED_IFORM_PADDSW_XMMdq_MEMdq=1112, 
  XED_IFORM_PADDSW_XMMdq_XMMdq=1113, 
  XED_IFORM_PADDUSB_MMXq_MEMq=1114, 
  XED_IFORM_PADDUSB_MMXq_MMXq=1115, 
  XED_IFORM_PADDUSB_XMMdq_MEMdq=1116, 
  XED_IFORM_PADDUSB_XMMdq_XMMdq=1117, 
  XED_IFORM_PADDUSW_MMXq_MEMq=1118, 
  XED_IFORM_PADDUSW_MMXq_MMXq=1119, 
  XED_IFORM_PADDUSW_XMMdq_MEMdq=1120, 
  XED_IFORM_PADDUSW_XMMdq_XMMdq=1121, 
  XED_IFORM_PADDW_MMXq_MEMq=1122, 
  XED_IFORM_PADDW_MMXq_MMXq=1123, 
  XED_IFORM_PADDW_XMMdq_MEMdq=1124, 
  XED_IFORM_PADDW_XMMdq_XMMdq=1125, 
  XED_IFORM_PALIGNR_MMXq_MEMq_IMMb=1126, 
  XED_IFORM_PALIGNR_MMXq_MMXq_IMMb=1127, 
  XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb=1128, 
  XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb=1129, 
  XED_IFORM_PAND_MMXq_MEMq=1130, 
  XED_IFORM_PAND_MMXq_MMXq=1131, 
  XED_IFORM_PAND_XMMdq_MEMdq=1132, 
  XED_IFORM_PAND_XMMdq_XMMdq=1133, 
  XED_IFORM_PANDN_MMXq_MEMq=1134, 
  XED_IFORM_PANDN_MMXq_MMXq=1135, 
  XED_IFORM_PANDN_XMMdq_MEMdq=1136, 
  XED_IFORM_PANDN_XMMdq_XMMdq=1137, 
  XED_IFORM_PAUSE=1138, 
  XED_IFORM_PAVGB_MMXq_MEMq=1139, 
  XED_IFORM_PAVGB_MMXq_MMXq=1140, 
  XED_IFORM_PAVGB_XMMdq_MEMdq=1141, 
  XED_IFORM_PAVGB_XMMdq_XMMdq=1142, 
  XED_IFORM_PAVGUSB_MMXq_MEMq=1143, 
  XED_IFORM_PAVGUSB_MMXq_MMXq=1144, 
  XED_IFORM_PAVGW_MMXq_MEMq=1145, 
  XED_IFORM_PAVGW_MMXq_MMXq=1146, 
  XED_IFORM_PAVGW_XMMdq_MEMdq=1147, 
  XED_IFORM_PAVGW_XMMdq_XMMdq=1148, 
  XED_IFORM_PBLENDVB_XMMdq_MEMdq=1149, 
  XED_IFORM_PBLENDVB_XMMdq_XMMdq=1150, 
  XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb=1151, 
  XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb=1152, 
  XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb=1153, 
  XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb=1154, 
  XED_IFORM_PCMPEQB_MMXq_MEMq=1155, 
  XED_IFORM_PCMPEQB_MMXq_MMXq=1156, 
  XED_IFORM_PCMPEQB_XMMdq_MEMdq=1157, 
  XED_IFORM_PCMPEQB_XMMdq_XMMdq=1158, 
  XED_IFORM_PCMPEQD_MMXq_MEMq=1159, 
  XED_IFORM_PCMPEQD_MMXq_MMXq=1160, 
  XED_IFORM_PCMPEQD_XMMdq_MEMdq=1161, 
  XED_IFORM_PCMPEQD_XMMdq_XMMdq=1162, 
  XED_IFORM_PCMPEQQ_XMMdq_MEMdq=1163, 
  XED_IFORM_PCMPEQQ_XMMdq_XMMdq=1164, 
  XED_IFORM_PCMPEQW_MMXq_MEMq=1165, 
  XED_IFORM_PCMPEQW_MMXq_MMXq=1166, 
  XED_IFORM_PCMPEQW_XMMdq_MEMdq=1167, 
  XED_IFORM_PCMPEQW_XMMdq_XMMdq=1168, 
  XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb=1169, 
  XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb=1170, 
  XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb=1171, 
  XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb=1172, 
  XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb=1173, 
  XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb=1174, 
  XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb=1175, 
  XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb=1176, 
  XED_IFORM_PCMPGTB_MMXq_MEMq=1177, 
  XED_IFORM_PCMPGTB_MMXq_MMXq=1178, 
  XED_IFORM_PCMPGTB_XMMdq_MEMdq=1179, 
  XED_IFORM_PCMPGTB_XMMdq_XMMdq=1180, 
  XED_IFORM_PCMPGTD_MMXq_MEMq=1181, 
  XED_IFORM_PCMPGTD_MMXq_MMXq=1182, 
  XED_IFORM_PCMPGTD_XMMdq_MEMdq=1183, 
  XED_IFORM_PCMPGTD_XMMdq_XMMdq=1184, 
  XED_IFORM_PCMPGTQ_XMMdq_MEMdq=1185, 
  XED_IFORM_PCMPGTQ_XMMdq_XMMdq=1186, 
  XED_IFORM_PCMPGTW_MMXq_MEMq=1187, 
  XED_IFORM_PCMPGTW_MMXq_MMXq=1188, 
  XED_IFORM_PCMPGTW_XMMdq_MEMdq=1189, 
  XED_IFORM_PCMPGTW_XMMdq_XMMdq=1190, 
  XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb=1191, 
  XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb=1192, 
  XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb=1193, 
  XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb=1194, 
  XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb=1195, 
  XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb=1196, 
  XED_IFORM_PCONFIG=1197, 
  XED_IFORM_PCONFIG64=1198, 
  XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd=1199, 
  XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d=1200, 
  XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq=1201, 
  XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q=1202, 
  XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd=1203, 
  XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d=1204, 
  XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq=1205, 
  XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q=1206, 
  XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb=1207, 
  XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb=1208, 
  XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb=1209, 
  XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb=1210, 
  XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb=1211, 
  XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb=1212, 
  XED_IFORM_PEXTRW_GPR32_MMXq_IMMb=1213, 
  XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb=1214, 
  XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb=1215, 
  XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb=1216, 
  XED_IFORM_PF2ID_MMXq_MEMq=1217, 
  XED_IFORM_PF2ID_MMXq_MMXq=1218, 
  XED_IFORM_PF2IW_MMXq_MEMq=1219, 
  XED_IFORM_PF2IW_MMXq_MMXq=1220, 
  XED_IFORM_PFACC_MMXq_MEMq=1221, 
  XED_IFORM_PFACC_MMXq_MMXq=1222, 
  XED_IFORM_PFADD_MMXq_MEMq=1223, 
  XED_IFORM_PFADD_MMXq_MMXq=1224, 
  XED_IFORM_PFCMPEQ_MMXq_MEMq=1225, 
  XED_IFORM_PFCMPEQ_MMXq_MMXq=1226, 
  XED_IFORM_PFCMPGE_MMXq_MEMq=1227, 
  XED_IFORM_PFCMPGE_MMXq_MMXq=1228, 
  XED_IFORM_PFCMPGT_MMXq_MEMq=1229, 
  XED_IFORM_PFCMPGT_MMXq_MMXq=1230, 
  XED_IFORM_PFMAX_MMXq_MEMq=1231, 
  XED_IFORM_PFMAX_MMXq_MMXq=1232, 
  XED_IFORM_PFMIN_MMXq_MEMq=1233, 
  XED_IFORM_PFMIN_MMXq_MMXq=1234, 
  XED_IFORM_PFMUL_MMXq_MEMq=1235, 
  XED_IFORM_PFMUL_MMXq_MMXq=1236, 
  XED_IFORM_PFNACC_MMXq_MEMq=1237, 
  XED_IFORM_PFNACC_MMXq_MMXq=1238, 
  XED_IFORM_PFPNACC_MMXq_MEMq=1239, 
  XED_IFORM_PFPNACC_MMXq_MMXq=1240, 
  XED_IFORM_PFRCP_MMXq_MEMq=1241, 
  XED_IFORM_PFRCP_MMXq_MMXq=1242, 
  XED_IFORM_PFRCPIT1_MMXq_MEMq=1243, 
  XED_IFORM_PFRCPIT1_MMXq_MMXq=1244, 
  XED_IFORM_PFRCPIT2_MMXq_MEMq=1245, 
  XED_IFORM_PFRCPIT2_MMXq_MMXq=1246, 
  XED_IFORM_PFRSQIT1_MMXq_MEMq=1247, 
  XED_IFORM_PFRSQIT1_MMXq_MMXq=1248, 
  XED_IFORM_PFRSQRT_MMXq_MEMq=1249, 
  XED_IFORM_PFRSQRT_MMXq_MMXq=1250, 
  XED_IFORM_PFSUB_MMXq_MEMq=1251, 
  XED_IFORM_PFSUB_MMXq_MMXq=1252, 
  XED_IFORM_PFSUBR_MMXq_MEMq=1253, 
  XED_IFORM_PFSUBR_MMXq_MMXq=1254, 
  XED_IFORM_PHADDD_MMXq_MEMq=1255, 
  XED_IFORM_PHADDD_MMXq_MMXq=1256, 
  XED_IFORM_PHADDD_XMMdq_MEMdq=1257, 
  XED_IFORM_PHADDD_XMMdq_XMMdq=1258, 
  XED_IFORM_PHADDSW_MMXq_MEMq=1259, 
  XED_IFORM_PHADDSW_MMXq_MMXq=1260, 
  XED_IFORM_PHADDSW_XMMdq_MEMdq=1261, 
  XED_IFORM_PHADDSW_XMMdq_XMMdq=1262, 
  XED_IFORM_PHADDW_MMXq_MEMq=1263, 
  XED_IFORM_PHADDW_MMXq_MMXq=1264, 
  XED_IFORM_PHADDW_XMMdq_MEMdq=1265, 
  XED_IFORM_PHADDW_XMMdq_XMMdq=1266, 
  XED_IFORM_PHMINPOSUW_XMMdq_MEMdq=1267, 
  XED_IFORM_PHMINPOSUW_XMMdq_XMMdq=1268, 
  XED_IFORM_PHSUBD_MMXq_MEMq=1269, 
  XED_IFORM_PHSUBD_MMXq_MMXq=1270, 
  XED_IFORM_PHSUBD_XMMdq_MEMdq=1271, 
  XED_IFORM_PHSUBD_XMMdq_XMMdq=1272, 
  XED_IFORM_PHSUBSW_MMXq_MEMq=1273, 
  XED_IFORM_PHSUBSW_MMXq_MMXq=1274, 
  XED_IFORM_PHSUBSW_XMMdq_MEMdq=1275, 
  XED_IFORM_PHSUBSW_XMMdq_XMMdq=1276, 
  XED_IFORM_PHSUBW_MMXq_MEMq=1277, 
  XED_IFORM_PHSUBW_MMXq_MMXq=1278, 
  XED_IFORM_PHSUBW_XMMdq_MEMdq=1279, 
  XED_IFORM_PHSUBW_XMMdq_XMMdq=1280, 
  XED_IFORM_PI2FD_MMXq_MEMq=1281, 
  XED_IFORM_PI2FD_MMXq_MMXq=1282, 
  XED_IFORM_PI2FW_MMXq_MEMq=1283, 
  XED_IFORM_PI2FW_MMXq_MMXq=1284, 
  XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb=1285, 
  XED_IFORM_PINSRB_XMMdq_MEMb_IMMb=1286, 
  XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb=1287, 
  XED_IFORM_PINSRD_XMMdq_MEMd_IMMb=1288, 
  XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb=1289, 
  XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb=1290, 
  XED_IFORM_PINSRW_MMXq_GPR32_IMMb=1291, 
  XED_IFORM_PINSRW_MMXq_MEMw_IMMb=1292, 
  XED_IFORM_PINSRW_XMMdq_GPR32_IMMb=1293, 
  XED_IFORM_PINSRW_XMMdq_MEMw_IMMb=1294, 
  XED_IFORM_PMADDUBSW_MMXq_MEMq=1295, 
  XED_IFORM_PMADDUBSW_MMXq_MMXq=1296, 
  XED_IFORM_PMADDUBSW_XMMdq_MEMdq=1297, 
  XED_IFORM_PMADDUBSW_XMMdq_XMMdq=1298, 
  XED_IFORM_PMADDWD_MMXq_MEMq=1299, 
  XED_IFORM_PMADDWD_MMXq_MMXq=1300, 
  XED_IFORM_PMADDWD_XMMdq_MEMdq=1301, 
  XED_IFORM_PMADDWD_XMMdq_XMMdq=1302, 
  XED_IFORM_PMAXSB_XMMdq_MEMdq=1303, 
  XED_IFORM_PMAXSB_XMMdq_XMMdq=1304, 
  XED_IFORM_PMAXSD_XMMdq_MEMdq=1305, 
  XED_IFORM_PMAXSD_XMMdq_XMMdq=1306, 
  XED_IFORM_PMAXSW_MMXq_MEMq=1307, 
  XED_IFORM_PMAXSW_MMXq_MMXq=1308, 
  XED_IFORM_PMAXSW_XMMdq_MEMdq=1309, 
  XED_IFORM_PMAXSW_XMMdq_XMMdq=1310, 
  XED_IFORM_PMAXUB_MMXq_MEMq=1311, 
  XED_IFORM_PMAXUB_MMXq_MMXq=1312, 
  XED_IFORM_PMAXUB_XMMdq_MEMdq=1313, 
  XED_IFORM_PMAXUB_XMMdq_XMMdq=1314, 
  XED_IFORM_PMAXUD_XMMdq_MEMdq=1315, 
  XED_IFORM_PMAXUD_XMMdq_XMMdq=1316, 
  XED_IFORM_PMAXUW_XMMdq_MEMdq=1317, 
  XED_IFORM_PMAXUW_XMMdq_XMMdq=1318, 
  XED_IFORM_PMINSB_XMMdq_MEMdq=1319, 
  XED_IFORM_PMINSB_XMMdq_XMMdq=1320, 
  XED_IFORM_PMINSD_XMMdq_MEMdq=1321, 
  XED_IFORM_PMINSD_XMMdq_XMMdq=1322, 
  XED_IFORM_PMINSW_MMXq_MEMq=1323, 
  XED_IFORM_PMINSW_MMXq_MMXq=1324, 
  XED_IFORM_PMINSW_XMMdq_MEMdq=1325, 
  XED_IFORM_PMINSW_XMMdq_XMMdq=1326, 
  XED_IFORM_PMINUB_MMXq_MEMq=1327, 
  XED_IFORM_PMINUB_MMXq_MMXq=1328, 
  XED_IFORM_PMINUB_XMMdq_MEMdq=1329, 
  XED_IFORM_PMINUB_XMMdq_XMMdq=1330, 
  XED_IFORM_PMINUD_XMMdq_MEMdq=1331, 
  XED_IFORM_PMINUD_XMMdq_XMMdq=1332, 
  XED_IFORM_PMINUW_XMMdq_MEMdq=1333, 
  XED_IFORM_PMINUW_XMMdq_XMMdq=1334, 
  XED_IFORM_PMOVMSKB_GPR32_MMXq=1335, 
  XED_IFORM_PMOVMSKB_GPR32_XMMdq=1336, 
  XED_IFORM_PMOVSXBD_XMMdq_MEMd=1337, 
  XED_IFORM_PMOVSXBD_XMMdq_XMMd=1338, 
  XED_IFORM_PMOVSXBQ_XMMdq_MEMw=1339, 
  XED_IFORM_PMOVSXBQ_XMMdq_XMMw=1340, 
  XED_IFORM_PMOVSXBW_XMMdq_MEMq=1341, 
  XED_IFORM_PMOVSXBW_XMMdq_XMMq=1342, 
  XED_IFORM_PMOVSXDQ_XMMdq_MEMq=1343, 
  XED_IFORM_PMOVSXDQ_XMMdq_XMMq=1344, 
  XED_IFORM_PMOVSXWD_XMMdq_MEMq=1345, 
  XED_IFORM_PMOVSXWD_XMMdq_XMMq=1346, 
  XED_IFORM_PMOVSXWQ_XMMdq_MEMd=1347, 
  XED_IFORM_PMOVSXWQ_XMMdq_XMMd=1348, 
  XED_IFORM_PMOVZXBD_XMMdq_MEMd=1349, 
  XED_IFORM_PMOVZXBD_XMMdq_XMMd=1350, 
  XED_IFORM_PMOVZXBQ_XMMdq_MEMw=1351, 
  XED_IFORM_PMOVZXBQ_XMMdq_XMMw=1352, 
  XED_IFORM_PMOVZXBW_XMMdq_MEMq=1353, 
  XED_IFORM_PMOVZXBW_XMMdq_XMMq=1354, 
  XED_IFORM_PMOVZXDQ_XMMdq_MEMq=1355, 
  XED_IFORM_PMOVZXDQ_XMMdq_XMMq=1356, 
  XED_IFORM_PMOVZXWD_XMMdq_MEMq=1357, 
  XED_IFORM_PMOVZXWD_XMMdq_XMMq=1358, 
  XED_IFORM_PMOVZXWQ_XMMdq_MEMd=1359, 
  XED_IFORM_PMOVZXWQ_XMMdq_XMMd=1360, 
  XED_IFORM_PMULDQ_XMMdq_MEMdq=1361, 
  XED_IFORM_PMULDQ_XMMdq_XMMdq=1362, 
  XED_IFORM_PMULHRSW_MMXq_MEMq=1363, 
  XED_IFORM_PMULHRSW_MMXq_MMXq=1364, 
  XED_IFORM_PMULHRSW_XMMdq_MEMdq=1365, 
  XED_IFORM_PMULHRSW_XMMdq_XMMdq=1366, 
  XED_IFORM_PMULHRW_MMXq_MEMq=1367, 
  XED_IFORM_PMULHRW_MMXq_MMXq=1368, 
  XED_IFORM_PMULHUW_MMXq_MEMq=1369, 
  XED_IFORM_PMULHUW_MMXq_MMXq=1370, 
  XED_IFORM_PMULHUW_XMMdq_MEMdq=1371, 
  XED_IFORM_PMULHUW_XMMdq_XMMdq=1372, 
  XED_IFORM_PMULHW_MMXq_MEMq=1373, 
  XED_IFORM_PMULHW_MMXq_MMXq=1374, 
  XED_IFORM_PMULHW_XMMdq_MEMdq=1375, 
  XED_IFORM_PMULHW_XMMdq_XMMdq=1376, 
  XED_IFORM_PMULLD_XMMdq_MEMdq=1377, 
  XED_IFORM_PMULLD_XMMdq_XMMdq=1378, 
  XED_IFORM_PMULLW_MMXq_MEMq=1379, 
  XED_IFORM_PMULLW_MMXq_MMXq=1380, 
  XED_IFORM_PMULLW_XMMdq_MEMdq=1381, 
  XED_IFORM_PMULLW_XMMdq_XMMdq=1382, 
  XED_IFORM_PMULUDQ_MMXq_MEMq=1383, 
  XED_IFORM_PMULUDQ_MMXq_MMXq=1384, 
  XED_IFORM_PMULUDQ_XMMdq_MEMdq=1385, 
  XED_IFORM_PMULUDQ_XMMdq_XMMdq=1386, 
  XED_IFORM_POP_DS=1387, 
  XED_IFORM_POP_ES=1388, 
  XED_IFORM_POP_FS=1389, 
  XED_IFORM_POP_GPRv_58=1390, 
  XED_IFORM_POP_GPRv_8F=1391, 
  XED_IFORM_POP_GS=1392, 
  XED_IFORM_POP_MEMv=1393, 
  XED_IFORM_POP_SS=1394, 
  XED_IFORM_POPA=1395, 
  XED_IFORM_POPAD=1396, 
  XED_IFORM_POPCNT_GPRv_GPRv=1397, 
  XED_IFORM_POPCNT_GPRv_MEMv=1398, 
  XED_IFORM_POPF=1399, 
  XED_IFORM_POPFD=1400, 
  XED_IFORM_POPFQ=1401, 
  XED_IFORM_POR_MMXq_MEMq=1402, 
  XED_IFORM_POR_MMXq_MMXq=1403, 
  XED_IFORM_POR_XMMdq_MEMdq=1404, 
  XED_IFORM_POR_XMMdq_XMMdq=1405, 
  XED_IFORM_PREFETCHNTA_MEMmprefetch=1406, 
  XED_IFORM_PREFETCHT0_MEMmprefetch=1407, 
  XED_IFORM_PREFETCHT1_MEMmprefetch=1408, 
  XED_IFORM_PREFETCHT2_MEMmprefetch=1409, 
  XED_IFORM_PREFETCHW_0F0Dr1=1410, 
  XED_IFORM_PREFETCHW_0F0Dr3=1411, 
  XED_IFORM_PREFETCHWT1_MEMu8=1412, 
  XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch=1413, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr4=1414, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr5=1415, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr6=1416, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr7=1417, 
  XED_IFORM_PSADBW_MMXq_MEMq=1418, 
  XED_IFORM_PSADBW_MMXq_MMXq=1419, 
  XED_IFORM_PSADBW_XMMdq_MEMdq=1420, 
  XED_IFORM_PSADBW_XMMdq_XMMdq=1421, 
  XED_IFORM_PSHUFB_MMXq_MEMq=1422, 
  XED_IFORM_PSHUFB_MMXq_MMXq=1423, 
  XED_IFORM_PSHUFB_XMMdq_MEMdq=1424, 
  XED_IFORM_PSHUFB_XMMdq_XMMdq=1425, 
  XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb=1426, 
  XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb=1427, 
  XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb=1428, 
  XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb=1429, 
  XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb=1430, 
  XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb=1431, 
  XED_IFORM_PSHUFW_MMXq_MEMq_IMMb=1432, 
  XED_IFORM_PSHUFW_MMXq_MMXq_IMMb=1433, 
  XED_IFORM_PSIGNB_MMXq_MEMq=1434, 
  XED_IFORM_PSIGNB_MMXq_MMXq=1435, 
  XED_IFORM_PSIGNB_XMMdq_MEMdq=1436, 
  XED_IFORM_PSIGNB_XMMdq_XMMdq=1437, 
  XED_IFORM_PSIGND_MMXq_MEMq=1438, 
  XED_IFORM_PSIGND_MMXq_MMXq=1439, 
  XED_IFORM_PSIGND_XMMdq_MEMdq=1440, 
  XED_IFORM_PSIGND_XMMdq_XMMdq=1441, 
  XED_IFORM_PSIGNW_MMXq_MEMq=1442, 
  XED_IFORM_PSIGNW_MMXq_MMXq=1443, 
  XED_IFORM_PSIGNW_XMMdq_MEMdq=1444, 
  XED_IFORM_PSIGNW_XMMdq_XMMdq=1445, 
  XED_IFORM_PSLLD_MMXq_IMMb=1446, 
  XED_IFORM_PSLLD_MMXq_MEMq=1447, 
  XED_IFORM_PSLLD_MMXq_MMXq=1448, 
  XED_IFORM_PSLLD_XMMdq_IMMb=1449, 
  XED_IFORM_PSLLD_XMMdq_MEMdq=1450, 
  XED_IFORM_PSLLD_XMMdq_XMMdq=1451, 
  XED_IFORM_PSLLDQ_XMMdq_IMMb=1452, 
  XED_IFORM_PSLLQ_MMXq_IMMb=1453, 
  XED_IFORM_PSLLQ_MMXq_MEMq=1454, 
  XED_IFORM_PSLLQ_MMXq_MMXq=1455, 
  XED_IFORM_PSLLQ_XMMdq_IMMb=1456, 
  XED_IFORM_PSLLQ_XMMdq_MEMdq=1457, 
  XED_IFORM_PSLLQ_XMMdq_XMMdq=1458, 
  XED_IFORM_PSLLW_MMXq_IMMb=1459, 
  XED_IFORM_PSLLW_MMXq_MEMq=1460, 
  XED_IFORM_PSLLW_MMXq_MMXq=1461, 
  XED_IFORM_PSLLW_XMMdq_IMMb=1462, 
  XED_IFORM_PSLLW_XMMdq_MEMdq=1463, 
  XED_IFORM_PSLLW_XMMdq_XMMdq=1464, 
  XED_IFORM_PSMASH_RAX=1465, 
  XED_IFORM_PSRAD_MMXq_IMMb=1466, 
  XED_IFORM_PSRAD_MMXq_MEMq=1467, 
  XED_IFORM_PSRAD_MMXq_MMXq=1468, 
  XED_IFORM_PSRAD_XMMdq_IMMb=1469, 
  XED_IFORM_PSRAD_XMMdq_MEMdq=1470, 
  XED_IFORM_PSRAD_XMMdq_XMMdq=1471, 
  XED_IFORM_PSRAW_MMXq_IMMb=1472, 
  XED_IFORM_PSRAW_MMXq_MEMq=1473, 
  XED_IFORM_PSRAW_MMXq_MMXq=1474, 
  XED_IFORM_PSRAW_XMMdq_IMMb=1475, 
  XED_IFORM_PSRAW_XMMdq_MEMdq=1476, 
  XED_IFORM_PSRAW_XMMdq_XMMdq=1477, 
  XED_IFORM_PSRLD_MMXq_IMMb=1478, 
  XED_IFORM_PSRLD_MMXq_MEMq=1479, 
  XED_IFORM_PSRLD_MMXq_MMXq=1480, 
  XED_IFORM_PSRLD_XMMdq_IMMb=1481, 
  XED_IFORM_PSRLD_XMMdq_MEMdq=1482, 
  XED_IFORM_PSRLD_XMMdq_XMMdq=1483, 
  XED_IFORM_PSRLDQ_XMMdq_IMMb=1484, 
  XED_IFORM_PSRLQ_MMXq_IMMb=1485, 
  XED_IFORM_PSRLQ_MMXq_MEMq=1486, 
  XED_IFORM_PSRLQ_MMXq_MMXq=1487, 
  XED_IFORM_PSRLQ_XMMdq_IMMb=1488, 
  XED_IFORM_PSRLQ_XMMdq_MEMdq=1489, 
  XED_IFORM_PSRLQ_XMMdq_XMMdq=1490, 
  XED_IFORM_PSRLW_MMXq_IMMb=1491, 
  XED_IFORM_PSRLW_MMXq_MEMq=1492, 
  XED_IFORM_PSRLW_MMXq_MMXq=1493, 
  XED_IFORM_PSRLW_XMMdq_IMMb=1494, 
  XED_IFORM_PSRLW_XMMdq_MEMdq=1495, 
  XED_IFORM_PSRLW_XMMdq_XMMdq=1496, 
  XED_IFORM_PSUBB_MMXq_MEMq=1497, 
  XED_IFORM_PSUBB_MMXq_MMXq=1498, 
  XED_IFORM_PSUBB_XMMdq_MEMdq=1499, 
  XED_IFORM_PSUBB_XMMdq_XMMdq=1500, 
  XED_IFORM_PSUBD_MMXq_MEMq=1501, 
  XED_IFORM_PSUBD_MMXq_MMXq=1502, 
  XED_IFORM_PSUBD_XMMdq_MEMdq=1503, 
  XED_IFORM_PSUBD_XMMdq_XMMdq=1504, 
  XED_IFORM_PSUBQ_MMXq_MEMq=1505, 
  XED_IFORM_PSUBQ_MMXq_MMXq=1506, 
  XED_IFORM_PSUBQ_XMMdq_MEMdq=1507, 
  XED_IFORM_PSUBQ_XMMdq_XMMdq=1508, 
  XED_IFORM_PSUBSB_MMXq_MEMq=1509, 
  XED_IFORM_PSUBSB_MMXq_MMXq=1510, 
  XED_IFORM_PSUBSB_XMMdq_MEMdq=1511, 
  XED_IFORM_PSUBSB_XMMdq_XMMdq=1512, 
  XED_IFORM_PSUBSW_MMXq_MEMq=1513, 
  XED_IFORM_PSUBSW_MMXq_MMXq=1514, 
  XED_IFORM_PSUBSW_XMMdq_MEMdq=1515, 
  XED_IFORM_PSUBSW_XMMdq_XMMdq=1516, 
  XED_IFORM_PSUBUSB_MMXq_MEMq=1517, 
  XED_IFORM_PSUBUSB_MMXq_MMXq=1518, 
  XED_IFORM_PSUBUSB_XMMdq_MEMdq=1519, 
  XED_IFORM_PSUBUSB_XMMdq_XMMdq=1520, 
  XED_IFORM_PSUBUSW_MMXq_MEMq=1521, 
  XED_IFORM_PSUBUSW_MMXq_MMXq=1522, 
  XED_IFORM_PSUBUSW_XMMdq_MEMdq=1523, 
  XED_IFORM_PSUBUSW_XMMdq_XMMdq=1524, 
  XED_IFORM_PSUBW_MMXq_MEMq=1525, 
  XED_IFORM_PSUBW_MMXq_MMXq=1526, 
  XED_IFORM_PSUBW_XMMdq_MEMdq=1527, 
  XED_IFORM_PSUBW_XMMdq_XMMdq=1528, 
  XED_IFORM_PSWAPD_MMXq_MEMq=1529, 
  XED_IFORM_PSWAPD_MMXq_MMXq=1530, 
  XED_IFORM_PTEST_XMMdq_MEMdq=1531, 
  XED_IFORM_PTEST_XMMdq_XMMdq=1532, 
  XED_IFORM_PTWRITE_GPRy=1533, 
  XED_IFORM_PTWRITE_MEMy=1534, 
  XED_IFORM_PUNPCKHBW_MMXq_MEMq=1535, 
  XED_IFORM_PUNPCKHBW_MMXq_MMXd=1536, 
  XED_IFORM_PUNPCKHBW_XMMdq_MEMdq=1537, 
  XED_IFORM_PUNPCKHBW_XMMdq_XMMq=1538, 
  XED_IFORM_PUNPCKHDQ_MMXq_MEMq=1539, 
  XED_IFORM_PUNPCKHDQ_MMXq_MMXd=1540, 
  XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq=1541, 
  XED_IFORM_PUNPCKHDQ_XMMdq_XMMq=1542, 
  XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq=1543, 
  XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq=1544, 
  XED_IFORM_PUNPCKHWD_MMXq_MEMq=1545, 
  XED_IFORM_PUNPCKHWD_MMXq_MMXd=1546, 
  XED_IFORM_PUNPCKHWD_XMMdq_MEMdq=1547, 
  XED_IFORM_PUNPCKHWD_XMMdq_XMMq=1548, 
  XED_IFORM_PUNPCKLBW_MMXq_MEMd=1549, 
  XED_IFORM_PUNPCKLBW_MMXq_MMXd=1550, 
  XED_IFORM_PUNPCKLBW_XMMdq_MEMdq=1551, 
  XED_IFORM_PUNPCKLBW_XMMdq_XMMq=1552, 
  XED_IFORM_PUNPCKLDQ_MMXq_MEMd=1553, 
  XED_IFORM_PUNPCKLDQ_MMXq_MMXd=1554, 
  XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq=1555, 
  XED_IFORM_PUNPCKLDQ_XMMdq_XMMq=1556, 
  XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq=1557, 
  XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq=1558, 
  XED_IFORM_PUNPCKLWD_MMXq_MEMd=1559, 
  XED_IFORM_PUNPCKLWD_MMXq_MMXd=1560, 
  XED_IFORM_PUNPCKLWD_XMMdq_MEMdq=1561, 
  XED_IFORM_PUNPCKLWD_XMMdq_XMMq=1562, 
  XED_IFORM_PUSH_CS=1563, 
  XED_IFORM_PUSH_DS=1564, 
  XED_IFORM_PUSH_ES=1565, 
  XED_IFORM_PUSH_FS=1566, 
  XED_IFORM_PUSH_GPRv_50=1567, 
  XED_IFORM_PUSH_GPRv_FFr6=1568, 
  XED_IFORM_PUSH_GS=1569, 
  XED_IFORM_PUSH_IMMb=1570, 
  XED_IFORM_PUSH_IMMz=1571, 
  XED_IFORM_PUSH_MEMv=1572, 
  XED_IFORM_PUSH_SS=1573, 
  XED_IFORM_PUSHA=1574, 
  XED_IFORM_PUSHAD=1575, 
  XED_IFORM_PUSHF=1576, 
  XED_IFORM_PUSHFD=1577, 
  XED_IFORM_PUSHFQ=1578, 
  XED_IFORM_PVALIDATE_RAX_ECX_EDX=1579, 
  XED_IFORM_PXOR_MMXq_MEMq=1580, 
  XED_IFORM_PXOR_MMXq_MMXq=1581, 
  XED_IFORM_PXOR_XMMdq_MEMdq=1582, 
  XED_IFORM_PXOR_XMMdq_XMMdq=1583, 
  XED_IFORM_RCL_GPR8_CL=1584, 
  XED_IFORM_RCL_GPR8_IMMb=1585, 
  XED_IFORM_RCL_GPR8_ONE=1586, 
  XED_IFORM_RCL_GPRv_CL=1587, 
  XED_IFORM_RCL_GPRv_IMMb=1588, 
  XED_IFORM_RCL_GPRv_ONE=1589, 
  XED_IFORM_RCL_MEMb_CL=1590, 
  XED_IFORM_RCL_MEMb_IMMb=1591, 
  XED_IFORM_RCL_MEMb_ONE=1592, 
  XED_IFORM_RCL_MEMv_CL=1593, 
  XED_IFORM_RCL_MEMv_IMMb=1594, 
  XED_IFORM_RCL_MEMv_ONE=1595, 
  XED_IFORM_RCPPS_XMMps_MEMps=1596, 
  XED_IFORM_RCPPS_XMMps_XMMps=1597, 
  XED_IFORM_RCPSS_XMMss_MEMss=1598, 
  XED_IFORM_RCPSS_XMMss_XMMss=1599, 
  XED_IFORM_RCR_GPR8_CL=1600, 
  XED_IFORM_RCR_GPR8_IMMb=1601, 
  XED_IFORM_RCR_GPR8_ONE=1602, 
  XED_IFORM_RCR_GPRv_CL=1603, 
  XED_IFORM_RCR_GPRv_IMMb=1604, 
  XED_IFORM_RCR_GPRv_ONE=1605, 
  XED_IFORM_RCR_MEMb_CL=1606, 
  XED_IFORM_RCR_MEMb_IMMb=1607, 
  XED_IFORM_RCR_MEMb_ONE=1608, 
  XED_IFORM_RCR_MEMv_CL=1609, 
  XED_IFORM_RCR_MEMv_IMMb=1610, 
  XED_IFORM_RCR_MEMv_ONE=1611, 
  XED_IFORM_RDFSBASE_GPRy=1612, 
  XED_IFORM_RDGSBASE_GPRy=1613, 
  XED_IFORM_RDMSR=1614, 
  XED_IFORM_RDPID_GPR32u32=1615, 
  XED_IFORM_RDPID_GPR64u64=1616, 
  XED_IFORM_RDPKRU=1617, 
  XED_IFORM_RDPMC=1618, 
  XED_IFORM_RDPRU=1619, 
  XED_IFORM_RDRAND_GPRv=1620, 
  XED_IFORM_RDSEED_GPRv=1621, 
  XED_IFORM_RDSSPD_GPR32u32=1622, 
  XED_IFORM_RDSSPQ_GPR64u64=1623, 
  XED_IFORM_RDTSC=1624, 
  XED_IFORM_RDTSCP=1625, 
  XED_IFORM_REPE_CMPSB=1626, 
  XED_IFORM_REPE_CMPSD=1627, 
  XED_IFORM_REPE_CMPSQ=1628, 
  XED_IFORM_REPE_CMPSW=1629, 
  XED_IFORM_REPE_SCASB=1630, 
  XED_IFORM_REPE_SCASD=1631, 
  XED_IFORM_REPE_SCASQ=1632, 
  XED_IFORM_REPE_SCASW=1633, 
  XED_IFORM_REPNE_CMPSB=1634, 
  XED_IFORM_REPNE_CMPSD=1635, 
  XED_IFORM_REPNE_CMPSQ=1636, 
  XED_IFORM_REPNE_CMPSW=1637, 
  XED_IFORM_REPNE_SCASB=1638, 
  XED_IFORM_REPNE_SCASD=1639, 
  XED_IFORM_REPNE_SCASQ=1640, 
  XED_IFORM_REPNE_SCASW=1641, 
  XED_IFORM_REP_INSB=1642, 
  XED_IFORM_REP_INSD=1643, 
  XED_IFORM_REP_INSW=1644, 
  XED_IFORM_REP_LODSB=1645, 
  XED_IFORM_REP_LODSD=1646, 
  XED_IFORM_REP_LODSQ=1647, 
  XED_IFORM_REP_LODSW=1648, 
  XED_IFORM_REP_MONTMUL=1649, 
  XED_IFORM_REP_MOVSB=1650, 
  XED_IFORM_REP_MOVSD=1651, 
  XED_IFORM_REP_MOVSQ=1652, 
  XED_IFORM_REP_MOVSW=1653, 
  XED_IFORM_REP_OUTSB=1654, 
  XED_IFORM_REP_OUTSD=1655, 
  XED_IFORM_REP_OUTSW=1656, 
  XED_IFORM_REP_STOSB=1657, 
  XED_IFORM_REP_STOSD=1658, 
  XED_IFORM_REP_STOSQ=1659, 
  XED_IFORM_REP_STOSW=1660, 
  XED_IFORM_REP_XCRYPTCBC=1661, 
  XED_IFORM_REP_XCRYPTCFB=1662, 
  XED_IFORM_REP_XCRYPTCTR=1663, 
  XED_IFORM_REP_XCRYPTECB=1664, 
  XED_IFORM_REP_XCRYPTOFB=1665, 
  XED_IFORM_REP_XSHA1=1666, 
  XED_IFORM_REP_XSHA256=1667, 
  XED_IFORM_REP_XSTORE=1668, 
  XED_IFORM_RET_FAR=1669, 
  XED_IFORM_RET_FAR_IMMw=1670, 
  XED_IFORM_RET_NEAR=1671, 
  XED_IFORM_RET_NEAR_IMMw=1672, 
  XED_IFORM_RMPADJUST_RAX_RCX_RDX=1673, 
  XED_IFORM_RMPUPDATE_RAX_RCX=1674, 
  XED_IFORM_ROL_GPR8_CL=1675, 
  XED_IFORM_ROL_GPR8_IMMb=1676, 
  XED_IFORM_ROL_GPR8_ONE=1677, 
  XED_IFORM_ROL_GPRv_CL=1678, 
  XED_IFORM_ROL_GPRv_IMMb=1679, 
  XED_IFORM_ROL_GPRv_ONE=1680, 
  XED_IFORM_ROL_MEMb_CL=1681, 
  XED_IFORM_ROL_MEMb_IMMb=1682, 
  XED_IFORM_ROL_MEMb_ONE=1683, 
  XED_IFORM_ROL_MEMv_CL=1684, 
  XED_IFORM_ROL_MEMv_IMMb=1685, 
  XED_IFORM_ROL_MEMv_ONE=1686, 
  XED_IFORM_ROR_GPR8_CL=1687, 
  XED_IFORM_ROR_GPR8_IMMb=1688, 
  XED_IFORM_ROR_GPR8_ONE=1689, 
  XED_IFORM_ROR_GPRv_CL=1690, 
  XED_IFORM_ROR_GPRv_IMMb=1691, 
  XED_IFORM_ROR_GPRv_ONE=1692, 
  XED_IFORM_ROR_MEMb_CL=1693, 
  XED_IFORM_ROR_MEMb_IMMb=1694, 
  XED_IFORM_ROR_MEMb_ONE=1695, 
  XED_IFORM_ROR_MEMv_CL=1696, 
  XED_IFORM_ROR_MEMv_IMMb=1697, 
  XED_IFORM_ROR_MEMv_ONE=1698, 
  XED_IFORM_RORX_VGPR32d_MEMd_IMMb=1699, 
  XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb=1700, 
  XED_IFORM_RORX_VGPR64q_MEMq_IMMb=1701, 
  XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb=1702, 
  XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb=1703, 
  XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb=1704, 
  XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb=1705, 
  XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb=1706, 
  XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb=1707, 
  XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb=1708, 
  XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb=1709, 
  XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb=1710, 
  XED_IFORM_RSM=1711, 
  XED_IFORM_RSQRTPS_XMMps_MEMps=1712, 
  XED_IFORM_RSQRTPS_XMMps_XMMps=1713, 
  XED_IFORM_RSQRTSS_XMMss_MEMss=1714, 
  XED_IFORM_RSQRTSS_XMMss_XMMss=1715, 
  XED_IFORM_RSTORSSP_MEMu64=1716, 
  XED_IFORM_SAHF=1717, 
  XED_IFORM_SALC=1718, 
  XED_IFORM_SAR_GPR8_CL=1719, 
  XED_IFORM_SAR_GPR8_IMMb=1720, 
  XED_IFORM_SAR_GPR8_ONE=1721, 
  XED_IFORM_SAR_GPRv_CL=1722, 
  XED_IFORM_SAR_GPRv_IMMb=1723, 
  XED_IFORM_SAR_GPRv_ONE=1724, 
  XED_IFORM_SAR_MEMb_CL=1725, 
  XED_IFORM_SAR_MEMb_IMMb=1726, 
  XED_IFORM_SAR_MEMb_ONE=1727, 
  XED_IFORM_SAR_MEMv_CL=1728, 
  XED_IFORM_SAR_MEMv_IMMb=1729, 
  XED_IFORM_SAR_MEMv_ONE=1730, 
  XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d=1731, 
  XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d=1732, 
  XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q=1733, 
  XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q=1734, 
  XED_IFORM_SAVEPREVSSP=1735, 
  XED_IFORM_SBB_AL_IMMb=1736, 
  XED_IFORM_SBB_GPR8_GPR8_18=1737, 
  XED_IFORM_SBB_GPR8_GPR8_1A=1738, 
  XED_IFORM_SBB_GPR8_IMMb_80r3=1739, 
  XED_IFORM_SBB_GPR8_IMMb_82r3=1740, 
  XED_IFORM_SBB_GPR8_MEMb=1741, 
  XED_IFORM_SBB_GPRv_GPRv_19=1742, 
  XED_IFORM_SBB_GPRv_GPRv_1B=1743, 
  XED_IFORM_SBB_GPRv_IMMb=1744, 
  XED_IFORM_SBB_GPRv_IMMz=1745, 
  XED_IFORM_SBB_GPRv_MEMv=1746, 
  XED_IFORM_SBB_MEMb_GPR8=1747, 
  XED_IFORM_SBB_MEMb_IMMb_80r3=1748, 
  XED_IFORM_SBB_MEMb_IMMb_82r3=1749, 
  XED_IFORM_SBB_MEMv_GPRv=1750, 
  XED_IFORM_SBB_MEMv_IMMb=1751, 
  XED_IFORM_SBB_MEMv_IMMz=1752, 
  XED_IFORM_SBB_OrAX_IMMz=1753, 
  XED_IFORM_SBB_LOCK_MEMb_GPR8=1754, 
  XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3=1755, 
  XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3=1756, 
  XED_IFORM_SBB_LOCK_MEMv_GPRv=1757, 
  XED_IFORM_SBB_LOCK_MEMv_IMMb=1758, 
  XED_IFORM_SBB_LOCK_MEMv_IMMz=1759, 
  XED_IFORM_SCASB=1760, 
  XED_IFORM_SCASD=1761, 
  XED_IFORM_SCASQ=1762, 
  XED_IFORM_SCASW=1763, 
  XED_IFORM_SERIALIZE=1764, 
  XED_IFORM_SETB_GPR8=1765, 
  XED_IFORM_SETB_MEMb=1766, 
  XED_IFORM_SETBE_GPR8=1767, 
  XED_IFORM_SETBE_MEMb=1768, 
  XED_IFORM_SETL_GPR8=1769, 
  XED_IFORM_SETL_MEMb=1770, 
  XED_IFORM_SETLE_GPR8=1771, 
  XED_IFORM_SETLE_MEMb=1772, 
  XED_IFORM_SETNB_GPR8=1773, 
  XED_IFORM_SETNB_MEMb=1774, 
  XED_IFORM_SETNBE_GPR8=1775, 
  XED_IFORM_SETNBE_MEMb=1776, 
  XED_IFORM_SETNL_GPR8=1777, 
  XED_IFORM_SETNL_MEMb=1778, 
  XED_IFORM_SETNLE_GPR8=1779, 
  XED_IFORM_SETNLE_MEMb=1780, 
  XED_IFORM_SETNO_GPR8=1781, 
  XED_IFORM_SETNO_MEMb=1782, 
  XED_IFORM_SETNP_GPR8=1783, 
  XED_IFORM_SETNP_MEMb=1784, 
  XED_IFORM_SETNS_GPR8=1785, 
  XED_IFORM_SETNS_MEMb=1786, 
  XED_IFORM_SETNZ_GPR8=1787, 
  XED_IFORM_SETNZ_MEMb=1788, 
  XED_IFORM_SETO_GPR8=1789, 
  XED_IFORM_SETO_MEMb=1790, 
  XED_IFORM_SETP_GPR8=1791, 
  XED_IFORM_SETP_MEMb=1792, 
  XED_IFORM_SETS_GPR8=1793, 
  XED_IFORM_SETS_MEMb=1794, 
  XED_IFORM_SETSSBSY=1795, 
  XED_IFORM_SETZ_GPR8=1796, 
  XED_IFORM_SETZ_MEMb=1797, 
  XED_IFORM_SFENCE=1798, 
  XED_IFORM_SGDT_MEMs=1799, 
  XED_IFORM_SGDT_MEMs64=1800, 
  XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA=1801, 
  XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA=1802, 
  XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA=1803, 
  XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA=1804, 
  XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA=1805, 
  XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA=1806, 
  XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA=1807, 
  XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA=1808, 
  XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA=1809, 
  XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA=1810, 
  XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA=1811, 
  XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA=1812, 
  XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA=1813, 
  XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA=1814, 
  XED_IFORM_SHL_GPR8_CL_D2r4=1815, 
  XED_IFORM_SHL_GPR8_CL_D2r6=1816, 
  XED_IFORM_SHL_GPR8_IMMb_C0r4=1817, 
  XED_IFORM_SHL_GPR8_IMMb_C0r6=1818, 
  XED_IFORM_SHL_GPR8_ONE_D0r4=1819, 
  XED_IFORM_SHL_GPR8_ONE_D0r6=1820, 
  XED_IFORM_SHL_GPRv_CL_D3r4=1821, 
  XED_IFORM_SHL_GPRv_CL_D3r6=1822, 
  XED_IFORM_SHL_GPRv_IMMb_C1r4=1823, 
  XED_IFORM_SHL_GPRv_IMMb_C1r6=1824, 
  XED_IFORM_SHL_GPRv_ONE_D1r4=1825, 
  XED_IFORM_SHL_GPRv_ONE_D1r6=1826, 
  XED_IFORM_SHL_MEMb_CL_D2r4=1827, 
  XED_IFORM_SHL_MEMb_CL_D2r6=1828, 
  XED_IFORM_SHL_MEMb_IMMb_C0r4=1829, 
  XED_IFORM_SHL_MEMb_IMMb_C0r6=1830, 
  XED_IFORM_SHL_MEMb_ONE_D0r4=1831, 
  XED_IFORM_SHL_MEMb_ONE_D0r6=1832, 
  XED_IFORM_SHL_MEMv_CL_D3r4=1833, 
  XED_IFORM_SHL_MEMv_CL_D3r6=1834, 
  XED_IFORM_SHL_MEMv_IMMb_C1r4=1835, 
  XED_IFORM_SHL_MEMv_IMMb_C1r6=1836, 
  XED_IFORM_SHL_MEMv_ONE_D1r4=1837, 
  XED_IFORM_SHL_MEMv_ONE_D1r6=1838, 
  XED_IFORM_SHLD_GPRv_GPRv_CL=1839, 
  XED_IFORM_SHLD_GPRv_GPRv_IMMb=1840, 
  XED_IFORM_SHLD_MEMv_GPRv_CL=1841, 
  XED_IFORM_SHLD_MEMv_GPRv_IMMb=1842, 
  XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d=1843, 
  XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d=1844, 
  XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q=1845, 
  XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q=1846, 
  XED_IFORM_SHR_GPR8_CL=1847, 
  XED_IFORM_SHR_GPR8_IMMb=1848, 
  XED_IFORM_SHR_GPR8_ONE=1849, 
  XED_IFORM_SHR_GPRv_CL=1850, 
  XED_IFORM_SHR_GPRv_IMMb=1851, 
  XED_IFORM_SHR_GPRv_ONE=1852, 
  XED_IFORM_SHR_MEMb_CL=1853, 
  XED_IFORM_SHR_MEMb_IMMb=1854, 
  XED_IFORM_SHR_MEMb_ONE=1855, 
  XED_IFORM_SHR_MEMv_CL=1856, 
  XED_IFORM_SHR_MEMv_IMMb=1857, 
  XED_IFORM_SHR_MEMv_ONE=1858, 
  XED_IFORM_SHRD_GPRv_GPRv_CL=1859, 
  XED_IFORM_SHRD_GPRv_GPRv_IMMb=1860, 
  XED_IFORM_SHRD_MEMv_GPRv_CL=1861, 
  XED_IFORM_SHRD_MEMv_GPRv_IMMb=1862, 
  XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d=1863, 
  XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d=1864, 
  XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q=1865, 
  XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q=1866, 
  XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb=1867, 
  XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb=1868, 
  XED_IFORM_SHUFPS_XMMps_MEMps_IMMb=1869, 
  XED_IFORM_SHUFPS_XMMps_XMMps_IMMb=1870, 
  XED_IFORM_SIDT_MEMs=1871, 
  XED_IFORM_SIDT_MEMs64=1872, 
  XED_IFORM_SKINIT_EAX=1873, 
  XED_IFORM_SLDT_GPRv=1874, 
  XED_IFORM_SLDT_MEMw=1875, 
  XED_IFORM_SLWPCB_GPRyy=1876, 
  XED_IFORM_SMSW_GPRv=1877, 
  XED_IFORM_SMSW_MEMw=1878, 
  XED_IFORM_SQRTPD_XMMpd_MEMpd=1879, 
  XED_IFORM_SQRTPD_XMMpd_XMMpd=1880, 
  XED_IFORM_SQRTPS_XMMps_MEMps=1881, 
  XED_IFORM_SQRTPS_XMMps_XMMps=1882, 
  XED_IFORM_SQRTSD_XMMsd_MEMsd=1883, 
  XED_IFORM_SQRTSD_XMMsd_XMMsd=1884, 
  XED_IFORM_SQRTSS_XMMss_MEMss=1885, 
  XED_IFORM_SQRTSS_XMMss_XMMss=1886, 
  XED_IFORM_STAC=1887, 
  XED_IFORM_STC=1888, 
  XED_IFORM_STD=1889, 
  XED_IFORM_STGI=1890, 
  XED_IFORM_STI=1891, 
  XED_IFORM_STMXCSR_MEMd=1892, 
  XED_IFORM_STOSB=1893, 
  XED_IFORM_STOSD=1894, 
  XED_IFORM_STOSQ=1895, 
  XED_IFORM_STOSW=1896, 
  XED_IFORM_STR_GPRv=1897, 
  XED_IFORM_STR_MEMw=1898, 
  XED_IFORM_SUB_AL_IMMb=1899, 
  XED_IFORM_SUB_GPR8_GPR8_28=1900, 
  XED_IFORM_SUB_GPR8_GPR8_2A=1901, 
  XED_IFORM_SUB_GPR8_IMMb_80r5=1902, 
  XED_IFORM_SUB_GPR8_IMMb_82r5=1903, 
  XED_IFORM_SUB_GPR8_MEMb=1904, 
  XED_IFORM_SUB_GPRv_GPRv_29=1905, 
  XED_IFORM_SUB_GPRv_GPRv_2B=1906, 
  XED_IFORM_SUB_GPRv_IMMb=1907, 
  XED_IFORM_SUB_GPRv_IMMz=1908, 
  XED_IFORM_SUB_GPRv_MEMv=1909, 
  XED_IFORM_SUB_MEMb_GPR8=1910, 
  XED_IFORM_SUB_MEMb_IMMb_80r5=1911, 
  XED_IFORM_SUB_MEMb_IMMb_82r5=1912, 
  XED_IFORM_SUB_MEMv_GPRv=1913, 
  XED_IFORM_SUB_MEMv_IMMb=1914, 
  XED_IFORM_SUB_MEMv_IMMz=1915, 
  XED_IFORM_SUB_OrAX_IMMz=1916, 
  XED_IFORM_SUBPD_XMMpd_MEMpd=1917, 
  XED_IFORM_SUBPD_XMMpd_XMMpd=1918, 
  XED_IFORM_SUBPS_XMMps_MEMps=1919, 
  XED_IFORM_SUBPS_XMMps_XMMps=1920, 
  XED_IFORM_SUBSD_XMMsd_MEMsd=1921, 
  XED_IFORM_SUBSD_XMMsd_XMMsd=1922, 
  XED_IFORM_SUBSS_XMMss_MEMss=1923, 
  XED_IFORM_SUBSS_XMMss_XMMss=1924, 
  XED_IFORM_SUB_LOCK_MEMb_GPR8=1925, 
  XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5=1926, 
  XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5=1927, 
  XED_IFORM_SUB_LOCK_MEMv_GPRv=1928, 
  XED_IFORM_SUB_LOCK_MEMv_IMMb=1929, 
  XED_IFORM_SUB_LOCK_MEMv_IMMz=1930, 
  XED_IFORM_SWAPGS=1931, 
  XED_IFORM_SYSCALL=1932, 
  XED_IFORM_SYSCALL_AMD=1933, 
  XED_IFORM_SYSENTER=1934, 
  XED_IFORM_SYSEXIT=1935, 
  XED_IFORM_SYSRET=1936, 
  XED_IFORM_SYSRET64=1937, 
  XED_IFORM_SYSRET_AMD=1938, 
  XED_IFORM_T1MSKC_VGPR32d_GPR32d=1939, 
  XED_IFORM_T1MSKC_VGPR32d_MEMd=1940, 
  XED_IFORM_T1MSKC_VGPRyy_GPRyy=1941, 
  XED_IFORM_T1MSKC_VGPRyy_MEMy=1942, 
  XED_IFORM_TEST_AL_IMMb=1943, 
  XED_IFORM_TEST_GPR8_GPR8=1944, 
  XED_IFORM_TEST_GPR8_IMMb_F6r0=1945, 
  XED_IFORM_TEST_GPR8_IMMb_F6r1=1946, 
  XED_IFORM_TEST_GPRv_GPRv=1947, 
  XED_IFORM_TEST_GPRv_IMMz_F7r0=1948, 
  XED_IFORM_TEST_GPRv_IMMz_F7r1=1949, 
  XED_IFORM_TEST_MEMb_GPR8=1950, 
  XED_IFORM_TEST_MEMb_IMMb_F6r0=1951, 
  XED_IFORM_TEST_MEMb_IMMb_F6r1=1952, 
  XED_IFORM_TEST_MEMv_GPRv=1953, 
  XED_IFORM_TEST_MEMv_IMMz_F7r0=1954, 
  XED_IFORM_TEST_MEMv_IMMz_F7r1=1955, 
  XED_IFORM_TEST_OrAX_IMMz=1956, 
  XED_IFORM_TLBSYNC=1957, 
  XED_IFORM_TPAUSE_GPR32u32=1958, 
  XED_IFORM_TPAUSE_GPR64u64=1959, 
  XED_IFORM_TZCNT_GPRv_GPRv=1960, 
  XED_IFORM_TZCNT_GPRv_MEMv=1961, 
  XED_IFORM_TZMSK_VGPR32d_GPR32d=1962, 
  XED_IFORM_TZMSK_VGPR32d_MEMd=1963, 
  XED_IFORM_TZMSK_VGPRyy_GPRyy=1964, 
  XED_IFORM_TZMSK_VGPRyy_MEMy=1965, 
  XED_IFORM_UCOMISD_XMMsd_MEMsd=1966, 
  XED_IFORM_UCOMISD_XMMsd_XMMsd=1967, 
  XED_IFORM_UCOMISS_XMMss_MEMss=1968, 
  XED_IFORM_UCOMISS_XMMss_XMMss=1969, 
  XED_IFORM_UD0_GPR32_GPR32=1970, 
  XED_IFORM_UD0_GPR32_MEMd=1971, 
  XED_IFORM_UD1_GPR32_GPR32=1972, 
  XED_IFORM_UD1_GPR32_MEMd=1973, 
  XED_IFORM_UD2=1974, 
  XED_IFORM_UMONITOR_GPRa=1975, 
  XED_IFORM_UMWAIT_GPR32=1976, 
  XED_IFORM_UMWAIT_GPR64=1977, 
  XED_IFORM_UNPCKHPD_XMMpd_MEMdq=1978, 
  XED_IFORM_UNPCKHPD_XMMpd_XMMq=1979, 
  XED_IFORM_UNPCKHPS_XMMps_MEMdq=1980, 
  XED_IFORM_UNPCKHPS_XMMps_XMMdq=1981, 
  XED_IFORM_UNPCKLPD_XMMpd_MEMdq=1982, 
  XED_IFORM_UNPCKLPD_XMMpd_XMMq=1983, 
  XED_IFORM_UNPCKLPS_XMMps_MEMdq=1984, 
  XED_IFORM_UNPCKLPS_XMMps_XMMq=1985, 
  XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=1986, 
  XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=1987, 
  XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=1988, 
  XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=1989, 
  XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq=1990, 
  XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq=1991, 
  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=1992, 
  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=1993, 
  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=1994, 
  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=1995, 
  XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq=1996, 
  XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq=1997, 
  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=1998, 
  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=1999, 
  XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq=2000, 
  XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq=2001, 
  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2002, 
  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2003, 
  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2004, 
  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2005, 
  XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq=2006, 
  XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq=2007, 
  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2008, 
  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2009, 
  XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq=2010, 
  XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq=2011, 
  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2012, 
  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2013, 
  XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd=2014, 
  XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd=2015, 
  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2016, 
  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2017, 
  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq=2018, 
  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq=2019, 
  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq=2020, 
  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq=2021, 
  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq=2022, 
  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq=2023, 
  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq=2024, 
  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq=2025, 
  XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq=2026, 
  XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq=2027, 
  XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512=2028, 
  XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512=2029, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128=2030, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512=2031, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128=2032, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512=2033, 
  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512=2034, 
  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512=2035, 
  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq=2036, 
  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq=2037, 
  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512=2038, 
  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512=2039, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128=2040, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512=2041, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128=2042, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512=2043, 
  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2044, 
  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2045, 
  XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq=2046, 
  XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq=2047, 
  XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512=2048, 
  XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512=2049, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128=2050, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512=2051, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128=2052, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512=2053, 
  XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512=2054, 
  XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512=2055, 
  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq=2056, 
  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq=2057, 
  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512=2058, 
  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512=2059, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128=2060, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512=2061, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128=2062, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512=2063, 
  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2064, 
  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2065, 
  XED_IFORM_VAESIMC_XMMdq_MEMdq=2066, 
  XED_IFORM_VAESIMC_XMMdq_XMMdq=2067, 
  XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb=2068, 
  XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb=2069, 
  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=2070, 
  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=2071, 
  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=2072, 
  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=2073, 
  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=2074, 
  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=2075, 
  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=2076, 
  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=2077, 
  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=2078, 
  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=2079, 
  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=2080, 
  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=2081, 
  XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq=2082, 
  XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq=2083, 
  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2084, 
  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2085, 
  XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq=2086, 
  XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq=2087, 
  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2088, 
  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2089, 
  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2090, 
  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2091, 
  XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq=2092, 
  XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq=2093, 
  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2094, 
  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2095, 
  XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq=2096, 
  XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq=2097, 
  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2098, 
  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2099, 
  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2100, 
  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2101, 
  XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq=2102, 
  XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq=2103, 
  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2104, 
  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2105, 
  XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq=2106, 
  XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq=2107, 
  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2108, 
  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2109, 
  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2110, 
  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2111, 
  XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq=2112, 
  XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq=2113, 
  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2114, 
  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2115, 
  XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq=2116, 
  XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq=2117, 
  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2118, 
  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2119, 
  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2120, 
  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2121, 
  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2122, 
  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2123, 
  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2124, 
  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2125, 
  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2126, 
  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2127, 
  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2128, 
  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2129, 
  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2130, 
  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2131, 
  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2132, 
  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2133, 
  XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb=2134, 
  XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb=2135, 
  XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb=2136, 
  XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb=2137, 
  XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb=2138, 
  XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb=2139, 
  XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb=2140, 
  XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb=2141, 
  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq=2142, 
  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq=2143, 
  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq=2144, 
  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq=2145, 
  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq=2146, 
  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq=2147, 
  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq=2148, 
  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq=2149, 
  XED_IFORM_VBROADCASTF128_YMMqq_MEMdq=2150, 
  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512=2151, 
  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512=2152, 
  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512=2153, 
  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512=2154, 
  XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512=2155, 
  XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512=2156, 
  XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512=2157, 
  XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512=2158, 
  XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512=2159, 
  XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512=2160, 
  XED_IFORM_VBROADCASTI128_YMMqq_MEMdq=2161, 
  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512=2162, 
  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512=2163, 
  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512=2164, 
  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512=2165, 
  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512=2166, 
  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512=2167, 
  XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512=2168, 
  XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512=2169, 
  XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512=2170, 
  XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512=2171, 
  XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512=2172, 
  XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512=2173, 
  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512=2174, 
  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512=2175, 
  XED_IFORM_VBROADCASTSD_YMMqq_MEMq=2176, 
  XED_IFORM_VBROADCASTSD_YMMqq_XMMdq=2177, 
  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512=2178, 
  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512=2179, 
  XED_IFORM_VBROADCASTSS_XMMdq_MEMd=2180, 
  XED_IFORM_VBROADCASTSS_XMMdq_XMMdq=2181, 
  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512=2182, 
  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512=2183, 
  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512=2184, 
  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512=2185, 
  XED_IFORM_VBROADCASTSS_YMMqq_MEMd=2186, 
  XED_IFORM_VBROADCASTSS_YMMqq_XMMdq=2187, 
  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512=2188, 
  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512=2189, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2190, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2191, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2192, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2193, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2194, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2195, 
  XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb=2196, 
  XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb=2197, 
  XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb=2198, 
  XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb=2199, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2200, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2201, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2202, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2203, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2204, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2205, 
  XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb=2206, 
  XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb=2207, 
  XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb=2208, 
  XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb=2209, 
  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2210, 
  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2211, 
  XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb=2212, 
  XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb=2213, 
  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2214, 
  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2215, 
  XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb=2216, 
  XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb=2217, 
  XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512=2218, 
  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512=2219, 
  XED_IFORM_VCOMISD_XMMq_MEMq=2220, 
  XED_IFORM_VCOMISD_XMMq_XMMq=2221, 
  XED_IFORM_VCOMISS_XMMd_MEMd=2222, 
  XED_IFORM_VCOMISS_XMMd_XMMd=2223, 
  XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512=2224, 
  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512=2225, 
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512=2226, 
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512=2227, 
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512=2228, 
  XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512=2229, 
  XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512=2230, 
  XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2231, 
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512=2232, 
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512=2233, 
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512=2234, 
  XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512=2235, 
  XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512=2236, 
  XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2237, 
  XED_IFORM_VCVTDQ2PD_XMMdq_MEMq=2238, 
  XED_IFORM_VCVTDQ2PD_XMMdq_XMMq=2239, 
  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512=2240, 
  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512=2241, 
  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512=2242, 
  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512=2243, 
  XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq=2244, 
  XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq=2245, 
  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512=2246, 
  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512=2247, 
  XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq=2248, 
  XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq=2249, 
  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512=2250, 
  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512=2251, 
  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512=2252, 
  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512=2253, 
  XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq=2254, 
  XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq=2255, 
  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512=2256, 
  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512=2257, 
  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128=2258, 
  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512=2259, 
  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256=2260, 
  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512=2261, 
  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512=2262, 
  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512=2263, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128=2264, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256=2265, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512=2266, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512=2267, 
  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512=2268, 
  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512=2269, 
  XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq=2270, 
  XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq=2271, 
  XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq=2272, 
  XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq=2273, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2274, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2275, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2276, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2277, 
  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2278, 
  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2279, 
  XED_IFORM_VCVTPD2PS_XMMdq_MEMdq=2280, 
  XED_IFORM_VCVTPD2PS_XMMdq_MEMqq=2281, 
  XED_IFORM_VCVTPD2PS_XMMdq_XMMdq=2282, 
  XED_IFORM_VCVTPD2PS_XMMdq_YMMqq=2283, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128=2284, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256=2285, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128=2286, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256=2287, 
  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512=2288, 
  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512=2289, 
  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2290, 
  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2291, 
  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2292, 
  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2293, 
  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2294, 
  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2295, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2296, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2297, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2298, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2299, 
  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2300, 
  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2301, 
  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2302, 
  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2303, 
  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2304, 
  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2305, 
  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2306, 
  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2307, 
  XED_IFORM_VCVTPH2PS_XMMdq_MEMq=2308, 
  XED_IFORM_VCVTPH2PS_XMMdq_XMMq=2309, 
  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512=2310, 
  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512=2311, 
  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512=2312, 
  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512=2313, 
  XED_IFORM_VCVTPH2PS_YMMqq_MEMdq=2314, 
  XED_IFORM_VCVTPH2PS_YMMqq_XMMdq=2315, 
  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512=2316, 
  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512=2317, 
  XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq=2318, 
  XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq=2319, 
  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2320, 
  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2321, 
  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2322, 
  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2323, 
  XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq=2324, 
  XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq=2325, 
  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2326, 
  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2327, 
  XED_IFORM_VCVTPS2PD_XMMdq_MEMq=2328, 
  XED_IFORM_VCVTPS2PD_XMMdq_XMMq=2329, 
  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512=2330, 
  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512=2331, 
  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512=2332, 
  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512=2333, 
  XED_IFORM_VCVTPS2PD_YMMqq_MEMdq=2334, 
  XED_IFORM_VCVTPS2PD_YMMqq_XMMdq=2335, 
  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512=2336, 
  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512=2337, 
  XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb=2338, 
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512=2339, 
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512=2340, 
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512=2341, 
  XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb=2342, 
  XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb=2343, 
  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512=2344, 
  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512=2345, 
  XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb=2346, 
  XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512=2347, 
  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2348, 
  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2349, 
  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2350, 
  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2351, 
  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2352, 
  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2353, 
  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2354, 
  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2355, 
  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2356, 
  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2357, 
  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2358, 
  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2359, 
  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2360, 
  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2361, 
  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2362, 
  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2363, 
  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2364, 
  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2365, 
  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512=2366, 
  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512=2367, 
  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512=2368, 
  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512=2369, 
  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512=2370, 
  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512=2371, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2372, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2373, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2374, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2375, 
  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2376, 
  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2377, 
  XED_IFORM_VCVTSD2SI_GPR32d_MEMq=2378, 
  XED_IFORM_VCVTSD2SI_GPR32d_XMMq=2379, 
  XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512=2380, 
  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512=2381, 
  XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512=2382, 
  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512=2383, 
  XED_IFORM_VCVTSD2SI_GPR64q_MEMq=2384, 
  XED_IFORM_VCVTSD2SI_GPR64q_XMMq=2385, 
  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq=2386, 
  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq=2387, 
  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512=2388, 
  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512=2389, 
  XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512=2390, 
  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512=2391, 
  XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512=2392, 
  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512=2393, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d=2394, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q=2395, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd=2396, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq=2397, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512=2398, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512=2399, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512=2400, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512=2401, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d=2402, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q=2403, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd=2404, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq=2405, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512=2406, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512=2407, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512=2408, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512=2409, 
  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd=2410, 
  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd=2411, 
  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512=2412, 
  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512=2413, 
  XED_IFORM_VCVTSS2SI_GPR32d_MEMd=2414, 
  XED_IFORM_VCVTSS2SI_GPR32d_XMMd=2415, 
  XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512=2416, 
  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512=2417, 
  XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512=2418, 
  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512=2419, 
  XED_IFORM_VCVTSS2SI_GPR64q_MEMd=2420, 
  XED_IFORM_VCVTSS2SI_GPR64q_XMMd=2421, 
  XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512=2422, 
  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512=2423, 
  XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512=2424, 
  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512=2425, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq=2426, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq=2427, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq=2428, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq=2429, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2430, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2431, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2432, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2433, 
  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2434, 
  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2435, 
  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2436, 
  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2437, 
  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2438, 
  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2439, 
  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2440, 
  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2441, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2442, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2443, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2444, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2445, 
  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2446, 
  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2447, 
  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2448, 
  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2449, 
  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2450, 
  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2451, 
  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2452, 
  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2453, 
  XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq=2454, 
  XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq=2455, 
  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2456, 
  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2457, 
  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2458, 
  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2459, 
  XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq=2460, 
  XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq=2461, 
  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2462, 
  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2463, 
  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2464, 
  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2465, 
  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2466, 
  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2467, 
  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2468, 
  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2469, 
  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2470, 
  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2471, 
  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2472, 
  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2473, 
  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2474, 
  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2475, 
  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2476, 
  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2477, 
  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2478, 
  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2479, 
  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2480, 
  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2481, 
  XED_IFORM_VCVTTSD2SI_GPR32d_MEMq=2482, 
  XED_IFORM_VCVTTSD2SI_GPR32d_XMMq=2483, 
  XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512=2484, 
  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512=2485, 
  XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512=2486, 
  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512=2487, 
  XED_IFORM_VCVTTSD2SI_GPR64q_MEMq=2488, 
  XED_IFORM_VCVTTSD2SI_GPR64q_XMMq=2489, 
  XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512=2490, 
  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512=2491, 
  XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512=2492, 
  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512=2493, 
  XED_IFORM_VCVTTSS2SI_GPR32d_MEMd=2494, 
  XED_IFORM_VCVTTSS2SI_GPR32d_XMMd=2495, 
  XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512=2496, 
  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512=2497, 
  XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512=2498, 
  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512=2499, 
  XED_IFORM_VCVTTSS2SI_GPR64q_MEMd=2500, 
  XED_IFORM_VCVTTSS2SI_GPR64q_XMMd=2501, 
  XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512=2502, 
  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512=2503, 
  XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512=2504, 
  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512=2505, 
  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512=2506, 
  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512=2507, 
  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512=2508, 
  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512=2509, 
  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512=2510, 
  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512=2511, 
  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512=2512, 
  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512=2513, 
  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512=2514, 
  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512=2515, 
  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512=2516, 
  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512=2517, 
  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512=2518, 
  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512=2519, 
  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512=2520, 
  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512=2521, 
  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512=2522, 
  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512=2523, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2524, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2525, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2526, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2527, 
  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2528, 
  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2529, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512=2530, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512=2531, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512=2532, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512=2533, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512=2534, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512=2535, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512=2536, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512=2537, 
  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=2538, 
  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=2539, 
  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=2540, 
  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=2541, 
  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=2542, 
  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=2543, 
  XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq=2544, 
  XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq=2545, 
  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2546, 
  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2547, 
  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2548, 
  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2549, 
  XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq=2550, 
  XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq=2551, 
  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2552, 
  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2553, 
  XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq=2554, 
  XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq=2555, 
  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2556, 
  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2557, 
  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2558, 
  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2559, 
  XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq=2560, 
  XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq=2561, 
  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2562, 
  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2563, 
  XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq=2564, 
  XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq=2565, 
  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2566, 
  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2567, 
  XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd=2568, 
  XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd=2569, 
  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2570, 
  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2571, 
  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512=2572, 
  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512=2573, 
  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512=2574, 
  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512=2575, 
  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512=2576, 
  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512=2577, 
  XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb=2578, 
  XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb=2579, 
  XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb=2580, 
  XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb=2581, 
  XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb=2582, 
  XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb=2583, 
  XED_IFORM_VERR_GPR16=2584, 
  XED_IFORM_VERR_MEMw=2585, 
  XED_IFORM_VERW_GPR16=2586, 
  XED_IFORM_VERW_MEMw=2587, 
  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=2588, 
  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=2589, 
  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=2590, 
  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=2591, 
  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512=2592, 
  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512=2593, 
  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512=2594, 
  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512=2595, 
  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512=2596, 
  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2597, 
  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512=2598, 
  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512=2599, 
  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512=2600, 
  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512=2601, 
  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512=2602, 
  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2603, 
  XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb=2604, 
  XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb=2605, 
  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512=2606, 
  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2607, 
  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512=2608, 
  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2609, 
  XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2610, 
  XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2611, 
  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512=2612, 
  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2613, 
  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512=2614, 
  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2615, 
  XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2616, 
  XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2617, 
  XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb=2618, 
  XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb=2619, 
  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512=2620, 
  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2621, 
  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512=2622, 
  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2623, 
  XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2624, 
  XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2625, 
  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512=2626, 
  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2627, 
  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512=2628, 
  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2629, 
  XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2630, 
  XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2631, 
  XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb=2632, 
  XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512=2633, 
  XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb=2634, 
  XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512=2635, 
  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2636, 
  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2637, 
  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2638, 
  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2639, 
  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2640, 
  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2641, 
  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2642, 
  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2643, 
  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2644, 
  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2645, 
  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2646, 
  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2647, 
  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2648, 
  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2649, 
  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2650, 
  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2651, 
  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq=2652, 
  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq=2653, 
  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2654, 
  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2655, 
  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2656, 
  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2657, 
  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq=2658, 
  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq=2659, 
  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2660, 
  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2661, 
  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq=2662, 
  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq=2663, 
  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2664, 
  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2665, 
  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2666, 
  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2667, 
  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq=2668, 
  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq=2669, 
  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2670, 
  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2671, 
  XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq=2672, 
  XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq=2673, 
  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2674, 
  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2675, 
  XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd=2676, 
  XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd=2677, 
  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2678, 
  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2679, 
  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq=2680, 
  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq=2681, 
  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2682, 
  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2683, 
  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2684, 
  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2685, 
  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq=2686, 
  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq=2687, 
  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2688, 
  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2689, 
  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq=2690, 
  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq=2691, 
  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2692, 
  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2693, 
  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2694, 
  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2695, 
  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq=2696, 
  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq=2697, 
  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2698, 
  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2699, 
  XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq=2700, 
  XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq=2701, 
  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2702, 
  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2703, 
  XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd=2704, 
  XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd=2705, 
  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2706, 
  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2707, 
  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq=2708, 
  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq=2709, 
  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2710, 
  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2711, 
  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2712, 
  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2713, 
  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq=2714, 
  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq=2715, 
  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2716, 
  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2717, 
  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq=2718, 
  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq=2719, 
  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2720, 
  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2721, 
  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2722, 
  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2723, 
  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq=2724, 
  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq=2725, 
  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2726, 
  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2727, 
  XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq=2728, 
  XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq=2729, 
  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2730, 
  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2731, 
  XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd=2732, 
  XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd=2733, 
  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2734, 
  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2735, 
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=2736, 
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=2737, 
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=2738, 
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=2739, 
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=2740, 
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=2741, 
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=2742, 
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=2743, 
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=2744, 
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=2745, 
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=2746, 
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=2747, 
  XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq=2748, 
  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq=2749, 
  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq=2750, 
  XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd=2751, 
  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd=2752, 
  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd=2753, 
  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq=2754, 
  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq=2755, 
  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2756, 
  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2757, 
  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2758, 
  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2759, 
  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq=2760, 
  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq=2761, 
  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2762, 
  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2763, 
  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq=2764, 
  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq=2765, 
  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2766, 
  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2767, 
  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2768, 
  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2769, 
  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq=2770, 
  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq=2771, 
  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2772, 
  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2773, 
  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq=2774, 
  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq=2775, 
  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2776, 
  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2777, 
  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2778, 
  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2779, 
  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq=2780, 
  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq=2781, 
  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2782, 
  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2783, 
  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq=2784, 
  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq=2785, 
  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2786, 
  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2787, 
  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2788, 
  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2789, 
  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq=2790, 
  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq=2791, 
  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2792, 
  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2793, 
  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq=2794, 
  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq=2795, 
  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2796, 
  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2797, 
  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2798, 
  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2799, 
  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq=2800, 
  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq=2801, 
  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2802, 
  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2803, 
  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq=2804, 
  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq=2805, 
  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2806, 
  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2807, 
  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2808, 
  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2809, 
  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq=2810, 
  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq=2811, 
  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2812, 
  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2813, 
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=2814, 
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=2815, 
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=2816, 
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=2817, 
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=2818, 
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=2819, 
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=2820, 
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=2821, 
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=2822, 
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=2823, 
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=2824, 
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=2825, 
  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq=2826, 
  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq=2827, 
  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2828, 
  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2829, 
  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2830, 
  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2831, 
  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq=2832, 
  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq=2833, 
  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2834, 
  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2835, 
  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq=2836, 
  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq=2837, 
  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2838, 
  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2839, 
  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2840, 
  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2841, 
  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq=2842, 
  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq=2843, 
  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2844, 
  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2845, 
  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq=2846, 
  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq=2847, 
  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2848, 
  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2849, 
  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd=2850, 
  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd=2851, 
  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2852, 
  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2853, 
  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq=2854, 
  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq=2855, 
  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2856, 
  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2857, 
  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2858, 
  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2859, 
  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq=2860, 
  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq=2861, 
  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2862, 
  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2863, 
  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq=2864, 
  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq=2865, 
  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2866, 
  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2867, 
  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2868, 
  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2869, 
  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq=2870, 
  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq=2871, 
  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2872, 
  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2873, 
  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq=2874, 
  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq=2875, 
  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2876, 
  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2877, 
  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd=2878, 
  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd=2879, 
  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2880, 
  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2881, 
  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq=2882, 
  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq=2883, 
  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2884, 
  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2885, 
  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2886, 
  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2887, 
  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq=2888, 
  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq=2889, 
  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2890, 
  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2891, 
  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq=2892, 
  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq=2893, 
  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2894, 
  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2895, 
  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2896, 
  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2897, 
  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq=2898, 
  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq=2899, 
  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2900, 
  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2901, 
  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq=2902, 
  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq=2903, 
  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2904, 
  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2905, 
  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd=2906, 
  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd=2907, 
  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2908, 
  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2909, 
  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq=2910, 
  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq=2911, 
  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2912, 
  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2913, 
  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2914, 
  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2915, 
  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq=2916, 
  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq=2917, 
  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2918, 
  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2919, 
  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq=2920, 
  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq=2921, 
  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2922, 
  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2923, 
  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2924, 
  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2925, 
  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq=2926, 
  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq=2927, 
  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2928, 
  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2929, 
  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq=2930, 
  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq=2931, 
  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2932, 
  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2933, 
  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2934, 
  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2935, 
  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq=2936, 
  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq=2937, 
  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2938, 
  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2939, 
  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq=2940, 
  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq=2941, 
  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2942, 
  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2943, 
  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2944, 
  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2945, 
  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq=2946, 
  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq=2947, 
  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2948, 
  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2949, 
  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq=2950, 
  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq=2951, 
  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2952, 
  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2953, 
  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2954, 
  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2955, 
  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq=2956, 
  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq=2957, 
  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2958, 
  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2959, 
  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq=2960, 
  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq=2961, 
  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2962, 
  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2963, 
  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2964, 
  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2965, 
  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq=2966, 
  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq=2967, 
  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2968, 
  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2969, 
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq=2970, 
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq=2971, 
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq=2972, 
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq=2973, 
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq=2974, 
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq=2975, 
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq=2976, 
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq=2977, 
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq=2978, 
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq=2979, 
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq=2980, 
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq=2981, 
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=2982, 
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=2983, 
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=2984, 
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=2985, 
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=2986, 
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=2987, 
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=2988, 
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=2989, 
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=2990, 
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=2991, 
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=2992, 
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=2993, 
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq=2994, 
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq=2995, 
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq=2996, 
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd=2997, 
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd=2998, 
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd=2999, 
  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq=3000, 
  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq=3001, 
  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3002, 
  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3003, 
  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3004, 
  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3005, 
  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq=3006, 
  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq=3007, 
  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3008, 
  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3009, 
  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq=3010, 
  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq=3011, 
  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3012, 
  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3013, 
  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3014, 
  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3015, 
  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq=3016, 
  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq=3017, 
  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3018, 
  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3019, 
  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq=3020, 
  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq=3021, 
  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3022, 
  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3023, 
  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd=3024, 
  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd=3025, 
  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3026, 
  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3027, 
  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq=3028, 
  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq=3029, 
  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3030, 
  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3031, 
  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3032, 
  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3033, 
  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq=3034, 
  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq=3035, 
  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3036, 
  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3037, 
  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq=3038, 
  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq=3039, 
  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3040, 
  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3041, 
  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3042, 
  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3043, 
  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq=3044, 
  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq=3045, 
  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3046, 
  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3047, 
  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq=3048, 
  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq=3049, 
  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3050, 
  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3051, 
  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd=3052, 
  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd=3053, 
  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3054, 
  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3055, 
  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq=3056, 
  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq=3057, 
  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3058, 
  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3059, 
  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3060, 
  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3061, 
  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq=3062, 
  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq=3063, 
  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3064, 
  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3065, 
  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq=3066, 
  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq=3067, 
  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3068, 
  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3069, 
  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3070, 
  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3071, 
  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq=3072, 
  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq=3073, 
  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3074, 
  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3075, 
  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq=3076, 
  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq=3077, 
  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3078, 
  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3079, 
  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd=3080, 
  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd=3081, 
  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3082, 
  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3083, 
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3084, 
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3085, 
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3086, 
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3087, 
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3088, 
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3089, 
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3090, 
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3091, 
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3092, 
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3093, 
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3094, 
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3095, 
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq=3096, 
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq=3097, 
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq=3098, 
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd=3099, 
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd=3100, 
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd=3101, 
  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq=3102, 
  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq=3103, 
  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3104, 
  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3105, 
  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3106, 
  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3107, 
  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq=3108, 
  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq=3109, 
  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3110, 
  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3111, 
  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq=3112, 
  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq=3113, 
  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3114, 
  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3115, 
  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3116, 
  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3117, 
  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq=3118, 
  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq=3119, 
  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3120, 
  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3121, 
  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq=3122, 
  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq=3123, 
  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3124, 
  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3125, 
  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd=3126, 
  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd=3127, 
  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3128, 
  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3129, 
  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq=3130, 
  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq=3131, 
  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3132, 
  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3133, 
  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3134, 
  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3135, 
  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq=3136, 
  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq=3137, 
  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3138, 
  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3139, 
  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq=3140, 
  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq=3141, 
  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3142, 
  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3143, 
  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3144, 
  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3145, 
  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq=3146, 
  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq=3147, 
  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3148, 
  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3149, 
  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq=3150, 
  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq=3151, 
  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3152, 
  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3153, 
  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd=3154, 
  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd=3155, 
  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3156, 
  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3157, 
  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq=3158, 
  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq=3159, 
  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3160, 
  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3161, 
  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3162, 
  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3163, 
  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq=3164, 
  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq=3165, 
  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3166, 
  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3167, 
  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq=3168, 
  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq=3169, 
  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3170, 
  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3171, 
  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3172, 
  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3173, 
  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq=3174, 
  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq=3175, 
  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3176, 
  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3177, 
  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq=3178, 
  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq=3179, 
  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3180, 
  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3181, 
  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd=3182, 
  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd=3183, 
  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3184, 
  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3185, 
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3186, 
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3187, 
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3188, 
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3189, 
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3190, 
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3191, 
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3192, 
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3193, 
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3194, 
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3195, 
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3196, 
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3197, 
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq=3198, 
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq=3199, 
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq=3200, 
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd=3201, 
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd=3202, 
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd=3203, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128=3204, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256=3205, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512=3206, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3207, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512=3208, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512=3209, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128=3210, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256=3211, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512=3212, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3213, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512=3214, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512=3215, 
  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512=3216, 
  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3217, 
  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512=3218, 
  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3219, 
  XED_IFORM_VFRCZPD_XMMdq_MEMdq=3220, 
  XED_IFORM_VFRCZPD_XMMdq_XMMdq=3221, 
  XED_IFORM_VFRCZPD_YMMqq_MEMqq=3222, 
  XED_IFORM_VFRCZPD_YMMqq_YMMqq=3223, 
  XED_IFORM_VFRCZPS_XMMdq_MEMdq=3224, 
  XED_IFORM_VFRCZPS_XMMdq_XMMdq=3225, 
  XED_IFORM_VFRCZPS_YMMqq_MEMqq=3226, 
  XED_IFORM_VFRCZPS_YMMqq_YMMqq=3227, 
  XED_IFORM_VFRCZSD_XMMdq_MEMq=3228, 
  XED_IFORM_VFRCZSD_XMMdq_XMMq=3229, 
  XED_IFORM_VFRCZSS_XMMdq_MEMd=3230, 
  XED_IFORM_VFRCZSS_XMMdq_XMMd=3231, 
  XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3232, 
  XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128=3233, 
  XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3234, 
  XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256=3235, 
  XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3236, 
  XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3237, 
  XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128=3238, 
  XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256=3239, 
  XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256=3240, 
  XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512=3241, 
  XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=3242, 
  XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=3243, 
  XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=3244, 
  XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=3245, 
  XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=3246, 
  XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=3247, 
  XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=3248, 
  XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=3249, 
  XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3250, 
  XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128=3251, 
  XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3252, 
  XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256=3253, 
  XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3254, 
  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3255, 
  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256=3256, 
  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128=3257, 
  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256=3258, 
  XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512=3259, 
  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512=3260, 
  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512=3261, 
  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512=3262, 
  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512=3263, 
  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512=3264, 
  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3265, 
  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512=3266, 
  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512=3267, 
  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512=3268, 
  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512=3269, 
  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512=3270, 
  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3271, 
  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3272, 
  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3273, 
  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3274, 
  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3275, 
  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=3276, 
  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=3277, 
  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=3278, 
  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=3279, 
  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=3280, 
  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=3281, 
  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=3282, 
  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=3283, 
  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=3284, 
  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=3285, 
  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=3286, 
  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=3287, 
  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=3288, 
  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=3289, 
  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=3290, 
  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=3291, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3292, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3293, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8=3294, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8=3295, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3296, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3297, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8=3298, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8=3299, 
  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3300, 
  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3301, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3302, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3303, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8=3304, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8=3305, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3306, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3307, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8=3308, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8=3309, 
  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3310, 
  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3311, 
  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3312, 
  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3313, 
  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8=3314, 
  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8=3315, 
  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3316, 
  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3317, 
  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8=3318, 
  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8=3319, 
  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3320, 
  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3321, 
  XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq=3322, 
  XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq=3323, 
  XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq=3324, 
  XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq=3325, 
  XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq=3326, 
  XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq=3327, 
  XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq=3328, 
  XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq=3329, 
  XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq=3330, 
  XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq=3331, 
  XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq=3332, 
  XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq=3333, 
  XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq=3334, 
  XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq=3335, 
  XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq=3336, 
  XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq=3337, 
  XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb=3338, 
  XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb=3339, 
  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=3340, 
  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512=3341, 
  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3342, 
  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512=3343, 
  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3344, 
  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512=3345, 
  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=3346, 
  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512=3347, 
  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3348, 
  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512=3349, 
  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3350, 
  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512=3351, 
  XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb=3352, 
  XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb=3353, 
  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=3354, 
  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512=3355, 
  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3356, 
  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512=3357, 
  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3358, 
  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512=3359, 
  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=3360, 
  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512=3361, 
  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3362, 
  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512=3363, 
  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3364, 
  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512=3365, 
  XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb=3366, 
  XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb=3367, 
  XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512=3368, 
  XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512=3369, 
  XED_IFORM_VLDDQU_XMMdq_MEMdq=3370, 
  XED_IFORM_VLDDQU_YMMqq_MEMqq=3371, 
  XED_IFORM_VLDMXCSR_MEMd=3372, 
  XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq=3373, 
  XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq=3374, 
  XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq=3375, 
  XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq=3376, 
  XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq=3377, 
  XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq=3378, 
  XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq=3379, 
  XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq=3380, 
  XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq=3381, 
  XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq=3382, 
  XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq=3383, 
  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3384, 
  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3385, 
  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3386, 
  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3387, 
  XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq=3388, 
  XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq=3389, 
  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3390, 
  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3391, 
  XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq=3392, 
  XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq=3393, 
  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3394, 
  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3395, 
  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3396, 
  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3397, 
  XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq=3398, 
  XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq=3399, 
  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3400, 
  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3401, 
  XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq=3402, 
  XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq=3403, 
  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3404, 
  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3405, 
  XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd=3406, 
  XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd=3407, 
  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3408, 
  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3409, 
  XED_IFORM_VMCALL=3410, 
  XED_IFORM_VMCLEAR_MEMq=3411, 
  XED_IFORM_VMFUNC=3412, 
  XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq=3413, 
  XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq=3414, 
  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3415, 
  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3416, 
  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3417, 
  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3418, 
  XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq=3419, 
  XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq=3420, 
  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3421, 
  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3422, 
  XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq=3423, 
  XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq=3424, 
  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3425, 
  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3426, 
  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3427, 
  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3428, 
  XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq=3429, 
  XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq=3430, 
  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3431, 
  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3432, 
  XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq=3433, 
  XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq=3434, 
  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3435, 
  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3436, 
  XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd=3437, 
  XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd=3438, 
  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3439, 
  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3440, 
  XED_IFORM_VMLAUNCH=3441, 
  XED_IFORM_VMLOAD_ArAX=3442, 
  XED_IFORM_VMMCALL=3443, 
  XED_IFORM_VMOVAPD_MEMdq_XMMdq=3444, 
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512=3445, 
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512=3446, 
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512=3447, 
  XED_IFORM_VMOVAPD_MEMqq_YMMqq=3448, 
  XED_IFORM_VMOVAPD_XMMdq_MEMdq=3449, 
  XED_IFORM_VMOVAPD_XMMdq_XMMdq_28=3450, 
  XED_IFORM_VMOVAPD_XMMdq_XMMdq_29=3451, 
  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512=3452, 
  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512=3453, 
  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512=3454, 
  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512=3455, 
  XED_IFORM_VMOVAPD_YMMqq_MEMqq=3456, 
  XED_IFORM_VMOVAPD_YMMqq_YMMqq_28=3457, 
  XED_IFORM_VMOVAPD_YMMqq_YMMqq_29=3458, 
  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512=3459, 
  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3460, 
  XED_IFORM_VMOVAPS_MEMdq_XMMdq=3461, 
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512=3462, 
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512=3463, 
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512=3464, 
  XED_IFORM_VMOVAPS_MEMqq_YMMqq=3465, 
  XED_IFORM_VMOVAPS_XMMdq_MEMdq=3466, 
  XED_IFORM_VMOVAPS_XMMdq_XMMdq_28=3467, 
  XED_IFORM_VMOVAPS_XMMdq_XMMdq_29=3468, 
  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512=3469, 
  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512=3470, 
  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512=3471, 
  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512=3472, 
  XED_IFORM_VMOVAPS_YMMqq_MEMqq=3473, 
  XED_IFORM_VMOVAPS_YMMqq_YMMqq_28=3474, 
  XED_IFORM_VMOVAPS_YMMqq_YMMqq_29=3475, 
  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512=3476, 
  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3477, 
  XED_IFORM_VMOVD_GPR32d_XMMd=3478, 
  XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512=3479, 
  XED_IFORM_VMOVD_MEMd_XMMd=3480, 
  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512=3481, 
  XED_IFORM_VMOVD_XMMdq_GPR32d=3482, 
  XED_IFORM_VMOVD_XMMdq_MEMd=3483, 
  XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512=3484, 
  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512=3485, 
  XED_IFORM_VMOVDDUP_XMMdq_MEMq=3486, 
  XED_IFORM_VMOVDDUP_XMMdq_XMMdq=3487, 
  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512=3488, 
  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512=3489, 
  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512=3490, 
  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512=3491, 
  XED_IFORM_VMOVDDUP_YMMqq_MEMqq=3492, 
  XED_IFORM_VMOVDDUP_YMMqq_YMMqq=3493, 
  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512=3494, 
  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512=3495, 
  XED_IFORM_VMOVDQA_MEMdq_XMMdq=3496, 
  XED_IFORM_VMOVDQA_MEMqq_YMMqq=3497, 
  XED_IFORM_VMOVDQA_XMMdq_MEMdq=3498, 
  XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F=3499, 
  XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F=3500, 
  XED_IFORM_VMOVDQA_YMMqq_MEMqq=3501, 
  XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F=3502, 
  XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F=3503, 
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512=3504, 
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512=3505, 
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512=3506, 
  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512=3507, 
  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512=3508, 
  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512=3509, 
  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512=3510, 
  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512=3511, 
  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512=3512, 
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512=3513, 
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512=3514, 
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512=3515, 
  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512=3516, 
  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512=3517, 
  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512=3518, 
  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512=3519, 
  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512=3520, 
  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512=3521, 
  XED_IFORM_VMOVDQU_MEMdq_XMMdq=3522, 
  XED_IFORM_VMOVDQU_MEMqq_YMMqq=3523, 
  XED_IFORM_VMOVDQU_XMMdq_MEMdq=3524, 
  XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F=3525, 
  XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F=3526, 
  XED_IFORM_VMOVDQU_YMMqq_MEMqq=3527, 
  XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F=3528, 
  XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F=3529, 
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512=3530, 
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512=3531, 
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512=3532, 
  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512=3533, 
  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512=3534, 
  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512=3535, 
  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512=3536, 
  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512=3537, 
  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512=3538, 
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512=3539, 
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512=3540, 
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512=3541, 
  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512=3542, 
  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512=3543, 
  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512=3544, 
  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512=3545, 
  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512=3546, 
  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512=3547, 
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512=3548, 
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512=3549, 
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512=3550, 
  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512=3551, 
  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512=3552, 
  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512=3553, 
  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512=3554, 
  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512=3555, 
  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512=3556, 
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512=3557, 
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512=3558, 
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512=3559, 
  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512=3560, 
  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512=3561, 
  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512=3562, 
  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512=3563, 
  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512=3564, 
  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512=3565, 
  XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq=3566, 
  XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512=3567, 
  XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512=3568, 
  XED_IFORM_VMOVHPD_MEMq_XMMdq=3569, 
  XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq=3570, 
  XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512=3571, 
  XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512=3572, 
  XED_IFORM_VMOVHPS_MEMq_XMMdq=3573, 
  XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq=3574, 
  XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512=3575, 
  XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq=3576, 
  XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512=3577, 
  XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512=3578, 
  XED_IFORM_VMOVLPD_MEMq_XMMq=3579, 
  XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq=3580, 
  XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512=3581, 
  XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512=3582, 
  XED_IFORM_VMOVLPS_MEMq_XMMq=3583, 
  XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq=3584, 
  XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512=3585, 
  XED_IFORM_VMOVMSKPD_GPR32d_XMMdq=3586, 
  XED_IFORM_VMOVMSKPD_GPR32d_YMMqq=3587, 
  XED_IFORM_VMOVMSKPS_GPR32d_XMMdq=3588, 
  XED_IFORM_VMOVMSKPS_GPR32d_YMMqq=3589, 
  XED_IFORM_VMOVNTDQ_MEMdq_XMMdq=3590, 
  XED_IFORM_VMOVNTDQ_MEMqq_YMMqq=3591, 
  XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512=3592, 
  XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512=3593, 
  XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512=3594, 
  XED_IFORM_VMOVNTDQA_XMMdq_MEMdq=3595, 
  XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512=3596, 
  XED_IFORM_VMOVNTDQA_YMMqq_MEMqq=3597, 
  XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512=3598, 
  XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512=3599, 
  XED_IFORM_VMOVNTPD_MEMdq_XMMdq=3600, 
  XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512=3601, 
  XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512=3602, 
  XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512=3603, 
  XED_IFORM_VMOVNTPD_MEMqq_YMMqq=3604, 
  XED_IFORM_VMOVNTPS_MEMdq_XMMdq=3605, 
  XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512=3606, 
  XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512=3607, 
  XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512=3608, 
  XED_IFORM_VMOVNTPS_MEMqq_YMMqq=3609, 
  XED_IFORM_VMOVQ_GPR64q_XMMq=3610, 
  XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512=3611, 
  XED_IFORM_VMOVQ_MEMq_XMMq_7E=3612, 
  XED_IFORM_VMOVQ_MEMq_XMMq_D6=3613, 
  XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512=3614, 
  XED_IFORM_VMOVQ_XMMdq_GPR64q=3615, 
  XED_IFORM_VMOVQ_XMMdq_MEMq_6E=3616, 
  XED_IFORM_VMOVQ_XMMdq_MEMq_7E=3617, 
  XED_IFORM_VMOVQ_XMMdq_XMMq_7E=3618, 
  XED_IFORM_VMOVQ_XMMdq_XMMq_D6=3619, 
  XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512=3620, 
  XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512=3621, 
  XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512=3622, 
  XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512=3623, 
  XED_IFORM_VMOVSD_MEMq_XMMq=3624, 
  XED_IFORM_VMOVSD_XMMdq_MEMq=3625, 
  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10=3626, 
  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11=3627, 
  XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512=3628, 
  XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3629, 
  XED_IFORM_VMOVSHDUP_XMMdq_MEMdq=3630, 
  XED_IFORM_VMOVSHDUP_XMMdq_XMMdq=3631, 
  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512=3632, 
  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512=3633, 
  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512=3634, 
  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512=3635, 
  XED_IFORM_VMOVSHDUP_YMMqq_MEMqq=3636, 
  XED_IFORM_VMOVSHDUP_YMMqq_YMMqq=3637, 
  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512=3638, 
  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=3639, 
  XED_IFORM_VMOVSLDUP_XMMdq_MEMdq=3640, 
  XED_IFORM_VMOVSLDUP_XMMdq_XMMdq=3641, 
  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512=3642, 
  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512=3643, 
  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512=3644, 
  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512=3645, 
  XED_IFORM_VMOVSLDUP_YMMqq_MEMqq=3646, 
  XED_IFORM_VMOVSLDUP_YMMqq_YMMqq=3647, 
  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512=3648, 
  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=3649, 
  XED_IFORM_VMOVSS_MEMd_XMMd=3650, 
  XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512=3651, 
  XED_IFORM_VMOVSS_XMMdq_MEMd=3652, 
  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10=3653, 
  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11=3654, 
  XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512=3655, 
  XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3656, 
  XED_IFORM_VMOVUPD_MEMdq_XMMdq=3657, 
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512=3658, 
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512=3659, 
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512=3660, 
  XED_IFORM_VMOVUPD_MEMqq_YMMqq=3661, 
  XED_IFORM_VMOVUPD_XMMdq_MEMdq=3662, 
  XED_IFORM_VMOVUPD_XMMdq_XMMdq_10=3663, 
  XED_IFORM_VMOVUPD_XMMdq_XMMdq_11=3664, 
  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512=3665, 
  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512=3666, 
  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512=3667, 
  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512=3668, 
  XED_IFORM_VMOVUPD_YMMqq_MEMqq=3669, 
  XED_IFORM_VMOVUPD_YMMqq_YMMqq_10=3670, 
  XED_IFORM_VMOVUPD_YMMqq_YMMqq_11=3671, 
  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512=3672, 
  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3673, 
  XED_IFORM_VMOVUPS_MEMdq_XMMdq=3674, 
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512=3675, 
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512=3676, 
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512=3677, 
  XED_IFORM_VMOVUPS_MEMqq_YMMqq=3678, 
  XED_IFORM_VMOVUPS_XMMdq_MEMdq=3679, 
  XED_IFORM_VMOVUPS_XMMdq_XMMdq_10=3680, 
  XED_IFORM_VMOVUPS_XMMdq_XMMdq_11=3681, 
  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512=3682, 
  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512=3683, 
  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512=3684, 
  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512=3685, 
  XED_IFORM_VMOVUPS_YMMqq_MEMqq=3686, 
  XED_IFORM_VMOVUPS_YMMqq_YMMqq_10=3687, 
  XED_IFORM_VMOVUPS_YMMqq_YMMqq_11=3688, 
  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512=3689, 
  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3690, 
  XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb=3691, 
  XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb=3692, 
  XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb=3693, 
  XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb=3694, 
  XED_IFORM_VMPTRLD_MEMq=3695, 
  XED_IFORM_VMPTRST_MEMq=3696, 
  XED_IFORM_VMREAD_GPR32_GPR32=3697, 
  XED_IFORM_VMREAD_GPR64_GPR64=3698, 
  XED_IFORM_VMREAD_MEMd_GPR32=3699, 
  XED_IFORM_VMREAD_MEMq_GPR64=3700, 
  XED_IFORM_VMRESUME=3701, 
  XED_IFORM_VMRUN_ArAX=3702, 
  XED_IFORM_VMSAVE=3703, 
  XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq=3704, 
  XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq=3705, 
  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3706, 
  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3707, 
  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3708, 
  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3709, 
  XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq=3710, 
  XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq=3711, 
  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3712, 
  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3713, 
  XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq=3714, 
  XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq=3715, 
  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3716, 
  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3717, 
  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3718, 
  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3719, 
  XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq=3720, 
  XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq=3721, 
  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3722, 
  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3723, 
  XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq=3724, 
  XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq=3725, 
  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3726, 
  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3727, 
  XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd=3728, 
  XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd=3729, 
  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3730, 
  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3731, 
  XED_IFORM_VMWRITE_GPR32_GPR32=3732, 
  XED_IFORM_VMWRITE_GPR32_MEMd=3733, 
  XED_IFORM_VMWRITE_GPR64_GPR64=3734, 
  XED_IFORM_VMWRITE_GPR64_MEMq=3735, 
  XED_IFORM_VMXOFF=3736, 
  XED_IFORM_VMXON_MEMq=3737, 
  XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq=3738, 
  XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq=3739, 
  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=3740, 
  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=3741, 
  XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq=3742, 
  XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq=3743, 
  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=3744, 
  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=3745, 
  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=3746, 
  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=3747, 
  XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq=3748, 
  XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq=3749, 
  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=3750, 
  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=3751, 
  XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq=3752, 
  XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq=3753, 
  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=3754, 
  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=3755, 
  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=3756, 
  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=3757, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512=3758, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512=3759, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512=3760, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512=3761, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512=3762, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512=3763, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512=3764, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512=3765, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512=3766, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512=3767, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512=3768, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512=3769, 
  XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=3770, 
  XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=3771, 
  XED_IFORM_VPABSB_XMMdq_MEMdq=3772, 
  XED_IFORM_VPABSB_XMMdq_XMMdq=3773, 
  XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512=3774, 
  XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512=3775, 
  XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512=3776, 
  XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512=3777, 
  XED_IFORM_VPABSB_YMMqq_MEMqq=3778, 
  XED_IFORM_VPABSB_YMMqq_YMMqq=3779, 
  XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512=3780, 
  XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512=3781, 
  XED_IFORM_VPABSD_XMMdq_MEMdq=3782, 
  XED_IFORM_VPABSD_XMMdq_XMMdq=3783, 
  XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512=3784, 
  XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512=3785, 
  XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512=3786, 
  XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512=3787, 
  XED_IFORM_VPABSD_YMMqq_MEMqq=3788, 
  XED_IFORM_VPABSD_YMMqq_YMMqq=3789, 
  XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512=3790, 
  XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512=3791, 
  XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512=3792, 
  XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512=3793, 
  XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512=3794, 
  XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512=3795, 
  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512=3796, 
  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512=3797, 
  XED_IFORM_VPABSW_XMMdq_MEMdq=3798, 
  XED_IFORM_VPABSW_XMMdq_XMMdq=3799, 
  XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512=3800, 
  XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512=3801, 
  XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512=3802, 
  XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512=3803, 
  XED_IFORM_VPABSW_YMMqq_MEMqq=3804, 
  XED_IFORM_VPABSW_YMMqq_YMMqq=3805, 
  XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512=3806, 
  XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512=3807, 
  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq=3808, 
  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq=3809, 
  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512=3810, 
  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512=3811, 
  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512=3812, 
  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512=3813, 
  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq=3814, 
  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq=3815, 
  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512=3816, 
  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512=3817, 
  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq=3818, 
  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq=3819, 
  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512=3820, 
  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512=3821, 
  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512=3822, 
  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512=3823, 
  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq=3824, 
  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq=3825, 
  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512=3826, 
  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512=3827, 
  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq=3828, 
  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq=3829, 
  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512=3830, 
  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512=3831, 
  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq=3832, 
  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq=3833, 
  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512=3834, 
  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512=3835, 
  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512=3836, 
  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512=3837, 
  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq=3838, 
  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq=3839, 
  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512=3840, 
  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512=3841, 
  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq=3842, 
  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq=3843, 
  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512=3844, 
  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512=3845, 
  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512=3846, 
  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512=3847, 
  XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq=3848, 
  XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq=3849, 
  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3850, 
  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3851, 
  XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq=3852, 
  XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq=3853, 
  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3854, 
  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3855, 
  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3856, 
  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3857, 
  XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq=3858, 
  XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq=3859, 
  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=3860, 
  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=3861, 
  XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq=3862, 
  XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq=3863, 
  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=3864, 
  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=3865, 
  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=3866, 
  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=3867, 
  XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq=3868, 
  XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq=3869, 
  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=3870, 
  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=3871, 
  XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq=3872, 
  XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq=3873, 
  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=3874, 
  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=3875, 
  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=3876, 
  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=3877, 
  XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq=3878, 
  XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq=3879, 
  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=3880, 
  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=3881, 
  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=3882, 
  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=3883, 
  XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq=3884, 
  XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq=3885, 
  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=3886, 
  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=3887, 
  XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq=3888, 
  XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq=3889, 
  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=3890, 
  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=3891, 
  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=3892, 
  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=3893, 
  XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq=3894, 
  XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq=3895, 
  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=3896, 
  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=3897, 
  XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq=3898, 
  XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq=3899, 
  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3900, 
  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3901, 
  XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq=3902, 
  XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq=3903, 
  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3904, 
  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3905, 
  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3906, 
  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3907, 
  XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq=3908, 
  XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq=3909, 
  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=3910, 
  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=3911, 
  XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq=3912, 
  XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq=3913, 
  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=3914, 
  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=3915, 
  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=3916, 
  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=3917, 
  XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq=3918, 
  XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq=3919, 
  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=3920, 
  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=3921, 
  XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq=3922, 
  XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq=3923, 
  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=3924, 
  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=3925, 
  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=3926, 
  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=3927, 
  XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb=3928, 
  XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb=3929, 
  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=3930, 
  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=3931, 
  XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb=3932, 
  XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb=3933, 
  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=3934, 
  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=3935, 
  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=3936, 
  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=3937, 
  XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq=3938, 
  XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq=3939, 
  XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq=3940, 
  XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq=3941, 
  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=3942, 
  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=3943, 
  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=3944, 
  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=3945, 
  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=3946, 
  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=3947, 
  XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq=3948, 
  XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq=3949, 
  XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq=3950, 
  XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq=3951, 
  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=3952, 
  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=3953, 
  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=3954, 
  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=3955, 
  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=3956, 
  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=3957, 
  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=3958, 
  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=3959, 
  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=3960, 
  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=3961, 
  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=3962, 
  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=3963, 
  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=3964, 
  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=3965, 
  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=3966, 
  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=3967, 
  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=3968, 
  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=3969, 
  XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq=3970, 
  XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq=3971, 
  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3972, 
  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3973, 
  XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq=3974, 
  XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq=3975, 
  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3976, 
  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3977, 
  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3978, 
  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3979, 
  XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq=3980, 
  XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq=3981, 
  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=3982, 
  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=3983, 
  XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq=3984, 
  XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq=3985, 
  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=3986, 
  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=3987, 
  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=3988, 
  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=3989, 
  XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb=3990, 
  XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb=3991, 
  XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb=3992, 
  XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb=3993, 
  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3994, 
  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3995, 
  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3996, 
  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3997, 
  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3998, 
  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3999, 
  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4000, 
  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4001, 
  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4002, 
  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4003, 
  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4004, 
  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4005, 
  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4006, 
  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4007, 
  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4008, 
  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4009, 
  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4010, 
  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4011, 
  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4012, 
  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4013, 
  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4014, 
  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4015, 
  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4016, 
  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4017, 
  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq=4018, 
  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq=4019, 
  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq=4020, 
  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq=4021, 
  XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb=4022, 
  XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb=4023, 
  XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb=4024, 
  XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb=4025, 
  XED_IFORM_VPBROADCASTB_XMMdq_MEMb=4026, 
  XED_IFORM_VPBROADCASTB_XMMdq_XMMb=4027, 
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512=4028, 
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512=4029, 
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512=4030, 
  XED_IFORM_VPBROADCASTB_YMMqq_MEMb=4031, 
  XED_IFORM_VPBROADCASTB_YMMqq_XMMb=4032, 
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512=4033, 
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512=4034, 
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512=4035, 
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512=4036, 
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512=4037, 
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512=4038, 
  XED_IFORM_VPBROADCASTD_XMMdq_MEMd=4039, 
  XED_IFORM_VPBROADCASTD_XMMdq_XMMd=4040, 
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512=4041, 
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512=4042, 
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512=4043, 
  XED_IFORM_VPBROADCASTD_YMMqq_MEMd=4044, 
  XED_IFORM_VPBROADCASTD_YMMqq_XMMd=4045, 
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512=4046, 
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512=4047, 
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512=4048, 
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512=4049, 
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512=4050, 
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512=4051, 
  XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512=4052, 
  XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512=4053, 
  XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD=4054, 
  XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512=4055, 
  XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512=4056, 
  XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD=4057, 
  XED_IFORM_VPBROADCASTQ_XMMdq_MEMq=4058, 
  XED_IFORM_VPBROADCASTQ_XMMdq_XMMq=4059, 
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512=4060, 
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512=4061, 
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512=4062, 
  XED_IFORM_VPBROADCASTQ_YMMqq_MEMq=4063, 
  XED_IFORM_VPBROADCASTQ_YMMqq_XMMq=4064, 
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512=4065, 
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512=4066, 
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512=4067, 
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512=4068, 
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512=4069, 
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512=4070, 
  XED_IFORM_VPBROADCASTW_XMMdq_MEMw=4071, 
  XED_IFORM_VPBROADCASTW_XMMdq_XMMw=4072, 
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512=4073, 
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512=4074, 
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512=4075, 
  XED_IFORM_VPBROADCASTW_YMMqq_MEMw=4076, 
  XED_IFORM_VPBROADCASTW_YMMqq_XMMw=4077, 
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512=4078, 
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512=4079, 
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512=4080, 
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512=4081, 
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512=4082, 
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512=4083, 
  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb=4084, 
  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb=4085, 
  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512=4086, 
  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512=4087, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8=4088, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512=4089, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8=4090, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512=4091, 
  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512=4092, 
  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512=4093, 
  XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq=4094, 
  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq=4095, 
  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq=4096, 
  XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq=4097, 
  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq=4098, 
  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq=4099, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512=4100, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512=4101, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512=4102, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512=4103, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512=4104, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512=4105, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512=4106, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512=4107, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512=4108, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512=4109, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512=4110, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512=4111, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4112, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4113, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4114, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4115, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4116, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4117, 
  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq=4118, 
  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq=4119, 
  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq=4120, 
  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq=4121, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=4122, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=4123, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=4124, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=4125, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=4126, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=4127, 
  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq=4128, 
  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq=4129, 
  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq=4130, 
  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq=4131, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=4132, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=4133, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=4134, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=4135, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=4136, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=4137, 
  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq=4138, 
  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq=4139, 
  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq=4140, 
  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq=4141, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4142, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4143, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4144, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4145, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4146, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4147, 
  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq=4148, 
  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq=4149, 
  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq=4150, 
  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq=4151, 
  XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb=4152, 
  XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb=4153, 
  XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb=4154, 
  XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb=4155, 
  XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb=4156, 
  XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb=4157, 
  XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb=4158, 
  XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb=4159, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4160, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4161, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4162, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4163, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4164, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4165, 
  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq=4166, 
  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq=4167, 
  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq=4168, 
  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq=4169, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512=4170, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512=4171, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512=4172, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512=4173, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512=4174, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512=4175, 
  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq=4176, 
  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq=4177, 
  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq=4178, 
  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq=4179, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512=4180, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512=4181, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512=4182, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512=4183, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512=4184, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512=4185, 
  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq=4186, 
  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq=4187, 
  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq=4188, 
  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq=4189, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4190, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4191, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4192, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4193, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4194, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4195, 
  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq=4196, 
  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq=4197, 
  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq=4198, 
  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq=4199, 
  XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb=4200, 
  XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb=4201, 
  XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb=4202, 
  XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb=4203, 
  XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb=4204, 
  XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb=4205, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512=4206, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512=4207, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512=4208, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512=4209, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512=4210, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512=4211, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4212, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4213, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4214, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4215, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4216, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4217, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=4218, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=4219, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=4220, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=4221, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=4222, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=4223, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=4224, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=4225, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=4226, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=4227, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=4228, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=4229, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=4230, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=4231, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=4232, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=4233, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=4234, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=4235, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512=4236, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512=4237, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512=4238, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512=4239, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512=4240, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512=4241, 
  XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb=4242, 
  XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb=4243, 
  XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb=4244, 
  XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb=4245, 
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512=4246, 
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512=4247, 
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512=4248, 
  XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512=4249, 
  XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512=4250, 
  XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512=4251, 
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512=4252, 
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512=4253, 
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512=4254, 
  XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512=4255, 
  XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512=4256, 
  XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512=4257, 
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512=4258, 
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512=4259, 
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512=4260, 
  XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512=4261, 
  XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512=4262, 
  XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4263, 
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512=4264, 
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512=4265, 
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512=4266, 
  XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512=4267, 
  XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512=4268, 
  XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512=4269, 
  XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb=4270, 
  XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb=4271, 
  XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb=4272, 
  XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb=4273, 
  XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb=4274, 
  XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb=4275, 
  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb=4276, 
  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb=4277, 
  XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb=4278, 
  XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb=4279, 
  XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb=4280, 
  XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb=4281, 
  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512=4282, 
  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512=4283, 
  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512=4284, 
  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512=4285, 
  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=4286, 
  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=4287, 
  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512=4288, 
  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512=4289, 
  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512=4290, 
  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512=4291, 
  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=4292, 
  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=4293, 
  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4294, 
  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4295, 
  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4296, 
  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4297, 
  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4298, 
  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4299, 
  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4300, 
  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4301, 
  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4302, 
  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4303, 
  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4304, 
  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4305, 
  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4306, 
  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4307, 
  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4308, 
  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4309, 
  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4310, 
  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4311, 
  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4312, 
  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4313, 
  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4314, 
  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4315, 
  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4316, 
  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4317, 
  XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb=4318, 
  XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb=4319, 
  XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb=4320, 
  XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb=4321, 
  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4322, 
  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4323, 
  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4324, 
  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4325, 
  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4326, 
  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4327, 
  XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq=4328, 
  XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq=4329, 
  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4330, 
  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4331, 
  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4332, 
  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4333, 
  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4334, 
  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4335, 
  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4336, 
  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4337, 
  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4338, 
  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4339, 
  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4340, 
  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4341, 
  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4342, 
  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4343, 
  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4344, 
  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4345, 
  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4346, 
  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4347, 
  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4348, 
  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4349, 
  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4350, 
  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4351, 
  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4352, 
  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4353, 
  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4354, 
  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4355, 
  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4356, 
  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4357, 
  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4358, 
  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4359, 
  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4360, 
  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4361, 
  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4362, 
  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4363, 
  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4364, 
  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4365, 
  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4366, 
  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4367, 
  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4368, 
  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4369, 
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4370, 
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4371, 
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4372, 
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4373, 
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4374, 
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4375, 
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4376, 
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4377, 
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4378, 
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4379, 
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4380, 
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4381, 
  XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb=4382, 
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb=4383, 
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq=4384, 
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq=4385, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=4386, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=4387, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4388, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4389, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4390, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4391, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4392, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4393, 
  XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb=4394, 
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb=4395, 
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq=4396, 
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq=4397, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4398, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4399, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4400, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4401, 
  XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb=4402, 
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb=4403, 
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq=4404, 
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq=4405, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=4406, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=4407, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4408, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4409, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=4410, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=4411, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4412, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4413, 
  XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb=4414, 
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb=4415, 
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq=4416, 
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq=4417, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=4418, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=4419, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4420, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4421, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4422, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4423, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4424, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4425, 
  XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb=4426, 
  XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb=4427, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4428, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4429, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4430, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4431, 
  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4432, 
  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4433, 
  XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq=4434, 
  XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq=4435, 
  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4436, 
  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4437, 
  XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb=4438, 
  XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb=4439, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=4440, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=4441, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4442, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4443, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=4444, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=4445, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4446, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4447, 
  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4448, 
  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4449, 
  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4450, 
  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4451, 
  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4452, 
  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4453, 
  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4454, 
  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4455, 
  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4456, 
  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4457, 
  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4458, 
  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4459, 
  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4460, 
  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4461, 
  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4462, 
  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4463, 
  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4464, 
  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4465, 
  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4466, 
  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4467, 
  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4468, 
  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4469, 
  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4470, 
  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4471, 
  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4472, 
  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4473, 
  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4474, 
  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4475, 
  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4476, 
  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4477, 
  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4478, 
  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4479, 
  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4480, 
  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4481, 
  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4482, 
  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4483, 
  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4484, 
  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4485, 
  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4486, 
  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4487, 
  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4488, 
  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4489, 
  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512=4490, 
  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512=4491, 
  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512=4492, 
  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512=4493, 
  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512=4494, 
  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512=4495, 
  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512=4496, 
  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512=4497, 
  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512=4498, 
  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512=4499, 
  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512=4500, 
  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512=4501, 
  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512=4502, 
  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512=4503, 
  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512=4504, 
  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512=4505, 
  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512=4506, 
  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4507, 
  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512=4508, 
  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512=4509, 
  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512=4510, 
  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512=4511, 
  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512=4512, 
  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512=4513, 
  XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb=4514, 
  XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512=4515, 
  XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb=4516, 
  XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512=4517, 
  XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb=4518, 
  XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512=4519, 
  XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb=4520, 
  XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512=4521, 
  XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb=4522, 
  XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512=4523, 
  XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb=4524, 
  XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512=4525, 
  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15=4526, 
  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5=4527, 
  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512=4528, 
  XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512=4529, 
  XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb=4530, 
  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5=4531, 
  XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4532, 
  XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128=4533, 
  XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256=4534, 
  XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256=4535, 
  XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512=4536, 
  XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=4537, 
  XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128=4538, 
  XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=4539, 
  XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256=4540, 
  XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=4541, 
  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4542, 
  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256=4543, 
  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128=4544, 
  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256=4545, 
  XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512=4546, 
  XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=4547, 
  XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128=4548, 
  XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=4549, 
  XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256=4550, 
  XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=4551, 
  XED_IFORM_VPHADDBD_XMMdq_MEMdq=4552, 
  XED_IFORM_VPHADDBD_XMMdq_XMMdq=4553, 
  XED_IFORM_VPHADDBQ_XMMdq_MEMdq=4554, 
  XED_IFORM_VPHADDBQ_XMMdq_XMMdq=4555, 
  XED_IFORM_VPHADDBW_XMMdq_MEMdq=4556, 
  XED_IFORM_VPHADDBW_XMMdq_XMMdq=4557, 
  XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq=4558, 
  XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq=4559, 
  XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq=4560, 
  XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq=4561, 
  XED_IFORM_VPHADDDQ_XMMdq_MEMdq=4562, 
  XED_IFORM_VPHADDDQ_XMMdq_XMMdq=4563, 
  XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq=4564, 
  XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq=4565, 
  XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq=4566, 
  XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq=4567, 
  XED_IFORM_VPHADDUBD_XMMdq_MEMdq=4568, 
  XED_IFORM_VPHADDUBD_XMMdq_XMMdq=4569, 
  XED_IFORM_VPHADDUBQ_XMMdq_MEMdq=4570, 
  XED_IFORM_VPHADDUBQ_XMMdq_XMMdq=4571, 
  XED_IFORM_VPHADDUBW_XMMdq_MEMdq=4572, 
  XED_IFORM_VPHADDUBW_XMMdq_XMMdq=4573, 
  XED_IFORM_VPHADDUDQ_XMMdq_MEMdq=4574, 
  XED_IFORM_VPHADDUDQ_XMMdq_XMMdq=4575, 
  XED_IFORM_VPHADDUWD_XMMdq_MEMdq=4576, 
  XED_IFORM_VPHADDUWD_XMMdq_XMMdq=4577, 
  XED_IFORM_VPHADDUWQ_XMMdq_MEMdq=4578, 
  XED_IFORM_VPHADDUWQ_XMMdq_XMMdq=4579, 
  XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq=4580, 
  XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq=4581, 
  XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq=4582, 
  XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq=4583, 
  XED_IFORM_VPHADDWD_XMMdq_MEMdq=4584, 
  XED_IFORM_VPHADDWD_XMMdq_XMMdq=4585, 
  XED_IFORM_VPHADDWQ_XMMdq_MEMdq=4586, 
  XED_IFORM_VPHADDWQ_XMMdq_XMMdq=4587, 
  XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq=4588, 
  XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq=4589, 
  XED_IFORM_VPHSUBBW_XMMdq_MEMdq=4590, 
  XED_IFORM_VPHSUBBW_XMMdq_XMMdq=4591, 
  XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq=4592, 
  XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq=4593, 
  XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq=4594, 
  XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq=4595, 
  XED_IFORM_VPHSUBDQ_XMMdq_MEMdq=4596, 
  XED_IFORM_VPHSUBDQ_XMMdq_XMMdq=4597, 
  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq=4598, 
  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq=4599, 
  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq=4600, 
  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq=4601, 
  XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq=4602, 
  XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq=4603, 
  XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq=4604, 
  XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq=4605, 
  XED_IFORM_VPHSUBWD_XMMdq_MEMdq=4606, 
  XED_IFORM_VPHSUBWD_XMMdq_XMMdq=4607, 
  XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb=4608, 
  XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb=4609, 
  XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512=4610, 
  XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512=4611, 
  XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb=4612, 
  XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb=4613, 
  XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512=4614, 
  XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512=4615, 
  XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb=4616, 
  XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb=4617, 
  XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512=4618, 
  XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512=4619, 
  XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb=4620, 
  XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb=4621, 
  XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512=4622, 
  XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512=4623, 
  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512=4624, 
  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512=4625, 
  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512=4626, 
  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512=4627, 
  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=4628, 
  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=4629, 
  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=4630, 
  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=4631, 
  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=4632, 
  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=4633, 
  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=4634, 
  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=4635, 
  XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq=4636, 
  XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq=4637, 
  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq=4638, 
  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq=4639, 
  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq=4640, 
  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq=4641, 
  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq=4642, 
  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq=4643, 
  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq=4644, 
  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq=4645, 
  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq=4646, 
  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq=4647, 
  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq=4648, 
  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq=4649, 
  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq=4650, 
  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq=4651, 
  XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq=4652, 
  XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq=4653, 
  XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq=4654, 
  XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq=4655, 
  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq=4656, 
  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq=4657, 
  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq=4658, 
  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq=4659, 
  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4660, 
  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4661, 
  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4662, 
  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4663, 
  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4664, 
  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4665, 
  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4666, 
  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4667, 
  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4668, 
  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4669, 
  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4670, 
  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4671, 
  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq=4672, 
  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq=4673, 
  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=4674, 
  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=4675, 
  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=4676, 
  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=4677, 
  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq=4678, 
  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq=4679, 
  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=4680, 
  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=4681, 
  XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq=4682, 
  XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq=4683, 
  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512=4684, 
  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512=4685, 
  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512=4686, 
  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512=4687, 
  XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq=4688, 
  XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq=4689, 
  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512=4690, 
  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512=4691, 
  XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq=4692, 
  XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq=4693, 
  XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq=4694, 
  XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq=4695, 
  XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq=4696, 
  XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq=4697, 
  XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq=4698, 
  XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq=4699, 
  XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq=4700, 
  XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq=4701, 
  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=4702, 
  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=4703, 
  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=4704, 
  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=4705, 
  XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq=4706, 
  XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq=4707, 
  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=4708, 
  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=4709, 
  XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq=4710, 
  XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq=4711, 
  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=4712, 
  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=4713, 
  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=4714, 
  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=4715, 
  XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq=4716, 
  XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq=4717, 
  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=4718, 
  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=4719, 
  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=4720, 
  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=4721, 
  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=4722, 
  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=4723, 
  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=4724, 
  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=4725, 
  XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq=4726, 
  XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq=4727, 
  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=4728, 
  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=4729, 
  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=4730, 
  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=4731, 
  XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq=4732, 
  XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq=4733, 
  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=4734, 
  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=4735, 
  XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq=4736, 
  XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq=4737, 
  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4738, 
  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4739, 
  XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq=4740, 
  XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq=4741, 
  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4742, 
  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4743, 
  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4744, 
  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4745, 
  XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq=4746, 
  XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq=4747, 
  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4748, 
  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4749, 
  XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq=4750, 
  XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq=4751, 
  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4752, 
  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4753, 
  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4754, 
  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4755, 
  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4756, 
  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4757, 
  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4758, 
  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4759, 
  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4760, 
  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4761, 
  XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq=4762, 
  XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq=4763, 
  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4764, 
  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4765, 
  XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq=4766, 
  XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq=4767, 
  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4768, 
  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4769, 
  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4770, 
  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4771, 
  XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq=4772, 
  XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq=4773, 
  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=4774, 
  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=4775, 
  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=4776, 
  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=4777, 
  XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq=4778, 
  XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq=4779, 
  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=4780, 
  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=4781, 
  XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq=4782, 
  XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq=4783, 
  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=4784, 
  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=4785, 
  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=4786, 
  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=4787, 
  XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq=4788, 
  XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq=4789, 
  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=4790, 
  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=4791, 
  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=4792, 
  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=4793, 
  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=4794, 
  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=4795, 
  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=4796, 
  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=4797, 
  XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq=4798, 
  XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq=4799, 
  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=4800, 
  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=4801, 
  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=4802, 
  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=4803, 
  XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq=4804, 
  XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq=4805, 
  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=4806, 
  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=4807, 
  XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq=4808, 
  XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq=4809, 
  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4810, 
  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4811, 
  XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq=4812, 
  XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq=4813, 
  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4814, 
  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4815, 
  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4816, 
  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4817, 
  XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq=4818, 
  XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq=4819, 
  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4820, 
  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4821, 
  XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq=4822, 
  XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq=4823, 
  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4824, 
  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4825, 
  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4826, 
  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4827, 
  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4828, 
  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4829, 
  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4830, 
  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4831, 
  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4832, 
  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4833, 
  XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq=4834, 
  XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq=4835, 
  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4836, 
  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4837, 
  XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq=4838, 
  XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq=4839, 
  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4840, 
  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4841, 
  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4842, 
  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4843, 
  XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512=4844, 
  XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512=4845, 
  XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512=4846, 
  XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512=4847, 
  XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512=4848, 
  XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512=4849, 
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512=4850, 
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512=4851, 
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512=4852, 
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512=4853, 
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512=4854, 
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512=4855, 
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512=4856, 
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512=4857, 
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512=4858, 
  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512=4859, 
  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512=4860, 
  XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512=4861, 
  XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512=4862, 
  XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512=4863, 
  XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512=4864, 
  XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512=4865, 
  XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512=4866, 
  XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512=4867, 
  XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512=4868, 
  XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512=4869, 
  XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512=4870, 
  XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512=4871, 
  XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512=4872, 
  XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512=4873, 
  XED_IFORM_VPMOVMSKB_GPR32d_XMMdq=4874, 
  XED_IFORM_VPMOVMSKB_GPR32d_YMMqq=4875, 
  XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512=4876, 
  XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512=4877, 
  XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512=4878, 
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512=4879, 
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512=4880, 
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512=4881, 
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512=4882, 
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512=4883, 
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512=4884, 
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512=4885, 
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512=4886, 
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512=4887, 
  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512=4888, 
  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512=4889, 
  XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512=4890, 
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512=4891, 
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512=4892, 
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512=4893, 
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512=4894, 
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512=4895, 
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512=4896, 
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512=4897, 
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512=4898, 
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512=4899, 
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512=4900, 
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512=4901, 
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512=4902, 
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512=4903, 
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512=4904, 
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512=4905, 
  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512=4906, 
  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512=4907, 
  XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512=4908, 
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512=4909, 
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512=4910, 
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512=4911, 
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512=4912, 
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512=4913, 
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512=4914, 
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512=4915, 
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512=4916, 
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512=4917, 
  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512=4918, 
  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512=4919, 
  XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512=4920, 
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512=4921, 
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512=4922, 
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512=4923, 
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512=4924, 
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512=4925, 
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512=4926, 
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512=4927, 
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512=4928, 
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512=4929, 
  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512=4930, 
  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512=4931, 
  XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512=4932, 
  XED_IFORM_VPMOVSXBD_XMMdq_MEMd=4933, 
  XED_IFORM_VPMOVSXBD_XMMdq_XMMd=4934, 
  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512=4935, 
  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512=4936, 
  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512=4937, 
  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512=4938, 
  XED_IFORM_VPMOVSXBD_YMMqq_MEMq=4939, 
  XED_IFORM_VPMOVSXBD_YMMqq_XMMq=4940, 
  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512=4941, 
  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512=4942, 
  XED_IFORM_VPMOVSXBQ_XMMdq_MEMw=4943, 
  XED_IFORM_VPMOVSXBQ_XMMdq_XMMw=4944, 
  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512=4945, 
  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512=4946, 
  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512=4947, 
  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512=4948, 
  XED_IFORM_VPMOVSXBQ_YMMqq_MEMd=4949, 
  XED_IFORM_VPMOVSXBQ_YMMqq_XMMd=4950, 
  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=4951, 
  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=4952, 
  XED_IFORM_VPMOVSXBW_XMMdq_MEMq=4953, 
  XED_IFORM_VPMOVSXBW_XMMdq_XMMq=4954, 
  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512=4955, 
  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512=4956, 
  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512=4957, 
  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512=4958, 
  XED_IFORM_VPMOVSXBW_YMMqq_MEMdq=4959, 
  XED_IFORM_VPMOVSXBW_YMMqq_XMMdq=4960, 
  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512=4961, 
  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512=4962, 
  XED_IFORM_VPMOVSXDQ_XMMdq_MEMq=4963, 
  XED_IFORM_VPMOVSXDQ_XMMdq_XMMq=4964, 
  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512=4965, 
  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512=4966, 
  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512=4967, 
  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512=4968, 
  XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq=4969, 
  XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq=4970, 
  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=4971, 
  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=4972, 
  XED_IFORM_VPMOVSXWD_XMMdq_MEMq=4973, 
  XED_IFORM_VPMOVSXWD_XMMdq_XMMq=4974, 
  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512=4975, 
  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512=4976, 
  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512=4977, 
  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512=4978, 
  XED_IFORM_VPMOVSXWD_YMMqq_MEMdq=4979, 
  XED_IFORM_VPMOVSXWD_YMMqq_XMMdq=4980, 
  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512=4981, 
  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512=4982, 
  XED_IFORM_VPMOVSXWQ_XMMdq_MEMd=4983, 
  XED_IFORM_VPMOVSXWQ_XMMdq_XMMd=4984, 
  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512=4985, 
  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512=4986, 
  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512=4987, 
  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512=4988, 
  XED_IFORM_VPMOVSXWQ_YMMqq_MEMq=4989, 
  XED_IFORM_VPMOVSXWQ_YMMqq_XMMq=4990, 
  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=4991, 
  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=4992, 
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512=4993, 
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512=4994, 
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512=4995, 
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512=4996, 
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512=4997, 
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512=4998, 
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512=4999, 
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512=5000, 
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512=5001, 
  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512=5002, 
  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512=5003, 
  XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512=5004, 
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512=5005, 
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512=5006, 
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512=5007, 
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512=5008, 
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512=5009, 
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512=5010, 
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512=5011, 
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512=5012, 
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512=5013, 
  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512=5014, 
  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512=5015, 
  XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512=5016, 
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512=5017, 
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512=5018, 
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512=5019, 
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512=5020, 
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512=5021, 
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512=5022, 
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512=5023, 
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512=5024, 
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512=5025, 
  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512=5026, 
  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512=5027, 
  XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512=5028, 
  XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512=5029, 
  XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512=5030, 
  XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512=5031, 
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512=5032, 
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512=5033, 
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512=5034, 
  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512=5035, 
  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512=5036, 
  XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512=5037, 
  XED_IFORM_VPMOVZXBD_XMMdq_MEMd=5038, 
  XED_IFORM_VPMOVZXBD_XMMdq_XMMd=5039, 
  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512=5040, 
  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512=5041, 
  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512=5042, 
  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512=5043, 
  XED_IFORM_VPMOVZXBD_YMMqq_MEMq=5044, 
  XED_IFORM_VPMOVZXBD_YMMqq_XMMq=5045, 
  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5046, 
  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5047, 
  XED_IFORM_VPMOVZXBQ_XMMdq_MEMw=5048, 
  XED_IFORM_VPMOVZXBQ_XMMdq_XMMw=5049, 
  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5050, 
  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5051, 
  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5052, 
  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5053, 
  XED_IFORM_VPMOVZXBQ_YMMqq_MEMd=5054, 
  XED_IFORM_VPMOVZXBQ_YMMqq_XMMd=5055, 
  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5056, 
  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5057, 
  XED_IFORM_VPMOVZXBW_XMMdq_MEMq=5058, 
  XED_IFORM_VPMOVZXBW_XMMdq_XMMq=5059, 
  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512=5060, 
  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512=5061, 
  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512=5062, 
  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512=5063, 
  XED_IFORM_VPMOVZXBW_YMMqq_MEMdq=5064, 
  XED_IFORM_VPMOVZXBW_YMMqq_XMMdq=5065, 
  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5066, 
  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5067, 
  XED_IFORM_VPMOVZXDQ_XMMdq_MEMq=5068, 
  XED_IFORM_VPMOVZXDQ_XMMdq_XMMq=5069, 
  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5070, 
  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5071, 
  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5072, 
  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5073, 
  XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq=5074, 
  XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq=5075, 
  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5076, 
  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5077, 
  XED_IFORM_VPMOVZXWD_XMMdq_MEMq=5078, 
  XED_IFORM_VPMOVZXWD_XMMdq_XMMq=5079, 
  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512=5080, 
  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512=5081, 
  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512=5082, 
  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512=5083, 
  XED_IFORM_VPMOVZXWD_YMMqq_MEMdq=5084, 
  XED_IFORM_VPMOVZXWD_YMMqq_XMMdq=5085, 
  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5086, 
  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5087, 
  XED_IFORM_VPMOVZXWQ_XMMdq_MEMd=5088, 
  XED_IFORM_VPMOVZXWQ_XMMdq_XMMd=5089, 
  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5090, 
  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5091, 
  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5092, 
  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5093, 
  XED_IFORM_VPMOVZXWQ_YMMqq_MEMq=5094, 
  XED_IFORM_VPMOVZXWQ_YMMqq_XMMq=5095, 
  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5096, 
  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5097, 
  XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq=5098, 
  XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq=5099, 
  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512=5100, 
  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512=5101, 
  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512=5102, 
  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512=5103, 
  XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq=5104, 
  XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq=5105, 
  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512=5106, 
  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512=5107, 
  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq=5108, 
  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq=5109, 
  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5110, 
  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5111, 
  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5112, 
  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5113, 
  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq=5114, 
  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq=5115, 
  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5116, 
  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5117, 
  XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq=5118, 
  XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq=5119, 
  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5120, 
  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5121, 
  XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq=5122, 
  XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq=5123, 
  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5124, 
  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5125, 
  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5126, 
  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5127, 
  XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq=5128, 
  XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq=5129, 
  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5130, 
  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5131, 
  XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq=5132, 
  XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq=5133, 
  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5134, 
  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5135, 
  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5136, 
  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5137, 
  XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq=5138, 
  XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq=5139, 
  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5140, 
  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5141, 
  XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq=5142, 
  XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq=5143, 
  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5144, 
  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5145, 
  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5146, 
  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5147, 
  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5148, 
  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5149, 
  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5150, 
  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5151, 
  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5152, 
  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5153, 
  XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq=5154, 
  XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq=5155, 
  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5156, 
  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5157, 
  XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq=5158, 
  XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq=5159, 
  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5160, 
  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5161, 
  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5162, 
  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5163, 
  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512=5164, 
  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512=5165, 
  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512=5166, 
  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512=5167, 
  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512=5168, 
  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512=5169, 
  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq=5170, 
  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq=5171, 
  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512=5172, 
  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512=5173, 
  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq=5174, 
  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq=5175, 
  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512=5176, 
  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512=5177, 
  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512=5178, 
  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512=5179, 
  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512=5180, 
  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512=5181, 
  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512=5182, 
  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512=5183, 
  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512=5184, 
  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512=5185, 
  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5186, 
  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5187, 
  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5188, 
  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5189, 
  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512=5190, 
  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512=5191, 
  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5192, 
  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5193, 
  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5194, 
  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5195, 
  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512=5196, 
  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512=5197, 
  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512=5198, 
  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512=5199, 
  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512=5200, 
  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512=5201, 
  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512=5202, 
  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512=5203, 
  XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq=5204, 
  XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq=5205, 
  XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq=5206, 
  XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq=5207, 
  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5208, 
  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5209, 
  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5210, 
  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5211, 
  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5212, 
  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5213, 
  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5214, 
  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5215, 
  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5216, 
  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5217, 
  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5218, 
  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5219, 
  XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq=5220, 
  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq=5221, 
  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq=5222, 
  XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5223, 
  XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5224, 
  XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5225, 
  XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5226, 
  XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5227, 
  XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5228, 
  XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5229, 
  XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5230, 
  XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5231, 
  XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5232, 
  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5233, 
  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5234, 
  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5235, 
  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5236, 
  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5237, 
  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5238, 
  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5239, 
  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5240, 
  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5241, 
  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5242, 
  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5243, 
  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5244, 
  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5245, 
  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5246, 
  XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5247, 
  XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5248, 
  XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5249, 
  XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5250, 
  XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5251, 
  XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5252, 
  XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5253, 
  XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5254, 
  XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5255, 
  XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5256, 
  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5257, 
  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5258, 
  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5259, 
  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5260, 
  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5261, 
  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5262, 
  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5263, 
  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5264, 
  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5265, 
  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5266, 
  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5267, 
  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5268, 
  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5269, 
  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5270, 
  XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb=5271, 
  XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq=5272, 
  XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb=5273, 
  XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq=5274, 
  XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq=5275, 
  XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb=5276, 
  XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq=5277, 
  XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb=5278, 
  XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq=5279, 
  XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq=5280, 
  XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb=5281, 
  XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq=5282, 
  XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb=5283, 
  XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq=5284, 
  XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq=5285, 
  XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb=5286, 
  XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq=5287, 
  XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb=5288, 
  XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq=5289, 
  XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq=5290, 
  XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq=5291, 
  XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq=5292, 
  XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512=5293, 
  XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512=5294, 
  XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq=5295, 
  XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq=5296, 
  XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512=5297, 
  XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512=5298, 
  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512=5299, 
  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512=5300, 
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5301, 
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256=5302, 
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512=5303, 
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5304, 
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5305, 
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5306, 
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5307, 
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256=5308, 
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512=5309, 
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5310, 
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5311, 
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5312, 
  XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq=5313, 
  XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq=5314, 
  XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq=5315, 
  XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq=5316, 
  XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq=5317, 
  XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq=5318, 
  XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq=5319, 
  XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq=5320, 
  XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq=5321, 
  XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq=5322, 
  XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq=5323, 
  XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq=5324, 
  XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq=5325, 
  XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq=5326, 
  XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq=5327, 
  XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq=5328, 
  XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq=5329, 
  XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq=5330, 
  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5331, 
  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5332, 
  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5333, 
  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5334, 
  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5335, 
  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5336, 
  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5337, 
  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5338, 
  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5339, 
  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5340, 
  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5341, 
  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5342, 
  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5343, 
  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5344, 
  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5345, 
  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5346, 
  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5347, 
  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5348, 
  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5349, 
  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5350, 
  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5351, 
  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5352, 
  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5353, 
  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5354, 
  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5355, 
  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5356, 
  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5357, 
  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5358, 
  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5359, 
  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5360, 
  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5361, 
  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5362, 
  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5363, 
  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5364, 
  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5365, 
  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5366, 
  XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq=5367, 
  XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq=5368, 
  XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq=5369, 
  XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq=5370, 
  XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq=5371, 
  XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq=5372, 
  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5373, 
  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5374, 
  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5375, 
  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5376, 
  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5377, 
  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5378, 
  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5379, 
  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5380, 
  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5381, 
  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5382, 
  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5383, 
  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5384, 
  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5385, 
  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5386, 
  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5387, 
  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5388, 
  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5389, 
  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5390, 
  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5391, 
  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5392, 
  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5393, 
  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5394, 
  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5395, 
  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5396, 
  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5397, 
  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5398, 
  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5399, 
  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5400, 
  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5401, 
  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5402, 
  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5403, 
  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5404, 
  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5405, 
  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5406, 
  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5407, 
  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5408, 
  XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq=5409, 
  XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq=5410, 
  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5411, 
  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5412, 
  XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq=5413, 
  XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq=5414, 
  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5415, 
  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5416, 
  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5417, 
  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5418, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512=5419, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512=5420, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512=5421, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512=5422, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512=5423, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512=5424, 
  XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb=5425, 
  XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb=5426, 
  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5427, 
  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5428, 
  XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb=5429, 
  XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb=5430, 
  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5431, 
  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5432, 
  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5433, 
  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5434, 
  XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb=5435, 
  XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb=5436, 
  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5437, 
  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5438, 
  XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb=5439, 
  XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb=5440, 
  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5441, 
  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5442, 
  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5443, 
  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5444, 
  XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb=5445, 
  XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb=5446, 
  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5447, 
  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5448, 
  XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb=5449, 
  XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb=5450, 
  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5451, 
  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5452, 
  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5453, 
  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5454, 
  XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq=5455, 
  XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq=5456, 
  XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq=5457, 
  XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq=5458, 
  XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq=5459, 
  XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq=5460, 
  XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq=5461, 
  XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq=5462, 
  XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq=5463, 
  XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq=5464, 
  XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq=5465, 
  XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq=5466, 
  XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb=5467, 
  XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq=5468, 
  XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq=5469, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5470, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5471, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5472, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5473, 
  XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb=5474, 
  XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq=5475, 
  XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq=5476, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5477, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5478, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5479, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=5480, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5481, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5482, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5483, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=5484, 
  XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb=5485, 
  XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512=5486, 
  XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512=5487, 
  XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb=5488, 
  XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512=5489, 
  XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512=5490, 
  XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512=5491, 
  XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512=5492, 
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb=5493, 
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq=5494, 
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq=5495, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5496, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5497, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5498, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5499, 
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb=5500, 
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq=5501, 
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq=5502, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5503, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5504, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5505, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=5506, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5507, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5508, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5509, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=5510, 
  XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq=5511, 
  XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq=5512, 
  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5513, 
  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5514, 
  XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq=5515, 
  XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq=5516, 
  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5517, 
  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5518, 
  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5519, 
  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5520, 
  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq=5521, 
  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq=5522, 
  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5523, 
  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5524, 
  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq=5525, 
  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq=5526, 
  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5527, 
  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5528, 
  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5529, 
  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5530, 
  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5531, 
  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5532, 
  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5533, 
  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5534, 
  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5535, 
  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5536, 
  XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb=5537, 
  XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq=5538, 
  XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq=5539, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5540, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5541, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5542, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5543, 
  XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb=5544, 
  XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq=5545, 
  XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq=5546, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5547, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5548, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5549, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=5550, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5551, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5552, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5553, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=5554, 
  XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb=5555, 
  XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq=5556, 
  XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq=5557, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5558, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5559, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5560, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5561, 
  XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb=5562, 
  XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq=5563, 
  XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq=5564, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5565, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5566, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5567, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=5568, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5569, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5570, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5571, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=5572, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5573, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5574, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5575, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5576, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5577, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5578, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5579, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=5580, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5581, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5582, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5583, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=5584, 
  XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq=5585, 
  XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq=5586, 
  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5587, 
  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5588, 
  XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq=5589, 
  XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq=5590, 
  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5591, 
  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5592, 
  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5593, 
  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5594, 
  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5595, 
  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5596, 
  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5597, 
  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5598, 
  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5599, 
  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5600, 
  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5601, 
  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5602, 
  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5603, 
  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5604, 
  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5605, 
  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5606, 
  XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb=5607, 
  XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq=5608, 
  XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq=5609, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5610, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5611, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5612, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5613, 
  XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb=5614, 
  XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq=5615, 
  XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq=5616, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5617, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5618, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5619, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=5620, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5621, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5622, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5623, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=5624, 
  XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb=5625, 
  XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq=5626, 
  XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq=5627, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5628, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5629, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5630, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5631, 
  XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb=5632, 
  XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq=5633, 
  XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq=5634, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5635, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5636, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5637, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=5638, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5639, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5640, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5641, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=5642, 
  XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb=5643, 
  XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512=5644, 
  XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512=5645, 
  XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb=5646, 
  XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512=5647, 
  XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512=5648, 
  XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512=5649, 
  XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512=5650, 
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb=5651, 
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq=5652, 
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq=5653, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5654, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5655, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5656, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5657, 
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb=5658, 
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq=5659, 
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq=5660, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5661, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5662, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5663, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=5664, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5665, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5666, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5667, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=5668, 
  XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq=5669, 
  XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq=5670, 
  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5671, 
  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5672, 
  XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq=5673, 
  XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq=5674, 
  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5675, 
  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5676, 
  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5677, 
  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5678, 
  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq=5679, 
  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq=5680, 
  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5681, 
  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5682, 
  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq=5683, 
  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq=5684, 
  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5685, 
  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5686, 
  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5687, 
  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5688, 
  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5689, 
  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5690, 
  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5691, 
  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5692, 
  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5693, 
  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5694, 
  XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb=5695, 
  XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq=5696, 
  XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq=5697, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5698, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5699, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5700, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5701, 
  XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb=5702, 
  XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq=5703, 
  XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq=5704, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5705, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5706, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5707, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=5708, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5709, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5710, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5711, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=5712, 
  XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq=5713, 
  XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq=5714, 
  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5715, 
  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5716, 
  XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq=5717, 
  XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq=5718, 
  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5719, 
  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5720, 
  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5721, 
  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5722, 
  XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq=5723, 
  XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq=5724, 
  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5725, 
  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5726, 
  XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq=5727, 
  XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq=5728, 
  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5729, 
  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5730, 
  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5731, 
  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5732, 
  XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq=5733, 
  XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq=5734, 
  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5735, 
  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5736, 
  XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq=5737, 
  XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq=5738, 
  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5739, 
  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5740, 
  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5741, 
  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5742, 
  XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq=5743, 
  XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq=5744, 
  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5745, 
  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5746, 
  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5747, 
  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5748, 
  XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq=5749, 
  XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq=5750, 
  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5751, 
  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5752, 
  XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq=5753, 
  XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq=5754, 
  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5755, 
  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5756, 
  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5757, 
  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5758, 
  XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq=5759, 
  XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq=5760, 
  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5761, 
  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5762, 
  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq=5763, 
  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq=5764, 
  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5765, 
  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5766, 
  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq=5767, 
  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq=5768, 
  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5769, 
  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5770, 
  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5771, 
  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5772, 
  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq=5773, 
  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq=5774, 
  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5775, 
  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5776, 
  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq=5777, 
  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq=5778, 
  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5779, 
  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5780, 
  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5781, 
  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5782, 
  XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq=5783, 
  XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq=5784, 
  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5785, 
  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5786, 
  XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq=5787, 
  XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq=5788, 
  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5789, 
  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5790, 
  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5791, 
  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5792, 
  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5793, 
  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5794, 
  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5795, 
  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5796, 
  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5797, 
  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5798, 
  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5799, 
  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5800, 
  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5801, 
  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5802, 
  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5803, 
  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5804, 
  XED_IFORM_VPTEST_XMMdq_MEMdq=5805, 
  XED_IFORM_VPTEST_XMMdq_XMMdq=5806, 
  XED_IFORM_VPTEST_YMMqq_MEMqq=5807, 
  XED_IFORM_VPTEST_YMMqq_YMMqq=5808, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=5809, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=5810, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=5811, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=5812, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=5813, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=5814, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=5815, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=5816, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=5817, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=5818, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=5819, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=5820, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=5821, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=5822, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=5823, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=5824, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=5825, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=5826, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=5827, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=5828, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=5829, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=5830, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=5831, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=5832, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=5833, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=5834, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=5835, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=5836, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=5837, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=5838, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=5839, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=5840, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=5841, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=5842, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=5843, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=5844, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=5845, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=5846, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=5847, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=5848, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=5849, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=5850, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=5851, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=5852, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=5853, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=5854, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=5855, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=5856, 
  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq=5857, 
  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq=5858, 
  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5859, 
  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5860, 
  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq=5861, 
  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq=5862, 
  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5863, 
  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5864, 
  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5865, 
  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5866, 
  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq=5867, 
  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq=5868, 
  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5869, 
  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5870, 
  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq=5871, 
  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq=5872, 
  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5873, 
  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5874, 
  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5875, 
  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5876, 
  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq=5877, 
  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq=5878, 
  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5879, 
  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5880, 
  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq=5881, 
  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq=5882, 
  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5883, 
  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5884, 
  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5885, 
  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5886, 
  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq=5887, 
  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq=5888, 
  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5889, 
  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5890, 
  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq=5891, 
  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq=5892, 
  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5893, 
  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5894, 
  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5895, 
  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5896, 
  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq=5897, 
  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq=5898, 
  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5899, 
  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5900, 
  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq=5901, 
  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq=5902, 
  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5903, 
  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5904, 
  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5905, 
  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5906, 
  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq=5907, 
  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq=5908, 
  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5909, 
  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5910, 
  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq=5911, 
  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq=5912, 
  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5913, 
  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5914, 
  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5915, 
  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5916, 
  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq=5917, 
  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq=5918, 
  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5919, 
  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5920, 
  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq=5921, 
  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq=5922, 
  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5923, 
  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5924, 
  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5925, 
  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5926, 
  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq=5927, 
  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq=5928, 
  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5929, 
  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5930, 
  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq=5931, 
  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq=5932, 
  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5933, 
  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5934, 
  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5935, 
  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5936, 
  XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq=5937, 
  XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq=5938, 
  XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq=5939, 
  XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq=5940, 
  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5941, 
  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5942, 
  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5943, 
  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5944, 
  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5945, 
  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5946, 
  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5947, 
  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5948, 
  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5949, 
  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5950, 
  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5951, 
  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5952, 
  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=5953, 
  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=5954, 
  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=5955, 
  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=5956, 
  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=5957, 
  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=5958, 
  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=5959, 
  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=5960, 
  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=5961, 
  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=5962, 
  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=5963, 
  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=5964, 
  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=5965, 
  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=5966, 
  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=5967, 
  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=5968, 
  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512=5969, 
  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512=5970, 
  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512=5971, 
  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512=5972, 
  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512=5973, 
  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=5974, 
  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512=5975, 
  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512=5976, 
  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512=5977, 
  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512=5978, 
  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512=5979, 
  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=5980, 
  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=5981, 
  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=5982, 
  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=5983, 
  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=5984, 
  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=5985, 
  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=5986, 
  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=5987, 
  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=5988, 
  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=5989, 
  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=5990, 
  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=5991, 
  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=5992, 
  XED_IFORM_VRCPPS_XMMdq_MEMdq=5993, 
  XED_IFORM_VRCPPS_XMMdq_XMMdq=5994, 
  XED_IFORM_VRCPPS_YMMqq_MEMqq=5995, 
  XED_IFORM_VRCPPS_YMMqq_YMMqq=5996, 
  XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd=5997, 
  XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd=5998, 
  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=5999, 
  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6000, 
  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6001, 
  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6002, 
  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6003, 
  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6004, 
  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6005, 
  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6006, 
  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6007, 
  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6008, 
  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6009, 
  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6010, 
  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6011, 
  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6012, 
  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6013, 
  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6014, 
  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6015, 
  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6016, 
  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6017, 
  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6018, 
  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6019, 
  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6020, 
  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6021, 
  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6022, 
  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6023, 
  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6024, 
  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6025, 
  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6026, 
  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6027, 
  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6028, 
  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6029, 
  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6030, 
  XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb=6031, 
  XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb=6032, 
  XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb=6033, 
  XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb=6034, 
  XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb=6035, 
  XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb=6036, 
  XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb=6037, 
  XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb=6038, 
  XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb=6039, 
  XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb=6040, 
  XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb=6041, 
  XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb=6042, 
  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512=6043, 
  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512=6044, 
  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512=6045, 
  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512=6046, 
  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6047, 
  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6048, 
  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512=6049, 
  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512=6050, 
  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512=6051, 
  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512=6052, 
  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6053, 
  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6054, 
  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6055, 
  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6056, 
  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6057, 
  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6058, 
  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6059, 
  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6060, 
  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6061, 
  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6062, 
  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6063, 
  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6064, 
  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6065, 
  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6066, 
  XED_IFORM_VRSQRTPS_XMMdq_MEMdq=6067, 
  XED_IFORM_VRSQRTPS_XMMdq_XMMdq=6068, 
  XED_IFORM_VRSQRTPS_YMMqq_MEMqq=6069, 
  XED_IFORM_VRSQRTPS_YMMqq_YMMqq=6070, 
  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd=6071, 
  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd=6072, 
  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6073, 
  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6074, 
  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6075, 
  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6076, 
  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6077, 
  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6078, 
  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6079, 
  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6080, 
  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6081, 
  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6082, 
  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6083, 
  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6084, 
  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6085, 
  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6086, 
  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6087, 
  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6088, 
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6089, 
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6090, 
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6091, 
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6092, 
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256=6093, 
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512=6094, 
  XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=6095, 
  XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=6096, 
  XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=6097, 
  XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=6098, 
  XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=6099, 
  XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=6100, 
  XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=6101, 
  XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=6102, 
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6103, 
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6104, 
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6105, 
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6106, 
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256=6107, 
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512=6108, 
  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6109, 
  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6110, 
  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6111, 
  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6112, 
  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6113, 
  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6114, 
  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6115, 
  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6116, 
  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6117, 
  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6118, 
  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6119, 
  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6120, 
  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6121, 
  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6122, 
  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6123, 
  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6124, 
  XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb=6125, 
  XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb=6126, 
  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6127, 
  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6128, 
  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6129, 
  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6130, 
  XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb=6131, 
  XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb=6132, 
  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6133, 
  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6134, 
  XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb=6135, 
  XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb=6136, 
  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6137, 
  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6138, 
  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6139, 
  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6140, 
  XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb=6141, 
  XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb=6142, 
  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6143, 
  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6144, 
  XED_IFORM_VSQRTPD_XMMdq_MEMdq=6145, 
  XED_IFORM_VSQRTPD_XMMdq_XMMdq=6146, 
  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512=6147, 
  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512=6148, 
  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512=6149, 
  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512=6150, 
  XED_IFORM_VSQRTPD_YMMqq_MEMqq=6151, 
  XED_IFORM_VSQRTPD_YMMqq_YMMqq=6152, 
  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512=6153, 
  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512=6154, 
  XED_IFORM_VSQRTPS_XMMdq_MEMdq=6155, 
  XED_IFORM_VSQRTPS_XMMdq_XMMdq=6156, 
  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512=6157, 
  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512=6158, 
  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512=6159, 
  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512=6160, 
  XED_IFORM_VSQRTPS_YMMqq_MEMqq=6161, 
  XED_IFORM_VSQRTPS_YMMqq_YMMqq=6162, 
  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512=6163, 
  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512=6164, 
  XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq=6165, 
  XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq=6166, 
  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6167, 
  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6168, 
  XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd=6169, 
  XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd=6170, 
  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6171, 
  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6172, 
  XED_IFORM_VSTMXCSR_MEMd=6173, 
  XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq=6174, 
  XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq=6175, 
  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6176, 
  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6177, 
  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6178, 
  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6179, 
  XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq=6180, 
  XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq=6181, 
  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6182, 
  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6183, 
  XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq=6184, 
  XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq=6185, 
  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6186, 
  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6187, 
  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6188, 
  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6189, 
  XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq=6190, 
  XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq=6191, 
  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6192, 
  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6193, 
  XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq=6194, 
  XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq=6195, 
  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6196, 
  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6197, 
  XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd=6198, 
  XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd=6199, 
  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6200, 
  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6201, 
  XED_IFORM_VTESTPD_XMMdq_MEMdq=6202, 
  XED_IFORM_VTESTPD_XMMdq_XMMdq=6203, 
  XED_IFORM_VTESTPD_YMMqq_MEMqq=6204, 
  XED_IFORM_VTESTPD_YMMqq_YMMqq=6205, 
  XED_IFORM_VTESTPS_XMMdq_MEMdq=6206, 
  XED_IFORM_VTESTPS_XMMdq_XMMdq=6207, 
  XED_IFORM_VTESTPS_YMMqq_MEMqq=6208, 
  XED_IFORM_VTESTPS_YMMqq_YMMqq=6209, 
  XED_IFORM_VUCOMISD_XMMdq_MEMq=6210, 
  XED_IFORM_VUCOMISD_XMMdq_XMMq=6211, 
  XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512=6212, 
  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512=6213, 
  XED_IFORM_VUCOMISS_XMMdq_MEMd=6214, 
  XED_IFORM_VUCOMISS_XMMdq_XMMd=6215, 
  XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512=6216, 
  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512=6217, 
  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq=6218, 
  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq=6219, 
  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6220, 
  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6221, 
  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6222, 
  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6223, 
  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq=6224, 
  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq=6225, 
  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6226, 
  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6227, 
  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq=6228, 
  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq=6229, 
  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6230, 
  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6231, 
  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6232, 
  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6233, 
  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq=6234, 
  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq=6235, 
  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6236, 
  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6237, 
  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq=6238, 
  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq=6239, 
  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6240, 
  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6241, 
  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6242, 
  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6243, 
  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq=6244, 
  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq=6245, 
  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6246, 
  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6247, 
  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq=6248, 
  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq=6249, 
  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6250, 
  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6251, 
  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6252, 
  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6253, 
  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq=6254, 
  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq=6255, 
  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6256, 
  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6257, 
  XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq=6258, 
  XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq=6259, 
  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6260, 
  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6261, 
  XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq=6262, 
  XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq=6263, 
  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6264, 
  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6265, 
  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6266, 
  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6267, 
  XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq=6268, 
  XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq=6269, 
  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6270, 
  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6271, 
  XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq=6272, 
  XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq=6273, 
  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6274, 
  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6275, 
  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6276, 
  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6277, 
  XED_IFORM_VZEROALL=6278, 
  XED_IFORM_VZEROUPPER=6279, 
  XED_IFORM_WBINVD=6280, 
  XED_IFORM_WBNOINVD=6281, 
  XED_IFORM_WRFSBASE_GPRy=6282, 
  XED_IFORM_WRGSBASE_GPRy=6283, 
  XED_IFORM_WRMSR=6284, 
  XED_IFORM_WRPKRU=6285, 
  XED_IFORM_WRSSD_MEMu32_GPR32u32=6286, 
  XED_IFORM_WRSSQ_MEMu64_GPR64u64=6287, 
  XED_IFORM_WRUSSD_MEMu32_GPR32u32=6288, 
  XED_IFORM_WRUSSQ_MEMu64_GPR64u64=6289, 
  XED_IFORM_XABORT_IMMb=6290, 
  XED_IFORM_XADD_GPR8_GPR8=6291, 
  XED_IFORM_XADD_GPRv_GPRv=6292, 
  XED_IFORM_XADD_MEMb_GPR8=6293, 
  XED_IFORM_XADD_MEMv_GPRv=6294, 
  XED_IFORM_XADD_LOCK_MEMb_GPR8=6295, 
  XED_IFORM_XADD_LOCK_MEMv_GPRv=6296, 
  XED_IFORM_XBEGIN_RELBRz=6297, 
  XED_IFORM_XCHG_GPR8_GPR8=6298, 
  XED_IFORM_XCHG_GPRv_GPRv=6299, 
  XED_IFORM_XCHG_GPRv_OrAX=6300, 
  XED_IFORM_XCHG_MEMb_GPR8=6301, 
  XED_IFORM_XCHG_MEMv_GPRv=6302, 
  XED_IFORM_XEND=6303, 
  XED_IFORM_XGETBV=6304, 
  XED_IFORM_XLAT=6305, 
  XED_IFORM_XOR_AL_IMMb=6306, 
  XED_IFORM_XOR_GPR8_GPR8_30=6307, 
  XED_IFORM_XOR_GPR8_GPR8_32=6308, 
  XED_IFORM_XOR_GPR8_IMMb_80r6=6309, 
  XED_IFORM_XOR_GPR8_IMMb_82r6=6310, 
  XED_IFORM_XOR_GPR8_MEMb=6311, 
  XED_IFORM_XOR_GPRv_GPRv_31=6312, 
  XED_IFORM_XOR_GPRv_GPRv_33=6313, 
  XED_IFORM_XOR_GPRv_IMMb=6314, 
  XED_IFORM_XOR_GPRv_IMMz=6315, 
  XED_IFORM_XOR_GPRv_MEMv=6316, 
  XED_IFORM_XOR_MEMb_GPR8=6317, 
  XED_IFORM_XOR_MEMb_IMMb_80r6=6318, 
  XED_IFORM_XOR_MEMb_IMMb_82r6=6319, 
  XED_IFORM_XOR_MEMv_GPRv=6320, 
  XED_IFORM_XOR_MEMv_IMMb=6321, 
  XED_IFORM_XOR_MEMv_IMMz=6322, 
  XED_IFORM_XOR_OrAX_IMMz=6323, 
  XED_IFORM_XORPD_XMMxuq_MEMxuq=6324, 
  XED_IFORM_XORPD_XMMxuq_XMMxuq=6325, 
  XED_IFORM_XORPS_XMMxud_MEMxud=6326, 
  XED_IFORM_XORPS_XMMxud_XMMxud=6327, 
  XED_IFORM_XOR_LOCK_MEMb_GPR8=6328, 
  XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6=6329, 
  XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6=6330, 
  XED_IFORM_XOR_LOCK_MEMv_GPRv=6331, 
  XED_IFORM_XOR_LOCK_MEMv_IMMb=6332, 
  XED_IFORM_XOR_LOCK_MEMv_IMMz=6333, 
  XED_IFORM_XRESLDTRK=6334, 
  XED_IFORM_XRSTOR_MEMmxsave=6335, 
  XED_IFORM_XRSTOR64_MEMmxsave=6336, 
  XED_IFORM_XRSTORS_MEMmxsave=6337, 
  XED_IFORM_XRSTORS64_MEMmxsave=6338, 
  XED_IFORM_XSAVE_MEMmxsave=6339, 
  XED_IFORM_XSAVE64_MEMmxsave=6340, 
  XED_IFORM_XSAVEC_MEMmxsave=6341, 
  XED_IFORM_XSAVEC64_MEMmxsave=6342, 
  XED_IFORM_XSAVEOPT_MEMmxsave=6343, 
  XED_IFORM_XSAVEOPT64_MEMmxsave=6344, 
  XED_IFORM_XSAVES_MEMmxsave=6345, 
  XED_IFORM_XSAVES64_MEMmxsave=6346, 
  XED_IFORM_XSETBV=6347, 
  XED_IFORM_XSTORE=6348, 
  XED_IFORM_XSUSLDTRK=6349, 
  XED_IFORM_XTEST=6350, 
  XED_IFORM_LAST
} xed_iform_enum_t;

/// This converts strings to #xed_iform_enum_t types.
/// @param s A C-string.
/// @return #xed_iform_enum_t
/// @ingroup ENUM
XED_DLL_EXPORT xed_iform_enum_t str2xed_iform_enum_t(const char* s);
/// This converts strings to #xed_iform_enum_t types.
/// @param p An enumeration element of type xed_iform_enum_t.
/// @return string
/// @ingroup ENUM
XED_DLL_EXPORT const char* xed_iform_enum_t2str(const xed_iform_enum_t p);

/// Returns the last element of the enumeration
/// @return xed_iform_enum_t The last element of the enumeration.
/// @ingroup ENUM
XED_DLL_EXPORT xed_iform_enum_t xed_iform_enum_t_last(void);
#endif