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352 lines
10 KiB
352 lines
10 KiB
/*
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* Copyright 2002-2019 Intel Corporation.
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*
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* This software is provided to you as Sample Source Code as defined in the accompanying
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* End User License Agreement for the Intel(R) Software Development Products ("Agreement")
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* section 1.L.
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*
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* This software and the related documents are provided as is, with no express or implied
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* warranties, other than those that are expressly stated in the License.
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*/
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/*! @file
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* This file contains an ISA-portable cache simulator
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* data cache hierarchies
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*/
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#include "pin.H"
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#include <iostream>
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#include <fstream>
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#include <cassert>
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#include "cache.H"
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#include "pin_profile.H"
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using std::cerr;
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using std::endl;
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/* ===================================================================== */
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/* Commandline Switches */
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/* ===================================================================== */
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KNOB<string> KnobOutputFile(KNOB_MODE_WRITEONCE, "pintool",
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"o", "dcache.out", "specify dcache file name");
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KNOB<BOOL> KnobTrackLoads(KNOB_MODE_WRITEONCE, "pintool",
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"tl", "0", "track individual loads -- increases profiling time");
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KNOB<BOOL> KnobTrackStores(KNOB_MODE_WRITEONCE, "pintool",
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"ts", "0", "track individual stores -- increases profiling time");
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KNOB<UINT32> KnobThresholdHit(KNOB_MODE_WRITEONCE , "pintool",
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"rh", "100", "only report memops with hit count above threshold");
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KNOB<UINT32> KnobThresholdMiss(KNOB_MODE_WRITEONCE, "pintool",
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"rm","100", "only report memops with miss count above threshold");
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KNOB<UINT32> KnobCacheSize(KNOB_MODE_WRITEONCE, "pintool",
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"c","32", "cache size in kilobytes");
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KNOB<UINT32> KnobLineSize(KNOB_MODE_WRITEONCE, "pintool",
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"b","32", "cache block size in bytes");
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KNOB<UINT32> KnobAssociativity(KNOB_MODE_WRITEONCE, "pintool",
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"a","4", "cache associativity (1 for direct mapped)");
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/* ===================================================================== */
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INT32 Usage()
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{
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cerr <<
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"This tool represents a cache simulator.\n"
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"\n";
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cerr << KNOB_BASE::StringKnobSummary();
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cerr << endl;
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return -1;
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}
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/* ===================================================================== */
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/* Global Variables */
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/* ===================================================================== */
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// wrap configuation constants into their own name space to avoid name clashes
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namespace DL1
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{
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const UINT32 max_sets = KILO; // cacheSize / (lineSize * associativity);
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const UINT32 max_associativity = 256; // associativity;
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const CACHE_ALLOC::STORE_ALLOCATION allocation = CACHE_ALLOC::STORE_ALLOCATE;
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typedef CACHE_ROUND_ROBIN(max_sets, max_associativity, allocation) CACHE;
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}
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DL1::CACHE* dl1 = NULL;
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typedef enum
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{
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COUNTER_MISS = 0,
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COUNTER_HIT = 1,
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COUNTER_NUM
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} COUNTER;
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typedef COUNTER_ARRAY<UINT64, COUNTER_NUM> COUNTER_HIT_MISS;
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// holds the counters with misses and hits
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// conceptually this is an array indexed by instruction address
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COMPRESSOR_COUNTER<ADDRINT, UINT32, COUNTER_HIT_MISS> profile;
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/* ===================================================================== */
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VOID LoadMulti(ADDRINT addr, UINT32 size, UINT32 instId)
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{
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// first level D-cache
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const BOOL dl1Hit = dl1->Access(addr, size, CACHE_BASE::ACCESS_TYPE_LOAD);
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const COUNTER counter = dl1Hit ? COUNTER_HIT : COUNTER_MISS;
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profile[instId][counter]++;
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}
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/* ===================================================================== */
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VOID StoreMulti(ADDRINT addr, UINT32 size, UINT32 instId)
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{
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// first level D-cache
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const BOOL dl1Hit = dl1->Access(addr, size, CACHE_BASE::ACCESS_TYPE_STORE);
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const COUNTER counter = dl1Hit ? COUNTER_HIT : COUNTER_MISS;
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profile[instId][counter]++;
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}
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/* ===================================================================== */
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VOID LoadSingle(ADDRINT addr, UINT32 instId)
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{
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// @todo we may access several cache lines for
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// first level D-cache
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const BOOL dl1Hit = dl1->AccessSingleLine(addr, CACHE_BASE::ACCESS_TYPE_LOAD);
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const COUNTER counter = dl1Hit ? COUNTER_HIT : COUNTER_MISS;
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profile[instId][counter]++;
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}
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/* ===================================================================== */
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VOID StoreSingle(ADDRINT addr, UINT32 instId)
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{
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// @todo we may access several cache lines for
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// first level D-cache
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const BOOL dl1Hit = dl1->AccessSingleLine(addr, CACHE_BASE::ACCESS_TYPE_STORE);
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const COUNTER counter = dl1Hit ? COUNTER_HIT : COUNTER_MISS;
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profile[instId][counter]++;
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}
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/* ===================================================================== */
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VOID LoadMultiFast(ADDRINT addr, UINT32 size)
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{
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dl1->Access(addr, size, CACHE_BASE::ACCESS_TYPE_LOAD);
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}
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/* ===================================================================== */
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VOID StoreMultiFast(ADDRINT addr, UINT32 size)
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{
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dl1->Access(addr, size, CACHE_BASE::ACCESS_TYPE_STORE);
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}
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/* ===================================================================== */
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VOID LoadSingleFast(ADDRINT addr)
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{
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dl1->AccessSingleLine(addr, CACHE_BASE::ACCESS_TYPE_LOAD);
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}
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/* ===================================================================== */
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VOID StoreSingleFast(ADDRINT addr)
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{
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dl1->AccessSingleLine(addr, CACHE_BASE::ACCESS_TYPE_STORE);
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}
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/* ===================================================================== */
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VOID Instruction(INS ins, void * v)
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{
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UINT32 memOperands = INS_MemoryOperandCount(ins);
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// Instrument each memory operand. If the operand is both read and written
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// it will be processed twice.
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// Iterating over memory operands ensures that instructions on IA-32 with
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// two read operands (such as SCAS and CMPS) are correctly handled.
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for (UINT32 memOp = 0; memOp < memOperands; memOp++)
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{
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const UINT32 size = INS_MemoryOperandSize(ins, memOp);
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const BOOL single = (size <= 4);
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if (INS_MemoryOperandIsRead(ins, memOp))
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{
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if( KnobTrackLoads )
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{
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// map sparse INS addresses to dense IDs
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const ADDRINT iaddr = INS_Address(ins);
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const UINT32 instId = profile.Map(iaddr);
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if( single )
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) LoadSingle,
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IARG_MEMORYOP_EA, memOp,
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IARG_UINT32, instId,
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IARG_END);
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}
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else
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) LoadMulti,
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IARG_MEMORYOP_EA, memOp,
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IARG_UINT32, size,
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IARG_UINT32, instId,
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IARG_END);
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}
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}
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else
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{
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if( single )
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) LoadSingleFast,
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IARG_MEMORYOP_EA, memOp,
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IARG_END);
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}
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else
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) LoadMultiFast,
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IARG_MEMORYOP_EA, memOp,
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IARG_UINT32, size,
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IARG_END);
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}
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}
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}
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if (INS_MemoryOperandIsWritten(ins, memOp))
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{
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if( KnobTrackStores )
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{
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const ADDRINT iaddr = INS_Address(ins);
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const UINT32 instId = profile.Map(iaddr);
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if( single )
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) StoreSingle,
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IARG_MEMORYOP_EA, memOp,
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IARG_UINT32, instId,
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IARG_END);
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}
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else
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) StoreMulti,
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IARG_MEMORYOP_EA,memOp,
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IARG_UINT32, size,
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IARG_UINT32, instId,
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IARG_END);
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}
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}
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else
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{
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if( single )
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) StoreSingleFast,
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IARG_MEMORYOP_EA, memOp,
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IARG_END);
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}
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else
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{
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, (AFUNPTR) StoreMultiFast,
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IARG_MEMORYOP_EA, memOp,
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IARG_UINT32, size,
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IARG_END);
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}
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}
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}
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}
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}
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/* ===================================================================== */
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VOID Fini(int code, VOID * v)
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{
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std::ofstream out(KnobOutputFile.Value().c_str());
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// print D-cache profile
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// @todo what does this print
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out << "PIN:MEMLATENCIES 1.0. 0x0\n";
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out <<
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"#\n"
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"# DCACHE stats\n"
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"#\n";
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out << dl1->StatsLong("# ", CACHE_BASE::CACHE_TYPE_DCACHE);
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if( KnobTrackLoads || KnobTrackStores ) {
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out <<
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"#\n"
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"# LOAD stats\n"
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"#\n";
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out << profile.StringLong();
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}
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out.close();
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}
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/* ===================================================================== */
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int main(int argc, char *argv[])
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{
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PIN_InitSymbols();
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if( PIN_Init(argc,argv) )
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{
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return Usage();
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}
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dl1 = new DL1::CACHE("L1 Data Cache",
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KnobCacheSize.Value() * KILO,
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KnobLineSize.Value(),
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KnobAssociativity.Value());
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profile.SetKeyName("iaddr ");
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profile.SetCounterName("dcache:miss dcache:hit");
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COUNTER_HIT_MISS threshold;
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threshold[COUNTER_HIT] = KnobThresholdHit.Value();
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threshold[COUNTER_MISS] = KnobThresholdMiss.Value();
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profile.SetThreshold( threshold );
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INS_AddInstrumentFunction(Instruction, 0);
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PIN_AddFiniFunction(Fini, 0);
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// Never returns
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PIN_StartProgram();
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return 0;
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}
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/* ===================================================================== */
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/* eof */
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/* ===================================================================== */
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