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123 lines
3.5 KiB
123 lines
3.5 KiB
/*
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* Copyright 2002-2019 Intel Corporation.
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*
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* This software is provided to you as Sample Source Code as defined in the accompanying
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* End User License Agreement for the Intel(R) Software Development Products ("Agreement")
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* section 1.L.
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*
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* This software and the related documents are provided as is, with no express or implied
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* warranties, other than those that are expressly stated in the License.
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*/
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/*! @file
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* This file contains an ISA-portable PIN tool for functional simulation of
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* the Intel XScale(R) processor L1 data cache
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*/
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#include <iostream>
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#include "pin.H"
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typedef UINT64 CACHE_STATS; // type of cache hit/miss counters
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#include "pin_cache.H"
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KNOB<UINT32> KnobCacheSize(KNOB_MODE_WRITEONCE, "pintool",
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"-s1", "32768", "l1 cache size in bytes");
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KNOB<UINT32> KnobCacheAssociativity(KNOB_MODE_WRITEONCE, "pintool",
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"-a1", "32", "l1 cache associativity");
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KNOB<UINT32> KnobCacheLineSize(KNOB_MODE_WRITEONCE, "pintool",
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"-l1", "32", "l1 cache size in bytes");
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namespace DL1
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{
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const CACHE_ALLOC::STORE_ALLOCATION allocation = CACHE_ALLOC::STORE_NO_ALLOCATE;
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const UINT32 max_sets = 128;
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const UINT32 max_associativity = 32;
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typedef CACHE_ROUND_ROBIN(max_sets, max_associativity, allocation) CACHE;
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}
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LOCALVAR DL1::CACHE *dl1;
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LOCALFUN VOID Fini(int code, VOID * v)
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{
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std::cerr << *dl1;
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}
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LOCALFUN VOID MemRefSingle(CACHE_BASE::ACCESS_TYPE accessType, ADDRINT addr)
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{
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// first level D-cache: single cache-line access
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dl1->AccessSingleLine(addr, accessType);
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}
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LOCALFUN VOID MemRefMulti(CACHE_BASE::ACCESS_TYPE accessType, ADDRINT addr, UINT32 size)
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{
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// first level D-cache: potentially multiple cache-line access
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dl1->Access(addr, size, accessType);
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}
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LOCALFUN VOID Instruction(INS ins, void * v)
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{
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if (INS_IsMemoryRead(ins) && INS_IsStandardMemop(ins))
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{
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const UINT32 size = INS_MemoryReadSize(ins);
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// we assume accesses <= 4 bytes stay in the same cache line
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// to speed up cache access lookups
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const AFUNPTR countFun = (size <= 4 ? (AFUNPTR) MemRefSingle : (AFUNPTR) MemRefMulti);
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// only predicated-on memory instructions access D-cache
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, countFun,
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IARG_UINT32, CACHE_BASE::ACCESS_TYPE_LOAD,
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IARG_MEMORYREAD_EA,
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IARG_MEMORYREAD_SIZE,
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IARG_END);
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}
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if (INS_IsMemoryWrite(ins) && INS_IsStandardMemop(ins))
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{
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const UINT32 size = INS_MemoryWriteSize(ins);
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const AFUNPTR countFun = (size <= 4 ? (AFUNPTR) MemRefSingle : (AFUNPTR) MemRefMulti);
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// only predicated-on memory instructions access D-cache
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INS_InsertPredicatedCall(
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ins, IPOINT_BEFORE, countFun,
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IARG_UINT32, CACHE_BASE::ACCESS_TYPE_STORE,
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IARG_MEMORYWRITE_EA,
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IARG_MEMORYWRITE_SIZE,
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IARG_END);
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}
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}
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GLOBALFUN int main(int argc, char *argv[])
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{
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PIN_Init(argc, argv);
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INS_AddInstrumentFunction(Instruction, 0);
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PIN_AddFiniFunction(Fini, 0);
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const UINT32 size = KnobCacheSize.Value();
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const UINT32 linesize = KnobCacheLineSize.Value();
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const UINT32 associativity = KnobCacheAssociativity.Value();
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ASSERTX( associativity <= DL1::max_associativity );
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ASSERTX( size /(associativity*linesize )<= DL1::max_sets );
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// create the cache object
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dl1 = new DL1::CACHE("L1 Data Cache", size, linesize, associativity);
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// Never returns
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PIN_StartProgram();
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return 0; // make compiler happy
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}
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