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199 lines
4.8 KiB
199 lines
4.8 KiB
/*
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* Copyright 2002-2019 Intel Corporation.
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*
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* This software is provided to you as Sample Source Code as defined in the accompanying
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* End User License Agreement for the Intel(R) Software Development Products ("Agreement")
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* section 1.L.
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*
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* This software and the related documents are provided as is, with no express or implied
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* warranties, other than those that are expressly stated in the License.
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*/
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#include <iostream>
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#include <fstream>
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#include <stdlib.h>
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#include "pin.H"
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using std::ofstream;
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using std::hex;
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using std::endl;
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ofstream out("reg.out");
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UINT64 icount = 0;
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VOID docount(VOID * ip, VOID * reg)
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{
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icount++;
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if ((icount % 1000) == 1)
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out << "ip:" << ip << " count:" << icount << " SP:" << reg << endl;
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}
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VOID Instruction(INS ins, VOID *v)
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{
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INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)docount,
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IARG_INST_PTR, IARG_REG_VALUE, REG_STACK_PTR, IARG_END);
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}
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VOID PrintError(ADDRINT ip, ADDRINT al, ADDRINT ah, ADDRINT ax, ADDRINT eax, ADDRINT rax)
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{
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std::cerr << hex << "ip " << ip
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<< " al " << al
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<< " ah " << ah
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<< " ax " << ax
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<< " eax " << eax
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<< " rax " << rax
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<< endl;
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exit(1);
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}
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VOID CheckRegs(ADDRINT ip, ADDRINT al, ADDRINT ah, ADDRINT ax, ADDRINT eax, ADDRINT rax)
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{
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if ((eax & 0xff) != al)
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{
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PrintError(ip, al, ah, ax, eax, rax);
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}
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if (((eax & 0xff00) >> 8) != ah)
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{
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PrintError(ip, al, ah, ax, eax, rax);
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}
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if ((eax & 0xffff) != ax)
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{
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PrintError(ip, al, ah, ax, eax, rax);
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}
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#if defined(TARGET_IA32E)
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if((rax & 0xffffffff) != eax)
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{
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PrintError(ip, al, ah, ax, eax, rax);
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}
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#endif
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}
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VOID CheckArRegs(ADDRINT rsc,
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ADDRINT bsp,
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ADDRINT bspstore,
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ADDRINT rnat,
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ADDRINT fcr,
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ADDRINT eflag,
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ADDRINT csd,
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ADDRINT ssd,
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ADDRINT cflg,
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ADDRINT fsr,
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ADDRINT fir,
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ADDRINT fdr,
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ADDRINT ccv,
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ADDRINT unat,
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ADDRINT fpsr,
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ADDRINT itc,
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ADDRINT pfs,
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ADDRINT lc,
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ADDRINT ec)
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{}
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VOID CheckNat(ADDRINT nat)
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{}
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ADDRINT capturedVal;
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ADDRINT capturedConstVal;
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// Make it inlineable
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VOID CaptureRef(ADDRINT *ref, ADDRINT *constRef)
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{
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capturedVal = *ref;
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capturedConstVal = *constRef;
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}
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VOID CheckRef(char const * name, ADDRINT val, ADDRINT *ref, ADDRINT const *constRef)
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{
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if (val != capturedVal
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|| val != *ref
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|| val != capturedConstVal
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|| val != *constRef
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)
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{
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std::cerr << hex << name << " val: " << val << " ref: " << *ref << " constRef: " << *constRef << endl;
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exit(1);
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}
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}
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VOID InsertCheckRef(TRACE trace, char const * name, REG reg)
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{
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// This is inlineable
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TRACE_InsertCall(trace, IPOINT_BEFORE, AFUNPTR(CaptureRef),
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IARG_REG_REFERENCE, reg,
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IARG_REG_CONST_REFERENCE, reg,
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IARG_END);
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// This is NOT inlineable
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TRACE_InsertCall(trace, IPOINT_BEFORE, AFUNPTR(CheckRef),
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IARG_PTR, name,
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IARG_REG_VALUE, reg,
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IARG_REG_REFERENCE, reg,
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IARG_REG_CONST_REFERENCE, reg,
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IARG_END);
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}
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VOID Trace(TRACE trace, VOID *v)
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{
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static BOOL first = TRUE;
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#if defined(TARGET_IA32) || defined(TARGET_IA32E)
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if (first)
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{
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InsertCheckRef(trace, "gax", REG_GAX);
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InsertCheckRef(trace, "stack", REG_STACK_PTR);
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}
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TRACE_InsertCall(trace, IPOINT_BEFORE, AFUNPTR(CheckRegs),
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IARG_INST_PTR,
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IARG_REG_VALUE, REG_AL,
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IARG_REG_VALUE, REG_AH,
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IARG_REG_VALUE, REG_AX,
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IARG_REG_VALUE, REG_EAX,
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#if defined(TARGET_IA32E)
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IARG_REG_VALUE, REG_RAX,
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#endif
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IARG_END
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);
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INS ins = BBL_InsHead(TRACE_BblHead(trace));
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static INT32 origCount = 0;
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if (INS_IsOriginal(ins))
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{
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origCount++;
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}
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static INT32 immcount = 10;
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if (immcount > 0)
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{
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for (UINT32 op = 0; op < INS_OperandCount(ins); op++)
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{
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if (INS_OperandIsImmediate(ins, op))
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{
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std::cerr << "Immediate: " << hex << INS_OperandImmediate(ins, op) << " ins " << INS_Disassemble(ins) << endl;
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immcount--;
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}
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}
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}
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#endif
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first = FALSE;
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}
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int main(INT32 argc, CHAR **argv)
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{
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PIN_Init(argc, argv);
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INS_AddInstrumentFunction(Instruction, 0);
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TRACE_AddInstrumentFunction(Trace, 0);
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// Never returns
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PIN_StartProgram();
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return 0;
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}
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