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450 lines
11 KiB
450 lines
11 KiB
/*
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* Copyright 2002-2019 Intel Corporation.
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*
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* This software is provided to you as Sample Source Code as defined in the accompanying
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* End User License Agreement for the Intel(R) Software Development Products ("Agreement")
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* section 1.L.
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*
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* This software and the related documents are provided as is, with no express or implied
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* warranties, other than those that are expressly stated in the License.
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*/
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#include <iostream>
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#include <iomanip>
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#include <cstdlib> // for atoi w/gcc4.3.x
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using std::cout;
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#define N 1024
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int main(int argc, char** argv);
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#if defined(_MSC_VER)
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typedef unsigned __int8 UINT8 ;
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typedef unsigned __int16 UINT16;
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typedef unsigned __int32 UINT32;
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typedef unsigned __int64 UINT64;
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typedef __int8 INT8;
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typedef __int16 INT16;
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typedef __int32 INT32;
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typedef __int64 INT64;
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#define ALIGN16 __declspec(align(16))
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#define ALIGN8 __declspec(align(8))
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#else
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#include <stdint.h>
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typedef uint8_t UINT8;
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typedef uint16_t UINT16;
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typedef uint32_t UINT32;
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typedef uint32_t UINT;
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typedef uint64_t UINT64;
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typedef int8_t INT8;
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typedef int16_t INT16;
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typedef int32_t INT32;
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typedef int64_t INT64;
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#define ALIGN16 __attribute__ ((aligned(16)))
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#define ALIGN8 __attribute__ ((aligned(8)))
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#endif
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#define MAX_XMM_REGS 16
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#define MAX_BYTES_PER_XMM_REG 16
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#define MAX_WORDS_PER_XMM_REG (MAX_BYTES_PER_XMM_REG/2)
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#define MAX_DWORDS_PER_XMM_REG (MAX_WORDS_PER_XMM_REG/2)
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#define MAX_QWORDS_PER_XMM_REG (MAX_DWORDS_PER_XMM_REG/2)
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#define MAX_FLOATS_PER_XMM_REG (MAX_BYTES_PER_XMM_REG/sizeof(float))
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#define MAX_DOUBLES_PER_XMM_REG (MAX_BYTES_PER_XMM_REG/sizeof(double))
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union ALIGN16 xmm_reg_t
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{
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UINT8 byte[MAX_BYTES_PER_XMM_REG];
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UINT16 word[MAX_WORDS_PER_XMM_REG];
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UINT32 dword[MAX_DWORDS_PER_XMM_REG];
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UINT64 qword[MAX_QWORDS_PER_XMM_REG];
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INT8 s_byte[MAX_BYTES_PER_XMM_REG];
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INT16 s_word[MAX_WORDS_PER_XMM_REG];
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INT32 s_dword[MAX_DWORDS_PER_XMM_REG];
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INT64 s_qword[MAX_QWORDS_PER_XMM_REG];
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float flt[MAX_FLOATS_PER_XMM_REG];
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double dbl[MAX_DOUBLES_PER_XMM_REG];
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} /*__attribute__ ((aligned(16)))*/;
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#if defined(_MSC_VER)
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extern "C" void set_xmm_reg0(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg0(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg1(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg1(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg2(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg2(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg3(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg3(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg4(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg4(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg5(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg5(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg6(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg6(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg7(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg7(xmm_reg_t& xmm_reg);
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#ifdef TARGET_IA32E
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extern "C" void set_xmm_reg8(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg8(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg9(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg9(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg10(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg10(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg11(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg11(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg12(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg12(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg13(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg13(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg14(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg14(xmm_reg_t& xmm_reg);
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extern "C" void set_xmm_reg15(xmm_reg_t& xmm_reg);
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extern "C" void get_xmm_reg15(xmm_reg_t& xmm_reg);
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#endif
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extern "C" void mmx_save(char* buf);
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extern "C" void mmx_restore(char* buf);
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#else
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static void set_xmm_reg0(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm0" : : "m" (xmm_reg) : "%xmm0" );
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}
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static void get_xmm_reg0(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm0,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg1(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm1" : : "m" (xmm_reg) : "%xmm1" );
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}
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static void get_xmm_reg1(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm1,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg2(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm2" : : "m" (xmm_reg) : "%xmm2" );
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}
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static void get_xmm_reg2(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm2,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg3(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm3" : : "m" (xmm_reg) : "%xmm3" );
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}
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static void get_xmm_reg3(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm3,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg4(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm4" : : "m" (xmm_reg) : "%xmm4" );
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}
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static void get_xmm_reg4(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm4,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg5(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm5" : : "m" (xmm_reg) : "%xmm5" );
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}
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static void get_xmm_reg5(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm5,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg6(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm6" : : "m" (xmm_reg) : "%xmm6" );
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}
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static void get_xmm_reg6(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm6,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg7(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm7" : : "m" (xmm_reg) : "%xmm7" );
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}
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static void get_xmm_reg7(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm7,%0" : "=m" (xmm_reg) );
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}
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#ifdef TARGET_IA32E
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static void set_xmm_reg8(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm8" : : "m" (xmm_reg) : "%xmm8" );
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}
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static void get_xmm_reg8(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm8,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg9(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm9" : : "m" (xmm_reg) : "%xmm9" );
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}
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static void get_xmm_reg9(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm9,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg10(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm10" : : "m" (xmm_reg) : "%xmm10" );
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}
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static void get_xmm_reg10(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm10,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg11(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm11" : : "m" (xmm_reg) : "%xmm11" );
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}
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static void get_xmm_reg11(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm11,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg12(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm12" : : "m" (xmm_reg) : "%xmm12" );
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}
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static void get_xmm_reg12(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm12,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg13(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm13" : : "m" (xmm_reg) : "%xmm13" );
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}
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static void get_xmm_reg13(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm13,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg14(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm14" : : "m" (xmm_reg) : "%xmm14" );
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}
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static void get_xmm_reg14(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm14,%0" : "=m" (xmm_reg) );
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}
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static void set_xmm_reg15(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %0, %%xmm15" : : "m" (xmm_reg) : "%xmm15" );
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}
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static void get_xmm_reg15(xmm_reg_t& xmm_reg)
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{
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asm volatile("movdqu %%xmm15,%0" : "=m" (xmm_reg) );
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}
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#endif
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#endif
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static void
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set_xmm_reg(xmm_reg_t& xmm_reg, UINT32 reg_no)
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{
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switch (reg_no)
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{
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case 0:
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set_xmm_reg0(xmm_reg);
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break;
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case 1:
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set_xmm_reg1(xmm_reg);
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break;
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case 2:
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set_xmm_reg2(xmm_reg);
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break;
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case 3:
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set_xmm_reg3(xmm_reg);
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break;
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case 4:
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set_xmm_reg4(xmm_reg);
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break;
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case 5:
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set_xmm_reg5(xmm_reg);
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break;
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case 6:
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set_xmm_reg6(xmm_reg);
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break;
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case 7:
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set_xmm_reg7(xmm_reg);
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break;
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#ifdef TARGET_IA32E
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case 8:
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set_xmm_reg8(xmm_reg);
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break;
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case 9:
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set_xmm_reg9(xmm_reg);
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break;
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case 10:
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set_xmm_reg10(xmm_reg);
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break;
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case 11:
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set_xmm_reg11(xmm_reg);
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break;
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case 12:
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set_xmm_reg12(xmm_reg);
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break;
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case 13:
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set_xmm_reg13(xmm_reg);
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break;
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case 14:
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set_xmm_reg14(xmm_reg);
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break;
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case 15:
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set_xmm_reg15(xmm_reg);
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break;
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#endif
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}
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}
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static void
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get_xmm_reg(xmm_reg_t& xmm_reg, UINT32 reg_no)
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{
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switch (reg_no)
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{
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case 0:
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get_xmm_reg0(xmm_reg);
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break;
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case 1:
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get_xmm_reg1(xmm_reg);
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break;
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case 2:
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get_xmm_reg2(xmm_reg);
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break;
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case 3:
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get_xmm_reg3(xmm_reg);
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break;
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case 4:
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get_xmm_reg4(xmm_reg);
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break;
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case 5:
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get_xmm_reg5(xmm_reg);
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break;
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case 6:
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get_xmm_reg6(xmm_reg);
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break;
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case 7:
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get_xmm_reg7(xmm_reg);
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break;
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#ifdef TARGET_IA32E
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case 8:
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get_xmm_reg8(xmm_reg);
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break;
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case 9:
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get_xmm_reg9(xmm_reg);
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break;
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case 10:
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get_xmm_reg10(xmm_reg);
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break;
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case 11:
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get_xmm_reg11(xmm_reg);
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break;
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case 12:
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get_xmm_reg12(xmm_reg);
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break;
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case 13:
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get_xmm_reg13(xmm_reg);
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break;
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case 14:
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get_xmm_reg14(xmm_reg);
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break;
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case 15:
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get_xmm_reg15(xmm_reg);
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break;
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#endif
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}
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}
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UINT32 init_sse(UINT32 z, UINT32 reg_no)
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{
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xmm_reg_t xmm;
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xmm.dword[0] = z;
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xmm.dword[1] = z;
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xmm.dword[2] = z;
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xmm.dword[3] = z;
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set_xmm_reg(xmm, reg_no); // from memory to register -- we modify the output using the tool
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get_xmm_reg(xmm, reg_no); // from register to memory
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return xmm.dword[0];
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}
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UINT32 read_sse(UINT32 reg_no)
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{
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xmm_reg_t xmm;
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xmm.dword[0] = 0;
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xmm.dword[1] = 0;
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xmm.dword[2] = 0;
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xmm.dword[3] = 0;
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get_xmm_reg(xmm, reg_no); // from register to memory
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return xmm.dword[0];
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}
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#ifdef TARGET_IA32E
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#define NUM_XMM_REGS 16
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#ifdef TARGET_WINDOWS
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#define NUM_INT_SCRATCHES 7
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#else
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#define NUM_INT_SCRATCHES 9
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#endif
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extern "C" unsigned long long scratchVals[];
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unsigned long long scratchVals[NUM_INT_SCRATCHES];
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#else
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#define NUM_XMM_REGS 8
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#define NUM_INT_SCRATCHES 3
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extern "C" unsigned int scratchVals[];
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unsigned int scratchVals[NUM_INT_SCRATCHES];
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#endif
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extern "C" void SetIntegerScratchesTo1();
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extern "C" void GetIntegerScratches();
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int main(int argc, char** argv)
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{
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SetIntegerScratchesTo1();
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GetIntegerScratches();
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for (UINT32 i=0; i<NUM_INT_SCRATCHES; i++)
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{
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if (scratchVals[i]!=1)
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{
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cout << "ERROR integer scratch regs do not have expected value\n";
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exit (-1);
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}
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}
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UINT32 valsToSet[NUM_XMM_REGS];
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for (UINT32 i=0; i<NUM_XMM_REGS; i++)
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{
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valsToSet[i] = 0xdeadbeef;
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}
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for (UINT32 i=0; i<NUM_XMM_REGS; i++)
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{
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// set xmm reg#i to have the value in the valsToSet
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init_sse(valsToSet[i], i);
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}
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for (UINT32 i=0; i<NUM_XMM_REGS; i++)
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{
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UINT32 x = read_sse(i);
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if ( valsToSet[i]!=x)
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{
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cout << "ERROR xmm regs do not have expected value\n";
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exit (-1);
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}
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}
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return 0;
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}
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