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54 lines
1.5 KiB
54 lines
1.5 KiB
/*
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* Copyright 2002-2019 Intel Corporation.
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*
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* This software is provided to you as Sample Source Code as defined in the accompanying
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* End User License Agreement for the Intel(R) Software Development Products ("Agreement")
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* section 1.L.
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*
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* This software and the related documents are provided as is, with no express or implied
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* warranties, other than those that are expressly stated in the License.
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*/
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#ifdef TARGET_MAC
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.global _SupportsAvx512f
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_SupportsAvx512f:
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#else
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.type SupportsAvx512f, @function
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.global SupportsAvx512f
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SupportsAvx512f:
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#endif
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push %ebp
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mov %esp, %ebp
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push %ebx # CPUID clobbers ebx, which may be used as the PIC register
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push %ecx
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push %edx
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mov $1, %eax
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cpuid
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andl $0x18000000, %ecx
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cmpl $0x18000000, %ecx # check both OSXSAVE and AVX feature flags
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jne NotSupported
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# processor supports AVX instructions and XGETBV is enabled by OS
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mov $0, %ecx # specify 0 for XFEATURE_ENABLED_MASK register
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# 0xd0010f is xgetbv - result in EDX:EAX
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.byte 0xf, 0x1, 0xd0
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andl $0x66, %eax
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cmpl $0x66, %eax # check OS has enabled both XMM, YMM, ZMM and OPMASK state support
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jne NotSupported
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mov $7, %eax
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mov $0, %ecx
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cpuid
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andl $0x10000, %ebx
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cmpl $0x10000, %ebx
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jne NotSupported # no AVX512
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mov $1, %eax
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done:
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pop %edx
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pop %ecx
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pop %ebx
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leave
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ret
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NotSupported:
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mov $0, %eax
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jmp done
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