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chaojiwudi.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000018c 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0000599c 0800018c 0800018c 0001018c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000120 08005b28 08005b28 00015b28 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08005c48 08005c48 0002006c 2**0
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CONTENTS
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4 .ARM 00000008 08005c48 08005c48 00015c48 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08005c50 08005c50 0002006c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08005c50 08005c50 00015c50 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08005c54 08005c54 00015c54 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 0000006c 20000000 08005c58 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000300 2000006c 08005cc4 0002006c 2**2
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ALLOC
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10 ._user_heap_stack 00000604 2000036c 08005cc4 0002036c 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0002006c 2**0
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CONTENTS, READONLY
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12 .comment 00000043 00000000 00000000 0002009c 2**0
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CONTENTS, READONLY
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13 .debug_info 00011bdc 00000000 00000000 000200df 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_abbrev 00002735 00000000 00000000 00031cbb 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_aranges 00001028 00000000 00000000 000343f0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_rnglists 00000c96 00000000 00000000 00035418 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_macro 000226bf 00000000 00000000 000360ae 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_line 00013012 00000000 00000000 0005876d 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .debug_str 000cfd9d 00000000 00000000 0006b77f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .debug_frame 000049d8 00000000 00000000 0013b51c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 0000004f 00000000 00000000 0013fef4 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800018c <__do_global_dtors_aux>:
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800018c: b510 push {r4, lr}
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800018e: 4c05 ldr r4, [pc, #20] ; (80001a4 <__do_global_dtors_aux+0x18>)
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8000190: 7823 ldrb r3, [r4, #0]
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8000192: b933 cbnz r3, 80001a2 <__do_global_dtors_aux+0x16>
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8000194: 4b04 ldr r3, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x1c>)
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8000196: b113 cbz r3, 800019e <__do_global_dtors_aux+0x12>
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8000198: 4804 ldr r0, [pc, #16] ; (80001ac <__do_global_dtors_aux+0x20>)
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800019a: f3af 8000 nop.w
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800019e: 2301 movs r3, #1
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80001a0: 7023 strb r3, [r4, #0]
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80001a2: bd10 pop {r4, pc}
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80001a4: 2000006c .word 0x2000006c
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80001a8: 00000000 .word 0x00000000
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80001ac: 08005b10 .word 0x08005b10
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080001b0 <frame_dummy>:
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80001b0: b508 push {r3, lr}
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80001b2: 4b03 ldr r3, [pc, #12] ; (80001c0 <frame_dummy+0x10>)
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80001b4: b11b cbz r3, 80001be <frame_dummy+0xe>
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80001b6: 4903 ldr r1, [pc, #12] ; (80001c4 <frame_dummy+0x14>)
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80001b8: 4803 ldr r0, [pc, #12] ; (80001c8 <frame_dummy+0x18>)
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80001ba: f3af 8000 nop.w
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80001be: bd08 pop {r3, pc}
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80001c0: 00000000 .word 0x00000000
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80001c4: 20000070 .word 0x20000070
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80001c8: 08005b10 .word 0x08005b10
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080001cc <strlen>:
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80001cc: 4603 mov r3, r0
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80001ce: f813 2b01 ldrb.w r2, [r3], #1
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80001d2: 2a00 cmp r2, #0
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80001d4: d1fb bne.n 80001ce <strlen+0x2>
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80001d6: 1a18 subs r0, r3, r0
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80001d8: 3801 subs r0, #1
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80001da: 4770 bx lr
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080001dc <__aeabi_uldivmod>:
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80001dc: b953 cbnz r3, 80001f4 <__aeabi_uldivmod+0x18>
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80001de: b94a cbnz r2, 80001f4 <__aeabi_uldivmod+0x18>
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80001e0: 2900 cmp r1, #0
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80001e2: bf08 it eq
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80001e4: 2800 cmpeq r0, #0
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80001e6: bf1c itt ne
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80001e8: f04f 31ff movne.w r1, #4294967295
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80001ec: f04f 30ff movne.w r0, #4294967295
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80001f0: f000 b970 b.w 80004d4 <__aeabi_idiv0>
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80001f4: f1ad 0c08 sub.w ip, sp, #8
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80001f8: e96d ce04 strd ip, lr, [sp, #-16]!
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80001fc: f000 f806 bl 800020c <__udivmoddi4>
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8000200: f8dd e004 ldr.w lr, [sp, #4]
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8000204: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000208: b004 add sp, #16
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800020a: 4770 bx lr
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0800020c <__udivmoddi4>:
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800020c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000210: 9e08 ldr r6, [sp, #32]
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8000212: 460d mov r5, r1
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8000214: 4604 mov r4, r0
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8000216: 460f mov r7, r1
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8000218: 2b00 cmp r3, #0
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800021a: d14a bne.n 80002b2 <__udivmoddi4+0xa6>
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800021c: 428a cmp r2, r1
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800021e: 4694 mov ip, r2
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8000220: d965 bls.n 80002ee <__udivmoddi4+0xe2>
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8000222: fab2 f382 clz r3, r2
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8000226: b143 cbz r3, 800023a <__udivmoddi4+0x2e>
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8000228: fa02 fc03 lsl.w ip, r2, r3
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800022c: f1c3 0220 rsb r2, r3, #32
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8000230: 409f lsls r7, r3
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8000232: fa20 f202 lsr.w r2, r0, r2
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8000236: 4317 orrs r7, r2
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8000238: 409c lsls r4, r3
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800023a: ea4f 4e1c mov.w lr, ip, lsr #16
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800023e: fa1f f58c uxth.w r5, ip
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8000242: fbb7 f1fe udiv r1, r7, lr
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8000246: 0c22 lsrs r2, r4, #16
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8000248: fb0e 7711 mls r7, lr, r1, r7
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800024c: ea42 4207 orr.w r2, r2, r7, lsl #16
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8000250: fb01 f005 mul.w r0, r1, r5
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8000254: 4290 cmp r0, r2
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8000256: d90a bls.n 800026e <__udivmoddi4+0x62>
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8000258: eb1c 0202 adds.w r2, ip, r2
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800025c: f101 37ff add.w r7, r1, #4294967295
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8000260: f080 811c bcs.w 800049c <__udivmoddi4+0x290>
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8000264: 4290 cmp r0, r2
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8000266: f240 8119 bls.w 800049c <__udivmoddi4+0x290>
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800026a: 3902 subs r1, #2
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800026c: 4462 add r2, ip
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800026e: 1a12 subs r2, r2, r0
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8000270: b2a4 uxth r4, r4
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8000272: fbb2 f0fe udiv r0, r2, lr
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8000276: fb0e 2210 mls r2, lr, r0, r2
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800027a: ea44 4402 orr.w r4, r4, r2, lsl #16
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800027e: fb00 f505 mul.w r5, r0, r5
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8000282: 42a5 cmp r5, r4
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8000284: d90a bls.n 800029c <__udivmoddi4+0x90>
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8000286: eb1c 0404 adds.w r4, ip, r4
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800028a: f100 32ff add.w r2, r0, #4294967295
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800028e: f080 8107 bcs.w 80004a0 <__udivmoddi4+0x294>
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8000292: 42a5 cmp r5, r4
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8000294: f240 8104 bls.w 80004a0 <__udivmoddi4+0x294>
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8000298: 4464 add r4, ip
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800029a: 3802 subs r0, #2
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800029c: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002a0: 1b64 subs r4, r4, r5
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80002a2: 2100 movs r1, #0
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80002a4: b11e cbz r6, 80002ae <__udivmoddi4+0xa2>
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80002a6: 40dc lsrs r4, r3
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80002a8: 2300 movs r3, #0
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80002aa: e9c6 4300 strd r4, r3, [r6]
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80002ae: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002b2: 428b cmp r3, r1
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80002b4: d908 bls.n 80002c8 <__udivmoddi4+0xbc>
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80002b6: 2e00 cmp r6, #0
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80002b8: f000 80ed beq.w 8000496 <__udivmoddi4+0x28a>
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80002bc: 2100 movs r1, #0
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80002be: e9c6 0500 strd r0, r5, [r6]
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80002c2: 4608 mov r0, r1
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80002c4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002c8: fab3 f183 clz r1, r3
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80002cc: 2900 cmp r1, #0
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80002ce: d149 bne.n 8000364 <__udivmoddi4+0x158>
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80002d0: 42ab cmp r3, r5
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80002d2: d302 bcc.n 80002da <__udivmoddi4+0xce>
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80002d4: 4282 cmp r2, r0
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80002d6: f200 80f8 bhi.w 80004ca <__udivmoddi4+0x2be>
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80002da: 1a84 subs r4, r0, r2
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80002dc: eb65 0203 sbc.w r2, r5, r3
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80002e0: 2001 movs r0, #1
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80002e2: 4617 mov r7, r2
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80002e4: 2e00 cmp r6, #0
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80002e6: d0e2 beq.n 80002ae <__udivmoddi4+0xa2>
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80002e8: e9c6 4700 strd r4, r7, [r6]
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80002ec: e7df b.n 80002ae <__udivmoddi4+0xa2>
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80002ee: b902 cbnz r2, 80002f2 <__udivmoddi4+0xe6>
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80002f0: deff udf #255 ; 0xff
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80002f2: fab2 f382 clz r3, r2
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80002f6: 2b00 cmp r3, #0
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80002f8: f040 8090 bne.w 800041c <__udivmoddi4+0x210>
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80002fc: 1a8a subs r2, r1, r2
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80002fe: ea4f 471c mov.w r7, ip, lsr #16
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8000302: fa1f fe8c uxth.w lr, ip
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8000306: 2101 movs r1, #1
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8000308: fbb2 f5f7 udiv r5, r2, r7
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800030c: fb07 2015 mls r0, r7, r5, r2
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8000310: 0c22 lsrs r2, r4, #16
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8000312: ea42 4200 orr.w r2, r2, r0, lsl #16
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8000316: fb0e f005 mul.w r0, lr, r5
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800031a: 4290 cmp r0, r2
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800031c: d908 bls.n 8000330 <__udivmoddi4+0x124>
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800031e: eb1c 0202 adds.w r2, ip, r2
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8000322: f105 38ff add.w r8, r5, #4294967295
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8000326: d202 bcs.n 800032e <__udivmoddi4+0x122>
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8000328: 4290 cmp r0, r2
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800032a: f200 80cb bhi.w 80004c4 <__udivmoddi4+0x2b8>
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800032e: 4645 mov r5, r8
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8000330: 1a12 subs r2, r2, r0
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8000332: b2a4 uxth r4, r4
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8000334: fbb2 f0f7 udiv r0, r2, r7
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8000338: fb07 2210 mls r2, r7, r0, r2
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800033c: ea44 4402 orr.w r4, r4, r2, lsl #16
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8000340: fb0e fe00 mul.w lr, lr, r0
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8000344: 45a6 cmp lr, r4
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8000346: d908 bls.n 800035a <__udivmoddi4+0x14e>
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8000348: eb1c 0404 adds.w r4, ip, r4
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800034c: f100 32ff add.w r2, r0, #4294967295
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8000350: d202 bcs.n 8000358 <__udivmoddi4+0x14c>
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8000352: 45a6 cmp lr, r4
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8000354: f200 80bb bhi.w 80004ce <__udivmoddi4+0x2c2>
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8000358: 4610 mov r0, r2
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800035a: eba4 040e sub.w r4, r4, lr
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800035e: ea40 4005 orr.w r0, r0, r5, lsl #16
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8000362: e79f b.n 80002a4 <__udivmoddi4+0x98>
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8000364: f1c1 0720 rsb r7, r1, #32
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8000368: 408b lsls r3, r1
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800036a: fa22 fc07 lsr.w ip, r2, r7
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800036e: ea4c 0c03 orr.w ip, ip, r3
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8000372: fa05 f401 lsl.w r4, r5, r1
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8000376: fa20 f307 lsr.w r3, r0, r7
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800037a: 40fd lsrs r5, r7
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800037c: ea4f 491c mov.w r9, ip, lsr #16
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8000380: 4323 orrs r3, r4
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8000382: fbb5 f8f9 udiv r8, r5, r9
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8000386: fa1f fe8c uxth.w lr, ip
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800038a: fb09 5518 mls r5, r9, r8, r5
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800038e: 0c1c lsrs r4, r3, #16
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8000390: ea44 4405 orr.w r4, r4, r5, lsl #16
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8000394: fb08 f50e mul.w r5, r8, lr
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8000398: 42a5 cmp r5, r4
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800039a: fa02 f201 lsl.w r2, r2, r1
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800039e: fa00 f001 lsl.w r0, r0, r1
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80003a2: d90b bls.n 80003bc <__udivmoddi4+0x1b0>
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80003a4: eb1c 0404 adds.w r4, ip, r4
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80003a8: f108 3aff add.w sl, r8, #4294967295
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80003ac: f080 8088 bcs.w 80004c0 <__udivmoddi4+0x2b4>
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80003b0: 42a5 cmp r5, r4
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80003b2: f240 8085 bls.w 80004c0 <__udivmoddi4+0x2b4>
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80003b6: f1a8 0802 sub.w r8, r8, #2
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80003ba: 4464 add r4, ip
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80003bc: 1b64 subs r4, r4, r5
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80003be: b29d uxth r5, r3
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80003c0: fbb4 f3f9 udiv r3, r4, r9
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80003c4: fb09 4413 mls r4, r9, r3, r4
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80003c8: ea45 4404 orr.w r4, r5, r4, lsl #16
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80003cc: fb03 fe0e mul.w lr, r3, lr
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80003d0: 45a6 cmp lr, r4
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80003d2: d908 bls.n 80003e6 <__udivmoddi4+0x1da>
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80003d4: eb1c 0404 adds.w r4, ip, r4
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80003d8: f103 35ff add.w r5, r3, #4294967295
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80003dc: d26c bcs.n 80004b8 <__udivmoddi4+0x2ac>
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80003de: 45a6 cmp lr, r4
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80003e0: d96a bls.n 80004b8 <__udivmoddi4+0x2ac>
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80003e2: 3b02 subs r3, #2
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80003e4: 4464 add r4, ip
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80003e6: ea43 4308 orr.w r3, r3, r8, lsl #16
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80003ea: fba3 9502 umull r9, r5, r3, r2
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80003ee: eba4 040e sub.w r4, r4, lr
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80003f2: 42ac cmp r4, r5
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80003f4: 46c8 mov r8, r9
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80003f6: 46ae mov lr, r5
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80003f8: d356 bcc.n 80004a8 <__udivmoddi4+0x29c>
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80003fa: d053 beq.n 80004a4 <__udivmoddi4+0x298>
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80003fc: b156 cbz r6, 8000414 <__udivmoddi4+0x208>
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80003fe: ebb0 0208 subs.w r2, r0, r8
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8000402: eb64 040e sbc.w r4, r4, lr
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8000406: fa04 f707 lsl.w r7, r4, r7
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800040a: 40ca lsrs r2, r1
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800040c: 40cc lsrs r4, r1
|
|
|
800040e: 4317 orrs r7, r2
|
|
|
8000410: e9c6 7400 strd r7, r4, [r6]
|
|
|
8000414: 4618 mov r0, r3
|
|
|
8000416: 2100 movs r1, #0
|
|
|
8000418: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
800041c: f1c3 0120 rsb r1, r3, #32
|
|
|
8000420: fa02 fc03 lsl.w ip, r2, r3
|
|
|
8000424: fa20 f201 lsr.w r2, r0, r1
|
|
|
8000428: fa25 f101 lsr.w r1, r5, r1
|
|
|
800042c: 409d lsls r5, r3
|
|
|
800042e: 432a orrs r2, r5
|
|
|
8000430: ea4f 471c mov.w r7, ip, lsr #16
|
|
|
8000434: fa1f fe8c uxth.w lr, ip
|
|
|
8000438: fbb1 f0f7 udiv r0, r1, r7
|
|
|
800043c: fb07 1510 mls r5, r7, r0, r1
|
|
|
8000440: 0c11 lsrs r1, r2, #16
|
|
|
8000442: ea41 4105 orr.w r1, r1, r5, lsl #16
|
|
|
8000446: fb00 f50e mul.w r5, r0, lr
|
|
|
800044a: 428d cmp r5, r1
|
|
|
800044c: fa04 f403 lsl.w r4, r4, r3
|
|
|
8000450: d908 bls.n 8000464 <__udivmoddi4+0x258>
|
|
|
8000452: eb1c 0101 adds.w r1, ip, r1
|
|
|
8000456: f100 38ff add.w r8, r0, #4294967295
|
|
|
800045a: d22f bcs.n 80004bc <__udivmoddi4+0x2b0>
|
|
|
800045c: 428d cmp r5, r1
|
|
|
800045e: d92d bls.n 80004bc <__udivmoddi4+0x2b0>
|
|
|
8000460: 3802 subs r0, #2
|
|
|
8000462: 4461 add r1, ip
|
|
|
8000464: 1b49 subs r1, r1, r5
|
|
|
8000466: b292 uxth r2, r2
|
|
|
8000468: fbb1 f5f7 udiv r5, r1, r7
|
|
|
800046c: fb07 1115 mls r1, r7, r5, r1
|
|
|
8000470: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
|
8000474: fb05 f10e mul.w r1, r5, lr
|
|
|
8000478: 4291 cmp r1, r2
|
|
|
800047a: d908 bls.n 800048e <__udivmoddi4+0x282>
|
|
|
800047c: eb1c 0202 adds.w r2, ip, r2
|
|
|
8000480: f105 38ff add.w r8, r5, #4294967295
|
|
|
8000484: d216 bcs.n 80004b4 <__udivmoddi4+0x2a8>
|
|
|
8000486: 4291 cmp r1, r2
|
|
|
8000488: d914 bls.n 80004b4 <__udivmoddi4+0x2a8>
|
|
|
800048a: 3d02 subs r5, #2
|
|
|
800048c: 4462 add r2, ip
|
|
|
800048e: 1a52 subs r2, r2, r1
|
|
|
8000490: ea45 4100 orr.w r1, r5, r0, lsl #16
|
|
|
8000494: e738 b.n 8000308 <__udivmoddi4+0xfc>
|
|
|
8000496: 4631 mov r1, r6
|
|
|
8000498: 4630 mov r0, r6
|
|
|
800049a: e708 b.n 80002ae <__udivmoddi4+0xa2>
|
|
|
800049c: 4639 mov r1, r7
|
|
|
800049e: e6e6 b.n 800026e <__udivmoddi4+0x62>
|
|
|
80004a0: 4610 mov r0, r2
|
|
|
80004a2: e6fb b.n 800029c <__udivmoddi4+0x90>
|
|
|
80004a4: 4548 cmp r0, r9
|
|
|
80004a6: d2a9 bcs.n 80003fc <__udivmoddi4+0x1f0>
|
|
|
80004a8: ebb9 0802 subs.w r8, r9, r2
|
|
|
80004ac: eb65 0e0c sbc.w lr, r5, ip
|
|
|
80004b0: 3b01 subs r3, #1
|
|
|
80004b2: e7a3 b.n 80003fc <__udivmoddi4+0x1f0>
|
|
|
80004b4: 4645 mov r5, r8
|
|
|
80004b6: e7ea b.n 800048e <__udivmoddi4+0x282>
|
|
|
80004b8: 462b mov r3, r5
|
|
|
80004ba: e794 b.n 80003e6 <__udivmoddi4+0x1da>
|
|
|
80004bc: 4640 mov r0, r8
|
|
|
80004be: e7d1 b.n 8000464 <__udivmoddi4+0x258>
|
|
|
80004c0: 46d0 mov r8, sl
|
|
|
80004c2: e77b b.n 80003bc <__udivmoddi4+0x1b0>
|
|
|
80004c4: 3d02 subs r5, #2
|
|
|
80004c6: 4462 add r2, ip
|
|
|
80004c8: e732 b.n 8000330 <__udivmoddi4+0x124>
|
|
|
80004ca: 4608 mov r0, r1
|
|
|
80004cc: e70a b.n 80002e4 <__udivmoddi4+0xd8>
|
|
|
80004ce: 4464 add r4, ip
|
|
|
80004d0: 3802 subs r0, #2
|
|
|
80004d2: e742 b.n 800035a <__udivmoddi4+0x14e>
|
|
|
|
|
|
080004d4 <__aeabi_idiv0>:
|
|
|
80004d4: 4770 bx lr
|
|
|
80004d6: bf00 nop
|
|
|
|
|
|
080004d8 <LoRa_SendCmd>:
|
|
|
* uint8_t *result，期望获得的结果
|
|
|
* uint32_t timeOut，等待期望结果的时间
|
|
|
* uint8_t isPrintf，是否打印 Log
|
|
|
*/
|
|
|
void LoRa_SendCmd(uint8_t *cmd, uint8_t *result, uint32_t timeOut, uint8_t isPrintf)
|
|
|
{
|
|
|
80004d8: b580 push {r7, lr}
|
|
|
80004da: b084 sub sp, #16
|
|
|
80004dc: af00 add r7, sp, #0
|
|
|
80004de: 60f8 str r0, [r7, #12]
|
|
|
80004e0: 60b9 str r1, [r7, #8]
|
|
|
80004e2: 607a str r2, [r7, #4]
|
|
|
80004e4: 70fb strb r3, [r7, #3]
|
|
|
// char *pos;
|
|
|
HAL_UART_Transmit(&hlpuart1, cmd, strlen((const char *)cmd), 0xff); // 发送AT 指令
|
|
|
80004e6: 68f8 ldr r0, [r7, #12]
|
|
|
80004e8: f7ff fe70 bl 80001cc <strlen>
|
|
|
80004ec: 4603 mov r3, r0
|
|
|
80004ee: b29a uxth r2, r3
|
|
|
80004f0: 23ff movs r3, #255 ; 0xff
|
|
|
80004f2: 68f9 ldr r1, [r7, #12]
|
|
|
80004f4: 4804 ldr r0, [pc, #16] ; (8000508 <LoRa_SendCmd+0x30>)
|
|
|
80004f6: f003 f9e5 bl 80038c4 <HAL_UART_Transmit>
|
|
|
//HAL_UART_Receive_IT(&hlpuart1, bRxBufferUart1, 1); // 启动低功耗串口接收中断
|
|
|
HAL_Delay(timeOut); // 延时等待
|
|
|
80004fa: 6878 ldr r0, [r7, #4]
|
|
|
80004fc: f000 fda0 bl 8001040 <HAL_Delay>
|
|
|
// // error 或者无应答，再次发送
|
|
|
// HAL_UART_Receive_IT(&hlpuart1, bRxBufferUart1, 1); // 启动低功耗串口接收中断
|
|
|
// HAL_Delay(timeOut);
|
|
|
// }
|
|
|
// }
|
|
|
}
|
|
|
8000500: bf00 nop
|
|
|
8000502: 3710 adds r7, #16
|
|
|
8000504: 46bd mov sp, r7
|
|
|
8000506: bd80 pop {r7, pc}
|
|
|
8000508: 20000088 .word 0x20000088
|
|
|
|
|
|
0800050c <LoRa_T_V_Attach>:
|
|
|
* uint8_t isPrintf:是否打印 Log
|
|
|
* uint8_t isReboot:是否重启
|
|
|
* 模块地址：0xFFFF 通信信道：10 发射功率：11dbm
|
|
|
*/
|
|
|
void LoRa_T_V_Attach(uint8_t isPrintf, uint8_t isReboot)
|
|
|
{
|
|
|
800050c: b580 push {r7, lr}
|
|
|
800050e: b082 sub sp, #8
|
|
|
8000510: af00 add r7, sp, #0
|
|
|
8000512: 4603 mov r3, r0
|
|
|
8000514: 460a mov r2, r1
|
|
|
8000516: 71fb strb r3, [r7, #7]
|
|
|
8000518: 4613 mov r3, r2
|
|
|
800051a: 71bb strb r3, [r7, #6]
|
|
|
if (isReboot == 1)
|
|
|
800051c: 79bb ldrb r3, [r7, #6]
|
|
|
800051e: 2b01 cmp r3, #1
|
|
|
8000520: d143 bne.n 80005aa <LoRa_T_V_Attach+0x9e>
|
|
|
{
|
|
|
//HAL_GPIO_WritePin(PA0_GPIO_Port, PA0_Pin, GPIO_PIN_SET);
|
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_SET);
|
|
|
8000522: 2201 movs r2, #1
|
|
|
8000524: 2101 movs r1, #1
|
|
|
8000526: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
|
800052a: f001 f8cf bl 80016cc <HAL_GPIO_WritePin>
|
|
|
HAL_Delay(1000);
|
|
|
800052e: f44f 707a mov.w r0, #1000 ; 0x3e8
|
|
|
8000532: f000 fd85 bl 8001040 <HAL_Delay>
|
|
|
LoRa_SendCmd((uint8_t *)"AT+UART=7,0\r\n", (uint8_t *)"OK",
|
|
|
8000536: 4b1f ldr r3, [pc, #124] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
8000538: 681a ldr r2, [r3, #0]
|
|
|
800053a: 79fb ldrb r3, [r7, #7]
|
|
|
800053c: 491e ldr r1, [pc, #120] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
800053e: 481f ldr r0, [pc, #124] ; (80005bc <LoRa_T_V_Attach+0xb0>)
|
|
|
8000540: f7ff ffca bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
LoRa_SendCmd((uint8_t *)"AT+WLRATE=11,5\r\n", (uint8_t *)"OK",
|
|
|
8000544: 4b1b ldr r3, [pc, #108] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
8000546: 681a ldr r2, [r3, #0]
|
|
|
8000548: 79fb ldrb r3, [r7, #7]
|
|
|
800054a: 491b ldr r1, [pc, #108] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
800054c: 481c ldr r0, [pc, #112] ; (80005c0 <LoRa_T_V_Attach+0xb4>)
|
|
|
800054e: f7ff ffc3 bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
LoRa_SendCmd((uint8_t *)"AT+TPOWER=0\r\n", (uint8_t *)"OK",
|
|
|
8000552: 4b18 ldr r3, [pc, #96] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
8000554: 681a ldr r2, [r3, #0]
|
|
|
8000556: 79fb ldrb r3, [r7, #7]
|
|
|
8000558: 4917 ldr r1, [pc, #92] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
800055a: 481a ldr r0, [pc, #104] ; (80005c4 <LoRa_T_V_Attach+0xb8>)
|
|
|
800055c: f7ff ffbc bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
LoRa_SendCmd((uint8_t *)"AT+TMODE=0\r\n", (uint8_t *)"OK",
|
|
|
8000560: 4b14 ldr r3, [pc, #80] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
8000562: 681a ldr r2, [r3, #0]
|
|
|
8000564: 79fb ldrb r3, [r7, #7]
|
|
|
8000566: 4914 ldr r1, [pc, #80] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
8000568: 4817 ldr r0, [pc, #92] ; (80005c8 <LoRa_T_V_Attach+0xbc>)
|
|
|
800056a: f7ff ffb5 bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
LoRa_SendCmd((uint8_t *)"AT+WLTIME=0\r\n", (uint8_t *)"OK",
|
|
|
800056e: 4b11 ldr r3, [pc, #68] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
8000570: 681a ldr r2, [r3, #0]
|
|
|
8000572: 79fb ldrb r3, [r7, #7]
|
|
|
8000574: 4910 ldr r1, [pc, #64] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
8000576: 4815 ldr r0, [pc, #84] ; (80005cc <LoRa_T_V_Attach+0xc0>)
|
|
|
8000578: f7ff ffae bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
LoRa_SendCmd((uint8_t *)"AT+CWMODE=0\r\n", (uint8_t *)"OK",
|
|
|
800057c: 4b0d ldr r3, [pc, #52] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
800057e: 681a ldr r2, [r3, #0]
|
|
|
8000580: 79fb ldrb r3, [r7, #7]
|
|
|
8000582: 490d ldr r1, [pc, #52] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
8000584: 4812 ldr r0, [pc, #72] ; (80005d0 <LoRa_T_V_Attach+0xc4>)
|
|
|
8000586: f7ff ffa7 bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
LoRa_SendCmd((uint8_t *)"AT+ADDR=FF,FF\r\n", (uint8_t *)"OK",
|
|
|
800058a: 4b0a ldr r3, [pc, #40] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
|
|
|
800058c: 681a ldr r2, [r3, #0]
|
|
|
800058e: 79fb ldrb r3, [r7, #7]
|
|
|
8000590: 4909 ldr r1, [pc, #36] ; (80005b8 <LoRa_T_V_Attach+0xac>)
|
|
|
8000592: 4810 ldr r0, [pc, #64] ; (80005d4 <LoRa_T_V_Attach+0xc8>)
|
|
|
8000594: f7ff ffa0 bl 80004d8 <LoRa_SendCmd>
|
|
|
DefaultTimeout, isPrintf);
|
|
|
//HAL_GPIO_WritePin(PA0_GPIO_Port, PA0_Pin, GPIO_PIN_RESET);
|
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
|
|
|
8000598: 2200 movs r2, #0
|
|
|
800059a: 2101 movs r1, #1
|
|
|
800059c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
|
80005a0: f001 f894 bl 80016cc <HAL_GPIO_WritePin>
|
|
|
printf("Attach!\r\n");
|
|
|
80005a4: 480c ldr r0, [pc, #48] ; (80005d8 <LoRa_T_V_Attach+0xcc>)
|
|
|
80005a6: f004 ff1d bl 80053e4 <puts>
|
|
|
}
|
|
|
}
|
|
|
80005aa: bf00 nop
|
|
|
80005ac: 3708 adds r7, #8
|
|
|
80005ae: 46bd mov sp, r7
|
|
|
80005b0: bd80 pop {r7, pc}
|
|
|
80005b2: bf00 nop
|
|
|
80005b4: 20000000 .word 0x20000000
|
|
|
80005b8: 08005b28 .word 0x08005b28
|
|
|
80005bc: 08005b2c .word 0x08005b2c
|
|
|
80005c0: 08005bac .word 0x08005bac
|
|
|
80005c4: 08005b50 .word 0x08005b50
|
|
|
80005c8: 08005b60 .word 0x08005b60
|
|
|
80005cc: 08005b70 .word 0x08005b70
|
|
|
80005d0: 08005b80 .word 0x08005b80
|
|
|
80005d4: 08005bc0 .word 0x08005bc0
|
|
|
80005d8: 08005ba0 .word 0x08005ba0
|
|
|
|
|
|
080005dc <Serial1_SendArray>:
|
|
|
static void MX_LPUART1_UART_Init(void);
|
|
|
static void MX_USART1_UART_Init(void);
|
|
|
static void MX_TIM1_Init(void);
|
|
|
/* USER CODE BEGIN PFP */
|
|
|
void Serial1_SendArray(uint8_t *Array, uint16_t Length)
|
|
|
{
|
|
|
80005dc: b580 push {r7, lr}
|
|
|
80005de: b082 sub sp, #8
|
|
|
80005e0: af00 add r7, sp, #0
|
|
|
80005e2: 6078 str r0, [r7, #4]
|
|
|
80005e4: 460b mov r3, r1
|
|
|
80005e6: 807b strh r3, [r7, #2]
|
|
|
HAL_UART_Transmit_IT(&huart1, Array, Length);
|
|
|
80005e8: 887b ldrh r3, [r7, #2]
|
|
|
80005ea: 461a mov r2, r3
|
|
|
80005ec: 6879 ldr r1, [r7, #4]
|
|
|
80005ee: 4803 ldr r0, [pc, #12] ; (80005fc <Serial1_SendArray+0x20>)
|
|
|
80005f0: f003 f9f2 bl 80039d8 <HAL_UART_Transmit_IT>
|
|
|
}
|
|
|
80005f4: bf00 nop
|
|
|
80005f6: 3708 adds r7, #8
|
|
|
80005f8: 46bd mov sp, r7
|
|
|
80005fa: bd80 pop {r7, pc}
|
|
|
80005fc: 20000110 .word 0x20000110
|
|
|
|
|
|
08000600 <Seriallp_SendArray>:
|
|
|
void Seriallp_SendArray(uint8_t *Array, uint16_t Length)
|
|
|
{
|
|
|
8000600: b580 push {r7, lr}
|
|
|
8000602: b082 sub sp, #8
|
|
|
8000604: af00 add r7, sp, #0
|
|
|
8000606: 6078 str r0, [r7, #4]
|
|
|
8000608: 460b mov r3, r1
|
|
|
800060a: 807b strh r3, [r7, #2]
|
|
|
HAL_UART_Transmit_IT(&hlpuart1, Array, Length);
|
|
|
800060c: 887b ldrh r3, [r7, #2]
|
|
|
800060e: 461a mov r2, r3
|
|
|
8000610: 6879 ldr r1, [r7, #4]
|
|
|
8000612: 4803 ldr r0, [pc, #12] ; (8000620 <Seriallp_SendArray+0x20>)
|
|
|
8000614: f003 f9e0 bl 80039d8 <HAL_UART_Transmit_IT>
|
|
|
}
|
|
|
8000618: bf00 nop
|
|
|
800061a: 3708 adds r7, #8
|
|
|
800061c: 46bd mov sp, r7
|
|
|
800061e: bd80 pop {r7, pc}
|
|
|
8000620: 20000088 .word 0x20000088
|
|
|
|
|
|
08000624 <HAL_UART_RxCpltCallback>:
|
|
|
|
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle)
|
|
|
{
|
|
|
8000624: b580 push {r7, lr}
|
|
|
8000626: b082 sub sp, #8
|
|
|
8000628: af00 add r7, sp, #0
|
|
|
800062a: 6078 str r0, [r7, #4]
|
|
|
HAL_UART_Receive_IT(&huart1, Rarr, 5);
|
|
|
800062c: 2205 movs r2, #5
|
|
|
800062e: 4906 ldr r1, [pc, #24] ; (8000648 <HAL_UART_RxCpltCallback+0x24>)
|
|
|
8000630: 4806 ldr r0, [pc, #24] ; (800064c <HAL_UART_RxCpltCallback+0x28>)
|
|
|
8000632: f003 fa2f bl 8003a94 <HAL_UART_Receive_IT>
|
|
|
Serial1_SendArray(Rarr, sizeof(Rarr) / sizeof(Rarr[0]));
|
|
|
8000636: 2132 movs r1, #50 ; 0x32
|
|
|
8000638: 4803 ldr r0, [pc, #12] ; (8000648 <HAL_UART_RxCpltCallback+0x24>)
|
|
|
800063a: f7ff ffcf bl 80005dc <Serial1_SendArray>
|
|
|
}
|
|
|
800063e: bf00 nop
|
|
|
8000640: 3708 adds r7, #8
|
|
|
8000642: 46bd mov sp, r7
|
|
|
8000644: bd80 pop {r7, pc}
|
|
|
8000646: bf00 nop
|
|
|
8000648: 200001e4 .word 0x200001e4
|
|
|
800064c: 20000110 .word 0x20000110
|
|
|
|
|
|
08000650 <HAL_UARTEx_RxEventCallback>:
|
|
|
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
|
{
|
|
|
8000650: b580 push {r7, lr}
|
|
|
8000652: b082 sub sp, #8
|
|
|
8000654: af00 add r7, sp, #0
|
|
|
8000656: 6078 str r0, [r7, #4]
|
|
|
8000658: 460b mov r3, r1
|
|
|
800065a: 807b strh r3, [r7, #2]
|
|
|
if (huart->Instance == USART1)
|
|
|
800065c: 687b ldr r3, [r7, #4]
|
|
|
800065e: 681b ldr r3, [r3, #0]
|
|
|
8000660: 4a10 ldr r2, [pc, #64] ; (80006a4 <HAL_UARTEx_RxEventCallback+0x54>)
|
|
|
8000662: 4293 cmp r3, r2
|
|
|
8000664: d10a bne.n 800067c <HAL_UARTEx_RxEventCallback+0x2c>
|
|
|
{
|
|
|
//Serial1_SendArray(Rarr, Size);
|
|
|
Seriallp_SendArray(Rarr, Size);
|
|
|
8000666: 887b ldrh r3, [r7, #2]
|
|
|
8000668: 4619 mov r1, r3
|
|
|
800066a: 480f ldr r0, [pc, #60] ; (80006a8 <HAL_UARTEx_RxEventCallback+0x58>)
|
|
|
800066c: f7ff ffc8 bl 8000600 <Seriallp_SendArray>
|
|
|
HAL_UARTEx_ReceiveToIdle_IT(&huart1, Rarr, 50);
|
|
|
8000670: 2232 movs r2, #50 ; 0x32
|
|
|
8000672: 490d ldr r1, [pc, #52] ; (80006a8 <HAL_UARTEx_RxEventCallback+0x58>)
|
|
|
8000674: 480d ldr r0, [pc, #52] ; (80006ac <HAL_UARTEx_RxEventCallback+0x5c>)
|
|
|
8000676: f004 fd4f bl 8005118 <HAL_UARTEx_ReceiveToIdle_IT>
|
|
|
|
|
|
// uint8_t atCommand[50]={0};
|
|
|
// sprintf(atCommand, "AT+SEND=%d,%s\r\n", strlen(Rarr), Rarr);
|
|
|
// Serial1_SendArray(atCommand, strlen(atCommand));
|
|
|
// LoRa_SendCmd((uint8_t *)atCommand, (uint8_t *)"OK", 300, 1);
|
|
|
}
|
|
|
800067a: e00e b.n 800069a <HAL_UARTEx_RxEventCallback+0x4a>
|
|
|
else if (huart->Instance == LPUART1)
|
|
|
800067c: 687b ldr r3, [r7, #4]
|
|
|
800067e: 681b ldr r3, [r3, #0]
|
|
|
8000680: 4a0b ldr r2, [pc, #44] ; (80006b0 <HAL_UARTEx_RxEventCallback+0x60>)
|
|
|
8000682: 4293 cmp r3, r2
|
|
|
8000684: d109 bne.n 800069a <HAL_UARTEx_RxEventCallback+0x4a>
|
|
|
Serial1_SendArray(Rarr, Size);
|
|
|
8000686: 887b ldrh r3, [r7, #2]
|
|
|
8000688: 4619 mov r1, r3
|
|
|
800068a: 4807 ldr r0, [pc, #28] ; (80006a8 <HAL_UARTEx_RxEventCallback+0x58>)
|
|
|
800068c: f7ff ffa6 bl 80005dc <Serial1_SendArray>
|
|
|
HAL_UARTEx_ReceiveToIdle_IT(&hlpuart1, Rarr, 50);
|
|
|
8000690: 2232 movs r2, #50 ; 0x32
|
|
|
8000692: 4905 ldr r1, [pc, #20] ; (80006a8 <HAL_UARTEx_RxEventCallback+0x58>)
|
|
|
8000694: 4807 ldr r0, [pc, #28] ; (80006b4 <HAL_UARTEx_RxEventCallback+0x64>)
|
|
|
8000696: f004 fd3f bl 8005118 <HAL_UARTEx_ReceiveToIdle_IT>
|
|
|
}
|
|
|
800069a: bf00 nop
|
|
|
800069c: 3708 adds r7, #8
|
|
|
800069e: 46bd mov sp, r7
|
|
|
80006a0: bd80 pop {r7, pc}
|
|
|
80006a2: bf00 nop
|
|
|
80006a4: 40013800 .word 0x40013800
|
|
|
80006a8: 200001e4 .word 0x200001e4
|
|
|
80006ac: 20000110 .word 0x20000110
|
|
|
80006b0: 40008000 .word 0x40008000
|
|
|
80006b4: 20000088 .word 0x20000088
|
|
|
|
|
|
080006b8 <main>:
|
|
|
/**
|
|
|
* @brief The application entry point.
|
|
|
* @retval int
|
|
|
*/
|
|
|
int main(void)
|
|
|
{
|
|
|
80006b8: b580 push {r7, lr}
|
|
|
80006ba: b082 sub sp, #8
|
|
|
80006bc: af00 add r7, sp, #0
|
|
|
/* USER CODE END 1 */
|
|
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
|
HAL_Init();
|
|
|
80006be: f000 fc4a bl 8000f56 <HAL_Init>
|
|
|
/* USER CODE BEGIN Init */
|
|
|
|
|
|
/* USER CODE END Init */
|
|
|
|
|
|
/* Configure the system clock */
|
|
|
SystemClock_Config();
|
|
|
80006c2: f000 f84d bl 8000760 <SystemClock_Config>
|
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
|
|
/* Initialize all configured peripherals */
|
|
|
MX_GPIO_Init();
|
|
|
80006c6: f000 f9a3 bl 8000a10 <MX_GPIO_Init>
|
|
|
MX_LPUART1_UART_Init();
|
|
|
80006ca: f000 f899 bl 8000800 <MX_LPUART1_UART_Init>
|
|
|
MX_USART1_UART_Init();
|
|
|
80006ce: f000 f8c3 bl 8000858 <MX_USART1_UART_Init>
|
|
|
MX_TIM1_Init();
|
|
|
80006d2: f000 f8f1 bl 80008b8 <MX_TIM1_Init>
|
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
|
|
HAL_UARTEx_ReceiveToIdle_IT(&huart1, Rarr, 50);
|
|
|
80006d6: 2232 movs r2, #50 ; 0x32
|
|
|
80006d8: 491b ldr r1, [pc, #108] ; (8000748 <main+0x90>)
|
|
|
80006da: 481c ldr r0, [pc, #112] ; (800074c <main+0x94>)
|
|
|
80006dc: f004 fd1c bl 8005118 <HAL_UARTEx_ReceiveToIdle_IT>
|
|
|
HAL_UARTEx_ReceiveToIdle_IT(&hlpuart1, Rarr, 50);
|
|
|
80006e0: 2232 movs r2, #50 ; 0x32
|
|
|
80006e2: 4919 ldr r1, [pc, #100] ; (8000748 <main+0x90>)
|
|
|
80006e4: 481a ldr r0, [pc, #104] ; (8000750 <main+0x98>)
|
|
|
80006e6: f004 fd17 bl 8005118 <HAL_UARTEx_ReceiveToIdle_IT>
|
|
|
LoRa_T_V_Attach(1,1);
|
|
|
80006ea: 2101 movs r1, #1
|
|
|
80006ec: 2001 movs r0, #1
|
|
|
80006ee: f7ff ff0d bl 800050c <LoRa_T_V_Attach>
|
|
|
uint16_t zt=0;
|
|
|
80006f2: 2300 movs r3, #0
|
|
|
80006f4: 80fb strh r3, [r7, #6]
|
|
|
//
|
|
|
// Seriallp_SendArray("NOBODY HERE\r\n", strlen("NOBODY HERE\r\n"));
|
|
|
//
|
|
|
// HAL_Delay(5000);
|
|
|
//
|
|
|
if(HAL_GPIO_ReadPin(GPIOB,8) == 1&&zt==0)
|
|
|
80006f6: 2108 movs r1, #8
|
|
|
80006f8: 4816 ldr r0, [pc, #88] ; (8000754 <main+0x9c>)
|
|
|
80006fa: f000 ffcf bl 800169c <HAL_GPIO_ReadPin>
|
|
|
80006fe: 4603 mov r3, r0
|
|
|
8000700: 2b01 cmp r3, #1
|
|
|
8000702: d10c bne.n 800071e <main+0x66>
|
|
|
8000704: 88fb ldrh r3, [r7, #6]
|
|
|
8000706: 2b00 cmp r3, #0
|
|
|
8000708: d109 bne.n 800071e <main+0x66>
|
|
|
{
|
|
|
Seriallp_SendArray("SOMEBODY HERE\r\n", strlen("SOMEBODY HERE\r\n"));
|
|
|
800070a: 210f movs r1, #15
|
|
|
800070c: 4812 ldr r0, [pc, #72] ; (8000758 <main+0xa0>)
|
|
|
800070e: f7ff ff77 bl 8000600 <Seriallp_SendArray>
|
|
|
zt=1;
|
|
|
8000712: 2301 movs r3, #1
|
|
|
8000714: 80fb strh r3, [r7, #6]
|
|
|
HAL_Delay(5000);
|
|
|
8000716: f241 3088 movw r0, #5000 ; 0x1388
|
|
|
800071a: f000 fc91 bl 8001040 <HAL_Delay>
|
|
|
}
|
|
|
if(HAL_GPIO_ReadPin(GPIOB,8) == 0&&zt==1)
|
|
|
800071e: 2108 movs r1, #8
|
|
|
8000720: 480c ldr r0, [pc, #48] ; (8000754 <main+0x9c>)
|
|
|
8000722: f000 ffbb bl 800169c <HAL_GPIO_ReadPin>
|
|
|
8000726: 4603 mov r3, r0
|
|
|
8000728: 2b00 cmp r3, #0
|
|
|
800072a: d1e4 bne.n 80006f6 <main+0x3e>
|
|
|
800072c: 88fb ldrh r3, [r7, #6]
|
|
|
800072e: 2b01 cmp r3, #1
|
|
|
8000730: d1e1 bne.n 80006f6 <main+0x3e>
|
|
|
{
|
|
|
Seriallp_SendArray("NOBODY HERE\r\n", strlen("NOBODY HERE\r\n"));
|
|
|
8000732: 210d movs r1, #13
|
|
|
8000734: 4809 ldr r0, [pc, #36] ; (800075c <main+0xa4>)
|
|
|
8000736: f7ff ff63 bl 8000600 <Seriallp_SendArray>
|
|
|
zt=0;
|
|
|
800073a: 2300 movs r3, #0
|
|
|
800073c: 80fb strh r3, [r7, #6]
|
|
|
HAL_Delay(5000);
|
|
|
800073e: f241 3088 movw r0, #5000 ; 0x1388
|
|
|
8000742: f000 fc7d bl 8001040 <HAL_Delay>
|
|
|
if(HAL_GPIO_ReadPin(GPIOB,8) == 1&&zt==0)
|
|
|
8000746: e7d6 b.n 80006f6 <main+0x3e>
|
|
|
8000748: 200001e4 .word 0x200001e4
|
|
|
800074c: 20000110 .word 0x20000110
|
|
|
8000750: 20000088 .word 0x20000088
|
|
|
8000754: 48000400 .word 0x48000400
|
|
|
8000758: 08005be0 .word 0x08005be0
|
|
|
800075c: 08005bf0 .word 0x08005bf0
|
|
|
|
|
|
08000760 <SystemClock_Config>:
|
|
|
/**
|
|
|
* @brief System Clock Configuration
|
|
|
* @retval None
|
|
|
*/
|
|
|
void SystemClock_Config(void)
|
|
|
{
|
|
|
8000760: b580 push {r7, lr}
|
|
|
8000762: b096 sub sp, #88 ; 0x58
|
|
|
8000764: af00 add r7, sp, #0
|
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
|
8000766: f107 0314 add.w r3, r7, #20
|
|
|
800076a: 2244 movs r2, #68 ; 0x44
|
|
|
800076c: 2100 movs r1, #0
|
|
|
800076e: 4618 mov r0, r3
|
|
|
8000770: f004 ff18 bl 80055a4 <memset>
|
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
|
8000774: 463b mov r3, r7
|
|
|
8000776: 2200 movs r2, #0
|
|
|
8000778: 601a str r2, [r3, #0]
|
|
|
800077a: 605a str r2, [r3, #4]
|
|
|
800077c: 609a str r2, [r3, #8]
|
|
|
800077e: 60da str r2, [r3, #12]
|
|
|
8000780: 611a str r2, [r3, #16]
|
|
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
|
*/
|
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
|
|
8000782: f44f 7000 mov.w r0, #512 ; 0x200
|
|
|
8000786: f000 ffc7 bl 8001718 <HAL_PWREx_ControlVoltageScaling>
|
|
|
800078a: 4603 mov r3, r0
|
|
|
800078c: 2b00 cmp r3, #0
|
|
|
800078e: d001 beq.n 8000794 <SystemClock_Config+0x34>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000790: f000 f996 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
|
* in the RCC_OscInitTypeDef structure.
|
|
|
*/
|
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
|
8000794: 2301 movs r3, #1
|
|
|
8000796: 617b str r3, [r7, #20]
|
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
|
8000798: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
|
800079c: 61bb str r3, [r7, #24]
|
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
|
800079e: 2302 movs r3, #2
|
|
|
80007a0: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
|
80007a2: 2303 movs r3, #3
|
|
|
80007a4: 643b str r3, [r7, #64] ; 0x40
|
|
|
RCC_OscInitStruct.PLL.PLLM = 2;
|
|
|
80007a6: 2302 movs r3, #2
|
|
|
80007a8: 647b str r3, [r7, #68] ; 0x44
|
|
|
RCC_OscInitStruct.PLL.PLLN = 40;
|
|
|
80007aa: 2328 movs r3, #40 ; 0x28
|
|
|
80007ac: 64bb str r3, [r7, #72] ; 0x48
|
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
|
|
80007ae: 2307 movs r3, #7
|
|
|
80007b0: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
|
80007b2: 2302 movs r3, #2
|
|
|
80007b4: 653b str r3, [r7, #80] ; 0x50
|
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
|
80007b6: 2302 movs r3, #2
|
|
|
80007b8: 657b str r3, [r7, #84] ; 0x54
|
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
|
80007ba: f107 0314 add.w r3, r7, #20
|
|
|
80007be: 4618 mov r0, r3
|
|
|
80007c0: f001 f800 bl 80017c4 <HAL_RCC_OscConfig>
|
|
|
80007c4: 4603 mov r3, r0
|
|
|
80007c6: 2b00 cmp r3, #0
|
|
|
80007c8: d001 beq.n 80007ce <SystemClock_Config+0x6e>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80007ca: f000 f979 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
|
*/
|
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
|
80007ce: 230f movs r3, #15
|
|
|
80007d0: 603b str r3, [r7, #0]
|
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
|
80007d2: 2303 movs r3, #3
|
|
|
80007d4: 607b str r3, [r7, #4]
|
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
|
80007d6: 2300 movs r3, #0
|
|
|
80007d8: 60bb str r3, [r7, #8]
|
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
|
|
80007da: f44f 63a0 mov.w r3, #1280 ; 0x500
|
|
|
80007de: 60fb str r3, [r7, #12]
|
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
|
80007e0: 2300 movs r3, #0
|
|
|
80007e2: 613b str r3, [r7, #16]
|
|
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
|
80007e4: 463b mov r3, r7
|
|
|
80007e6: 2104 movs r1, #4
|
|
|
80007e8: 4618 mov r0, r3
|
|
|
80007ea: f001 fbff bl 8001fec <HAL_RCC_ClockConfig>
|
|
|
80007ee: 4603 mov r3, r0
|
|
|
80007f0: 2b00 cmp r3, #0
|
|
|
80007f2: d001 beq.n 80007f8 <SystemClock_Config+0x98>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80007f4: f000 f964 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
}
|
|
|
80007f8: bf00 nop
|
|
|
80007fa: 3758 adds r7, #88 ; 0x58
|
|
|
80007fc: 46bd mov sp, r7
|
|
|
80007fe: bd80 pop {r7, pc}
|
|
|
|
|
|
08000800 <MX_LPUART1_UART_Init>:
|
|
|
* @brief LPUART1 Initialization Function
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void MX_LPUART1_UART_Init(void)
|
|
|
{
|
|
|
8000800: b580 push {r7, lr}
|
|
|
8000802: af00 add r7, sp, #0
|
|
|
/* USER CODE END LPUART1_Init 0 */
|
|
|
|
|
|
/* USER CODE BEGIN LPUART1_Init 1 */
|
|
|
|
|
|
/* USER CODE END LPUART1_Init 1 */
|
|
|
hlpuart1.Instance = LPUART1;
|
|
|
8000804: 4b12 ldr r3, [pc, #72] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
8000806: 4a13 ldr r2, [pc, #76] ; (8000854 <MX_LPUART1_UART_Init+0x54>)
|
|
|
8000808: 601a str r2, [r3, #0]
|
|
|
hlpuart1.Init.BaudRate = 115200;
|
|
|
800080a: 4b11 ldr r3, [pc, #68] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
800080c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
|
8000810: 605a str r2, [r3, #4]
|
|
|
hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
|
8000812: 4b0f ldr r3, [pc, #60] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
8000814: 2200 movs r2, #0
|
|
|
8000816: 609a str r2, [r3, #8]
|
|
|
hlpuart1.Init.StopBits = UART_STOPBITS_1;
|
|
|
8000818: 4b0d ldr r3, [pc, #52] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
800081a: 2200 movs r2, #0
|
|
|
800081c: 60da str r2, [r3, #12]
|
|
|
hlpuart1.Init.Parity = UART_PARITY_NONE;
|
|
|
800081e: 4b0c ldr r3, [pc, #48] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
8000820: 2200 movs r2, #0
|
|
|
8000822: 611a str r2, [r3, #16]
|
|
|
hlpuart1.Init.Mode = UART_MODE_TX_RX;
|
|
|
8000824: 4b0a ldr r3, [pc, #40] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
8000826: 220c movs r2, #12
|
|
|
8000828: 615a str r2, [r3, #20]
|
|
|
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
|
800082a: 4b09 ldr r3, [pc, #36] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
800082c: 2200 movs r2, #0
|
|
|
800082e: 619a str r2, [r3, #24]
|
|
|
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
|
8000830: 4b07 ldr r3, [pc, #28] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
8000832: 2200 movs r2, #0
|
|
|
8000834: 621a str r2, [r3, #32]
|
|
|
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
|
8000836: 4b06 ldr r3, [pc, #24] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
8000838: 2200 movs r2, #0
|
|
|
800083a: 625a str r2, [r3, #36] ; 0x24
|
|
|
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
|
|
|
800083c: 4804 ldr r0, [pc, #16] ; (8000850 <MX_LPUART1_UART_Init+0x50>)
|
|
|
800083e: f002 fff3 bl 8003828 <HAL_UART_Init>
|
|
|
8000842: 4603 mov r3, r0
|
|
|
8000844: 2b00 cmp r3, #0
|
|
|
8000846: d001 beq.n 800084c <MX_LPUART1_UART_Init+0x4c>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000848: f000 f93a bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN LPUART1_Init 2 */
|
|
|
|
|
|
/* USER CODE END LPUART1_Init 2 */
|
|
|
|
|
|
}
|
|
|
800084c: bf00 nop
|
|
|
800084e: bd80 pop {r7, pc}
|
|
|
8000850: 20000088 .word 0x20000088
|
|
|
8000854: 40008000 .word 0x40008000
|
|
|
|
|
|
08000858 <MX_USART1_UART_Init>:
|
|
|
* @brief USART1 Initialization Function
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void MX_USART1_UART_Init(void)
|
|
|
{
|
|
|
8000858: b580 push {r7, lr}
|
|
|
800085a: af00 add r7, sp, #0
|
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
|
huart1.Instance = USART1;
|
|
|
800085c: 4b14 ldr r3, [pc, #80] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
800085e: 4a15 ldr r2, [pc, #84] ; (80008b4 <MX_USART1_UART_Init+0x5c>)
|
|
|
8000860: 601a str r2, [r3, #0]
|
|
|
huart1.Init.BaudRate = 115200;
|
|
|
8000862: 4b13 ldr r3, [pc, #76] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
8000864: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
|
8000868: 605a str r2, [r3, #4]
|
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
|
800086a: 4b11 ldr r3, [pc, #68] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
800086c: 2200 movs r2, #0
|
|
|
800086e: 609a str r2, [r3, #8]
|
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
|
8000870: 4b0f ldr r3, [pc, #60] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
8000872: 2200 movs r2, #0
|
|
|
8000874: 60da str r2, [r3, #12]
|
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
|
8000876: 4b0e ldr r3, [pc, #56] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
8000878: 2200 movs r2, #0
|
|
|
800087a: 611a str r2, [r3, #16]
|
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
|
800087c: 4b0c ldr r3, [pc, #48] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
800087e: 220c movs r2, #12
|
|
|
8000880: 615a str r2, [r3, #20]
|
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
|
8000882: 4b0b ldr r3, [pc, #44] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
8000884: 2200 movs r2, #0
|
|
|
8000886: 619a str r2, [r3, #24]
|
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
|
8000888: 4b09 ldr r3, [pc, #36] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
800088a: 2200 movs r2, #0
|
|
|
800088c: 61da str r2, [r3, #28]
|
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
|
800088e: 4b08 ldr r3, [pc, #32] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
8000890: 2200 movs r2, #0
|
|
|
8000892: 621a str r2, [r3, #32]
|
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
|
8000894: 4b06 ldr r3, [pc, #24] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
8000896: 2200 movs r2, #0
|
|
|
8000898: 625a str r2, [r3, #36] ; 0x24
|
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
|
800089a: 4805 ldr r0, [pc, #20] ; (80008b0 <MX_USART1_UART_Init+0x58>)
|
|
|
800089c: f002 ffc4 bl 8003828 <HAL_UART_Init>
|
|
|
80008a0: 4603 mov r3, r0
|
|
|
80008a2: 2b00 cmp r3, #0
|
|
|
80008a4: d001 beq.n 80008aa <MX_USART1_UART_Init+0x52>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80008a6: f000 f90b bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
|
|
}
|
|
|
80008aa: bf00 nop
|
|
|
80008ac: bd80 pop {r7, pc}
|
|
|
80008ae: bf00 nop
|
|
|
80008b0: 20000110 .word 0x20000110
|
|
|
80008b4: 40013800 .word 0x40013800
|
|
|
|
|
|
080008b8 <MX_TIM1_Init>:
|
|
|
* @brief TIM1 Initialization Function
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void MX_TIM1_Init(void)
|
|
|
{
|
|
|
80008b8: b580 push {r7, lr}
|
|
|
80008ba: b09a sub sp, #104 ; 0x68
|
|
|
80008bc: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE BEGIN TIM1_Init 0 */
|
|
|
|
|
|
/* USER CODE END TIM1_Init 0 */
|
|
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
|
80008be: f107 0358 add.w r3, r7, #88 ; 0x58
|
|
|
80008c2: 2200 movs r2, #0
|
|
|
80008c4: 601a str r2, [r3, #0]
|
|
|
80008c6: 605a str r2, [r3, #4]
|
|
|
80008c8: 609a str r2, [r3, #8]
|
|
|
80008ca: 60da str r2, [r3, #12]
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
|
80008cc: f107 034c add.w r3, r7, #76 ; 0x4c
|
|
|
80008d0: 2200 movs r2, #0
|
|
|
80008d2: 601a str r2, [r3, #0]
|
|
|
80008d4: 605a str r2, [r3, #4]
|
|
|
80008d6: 609a str r2, [r3, #8]
|
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
|
80008d8: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
|
80008dc: 2200 movs r2, #0
|
|
|
80008de: 601a str r2, [r3, #0]
|
|
|
80008e0: 605a str r2, [r3, #4]
|
|
|
80008e2: 609a str r2, [r3, #8]
|
|
|
80008e4: 60da str r2, [r3, #12]
|
|
|
80008e6: 611a str r2, [r3, #16]
|
|
|
80008e8: 615a str r2, [r3, #20]
|
|
|
80008ea: 619a str r2, [r3, #24]
|
|
|
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
|
|
|
80008ec: 1d3b adds r3, r7, #4
|
|
|
80008ee: 222c movs r2, #44 ; 0x2c
|
|
|
80008f0: 2100 movs r1, #0
|
|
|
80008f2: 4618 mov r0, r3
|
|
|
80008f4: f004 fe56 bl 80055a4 <memset>
|
|
|
|
|
|
/* USER CODE BEGIN TIM1_Init 1 */
|
|
|
|
|
|
/* USER CODE END TIM1_Init 1 */
|
|
|
htim1.Instance = TIM1;
|
|
|
80008f8: 4b43 ldr r3, [pc, #268] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
80008fa: 4a44 ldr r2, [pc, #272] ; (8000a0c <MX_TIM1_Init+0x154>)
|
|
|
80008fc: 601a str r2, [r3, #0]
|
|
|
htim1.Init.Prescaler = 0;
|
|
|
80008fe: 4b42 ldr r3, [pc, #264] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000900: 2200 movs r2, #0
|
|
|
8000902: 605a str r2, [r3, #4]
|
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
|
8000904: 4b40 ldr r3, [pc, #256] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000906: 2200 movs r2, #0
|
|
|
8000908: 609a str r2, [r3, #8]
|
|
|
htim1.Init.Period = 65535;
|
|
|
800090a: 4b3f ldr r3, [pc, #252] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
800090c: f64f 72ff movw r2, #65535 ; 0xffff
|
|
|
8000910: 60da str r2, [r3, #12]
|
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
|
8000912: 4b3d ldr r3, [pc, #244] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000914: 2200 movs r2, #0
|
|
|
8000916: 611a str r2, [r3, #16]
|
|
|
htim1.Init.RepetitionCounter = 0;
|
|
|
8000918: 4b3b ldr r3, [pc, #236] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
800091a: 2200 movs r2, #0
|
|
|
800091c: 615a str r2, [r3, #20]
|
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
|
800091e: 4b3a ldr r3, [pc, #232] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000920: 2200 movs r2, #0
|
|
|
8000922: 619a str r2, [r3, #24]
|
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
|
8000924: 4838 ldr r0, [pc, #224] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000926: f002 f88f bl 8002a48 <HAL_TIM_Base_Init>
|
|
|
800092a: 4603 mov r3, r0
|
|
|
800092c: 2b00 cmp r3, #0
|
|
|
800092e: d001 beq.n 8000934 <MX_TIM1_Init+0x7c>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000930: f000 f8c6 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
|
8000934: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
|
8000938: 65bb str r3, [r7, #88] ; 0x58
|
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
|
800093a: f107 0358 add.w r3, r7, #88 ; 0x58
|
|
|
800093e: 4619 mov r1, r3
|
|
|
8000940: 4831 ldr r0, [pc, #196] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000942: f002 fa4d bl 8002de0 <HAL_TIM_ConfigClockSource>
|
|
|
8000946: 4603 mov r3, r0
|
|
|
8000948: 2b00 cmp r3, #0
|
|
|
800094a: d001 beq.n 8000950 <MX_TIM1_Init+0x98>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
800094c: f000 f8b8 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
|
|
|
8000950: 482d ldr r0, [pc, #180] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000952: f002 f8d0 bl 8002af6 <HAL_TIM_PWM_Init>
|
|
|
8000956: 4603 mov r3, r0
|
|
|
8000958: 2b00 cmp r3, #0
|
|
|
800095a: d001 beq.n 8000960 <MX_TIM1_Init+0xa8>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
800095c: f000 f8b0 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
|
8000960: 2300 movs r3, #0
|
|
|
8000962: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
|
|
|
8000964: 2300 movs r3, #0
|
|
|
8000966: 653b str r3, [r7, #80] ; 0x50
|
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
|
8000968: 2300 movs r3, #0
|
|
|
800096a: 657b str r3, [r7, #84] ; 0x54
|
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
|
800096c: f107 034c add.w r3, r7, #76 ; 0x4c
|
|
|
8000970: 4619 mov r1, r3
|
|
|
8000972: 4825 ldr r0, [pc, #148] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
8000974: f002 fe7a bl 800366c <HAL_TIMEx_MasterConfigSynchronization>
|
|
|
8000978: 4603 mov r3, r0
|
|
|
800097a: 2b00 cmp r3, #0
|
|
|
800097c: d001 beq.n 8000982 <MX_TIM1_Init+0xca>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
800097e: f000 f89f bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
|
8000982: 2360 movs r3, #96 ; 0x60
|
|
|
8000984: 633b str r3, [r7, #48] ; 0x30
|
|
|
sConfigOC.Pulse = 0;
|
|
|
8000986: 2300 movs r3, #0
|
|
|
8000988: 637b str r3, [r7, #52] ; 0x34
|
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
|
800098a: 2300 movs r3, #0
|
|
|
800098c: 63bb str r3, [r7, #56] ; 0x38
|
|
|
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
|
|
800098e: 2300 movs r3, #0
|
|
|
8000990: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
|
8000992: 2300 movs r3, #0
|
|
|
8000994: 643b str r3, [r7, #64] ; 0x40
|
|
|
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
|
|
|
8000996: 2300 movs r3, #0
|
|
|
8000998: 647b str r3, [r7, #68] ; 0x44
|
|
|
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
|
|
800099a: 2300 movs r3, #0
|
|
|
800099c: 64bb str r3, [r7, #72] ; 0x48
|
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
|
800099e: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
|
80009a2: 2200 movs r2, #0
|
|
|
80009a4: 4619 mov r1, r3
|
|
|
80009a6: 4818 ldr r0, [pc, #96] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
80009a8: f002 f906 bl 8002bb8 <HAL_TIM_PWM_ConfigChannel>
|
|
|
80009ac: 4603 mov r3, r0
|
|
|
80009ae: 2b00 cmp r3, #0
|
|
|
80009b0: d001 beq.n 80009b6 <MX_TIM1_Init+0xfe>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80009b2: f000 f885 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
|
|
|
80009b6: 2300 movs r3, #0
|
|
|
80009b8: 607b str r3, [r7, #4]
|
|
|
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
|
|
|
80009ba: 2300 movs r3, #0
|
|
|
80009bc: 60bb str r3, [r7, #8]
|
|
|
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
|
|
|
80009be: 2300 movs r3, #0
|
|
|
80009c0: 60fb str r3, [r7, #12]
|
|
|
sBreakDeadTimeConfig.DeadTime = 0;
|
|
|
80009c2: 2300 movs r3, #0
|
|
|
80009c4: 613b str r3, [r7, #16]
|
|
|
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
|
|
|
80009c6: 2300 movs r3, #0
|
|
|
80009c8: 617b str r3, [r7, #20]
|
|
|
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
|
|
|
80009ca: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
|
80009ce: 61bb str r3, [r7, #24]
|
|
|
sBreakDeadTimeConfig.BreakFilter = 0;
|
|
|
80009d0: 2300 movs r3, #0
|
|
|
80009d2: 61fb str r3, [r7, #28]
|
|
|
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
|
|
|
80009d4: 2300 movs r3, #0
|
|
|
80009d6: 623b str r3, [r7, #32]
|
|
|
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
|
|
|
80009d8: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
|
80009dc: 627b str r3, [r7, #36] ; 0x24
|
|
|
sBreakDeadTimeConfig.Break2Filter = 0;
|
|
|
80009de: 2300 movs r3, #0
|
|
|
80009e0: 62bb str r3, [r7, #40] ; 0x28
|
|
|
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
|
|
|
80009e2: 2300 movs r3, #0
|
|
|
80009e4: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
|
|
|
80009e6: 1d3b adds r3, r7, #4
|
|
|
80009e8: 4619 mov r1, r3
|
|
|
80009ea: 4807 ldr r0, [pc, #28] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
80009ec: f002 fea4 bl 8003738 <HAL_TIMEx_ConfigBreakDeadTime>
|
|
|
80009f0: 4603 mov r3, r0
|
|
|
80009f2: 2b00 cmp r3, #0
|
|
|
80009f4: d001 beq.n 80009fa <MX_TIM1_Init+0x142>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80009f6: f000 f863 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN TIM1_Init 2 */
|
|
|
|
|
|
/* USER CODE END TIM1_Init 2 */
|
|
|
HAL_TIM_MspPostInit(&htim1);
|
|
|
80009fa: 4803 ldr r0, [pc, #12] ; (8000a08 <MX_TIM1_Init+0x150>)
|
|
|
80009fc: f000 f956 bl 8000cac <HAL_TIM_MspPostInit>
|
|
|
|
|
|
}
|
|
|
8000a00: bf00 nop
|
|
|
8000a02: 3768 adds r7, #104 ; 0x68
|
|
|
8000a04: 46bd mov sp, r7
|
|
|
8000a06: bd80 pop {r7, pc}
|
|
|
8000a08: 20000198 .word 0x20000198
|
|
|
8000a0c: 40012c00 .word 0x40012c00
|
|
|
|
|
|
08000a10 <MX_GPIO_Init>:
|
|
|
* @brief GPIO Initialization Function
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void MX_GPIO_Init(void)
|
|
|
{
|
|
|
8000a10: b580 push {r7, lr}
|
|
|
8000a12: b088 sub sp, #32
|
|
|
8000a14: af00 add r7, sp, #0
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
|
8000a16: f107 030c add.w r3, r7, #12
|
|
|
8000a1a: 2200 movs r2, #0
|
|
|
8000a1c: 601a str r2, [r3, #0]
|
|
|
8000a1e: 605a str r2, [r3, #4]
|
|
|
8000a20: 609a str r2, [r3, #8]
|
|
|
8000a22: 60da str r2, [r3, #12]
|
|
|
8000a24: 611a str r2, [r3, #16]
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
|
8000a26: 4b24 ldr r3, [pc, #144] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a28: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000a2a: 4a23 ldr r2, [pc, #140] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a2c: f043 0304 orr.w r3, r3, #4
|
|
|
8000a30: 64d3 str r3, [r2, #76] ; 0x4c
|
|
|
8000a32: 4b21 ldr r3, [pc, #132] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a34: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000a36: f003 0304 and.w r3, r3, #4
|
|
|
8000a3a: 60bb str r3, [r7, #8]
|
|
|
8000a3c: 68bb ldr r3, [r7, #8]
|
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
|
8000a3e: 4b1e ldr r3, [pc, #120] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a40: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000a42: 4a1d ldr r2, [pc, #116] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a44: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
|
8000a48: 64d3 str r3, [r2, #76] ; 0x4c
|
|
|
8000a4a: 4b1b ldr r3, [pc, #108] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a4c: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000a4e: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
|
8000a52: 607b str r3, [r7, #4]
|
|
|
8000a54: 687b ldr r3, [r7, #4]
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
8000a56: 4b18 ldr r3, [pc, #96] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a58: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000a5a: 4a17 ldr r2, [pc, #92] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a5c: f043 0301 orr.w r3, r3, #1
|
|
|
8000a60: 64d3 str r3, [r2, #76] ; 0x4c
|
|
|
8000a62: 4b15 ldr r3, [pc, #84] ; (8000ab8 <MX_GPIO_Init+0xa8>)
|
|
|
8000a64: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000a66: f003 0301 and.w r3, r3, #1
|
|
|
8000a6a: 603b str r3, [r7, #0]
|
|
|
8000a6c: 683b ldr r3, [r7, #0]
|
|
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_2, GPIO_PIN_RESET);
|
|
|
8000a6e: 2200 movs r2, #0
|
|
|
8000a70: 2104 movs r1, #4
|
|
|
8000a72: 4812 ldr r0, [pc, #72] ; (8000abc <MX_GPIO_Init+0xac>)
|
|
|
8000a74: f000 fe2a bl 80016cc <HAL_GPIO_WritePin>
|
|
|
|
|
|
/*Configure GPIO pin : PC2 */
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
|
8000a78: 2304 movs r3, #4
|
|
|
8000a7a: 60fb str r3, [r7, #12]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
|
8000a7c: 2301 movs r3, #1
|
|
|
8000a7e: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000a80: 2300 movs r3, #0
|
|
|
8000a82: 617b str r3, [r7, #20]
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
|
8000a84: 2300 movs r3, #0
|
|
|
8000a86: 61bb str r3, [r7, #24]
|
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
|
8000a88: f107 030c add.w r3, r7, #12
|
|
|
8000a8c: 4619 mov r1, r3
|
|
|
8000a8e: 480b ldr r0, [pc, #44] ; (8000abc <MX_GPIO_Init+0xac>)
|
|
|
8000a90: f000 fc8a bl 80013a8 <HAL_GPIO_Init>
|
|
|
|
|
|
/*Configure GPIO pin : PA0 */
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
|
|
8000a94: 2301 movs r3, #1
|
|
|
8000a96: 60fb str r3, [r7, #12]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
|
8000a98: 2300 movs r3, #0
|
|
|
8000a9a: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000a9c: 2300 movs r3, #0
|
|
|
8000a9e: 617b str r3, [r7, #20]
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000aa0: f107 030c add.w r3, r7, #12
|
|
|
8000aa4: 4619 mov r1, r3
|
|
|
8000aa6: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
|
8000aaa: f000 fc7d bl 80013a8 <HAL_GPIO_Init>
|
|
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
|
}
|
|
|
8000aae: bf00 nop
|
|
|
8000ab0: 3720 adds r7, #32
|
|
|
8000ab2: 46bd mov sp, r7
|
|
|
8000ab4: bd80 pop {r7, pc}
|
|
|
8000ab6: bf00 nop
|
|
|
8000ab8: 40021000 .word 0x40021000
|
|
|
8000abc: 48000800 .word 0x48000800
|
|
|
|
|
|
08000ac0 <Error_Handler>:
|
|
|
/**
|
|
|
* @brief This function is executed in case of error occurrence.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void Error_Handler(void)
|
|
|
{
|
|
|
8000ac0: b480 push {r7}
|
|
|
8000ac2: af00 add r7, sp, #0
|
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
|
Can only be executed in Privileged modes.
|
|
|
*/
|
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
|
{
|
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
|
8000ac4: b672 cpsid i
|
|
|
}
|
|
|
8000ac6: bf00 nop
|
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
|
__disable_irq();
|
|
|
while (1)
|
|
|
8000ac8: e7fe b.n 8000ac8 <Error_Handler+0x8>
|
|
|
...
|
|
|
|
|
|
08000acc <HAL_MspInit>:
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
|
/**
|
|
|
* Initializes the Global MSP.
|
|
|
*/
|
|
|
void HAL_MspInit(void)
|
|
|
{
|
|
|
8000acc: b480 push {r7}
|
|
|
8000ace: b083 sub sp, #12
|
|
|
8000ad0: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
|
8000ad2: 4b0f ldr r3, [pc, #60] ; (8000b10 <HAL_MspInit+0x44>)
|
|
|
8000ad4: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8000ad6: 4a0e ldr r2, [pc, #56] ; (8000b10 <HAL_MspInit+0x44>)
|
|
|
8000ad8: f043 0301 orr.w r3, r3, #1
|
|
|
8000adc: 6613 str r3, [r2, #96] ; 0x60
|
|
|
8000ade: 4b0c ldr r3, [pc, #48] ; (8000b10 <HAL_MspInit+0x44>)
|
|
|
8000ae0: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8000ae2: f003 0301 and.w r3, r3, #1
|
|
|
8000ae6: 607b str r3, [r7, #4]
|
|
|
8000ae8: 687b ldr r3, [r7, #4]
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
8000aea: 4b09 ldr r3, [pc, #36] ; (8000b10 <HAL_MspInit+0x44>)
|
|
|
8000aec: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8000aee: 4a08 ldr r2, [pc, #32] ; (8000b10 <HAL_MspInit+0x44>)
|
|
|
8000af0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000af4: 6593 str r3, [r2, #88] ; 0x58
|
|
|
8000af6: 4b06 ldr r3, [pc, #24] ; (8000b10 <HAL_MspInit+0x44>)
|
|
|
8000af8: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8000afa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000afe: 603b str r3, [r7, #0]
|
|
|
8000b00: 683b ldr r3, [r7, #0]
|
|
|
/* System interrupt init*/
|
|
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
|
}
|
|
|
8000b02: bf00 nop
|
|
|
8000b04: 370c adds r7, #12
|
|
|
8000b06: 46bd mov sp, r7
|
|
|
8000b08: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000b0c: 4770 bx lr
|
|
|
8000b0e: bf00 nop
|
|
|
8000b10: 40021000 .word 0x40021000
|
|
|
|
|
|
08000b14 <HAL_UART_MspInit>:
|
|
|
* This function configures the hardware resources used in this example
|
|
|
* @param huart: UART handle pointer
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
|
{
|
|
|
8000b14: b580 push {r7, lr}
|
|
|
8000b16: b0a2 sub sp, #136 ; 0x88
|
|
|
8000b18: af00 add r7, sp, #0
|
|
|
8000b1a: 6078 str r0, [r7, #4]
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
|
8000b1c: f107 0374 add.w r3, r7, #116 ; 0x74
|
|
|
8000b20: 2200 movs r2, #0
|
|
|
8000b22: 601a str r2, [r3, #0]
|
|
|
8000b24: 605a str r2, [r3, #4]
|
|
|
8000b26: 609a str r2, [r3, #8]
|
|
|
8000b28: 60da str r2, [r3, #12]
|
|
|
8000b2a: 611a str r2, [r3, #16]
|
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
|
8000b2c: f107 0318 add.w r3, r7, #24
|
|
|
8000b30: 225c movs r2, #92 ; 0x5c
|
|
|
8000b32: 2100 movs r1, #0
|
|
|
8000b34: 4618 mov r0, r3
|
|
|
8000b36: f004 fd35 bl 80055a4 <memset>
|
|
|
if(huart->Instance==LPUART1)
|
|
|
8000b3a: 687b ldr r3, [r7, #4]
|
|
|
8000b3c: 681b ldr r3, [r3, #0]
|
|
|
8000b3e: 4a47 ldr r2, [pc, #284] ; (8000c5c <HAL_UART_MspInit+0x148>)
|
|
|
8000b40: 4293 cmp r3, r2
|
|
|
8000b42: d140 bne.n 8000bc6 <HAL_UART_MspInit+0xb2>
|
|
|
|
|
|
/* USER CODE END LPUART1_MspInit 0 */
|
|
|
|
|
|
/** Initializes the peripherals clock
|
|
|
*/
|
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
|
|
|
8000b44: 2320 movs r3, #32
|
|
|
8000b46: 61bb str r3, [r7, #24]
|
|
|
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
|
|
|
8000b48: 2300 movs r3, #0
|
|
|
8000b4a: 647b str r3, [r7, #68] ; 0x44
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
|
8000b4c: f107 0318 add.w r3, r7, #24
|
|
|
8000b50: 4618 mov r0, r3
|
|
|
8000b52: f001 fc6f bl 8002434 <HAL_RCCEx_PeriphCLKConfig>
|
|
|
8000b56: 4603 mov r3, r0
|
|
|
8000b58: 2b00 cmp r3, #0
|
|
|
8000b5a: d001 beq.n 8000b60 <HAL_UART_MspInit+0x4c>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000b5c: f7ff ffb0 bl 8000ac0 <Error_Handler>
|
|
|
}
|
|
|
|
|
|
/* Peripheral clock enable */
|
|
|
__HAL_RCC_LPUART1_CLK_ENABLE();
|
|
|
8000b60: 4b3f ldr r3, [pc, #252] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000b62: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
|
8000b64: 4a3e ldr r2, [pc, #248] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000b66: f043 0301 orr.w r3, r3, #1
|
|
|
8000b6a: 65d3 str r3, [r2, #92] ; 0x5c
|
|
|
8000b6c: 4b3c ldr r3, [pc, #240] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000b6e: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
|
8000b70: f003 0301 and.w r3, r3, #1
|
|
|
8000b74: 617b str r3, [r7, #20]
|
|
|
8000b76: 697b ldr r3, [r7, #20]
|
|
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
|
8000b78: 4b39 ldr r3, [pc, #228] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000b7a: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000b7c: 4a38 ldr r2, [pc, #224] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000b7e: f043 0304 orr.w r3, r3, #4
|
|
|
8000b82: 64d3 str r3, [r2, #76] ; 0x4c
|
|
|
8000b84: 4b36 ldr r3, [pc, #216] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000b86: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000b88: f003 0304 and.w r3, r3, #4
|
|
|
8000b8c: 613b str r3, [r7, #16]
|
|
|
8000b8e: 693b ldr r3, [r7, #16]
|
|
|
/**LPUART1 GPIO Configuration
|
|
|
PC0 ------> LPUART1_RX
|
|
|
PC1 ------> LPUART1_TX
|
|
|
*/
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
|
8000b90: 2303 movs r3, #3
|
|
|
8000b92: 677b str r3, [r7, #116] ; 0x74
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
8000b94: 2302 movs r3, #2
|
|
|
8000b96: 67bb str r3, [r7, #120] ; 0x78
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000b98: 2300 movs r3, #0
|
|
|
8000b9a: 67fb str r3, [r7, #124] ; 0x7c
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
|
8000b9c: 2303 movs r3, #3
|
|
|
8000b9e: f8c7 3080 str.w r3, [r7, #128] ; 0x80
|
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
|
|
|
8000ba2: 2308 movs r3, #8
|
|
|
8000ba4: f8c7 3084 str.w r3, [r7, #132] ; 0x84
|
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
|
8000ba8: f107 0374 add.w r3, r7, #116 ; 0x74
|
|
|
8000bac: 4619 mov r1, r3
|
|
|
8000bae: 482d ldr r0, [pc, #180] ; (8000c64 <HAL_UART_MspInit+0x150>)
|
|
|
8000bb0: f000 fbfa bl 80013a8 <HAL_GPIO_Init>
|
|
|
|
|
|
/* LPUART1 interrupt Init */
|
|
|
HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
|
|
|
8000bb4: 2200 movs r2, #0
|
|
|
8000bb6: 2100 movs r1, #0
|
|
|
8000bb8: 2046 movs r0, #70 ; 0x46
|
|
|
8000bba: f000 fb40 bl 800123e <HAL_NVIC_SetPriority>
|
|
|
HAL_NVIC_EnableIRQ(LPUART1_IRQn);
|
|
|
8000bbe: 2046 movs r0, #70 ; 0x46
|
|
|
8000bc0: f000 fb59 bl 8001276 <HAL_NVIC_EnableIRQ>
|
|
|
/* USER CODE BEGIN USART1_MspInit 1 */
|
|
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
|
}
|
|
|
|
|
|
}
|
|
|
8000bc4: e046 b.n 8000c54 <HAL_UART_MspInit+0x140>
|
|
|
else if(huart->Instance==USART1)
|
|
|
8000bc6: 687b ldr r3, [r7, #4]
|
|
|
8000bc8: 681b ldr r3, [r3, #0]
|
|
|
8000bca: 4a27 ldr r2, [pc, #156] ; (8000c68 <HAL_UART_MspInit+0x154>)
|
|
|
8000bcc: 4293 cmp r3, r2
|
|
|
8000bce: d141 bne.n 8000c54 <HAL_UART_MspInit+0x140>
|
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
|
8000bd0: 2301 movs r3, #1
|
|
|
8000bd2: 61bb str r3, [r7, #24]
|
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
|
8000bd4: 2300 movs r3, #0
|
|
|
8000bd6: 63bb str r3, [r7, #56] ; 0x38
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
|
8000bd8: f107 0318 add.w r3, r7, #24
|
|
|
8000bdc: 4618 mov r0, r3
|
|
|
8000bde: f001 fc29 bl 8002434 <HAL_RCCEx_PeriphCLKConfig>
|
|
|
8000be2: 4603 mov r3, r0
|
|
|
8000be4: 2b00 cmp r3, #0
|
|
|
8000be6: d001 beq.n 8000bec <HAL_UART_MspInit+0xd8>
|
|
|
Error_Handler();
|
|
|
8000be8: f7ff ff6a bl 8000ac0 <Error_Handler>
|
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
|
8000bec: 4b1c ldr r3, [pc, #112] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000bee: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8000bf0: 4a1b ldr r2, [pc, #108] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000bf2: f443 4380 orr.w r3, r3, #16384 ; 0x4000
|
|
|
8000bf6: 6613 str r3, [r2, #96] ; 0x60
|
|
|
8000bf8: 4b19 ldr r3, [pc, #100] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000bfa: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8000bfc: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
|
8000c00: 60fb str r3, [r7, #12]
|
|
|
8000c02: 68fb ldr r3, [r7, #12]
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
8000c04: 4b16 ldr r3, [pc, #88] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000c06: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000c08: 4a15 ldr r2, [pc, #84] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000c0a: f043 0301 orr.w r3, r3, #1
|
|
|
8000c0e: 64d3 str r3, [r2, #76] ; 0x4c
|
|
|
8000c10: 4b13 ldr r3, [pc, #76] ; (8000c60 <HAL_UART_MspInit+0x14c>)
|
|
|
8000c12: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000c14: f003 0301 and.w r3, r3, #1
|
|
|
8000c18: 60bb str r3, [r7, #8]
|
|
|
8000c1a: 68bb ldr r3, [r7, #8]
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|
|
8000c1c: f44f 63c0 mov.w r3, #1536 ; 0x600
|
|
|
8000c20: 677b str r3, [r7, #116] ; 0x74
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
8000c22: 2302 movs r3, #2
|
|
|
8000c24: 67bb str r3, [r7, #120] ; 0x78
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000c26: 2300 movs r3, #0
|
|
|
8000c28: 67fb str r3, [r7, #124] ; 0x7c
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
|
8000c2a: 2303 movs r3, #3
|
|
|
8000c2c: f8c7 3080 str.w r3, [r7, #128] ; 0x80
|
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
|
8000c30: 2307 movs r3, #7
|
|
|
8000c32: f8c7 3084 str.w r3, [r7, #132] ; 0x84
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000c36: f107 0374 add.w r3, r7, #116 ; 0x74
|
|
|
8000c3a: 4619 mov r1, r3
|
|
|
8000c3c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
|
8000c40: f000 fbb2 bl 80013a8 <HAL_GPIO_Init>
|
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
|
|
|
8000c44: 2200 movs r2, #0
|
|
|
8000c46: 2100 movs r1, #0
|
|
|
8000c48: 2025 movs r0, #37 ; 0x25
|
|
|
8000c4a: f000 faf8 bl 800123e <HAL_NVIC_SetPriority>
|
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|
|
8000c4e: 2025 movs r0, #37 ; 0x25
|
|
|
8000c50: f000 fb11 bl 8001276 <HAL_NVIC_EnableIRQ>
|
|
|
}
|
|
|
8000c54: bf00 nop
|
|
|
8000c56: 3788 adds r7, #136 ; 0x88
|
|
|
8000c58: 46bd mov sp, r7
|
|
|
8000c5a: bd80 pop {r7, pc}
|
|
|
8000c5c: 40008000 .word 0x40008000
|
|
|
8000c60: 40021000 .word 0x40021000
|
|
|
8000c64: 48000800 .word 0x48000800
|
|
|
8000c68: 40013800 .word 0x40013800
|
|
|
|
|
|
08000c6c <HAL_TIM_Base_MspInit>:
|
|
|
* This function configures the hardware resources used in this example
|
|
|
* @param htim_base: TIM_Base handle pointer
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
|
{
|
|
|
8000c6c: b480 push {r7}
|
|
|
8000c6e: b085 sub sp, #20
|
|
|
8000c70: af00 add r7, sp, #0
|
|
|
8000c72: 6078 str r0, [r7, #4]
|
|
|
if(htim_base->Instance==TIM1)
|
|
|
8000c74: 687b ldr r3, [r7, #4]
|
|
|
8000c76: 681b ldr r3, [r3, #0]
|
|
|
8000c78: 4a0a ldr r2, [pc, #40] ; (8000ca4 <HAL_TIM_Base_MspInit+0x38>)
|
|
|
8000c7a: 4293 cmp r3, r2
|
|
|
8000c7c: d10b bne.n 8000c96 <HAL_TIM_Base_MspInit+0x2a>
|
|
|
{
|
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
|
/* Peripheral clock enable */
|
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
|
8000c7e: 4b0a ldr r3, [pc, #40] ; (8000ca8 <HAL_TIM_Base_MspInit+0x3c>)
|
|
|
8000c80: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8000c82: 4a09 ldr r2, [pc, #36] ; (8000ca8 <HAL_TIM_Base_MspInit+0x3c>)
|
|
|
8000c84: f443 6300 orr.w r3, r3, #2048 ; 0x800
|
|
|
8000c88: 6613 str r3, [r2, #96] ; 0x60
|
|
|
8000c8a: 4b07 ldr r3, [pc, #28] ; (8000ca8 <HAL_TIM_Base_MspInit+0x3c>)
|
|
|
8000c8c: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8000c8e: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
|
8000c92: 60fb str r3, [r7, #12]
|
|
|
8000c94: 68fb ldr r3, [r7, #12]
|
|
|
/* USER CODE BEGIN TIM1_MspInit 1 */
|
|
|
|
|
|
/* USER CODE END TIM1_MspInit 1 */
|
|
|
}
|
|
|
|
|
|
}
|
|
|
8000c96: bf00 nop
|
|
|
8000c98: 3714 adds r7, #20
|
|
|
8000c9a: 46bd mov sp, r7
|
|
|
8000c9c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000ca0: 4770 bx lr
|
|
|
8000ca2: bf00 nop
|
|
|
8000ca4: 40012c00 .word 0x40012c00
|
|
|
8000ca8: 40021000 .word 0x40021000
|
|
|
|
|
|
08000cac <HAL_TIM_MspPostInit>:
|
|
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
|
{
|
|
|
8000cac: b580 push {r7, lr}
|
|
|
8000cae: b088 sub sp, #32
|
|
|
8000cb0: af00 add r7, sp, #0
|
|
|
8000cb2: 6078 str r0, [r7, #4]
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
|
8000cb4: f107 030c add.w r3, r7, #12
|
|
|
8000cb8: 2200 movs r2, #0
|
|
|
8000cba: 601a str r2, [r3, #0]
|
|
|
8000cbc: 605a str r2, [r3, #4]
|
|
|
8000cbe: 609a str r2, [r3, #8]
|
|
|
8000cc0: 60da str r2, [r3, #12]
|
|
|
8000cc2: 611a str r2, [r3, #16]
|
|
|
if(htim->Instance==TIM1)
|
|
|
8000cc4: 687b ldr r3, [r7, #4]
|
|
|
8000cc6: 681b ldr r3, [r3, #0]
|
|
|
8000cc8: 4a12 ldr r2, [pc, #72] ; (8000d14 <HAL_TIM_MspPostInit+0x68>)
|
|
|
8000cca: 4293 cmp r3, r2
|
|
|
8000ccc: d11d bne.n 8000d0a <HAL_TIM_MspPostInit+0x5e>
|
|
|
{
|
|
|
/* USER CODE BEGIN TIM1_MspPostInit 0 */
|
|
|
|
|
|
/* USER CODE END TIM1_MspPostInit 0 */
|
|
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
8000cce: 4b12 ldr r3, [pc, #72] ; (8000d18 <HAL_TIM_MspPostInit+0x6c>)
|
|
|
8000cd0: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000cd2: 4a11 ldr r2, [pc, #68] ; (8000d18 <HAL_TIM_MspPostInit+0x6c>)
|
|
|
8000cd4: f043 0301 orr.w r3, r3, #1
|
|
|
8000cd8: 64d3 str r3, [r2, #76] ; 0x4c
|
|
|
8000cda: 4b0f ldr r3, [pc, #60] ; (8000d18 <HAL_TIM_MspPostInit+0x6c>)
|
|
|
8000cdc: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8000cde: f003 0301 and.w r3, r3, #1
|
|
|
8000ce2: 60bb str r3, [r7, #8]
|
|
|
8000ce4: 68bb ldr r3, [r7, #8]
|
|
|
/**TIM1 GPIO Configuration
|
|
|
PA8 ------> TIM1_CH1
|
|
|
*/
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
|
8000ce6: f44f 7380 mov.w r3, #256 ; 0x100
|
|
|
8000cea: 60fb str r3, [r7, #12]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
8000cec: 2302 movs r3, #2
|
|
|
8000cee: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000cf0: 2300 movs r3, #0
|
|
|
8000cf2: 617b str r3, [r7, #20]
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
|
8000cf4: 2300 movs r3, #0
|
|
|
8000cf6: 61bb str r3, [r7, #24]
|
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
|
|
|
8000cf8: 2301 movs r3, #1
|
|
|
8000cfa: 61fb str r3, [r7, #28]
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000cfc: f107 030c add.w r3, r7, #12
|
|
|
8000d00: 4619 mov r1, r3
|
|
|
8000d02: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
|
8000d06: f000 fb4f bl 80013a8 <HAL_GPIO_Init>
|
|
|
/* USER CODE BEGIN TIM1_MspPostInit 1 */
|
|
|
|
|
|
/* USER CODE END TIM1_MspPostInit 1 */
|
|
|
}
|
|
|
|
|
|
}
|
|
|
8000d0a: bf00 nop
|
|
|
8000d0c: 3720 adds r7, #32
|
|
|
8000d0e: 46bd mov sp, r7
|
|
|
8000d10: bd80 pop {r7, pc}
|
|
|
8000d12: bf00 nop
|
|
|
8000d14: 40012c00 .word 0x40012c00
|
|
|
8000d18: 40021000 .word 0x40021000
|
|
|
|
|
|
08000d1c <NMI_Handler>:
|
|
|
/******************************************************************************/
|
|
|
/**
|
|
|
* @brief This function handles Non maskable interrupt.
|
|
|
*/
|
|
|
void NMI_Handler(void)
|
|
|
{
|
|
|
8000d1c: b480 push {r7}
|
|
|
8000d1e: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
while (1)
|
|
|
8000d20: e7fe b.n 8000d20 <NMI_Handler+0x4>
|
|
|
|
|
|
08000d22 <HardFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Hard fault interrupt.
|
|
|
*/
|
|
|
void HardFault_Handler(void)
|
|
|
{
|
|
|
8000d22: b480 push {r7}
|
|
|
8000d24: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000d26: e7fe b.n 8000d26 <HardFault_Handler+0x4>
|
|
|
|
|
|
08000d28 <MemManage_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Memory management fault.
|
|
|
*/
|
|
|
void MemManage_Handler(void)
|
|
|
{
|
|
|
8000d28: b480 push {r7}
|
|
|
8000d2a: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
|
while (1)
|
|
|
8000d2c: e7fe b.n 8000d2c <MemManage_Handler+0x4>
|
|
|
|
|
|
08000d2e <BusFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
|
*/
|
|
|
void BusFault_Handler(void)
|
|
|
{
|
|
|
8000d2e: b480 push {r7}
|
|
|
8000d30: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000d32: e7fe b.n 8000d32 <BusFault_Handler+0x4>
|
|
|
|
|
|
08000d34 <UsageFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
|
*/
|
|
|
void UsageFault_Handler(void)
|
|
|
{
|
|
|
8000d34: b480 push {r7}
|
|
|
8000d36: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000d38: e7fe b.n 8000d38 <UsageFault_Handler+0x4>
|
|
|
|
|
|
08000d3a <SVC_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles System service call via SWI instruction.
|
|
|
*/
|
|
|
void SVC_Handler(void)
|
|
|
{
|
|
|
8000d3a: b480 push {r7}
|
|
|
8000d3c: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
|
}
|
|
|
8000d3e: bf00 nop
|
|
|
8000d40: 46bd mov sp, r7
|
|
|
8000d42: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000d46: 4770 bx lr
|
|
|
|
|
|
08000d48 <DebugMon_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Debug monitor.
|
|
|
*/
|
|
|
void DebugMon_Handler(void)
|
|
|
{
|
|
|
8000d48: b480 push {r7}
|
|
|
8000d4a: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
|
}
|
|
|
8000d4c: bf00 nop
|
|
|
8000d4e: 46bd mov sp, r7
|
|
|
8000d50: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000d54: 4770 bx lr
|
|
|
|
|
|
08000d56 <PendSV_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Pendable request for system service.
|
|
|
*/
|
|
|
void PendSV_Handler(void)
|
|
|
{
|
|
|
8000d56: b480 push {r7}
|
|
|
8000d58: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
|
}
|
|
|
8000d5a: bf00 nop
|
|
|
8000d5c: 46bd mov sp, r7
|
|
|
8000d5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000d62: 4770 bx lr
|
|
|
|
|
|
08000d64 <SysTick_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles System tick timer.
|
|
|
*/
|
|
|
void SysTick_Handler(void)
|
|
|
{
|
|
|
8000d64: b580 push {r7, lr}
|
|
|
8000d66: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
|
HAL_IncTick();
|
|
|
8000d68: f000 f94a bl 8001000 <HAL_IncTick>
|
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
|
}
|
|
|
8000d6c: bf00 nop
|
|
|
8000d6e: bd80 pop {r7, pc}
|
|
|
|
|
|
08000d70 <USART1_IRQHandler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles USART1 global interrupt.
|
|
|
*/
|
|
|
void USART1_IRQHandler(void)
|
|
|
{
|
|
|
8000d70: b580 push {r7, lr}
|
|
|
8000d72: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END USART1_IRQn 0 */
|
|
|
HAL_UART_IRQHandler(&huart1);
|
|
|
8000d74: 4802 ldr r0, [pc, #8] ; (8000d80 <USART1_IRQHandler+0x10>)
|
|
|
8000d76: f002 fed9 bl 8003b2c <HAL_UART_IRQHandler>
|
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END USART1_IRQn 1 */
|
|
|
}
|
|
|
8000d7a: bf00 nop
|
|
|
8000d7c: bd80 pop {r7, pc}
|
|
|
8000d7e: bf00 nop
|
|
|
8000d80: 20000110 .word 0x20000110
|
|
|
|
|
|
08000d84 <LPUART1_IRQHandler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles LPUART1 global interrupt.
|
|
|
*/
|
|
|
void LPUART1_IRQHandler(void)
|
|
|
{
|
|
|
8000d84: b580 push {r7, lr}
|
|
|
8000d86: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN LPUART1_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END LPUART1_IRQn 0 */
|
|
|
HAL_UART_IRQHandler(&hlpuart1);
|
|
|
8000d88: 4802 ldr r0, [pc, #8] ; (8000d94 <LPUART1_IRQHandler+0x10>)
|
|
|
8000d8a: f002 fecf bl 8003b2c <HAL_UART_IRQHandler>
|
|
|
/* USER CODE BEGIN LPUART1_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END LPUART1_IRQn 1 */
|
|
|
}
|
|
|
8000d8e: bf00 nop
|
|
|
8000d90: bd80 pop {r7, pc}
|
|
|
8000d92: bf00 nop
|
|
|
8000d94: 20000088 .word 0x20000088
|
|
|
|
|
|
08000d98 <_read>:
|
|
|
8000d98: b580 push {r7, lr}
|
|
|
8000d9a: b086 sub sp, #24
|
|
|
8000d9c: af00 add r7, sp, #0
|
|
|
8000d9e: 60f8 str r0, [r7, #12]
|
|
|
8000da0: 60b9 str r1, [r7, #8]
|
|
|
8000da2: 607a str r2, [r7, #4]
|
|
|
8000da4: 2300 movs r3, #0
|
|
|
8000da6: 617b str r3, [r7, #20]
|
|
|
8000da8: e00a b.n 8000dc0 <_read+0x28>
|
|
|
8000daa: f3af 8000 nop.w
|
|
|
8000dae: 4601 mov r1, r0
|
|
|
8000db0: 68bb ldr r3, [r7, #8]
|
|
|
8000db2: 1c5a adds r2, r3, #1
|
|
|
8000db4: 60ba str r2, [r7, #8]
|
|
|
8000db6: b2ca uxtb r2, r1
|
|
|
8000db8: 701a strb r2, [r3, #0]
|
|
|
8000dba: 697b ldr r3, [r7, #20]
|
|
|
8000dbc: 3301 adds r3, #1
|
|
|
8000dbe: 617b str r3, [r7, #20]
|
|
|
8000dc0: 697a ldr r2, [r7, #20]
|
|
|
8000dc2: 687b ldr r3, [r7, #4]
|
|
|
8000dc4: 429a cmp r2, r3
|
|
|
8000dc6: dbf0 blt.n 8000daa <_read+0x12>
|
|
|
8000dc8: 687b ldr r3, [r7, #4]
|
|
|
8000dca: 4618 mov r0, r3
|
|
|
8000dcc: 3718 adds r7, #24
|
|
|
8000dce: 46bd mov sp, r7
|
|
|
8000dd0: bd80 pop {r7, pc}
|
|
|
|
|
|
08000dd2 <_write>:
|
|
|
8000dd2: b580 push {r7, lr}
|
|
|
8000dd4: b086 sub sp, #24
|
|
|
8000dd6: af00 add r7, sp, #0
|
|
|
8000dd8: 60f8 str r0, [r7, #12]
|
|
|
8000dda: 60b9 str r1, [r7, #8]
|
|
|
8000ddc: 607a str r2, [r7, #4]
|
|
|
8000dde: 2300 movs r3, #0
|
|
|
8000de0: 617b str r3, [r7, #20]
|
|
|
8000de2: e009 b.n 8000df8 <_write+0x26>
|
|
|
8000de4: 68bb ldr r3, [r7, #8]
|
|
|
8000de6: 1c5a adds r2, r3, #1
|
|
|
8000de8: 60ba str r2, [r7, #8]
|
|
|
8000dea: 781b ldrb r3, [r3, #0]
|
|
|
8000dec: 4618 mov r0, r3
|
|
|
8000dee: f3af 8000 nop.w
|
|
|
8000df2: 697b ldr r3, [r7, #20]
|
|
|
8000df4: 3301 adds r3, #1
|
|
|
8000df6: 617b str r3, [r7, #20]
|
|
|
8000df8: 697a ldr r2, [r7, #20]
|
|
|
8000dfa: 687b ldr r3, [r7, #4]
|
|
|
8000dfc: 429a cmp r2, r3
|
|
|
8000dfe: dbf1 blt.n 8000de4 <_write+0x12>
|
|
|
8000e00: 687b ldr r3, [r7, #4]
|
|
|
8000e02: 4618 mov r0, r3
|
|
|
8000e04: 3718 adds r7, #24
|
|
|
8000e06: 46bd mov sp, r7
|
|
|
8000e08: bd80 pop {r7, pc}
|
|
|
|
|
|
08000e0a <_close>:
|
|
|
8000e0a: b480 push {r7}
|
|
|
8000e0c: b083 sub sp, #12
|
|
|
8000e0e: af00 add r7, sp, #0
|
|
|
8000e10: 6078 str r0, [r7, #4]
|
|
|
8000e12: f04f 33ff mov.w r3, #4294967295
|
|
|
8000e16: 4618 mov r0, r3
|
|
|
8000e18: 370c adds r7, #12
|
|
|
8000e1a: 46bd mov sp, r7
|
|
|
8000e1c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000e20: 4770 bx lr
|
|
|
|
|
|
08000e22 <_fstat>:
|
|
|
8000e22: b480 push {r7}
|
|
|
8000e24: b083 sub sp, #12
|
|
|
8000e26: af00 add r7, sp, #0
|
|
|
8000e28: 6078 str r0, [r7, #4]
|
|
|
8000e2a: 6039 str r1, [r7, #0]
|
|
|
8000e2c: 683b ldr r3, [r7, #0]
|
|
|
8000e2e: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
|
8000e32: 605a str r2, [r3, #4]
|
|
|
8000e34: 2300 movs r3, #0
|
|
|
8000e36: 4618 mov r0, r3
|
|
|
8000e38: 370c adds r7, #12
|
|
|
8000e3a: 46bd mov sp, r7
|
|
|
8000e3c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000e40: 4770 bx lr
|
|
|
|
|
|
08000e42 <_isatty>:
|
|
|
8000e42: b480 push {r7}
|
|
|
8000e44: b083 sub sp, #12
|
|
|
8000e46: af00 add r7, sp, #0
|
|
|
8000e48: 6078 str r0, [r7, #4]
|
|
|
8000e4a: 2301 movs r3, #1
|
|
|
8000e4c: 4618 mov r0, r3
|
|
|
8000e4e: 370c adds r7, #12
|
|
|
8000e50: 46bd mov sp, r7
|
|
|
8000e52: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000e56: 4770 bx lr
|
|
|
|
|
|
08000e58 <_lseek>:
|
|
|
8000e58: b480 push {r7}
|
|
|
8000e5a: b085 sub sp, #20
|
|
|
8000e5c: af00 add r7, sp, #0
|
|
|
8000e5e: 60f8 str r0, [r7, #12]
|
|
|
8000e60: 60b9 str r1, [r7, #8]
|
|
|
8000e62: 607a str r2, [r7, #4]
|
|
|
8000e64: 2300 movs r3, #0
|
|
|
8000e66: 4618 mov r0, r3
|
|
|
8000e68: 3714 adds r7, #20
|
|
|
8000e6a: 46bd mov sp, r7
|
|
|
8000e6c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000e70: 4770 bx lr
|
|
|
...
|
|
|
|
|
|
08000e74 <_sbrk>:
|
|
|
8000e74: b580 push {r7, lr}
|
|
|
8000e76: b086 sub sp, #24
|
|
|
8000e78: af00 add r7, sp, #0
|
|
|
8000e7a: 6078 str r0, [r7, #4]
|
|
|
8000e7c: 4a14 ldr r2, [pc, #80] ; (8000ed0 <_sbrk+0x5c>)
|
|
|
8000e7e: 4b15 ldr r3, [pc, #84] ; (8000ed4 <_sbrk+0x60>)
|
|
|
8000e80: 1ad3 subs r3, r2, r3
|
|
|
8000e82: 617b str r3, [r7, #20]
|
|
|
8000e84: 697b ldr r3, [r7, #20]
|
|
|
8000e86: 613b str r3, [r7, #16]
|
|
|
8000e88: 4b13 ldr r3, [pc, #76] ; (8000ed8 <_sbrk+0x64>)
|
|
|
8000e8a: 681b ldr r3, [r3, #0]
|
|
|
8000e8c: 2b00 cmp r3, #0
|
|
|
8000e8e: d102 bne.n 8000e96 <_sbrk+0x22>
|
|
|
8000e90: 4b11 ldr r3, [pc, #68] ; (8000ed8 <_sbrk+0x64>)
|
|
|
8000e92: 4a12 ldr r2, [pc, #72] ; (8000edc <_sbrk+0x68>)
|
|
|
8000e94: 601a str r2, [r3, #0]
|
|
|
8000e96: 4b10 ldr r3, [pc, #64] ; (8000ed8 <_sbrk+0x64>)
|
|
|
8000e98: 681a ldr r2, [r3, #0]
|
|
|
8000e9a: 687b ldr r3, [r7, #4]
|
|
|
8000e9c: 4413 add r3, r2
|
|
|
8000e9e: 693a ldr r2, [r7, #16]
|
|
|
8000ea0: 429a cmp r2, r3
|
|
|
8000ea2: d207 bcs.n 8000eb4 <_sbrk+0x40>
|
|
|
8000ea4: f004 fbcc bl 8005640 <__errno>
|
|
|
8000ea8: 4603 mov r3, r0
|
|
|
8000eaa: 220c movs r2, #12
|
|
|
8000eac: 601a str r2, [r3, #0]
|
|
|
8000eae: f04f 33ff mov.w r3, #4294967295
|
|
|
8000eb2: e009 b.n 8000ec8 <_sbrk+0x54>
|
|
|
8000eb4: 4b08 ldr r3, [pc, #32] ; (8000ed8 <_sbrk+0x64>)
|
|
|
8000eb6: 681b ldr r3, [r3, #0]
|
|
|
8000eb8: 60fb str r3, [r7, #12]
|
|
|
8000eba: 4b07 ldr r3, [pc, #28] ; (8000ed8 <_sbrk+0x64>)
|
|
|
8000ebc: 681a ldr r2, [r3, #0]
|
|
|
8000ebe: 687b ldr r3, [r7, #4]
|
|
|
8000ec0: 4413 add r3, r2
|
|
|
8000ec2: 4a05 ldr r2, [pc, #20] ; (8000ed8 <_sbrk+0x64>)
|
|
|
8000ec4: 6013 str r3, [r2, #0]
|
|
|
8000ec6: 68fb ldr r3, [r7, #12]
|
|
|
8000ec8: 4618 mov r0, r3
|
|
|
8000eca: 3718 adds r7, #24
|
|
|
8000ecc: 46bd mov sp, r7
|
|
|
8000ece: bd80 pop {r7, pc}
|
|
|
8000ed0: 20010000 .word 0x20010000
|
|
|
8000ed4: 00000400 .word 0x00000400
|
|
|
8000ed8: 20000218 .word 0x20000218
|
|
|
8000edc: 20000370 .word 0x20000370
|
|
|
|
|
|
08000ee0 <SystemInit>:
|
|
|
* @brief Setup the microcontroller system.
|
|
|
* @retval None
|
|
|
*/
|
|
|
|
|
|
void SystemInit(void)
|
|
|
{
|
|
|
8000ee0: b480 push {r7}
|
|
|
8000ee2: af00 add r7, sp, #0
|
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
|
#endif
|
|
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
|
|
8000ee4: 4b06 ldr r3, [pc, #24] ; (8000f00 <SystemInit+0x20>)
|
|
|
8000ee6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8000eea: 4a05 ldr r2, [pc, #20] ; (8000f00 <SystemInit+0x20>)
|
|
|
8000eec: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
|
8000ef0: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
|
|
#endif
|
|
|
}
|
|
|
8000ef4: bf00 nop
|
|
|
8000ef6: 46bd mov sp, r7
|
|
|
8000ef8: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8000efc: 4770 bx lr
|
|
|
8000efe: bf00 nop
|
|
|
8000f00: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
08000f04 <Reset_Handler>:
|
|
|
8000f04: f8df d034 ldr.w sp, [pc, #52] ; 8000f3c <LoopForever+0x2>
|
|
|
8000f08: f7ff ffea bl 8000ee0 <SystemInit>
|
|
|
8000f0c: 480c ldr r0, [pc, #48] ; (8000f40 <LoopForever+0x6>)
|
|
|
8000f0e: 490d ldr r1, [pc, #52] ; (8000f44 <LoopForever+0xa>)
|
|
|
8000f10: 4a0d ldr r2, [pc, #52] ; (8000f48 <LoopForever+0xe>)
|
|
|
8000f12: 2300 movs r3, #0
|
|
|
8000f14: e002 b.n 8000f1c <LoopCopyDataInit>
|
|
|
|
|
|
08000f16 <CopyDataInit>:
|
|
|
8000f16: 58d4 ldr r4, [r2, r3]
|
|
|
8000f18: 50c4 str r4, [r0, r3]
|
|
|
8000f1a: 3304 adds r3, #4
|
|
|
|
|
|
08000f1c <LoopCopyDataInit>:
|
|
|
8000f1c: 18c4 adds r4, r0, r3
|
|
|
8000f1e: 428c cmp r4, r1
|
|
|
8000f20: d3f9 bcc.n 8000f16 <CopyDataInit>
|
|
|
8000f22: 4a0a ldr r2, [pc, #40] ; (8000f4c <LoopForever+0x12>)
|
|
|
8000f24: 4c0a ldr r4, [pc, #40] ; (8000f50 <LoopForever+0x16>)
|
|
|
8000f26: 2300 movs r3, #0
|
|
|
8000f28: e001 b.n 8000f2e <LoopFillZerobss>
|
|
|
|
|
|
08000f2a <FillZerobss>:
|
|
|
8000f2a: 6013 str r3, [r2, #0]
|
|
|
8000f2c: 3204 adds r2, #4
|
|
|
|
|
|
08000f2e <LoopFillZerobss>:
|
|
|
8000f2e: 42a2 cmp r2, r4
|
|
|
8000f30: d3fb bcc.n 8000f2a <FillZerobss>
|
|
|
8000f32: f004 fb8b bl 800564c <__libc_init_array>
|
|
|
8000f36: f7ff fbbf bl 80006b8 <main>
|
|
|
|
|
|
08000f3a <LoopForever>:
|
|
|
8000f3a: e7fe b.n 8000f3a <LoopForever>
|
|
|
8000f3c: 20010000 .word 0x20010000
|
|
|
8000f40: 20000000 .word 0x20000000
|
|
|
8000f44: 2000006c .word 0x2000006c
|
|
|
8000f48: 08005c58 .word 0x08005c58
|
|
|
8000f4c: 2000006c .word 0x2000006c
|
|
|
8000f50: 2000036c .word 0x2000036c
|
|
|
|
|
|
08000f54 <ADC1_IRQHandler>:
|
|
|
8000f54: e7fe b.n 8000f54 <ADC1_IRQHandler>
|
|
|
|
|
|
08000f56 <HAL_Init>:
|
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
|
*
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
|
{
|
|
|
8000f56: b580 push {r7, lr}
|
|
|
8000f58: b082 sub sp, #8
|
|
|
8000f5a: af00 add r7, sp, #0
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8000f5c: 2300 movs r3, #0
|
|
|
8000f5e: 71fb strb r3, [r7, #7]
|
|
|
#if (PREFETCH_ENABLE != 0)
|
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
|
|
/* Set Interrupt Group Priority */
|
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
|
8000f60: 2003 movs r0, #3
|
|
|
8000f62: f000 f961 bl 8001228 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
|
8000f66: 200f movs r0, #15
|
|
|
8000f68: f000 f80e bl 8000f88 <HAL_InitTick>
|
|
|
8000f6c: 4603 mov r3, r0
|
|
|
8000f6e: 2b00 cmp r3, #0
|
|
|
8000f70: d002 beq.n 8000f78 <HAL_Init+0x22>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8000f72: 2301 movs r3, #1
|
|
|
8000f74: 71fb strb r3, [r7, #7]
|
|
|
8000f76: e001 b.n 8000f7c <HAL_Init+0x26>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Init the low level hardware */
|
|
|
HAL_MspInit();
|
|
|
8000f78: f7ff fda8 bl 8000acc <HAL_MspInit>
|
|
|
}
|
|
|
|
|
|
/* Return function status */
|
|
|
return status;
|
|
|
8000f7c: 79fb ldrb r3, [r7, #7]
|
|
|
}
|
|
|
8000f7e: 4618 mov r0, r3
|
|
|
8000f80: 3708 adds r7, #8
|
|
|
8000f82: 46bd mov sp, r7
|
|
|
8000f84: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08000f88 <HAL_InitTick>:
|
|
|
* implementation in user file.
|
|
|
* @param TickPriority Tick interrupt priority.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
|
{
|
|
|
8000f88: b580 push {r7, lr}
|
|
|
8000f8a: b084 sub sp, #16
|
|
|
8000f8c: af00 add r7, sp, #0
|
|
|
8000f8e: 6078 str r0, [r7, #4]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8000f90: 2300 movs r3, #0
|
|
|
8000f92: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
|
8000f94: 4b17 ldr r3, [pc, #92] ; (8000ff4 <HAL_InitTick+0x6c>)
|
|
|
8000f96: 781b ldrb r3, [r3, #0]
|
|
|
8000f98: 2b00 cmp r3, #0
|
|
|
8000f9a: d023 beq.n 8000fe4 <HAL_InitTick+0x5c>
|
|
|
{
|
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
|
8000f9c: 4b16 ldr r3, [pc, #88] ; (8000ff8 <HAL_InitTick+0x70>)
|
|
|
8000f9e: 681a ldr r2, [r3, #0]
|
|
|
8000fa0: 4b14 ldr r3, [pc, #80] ; (8000ff4 <HAL_InitTick+0x6c>)
|
|
|
8000fa2: 781b ldrb r3, [r3, #0]
|
|
|
8000fa4: 4619 mov r1, r3
|
|
|
8000fa6: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
|
8000faa: fbb3 f3f1 udiv r3, r3, r1
|
|
|
8000fae: fbb2 f3f3 udiv r3, r2, r3
|
|
|
8000fb2: 4618 mov r0, r3
|
|
|
8000fb4: f000 f96d bl 8001292 <HAL_SYSTICK_Config>
|
|
|
8000fb8: 4603 mov r3, r0
|
|
|
8000fba: 2b00 cmp r3, #0
|
|
|
8000fbc: d10f bne.n 8000fde <HAL_InitTick+0x56>
|
|
|
{
|
|
|
/* Configure the SysTick IRQ priority */
|
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
|
8000fbe: 687b ldr r3, [r7, #4]
|
|
|
8000fc0: 2b0f cmp r3, #15
|
|
|
8000fc2: d809 bhi.n 8000fd8 <HAL_InitTick+0x50>
|
|
|
{
|
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
|
8000fc4: 2200 movs r2, #0
|
|
|
8000fc6: 6879 ldr r1, [r7, #4]
|
|
|
8000fc8: f04f 30ff mov.w r0, #4294967295
|
|
|
8000fcc: f000 f937 bl 800123e <HAL_NVIC_SetPriority>
|
|
|
uwTickPrio = TickPriority;
|
|
|
8000fd0: 4a0a ldr r2, [pc, #40] ; (8000ffc <HAL_InitTick+0x74>)
|
|
|
8000fd2: 687b ldr r3, [r7, #4]
|
|
|
8000fd4: 6013 str r3, [r2, #0]
|
|
|
8000fd6: e007 b.n 8000fe8 <HAL_InitTick+0x60>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8000fd8: 2301 movs r3, #1
|
|
|
8000fda: 73fb strb r3, [r7, #15]
|
|
|
8000fdc: e004 b.n 8000fe8 <HAL_InitTick+0x60>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8000fde: 2301 movs r3, #1
|
|
|
8000fe0: 73fb strb r3, [r7, #15]
|
|
|
8000fe2: e001 b.n 8000fe8 <HAL_InitTick+0x60>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8000fe4: 2301 movs r3, #1
|
|
|
8000fe6: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
|
|
|
/* Return function status */
|
|
|
return status;
|
|
|
8000fe8: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
8000fea: 4618 mov r0, r3
|
|
|
8000fec: 3710 adds r7, #16
|
|
|
8000fee: 46bd mov sp, r7
|
|
|
8000ff0: bd80 pop {r7, pc}
|
|
|
8000ff2: bf00 nop
|
|
|
8000ff4: 2000000c .word 0x2000000c
|
|
|
8000ff8: 20000004 .word 0x20000004
|
|
|
8000ffc: 20000008 .word 0x20000008
|
|
|
|
|
|
08001000 <HAL_IncTick>:
|
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
|
* implementations in user file.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_IncTick(void)
|
|
|
{
|
|
|
8001000: b480 push {r7}
|
|
|
8001002: af00 add r7, sp, #0
|
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
|
8001004: 4b06 ldr r3, [pc, #24] ; (8001020 <HAL_IncTick+0x20>)
|
|
|
8001006: 781b ldrb r3, [r3, #0]
|
|
|
8001008: 461a mov r2, r3
|
|
|
800100a: 4b06 ldr r3, [pc, #24] ; (8001024 <HAL_IncTick+0x24>)
|
|
|
800100c: 681b ldr r3, [r3, #0]
|
|
|
800100e: 4413 add r3, r2
|
|
|
8001010: 4a04 ldr r2, [pc, #16] ; (8001024 <HAL_IncTick+0x24>)
|
|
|
8001012: 6013 str r3, [r2, #0]
|
|
|
}
|
|
|
8001014: bf00 nop
|
|
|
8001016: 46bd mov sp, r7
|
|
|
8001018: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800101c: 4770 bx lr
|
|
|
800101e: bf00 nop
|
|
|
8001020: 2000000c .word 0x2000000c
|
|
|
8001024: 2000021c .word 0x2000021c
|
|
|
|
|
|
08001028 <HAL_GetTick>:
|
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
|
* implementations in user file.
|
|
|
* @retval tick value
|
|
|
*/
|
|
|
__weak uint32_t HAL_GetTick(void)
|
|
|
{
|
|
|
8001028: b480 push {r7}
|
|
|
800102a: af00 add r7, sp, #0
|
|
|
return uwTick;
|
|
|
800102c: 4b03 ldr r3, [pc, #12] ; (800103c <HAL_GetTick+0x14>)
|
|
|
800102e: 681b ldr r3, [r3, #0]
|
|
|
}
|
|
|
8001030: 4618 mov r0, r3
|
|
|
8001032: 46bd mov sp, r7
|
|
|
8001034: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8001038: 4770 bx lr
|
|
|
800103a: bf00 nop
|
|
|
800103c: 2000021c .word 0x2000021c
|
|
|
|
|
|
08001040 <HAL_Delay>:
|
|
|
* implementations in user file.
|
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
|
{
|
|
|
8001040: b580 push {r7, lr}
|
|
|
8001042: b084 sub sp, #16
|
|
|
8001044: af00 add r7, sp, #0
|
|
|
8001046: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
|
8001048: f7ff ffee bl 8001028 <HAL_GetTick>
|
|
|
800104c: 60b8 str r0, [r7, #8]
|
|
|
uint32_t wait = Delay;
|
|
|
800104e: 687b ldr r3, [r7, #4]
|
|
|
8001050: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Add a period to guaranty minimum wait */
|
|
|
if (wait < HAL_MAX_DELAY)
|
|
|
8001052: 68fb ldr r3, [r7, #12]
|
|
|
8001054: f1b3 3fff cmp.w r3, #4294967295
|
|
|
8001058: d005 beq.n 8001066 <HAL_Delay+0x26>
|
|
|
{
|
|
|
wait += (uint32_t)uwTickFreq;
|
|
|
800105a: 4b0a ldr r3, [pc, #40] ; (8001084 <HAL_Delay+0x44>)
|
|
|
800105c: 781b ldrb r3, [r3, #0]
|
|
|
800105e: 461a mov r2, r3
|
|
|
8001060: 68fb ldr r3, [r7, #12]
|
|
|
8001062: 4413 add r3, r2
|
|
|
8001064: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
|
8001066: bf00 nop
|
|
|
8001068: f7ff ffde bl 8001028 <HAL_GetTick>
|
|
|
800106c: 4602 mov r2, r0
|
|
|
800106e: 68bb ldr r3, [r7, #8]
|
|
|
8001070: 1ad3 subs r3, r2, r3
|
|
|
8001072: 68fa ldr r2, [r7, #12]
|
|
|
8001074: 429a cmp r2, r3
|
|
|
8001076: d8f7 bhi.n 8001068 <HAL_Delay+0x28>
|
|
|
{
|
|
|
}
|
|
|
}
|
|
|
8001078: bf00 nop
|
|
|
800107a: bf00 nop
|
|
|
800107c: 3710 adds r7, #16
|
|
|
800107e: 46bd mov sp, r7
|
|
|
8001080: bd80 pop {r7, pc}
|
|
|
8001082: bf00 nop
|
|
|
8001084: 2000000c .word 0x2000000c
|
|
|
|
|
|
08001088 <__NVIC_SetPriorityGrouping>:
|
|
|
In case of a conflict between priority grouping and available
|
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
|
{
|
|
|
8001088: b480 push {r7}
|
|
|
800108a: b085 sub sp, #20
|
|
|
800108c: af00 add r7, sp, #0
|
|
|
800108e: 6078 str r0, [r7, #4]
|
|
|
uint32_t reg_value;
|
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
|
8001090: 687b ldr r3, [r7, #4]
|
|
|
8001092: f003 0307 and.w r3, r3, #7
|
|
|
8001096: 60fb str r3, [r7, #12]
|
|
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
|
8001098: 4b0c ldr r3, [pc, #48] ; (80010cc <__NVIC_SetPriorityGrouping+0x44>)
|
|
|
800109a: 68db ldr r3, [r3, #12]
|
|
|
800109c: 60bb str r3, [r7, #8]
|
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
|
800109e: 68ba ldr r2, [r7, #8]
|
|
|
80010a0: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
|
80010a4: 4013 ands r3, r2
|
|
|
80010a6: 60bb str r3, [r7, #8]
|
|
|
reg_value = (reg_value |
|
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
|
80010a8: 68fb ldr r3, [r7, #12]
|
|
|
80010aa: 021a lsls r2, r3, #8
|
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
80010ac: 68bb ldr r3, [r7, #8]
|
|
|
80010ae: 4313 orrs r3, r2
|
|
|
reg_value = (reg_value |
|
|
|
80010b0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
|
80010b4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
|
80010b8: 60bb str r3, [r7, #8]
|
|
|
SCB->AIRCR = reg_value;
|
|
|
80010ba: 4a04 ldr r2, [pc, #16] ; (80010cc <__NVIC_SetPriorityGrouping+0x44>)
|
|
|
80010bc: 68bb ldr r3, [r7, #8]
|
|
|
80010be: 60d3 str r3, [r2, #12]
|
|
|
}
|
|
|
80010c0: bf00 nop
|
|
|
80010c2: 3714 adds r7, #20
|
|
|
80010c4: 46bd mov sp, r7
|
|
|
80010c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80010ca: 4770 bx lr
|
|
|
80010cc: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
080010d0 <__NVIC_GetPriorityGrouping>:
|
|
|
\brief Get Priority Grouping
|
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
|
{
|
|
|
80010d0: b480 push {r7}
|
|
|
80010d2: af00 add r7, sp, #0
|
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
|
80010d4: 4b04 ldr r3, [pc, #16] ; (80010e8 <__NVIC_GetPriorityGrouping+0x18>)
|
|
|
80010d6: 68db ldr r3, [r3, #12]
|
|
|
80010d8: 0a1b lsrs r3, r3, #8
|
|
|
80010da: f003 0307 and.w r3, r3, #7
|
|
|
}
|
|
|
80010de: 4618 mov r0, r3
|
|
|
80010e0: 46bd mov sp, r7
|
|
|
80010e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80010e6: 4770 bx lr
|
|
|
80010e8: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
080010ec <__NVIC_EnableIRQ>:
|
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
|
\param [in] IRQn Device specific interrupt number.
|
|
|
\note IRQn must not be negative.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
|
{
|
|
|
80010ec: b480 push {r7}
|
|
|
80010ee: b083 sub sp, #12
|
|
|
80010f0: af00 add r7, sp, #0
|
|
|
80010f2: 4603 mov r3, r0
|
|
|
80010f4: 71fb strb r3, [r7, #7]
|
|
|
if ((int32_t)(IRQn) >= 0)
|
|
|
80010f6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
80010fa: 2b00 cmp r3, #0
|
|
|
80010fc: db0b blt.n 8001116 <__NVIC_EnableIRQ+0x2a>
|
|
|
{
|
|
|
__COMPILER_BARRIER();
|
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
|
80010fe: 79fb ldrb r3, [r7, #7]
|
|
|
8001100: f003 021f and.w r2, r3, #31
|
|
|
8001104: 4907 ldr r1, [pc, #28] ; (8001124 <__NVIC_EnableIRQ+0x38>)
|
|
|
8001106: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
800110a: 095b lsrs r3, r3, #5
|
|
|
800110c: 2001 movs r0, #1
|
|
|
800110e: fa00 f202 lsl.w r2, r0, r2
|
|
|
8001112: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
__COMPILER_BARRIER();
|
|
|
}
|
|
|
}
|
|
|
8001116: bf00 nop
|
|
|
8001118: 370c adds r7, #12
|
|
|
800111a: 46bd mov sp, r7
|
|
|
800111c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8001120: 4770 bx lr
|
|
|
8001122: bf00 nop
|
|
|
8001124: e000e100 .word 0xe000e100
|
|
|
|
|
|
08001128 <__NVIC_SetPriority>:
|
|
|
\param [in] IRQn Interrupt number.
|
|
|
\param [in] priority Priority to set.
|
|
|
\note The priority cannot be set for every processor exception.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
|
{
|
|
|
8001128: b480 push {r7}
|
|
|
800112a: b083 sub sp, #12
|
|
|
800112c: af00 add r7, sp, #0
|
|
|
800112e: 4603 mov r3, r0
|
|
|
8001130: 6039 str r1, [r7, #0]
|
|
|
8001132: 71fb strb r3, [r7, #7]
|
|
|
if ((int32_t)(IRQn) >= 0)
|
|
|
8001134: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
8001138: 2b00 cmp r3, #0
|
|
|
800113a: db0a blt.n 8001152 <__NVIC_SetPriority+0x2a>
|
|
|
{
|
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
800113c: 683b ldr r3, [r7, #0]
|
|
|
800113e: b2da uxtb r2, r3
|
|
|
8001140: 490c ldr r1, [pc, #48] ; (8001174 <__NVIC_SetPriority+0x4c>)
|
|
|
8001142: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
8001146: 0112 lsls r2, r2, #4
|
|
|
8001148: b2d2 uxtb r2, r2
|
|
|
800114a: 440b add r3, r1
|
|
|
800114c: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
}
|
|
|
}
|
|
|
8001150: e00a b.n 8001168 <__NVIC_SetPriority+0x40>
|
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
8001152: 683b ldr r3, [r7, #0]
|
|
|
8001154: b2da uxtb r2, r3
|
|
|
8001156: 4908 ldr r1, [pc, #32] ; (8001178 <__NVIC_SetPriority+0x50>)
|
|
|
8001158: 79fb ldrb r3, [r7, #7]
|
|
|
800115a: f003 030f and.w r3, r3, #15
|
|
|
800115e: 3b04 subs r3, #4
|
|
|
8001160: 0112 lsls r2, r2, #4
|
|
|
8001162: b2d2 uxtb r2, r2
|
|
|
8001164: 440b add r3, r1
|
|
|
8001166: 761a strb r2, [r3, #24]
|
|
|
}
|
|
|
8001168: bf00 nop
|
|
|
800116a: 370c adds r7, #12
|
|
|
800116c: 46bd mov sp, r7
|
|
|
800116e: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8001172: 4770 bx lr
|
|
|
8001174: e000e100 .word 0xe000e100
|
|
|
8001178: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
0800117c <NVIC_EncodePriority>:
|
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
|
{
|
|
|
800117c: b480 push {r7}
|
|
|
800117e: b089 sub sp, #36 ; 0x24
|
|
|
8001180: af00 add r7, sp, #0
|
|
|
8001182: 60f8 str r0, [r7, #12]
|
|
|
8001184: 60b9 str r1, [r7, #8]
|
|
|
8001186: 607a str r2, [r7, #4]
|
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
|
8001188: 68fb ldr r3, [r7, #12]
|
|
|
800118a: f003 0307 and.w r3, r3, #7
|
|
|
800118e: 61fb str r3, [r7, #28]
|
|
|
uint32_t PreemptPriorityBits;
|
|
|
uint32_t SubPriorityBits;
|
|
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
|
8001190: 69fb ldr r3, [r7, #28]
|
|
|
8001192: f1c3 0307 rsb r3, r3, #7
|
|
|
8001196: 2b04 cmp r3, #4
|
|
|
8001198: bf28 it cs
|
|
|
800119a: 2304 movcs r3, #4
|
|
|
800119c: 61bb str r3, [r7, #24]
|
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
|
800119e: 69fb ldr r3, [r7, #28]
|
|
|
80011a0: 3304 adds r3, #4
|
|
|
80011a2: 2b06 cmp r3, #6
|
|
|
80011a4: d902 bls.n 80011ac <NVIC_EncodePriority+0x30>
|
|
|
80011a6: 69fb ldr r3, [r7, #28]
|
|
|
80011a8: 3b03 subs r3, #3
|
|
|
80011aa: e000 b.n 80011ae <NVIC_EncodePriority+0x32>
|
|
|
80011ac: 2300 movs r3, #0
|
|
|
80011ae: 617b str r3, [r7, #20]
|
|
|
|
|
|
return (
|
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
|
80011b0: f04f 32ff mov.w r2, #4294967295
|
|
|
80011b4: 69bb ldr r3, [r7, #24]
|
|
|
80011b6: fa02 f303 lsl.w r3, r2, r3
|
|
|
80011ba: 43da mvns r2, r3
|
|
|
80011bc: 68bb ldr r3, [r7, #8]
|
|
|
80011be: 401a ands r2, r3
|
|
|
80011c0: 697b ldr r3, [r7, #20]
|
|
|
80011c2: 409a lsls r2, r3
|
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
|
80011c4: f04f 31ff mov.w r1, #4294967295
|
|
|
80011c8: 697b ldr r3, [r7, #20]
|
|
|
80011ca: fa01 f303 lsl.w r3, r1, r3
|
|
|
80011ce: 43d9 mvns r1, r3
|
|
|
80011d0: 687b ldr r3, [r7, #4]
|
|
|
80011d2: 400b ands r3, r1
|
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
|
80011d4: 4313 orrs r3, r2
|
|
|
);
|
|
|
}
|
|
|
80011d6: 4618 mov r0, r3
|
|
|
80011d8: 3724 adds r7, #36 ; 0x24
|
|
|
80011da: 46bd mov sp, r7
|
|
|
80011dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80011e0: 4770 bx lr
|
|
|
...
|
|
|
|
|
|
080011e4 <SysTick_Config>:
|
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
|
must contain a vendor-specific implementation of this function.
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
|
{
|
|
|
80011e4: b580 push {r7, lr}
|
|
|
80011e6: b082 sub sp, #8
|
|
|
80011e8: af00 add r7, sp, #0
|
|
|
80011ea: 6078 str r0, [r7, #4]
|
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
|
80011ec: 687b ldr r3, [r7, #4]
|
|
|
80011ee: 3b01 subs r3, #1
|
|
|
80011f0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
|
80011f4: d301 bcc.n 80011fa <SysTick_Config+0x16>
|
|
|
{
|
|
|
return (1UL); /* Reload value impossible */
|
|
|
80011f6: 2301 movs r3, #1
|
|
|
80011f8: e00f b.n 800121a <SysTick_Config+0x36>
|
|
|
}
|
|
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
|
80011fa: 4a0a ldr r2, [pc, #40] ; (8001224 <SysTick_Config+0x40>)
|
|
|
80011fc: 687b ldr r3, [r7, #4]
|
|
|
80011fe: 3b01 subs r3, #1
|
|
|
8001200: 6053 str r3, [r2, #4]
|
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
|
8001202: 210f movs r1, #15
|
|
|
8001204: f04f 30ff mov.w r0, #4294967295
|
|
|
8001208: f7ff ff8e bl 8001128 <__NVIC_SetPriority>
|
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
|
800120c: 4b05 ldr r3, [pc, #20] ; (8001224 <SysTick_Config+0x40>)
|
|
|
800120e: 2200 movs r2, #0
|
|
|
8001210: 609a str r2, [r3, #8]
|
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
|
8001212: 4b04 ldr r3, [pc, #16] ; (8001224 <SysTick_Config+0x40>)
|
|
|
8001214: 2207 movs r2, #7
|
|
|
8001216: 601a str r2, [r3, #0]
|
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
|
return (0UL); /* Function successful */
|
|
|
8001218: 2300 movs r3, #0
|
|
|
}
|
|
|
800121a: 4618 mov r0, r3
|
|
|
800121c: 3708 adds r7, #8
|
|
|
800121e: 46bd mov sp, r7
|
|
|
8001220: bd80 pop {r7, pc}
|
|
|
8001222: bf00 nop
|
|
|
8001224: e000e010 .word 0xe000e010
|
|
|
|
|
|
08001228 <HAL_NVIC_SetPriorityGrouping>:
|
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
|
{
|
|
|
8001228: b580 push {r7, lr}
|
|
|
800122a: b082 sub sp, #8
|
|
|
800122c: af00 add r7, sp, #0
|
|
|
800122e: 6078 str r0, [r7, #4]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
|
8001230: 6878 ldr r0, [r7, #4]
|
|
|
8001232: f7ff ff29 bl 8001088 <__NVIC_SetPriorityGrouping>
|
|
|
}
|
|
|
8001236: bf00 nop
|
|
|
8001238: 3708 adds r7, #8
|
|
|
800123a: 46bd mov sp, r7
|
|
|
800123c: bd80 pop {r7, pc}
|
|
|
|
|
|
0800123e <HAL_NVIC_SetPriority>:
|
|
|
* This parameter can be a value between 0 and 15
|
|
|
* A lower priority value indicates a higher priority.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
|
{
|
|
|
800123e: b580 push {r7, lr}
|
|
|
8001240: b086 sub sp, #24
|
|
|
8001242: af00 add r7, sp, #0
|
|
|
8001244: 4603 mov r3, r0
|
|
|
8001246: 60b9 str r1, [r7, #8]
|
|
|
8001248: 607a str r2, [r7, #4]
|
|
|
800124a: 73fb strb r3, [r7, #15]
|
|
|
uint32_t prioritygroup = 0x00;
|
|
|
800124c: 2300 movs r3, #0
|
|
|
800124e: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
|
8001250: f7ff ff3e bl 80010d0 <__NVIC_GetPriorityGrouping>
|
|
|
8001254: 6178 str r0, [r7, #20]
|
|
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
|
8001256: 687a ldr r2, [r7, #4]
|
|
|
8001258: 68b9 ldr r1, [r7, #8]
|
|
|
800125a: 6978 ldr r0, [r7, #20]
|
|
|
800125c: f7ff ff8e bl 800117c <NVIC_EncodePriority>
|
|
|
8001260: 4602 mov r2, r0
|
|
|
8001262: f997 300f ldrsb.w r3, [r7, #15]
|
|
|
8001266: 4611 mov r1, r2
|
|
|
8001268: 4618 mov r0, r3
|
|
|
800126a: f7ff ff5d bl 8001128 <__NVIC_SetPriority>
|
|
|
}
|
|
|
800126e: bf00 nop
|
|
|
8001270: 3718 adds r7, #24
|
|
|
8001272: 46bd mov sp, r7
|
|
|
8001274: bd80 pop {r7, pc}
|
|
|
|
|
|
08001276 <HAL_NVIC_EnableIRQ>:
|
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
|
{
|
|
|
8001276: b580 push {r7, lr}
|
|
|
8001278: b082 sub sp, #8
|
|
|
800127a: af00 add r7, sp, #0
|
|
|
800127c: 4603 mov r3, r0
|
|
|
800127e: 71fb strb r3, [r7, #7]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
|
|
/* Enable interrupt */
|
|
|
NVIC_EnableIRQ(IRQn);
|
|
|
8001280: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
8001284: 4618 mov r0, r3
|
|
|
8001286: f7ff ff31 bl 80010ec <__NVIC_EnableIRQ>
|
|
|
}
|
|
|
800128a: bf00 nop
|
|
|
800128c: 3708 adds r7, #8
|
|
|
800128e: 46bd mov sp, r7
|
|
|
8001290: bd80 pop {r7, pc}
|
|
|
|
|
|
08001292 <HAL_SYSTICK_Config>:
|
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
|
* @retval status: - 0 Function succeeded.
|
|
|
* - 1 Function failed.
|
|
|
*/
|
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
|
{
|
|
|
8001292: b580 push {r7, lr}
|
|
|
8001294: b082 sub sp, #8
|
|
|
8001296: af00 add r7, sp, #0
|
|
|
8001298: 6078 str r0, [r7, #4]
|
|
|
return SysTick_Config(TicksNumb);
|
|
|
800129a: 6878 ldr r0, [r7, #4]
|
|
|
800129c: f7ff ffa2 bl 80011e4 <SysTick_Config>
|
|
|
80012a0: 4603 mov r3, r0
|
|
|
}
|
|
|
80012a2: 4618 mov r0, r3
|
|
|
80012a4: 3708 adds r7, #8
|
|
|
80012a6: 46bd mov sp, r7
|
|
|
80012a8: bd80 pop {r7, pc}
|
|
|
|
|
|
080012aa <HAL_DMA_Abort>:
|
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
|
* the configuration information for the specified DMA Channel.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
|
{
|
|
|
80012aa: b480 push {r7}
|
|
|
80012ac: b085 sub sp, #20
|
|
|
80012ae: af00 add r7, sp, #0
|
|
|
80012b0: 6078 str r0, [r7, #4]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
80012b2: 2300 movs r3, #0
|
|
|
80012b4: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
/* Check the DMA peripheral state */
|
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
|
80012b6: 687b ldr r3, [r7, #4]
|
|
|
80012b8: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
|
|
|
80012bc: b2db uxtb r3, r3
|
|
|
80012be: 2b02 cmp r3, #2
|
|
|
80012c0: d008 beq.n 80012d4 <HAL_DMA_Abort+0x2a>
|
|
|
{
|
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
|
80012c2: 687b ldr r3, [r7, #4]
|
|
|
80012c4: 2204 movs r2, #4
|
|
|
80012c6: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(hdma);
|
|
|
80012c8: 687b ldr r3, [r7, #4]
|
|
|
80012ca: 2200 movs r2, #0
|
|
|
80012cc: f883 2024 strb.w r2, [r3, #36] ; 0x24
|
|
|
|
|
|
return HAL_ERROR;
|
|
|
80012d0: 2301 movs r3, #1
|
|
|
80012d2: e022 b.n 800131a <HAL_DMA_Abort+0x70>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable DMA IT */
|
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
|
80012d4: 687b ldr r3, [r7, #4]
|
|
|
80012d6: 681b ldr r3, [r3, #0]
|
|
|
80012d8: 681a ldr r2, [r3, #0]
|
|
|
80012da: 687b ldr r3, [r7, #4]
|
|
|
80012dc: 681b ldr r3, [r3, #0]
|
|
|
80012de: f022 020e bic.w r2, r2, #14
|
|
|
80012e2: 601a str r2, [r3, #0]
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
|
#endif /* DMAMUX1 */
|
|
|
|
|
|
/* Disable the channel */
|
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
80012e4: 687b ldr r3, [r7, #4]
|
|
|
80012e6: 681b ldr r3, [r3, #0]
|
|
|
80012e8: 681a ldr r2, [r3, #0]
|
|
|
80012ea: 687b ldr r3, [r7, #4]
|
|
|
80012ec: 681b ldr r3, [r3, #0]
|
|
|
80012ee: f022 0201 bic.w r2, r2, #1
|
|
|
80012f2: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Clear all flags */
|
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
|
80012f4: 687b ldr r3, [r7, #4]
|
|
|
80012f6: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
|
80012f8: f003 021c and.w r2, r3, #28
|
|
|
80012fc: 687b ldr r3, [r7, #4]
|
|
|
80012fe: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
|
8001300: 2101 movs r1, #1
|
|
|
8001302: fa01 f202 lsl.w r2, r1, r2
|
|
|
8001306: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
|
|
|
#endif /* DMAMUX1 */
|
|
|
|
|
|
/* Change the DMA state */
|
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
8001308: 687b ldr r3, [r7, #4]
|
|
|
800130a: 2201 movs r2, #1
|
|
|
800130c: f883 2025 strb.w r2, [r3, #37] ; 0x25
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(hdma);
|
|
|
8001310: 687b ldr r3, [r7, #4]
|
|
|
8001312: 2200 movs r2, #0
|
|
|
8001314: f883 2024 strb.w r2, [r3, #36] ; 0x24
|
|
|
|
|
|
return status;
|
|
|
8001318: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
}
|
|
|
800131a: 4618 mov r0, r3
|
|
|
800131c: 3714 adds r7, #20
|
|
|
800131e: 46bd mov sp, r7
|
|
|
8001320: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8001324: 4770 bx lr
|
|
|
|
|
|
08001326 <HAL_DMA_Abort_IT>:
|
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
|
* the configuration information for the specified DMA Channel.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
|
{
|
|
|
8001326: b580 push {r7, lr}
|
|
|
8001328: b084 sub sp, #16
|
|
|
800132a: af00 add r7, sp, #0
|
|
|
800132c: 6078 str r0, [r7, #4]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
800132e: 2300 movs r3, #0
|
|
|
8001330: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
|
8001332: 687b ldr r3, [r7, #4]
|
|
|
8001334: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
|
|
|
8001338: b2db uxtb r3, r3
|
|
|
800133a: 2b02 cmp r3, #2
|
|
|
800133c: d005 beq.n 800134a <HAL_DMA_Abort_IT+0x24>
|
|
|
{
|
|
|
/* no transfer ongoing */
|
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
|
800133e: 687b ldr r3, [r7, #4]
|
|
|
8001340: 2204 movs r2, #4
|
|
|
8001342: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
status = HAL_ERROR;
|
|
|
8001344: 2301 movs r3, #1
|
|
|
8001346: 73fb strb r3, [r7, #15]
|
|
|
8001348: e029 b.n 800139e <HAL_DMA_Abort_IT+0x78>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable DMA IT */
|
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
|
800134a: 687b ldr r3, [r7, #4]
|
|
|
800134c: 681b ldr r3, [r3, #0]
|
|
|
800134e: 681a ldr r2, [r3, #0]
|
|
|
8001350: 687b ldr r3, [r7, #4]
|
|
|
8001352: 681b ldr r3, [r3, #0]
|
|
|
8001354: f022 020e bic.w r2, r2, #14
|
|
|
8001358: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Disable the channel */
|
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
800135a: 687b ldr r3, [r7, #4]
|
|
|
800135c: 681b ldr r3, [r3, #0]
|
|
|
800135e: 681a ldr r2, [r3, #0]
|
|
|
8001360: 687b ldr r3, [r7, #4]
|
|
|
8001362: 681b ldr r3, [r3, #0]
|
|
|
8001364: f022 0201 bic.w r2, r2, #1
|
|
|
8001368: 601a str r2, [r3, #0]
|
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
|
}
|
|
|
|
|
|
#else
|
|
|
/* Clear all flags */
|
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
|
800136a: 687b ldr r3, [r7, #4]
|
|
|
800136c: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
|
800136e: f003 021c and.w r2, r3, #28
|
|
|
8001372: 687b ldr r3, [r7, #4]
|
|
|
8001374: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
|
8001376: 2101 movs r1, #1
|
|
|
8001378: fa01 f202 lsl.w r2, r1, r2
|
|
|
800137c: 605a str r2, [r3, #4]
|
|
|
#endif /* DMAMUX1 */
|
|
|
|
|
|
/* Change the DMA state */
|
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
800137e: 687b ldr r3, [r7, #4]
|
|
|
8001380: 2201 movs r2, #1
|
|
|
8001382: f883 2025 strb.w r2, [r3, #37] ; 0x25
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(hdma);
|
|
|
8001386: 687b ldr r3, [r7, #4]
|
|
|
8001388: 2200 movs r2, #0
|
|
|
800138a: f883 2024 strb.w r2, [r3, #36] ; 0x24
|
|
|
|
|
|
/* Call User Abort callback */
|
|
|
if (hdma->XferAbortCallback != NULL)
|
|
|
800138e: 687b ldr r3, [r7, #4]
|
|
|
8001390: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
|
8001392: 2b00 cmp r3, #0
|
|
|
8001394: d003 beq.n 800139e <HAL_DMA_Abort_IT+0x78>
|
|
|
{
|
|
|
hdma->XferAbortCallback(hdma);
|
|
|
8001396: 687b ldr r3, [r7, #4]
|
|
|
8001398: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
|
800139a: 6878 ldr r0, [r7, #4]
|
|
|
800139c: 4798 blx r3
|
|
|
}
|
|
|
}
|
|
|
return status;
|
|
|
800139e: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
80013a0: 4618 mov r0, r3
|
|
|
80013a2: 3710 adds r7, #16
|
|
|
80013a4: 46bd mov sp, r7
|
|
|
80013a6: bd80 pop {r7, pc}
|
|
|
|
|
|
080013a8 <HAL_GPIO_Init>:
|
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
|
* the configuration information for the specified GPIO peripheral.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
|
{
|
|
|
80013a8: b480 push {r7}
|
|
|
80013aa: b087 sub sp, #28
|
|
|
80013ac: af00 add r7, sp, #0
|
|
|
80013ae: 6078 str r0, [r7, #4]
|
|
|
80013b0: 6039 str r1, [r7, #0]
|
|
|
uint32_t position = 0x00u;
|
|
|
80013b2: 2300 movs r3, #0
|
|
|
80013b4: 617b str r3, [r7, #20]
|
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
|
|
/* Configure the port pins */
|
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
|
80013b6: e154 b.n 8001662 <HAL_GPIO_Init+0x2ba>
|
|
|
{
|
|
|
/* Get current io position */
|
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
|
80013b8: 683b ldr r3, [r7, #0]
|
|
|
80013ba: 681a ldr r2, [r3, #0]
|
|
|
80013bc: 2101 movs r1, #1
|
|
|
80013be: 697b ldr r3, [r7, #20]
|
|
|
80013c0: fa01 f303 lsl.w r3, r1, r3
|
|
|
80013c4: 4013 ands r3, r2
|
|
|
80013c6: 60fb str r3, [r7, #12]
|
|
|
|
|
|
if (iocurrent != 0x00u)
|
|
|
80013c8: 68fb ldr r3, [r7, #12]
|
|
|
80013ca: 2b00 cmp r3, #0
|
|
|
80013cc: f000 8146 beq.w 800165c <HAL_GPIO_Init+0x2b4>
|
|
|
{
|
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
|
/* In case of Output or Alternate function mode selection */
|
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
|
80013d0: 683b ldr r3, [r7, #0]
|
|
|
80013d2: 685b ldr r3, [r3, #4]
|
|
|
80013d4: f003 0303 and.w r3, r3, #3
|
|
|
80013d8: 2b01 cmp r3, #1
|
|
|
80013da: d005 beq.n 80013e8 <HAL_GPIO_Init+0x40>
|
|
|
80013dc: 683b ldr r3, [r7, #0]
|
|
|
80013de: 685b ldr r3, [r3, #4]
|
|
|
80013e0: f003 0303 and.w r3, r3, #3
|
|
|
80013e4: 2b02 cmp r3, #2
|
|
|
80013e6: d130 bne.n 800144a <HAL_GPIO_Init+0xa2>
|
|
|
{
|
|
|
/* Check the Speed parameter */
|
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
|
|
/* Configure the IO Speed */
|
|
|
temp = GPIOx->OSPEEDR;
|
|
|
80013e8: 687b ldr r3, [r7, #4]
|
|
|
80013ea: 689b ldr r3, [r3, #8]
|
|
|
80013ec: 613b str r3, [r7, #16]
|
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
|
80013ee: 697b ldr r3, [r7, #20]
|
|
|
80013f0: 005b lsls r3, r3, #1
|
|
|
80013f2: 2203 movs r2, #3
|
|
|
80013f4: fa02 f303 lsl.w r3, r2, r3
|
|
|
80013f8: 43db mvns r3, r3
|
|
|
80013fa: 693a ldr r2, [r7, #16]
|
|
|
80013fc: 4013 ands r3, r2
|
|
|
80013fe: 613b str r3, [r7, #16]
|
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
|
8001400: 683b ldr r3, [r7, #0]
|
|
|
8001402: 68da ldr r2, [r3, #12]
|
|
|
8001404: 697b ldr r3, [r7, #20]
|
|
|
8001406: 005b lsls r3, r3, #1
|
|
|
8001408: fa02 f303 lsl.w r3, r2, r3
|
|
|
800140c: 693a ldr r2, [r7, #16]
|
|
|
800140e: 4313 orrs r3, r2
|
|
|
8001410: 613b str r3, [r7, #16]
|
|
|
GPIOx->OSPEEDR = temp;
|
|
|
8001412: 687b ldr r3, [r7, #4]
|
|
|
8001414: 693a ldr r2, [r7, #16]
|
|
|
8001416: 609a str r2, [r3, #8]
|
|
|
|
|
|
/* Configure the IO Output Type */
|
|
|
temp = GPIOx->OTYPER;
|
|
|
8001418: 687b ldr r3, [r7, #4]
|
|
|
800141a: 685b ldr r3, [r3, #4]
|
|
|
800141c: 613b str r3, [r7, #16]
|
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
|
800141e: 2201 movs r2, #1
|
|
|
8001420: 697b ldr r3, [r7, #20]
|
|
|
8001422: fa02 f303 lsl.w r3, r2, r3
|
|
|
8001426: 43db mvns r3, r3
|
|
|
8001428: 693a ldr r2, [r7, #16]
|
|
|
800142a: 4013 ands r3, r2
|
|
|
800142c: 613b str r3, [r7, #16]
|
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
|
800142e: 683b ldr r3, [r7, #0]
|
|
|
8001430: 685b ldr r3, [r3, #4]
|
|
|
8001432: 091b lsrs r3, r3, #4
|
|
|
8001434: f003 0201 and.w r2, r3, #1
|
|
|
8001438: 697b ldr r3, [r7, #20]
|
|
|
800143a: fa02 f303 lsl.w r3, r2, r3
|
|
|
800143e: 693a ldr r2, [r7, #16]
|
|
|
8001440: 4313 orrs r3, r2
|
|
|
8001442: 613b str r3, [r7, #16]
|
|
|
GPIOx->OTYPER = temp;
|
|
|
8001444: 687b ldr r3, [r7, #4]
|
|
|
8001446: 693a ldr r2, [r7, #16]
|
|
|
8001448: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
|
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
|
800144a: 683b ldr r3, [r7, #0]
|
|
|
800144c: 685b ldr r3, [r3, #4]
|
|
|
800144e: f003 0303 and.w r3, r3, #3
|
|
|
8001452: 2b03 cmp r3, #3
|
|
|
8001454: d017 beq.n 8001486 <HAL_GPIO_Init+0xde>
|
|
|
{
|
|
|
/* Check the Pull parameter */
|
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
|
|
temp = GPIOx->PUPDR;
|
|
|
8001456: 687b ldr r3, [r7, #4]
|
|
|
8001458: 68db ldr r3, [r3, #12]
|
|
|
800145a: 613b str r3, [r7, #16]
|
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
|
800145c: 697b ldr r3, [r7, #20]
|
|
|
800145e: 005b lsls r3, r3, #1
|
|
|
8001460: 2203 movs r2, #3
|
|
|
8001462: fa02 f303 lsl.w r3, r2, r3
|
|
|
8001466: 43db mvns r3, r3
|
|
|
8001468: 693a ldr r2, [r7, #16]
|
|
|
800146a: 4013 ands r3, r2
|
|
|
800146c: 613b str r3, [r7, #16]
|
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
|
800146e: 683b ldr r3, [r7, #0]
|
|
|
8001470: 689a ldr r2, [r3, #8]
|
|
|
8001472: 697b ldr r3, [r7, #20]
|
|
|
8001474: 005b lsls r3, r3, #1
|
|
|
8001476: fa02 f303 lsl.w r3, r2, r3
|
|
|
800147a: 693a ldr r2, [r7, #16]
|
|
|
800147c: 4313 orrs r3, r2
|
|
|
800147e: 613b str r3, [r7, #16]
|
|
|
GPIOx->PUPDR = temp;
|
|
|
8001480: 687b ldr r3, [r7, #4]
|
|
|
8001482: 693a ldr r2, [r7, #16]
|
|
|
8001484: 60da str r2, [r3, #12]
|
|
|
}
|
|
|
|
|
|
/* In case of Alternate function mode selection */
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
|
8001486: 683b ldr r3, [r7, #0]
|
|
|
8001488: 685b ldr r3, [r3, #4]
|
|
|
800148a: f003 0303 and.w r3, r3, #3
|
|
|
800148e: 2b02 cmp r3, #2
|
|
|
8001490: d123 bne.n 80014da <HAL_GPIO_Init+0x132>
|
|
|
/* Check the Alternate function parameters */
|
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
|
8001492: 697b ldr r3, [r7, #20]
|
|
|
8001494: 08da lsrs r2, r3, #3
|
|
|
8001496: 687b ldr r3, [r7, #4]
|
|
|
8001498: 3208 adds r2, #8
|
|
|
800149a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
|
800149e: 613b str r3, [r7, #16]
|
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
|
80014a0: 697b ldr r3, [r7, #20]
|
|
|
80014a2: f003 0307 and.w r3, r3, #7
|
|
|
80014a6: 009b lsls r3, r3, #2
|
|
|
80014a8: 220f movs r2, #15
|
|
|
80014aa: fa02 f303 lsl.w r3, r2, r3
|
|
|
80014ae: 43db mvns r3, r3
|
|
|
80014b0: 693a ldr r2, [r7, #16]
|
|
|
80014b2: 4013 ands r3, r2
|
|
|
80014b4: 613b str r3, [r7, #16]
|
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
|
80014b6: 683b ldr r3, [r7, #0]
|
|
|
80014b8: 691a ldr r2, [r3, #16]
|
|
|
80014ba: 697b ldr r3, [r7, #20]
|
|
|
80014bc: f003 0307 and.w r3, r3, #7
|
|
|
80014c0: 009b lsls r3, r3, #2
|
|
|
80014c2: fa02 f303 lsl.w r3, r2, r3
|
|
|
80014c6: 693a ldr r2, [r7, #16]
|
|
|
80014c8: 4313 orrs r3, r2
|
|
|
80014ca: 613b str r3, [r7, #16]
|
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
|
80014cc: 697b ldr r3, [r7, #20]
|
|
|
80014ce: 08da lsrs r2, r3, #3
|
|
|
80014d0: 687b ldr r3, [r7, #4]
|
|
|
80014d2: 3208 adds r2, #8
|
|
|
80014d4: 6939 ldr r1, [r7, #16]
|
|
|
80014d6: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
}
|
|
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
|
temp = GPIOx->MODER;
|
|
|
80014da: 687b ldr r3, [r7, #4]
|
|
|
80014dc: 681b ldr r3, [r3, #0]
|
|
|
80014de: 613b str r3, [r7, #16]
|
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
|
80014e0: 697b ldr r3, [r7, #20]
|
|
|
80014e2: 005b lsls r3, r3, #1
|
|
|
80014e4: 2203 movs r2, #3
|
|
|
80014e6: fa02 f303 lsl.w r3, r2, r3
|
|
|
80014ea: 43db mvns r3, r3
|
|
|
80014ec: 693a ldr r2, [r7, #16]
|
|
|
80014ee: 4013 ands r3, r2
|
|
|
80014f0: 613b str r3, [r7, #16]
|
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
|
80014f2: 683b ldr r3, [r7, #0]
|
|
|
80014f4: 685b ldr r3, [r3, #4]
|
|
|
80014f6: f003 0203 and.w r2, r3, #3
|
|
|
80014fa: 697b ldr r3, [r7, #20]
|
|
|
80014fc: 005b lsls r3, r3, #1
|
|
|
80014fe: fa02 f303 lsl.w r3, r2, r3
|
|
|
8001502: 693a ldr r2, [r7, #16]
|
|
|
8001504: 4313 orrs r3, r2
|
|
|
8001506: 613b str r3, [r7, #16]
|
|
|
GPIOx->MODER = temp;
|
|
|
8001508: 687b ldr r3, [r7, #4]
|
|
|
800150a: 693a ldr r2, [r7, #16]
|
|
|
800150c: 601a str r2, [r3, #0]
|
|
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
|
800150e: 683b ldr r3, [r7, #0]
|
|
|
8001510: 685b ldr r3, [r3, #4]
|
|
|
8001512: f403 3340 and.w r3, r3, #196608 ; 0x30000
|
|
|
8001516: 2b00 cmp r3, #0
|
|
|
8001518: f000 80a0 beq.w 800165c <HAL_GPIO_Init+0x2b4>
|
|
|
{
|
|
|
/* Enable SYSCFG Clock */
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
|
800151c: 4b58 ldr r3, [pc, #352] ; (8001680 <HAL_GPIO_Init+0x2d8>)
|
|
|
800151e: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8001520: 4a57 ldr r2, [pc, #348] ; (8001680 <HAL_GPIO_Init+0x2d8>)
|
|
|
8001522: f043 0301 orr.w r3, r3, #1
|
|
|
8001526: 6613 str r3, [r2, #96] ; 0x60
|
|
|
8001528: 4b55 ldr r3, [pc, #340] ; (8001680 <HAL_GPIO_Init+0x2d8>)
|
|
|
800152a: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
800152c: f003 0301 and.w r3, r3, #1
|
|
|
8001530: 60bb str r3, [r7, #8]
|
|
|
8001532: 68bb ldr r3, [r7, #8]
|
|
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
|
8001534: 4a53 ldr r2, [pc, #332] ; (8001684 <HAL_GPIO_Init+0x2dc>)
|
|
|
8001536: 697b ldr r3, [r7, #20]
|
|
|
8001538: 089b lsrs r3, r3, #2
|
|
|
800153a: 3302 adds r3, #2
|
|
|
800153c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
|
8001540: 613b str r3, [r7, #16]
|
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
|
8001542: 697b ldr r3, [r7, #20]
|
|
|
8001544: f003 0303 and.w r3, r3, #3
|
|
|
8001548: 009b lsls r3, r3, #2
|
|
|
800154a: 220f movs r2, #15
|
|
|
800154c: fa02 f303 lsl.w r3, r2, r3
|
|
|
8001550: 43db mvns r3, r3
|
|
|
8001552: 693a ldr r2, [r7, #16]
|
|
|
8001554: 4013 ands r3, r2
|
|
|
8001556: 613b str r3, [r7, #16]
|
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
|
8001558: 687b ldr r3, [r7, #4]
|
|
|
800155a: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
|
|
|
800155e: d019 beq.n 8001594 <HAL_GPIO_Init+0x1ec>
|
|
|
8001560: 687b ldr r3, [r7, #4]
|
|
|
8001562: 4a49 ldr r2, [pc, #292] ; (8001688 <HAL_GPIO_Init+0x2e0>)
|
|
|
8001564: 4293 cmp r3, r2
|
|
|
8001566: d013 beq.n 8001590 <HAL_GPIO_Init+0x1e8>
|
|
|
8001568: 687b ldr r3, [r7, #4]
|
|
|
800156a: 4a48 ldr r2, [pc, #288] ; (800168c <HAL_GPIO_Init+0x2e4>)
|
|
|
800156c: 4293 cmp r3, r2
|
|
|
800156e: d00d beq.n 800158c <HAL_GPIO_Init+0x1e4>
|
|
|
8001570: 687b ldr r3, [r7, #4]
|
|
|
8001572: 4a47 ldr r2, [pc, #284] ; (8001690 <HAL_GPIO_Init+0x2e8>)
|
|
|
8001574: 4293 cmp r3, r2
|
|
|
8001576: d007 beq.n 8001588 <HAL_GPIO_Init+0x1e0>
|
|
|
8001578: 687b ldr r3, [r7, #4]
|
|
|
800157a: 4a46 ldr r2, [pc, #280] ; (8001694 <HAL_GPIO_Init+0x2ec>)
|
|
|
800157c: 4293 cmp r3, r2
|
|
|
800157e: d101 bne.n 8001584 <HAL_GPIO_Init+0x1dc>
|
|
|
8001580: 2304 movs r3, #4
|
|
|
8001582: e008 b.n 8001596 <HAL_GPIO_Init+0x1ee>
|
|
|
8001584: 2307 movs r3, #7
|
|
|
8001586: e006 b.n 8001596 <HAL_GPIO_Init+0x1ee>
|
|
|
8001588: 2303 movs r3, #3
|
|
|
800158a: e004 b.n 8001596 <HAL_GPIO_Init+0x1ee>
|
|
|
800158c: 2302 movs r3, #2
|
|
|
800158e: e002 b.n 8001596 <HAL_GPIO_Init+0x1ee>
|
|
|
8001590: 2301 movs r3, #1
|
|
|
8001592: e000 b.n 8001596 <HAL_GPIO_Init+0x1ee>
|
|
|
8001594: 2300 movs r3, #0
|
|
|
8001596: 697a ldr r2, [r7, #20]
|
|
|
8001598: f002 0203 and.w r2, r2, #3
|
|
|
800159c: 0092 lsls r2, r2, #2
|
|
|
800159e: 4093 lsls r3, r2
|
|
|
80015a0: 693a ldr r2, [r7, #16]
|
|
|
80015a2: 4313 orrs r3, r2
|
|
|
80015a4: 613b str r3, [r7, #16]
|
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
|
80015a6: 4937 ldr r1, [pc, #220] ; (8001684 <HAL_GPIO_Init+0x2dc>)
|
|
|
80015a8: 697b ldr r3, [r7, #20]
|
|
|
80015aa: 089b lsrs r3, r3, #2
|
|
|
80015ac: 3302 adds r3, #2
|
|
|
80015ae: 693a ldr r2, [r7, #16]
|
|
|
80015b0: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
|
temp = EXTI->RTSR1;
|
|
|
80015b4: 4b38 ldr r3, [pc, #224] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
80015b6: 689b ldr r3, [r3, #8]
|
|
|
80015b8: 613b str r3, [r7, #16]
|
|
|
temp &= ~(iocurrent);
|
|
|
80015ba: 68fb ldr r3, [r7, #12]
|
|
|
80015bc: 43db mvns r3, r3
|
|
|
80015be: 693a ldr r2, [r7, #16]
|
|
|
80015c0: 4013 ands r3, r2
|
|
|
80015c2: 613b str r3, [r7, #16]
|
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
|
80015c4: 683b ldr r3, [r7, #0]
|
|
|
80015c6: 685b ldr r3, [r3, #4]
|
|
|
80015c8: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
|
80015cc: 2b00 cmp r3, #0
|
|
|
80015ce: d003 beq.n 80015d8 <HAL_GPIO_Init+0x230>
|
|
|
{
|
|
|
temp |= iocurrent;
|
|
|
80015d0: 693a ldr r2, [r7, #16]
|
|
|
80015d2: 68fb ldr r3, [r7, #12]
|
|
|
80015d4: 4313 orrs r3, r2
|
|
|
80015d6: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
EXTI->RTSR1 = temp;
|
|
|
80015d8: 4a2f ldr r2, [pc, #188] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
80015da: 693b ldr r3, [r7, #16]
|
|
|
80015dc: 6093 str r3, [r2, #8]
|
|
|
|
|
|
temp = EXTI->FTSR1;
|
|
|
80015de: 4b2e ldr r3, [pc, #184] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
80015e0: 68db ldr r3, [r3, #12]
|
|
|
80015e2: 613b str r3, [r7, #16]
|
|
|
temp &= ~(iocurrent);
|
|
|
80015e4: 68fb ldr r3, [r7, #12]
|
|
|
80015e6: 43db mvns r3, r3
|
|
|
80015e8: 693a ldr r2, [r7, #16]
|
|
|
80015ea: 4013 ands r3, r2
|
|
|
80015ec: 613b str r3, [r7, #16]
|
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
|
80015ee: 683b ldr r3, [r7, #0]
|
|
|
80015f0: 685b ldr r3, [r3, #4]
|
|
|
80015f2: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
|
80015f6: 2b00 cmp r3, #0
|
|
|
80015f8: d003 beq.n 8001602 <HAL_GPIO_Init+0x25a>
|
|
|
{
|
|
|
temp |= iocurrent;
|
|
|
80015fa: 693a ldr r2, [r7, #16]
|
|
|
80015fc: 68fb ldr r3, [r7, #12]
|
|
|
80015fe: 4313 orrs r3, r2
|
|
|
8001600: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
EXTI->FTSR1 = temp;
|
|
|
8001602: 4a25 ldr r2, [pc, #148] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
8001604: 693b ldr r3, [r7, #16]
|
|
|
8001606: 60d3 str r3, [r2, #12]
|
|
|
|
|
|
/* Clear EXTI line configuration */
|
|
|
temp = EXTI->EMR1;
|
|
|
8001608: 4b23 ldr r3, [pc, #140] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
800160a: 685b ldr r3, [r3, #4]
|
|
|
800160c: 613b str r3, [r7, #16]
|
|
|
temp &= ~(iocurrent);
|
|
|
800160e: 68fb ldr r3, [r7, #12]
|
|
|
8001610: 43db mvns r3, r3
|
|
|
8001612: 693a ldr r2, [r7, #16]
|
|
|
8001614: 4013 ands r3, r2
|
|
|
8001616: 613b str r3, [r7, #16]
|
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
|
8001618: 683b ldr r3, [r7, #0]
|
|
|
800161a: 685b ldr r3, [r3, #4]
|
|
|
800161c: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8001620: 2b00 cmp r3, #0
|
|
|
8001622: d003 beq.n 800162c <HAL_GPIO_Init+0x284>
|
|
|
{
|
|
|
temp |= iocurrent;
|
|
|
8001624: 693a ldr r2, [r7, #16]
|
|
|
8001626: 68fb ldr r3, [r7, #12]
|
|
|
8001628: 4313 orrs r3, r2
|
|
|
800162a: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
EXTI->EMR1 = temp;
|
|
|
800162c: 4a1a ldr r2, [pc, #104] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
800162e: 693b ldr r3, [r7, #16]
|
|
|
8001630: 6053 str r3, [r2, #4]
|
|
|
|
|
|
temp = EXTI->IMR1;
|
|
|
8001632: 4b19 ldr r3, [pc, #100] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
8001634: 681b ldr r3, [r3, #0]
|
|
|
8001636: 613b str r3, [r7, #16]
|
|
|
temp &= ~(iocurrent);
|
|
|
8001638: 68fb ldr r3, [r7, #12]
|
|
|
800163a: 43db mvns r3, r3
|
|
|
800163c: 693a ldr r2, [r7, #16]
|
|
|
800163e: 4013 ands r3, r2
|
|
|
8001640: 613b str r3, [r7, #16]
|
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
|
8001642: 683b ldr r3, [r7, #0]
|
|
|
8001644: 685b ldr r3, [r3, #4]
|
|
|
8001646: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
800164a: 2b00 cmp r3, #0
|
|
|
800164c: d003 beq.n 8001656 <HAL_GPIO_Init+0x2ae>
|
|
|
{
|
|
|
temp |= iocurrent;
|
|
|
800164e: 693a ldr r2, [r7, #16]
|
|
|
8001650: 68fb ldr r3, [r7, #12]
|
|
|
8001652: 4313 orrs r3, r2
|
|
|
8001654: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
EXTI->IMR1 = temp;
|
|
|
8001656: 4a10 ldr r2, [pc, #64] ; (8001698 <HAL_GPIO_Init+0x2f0>)
|
|
|
8001658: 693b ldr r3, [r7, #16]
|
|
|
800165a: 6013 str r3, [r2, #0]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
position++;
|
|
|
800165c: 697b ldr r3, [r7, #20]
|
|
|
800165e: 3301 adds r3, #1
|
|
|
8001660: 617b str r3, [r7, #20]
|
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
|
8001662: 683b ldr r3, [r7, #0]
|
|
|
8001664: 681a ldr r2, [r3, #0]
|
|
|
8001666: 697b ldr r3, [r7, #20]
|
|
|
8001668: fa22 f303 lsr.w r3, r2, r3
|
|
|
800166c: 2b00 cmp r3, #0
|
|
|
800166e: f47f aea3 bne.w 80013b8 <HAL_GPIO_Init+0x10>
|
|
|
}
|
|
|
}
|
|
|
8001672: bf00 nop
|
|
|
8001674: bf00 nop
|
|
|
8001676: 371c adds r7, #28
|
|
|
8001678: 46bd mov sp, r7
|
|
|
800167a: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800167e: 4770 bx lr
|
|
|
8001680: 40021000 .word 0x40021000
|
|
|
8001684: 40010000 .word 0x40010000
|
|
|
8001688: 48000400 .word 0x48000400
|
|
|
800168c: 48000800 .word 0x48000800
|
|
|
8001690: 48000c00 .word 0x48000c00
|
|
|
8001694: 48001000 .word 0x48001000
|
|
|
8001698: 40010400 .word 0x40010400
|
|
|
|
|
|
0800169c <HAL_GPIO_ReadPin>:
|
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
|
|
* @retval The input port pin value.
|
|
|
*/
|
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
|
{
|
|
|
800169c: b480 push {r7}
|
|
|
800169e: b085 sub sp, #20
|
|
|
80016a0: af00 add r7, sp, #0
|
|
|
80016a2: 6078 str r0, [r7, #4]
|
|
|
80016a4: 460b mov r3, r1
|
|
|
80016a6: 807b strh r3, [r7, #2]
|
|
|
GPIO_PinState bitstatus;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
|
|
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
|
|
|
80016a8: 687b ldr r3, [r7, #4]
|
|
|
80016aa: 691a ldr r2, [r3, #16]
|
|
|
80016ac: 887b ldrh r3, [r7, #2]
|
|
|
80016ae: 4013 ands r3, r2
|
|
|
80016b0: 2b00 cmp r3, #0
|
|
|
80016b2: d002 beq.n 80016ba <HAL_GPIO_ReadPin+0x1e>
|
|
|
{
|
|
|
bitstatus = GPIO_PIN_SET;
|
|
|
80016b4: 2301 movs r3, #1
|
|
|
80016b6: 73fb strb r3, [r7, #15]
|
|
|
80016b8: e001 b.n 80016be <HAL_GPIO_ReadPin+0x22>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
bitstatus = GPIO_PIN_RESET;
|
|
|
80016ba: 2300 movs r3, #0
|
|
|
80016bc: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
return bitstatus;
|
|
|
80016be: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
80016c0: 4618 mov r0, r3
|
|
|
80016c2: 3714 adds r7, #20
|
|
|
80016c4: 46bd mov sp, r7
|
|
|
80016c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80016ca: 4770 bx lr
|
|
|
|
|
|
080016cc <HAL_GPIO_WritePin>:
|
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
|
{
|
|
|
80016cc: b480 push {r7}
|
|
|
80016ce: b083 sub sp, #12
|
|
|
80016d0: af00 add r7, sp, #0
|
|
|
80016d2: 6078 str r0, [r7, #4]
|
|
|
80016d4: 460b mov r3, r1
|
|
|
80016d6: 807b strh r3, [r7, #2]
|
|
|
80016d8: 4613 mov r3, r2
|
|
|
80016da: 707b strb r3, [r7, #1]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
|
80016dc: 787b ldrb r3, [r7, #1]
|
|
|
80016de: 2b00 cmp r3, #0
|
|
|
80016e0: d003 beq.n 80016ea <HAL_GPIO_WritePin+0x1e>
|
|
|
{
|
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
|
80016e2: 887a ldrh r2, [r7, #2]
|
|
|
80016e4: 687b ldr r3, [r7, #4]
|
|
|
80016e6: 619a str r2, [r3, #24]
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
|
}
|
|
|
}
|
|
|
80016e8: e002 b.n 80016f0 <HAL_GPIO_WritePin+0x24>
|
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
|
80016ea: 887a ldrh r2, [r7, #2]
|
|
|
80016ec: 687b ldr r3, [r7, #4]
|
|
|
80016ee: 629a str r2, [r3, #40] ; 0x28
|
|
|
}
|
|
|
80016f0: bf00 nop
|
|
|
80016f2: 370c adds r7, #12
|
|
|
80016f4: 46bd mov sp, r7
|
|
|
80016f6: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80016fa: 4770 bx lr
|
|
|
|
|
|
080016fc <HAL_PWREx_GetVoltageRange>:
|
|
|
* @brief Return Voltage Scaling Range.
|
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
|
|
*/
|
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
|
{
|
|
|
80016fc: b480 push {r7}
|
|
|
80016fe: af00 add r7, sp, #0
|
|
|
else
|
|
|
{
|
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
|
|
}
|
|
|
#else
|
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
|
8001700: 4b04 ldr r3, [pc, #16] ; (8001714 <HAL_PWREx_GetVoltageRange+0x18>)
|
|
|
8001702: 681b ldr r3, [r3, #0]
|
|
|
8001704: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
|
|
#endif
|
|
|
}
|
|
|
8001708: 4618 mov r0, r3
|
|
|
800170a: 46bd mov sp, r7
|
|
|
800170c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8001710: 4770 bx lr
|
|
|
8001712: bf00 nop
|
|
|
8001714: 40007000 .word 0x40007000
|
|
|
|
|
|
08001718 <HAL_PWREx_ControlVoltageScaling>:
|
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
|
* @retval HAL Status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
|
{
|
|
|
8001718: b480 push {r7}
|
|
|
800171a: b085 sub sp, #20
|
|
|
800171c: af00 add r7, sp, #0
|
|
|
800171e: 6078 str r0, [r7, #4]
|
|
|
}
|
|
|
|
|
|
#else
|
|
|
|
|
|
/* If Set Range 1 */
|
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
|
8001720: 687b ldr r3, [r7, #4]
|
|
|
8001722: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
|
8001726: d130 bne.n 800178a <HAL_PWREx_ControlVoltageScaling+0x72>
|
|
|
{
|
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
|
8001728: 4b23 ldr r3, [pc, #140] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
800172a: 681b ldr r3, [r3, #0]
|
|
|
800172c: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
|
|
8001730: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
|
8001734: d038 beq.n 80017a8 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
|
{
|
|
|
/* Set Range 1 */
|
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
|
8001736: 4b20 ldr r3, [pc, #128] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
8001738: 681b ldr r3, [r3, #0]
|
|
|
800173a: f423 63c0 bic.w r3, r3, #1536 ; 0x600
|
|
|
800173e: 4a1e ldr r2, [pc, #120] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
8001740: f443 7300 orr.w r3, r3, #512 ; 0x200
|
|
|
8001744: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Wait until VOSF is cleared */
|
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
|
8001746: 4b1d ldr r3, [pc, #116] ; (80017bc <HAL_PWREx_ControlVoltageScaling+0xa4>)
|
|
|
8001748: 681b ldr r3, [r3, #0]
|
|
|
800174a: 2232 movs r2, #50 ; 0x32
|
|
|
800174c: fb02 f303 mul.w r3, r2, r3
|
|
|
8001750: 4a1b ldr r2, [pc, #108] ; (80017c0 <HAL_PWREx_ControlVoltageScaling+0xa8>)
|
|
|
8001752: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001756: 0c9b lsrs r3, r3, #18
|
|
|
8001758: 3301 adds r3, #1
|
|
|
800175a: 60fb str r3, [r7, #12]
|
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
|
800175c: e002 b.n 8001764 <HAL_PWREx_ControlVoltageScaling+0x4c>
|
|
|
{
|
|
|
wait_loop_index--;
|
|
|
800175e: 68fb ldr r3, [r7, #12]
|
|
|
8001760: 3b01 subs r3, #1
|
|
|
8001762: 60fb str r3, [r7, #12]
|
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
|
8001764: 4b14 ldr r3, [pc, #80] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
8001766: 695b ldr r3, [r3, #20]
|
|
|
8001768: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
800176c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
|
8001770: d102 bne.n 8001778 <HAL_PWREx_ControlVoltageScaling+0x60>
|
|
|
8001772: 68fb ldr r3, [r7, #12]
|
|
|
8001774: 2b00 cmp r3, #0
|
|
|
8001776: d1f2 bne.n 800175e <HAL_PWREx_ControlVoltageScaling+0x46>
|
|
|
}
|
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
|
8001778: 4b0f ldr r3, [pc, #60] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
800177a: 695b ldr r3, [r3, #20]
|
|
|
800177c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
8001780: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
|
8001784: d110 bne.n 80017a8 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001786: 2303 movs r3, #3
|
|
|
8001788: e00f b.n 80017aa <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
|
800178a: 4b0b ldr r3, [pc, #44] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
800178c: 681b ldr r3, [r3, #0]
|
|
|
800178e: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
|
|
8001792: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
|
8001796: d007 beq.n 80017a8 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
|
{
|
|
|
/* Set Range 2 */
|
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
|
8001798: 4b07 ldr r3, [pc, #28] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
800179a: 681b ldr r3, [r3, #0]
|
|
|
800179c: f423 63c0 bic.w r3, r3, #1536 ; 0x600
|
|
|
80017a0: 4a05 ldr r2, [pc, #20] ; (80017b8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
|
80017a2: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
|
|
80017a6: 6013 str r3, [r2, #0]
|
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
|
}
|
|
|
}
|
|
|
#endif
|
|
|
|
|
|
return HAL_OK;
|
|
|
80017a8: 2300 movs r3, #0
|
|
|
}
|
|
|
80017aa: 4618 mov r0, r3
|
|
|
80017ac: 3714 adds r7, #20
|
|
|
80017ae: 46bd mov sp, r7
|
|
|
80017b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80017b4: 4770 bx lr
|
|
|
80017b6: bf00 nop
|
|
|
80017b8: 40007000 .word 0x40007000
|
|
|
80017bc: 20000004 .word 0x20000004
|
|
|
80017c0: 431bde83 .word 0x431bde83
|
|
|
|
|
|
080017c4 <HAL_RCC_OscConfig>:
|
|
|
* @note If HSE failed to start, HSE should be disabled before recalling
|
|
|
HAL_RCC_OscConfig().
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
|
{
|
|
|
80017c4: b580 push {r7, lr}
|
|
|
80017c6: b088 sub sp, #32
|
|
|
80017c8: af00 add r7, sp, #0
|
|
|
80017ca: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart;
|
|
|
HAL_StatusTypeDef status;
|
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
|
|
/* Check Null pointer */
|
|
|
if(RCC_OscInitStruct == NULL)
|
|
|
80017cc: 687b ldr r3, [r7, #4]
|
|
|
80017ce: 2b00 cmp r3, #0
|
|
|
80017d0: d102 bne.n 80017d8 <HAL_RCC_OscConfig+0x14>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80017d2: 2301 movs r3, #1
|
|
|
80017d4: f000 bc02 b.w 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
|
80017d8: 4b96 ldr r3, [pc, #600] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80017da: 689b ldr r3, [r3, #8]
|
|
|
80017dc: f003 030c and.w r3, r3, #12
|
|
|
80017e0: 61bb str r3, [r7, #24]
|
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
|
80017e2: 4b94 ldr r3, [pc, #592] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80017e4: 68db ldr r3, [r3, #12]
|
|
|
80017e6: f003 0303 and.w r3, r3, #3
|
|
|
80017ea: 617b str r3, [r7, #20]
|
|
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
|
80017ec: 687b ldr r3, [r7, #4]
|
|
|
80017ee: 681b ldr r3, [r3, #0]
|
|
|
80017f0: f003 0310 and.w r3, r3, #16
|
|
|
80017f4: 2b00 cmp r3, #0
|
|
|
80017f6: f000 80e4 beq.w 80019c2 <HAL_RCC_OscConfig+0x1fe>
|
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
|
80017fa: 69bb ldr r3, [r7, #24]
|
|
|
80017fc: 2b00 cmp r3, #0
|
|
|
80017fe: d007 beq.n 8001810 <HAL_RCC_OscConfig+0x4c>
|
|
|
8001800: 69bb ldr r3, [r7, #24]
|
|
|
8001802: 2b0c cmp r3, #12
|
|
|
8001804: f040 808b bne.w 800191e <HAL_RCC_OscConfig+0x15a>
|
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
|
8001808: 697b ldr r3, [r7, #20]
|
|
|
800180a: 2b01 cmp r3, #1
|
|
|
800180c: f040 8087 bne.w 800191e <HAL_RCC_OscConfig+0x15a>
|
|
|
{
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
|
8001810: 4b88 ldr r3, [pc, #544] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001812: 681b ldr r3, [r3, #0]
|
|
|
8001814: f003 0302 and.w r3, r3, #2
|
|
|
8001818: 2b00 cmp r3, #0
|
|
|
800181a: d005 beq.n 8001828 <HAL_RCC_OscConfig+0x64>
|
|
|
800181c: 687b ldr r3, [r7, #4]
|
|
|
800181e: 699b ldr r3, [r3, #24]
|
|
|
8001820: 2b00 cmp r3, #0
|
|
|
8001822: d101 bne.n 8001828 <HAL_RCC_OscConfig+0x64>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001824: 2301 movs r3, #1
|
|
|
8001826: e3d9 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
else
|
|
|
{
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
|
8001828: 687b ldr r3, [r7, #4]
|
|
|
800182a: 6a1a ldr r2, [r3, #32]
|
|
|
800182c: 4b81 ldr r3, [pc, #516] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800182e: 681b ldr r3, [r3, #0]
|
|
|
8001830: f003 0308 and.w r3, r3, #8
|
|
|
8001834: 2b00 cmp r3, #0
|
|
|
8001836: d004 beq.n 8001842 <HAL_RCC_OscConfig+0x7e>
|
|
|
8001838: 4b7e ldr r3, [pc, #504] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800183a: 681b ldr r3, [r3, #0]
|
|
|
800183c: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
|
8001840: e005 b.n 800184e <HAL_RCC_OscConfig+0x8a>
|
|
|
8001842: 4b7c ldr r3, [pc, #496] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001844: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
|
8001848: 091b lsrs r3, r3, #4
|
|
|
800184a: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
|
800184e: 4293 cmp r3, r2
|
|
|
8001850: d223 bcs.n 800189a <HAL_RCC_OscConfig+0xd6>
|
|
|
{
|
|
|
/* First increase number of wait states update if necessary */
|
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
|
8001852: 687b ldr r3, [r7, #4]
|
|
|
8001854: 6a1b ldr r3, [r3, #32]
|
|
|
8001856: 4618 mov r0, r3
|
|
|
8001858: f000 fd8c bl 8002374 <RCC_SetFlashLatencyFromMSIRange>
|
|
|
800185c: 4603 mov r3, r0
|
|
|
800185e: 2b00 cmp r3, #0
|
|
|
8001860: d001 beq.n 8001866 <HAL_RCC_OscConfig+0xa2>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001862: 2301 movs r3, #1
|
|
|
8001864: e3ba b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
|
8001866: 4b73 ldr r3, [pc, #460] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001868: 681b ldr r3, [r3, #0]
|
|
|
800186a: 4a72 ldr r2, [pc, #456] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800186c: f043 0308 orr.w r3, r3, #8
|
|
|
8001870: 6013 str r3, [r2, #0]
|
|
|
8001872: 4b70 ldr r3, [pc, #448] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001874: 681b ldr r3, [r3, #0]
|
|
|
8001876: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
800187a: 687b ldr r3, [r7, #4]
|
|
|
800187c: 6a1b ldr r3, [r3, #32]
|
|
|
800187e: 496d ldr r1, [pc, #436] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001880: 4313 orrs r3, r2
|
|
|
8001882: 600b str r3, [r1, #0]
|
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
|
8001884: 4b6b ldr r3, [pc, #428] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001886: 685b ldr r3, [r3, #4]
|
|
|
8001888: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
|
|
800188c: 687b ldr r3, [r7, #4]
|
|
|
800188e: 69db ldr r3, [r3, #28]
|
|
|
8001890: 021b lsls r3, r3, #8
|
|
|
8001892: 4968 ldr r1, [pc, #416] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001894: 4313 orrs r3, r2
|
|
|
8001896: 604b str r3, [r1, #4]
|
|
|
8001898: e025 b.n 80018e6 <HAL_RCC_OscConfig+0x122>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
|
800189a: 4b66 ldr r3, [pc, #408] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800189c: 681b ldr r3, [r3, #0]
|
|
|
800189e: 4a65 ldr r2, [pc, #404] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80018a0: f043 0308 orr.w r3, r3, #8
|
|
|
80018a4: 6013 str r3, [r2, #0]
|
|
|
80018a6: 4b63 ldr r3, [pc, #396] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80018a8: 681b ldr r3, [r3, #0]
|
|
|
80018aa: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
80018ae: 687b ldr r3, [r7, #4]
|
|
|
80018b0: 6a1b ldr r3, [r3, #32]
|
|
|
80018b2: 4960 ldr r1, [pc, #384] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80018b4: 4313 orrs r3, r2
|
|
|
80018b6: 600b str r3, [r1, #0]
|
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
|
80018b8: 4b5e ldr r3, [pc, #376] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80018ba: 685b ldr r3, [r3, #4]
|
|
|
80018bc: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
|
|
80018c0: 687b ldr r3, [r7, #4]
|
|
|
80018c2: 69db ldr r3, [r3, #28]
|
|
|
80018c4: 021b lsls r3, r3, #8
|
|
|
80018c6: 495b ldr r1, [pc, #364] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80018c8: 4313 orrs r3, r2
|
|
|
80018ca: 604b str r3, [r1, #4]
|
|
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
|
/* Only possible when MSI is the System clock source */
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
|
80018cc: 69bb ldr r3, [r7, #24]
|
|
|
80018ce: 2b00 cmp r3, #0
|
|
|
80018d0: d109 bne.n 80018e6 <HAL_RCC_OscConfig+0x122>
|
|
|
{
|
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
|
80018d2: 687b ldr r3, [r7, #4]
|
|
|
80018d4: 6a1b ldr r3, [r3, #32]
|
|
|
80018d6: 4618 mov r0, r3
|
|
|
80018d8: f000 fd4c bl 8002374 <RCC_SetFlashLatencyFromMSIRange>
|
|
|
80018dc: 4603 mov r3, r0
|
|
|
80018de: 2b00 cmp r3, #0
|
|
|
80018e0: d001 beq.n 80018e6 <HAL_RCC_OscConfig+0x122>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80018e2: 2301 movs r3, #1
|
|
|
80018e4: e37a b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
|
80018e6: f000 fc81 bl 80021ec <HAL_RCC_GetSysClockFreq>
|
|
|
80018ea: 4602 mov r2, r0
|
|
|
80018ec: 4b51 ldr r3, [pc, #324] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80018ee: 689b ldr r3, [r3, #8]
|
|
|
80018f0: 091b lsrs r3, r3, #4
|
|
|
80018f2: f003 030f and.w r3, r3, #15
|
|
|
80018f6: 4950 ldr r1, [pc, #320] ; (8001a38 <HAL_RCC_OscConfig+0x274>)
|
|
|
80018f8: 5ccb ldrb r3, [r1, r3]
|
|
|
80018fa: f003 031f and.w r3, r3, #31
|
|
|
80018fe: fa22 f303 lsr.w r3, r2, r3
|
|
|
8001902: 4a4e ldr r2, [pc, #312] ; (8001a3c <HAL_RCC_OscConfig+0x278>)
|
|
|
8001904: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
|
status = HAL_InitTick(uwTickPrio);
|
|
|
8001906: 4b4e ldr r3, [pc, #312] ; (8001a40 <HAL_RCC_OscConfig+0x27c>)
|
|
|
8001908: 681b ldr r3, [r3, #0]
|
|
|
800190a: 4618 mov r0, r3
|
|
|
800190c: f7ff fb3c bl 8000f88 <HAL_InitTick>
|
|
|
8001910: 4603 mov r3, r0
|
|
|
8001912: 73fb strb r3, [r7, #15]
|
|
|
if(status != HAL_OK)
|
|
|
8001914: 7bfb ldrb r3, [r7, #15]
|
|
|
8001916: 2b00 cmp r3, #0
|
|
|
8001918: d052 beq.n 80019c0 <HAL_RCC_OscConfig+0x1fc>
|
|
|
{
|
|
|
return status;
|
|
|
800191a: 7bfb ldrb r3, [r7, #15]
|
|
|
800191c: e35e b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check the MSI State */
|
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
|
800191e: 687b ldr r3, [r7, #4]
|
|
|
8001920: 699b ldr r3, [r3, #24]
|
|
|
8001922: 2b00 cmp r3, #0
|
|
|
8001924: d032 beq.n 800198c <HAL_RCC_OscConfig+0x1c8>
|
|
|
{
|
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
|
__HAL_RCC_MSI_ENABLE();
|
|
|
8001926: 4b43 ldr r3, [pc, #268] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001928: 681b ldr r3, [r3, #0]
|
|
|
800192a: 4a42 ldr r2, [pc, #264] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800192c: f043 0301 orr.w r3, r3, #1
|
|
|
8001930: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get timeout */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001932: f7ff fb79 bl 8001028 <HAL_GetTick>
|
|
|
8001936: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till MSI is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
|
8001938: e008 b.n 800194c <HAL_RCC_OscConfig+0x188>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
|
800193a: f7ff fb75 bl 8001028 <HAL_GetTick>
|
|
|
800193e: 4602 mov r2, r0
|
|
|
8001940: 693b ldr r3, [r7, #16]
|
|
|
8001942: 1ad3 subs r3, r2, r3
|
|
|
8001944: 2b02 cmp r3, #2
|
|
|
8001946: d901 bls.n 800194c <HAL_RCC_OscConfig+0x188>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001948: 2303 movs r3, #3
|
|
|
800194a: e347 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
|
800194c: 4b39 ldr r3, [pc, #228] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800194e: 681b ldr r3, [r3, #0]
|
|
|
8001950: f003 0302 and.w r3, r3, #2
|
|
|
8001954: 2b00 cmp r3, #0
|
|
|
8001956: d0f0 beq.n 800193a <HAL_RCC_OscConfig+0x176>
|
|
|
}
|
|
|
}
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
|
8001958: 4b36 ldr r3, [pc, #216] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800195a: 681b ldr r3, [r3, #0]
|
|
|
800195c: 4a35 ldr r2, [pc, #212] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800195e: f043 0308 orr.w r3, r3, #8
|
|
|
8001962: 6013 str r3, [r2, #0]
|
|
|
8001964: 4b33 ldr r3, [pc, #204] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001966: 681b ldr r3, [r3, #0]
|
|
|
8001968: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
800196c: 687b ldr r3, [r7, #4]
|
|
|
800196e: 6a1b ldr r3, [r3, #32]
|
|
|
8001970: 4930 ldr r1, [pc, #192] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001972: 4313 orrs r3, r2
|
|
|
8001974: 600b str r3, [r1, #0]
|
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
|
8001976: 4b2f ldr r3, [pc, #188] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001978: 685b ldr r3, [r3, #4]
|
|
|
800197a: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
|
|
800197e: 687b ldr r3, [r7, #4]
|
|
|
8001980: 69db ldr r3, [r3, #28]
|
|
|
8001982: 021b lsls r3, r3, #8
|
|
|
8001984: 492b ldr r1, [pc, #172] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001986: 4313 orrs r3, r2
|
|
|
8001988: 604b str r3, [r1, #4]
|
|
|
800198a: e01a b.n 80019c2 <HAL_RCC_OscConfig+0x1fe>
|
|
|
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
|
__HAL_RCC_MSI_DISABLE();
|
|
|
800198c: 4b29 ldr r3, [pc, #164] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
800198e: 681b ldr r3, [r3, #0]
|
|
|
8001990: 4a28 ldr r2, [pc, #160] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001992: f023 0301 bic.w r3, r3, #1
|
|
|
8001996: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get timeout */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001998: f7ff fb46 bl 8001028 <HAL_GetTick>
|
|
|
800199c: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till MSI is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
|
800199e: e008 b.n 80019b2 <HAL_RCC_OscConfig+0x1ee>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
|
80019a0: f7ff fb42 bl 8001028 <HAL_GetTick>
|
|
|
80019a4: 4602 mov r2, r0
|
|
|
80019a6: 693b ldr r3, [r7, #16]
|
|
|
80019a8: 1ad3 subs r3, r2, r3
|
|
|
80019aa: 2b02 cmp r3, #2
|
|
|
80019ac: d901 bls.n 80019b2 <HAL_RCC_OscConfig+0x1ee>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80019ae: 2303 movs r3, #3
|
|
|
80019b0: e314 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
|
80019b2: 4b20 ldr r3, [pc, #128] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80019b4: 681b ldr r3, [r3, #0]
|
|
|
80019b6: f003 0302 and.w r3, r3, #2
|
|
|
80019ba: 2b00 cmp r3, #0
|
|
|
80019bc: d1f0 bne.n 80019a0 <HAL_RCC_OscConfig+0x1dc>
|
|
|
80019be: e000 b.n 80019c2 <HAL_RCC_OscConfig+0x1fe>
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
|
80019c0: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
|
80019c2: 687b ldr r3, [r7, #4]
|
|
|
80019c4: 681b ldr r3, [r3, #0]
|
|
|
80019c6: f003 0301 and.w r3, r3, #1
|
|
|
80019ca: 2b00 cmp r3, #0
|
|
|
80019cc: d073 beq.n 8001ab6 <HAL_RCC_OscConfig+0x2f2>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
|
|
80019ce: 69bb ldr r3, [r7, #24]
|
|
|
80019d0: 2b08 cmp r3, #8
|
|
|
80019d2: d005 beq.n 80019e0 <HAL_RCC_OscConfig+0x21c>
|
|
|
80019d4: 69bb ldr r3, [r7, #24]
|
|
|
80019d6: 2b0c cmp r3, #12
|
|
|
80019d8: d10e bne.n 80019f8 <HAL_RCC_OscConfig+0x234>
|
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
|
80019da: 697b ldr r3, [r7, #20]
|
|
|
80019dc: 2b03 cmp r3, #3
|
|
|
80019de: d10b bne.n 80019f8 <HAL_RCC_OscConfig+0x234>
|
|
|
{
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
|
80019e0: 4b14 ldr r3, [pc, #80] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
80019e2: 681b ldr r3, [r3, #0]
|
|
|
80019e4: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
80019e8: 2b00 cmp r3, #0
|
|
|
80019ea: d063 beq.n 8001ab4 <HAL_RCC_OscConfig+0x2f0>
|
|
|
80019ec: 687b ldr r3, [r7, #4]
|
|
|
80019ee: 685b ldr r3, [r3, #4]
|
|
|
80019f0: 2b00 cmp r3, #0
|
|
|
80019f2: d15f bne.n 8001ab4 <HAL_RCC_OscConfig+0x2f0>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80019f4: 2301 movs r3, #1
|
|
|
80019f6: e2f1 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
|
80019f8: 687b ldr r3, [r7, #4]
|
|
|
80019fa: 685b ldr r3, [r3, #4]
|
|
|
80019fc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
8001a00: d106 bne.n 8001a10 <HAL_RCC_OscConfig+0x24c>
|
|
|
8001a02: 4b0c ldr r3, [pc, #48] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001a04: 681b ldr r3, [r3, #0]
|
|
|
8001a06: 4a0b ldr r2, [pc, #44] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001a08: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
8001a0c: 6013 str r3, [r2, #0]
|
|
|
8001a0e: e025 b.n 8001a5c <HAL_RCC_OscConfig+0x298>
|
|
|
8001a10: 687b ldr r3, [r7, #4]
|
|
|
8001a12: 685b ldr r3, [r3, #4]
|
|
|
8001a14: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
|
8001a18: d114 bne.n 8001a44 <HAL_RCC_OscConfig+0x280>
|
|
|
8001a1a: 4b06 ldr r3, [pc, #24] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001a1c: 681b ldr r3, [r3, #0]
|
|
|
8001a1e: 4a05 ldr r2, [pc, #20] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001a20: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
|
8001a24: 6013 str r3, [r2, #0]
|
|
|
8001a26: 4b03 ldr r3, [pc, #12] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001a28: 681b ldr r3, [r3, #0]
|
|
|
8001a2a: 4a02 ldr r2, [pc, #8] ; (8001a34 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001a2c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
8001a30: 6013 str r3, [r2, #0]
|
|
|
8001a32: e013 b.n 8001a5c <HAL_RCC_OscConfig+0x298>
|
|
|
8001a34: 40021000 .word 0x40021000
|
|
|
8001a38: 08005c00 .word 0x08005c00
|
|
|
8001a3c: 20000004 .word 0x20000004
|
|
|
8001a40: 20000008 .word 0x20000008
|
|
|
8001a44: 4ba0 ldr r3, [pc, #640] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001a46: 681b ldr r3, [r3, #0]
|
|
|
8001a48: 4a9f ldr r2, [pc, #636] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001a4a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8001a4e: 6013 str r3, [r2, #0]
|
|
|
8001a50: 4b9d ldr r3, [pc, #628] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001a52: 681b ldr r3, [r3, #0]
|
|
|
8001a54: 4a9c ldr r2, [pc, #624] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001a56: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
|
8001a5a: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
|
8001a5c: 687b ldr r3, [r7, #4]
|
|
|
8001a5e: 685b ldr r3, [r3, #4]
|
|
|
8001a60: 2b00 cmp r3, #0
|
|
|
8001a62: d013 beq.n 8001a8c <HAL_RCC_OscConfig+0x2c8>
|
|
|
{
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001a64: f7ff fae0 bl 8001028 <HAL_GetTick>
|
|
|
8001a68: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSE is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
|
8001a6a: e008 b.n 8001a7e <HAL_RCC_OscConfig+0x2ba>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
|
8001a6c: f7ff fadc bl 8001028 <HAL_GetTick>
|
|
|
8001a70: 4602 mov r2, r0
|
|
|
8001a72: 693b ldr r3, [r7, #16]
|
|
|
8001a74: 1ad3 subs r3, r2, r3
|
|
|
8001a76: 2b64 cmp r3, #100 ; 0x64
|
|
|
8001a78: d901 bls.n 8001a7e <HAL_RCC_OscConfig+0x2ba>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001a7a: 2303 movs r3, #3
|
|
|
8001a7c: e2ae b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
|
8001a7e: 4b92 ldr r3, [pc, #584] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001a80: 681b ldr r3, [r3, #0]
|
|
|
8001a82: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8001a86: 2b00 cmp r3, #0
|
|
|
8001a88: d0f0 beq.n 8001a6c <HAL_RCC_OscConfig+0x2a8>
|
|
|
8001a8a: e014 b.n 8001ab6 <HAL_RCC_OscConfig+0x2f2>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001a8c: f7ff facc bl 8001028 <HAL_GetTick>
|
|
|
8001a90: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSE is disabled */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
|
8001a92: e008 b.n 8001aa6 <HAL_RCC_OscConfig+0x2e2>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
|
8001a94: f7ff fac8 bl 8001028 <HAL_GetTick>
|
|
|
8001a98: 4602 mov r2, r0
|
|
|
8001a9a: 693b ldr r3, [r7, #16]
|
|
|
8001a9c: 1ad3 subs r3, r2, r3
|
|
|
8001a9e: 2b64 cmp r3, #100 ; 0x64
|
|
|
8001aa0: d901 bls.n 8001aa6 <HAL_RCC_OscConfig+0x2e2>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001aa2: 2303 movs r3, #3
|
|
|
8001aa4: e29a b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
|
8001aa6: 4b88 ldr r3, [pc, #544] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001aa8: 681b ldr r3, [r3, #0]
|
|
|
8001aaa: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8001aae: 2b00 cmp r3, #0
|
|
|
8001ab0: d1f0 bne.n 8001a94 <HAL_RCC_OscConfig+0x2d0>
|
|
|
8001ab2: e000 b.n 8001ab6 <HAL_RCC_OscConfig+0x2f2>
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
|
8001ab4: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
|
8001ab6: 687b ldr r3, [r7, #4]
|
|
|
8001ab8: 681b ldr r3, [r3, #0]
|
|
|
8001aba: f003 0302 and.w r3, r3, #2
|
|
|
8001abe: 2b00 cmp r3, #0
|
|
|
8001ac0: d060 beq.n 8001b84 <HAL_RCC_OscConfig+0x3c0>
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
|
|
8001ac2: 69bb ldr r3, [r7, #24]
|
|
|
8001ac4: 2b04 cmp r3, #4
|
|
|
8001ac6: d005 beq.n 8001ad4 <HAL_RCC_OscConfig+0x310>
|
|
|
8001ac8: 69bb ldr r3, [r7, #24]
|
|
|
8001aca: 2b0c cmp r3, #12
|
|
|
8001acc: d119 bne.n 8001b02 <HAL_RCC_OscConfig+0x33e>
|
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
|
8001ace: 697b ldr r3, [r7, #20]
|
|
|
8001ad0: 2b02 cmp r3, #2
|
|
|
8001ad2: d116 bne.n 8001b02 <HAL_RCC_OscConfig+0x33e>
|
|
|
{
|
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
|
8001ad4: 4b7c ldr r3, [pc, #496] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001ad6: 681b ldr r3, [r3, #0]
|
|
|
8001ad8: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
8001adc: 2b00 cmp r3, #0
|
|
|
8001ade: d005 beq.n 8001aec <HAL_RCC_OscConfig+0x328>
|
|
|
8001ae0: 687b ldr r3, [r7, #4]
|
|
|
8001ae2: 68db ldr r3, [r3, #12]
|
|
|
8001ae4: 2b00 cmp r3, #0
|
|
|
8001ae6: d101 bne.n 8001aec <HAL_RCC_OscConfig+0x328>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001ae8: 2301 movs r3, #1
|
|
|
8001aea: e277 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
/* Otherwise, just the calibration is allowed */
|
|
|
else
|
|
|
{
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
8001aec: 4b76 ldr r3, [pc, #472] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001aee: 685b ldr r3, [r3, #4]
|
|
|
8001af0: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000
|
|
|
8001af4: 687b ldr r3, [r7, #4]
|
|
|
8001af6: 691b ldr r3, [r3, #16]
|
|
|
8001af8: 061b lsls r3, r3, #24
|
|
|
8001afa: 4973 ldr r1, [pc, #460] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001afc: 4313 orrs r3, r2
|
|
|
8001afe: 604b str r3, [r1, #4]
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
|
8001b00: e040 b.n 8001b84 <HAL_RCC_OscConfig+0x3c0>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check the HSI State */
|
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
|
8001b02: 687b ldr r3, [r7, #4]
|
|
|
8001b04: 68db ldr r3, [r3, #12]
|
|
|
8001b06: 2b00 cmp r3, #0
|
|
|
8001b08: d023 beq.n 8001b52 <HAL_RCC_OscConfig+0x38e>
|
|
|
{
|
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
|
__HAL_RCC_HSI_ENABLE();
|
|
|
8001b0a: 4b6f ldr r3, [pc, #444] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b0c: 681b ldr r3, [r3, #0]
|
|
|
8001b0e: 4a6e ldr r2, [pc, #440] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b10: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
|
8001b14: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001b16: f7ff fa87 bl 8001028 <HAL_GetTick>
|
|
|
8001b1a: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
|
8001b1c: e008 b.n 8001b30 <HAL_RCC_OscConfig+0x36c>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
|
8001b1e: f7ff fa83 bl 8001028 <HAL_GetTick>
|
|
|
8001b22: 4602 mov r2, r0
|
|
|
8001b24: 693b ldr r3, [r7, #16]
|
|
|
8001b26: 1ad3 subs r3, r2, r3
|
|
|
8001b28: 2b02 cmp r3, #2
|
|
|
8001b2a: d901 bls.n 8001b30 <HAL_RCC_OscConfig+0x36c>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001b2c: 2303 movs r3, #3
|
|
|
8001b2e: e255 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
|
8001b30: 4b65 ldr r3, [pc, #404] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b32: 681b ldr r3, [r3, #0]
|
|
|
8001b34: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
8001b38: 2b00 cmp r3, #0
|
|
|
8001b3a: d0f0 beq.n 8001b1e <HAL_RCC_OscConfig+0x35a>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
8001b3c: 4b62 ldr r3, [pc, #392] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b3e: 685b ldr r3, [r3, #4]
|
|
|
8001b40: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000
|
|
|
8001b44: 687b ldr r3, [r7, #4]
|
|
|
8001b46: 691b ldr r3, [r3, #16]
|
|
|
8001b48: 061b lsls r3, r3, #24
|
|
|
8001b4a: 495f ldr r1, [pc, #380] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b4c: 4313 orrs r3, r2
|
|
|
8001b4e: 604b str r3, [r1, #4]
|
|
|
8001b50: e018 b.n 8001b84 <HAL_RCC_OscConfig+0x3c0>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
|
__HAL_RCC_HSI_DISABLE();
|
|
|
8001b52: 4b5d ldr r3, [pc, #372] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b54: 681b ldr r3, [r3, #0]
|
|
|
8001b56: 4a5c ldr r2, [pc, #368] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b58: f423 7380 bic.w r3, r3, #256 ; 0x100
|
|
|
8001b5c: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001b5e: f7ff fa63 bl 8001028 <HAL_GetTick>
|
|
|
8001b62: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI is disabled */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
|
8001b64: e008 b.n 8001b78 <HAL_RCC_OscConfig+0x3b4>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
|
8001b66: f7ff fa5f bl 8001028 <HAL_GetTick>
|
|
|
8001b6a: 4602 mov r2, r0
|
|
|
8001b6c: 693b ldr r3, [r7, #16]
|
|
|
8001b6e: 1ad3 subs r3, r2, r3
|
|
|
8001b70: 2b02 cmp r3, #2
|
|
|
8001b72: d901 bls.n 8001b78 <HAL_RCC_OscConfig+0x3b4>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001b74: 2303 movs r3, #3
|
|
|
8001b76: e231 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
|
8001b78: 4b53 ldr r3, [pc, #332] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b7a: 681b ldr r3, [r3, #0]
|
|
|
8001b7c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
8001b80: 2b00 cmp r3, #0
|
|
|
8001b82: d1f0 bne.n 8001b66 <HAL_RCC_OscConfig+0x3a2>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
|
8001b84: 687b ldr r3, [r7, #4]
|
|
|
8001b86: 681b ldr r3, [r3, #0]
|
|
|
8001b88: f003 0308 and.w r3, r3, #8
|
|
|
8001b8c: 2b00 cmp r3, #0
|
|
|
8001b8e: d03c beq.n 8001c0a <HAL_RCC_OscConfig+0x446>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
|
|
/* Check the LSI State */
|
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
|
8001b90: 687b ldr r3, [r7, #4]
|
|
|
8001b92: 695b ldr r3, [r3, #20]
|
|
|
8001b94: 2b00 cmp r3, #0
|
|
|
8001b96: d01c beq.n 8001bd2 <HAL_RCC_OscConfig+0x40e>
|
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
|
|
}
|
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
|
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
|
__HAL_RCC_LSI_ENABLE();
|
|
|
8001b98: 4b4b ldr r3, [pc, #300] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001b9a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
|
8001b9e: 4a4a ldr r2, [pc, #296] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001ba0: f043 0301 orr.w r3, r3, #1
|
|
|
8001ba4: f8c2 3094 str.w r3, [r2, #148] ; 0x94
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001ba8: f7ff fa3e bl 8001028 <HAL_GetTick>
|
|
|
8001bac: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSI is ready */
|
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
|
8001bae: e008 b.n 8001bc2 <HAL_RCC_OscConfig+0x3fe>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
|
8001bb0: f7ff fa3a bl 8001028 <HAL_GetTick>
|
|
|
8001bb4: 4602 mov r2, r0
|
|
|
8001bb6: 693b ldr r3, [r7, #16]
|
|
|
8001bb8: 1ad3 subs r3, r2, r3
|
|
|
8001bba: 2b02 cmp r3, #2
|
|
|
8001bbc: d901 bls.n 8001bc2 <HAL_RCC_OscConfig+0x3fe>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001bbe: 2303 movs r3, #3
|
|
|
8001bc0: e20c b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
|
8001bc2: 4b41 ldr r3, [pc, #260] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001bc4: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
|
8001bc8: f003 0302 and.w r3, r3, #2
|
|
|
8001bcc: 2b00 cmp r3, #0
|
|
|
8001bce: d0ef beq.n 8001bb0 <HAL_RCC_OscConfig+0x3ec>
|
|
|
8001bd0: e01b b.n 8001c0a <HAL_RCC_OscConfig+0x446>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
|
__HAL_RCC_LSI_DISABLE();
|
|
|
8001bd2: 4b3d ldr r3, [pc, #244] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001bd4: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
|
8001bd8: 4a3b ldr r2, [pc, #236] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001bda: f023 0301 bic.w r3, r3, #1
|
|
|
8001bde: f8c2 3094 str.w r3, [r2, #148] ; 0x94
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001be2: f7ff fa21 bl 8001028 <HAL_GetTick>
|
|
|
8001be6: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSI is disabled */
|
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
|
8001be8: e008 b.n 8001bfc <HAL_RCC_OscConfig+0x438>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
|
8001bea: f7ff fa1d bl 8001028 <HAL_GetTick>
|
|
|
8001bee: 4602 mov r2, r0
|
|
|
8001bf0: 693b ldr r3, [r7, #16]
|
|
|
8001bf2: 1ad3 subs r3, r2, r3
|
|
|
8001bf4: 2b02 cmp r3, #2
|
|
|
8001bf6: d901 bls.n 8001bfc <HAL_RCC_OscConfig+0x438>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001bf8: 2303 movs r3, #3
|
|
|
8001bfa: e1ef b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
|
8001bfc: 4b32 ldr r3, [pc, #200] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001bfe: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
|
8001c02: f003 0302 and.w r3, r3, #2
|
|
|
8001c06: 2b00 cmp r3, #0
|
|
|
8001c08: d1ef bne.n 8001bea <HAL_RCC_OscConfig+0x426>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
|
8001c0a: 687b ldr r3, [r7, #4]
|
|
|
8001c0c: 681b ldr r3, [r3, #0]
|
|
|
8001c0e: f003 0304 and.w r3, r3, #4
|
|
|
8001c12: 2b00 cmp r3, #0
|
|
|
8001c14: f000 80a6 beq.w 8001d64 <HAL_RCC_OscConfig+0x5a0>
|
|
|
{
|
|
|
FlagStatus pwrclkchanged = RESET;
|
|
|
8001c18: 2300 movs r3, #0
|
|
|
8001c1a: 77fb strb r3, [r7, #31]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
|
|
8001c1c: 4b2a ldr r3, [pc, #168] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001c1e: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8001c20: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001c24: 2b00 cmp r3, #0
|
|
|
8001c26: d10d bne.n 8001c44 <HAL_RCC_OscConfig+0x480>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
8001c28: 4b27 ldr r3, [pc, #156] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001c2a: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8001c2c: 4a26 ldr r2, [pc, #152] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001c2e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001c32: 6593 str r3, [r2, #88] ; 0x58
|
|
|
8001c34: 4b24 ldr r3, [pc, #144] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001c36: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8001c38: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001c3c: 60bb str r3, [r7, #8]
|
|
|
8001c3e: 68bb ldr r3, [r7, #8]
|
|
|
pwrclkchanged = SET;
|
|
|
8001c40: 2301 movs r3, #1
|
|
|
8001c42: 77fb strb r3, [r7, #31]
|
|
|
}
|
|
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
|
8001c44: 4b21 ldr r3, [pc, #132] ; (8001ccc <HAL_RCC_OscConfig+0x508>)
|
|
|
8001c46: 681b ldr r3, [r3, #0]
|
|
|
8001c48: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8001c4c: 2b00 cmp r3, #0
|
|
|
8001c4e: d118 bne.n 8001c82 <HAL_RCC_OscConfig+0x4be>
|
|
|
{
|
|
|
/* Enable write access to Backup domain */
|
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
|
8001c50: 4b1e ldr r3, [pc, #120] ; (8001ccc <HAL_RCC_OscConfig+0x508>)
|
|
|
8001c52: 681b ldr r3, [r3, #0]
|
|
|
8001c54: 4a1d ldr r2, [pc, #116] ; (8001ccc <HAL_RCC_OscConfig+0x508>)
|
|
|
8001c56: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
|
8001c5a: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001c5c: f7ff f9e4 bl 8001028 <HAL_GetTick>
|
|
|
8001c60: 6138 str r0, [r7, #16]
|
|
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
|
8001c62: e008 b.n 8001c76 <HAL_RCC_OscConfig+0x4b2>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
8001c64: f7ff f9e0 bl 8001028 <HAL_GetTick>
|
|
|
8001c68: 4602 mov r2, r0
|
|
|
8001c6a: 693b ldr r3, [r7, #16]
|
|
|
8001c6c: 1ad3 subs r3, r2, r3
|
|
|
8001c6e: 2b02 cmp r3, #2
|
|
|
8001c70: d901 bls.n 8001c76 <HAL_RCC_OscConfig+0x4b2>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001c72: 2303 movs r3, #3
|
|
|
8001c74: e1b2 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
|
8001c76: 4b15 ldr r3, [pc, #84] ; (8001ccc <HAL_RCC_OscConfig+0x508>)
|
|
|
8001c78: 681b ldr r3, [r3, #0]
|
|
|
8001c7a: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8001c7e: 2b00 cmp r3, #0
|
|
|
8001c80: d0f0 beq.n 8001c64 <HAL_RCC_OscConfig+0x4a0>
|
|
|
{
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
|
}
|
|
|
#else
|
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
|
8001c82: 687b ldr r3, [r7, #4]
|
|
|
8001c84: 689b ldr r3, [r3, #8]
|
|
|
8001c86: 2b01 cmp r3, #1
|
|
|
8001c88: d108 bne.n 8001c9c <HAL_RCC_OscConfig+0x4d8>
|
|
|
8001c8a: 4b0f ldr r3, [pc, #60] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001c8c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001c90: 4a0d ldr r2, [pc, #52] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001c92: f043 0301 orr.w r3, r3, #1
|
|
|
8001c96: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
8001c9a: e029 b.n 8001cf0 <HAL_RCC_OscConfig+0x52c>
|
|
|
8001c9c: 687b ldr r3, [r7, #4]
|
|
|
8001c9e: 689b ldr r3, [r3, #8]
|
|
|
8001ca0: 2b05 cmp r3, #5
|
|
|
8001ca2: d115 bne.n 8001cd0 <HAL_RCC_OscConfig+0x50c>
|
|
|
8001ca4: 4b08 ldr r3, [pc, #32] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001ca6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001caa: 4a07 ldr r2, [pc, #28] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001cac: f043 0304 orr.w r3, r3, #4
|
|
|
8001cb0: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
8001cb4: 4b04 ldr r3, [pc, #16] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001cb6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001cba: 4a03 ldr r2, [pc, #12] ; (8001cc8 <HAL_RCC_OscConfig+0x504>)
|
|
|
8001cbc: f043 0301 orr.w r3, r3, #1
|
|
|
8001cc0: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
8001cc4: e014 b.n 8001cf0 <HAL_RCC_OscConfig+0x52c>
|
|
|
8001cc6: bf00 nop
|
|
|
8001cc8: 40021000 .word 0x40021000
|
|
|
8001ccc: 40007000 .word 0x40007000
|
|
|
8001cd0: 4b9a ldr r3, [pc, #616] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001cd2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001cd6: 4a99 ldr r2, [pc, #612] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001cd8: f023 0301 bic.w r3, r3, #1
|
|
|
8001cdc: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
8001ce0: 4b96 ldr r3, [pc, #600] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001ce2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001ce6: 4a95 ldr r2, [pc, #596] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001ce8: f023 0304 bic.w r3, r3, #4
|
|
|
8001cec: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
|
|
|
/* Check the LSE State */
|
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
|
8001cf0: 687b ldr r3, [r7, #4]
|
|
|
8001cf2: 689b ldr r3, [r3, #8]
|
|
|
8001cf4: 2b00 cmp r3, #0
|
|
|
8001cf6: d016 beq.n 8001d26 <HAL_RCC_OscConfig+0x562>
|
|
|
{
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001cf8: f7ff f996 bl 8001028 <HAL_GetTick>
|
|
|
8001cfc: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is ready */
|
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
|
8001cfe: e00a b.n 8001d16 <HAL_RCC_OscConfig+0x552>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
8001d00: f7ff f992 bl 8001028 <HAL_GetTick>
|
|
|
8001d04: 4602 mov r2, r0
|
|
|
8001d06: 693b ldr r3, [r7, #16]
|
|
|
8001d08: 1ad3 subs r3, r2, r3
|
|
|
8001d0a: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
8001d0e: 4293 cmp r3, r2
|
|
|
8001d10: d901 bls.n 8001d16 <HAL_RCC_OscConfig+0x552>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001d12: 2303 movs r3, #3
|
|
|
8001d14: e162 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
|
8001d16: 4b89 ldr r3, [pc, #548] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001d18: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001d1c: f003 0302 and.w r3, r3, #2
|
|
|
8001d20: 2b00 cmp r3, #0
|
|
|
8001d22: d0ed beq.n 8001d00 <HAL_RCC_OscConfig+0x53c>
|
|
|
8001d24: e015 b.n 8001d52 <HAL_RCC_OscConfig+0x58e>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001d26: f7ff f97f bl 8001028 <HAL_GetTick>
|
|
|
8001d2a: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is disabled */
|
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
|
8001d2c: e00a b.n 8001d44 <HAL_RCC_OscConfig+0x580>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
8001d2e: f7ff f97b bl 8001028 <HAL_GetTick>
|
|
|
8001d32: 4602 mov r2, r0
|
|
|
8001d34: 693b ldr r3, [r7, #16]
|
|
|
8001d36: 1ad3 subs r3, r2, r3
|
|
|
8001d38: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
8001d3c: 4293 cmp r3, r2
|
|
|
8001d3e: d901 bls.n 8001d44 <HAL_RCC_OscConfig+0x580>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001d40: 2303 movs r3, #3
|
|
|
8001d42: e14b b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
|
8001d44: 4b7d ldr r3, [pc, #500] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001d46: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8001d4a: f003 0302 and.w r3, r3, #2
|
|
|
8001d4e: 2b00 cmp r3, #0
|
|
|
8001d50: d1ed bne.n 8001d2e <HAL_RCC_OscConfig+0x56a>
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
}
|
|
|
|
|
|
/* Restore clock configuration if changed */
|
|
|
if(pwrclkchanged == SET)
|
|
|
8001d52: 7ffb ldrb r3, [r7, #31]
|
|
|
8001d54: 2b01 cmp r3, #1
|
|
|
8001d56: d105 bne.n 8001d64 <HAL_RCC_OscConfig+0x5a0>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
|
8001d58: 4b78 ldr r3, [pc, #480] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001d5a: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8001d5c: 4a77 ldr r2, [pc, #476] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001d5e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001d62: 6593 str r3, [r2, #88] ; 0x58
|
|
|
}
|
|
|
}
|
|
|
#if defined(RCC_HSI48_SUPPORT)
|
|
|
/*------------------------------ HSI48 Configuration -----------------------*/
|
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|
|
8001d64: 687b ldr r3, [r7, #4]
|
|
|
8001d66: 681b ldr r3, [r3, #0]
|
|
|
8001d68: f003 0320 and.w r3, r3, #32
|
|
|
8001d6c: 2b00 cmp r3, #0
|
|
|
8001d6e: d03c beq.n 8001dea <HAL_RCC_OscConfig+0x626>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|
|
|
|
|
/* Check the LSI State */
|
|
|
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|
|
8001d70: 687b ldr r3, [r7, #4]
|
|
|
8001d72: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8001d74: 2b00 cmp r3, #0
|
|
|
8001d76: d01c beq.n 8001db2 <HAL_RCC_OscConfig+0x5ee>
|
|
|
{
|
|
|
/* Enable the Internal Low Speed oscillator (HSI48). */
|
|
|
__HAL_RCC_HSI48_ENABLE();
|
|
|
8001d78: 4b70 ldr r3, [pc, #448] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001d7a: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
|
|
|
8001d7e: 4a6f ldr r2, [pc, #444] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001d80: f043 0301 orr.w r3, r3, #1
|
|
|
8001d84: f8c2 3098 str.w r3, [r2, #152] ; 0x98
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001d88: f7ff f94e bl 8001028 <HAL_GetTick>
|
|
|
8001d8c: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI48 is ready */
|
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
|
8001d8e: e008 b.n 8001da2 <HAL_RCC_OscConfig+0x5de>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
|
8001d90: f7ff f94a bl 8001028 <HAL_GetTick>
|
|
|
8001d94: 4602 mov r2, r0
|
|
|
8001d96: 693b ldr r3, [r7, #16]
|
|
|
8001d98: 1ad3 subs r3, r2, r3
|
|
|
8001d9a: 2b02 cmp r3, #2
|
|
|
8001d9c: d901 bls.n 8001da2 <HAL_RCC_OscConfig+0x5de>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001d9e: 2303 movs r3, #3
|
|
|
8001da0: e11c b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
|
8001da2: 4b66 ldr r3, [pc, #408] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001da4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
|
|
|
8001da8: f003 0302 and.w r3, r3, #2
|
|
|
8001dac: 2b00 cmp r3, #0
|
|
|
8001dae: d0ef beq.n 8001d90 <HAL_RCC_OscConfig+0x5cc>
|
|
|
8001db0: e01b b.n 8001dea <HAL_RCC_OscConfig+0x626>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal Low Speed oscillator (HSI48). */
|
|
|
__HAL_RCC_HSI48_DISABLE();
|
|
|
8001db2: 4b62 ldr r3, [pc, #392] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001db4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
|
|
|
8001db8: 4a60 ldr r2, [pc, #384] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001dba: f023 0301 bic.w r3, r3, #1
|
|
|
8001dbe: f8c2 3098 str.w r3, [r2, #152] ; 0x98
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001dc2: f7ff f931 bl 8001028 <HAL_GetTick>
|
|
|
8001dc6: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI48 is disabled */
|
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
|
8001dc8: e008 b.n 8001ddc <HAL_RCC_OscConfig+0x618>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
|
8001dca: f7ff f92d bl 8001028 <HAL_GetTick>
|
|
|
8001dce: 4602 mov r2, r0
|
|
|
8001dd0: 693b ldr r3, [r7, #16]
|
|
|
8001dd2: 1ad3 subs r3, r2, r3
|
|
|
8001dd4: 2b02 cmp r3, #2
|
|
|
8001dd6: d901 bls.n 8001ddc <HAL_RCC_OscConfig+0x618>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001dd8: 2303 movs r3, #3
|
|
|
8001dda: e0ff b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
|
8001ddc: 4b57 ldr r3, [pc, #348] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001dde: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
|
|
|
8001de2: f003 0302 and.w r3, r3, #2
|
|
|
8001de6: 2b00 cmp r3, #0
|
|
|
8001de8: d1ef bne.n 8001dca <HAL_RCC_OscConfig+0x606>
|
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
|
8001dea: 687b ldr r3, [r7, #4]
|
|
|
8001dec: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
|
8001dee: 2b00 cmp r3, #0
|
|
|
8001df0: f000 80f3 beq.w 8001fda <HAL_RCC_OscConfig+0x816>
|
|
|
{
|
|
|
/* PLL On ? */
|
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
|
8001df4: 687b ldr r3, [r7, #4]
|
|
|
8001df6: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
|
8001df8: 2b02 cmp r3, #2
|
|
|
8001dfa: f040 80c9 bne.w 8001f90 <HAL_RCC_OscConfig+0x7cc>
|
|
|
#endif /* RCC_PLLP_SUPPORT */
|
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
|
|
/* Do nothing if PLL configuration is the unchanged */
|
|
|
pll_config = RCC->PLLCFGR;
|
|
|
8001dfe: 4b4f ldr r3, [pc, #316] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001e00: 68db ldr r3, [r3, #12]
|
|
|
8001e02: 617b str r3, [r7, #20]
|
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
|
8001e04: 697b ldr r3, [r7, #20]
|
|
|
8001e06: f003 0203 and.w r2, r3, #3
|
|
|
8001e0a: 687b ldr r3, [r7, #4]
|
|
|
8001e0c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
|
8001e0e: 429a cmp r2, r3
|
|
|
8001e10: d12c bne.n 8001e6c <HAL_RCC_OscConfig+0x6a8>
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
|
8001e12: 697b ldr r3, [r7, #20]
|
|
|
8001e14: f003 0270 and.w r2, r3, #112 ; 0x70
|
|
|
8001e18: 687b ldr r3, [r7, #4]
|
|
|
8001e1a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
|
8001e1c: 3b01 subs r3, #1
|
|
|
8001e1e: 011b lsls r3, r3, #4
|
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
|
8001e20: 429a cmp r2, r3
|
|
|
8001e22: d123 bne.n 8001e6c <HAL_RCC_OscConfig+0x6a8>
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
|
8001e24: 697b ldr r3, [r7, #20]
|
|
|
8001e26: f403 42fe and.w r2, r3, #32512 ; 0x7f00
|
|
|
8001e2a: 687b ldr r3, [r7, #4]
|
|
|
8001e2c: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
|
8001e2e: 021b lsls r3, r3, #8
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
|
8001e30: 429a cmp r2, r3
|
|
|
8001e32: d11b bne.n 8001e6c <HAL_RCC_OscConfig+0x6a8>
|
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
|
8001e34: 697b ldr r3, [r7, #20]
|
|
|
8001e36: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000
|
|
|
8001e3a: 687b ldr r3, [r7, #4]
|
|
|
8001e3c: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
|
8001e3e: 06db lsls r3, r3, #27
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
|
8001e40: 429a cmp r2, r3
|
|
|
8001e42: d113 bne.n 8001e6c <HAL_RCC_OscConfig+0x6a8>
|
|
|
#else
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
|
#endif
|
|
|
#endif
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
|
8001e44: 697b ldr r3, [r7, #20]
|
|
|
8001e46: f403 02c0 and.w r2, r3, #6291456 ; 0x600000
|
|
|
8001e4a: 687b ldr r3, [r7, #4]
|
|
|
8001e4c: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
|
8001e4e: 085b lsrs r3, r3, #1
|
|
|
8001e50: 3b01 subs r3, #1
|
|
|
8001e52: 055b lsls r3, r3, #21
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
|
8001e54: 429a cmp r2, r3
|
|
|
8001e56: d109 bne.n 8001e6c <HAL_RCC_OscConfig+0x6a8>
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
|
8001e58: 697b ldr r3, [r7, #20]
|
|
|
8001e5a: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000
|
|
|
8001e5e: 687b ldr r3, [r7, #4]
|
|
|
8001e60: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
|
8001e62: 085b lsrs r3, r3, #1
|
|
|
8001e64: 3b01 subs r3, #1
|
|
|
8001e66: 065b lsls r3, r3, #25
|
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
|
8001e68: 429a cmp r2, r3
|
|
|
8001e6a: d06b beq.n 8001f44 <HAL_RCC_OscConfig+0x780>
|
|
|
{
|
|
|
/* Check if the PLL is used as system clock or not */
|
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
|
8001e6c: 69bb ldr r3, [r7, #24]
|
|
|
8001e6e: 2b0c cmp r3, #12
|
|
|
8001e70: d062 beq.n 8001f38 <HAL_RCC_OscConfig+0x774>
|
|
|
{
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
|
|
/* Check if main PLL can be updated */
|
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
|
8001e72: 4b32 ldr r3, [pc, #200] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001e74: 681b ldr r3, [r3, #0]
|
|
|
8001e76: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
|
8001e7a: 2b00 cmp r3, #0
|
|
|
8001e7c: d001 beq.n 8001e82 <HAL_RCC_OscConfig+0x6be>
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
|
|
#endif
|
|
|
)
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001e7e: 2301 movs r3, #1
|
|
|
8001e80: e0ac b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
else
|
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
|
|
{
|
|
|
/* Disable the main PLL. */
|
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
8001e82: 4b2e ldr r3, [pc, #184] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001e84: 681b ldr r3, [r3, #0]
|
|
|
8001e86: 4a2d ldr r2, [pc, #180] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001e88: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
|
8001e8c: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001e8e: f7ff f8cb bl 8001028 <HAL_GetTick>
|
|
|
8001e92: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
|
8001e94: e008 b.n 8001ea8 <HAL_RCC_OscConfig+0x6e4>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001e96: f7ff f8c7 bl 8001028 <HAL_GetTick>
|
|
|
8001e9a: 4602 mov r2, r0
|
|
|
8001e9c: 693b ldr r3, [r7, #16]
|
|
|
8001e9e: 1ad3 subs r3, r2, r3
|
|
|
8001ea0: 2b02 cmp r3, #2
|
|
|
8001ea2: d901 bls.n 8001ea8 <HAL_RCC_OscConfig+0x6e4>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001ea4: 2303 movs r3, #3
|
|
|
8001ea6: e099 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
|
8001ea8: 4b24 ldr r3, [pc, #144] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001eaa: 681b ldr r3, [r3, #0]
|
|
|
8001eac: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
8001eb0: 2b00 cmp r3, #0
|
|
|
8001eb2: d1f0 bne.n 8001e96 <HAL_RCC_OscConfig+0x6d2>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
|
8001eb4: 4b21 ldr r3, [pc, #132] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001eb6: 68da ldr r2, [r3, #12]
|
|
|
8001eb8: 4b21 ldr r3, [pc, #132] ; (8001f40 <HAL_RCC_OscConfig+0x77c>)
|
|
|
8001eba: 4013 ands r3, r2
|
|
|
8001ebc: 687a ldr r2, [r7, #4]
|
|
|
8001ebe: 6ad1 ldr r1, [r2, #44] ; 0x2c
|
|
|
8001ec0: 687a ldr r2, [r7, #4]
|
|
|
8001ec2: 6b12 ldr r2, [r2, #48] ; 0x30
|
|
|
8001ec4: 3a01 subs r2, #1
|
|
|
8001ec6: 0112 lsls r2, r2, #4
|
|
|
8001ec8: 4311 orrs r1, r2
|
|
|
8001eca: 687a ldr r2, [r7, #4]
|
|
|
8001ecc: 6b52 ldr r2, [r2, #52] ; 0x34
|
|
|
8001ece: 0212 lsls r2, r2, #8
|
|
|
8001ed0: 4311 orrs r1, r2
|
|
|
8001ed2: 687a ldr r2, [r7, #4]
|
|
|
8001ed4: 6bd2 ldr r2, [r2, #60] ; 0x3c
|
|
|
8001ed6: 0852 lsrs r2, r2, #1
|
|
|
8001ed8: 3a01 subs r2, #1
|
|
|
8001eda: 0552 lsls r2, r2, #21
|
|
|
8001edc: 4311 orrs r1, r2
|
|
|
8001ede: 687a ldr r2, [r7, #4]
|
|
|
8001ee0: 6c12 ldr r2, [r2, #64] ; 0x40
|
|
|
8001ee2: 0852 lsrs r2, r2, #1
|
|
|
8001ee4: 3a01 subs r2, #1
|
|
|
8001ee6: 0652 lsls r2, r2, #25
|
|
|
8001ee8: 4311 orrs r1, r2
|
|
|
8001eea: 687a ldr r2, [r7, #4]
|
|
|
8001eec: 6b92 ldr r2, [r2, #56] ; 0x38
|
|
|
8001eee: 06d2 lsls r2, r2, #27
|
|
|
8001ef0: 430a orrs r2, r1
|
|
|
8001ef2: 4912 ldr r1, [pc, #72] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001ef4: 4313 orrs r3, r2
|
|
|
8001ef6: 60cb str r3, [r1, #12]
|
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
#endif
|
|
|
|
|
|
/* Enable the main PLL. */
|
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
8001ef8: 4b10 ldr r3, [pc, #64] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001efa: 681b ldr r3, [r3, #0]
|
|
|
8001efc: 4a0f ldr r2, [pc, #60] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001efe: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
|
8001f02: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Enable PLL System Clock output. */
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
|
8001f04: 4b0d ldr r3, [pc, #52] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001f06: 68db ldr r3, [r3, #12]
|
|
|
8001f08: 4a0c ldr r2, [pc, #48] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001f0a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
|
8001f0e: 60d3 str r3, [r2, #12]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001f10: f7ff f88a bl 8001028 <HAL_GetTick>
|
|
|
8001f14: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
|
8001f16: e008 b.n 8001f2a <HAL_RCC_OscConfig+0x766>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001f18: f7ff f886 bl 8001028 <HAL_GetTick>
|
|
|
8001f1c: 4602 mov r2, r0
|
|
|
8001f1e: 693b ldr r3, [r7, #16]
|
|
|
8001f20: 1ad3 subs r3, r2, r3
|
|
|
8001f22: 2b02 cmp r3, #2
|
|
|
8001f24: d901 bls.n 8001f2a <HAL_RCC_OscConfig+0x766>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001f26: 2303 movs r3, #3
|
|
|
8001f28: e058 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
|
8001f2a: 4b04 ldr r3, [pc, #16] ; (8001f3c <HAL_RCC_OscConfig+0x778>)
|
|
|
8001f2c: 681b ldr r3, [r3, #0]
|
|
|
8001f2e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
8001f32: 2b00 cmp r3, #0
|
|
|
8001f34: d0f0 beq.n 8001f18 <HAL_RCC_OscConfig+0x754>
|
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
|
8001f36: e050 b.n 8001fda <HAL_RCC_OscConfig+0x816>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* PLL is already used as System core clock */
|
|
|
return HAL_ERROR;
|
|
|
8001f38: 2301 movs r3, #1
|
|
|
8001f3a: e04f b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
8001f3c: 40021000 .word 0x40021000
|
|
|
8001f40: 019d808c .word 0x019d808c
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* PLL configuration is unchanged */
|
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
|
8001f44: 4b27 ldr r3, [pc, #156] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f46: 681b ldr r3, [r3, #0]
|
|
|
8001f48: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
8001f4c: 2b00 cmp r3, #0
|
|
|
8001f4e: d144 bne.n 8001fda <HAL_RCC_OscConfig+0x816>
|
|
|
{
|
|
|
/* Enable the main PLL. */
|
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
8001f50: 4b24 ldr r3, [pc, #144] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f52: 681b ldr r3, [r3, #0]
|
|
|
8001f54: 4a23 ldr r2, [pc, #140] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f56: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
|
8001f5a: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Enable PLL System Clock output. */
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
|
8001f5c: 4b21 ldr r3, [pc, #132] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f5e: 68db ldr r3, [r3, #12]
|
|
|
8001f60: 4a20 ldr r2, [pc, #128] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f62: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
|
8001f66: 60d3 str r3, [r2, #12]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001f68: f7ff f85e bl 8001028 <HAL_GetTick>
|
|
|
8001f6c: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
|
8001f6e: e008 b.n 8001f82 <HAL_RCC_OscConfig+0x7be>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001f70: f7ff f85a bl 8001028 <HAL_GetTick>
|
|
|
8001f74: 4602 mov r2, r0
|
|
|
8001f76: 693b ldr r3, [r7, #16]
|
|
|
8001f78: 1ad3 subs r3, r2, r3
|
|
|
8001f7a: 2b02 cmp r3, #2
|
|
|
8001f7c: d901 bls.n 8001f82 <HAL_RCC_OscConfig+0x7be>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001f7e: 2303 movs r3, #3
|
|
|
8001f80: e02c b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
|
8001f82: 4b18 ldr r3, [pc, #96] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f84: 681b ldr r3, [r3, #0]
|
|
|
8001f86: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
8001f8a: 2b00 cmp r3, #0
|
|
|
8001f8c: d0f0 beq.n 8001f70 <HAL_RCC_OscConfig+0x7ac>
|
|
|
8001f8e: e024 b.n 8001fda <HAL_RCC_OscConfig+0x816>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check that PLL is not used as system clock or not */
|
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
|
8001f90: 69bb ldr r3, [r7, #24]
|
|
|
8001f92: 2b0c cmp r3, #12
|
|
|
8001f94: d01f beq.n 8001fd6 <HAL_RCC_OscConfig+0x812>
|
|
|
{
|
|
|
/* Disable the main PLL. */
|
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
8001f96: 4b13 ldr r3, [pc, #76] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f98: 681b ldr r3, [r3, #0]
|
|
|
8001f9a: 4a12 ldr r2, [pc, #72] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001f9c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
|
8001fa0: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001fa2: f7ff f841 bl 8001028 <HAL_GetTick>
|
|
|
8001fa6: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is disabled */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
|
8001fa8: e008 b.n 8001fbc <HAL_RCC_OscConfig+0x7f8>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001faa: f7ff f83d bl 8001028 <HAL_GetTick>
|
|
|
8001fae: 4602 mov r2, r0
|
|
|
8001fb0: 693b ldr r3, [r7, #16]
|
|
|
8001fb2: 1ad3 subs r3, r2, r3
|
|
|
8001fb4: 2b02 cmp r3, #2
|
|
|
8001fb6: d901 bls.n 8001fbc <HAL_RCC_OscConfig+0x7f8>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001fb8: 2303 movs r3, #3
|
|
|
8001fba: e00f b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
|
8001fbc: 4b09 ldr r3, [pc, #36] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001fbe: 681b ldr r3, [r3, #0]
|
|
|
8001fc0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
8001fc4: 2b00 cmp r3, #0
|
|
|
8001fc6: d1f0 bne.n 8001faa <HAL_RCC_OscConfig+0x7e6>
|
|
|
}
|
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
|
|
#elif defined(RCC_PLLSAI1_SUPPORT)
|
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
|
|
|
8001fc8: 4b06 ldr r3, [pc, #24] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001fca: 68da ldr r2, [r3, #12]
|
|
|
8001fcc: 4905 ldr r1, [pc, #20] ; (8001fe4 <HAL_RCC_OscConfig+0x820>)
|
|
|
8001fce: 4b06 ldr r3, [pc, #24] ; (8001fe8 <HAL_RCC_OscConfig+0x824>)
|
|
|
8001fd0: 4013 ands r3, r2
|
|
|
8001fd2: 60cb str r3, [r1, #12]
|
|
|
8001fd4: e001 b.n 8001fda <HAL_RCC_OscConfig+0x816>
|
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* PLL is already used as System core clock */
|
|
|
return HAL_ERROR;
|
|
|
8001fd6: 2301 movs r3, #1
|
|
|
8001fd8: e000 b.n 8001fdc <HAL_RCC_OscConfig+0x818>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
return HAL_OK;
|
|
|
8001fda: 2300 movs r3, #0
|
|
|
}
|
|
|
8001fdc: 4618 mov r0, r3
|
|
|
8001fde: 3720 adds r7, #32
|
|
|
8001fe0: 46bd mov sp, r7
|
|
|
8001fe2: bd80 pop {r7, pc}
|
|
|
8001fe4: 40021000 .word 0x40021000
|
|
|
8001fe8: feeefffc .word 0xfeeefffc
|
|
|
|
|
|
08001fec <HAL_RCC_ClockConfig>:
|
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
|
* @retval None
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
|
{
|
|
|
8001fec: b580 push {r7, lr}
|
|
|
8001fee: b084 sub sp, #16
|
|
|
8001ff0: af00 add r7, sp, #0
|
|
|
8001ff2: 6078 str r0, [r7, #4]
|
|
|
8001ff4: 6039 str r1, [r7, #0]
|
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
|
#endif
|
|
|
HAL_StatusTypeDef status;
|
|
|
|
|
|
/* Check Null pointer */
|
|
|
if(RCC_ClkInitStruct == NULL)
|
|
|
8001ff6: 687b ldr r3, [r7, #4]
|
|
|
8001ff8: 2b00 cmp r3, #0
|
|
|
8001ffa: d101 bne.n 8002000 <HAL_RCC_ClockConfig+0x14>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001ffc: 2301 movs r3, #1
|
|
|
8001ffe: e0e7 b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
|
8002000: 4b75 ldr r3, [pc, #468] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002002: 681b ldr r3, [r3, #0]
|
|
|
8002004: f003 0307 and.w r3, r3, #7
|
|
|
8002008: 683a ldr r2, [r7, #0]
|
|
|
800200a: 429a cmp r2, r3
|
|
|
800200c: d910 bls.n 8002030 <HAL_RCC_ClockConfig+0x44>
|
|
|
{
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
800200e: 4b72 ldr r3, [pc, #456] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002010: 681b ldr r3, [r3, #0]
|
|
|
8002012: f023 0207 bic.w r2, r3, #7
|
|
|
8002016: 4970 ldr r1, [pc, #448] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002018: 683b ldr r3, [r7, #0]
|
|
|
800201a: 4313 orrs r3, r2
|
|
|
800201c: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
|
800201e: 4b6e ldr r3, [pc, #440] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002020: 681b ldr r3, [r3, #0]
|
|
|
8002022: f003 0307 and.w r3, r3, #7
|
|
|
8002026: 683a ldr r2, [r7, #0]
|
|
|
8002028: 429a cmp r2, r3
|
|
|
800202a: d001 beq.n 8002030 <HAL_RCC_ClockConfig+0x44>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800202c: 2301 movs r3, #1
|
|
|
800202e: e0cf b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
|
|
|
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
|
8002030: 687b ldr r3, [r7, #4]
|
|
|
8002032: 681b ldr r3, [r3, #0]
|
|
|
8002034: f003 0302 and.w r3, r3, #2
|
|
|
8002038: 2b00 cmp r3, #0
|
|
|
800203a: d010 beq.n 800205e <HAL_RCC_ClockConfig+0x72>
|
|
|
{
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
|
|
|
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
|
800203c: 687b ldr r3, [r7, #4]
|
|
|
800203e: 689a ldr r2, [r3, #8]
|
|
|
8002040: 4b66 ldr r3, [pc, #408] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
8002042: 689b ldr r3, [r3, #8]
|
|
|
8002044: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
|
8002048: 429a cmp r2, r3
|
|
|
800204a: d908 bls.n 800205e <HAL_RCC_ClockConfig+0x72>
|
|
|
{
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
800204c: 4b63 ldr r3, [pc, #396] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800204e: 689b ldr r3, [r3, #8]
|
|
|
8002050: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
8002054: 687b ldr r3, [r7, #4]
|
|
|
8002056: 689b ldr r3, [r3, #8]
|
|
|
8002058: 4960 ldr r1, [pc, #384] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800205a: 4313 orrs r3, r2
|
|
|
800205c: 608b str r3, [r1, #8]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
|
800205e: 687b ldr r3, [r7, #4]
|
|
|
8002060: 681b ldr r3, [r3, #0]
|
|
|
8002062: f003 0301 and.w r3, r3, #1
|
|
|
8002066: 2b00 cmp r3, #0
|
|
|
8002068: d04c beq.n 8002104 <HAL_RCC_ClockConfig+0x118>
|
|
|
{
|
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
800206a: 687b ldr r3, [r7, #4]
|
|
|
800206c: 685b ldr r3, [r3, #4]
|
|
|
800206e: 2b03 cmp r3, #3
|
|
|
8002070: d107 bne.n 8002082 <HAL_RCC_ClockConfig+0x96>
|
|
|
{
|
|
|
/* Check the PLL ready flag */
|
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
|
8002072: 4b5a ldr r3, [pc, #360] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
8002074: 681b ldr r3, [r3, #0]
|
|
|
8002076: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
800207a: 2b00 cmp r3, #0
|
|
|
800207c: d121 bne.n 80020c2 <HAL_RCC_ClockConfig+0xd6>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800207e: 2301 movs r3, #1
|
|
|
8002080: e0a6 b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
#endif
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* HSE is selected as System Clock Source */
|
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
8002082: 687b ldr r3, [r7, #4]
|
|
|
8002084: 685b ldr r3, [r3, #4]
|
|
|
8002086: 2b02 cmp r3, #2
|
|
|
8002088: d107 bne.n 800209a <HAL_RCC_ClockConfig+0xae>
|
|
|
{
|
|
|
/* Check the HSE ready flag */
|
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
|
800208a: 4b54 ldr r3, [pc, #336] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800208c: 681b ldr r3, [r3, #0]
|
|
|
800208e: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8002092: 2b00 cmp r3, #0
|
|
|
8002094: d115 bne.n 80020c2 <HAL_RCC_ClockConfig+0xd6>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8002096: 2301 movs r3, #1
|
|
|
8002098: e09a b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
}
|
|
|
}
|
|
|
/* MSI is selected as System Clock Source */
|
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
|
800209a: 687b ldr r3, [r7, #4]
|
|
|
800209c: 685b ldr r3, [r3, #4]
|
|
|
800209e: 2b00 cmp r3, #0
|
|
|
80020a0: d107 bne.n 80020b2 <HAL_RCC_ClockConfig+0xc6>
|
|
|
{
|
|
|
/* Check the MSI ready flag */
|
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
|
80020a2: 4b4e ldr r3, [pc, #312] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
80020a4: 681b ldr r3, [r3, #0]
|
|
|
80020a6: f003 0302 and.w r3, r3, #2
|
|
|
80020aa: 2b00 cmp r3, #0
|
|
|
80020ac: d109 bne.n 80020c2 <HAL_RCC_ClockConfig+0xd6>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80020ae: 2301 movs r3, #1
|
|
|
80020b0: e08e b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
}
|
|
|
/* HSI is selected as System Clock Source */
|
|
|
else
|
|
|
{
|
|
|
/* Check the HSI ready flag */
|
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
|
80020b2: 4b4a ldr r3, [pc, #296] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
80020b4: 681b ldr r3, [r3, #0]
|
|
|
80020b6: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
80020ba: 2b00 cmp r3, #0
|
|
|
80020bc: d101 bne.n 80020c2 <HAL_RCC_ClockConfig+0xd6>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80020be: 2301 movs r3, #1
|
|
|
80020c0: e086 b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
}
|
|
|
#endif
|
|
|
|
|
|
}
|
|
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
|
80020c2: 4b46 ldr r3, [pc, #280] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
80020c4: 689b ldr r3, [r3, #8]
|
|
|
80020c6: f023 0203 bic.w r2, r3, #3
|
|
|
80020ca: 687b ldr r3, [r7, #4]
|
|
|
80020cc: 685b ldr r3, [r3, #4]
|
|
|
80020ce: 4943 ldr r1, [pc, #268] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
80020d0: 4313 orrs r3, r2
|
|
|
80020d2: 608b str r3, [r1, #8]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
80020d4: f7fe ffa8 bl 8001028 <HAL_GetTick>
|
|
|
80020d8: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
|
80020da: e00a b.n 80020f2 <HAL_RCC_ClockConfig+0x106>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
80020dc: f7fe ffa4 bl 8001028 <HAL_GetTick>
|
|
|
80020e0: 4602 mov r2, r0
|
|
|
80020e2: 68fb ldr r3, [r7, #12]
|
|
|
80020e4: 1ad3 subs r3, r2, r3
|
|
|
80020e6: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
80020ea: 4293 cmp r3, r2
|
|
|
80020ec: d901 bls.n 80020f2 <HAL_RCC_ClockConfig+0x106>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80020ee: 2303 movs r3, #3
|
|
|
80020f0: e06e b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
|
80020f2: 4b3a ldr r3, [pc, #232] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
80020f4: 689b ldr r3, [r3, #8]
|
|
|
80020f6: f003 020c and.w r2, r3, #12
|
|
|
80020fa: 687b ldr r3, [r7, #4]
|
|
|
80020fc: 685b ldr r3, [r3, #4]
|
|
|
80020fe: 009b lsls r3, r3, #2
|
|
|
8002100: 429a cmp r2, r3
|
|
|
8002102: d1eb bne.n 80020dc <HAL_RCC_ClockConfig+0xf0>
|
|
|
}
|
|
|
#endif
|
|
|
|
|
|
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
|
|
|
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
|
8002104: 687b ldr r3, [r7, #4]
|
|
|
8002106: 681b ldr r3, [r3, #0]
|
|
|
8002108: f003 0302 and.w r3, r3, #2
|
|
|
800210c: 2b00 cmp r3, #0
|
|
|
800210e: d010 beq.n 8002132 <HAL_RCC_ClockConfig+0x146>
|
|
|
{
|
|
|
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
|
8002110: 687b ldr r3, [r7, #4]
|
|
|
8002112: 689a ldr r2, [r3, #8]
|
|
|
8002114: 4b31 ldr r3, [pc, #196] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
8002116: 689b ldr r3, [r3, #8]
|
|
|
8002118: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
|
800211c: 429a cmp r2, r3
|
|
|
800211e: d208 bcs.n 8002132 <HAL_RCC_ClockConfig+0x146>
|
|
|
{
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
8002120: 4b2e ldr r3, [pc, #184] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
8002122: 689b ldr r3, [r3, #8]
|
|
|
8002124: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
8002128: 687b ldr r3, [r7, #4]
|
|
|
800212a: 689b ldr r3, [r3, #8]
|
|
|
800212c: 492b ldr r1, [pc, #172] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800212e: 4313 orrs r3, r2
|
|
|
8002130: 608b str r3, [r1, #8]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
|
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
|
8002132: 4b29 ldr r3, [pc, #164] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002134: 681b ldr r3, [r3, #0]
|
|
|
8002136: f003 0307 and.w r3, r3, #7
|
|
|
800213a: 683a ldr r2, [r7, #0]
|
|
|
800213c: 429a cmp r2, r3
|
|
|
800213e: d210 bcs.n 8002162 <HAL_RCC_ClockConfig+0x176>
|
|
|
{
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
8002140: 4b25 ldr r3, [pc, #148] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002142: 681b ldr r3, [r3, #0]
|
|
|
8002144: f023 0207 bic.w r2, r3, #7
|
|
|
8002148: 4923 ldr r1, [pc, #140] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
800214a: 683b ldr r3, [r7, #0]
|
|
|
800214c: 4313 orrs r3, r2
|
|
|
800214e: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
|
8002150: 4b21 ldr r3, [pc, #132] ; (80021d8 <HAL_RCC_ClockConfig+0x1ec>)
|
|
|
8002152: 681b ldr r3, [r3, #0]
|
|
|
8002154: f003 0307 and.w r3, r3, #7
|
|
|
8002158: 683a ldr r2, [r7, #0]
|
|
|
800215a: 429a cmp r2, r3
|
|
|
800215c: d001 beq.n 8002162 <HAL_RCC_ClockConfig+0x176>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800215e: 2301 movs r3, #1
|
|
|
8002160: e036 b.n 80021d0 <HAL_RCC_ClockConfig+0x1e4>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
|
8002162: 687b ldr r3, [r7, #4]
|
|
|
8002164: 681b ldr r3, [r3, #0]
|
|
|
8002166: f003 0304 and.w r3, r3, #4
|
|
|
800216a: 2b00 cmp r3, #0
|
|
|
800216c: d008 beq.n 8002180 <HAL_RCC_ClockConfig+0x194>
|
|
|
{
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
|
800216e: 4b1b ldr r3, [pc, #108] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
8002170: 689b ldr r3, [r3, #8]
|
|
|
8002172: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
|
8002176: 687b ldr r3, [r7, #4]
|
|
|
8002178: 68db ldr r3, [r3, #12]
|
|
|
800217a: 4918 ldr r1, [pc, #96] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800217c: 4313 orrs r3, r2
|
|
|
800217e: 608b str r3, [r1, #8]
|
|
|
}
|
|
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
|
8002180: 687b ldr r3, [r7, #4]
|
|
|
8002182: 681b ldr r3, [r3, #0]
|
|
|
8002184: f003 0308 and.w r3, r3, #8
|
|
|
8002188: 2b00 cmp r3, #0
|
|
|
800218a: d009 beq.n 80021a0 <HAL_RCC_ClockConfig+0x1b4>
|
|
|
{
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
|
800218c: 4b13 ldr r3, [pc, #76] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800218e: 689b ldr r3, [r3, #8]
|
|
|
8002190: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
|
8002194: 687b ldr r3, [r7, #4]
|
|
|
8002196: 691b ldr r3, [r3, #16]
|
|
|
8002198: 00db lsls r3, r3, #3
|
|
|
800219a: 4910 ldr r1, [pc, #64] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
800219c: 4313 orrs r3, r2
|
|
|
800219e: 608b str r3, [r1, #8]
|
|
|
}
|
|
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
|
80021a0: f000 f824 bl 80021ec <HAL_RCC_GetSysClockFreq>
|
|
|
80021a4: 4602 mov r2, r0
|
|
|
80021a6: 4b0d ldr r3, [pc, #52] ; (80021dc <HAL_RCC_ClockConfig+0x1f0>)
|
|
|
80021a8: 689b ldr r3, [r3, #8]
|
|
|
80021aa: 091b lsrs r3, r3, #4
|
|
|
80021ac: f003 030f and.w r3, r3, #15
|
|
|
80021b0: 490b ldr r1, [pc, #44] ; (80021e0 <HAL_RCC_ClockConfig+0x1f4>)
|
|
|
80021b2: 5ccb ldrb r3, [r1, r3]
|
|
|
80021b4: f003 031f and.w r3, r3, #31
|
|
|
80021b8: fa22 f303 lsr.w r3, r2, r3
|
|
|
80021bc: 4a09 ldr r2, [pc, #36] ; (80021e4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
|
80021be: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
|
status = HAL_InitTick(uwTickPrio);
|
|
|
80021c0: 4b09 ldr r3, [pc, #36] ; (80021e8 <HAL_RCC_ClockConfig+0x1fc>)
|
|
|
80021c2: 681b ldr r3, [r3, #0]
|
|
|
80021c4: 4618 mov r0, r3
|
|
|
80021c6: f7fe fedf bl 8000f88 <HAL_InitTick>
|
|
|
80021ca: 4603 mov r3, r0
|
|
|
80021cc: 72fb strb r3, [r7, #11]
|
|
|
|
|
|
return status;
|
|
|
80021ce: 7afb ldrb r3, [r7, #11]
|
|
|
}
|
|
|
80021d0: 4618 mov r0, r3
|
|
|
80021d2: 3710 adds r7, #16
|
|
|
80021d4: 46bd mov sp, r7
|
|
|
80021d6: bd80 pop {r7, pc}
|
|
|
80021d8: 40022000 .word 0x40022000
|
|
|
80021dc: 40021000 .word 0x40021000
|
|
|
80021e0: 08005c00 .word 0x08005c00
|
|
|
80021e4: 20000004 .word 0x20000004
|
|
|
80021e8: 20000008 .word 0x20000008
|
|
|
|
|
|
080021ec <HAL_RCC_GetSysClockFreq>:
|
|
|
*
|
|
|
*
|
|
|
* @retval SYSCLK frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
|
{
|
|
|
80021ec: b480 push {r7}
|
|
|
80021ee: b089 sub sp, #36 ; 0x24
|
|
|
80021f0: af00 add r7, sp, #0
|
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
|
|
80021f2: 2300 movs r3, #0
|
|
|
80021f4: 61fb str r3, [r7, #28]
|
|
|
80021f6: 2300 movs r3, #0
|
|
|
80021f8: 61bb str r3, [r7, #24]
|
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
|
|
uint32_t sysclk_source, pll_oscsource;
|
|
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
|
80021fa: 4b3e ldr r3, [pc, #248] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
80021fc: 689b ldr r3, [r3, #8]
|
|
|
80021fe: f003 030c and.w r3, r3, #12
|
|
|
8002202: 613b str r3, [r7, #16]
|
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
|
8002204: 4b3b ldr r3, [pc, #236] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
8002206: 68db ldr r3, [r3, #12]
|
|
|
8002208: f003 0303 and.w r3, r3, #3
|
|
|
800220c: 60fb str r3, [r7, #12]
|
|
|
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
|
800220e: 693b ldr r3, [r7, #16]
|
|
|
8002210: 2b00 cmp r3, #0
|
|
|
8002212: d005 beq.n 8002220 <HAL_RCC_GetSysClockFreq+0x34>
|
|
|
8002214: 693b ldr r3, [r7, #16]
|
|
|
8002216: 2b0c cmp r3, #12
|
|
|
8002218: d121 bne.n 800225e <HAL_RCC_GetSysClockFreq+0x72>
|
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
|
800221a: 68fb ldr r3, [r7, #12]
|
|
|
800221c: 2b01 cmp r3, #1
|
|
|
800221e: d11e bne.n 800225e <HAL_RCC_GetSysClockFreq+0x72>
|
|
|
{
|
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
|
|
/* Get SYSCLK source */
|
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
|
8002220: 4b34 ldr r3, [pc, #208] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
8002222: 681b ldr r3, [r3, #0]
|
|
|
8002224: f003 0308 and.w r3, r3, #8
|
|
|
8002228: 2b00 cmp r3, #0
|
|
|
800222a: d107 bne.n 800223c <HAL_RCC_GetSysClockFreq+0x50>
|
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
|
|
800222c: 4b31 ldr r3, [pc, #196] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
800222e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
|
8002232: 0a1b lsrs r3, r3, #8
|
|
|
8002234: f003 030f and.w r3, r3, #15
|
|
|
8002238: 61fb str r3, [r7, #28]
|
|
|
800223a: e005 b.n 8002248 <HAL_RCC_GetSysClockFreq+0x5c>
|
|
|
}
|
|
|
else
|
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
|
800223c: 4b2d ldr r3, [pc, #180] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
800223e: 681b ldr r3, [r3, #0]
|
|
|
8002240: 091b lsrs r3, r3, #4
|
|
|
8002242: f003 030f and.w r3, r3, #15
|
|
|
8002246: 61fb str r3, [r7, #28]
|
|
|
}
|
|
|
/*MSI frequency range in HZ*/
|
|
|
msirange = MSIRangeTable[msirange];
|
|
|
8002248: 4a2b ldr r2, [pc, #172] ; (80022f8 <HAL_RCC_GetSysClockFreq+0x10c>)
|
|
|
800224a: 69fb ldr r3, [r7, #28]
|
|
|
800224c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
|
8002250: 61fb str r3, [r7, #28]
|
|
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
|
8002252: 693b ldr r3, [r7, #16]
|
|
|
8002254: 2b00 cmp r3, #0
|
|
|
8002256: d10d bne.n 8002274 <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
{
|
|
|
/* MSI used as system clock source */
|
|
|
sysclockfreq = msirange;
|
|
|
8002258: 69fb ldr r3, [r7, #28]
|
|
|
800225a: 61bb str r3, [r7, #24]
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
|
800225c: e00a b.n 8002274 <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
}
|
|
|
}
|
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
|
|
800225e: 693b ldr r3, [r7, #16]
|
|
|
8002260: 2b04 cmp r3, #4
|
|
|
8002262: d102 bne.n 800226a <HAL_RCC_GetSysClockFreq+0x7e>
|
|
|
{
|
|
|
/* HSI used as system clock source */
|
|
|
sysclockfreq = HSI_VALUE;
|
|
|
8002264: 4b25 ldr r3, [pc, #148] ; (80022fc <HAL_RCC_GetSysClockFreq+0x110>)
|
|
|
8002266: 61bb str r3, [r7, #24]
|
|
|
8002268: e004 b.n 8002274 <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
}
|
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
|
|
800226a: 693b ldr r3, [r7, #16]
|
|
|
800226c: 2b08 cmp r3, #8
|
|
|
800226e: d101 bne.n 8002274 <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
{
|
|
|
/* HSE used as system clock source */
|
|
|
sysclockfreq = HSE_VALUE;
|
|
|
8002270: 4b23 ldr r3, [pc, #140] ; (8002300 <HAL_RCC_GetSysClockFreq+0x114>)
|
|
|
8002272: 61bb str r3, [r7, #24]
|
|
|
else
|
|
|
{
|
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
|
}
|
|
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
|
|
8002274: 693b ldr r3, [r7, #16]
|
|
|
8002276: 2b0c cmp r3, #12
|
|
|
8002278: d134 bne.n 80022e4 <HAL_RCC_GetSysClockFreq+0xf8>
|
|
|
/* PLL used as system clock source */
|
|
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
|
SYSCLK = PLL_VCO / PLLR
|
|
|
*/
|
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
|
800227a: 4b1e ldr r3, [pc, #120] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
800227c: 68db ldr r3, [r3, #12]
|
|
|
800227e: f003 0303 and.w r3, r3, #3
|
|
|
8002282: 60bb str r3, [r7, #8]
|
|
|
|
|
|
switch (pllsource)
|
|
|
8002284: 68bb ldr r3, [r7, #8]
|
|
|
8002286: 2b02 cmp r3, #2
|
|
|
8002288: d003 beq.n 8002292 <HAL_RCC_GetSysClockFreq+0xa6>
|
|
|
800228a: 68bb ldr r3, [r7, #8]
|
|
|
800228c: 2b03 cmp r3, #3
|
|
|
800228e: d003 beq.n 8002298 <HAL_RCC_GetSysClockFreq+0xac>
|
|
|
8002290: e005 b.n 800229e <HAL_RCC_GetSysClockFreq+0xb2>
|
|
|
{
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
|
pllvco = HSI_VALUE;
|
|
|
8002292: 4b1a ldr r3, [pc, #104] ; (80022fc <HAL_RCC_GetSysClockFreq+0x110>)
|
|
|
8002294: 617b str r3, [r7, #20]
|
|
|
break;
|
|
|
8002296: e005 b.n 80022a4 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
|
pllvco = HSE_VALUE;
|
|
|
8002298: 4b19 ldr r3, [pc, #100] ; (8002300 <HAL_RCC_GetSysClockFreq+0x114>)
|
|
|
800229a: 617b str r3, [r7, #20]
|
|
|
break;
|
|
|
800229c: e002 b.n 80022a4 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
|
default:
|
|
|
pllvco = msirange;
|
|
|
800229e: 69fb ldr r3, [r7, #28]
|
|
|
80022a0: 617b str r3, [r7, #20]
|
|
|
break;
|
|
|
80022a2: bf00 nop
|
|
|
}
|
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
|
80022a4: 4b13 ldr r3, [pc, #76] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
80022a6: 68db ldr r3, [r3, #12]
|
|
|
80022a8: 091b lsrs r3, r3, #4
|
|
|
80022aa: f003 0307 and.w r3, r3, #7
|
|
|
80022ae: 3301 adds r3, #1
|
|
|
80022b0: 607b str r3, [r7, #4]
|
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
|
|
80022b2: 4b10 ldr r3, [pc, #64] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
80022b4: 68db ldr r3, [r3, #12]
|
|
|
80022b6: 0a1b lsrs r3, r3, #8
|
|
|
80022b8: f003 037f and.w r3, r3, #127 ; 0x7f
|
|
|
80022bc: 697a ldr r2, [r7, #20]
|
|
|
80022be: fb03 f202 mul.w r2, r3, r2
|
|
|
80022c2: 687b ldr r3, [r7, #4]
|
|
|
80022c4: fbb2 f3f3 udiv r3, r2, r3
|
|
|
80022c8: 617b str r3, [r7, #20]
|
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
|
80022ca: 4b0a ldr r3, [pc, #40] ; (80022f4 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
|
80022cc: 68db ldr r3, [r3, #12]
|
|
|
80022ce: 0e5b lsrs r3, r3, #25
|
|
|
80022d0: f003 0303 and.w r3, r3, #3
|
|
|
80022d4: 3301 adds r3, #1
|
|
|
80022d6: 005b lsls r3, r3, #1
|
|
|
80022d8: 603b str r3, [r7, #0]
|
|
|
sysclockfreq = pllvco / pllr;
|
|
|
80022da: 697a ldr r2, [r7, #20]
|
|
|
80022dc: 683b ldr r3, [r7, #0]
|
|
|
80022de: fbb2 f3f3 udiv r3, r2, r3
|
|
|
80022e2: 61bb str r3, [r7, #24]
|
|
|
}
|
|
|
|
|
|
return sysclockfreq;
|
|
|
80022e4: 69bb ldr r3, [r7, #24]
|
|
|
}
|
|
|
80022e6: 4618 mov r0, r3
|
|
|
80022e8: 3724 adds r7, #36 ; 0x24
|
|
|
80022ea: 46bd mov sp, r7
|
|
|
80022ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80022f0: 4770 bx lr
|
|
|
80022f2: bf00 nop
|
|
|
80022f4: 40021000 .word 0x40021000
|
|
|
80022f8: 08005c18 .word 0x08005c18
|
|
|
80022fc: 00f42400 .word 0x00f42400
|
|
|
8002300: 007a1200 .word 0x007a1200
|
|
|
|
|
|
08002304 <HAL_RCC_GetHCLKFreq>:
|
|
|
*
|
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
|
* @retval HCLK frequency in Hz
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
|
{
|
|
|
8002304: b480 push {r7}
|
|
|
8002306: af00 add r7, sp, #0
|
|
|
return SystemCoreClock;
|
|
|
8002308: 4b03 ldr r3, [pc, #12] ; (8002318 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
|
800230a: 681b ldr r3, [r3, #0]
|
|
|
}
|
|
|
800230c: 4618 mov r0, r3
|
|
|
800230e: 46bd mov sp, r7
|
|
|
8002310: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8002314: 4770 bx lr
|
|
|
8002316: bf00 nop
|
|
|
8002318: 20000004 .word 0x20000004
|
|
|
|
|
|
0800231c <HAL_RCC_GetPCLK1Freq>:
|
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
* @retval PCLK1 frequency in Hz
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
|
{
|
|
|
800231c: b580 push {r7, lr}
|
|
|
800231e: af00 add r7, sp, #0
|
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
|
8002320: f7ff fff0 bl 8002304 <HAL_RCC_GetHCLKFreq>
|
|
|
8002324: 4602 mov r2, r0
|
|
|
8002326: 4b06 ldr r3, [pc, #24] ; (8002340 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
|
8002328: 689b ldr r3, [r3, #8]
|
|
|
800232a: 0a1b lsrs r3, r3, #8
|
|
|
800232c: f003 0307 and.w r3, r3, #7
|
|
|
8002330: 4904 ldr r1, [pc, #16] ; (8002344 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
|
8002332: 5ccb ldrb r3, [r1, r3]
|
|
|
8002334: f003 031f and.w r3, r3, #31
|
|
|
8002338: fa22 f303 lsr.w r3, r2, r3
|
|
|
}
|
|
|
800233c: 4618 mov r0, r3
|
|
|
800233e: bd80 pop {r7, pc}
|
|
|
8002340: 40021000 .word 0x40021000
|
|
|
8002344: 08005c10 .word 0x08005c10
|
|
|
|
|
|
08002348 <HAL_RCC_GetPCLK2Freq>:
|
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
* @retval PCLK2 frequency in Hz
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
|
{
|
|
|
8002348: b580 push {r7, lr}
|
|
|
800234a: af00 add r7, sp, #0
|
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
|
800234c: f7ff ffda bl 8002304 <HAL_RCC_GetHCLKFreq>
|
|
|
8002350: 4602 mov r2, r0
|
|
|
8002352: 4b06 ldr r3, [pc, #24] ; (800236c <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
|
8002354: 689b ldr r3, [r3, #8]
|
|
|
8002356: 0adb lsrs r3, r3, #11
|
|
|
8002358: f003 0307 and.w r3, r3, #7
|
|
|
800235c: 4904 ldr r1, [pc, #16] ; (8002370 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
|
800235e: 5ccb ldrb r3, [r1, r3]
|
|
|
8002360: f003 031f and.w r3, r3, #31
|
|
|
8002364: fa22 f303 lsr.w r3, r2, r3
|
|
|
}
|
|
|
8002368: 4618 mov r0, r3
|
|
|
800236a: bd80 pop {r7, pc}
|
|
|
800236c: 40021000 .word 0x40021000
|
|
|
8002370: 08005c10 .word 0x08005c10
|
|
|
|
|
|
08002374 <RCC_SetFlashLatencyFromMSIRange>:
|
|
|
voltage range.
|
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
|
{
|
|
|
8002374: b580 push {r7, lr}
|
|
|
8002376: b086 sub sp, #24
|
|
|
8002378: af00 add r7, sp, #0
|
|
|
800237a: 6078 str r0, [r7, #4]
|
|
|
uint32_t vos;
|
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
|
800237c: 2300 movs r3, #0
|
|
|
800237e: 613b str r3, [r7, #16]
|
|
|
|
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
|
8002380: 4b2a ldr r3, [pc, #168] ; (800242c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
|
8002382: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8002384: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8002388: 2b00 cmp r3, #0
|
|
|
800238a: d003 beq.n 8002394 <RCC_SetFlashLatencyFromMSIRange+0x20>
|
|
|
{
|
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
|
800238c: f7ff f9b6 bl 80016fc <HAL_PWREx_GetVoltageRange>
|
|
|
8002390: 6178 str r0, [r7, #20]
|
|
|
8002392: e014 b.n 80023be <RCC_SetFlashLatencyFromMSIRange+0x4a>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
8002394: 4b25 ldr r3, [pc, #148] ; (800242c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
|
8002396: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8002398: 4a24 ldr r2, [pc, #144] ; (800242c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
|
800239a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
800239e: 6593 str r3, [r2, #88] ; 0x58
|
|
|
80023a0: 4b22 ldr r3, [pc, #136] ; (800242c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
|
80023a2: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80023a4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
80023a8: 60fb str r3, [r7, #12]
|
|
|
80023aa: 68fb ldr r3, [r7, #12]
|
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
|
80023ac: f7ff f9a6 bl 80016fc <HAL_PWREx_GetVoltageRange>
|
|
|
80023b0: 6178 str r0, [r7, #20]
|
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
|
80023b2: 4b1e ldr r3, [pc, #120] ; (800242c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
|
80023b4: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80023b6: 4a1d ldr r2, [pc, #116] ; (800242c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
|
80023b8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
|
80023bc: 6593 str r3, [r2, #88] ; 0x58
|
|
|
}
|
|
|
|
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
|
80023be: 697b ldr r3, [r7, #20]
|
|
|
80023c0: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
|
80023c4: d10b bne.n 80023de <RCC_SetFlashLatencyFromMSIRange+0x6a>
|
|
|
{
|
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
|
80023c6: 687b ldr r3, [r7, #4]
|
|
|
80023c8: 2b80 cmp r3, #128 ; 0x80
|
|
|
80023ca: d919 bls.n 8002400 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
|
{
|
|
|
/* MSI > 16Mhz */
|
|
|
if(msirange > RCC_MSIRANGE_10)
|
|
|
80023cc: 687b ldr r3, [r7, #4]
|
|
|
80023ce: 2ba0 cmp r3, #160 ; 0xa0
|
|
|
80023d0: d902 bls.n 80023d8 <RCC_SetFlashLatencyFromMSIRange+0x64>
|
|
|
{
|
|
|
/* MSI 48Mhz */
|
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
|
80023d2: 2302 movs r3, #2
|
|
|
80023d4: 613b str r3, [r7, #16]
|
|
|
80023d6: e013 b.n 8002400 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* MSI 24Mhz or 32Mhz */
|
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
|
80023d8: 2301 movs r3, #1
|
|
|
80023da: 613b str r3, [r7, #16]
|
|
|
80023dc: e010 b.n 8002400 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
|
}
|
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
|
}
|
|
|
#else
|
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
|
80023de: 687b ldr r3, [r7, #4]
|
|
|
80023e0: 2b80 cmp r3, #128 ; 0x80
|
|
|
80023e2: d902 bls.n 80023ea <RCC_SetFlashLatencyFromMSIRange+0x76>
|
|
|
{
|
|
|
/* MSI > 16Mhz */
|
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
|
|
80023e4: 2303 movs r3, #3
|
|
|
80023e6: 613b str r3, [r7, #16]
|
|
|
80023e8: e00a b.n 8002400 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
if(msirange == RCC_MSIRANGE_8)
|
|
|
80023ea: 687b ldr r3, [r7, #4]
|
|
|
80023ec: 2b80 cmp r3, #128 ; 0x80
|
|
|
80023ee: d102 bne.n 80023f6 <RCC_SetFlashLatencyFromMSIRange+0x82>
|
|
|
{
|
|
|
/* MSI 16Mhz */
|
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
|
80023f0: 2302 movs r3, #2
|
|
|
80023f2: 613b str r3, [r7, #16]
|
|
|
80023f4: e004 b.n 8002400 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
|
}
|
|
|
else if(msirange == RCC_MSIRANGE_7)
|
|
|
80023f6: 687b ldr r3, [r7, #4]
|
|
|
80023f8: 2b70 cmp r3, #112 ; 0x70
|
|
|
80023fa: d101 bne.n 8002400 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
|
{
|
|
|
/* MSI 8Mhz */
|
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
|
80023fc: 2301 movs r3, #1
|
|
|
80023fe: 613b str r3, [r7, #16]
|
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
|
}
|
|
|
#endif
|
|
|
}
|
|
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
|
8002400: 4b0b ldr r3, [pc, #44] ; (8002430 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
|
8002402: 681b ldr r3, [r3, #0]
|
|
|
8002404: f023 0207 bic.w r2, r3, #7
|
|
|
8002408: 4909 ldr r1, [pc, #36] ; (8002430 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
|
800240a: 693b ldr r3, [r7, #16]
|
|
|
800240c: 4313 orrs r3, r2
|
|
|
800240e: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
|
8002410: 4b07 ldr r3, [pc, #28] ; (8002430 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
|
8002412: 681b ldr r3, [r3, #0]
|
|
|
8002414: f003 0307 and.w r3, r3, #7
|
|
|
8002418: 693a ldr r2, [r7, #16]
|
|
|
800241a: 429a cmp r2, r3
|
|
|
800241c: d001 beq.n 8002422 <RCC_SetFlashLatencyFromMSIRange+0xae>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800241e: 2301 movs r3, #1
|
|
|
8002420: e000 b.n 8002424 <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
8002422: 2300 movs r3, #0
|
|
|
}
|
|
|
8002424: 4618 mov r0, r3
|
|
|
8002426: 3718 adds r7, #24
|
|
|
8002428: 46bd mov sp, r7
|
|
|
800242a: bd80 pop {r7, pc}
|
|
|
800242c: 40021000 .word 0x40021000
|
|
|
8002430: 40022000 .word 0x40022000
|
|
|
|
|
|
08002434 <HAL_RCCEx_PeriphCLKConfig>:
|
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
|
*
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
|
{
|
|
|
8002434: b580 push {r7, lr}
|
|
|
8002436: b086 sub sp, #24
|
|
|
8002438: af00 add r7, sp, #0
|
|
|
800243a: 6078 str r0, [r7, #4]
|
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
|
800243c: 2300 movs r3, #0
|
|
|
800243e: 74fb strb r3, [r7, #19]
|
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
|
8002440: 2300 movs r3, #0
|
|
|
8002442: 74bb strb r3, [r7, #18]
|
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
|
|
#if defined(SAI1)
|
|
|
|
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
|
8002444: 687b ldr r3, [r7, #4]
|
|
|
8002446: 681b ldr r3, [r3, #0]
|
|
|
8002448: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
|
800244c: 2b00 cmp r3, #0
|
|
|
800244e: d031 beq.n 80024b4 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
|
|
8002450: 687b ldr r3, [r7, #4]
|
|
|
8002452: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
|
8002454: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
|
|
|
8002458: d01a beq.n 8002490 <HAL_RCCEx_PeriphCLKConfig+0x5c>
|
|
|
800245a: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
|
|
|
800245e: d814 bhi.n 800248a <HAL_RCCEx_PeriphCLKConfig+0x56>
|
|
|
8002460: 2b00 cmp r3, #0
|
|
|
8002462: d009 beq.n 8002478 <HAL_RCCEx_PeriphCLKConfig+0x44>
|
|
|
8002464: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
|
|
|
8002468: d10f bne.n 800248a <HAL_RCCEx_PeriphCLKConfig+0x56>
|
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
|
#else
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
|
|
800246a: 4b5d ldr r3, [pc, #372] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
800246c: 68db ldr r3, [r3, #12]
|
|
|
800246e: 4a5c ldr r2, [pc, #368] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
8002470: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
8002474: 60d3 str r3, [r2, #12]
|
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
|
break;
|
|
|
8002476: e00c b.n 8002492 <HAL_RCCEx_PeriphCLKConfig+0x5e>
|
|
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
|
8002478: 687b ldr r3, [r7, #4]
|
|
|
800247a: 3304 adds r3, #4
|
|
|
800247c: 2100 movs r1, #0
|
|
|
800247e: 4618 mov r0, r3
|
|
|
8002480: f000 f9f0 bl 8002864 <RCCEx_PLLSAI1_Config>
|
|
|
8002484: 4603 mov r3, r0
|
|
|
8002486: 74fb strb r3, [r7, #19]
|
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
|
break;
|
|
|
8002488: e003 b.n 8002492 <HAL_RCCEx_PeriphCLKConfig+0x5e>
|
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
ret = HAL_ERROR;
|
|
|
800248a: 2301 movs r3, #1
|
|
|
800248c: 74fb strb r3, [r7, #19]
|
|
|
break;
|
|
|
800248e: e000 b.n 8002492 <HAL_RCCEx_PeriphCLKConfig+0x5e>
|
|
|
break;
|
|
|
8002490: bf00 nop
|
|
|
}
|
|
|
|
|
|
if(ret == HAL_OK)
|
|
|
8002492: 7cfb ldrb r3, [r7, #19]
|
|
|
8002494: 2b00 cmp r3, #0
|
|
|
8002496: d10b bne.n 80024b0 <HAL_RCCEx_PeriphCLKConfig+0x7c>
|
|
|
{
|
|
|
/* Set the source of SAI1 clock*/
|
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
|
8002498: 4b51 ldr r3, [pc, #324] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
800249a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
800249e: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
|
|
|
80024a2: 687b ldr r3, [r7, #4]
|
|
|
80024a4: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
|
80024a6: 494e ldr r1, [pc, #312] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80024a8: 4313 orrs r3, r2
|
|
|
80024aa: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
80024ae: e001 b.n 80024b4 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* set overall return value */
|
|
|
status = ret;
|
|
|
80024b0: 7cfb ldrb r3, [r7, #19]
|
|
|
80024b2: 74bb strb r3, [r7, #18]
|
|
|
}
|
|
|
}
|
|
|
#endif /* SAI2 */
|
|
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
|
80024b4: 687b ldr r3, [r7, #4]
|
|
|
80024b6: 681b ldr r3, [r3, #0]
|
|
|
80024b8: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
80024bc: 2b00 cmp r3, #0
|
|
|
80024be: f000 809e beq.w 80025fe <HAL_RCCEx_PeriphCLKConfig+0x1ca>
|
|
|
{
|
|
|
FlagStatus pwrclkchanged = RESET;
|
|
|
80024c2: 2300 movs r3, #0
|
|
|
80024c4: 747b strb r3, [r7, #17]
|
|
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
|
|
/* Enable Power Clock */
|
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
|
80024c6: 4b46 ldr r3, [pc, #280] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80024c8: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80024ca: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
80024ce: 2b00 cmp r3, #0
|
|
|
80024d0: d101 bne.n 80024d6 <HAL_RCCEx_PeriphCLKConfig+0xa2>
|
|
|
80024d2: 2301 movs r3, #1
|
|
|
80024d4: e000 b.n 80024d8 <HAL_RCCEx_PeriphCLKConfig+0xa4>
|
|
|
80024d6: 2300 movs r3, #0
|
|
|
80024d8: 2b00 cmp r3, #0
|
|
|
80024da: d00d beq.n 80024f8 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
80024dc: 4b40 ldr r3, [pc, #256] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80024de: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80024e0: 4a3f ldr r2, [pc, #252] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80024e2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
80024e6: 6593 str r3, [r2, #88] ; 0x58
|
|
|
80024e8: 4b3d ldr r3, [pc, #244] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80024ea: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80024ec: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
80024f0: 60bb str r3, [r7, #8]
|
|
|
80024f2: 68bb ldr r3, [r7, #8]
|
|
|
pwrclkchanged = SET;
|
|
|
80024f4: 2301 movs r3, #1
|
|
|
80024f6: 747b strb r3, [r7, #17]
|
|
|
}
|
|
|
|
|
|
/* Enable write access to Backup domain */
|
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
|
80024f8: 4b3a ldr r3, [pc, #232] ; (80025e4 <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
|
|
|
80024fa: 681b ldr r3, [r3, #0]
|
|
|
80024fc: 4a39 ldr r2, [pc, #228] ; (80025e4 <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
|
|
|
80024fe: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
|
8002502: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8002504: f7fe fd90 bl 8001028 <HAL_GetTick>
|
|
|
8002508: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
|
800250a: e009 b.n 8002520 <HAL_RCCEx_PeriphCLKConfig+0xec>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
800250c: f7fe fd8c bl 8001028 <HAL_GetTick>
|
|
|
8002510: 4602 mov r2, r0
|
|
|
8002512: 68fb ldr r3, [r7, #12]
|
|
|
8002514: 1ad3 subs r3, r2, r3
|
|
|
8002516: 2b02 cmp r3, #2
|
|
|
8002518: d902 bls.n 8002520 <HAL_RCCEx_PeriphCLKConfig+0xec>
|
|
|
{
|
|
|
ret = HAL_TIMEOUT;
|
|
|
800251a: 2303 movs r3, #3
|
|
|
800251c: 74fb strb r3, [r7, #19]
|
|
|
break;
|
|
|
800251e: e005 b.n 800252c <HAL_RCCEx_PeriphCLKConfig+0xf8>
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
|
8002520: 4b30 ldr r3, [pc, #192] ; (80025e4 <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
|
|
|
8002522: 681b ldr r3, [r3, #0]
|
|
|
8002524: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8002528: 2b00 cmp r3, #0
|
|
|
800252a: d0ef beq.n 800250c <HAL_RCCEx_PeriphCLKConfig+0xd8>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if(ret == HAL_OK)
|
|
|
800252c: 7cfb ldrb r3, [r7, #19]
|
|
|
800252e: 2b00 cmp r3, #0
|
|
|
8002530: d15a bne.n 80025e8 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
|
|
|
{
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
|
8002532: 4b2b ldr r3, [pc, #172] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
8002534: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8002538: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
|
800253c: 617b str r3, [r7, #20]
|
|
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
|
800253e: 697b ldr r3, [r7, #20]
|
|
|
8002540: 2b00 cmp r3, #0
|
|
|
8002542: d01e beq.n 8002582 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|
|
8002544: 687b ldr r3, [r7, #4]
|
|
|
8002546: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
8002548: 697a ldr r2, [r7, #20]
|
|
|
800254a: 429a cmp r2, r3
|
|
|
800254c: d019 beq.n 8002582 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|
|
{
|
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
|
800254e: 4b24 ldr r3, [pc, #144] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
8002550: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8002554: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
|
8002558: 617b str r3, [r7, #20]
|
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
|
800255a: 4b21 ldr r3, [pc, #132] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
800255c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8002560: 4a1f ldr r2, [pc, #124] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
8002562: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
8002566: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
|
800256a: 4b1d ldr r3, [pc, #116] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
800256c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
8002570: 4a1b ldr r2, [pc, #108] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
8002572: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8002576: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
/* Restore the Content of BDCR register */
|
|
|
RCC->BDCR = tmpregister;
|
|
|
800257a: 4a19 ldr r2, [pc, #100] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
800257c: 697b ldr r3, [r7, #20]
|
|
|
800257e: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
|
|
}
|
|
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
|
8002582: 697b ldr r3, [r7, #20]
|
|
|
8002584: f003 0301 and.w r3, r3, #1
|
|
|
8002588: 2b00 cmp r3, #0
|
|
|
800258a: d016 beq.n 80025ba <HAL_RCCEx_PeriphCLKConfig+0x186>
|
|
|
{
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
800258c: f7fe fd4c bl 8001028 <HAL_GetTick>
|
|
|
8002590: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
/* Wait till LSE is ready */
|
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
|
8002592: e00b b.n 80025ac <HAL_RCCEx_PeriphCLKConfig+0x178>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
8002594: f7fe fd48 bl 8001028 <HAL_GetTick>
|
|
|
8002598: 4602 mov r2, r0
|
|
|
800259a: 68fb ldr r3, [r7, #12]
|
|
|
800259c: 1ad3 subs r3, r2, r3
|
|
|
800259e: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
80025a2: 4293 cmp r3, r2
|
|
|
80025a4: d902 bls.n 80025ac <HAL_RCCEx_PeriphCLKConfig+0x178>
|
|
|
{
|
|
|
ret = HAL_TIMEOUT;
|
|
|
80025a6: 2303 movs r3, #3
|
|
|
80025a8: 74fb strb r3, [r7, #19]
|
|
|
break;
|
|
|
80025aa: e006 b.n 80025ba <HAL_RCCEx_PeriphCLKConfig+0x186>
|
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
|
80025ac: 4b0c ldr r3, [pc, #48] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80025ae: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
80025b2: f003 0302 and.w r3, r3, #2
|
|
|
80025b6: 2b00 cmp r3, #0
|
|
|
80025b8: d0ec beq.n 8002594 <HAL_RCCEx_PeriphCLKConfig+0x160>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if(ret == HAL_OK)
|
|
|
80025ba: 7cfb ldrb r3, [r7, #19]
|
|
|
80025bc: 2b00 cmp r3, #0
|
|
|
80025be: d10b bne.n 80025d8 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
|
|
|
{
|
|
|
/* Apply new RTC clock source selection */
|
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
|
80025c0: 4b07 ldr r3, [pc, #28] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80025c2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
|
80025c6: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
|
80025ca: 687b ldr r3, [r7, #4]
|
|
|
80025cc: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80025ce: 4904 ldr r1, [pc, #16] ; (80025e0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
|
|
|
80025d0: 4313 orrs r3, r2
|
|
|
80025d2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
|
80025d6: e009 b.n 80025ec <HAL_RCCEx_PeriphCLKConfig+0x1b8>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* set overall return value */
|
|
|
status = ret;
|
|
|
80025d8: 7cfb ldrb r3, [r7, #19]
|
|
|
80025da: 74bb strb r3, [r7, #18]
|
|
|
80025dc: e006 b.n 80025ec <HAL_RCCEx_PeriphCLKConfig+0x1b8>
|
|
|
80025de: bf00 nop
|
|
|
80025e0: 40021000 .word 0x40021000
|
|
|
80025e4: 40007000 .word 0x40007000
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* set overall return value */
|
|
|
status = ret;
|
|
|
80025e8: 7cfb ldrb r3, [r7, #19]
|
|
|
80025ea: 74bb strb r3, [r7, #18]
|
|
|
}
|
|
|
|
|
|
/* Restore clock configuration if changed */
|
|
|
if(pwrclkchanged == SET)
|
|
|
80025ec: 7c7b ldrb r3, [r7, #17]
|
|
|
80025ee: 2b01 cmp r3, #1
|
|
|
80025f0: d105 bne.n 80025fe <HAL_RCCEx_PeriphCLKConfig+0x1ca>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
|
80025f2: 4b9b ldr r3, [pc, #620] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80025f4: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
|
80025f6: 4a9a ldr r2, [pc, #616] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80025f8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
|
80025fc: 6593 str r3, [r2, #88] ; 0x58
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
|
80025fe: 687b ldr r3, [r7, #4]
|
|
|
8002600: 681b ldr r3, [r3, #0]
|
|
|
8002602: f003 0301 and.w r3, r3, #1
|
|
|
8002606: 2b00 cmp r3, #0
|
|
|
8002608: d00a beq.n 8002620 <HAL_RCCEx_PeriphCLKConfig+0x1ec>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
|
|
/* Configure the USART1 clock source */
|
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
|
800260a: 4b95 ldr r3, [pc, #596] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800260c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002610: f023 0203 bic.w r2, r3, #3
|
|
|
8002614: 687b ldr r3, [r7, #4]
|
|
|
8002616: 6a1b ldr r3, [r3, #32]
|
|
|
8002618: 4991 ldr r1, [pc, #580] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800261a: 4313 orrs r3, r2
|
|
|
800261c: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
|
8002620: 687b ldr r3, [r7, #4]
|
|
|
8002622: 681b ldr r3, [r3, #0]
|
|
|
8002624: f003 0302 and.w r3, r3, #2
|
|
|
8002628: 2b00 cmp r3, #0
|
|
|
800262a: d00a beq.n 8002642 <HAL_RCCEx_PeriphCLKConfig+0x20e>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
|
|
/* Configure the USART2 clock source */
|
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
|
800262c: 4b8c ldr r3, [pc, #560] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800262e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002632: f023 020c bic.w r2, r3, #12
|
|
|
8002636: 687b ldr r3, [r7, #4]
|
|
|
8002638: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800263a: 4989 ldr r1, [pc, #548] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800263c: 4313 orrs r3, r2
|
|
|
800263e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
#if defined(USART3)
|
|
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
|
8002642: 687b ldr r3, [r7, #4]
|
|
|
8002644: 681b ldr r3, [r3, #0]
|
|
|
8002646: f003 0304 and.w r3, r3, #4
|
|
|
800264a: 2b00 cmp r3, #0
|
|
|
800264c: d00a beq.n 8002664 <HAL_RCCEx_PeriphCLKConfig+0x230>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
|
|
/* Configure the USART3 clock source */
|
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
|
800264e: 4b84 ldr r3, [pc, #528] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002650: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002654: f023 0230 bic.w r2, r3, #48 ; 0x30
|
|
|
8002658: 687b ldr r3, [r7, #4]
|
|
|
800265a: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
|
800265c: 4980 ldr r1, [pc, #512] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800265e: 4313 orrs r3, r2
|
|
|
8002660: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
#endif /* UART5 */
|
|
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
|
8002664: 687b ldr r3, [r7, #4]
|
|
|
8002666: 681b ldr r3, [r3, #0]
|
|
|
8002668: f003 0320 and.w r3, r3, #32
|
|
|
800266c: 2b00 cmp r3, #0
|
|
|
800266e: d00a beq.n 8002686 <HAL_RCCEx_PeriphCLKConfig+0x252>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
|
8002670: 4b7b ldr r3, [pc, #492] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002672: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002676: f423 6240 bic.w r2, r3, #3072 ; 0xc00
|
|
|
800267a: 687b ldr r3, [r7, #4]
|
|
|
800267c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
|
800267e: 4978 ldr r1, [pc, #480] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002680: 4313 orrs r3, r2
|
|
|
8002682: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
|
8002686: 687b ldr r3, [r7, #4]
|
|
|
8002688: 681b ldr r3, [r3, #0]
|
|
|
800268a: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
|
800268e: 2b00 cmp r3, #0
|
|
|
8002690: d00a beq.n 80026a8 <HAL_RCCEx_PeriphCLKConfig+0x274>
|
|
|
{
|
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
|
8002692: 4b73 ldr r3, [pc, #460] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002694: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002698: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
|
|
|
800269c: 687b ldr r3, [r7, #4]
|
|
|
800269e: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
|
80026a0: 496f ldr r1, [pc, #444] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80026a2: 4313 orrs r3, r2
|
|
|
80026a4: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
|
80026a8: 687b ldr r3, [r7, #4]
|
|
|
80026aa: 681b ldr r3, [r3, #0]
|
|
|
80026ac: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
80026b0: 2b00 cmp r3, #0
|
|
|
80026b2: d00a beq.n 80026ca <HAL_RCCEx_PeriphCLKConfig+0x296>
|
|
|
{
|
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
|
80026b4: 4b6a ldr r3, [pc, #424] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80026b6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80026ba: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
|
|
|
80026be: 687b ldr r3, [r7, #4]
|
|
|
80026c0: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
|
80026c2: 4967 ldr r1, [pc, #412] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80026c4: 4313 orrs r3, r2
|
|
|
80026c6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
|
80026ca: 687b ldr r3, [r7, #4]
|
|
|
80026cc: 681b ldr r3, [r3, #0]
|
|
|
80026ce: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
80026d2: 2b00 cmp r3, #0
|
|
|
80026d4: d00a beq.n 80026ec <HAL_RCCEx_PeriphCLKConfig+0x2b8>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
|
|
/* Configure the I2C1 clock source */
|
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
|
80026d6: 4b62 ldr r3, [pc, #392] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80026d8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80026dc: f423 5240 bic.w r2, r3, #12288 ; 0x3000
|
|
|
80026e0: 687b ldr r3, [r7, #4]
|
|
|
80026e2: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
|
80026e4: 495e ldr r1, [pc, #376] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80026e6: 4313 orrs r3, r2
|
|
|
80026e8: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
#if defined(I2C2)
|
|
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
|
80026ec: 687b ldr r3, [r7, #4]
|
|
|
80026ee: 681b ldr r3, [r3, #0]
|
|
|
80026f0: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
|
80026f4: 2b00 cmp r3, #0
|
|
|
80026f6: d00a beq.n 800270e <HAL_RCCEx_PeriphCLKConfig+0x2da>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
|
|
/* Configure the I2C2 clock source */
|
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
|
80026f8: 4b59 ldr r3, [pc, #356] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80026fa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80026fe: f423 4240 bic.w r2, r3, #49152 ; 0xc000
|
|
|
8002702: 687b ldr r3, [r7, #4]
|
|
|
8002704: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
|
8002706: 4956 ldr r1, [pc, #344] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002708: 4313 orrs r3, r2
|
|
|
800270a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
|
|
|
#endif /* I2C2 */
|
|
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
|
800270e: 687b ldr r3, [r7, #4]
|
|
|
8002710: 681b ldr r3, [r3, #0]
|
|
|
8002712: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8002716: 2b00 cmp r3, #0
|
|
|
8002718: d00a beq.n 8002730 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
|
|
/* Configure the I2C3 clock source */
|
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
|
800271a: 4b51 ldr r3, [pc, #324] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800271c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002720: f423 3240 bic.w r2, r3, #196608 ; 0x30000
|
|
|
8002724: 687b ldr r3, [r7, #4]
|
|
|
8002726: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
|
8002728: 494d ldr r1, [pc, #308] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800272a: 4313 orrs r3, r2
|
|
|
800272c: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
#endif /* USB_OTG_FS || USB */
|
|
|
|
|
|
#if defined(SDMMC1)
|
|
|
|
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
|
|
8002730: 687b ldr r3, [r7, #4]
|
|
|
8002732: 681b ldr r3, [r3, #0]
|
|
|
8002734: f403 2300 and.w r3, r3, #524288 ; 0x80000
|
|
|
8002738: 2b00 cmp r3, #0
|
|
|
800273a: d028 beq.n 800278e <HAL_RCCEx_PeriphCLKConfig+0x35a>
|
|
|
{
|
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
|
800273c: 4b48 ldr r3, [pc, #288] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800273e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002742: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
|
|
|
8002746: 687b ldr r3, [r7, #4]
|
|
|
8002748: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
|
800274a: 4945 ldr r1, [pc, #276] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800274c: 4313 orrs r3, r2
|
|
|
800274e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
|
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
|
|
8002752: 687b ldr r3, [r7, #4]
|
|
|
8002754: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
|
8002756: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
|
800275a: d106 bne.n 800276a <HAL_RCCEx_PeriphCLKConfig+0x336>
|
|
|
{
|
|
|
/* Enable PLL48M1CLK output clock */
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
|
800275c: 4b40 ldr r3, [pc, #256] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800275e: 68db ldr r3, [r3, #12]
|
|
|
8002760: 4a3f ldr r2, [pc, #252] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002762: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
|
|
8002766: 60d3 str r3, [r2, #12]
|
|
|
8002768: e011 b.n 800278e <HAL_RCCEx_PeriphCLKConfig+0x35a>
|
|
|
{
|
|
|
/* Enable PLLSAI3CLK output */
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
|
}
|
|
|
#endif
|
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
|
|
800276a: 687b ldr r3, [r7, #4]
|
|
|
800276c: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
|
800276e: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
|
|
8002772: d10c bne.n 800278e <HAL_RCCEx_PeriphCLKConfig+0x35a>
|
|
|
{
|
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
|
8002774: 687b ldr r3, [r7, #4]
|
|
|
8002776: 3304 adds r3, #4
|
|
|
8002778: 2101 movs r1, #1
|
|
|
800277a: 4618 mov r0, r3
|
|
|
800277c: f000 f872 bl 8002864 <RCCEx_PLLSAI1_Config>
|
|
|
8002780: 4603 mov r3, r0
|
|
|
8002782: 74fb strb r3, [r7, #19]
|
|
|
|
|
|
if(ret != HAL_OK)
|
|
|
8002784: 7cfb ldrb r3, [r7, #19]
|
|
|
8002786: 2b00 cmp r3, #0
|
|
|
8002788: d001 beq.n 800278e <HAL_RCCEx_PeriphCLKConfig+0x35a>
|
|
|
{
|
|
|
/* set overall return value */
|
|
|
status = ret;
|
|
|
800278a: 7cfb ldrb r3, [r7, #19]
|
|
|
800278c: 74bb strb r3, [r7, #18]
|
|
|
}
|
|
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
|
800278e: 687b ldr r3, [r7, #4]
|
|
|
8002790: 681b ldr r3, [r3, #0]
|
|
|
8002792: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
|
|
8002796: 2b00 cmp r3, #0
|
|
|
8002798: d028 beq.n 80027ec <HAL_RCCEx_PeriphCLKConfig+0x3b8>
|
|
|
{
|
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
|
800279a: 4b31 ldr r3, [pc, #196] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800279c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80027a0: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
|
|
|
80027a4: 687b ldr r3, [r7, #4]
|
|
|
80027a6: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
80027a8: 492d ldr r1, [pc, #180] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80027aa: 4313 orrs r3, r2
|
|
|
80027ac: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
|
80027b0: 687b ldr r3, [r7, #4]
|
|
|
80027b2: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
80027b4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
|
80027b8: d106 bne.n 80027c8 <HAL_RCCEx_PeriphCLKConfig+0x394>
|
|
|
{
|
|
|
/* Enable PLL48M1CLK output clock */
|
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
|
80027ba: 4b29 ldr r3, [pc, #164] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80027bc: 68db ldr r3, [r3, #12]
|
|
|
80027be: 4a28 ldr r2, [pc, #160] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80027c0: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
|
|
80027c4: 60d3 str r3, [r2, #12]
|
|
|
80027c6: e011 b.n 80027ec <HAL_RCCEx_PeriphCLKConfig+0x3b8>
|
|
|
}
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
|
|
80027c8: 687b ldr r3, [r7, #4]
|
|
|
80027ca: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
80027cc: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
|
|
80027d0: d10c bne.n 80027ec <HAL_RCCEx_PeriphCLKConfig+0x3b8>
|
|
|
{
|
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
|
80027d2: 687b ldr r3, [r7, #4]
|
|
|
80027d4: 3304 adds r3, #4
|
|
|
80027d6: 2101 movs r1, #1
|
|
|
80027d8: 4618 mov r0, r3
|
|
|
80027da: f000 f843 bl 8002864 <RCCEx_PLLSAI1_Config>
|
|
|
80027de: 4603 mov r3, r0
|
|
|
80027e0: 74fb strb r3, [r7, #19]
|
|
|
|
|
|
if(ret != HAL_OK)
|
|
|
80027e2: 7cfb ldrb r3, [r7, #19]
|
|
|
80027e4: 2b00 cmp r3, #0
|
|
|
80027e6: d001 beq.n 80027ec <HAL_RCCEx_PeriphCLKConfig+0x3b8>
|
|
|
{
|
|
|
/* set overall return value */
|
|
|
status = ret;
|
|
|
80027e8: 7cfb ldrb r3, [r7, #19]
|
|
|
80027ea: 74bb strb r3, [r7, #18]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
|
80027ec: 687b ldr r3, [r7, #4]
|
|
|
80027ee: 681b ldr r3, [r3, #0]
|
|
|
80027f0: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
|
80027f4: 2b00 cmp r3, #0
|
|
|
80027f6: d01c beq.n 8002832 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
|
|
/* Configure the ADC interface clock source */
|
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
|
80027f8: 4b19 ldr r3, [pc, #100] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
80027fa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80027fe: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
|
|
|
8002802: 687b ldr r3, [r7, #4]
|
|
|
8002804: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
|
8002806: 4916 ldr r1, [pc, #88] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002808: 4313 orrs r3, r2
|
|
|
800280a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
|
800280e: 687b ldr r3, [r7, #4]
|
|
|
8002810: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
|
8002812: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
|
|
|
8002816: d10c bne.n 8002832 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
|
|
|
{
|
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
|
|
8002818: 687b ldr r3, [r7, #4]
|
|
|
800281a: 3304 adds r3, #4
|
|
|
800281c: 2102 movs r1, #2
|
|
|
800281e: 4618 mov r0, r3
|
|
|
8002820: f000 f820 bl 8002864 <RCCEx_PLLSAI1_Config>
|
|
|
8002824: 4603 mov r3, r0
|
|
|
8002826: 74fb strb r3, [r7, #19]
|
|
|
|
|
|
if(ret != HAL_OK)
|
|
|
8002828: 7cfb ldrb r3, [r7, #19]
|
|
|
800282a: 2b00 cmp r3, #0
|
|
|
800282c: d001 beq.n 8002832 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
|
|
|
{
|
|
|
/* set overall return value */
|
|
|
status = ret;
|
|
|
800282e: 7cfb ldrb r3, [r7, #19]
|
|
|
8002830: 74bb strb r3, [r7, #18]
|
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
|
|
|
|
|
#if defined(SWPMI1)
|
|
|
|
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
|
|
8002832: 687b ldr r3, [r7, #4]
|
|
|
8002834: 681b ldr r3, [r3, #0]
|
|
|
8002836: f403 4300 and.w r3, r3, #32768 ; 0x8000
|
|
|
800283a: 2b00 cmp r3, #0
|
|
|
800283c: d00a beq.n 8002854 <HAL_RCCEx_PeriphCLKConfig+0x420>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
|
|
|
|
|
/* Configure the SWPMI1 clock source */
|
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
|
|
800283e: 4b08 ldr r3, [pc, #32] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
8002840: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8002844: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000
|
|
|
8002848: 687b ldr r3, [r7, #4]
|
|
|
800284a: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
800284c: 4904 ldr r1, [pc, #16] ; (8002860 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
|
|
|
800284e: 4313 orrs r3, r2
|
|
|
8002850: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
}
|
|
|
}
|
|
|
|
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
|
|
|
|
|
return status;
|
|
|
8002854: 7cbb ldrb r3, [r7, #18]
|
|
|
}
|
|
|
8002856: 4618 mov r0, r3
|
|
|
8002858: 3718 adds r7, #24
|
|
|
800285a: 46bd mov sp, r7
|
|
|
800285c: bd80 pop {r7, pc}
|
|
|
800285e: bf00 nop
|
|
|
8002860: 40021000 .word 0x40021000
|
|
|
|
|
|
08002864 <RCCEx_PLLSAI1_Config>:
|
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
|
*
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
|
|
{
|
|
|
8002864: b580 push {r7, lr}
|
|
|
8002866: b084 sub sp, #16
|
|
|
8002868: af00 add r7, sp, #0
|
|
|
800286a: 6078 str r0, [r7, #4]
|
|
|
800286c: 6039 str r1, [r7, #0]
|
|
|
uint32_t tickstart;
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
800286e: 2300 movs r3, #0
|
|
|
8002870: 73fb strb r3, [r7, #15]
|
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
|
|
|
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
|
8002872: 4b74 ldr r3, [pc, #464] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002874: 68db ldr r3, [r3, #12]
|
|
|
8002876: f003 0303 and.w r3, r3, #3
|
|
|
800287a: 2b00 cmp r3, #0
|
|
|
800287c: d018 beq.n 80028b0 <RCCEx_PLLSAI1_Config+0x4c>
|
|
|
{
|
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
|
|
800287e: 4b71 ldr r3, [pc, #452] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002880: 68db ldr r3, [r3, #12]
|
|
|
8002882: f003 0203 and.w r2, r3, #3
|
|
|
8002886: 687b ldr r3, [r7, #4]
|
|
|
8002888: 681b ldr r3, [r3, #0]
|
|
|
800288a: 429a cmp r2, r3
|
|
|
800288c: d10d bne.n 80028aa <RCCEx_PLLSAI1_Config+0x46>
|
|
|
||
|
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
|
|
800288e: 687b ldr r3, [r7, #4]
|
|
|
8002890: 681b ldr r3, [r3, #0]
|
|
|
||
|
|
|
8002892: 2b00 cmp r3, #0
|
|
|
8002894: d009 beq.n 80028aa <RCCEx_PLLSAI1_Config+0x46>
|
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
|
||
|
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
|
|
8002896: 4b6b ldr r3, [pc, #428] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002898: 68db ldr r3, [r3, #12]
|
|
|
800289a: 091b lsrs r3, r3, #4
|
|
|
800289c: f003 0307 and.w r3, r3, #7
|
|
|
80028a0: 1c5a adds r2, r3, #1
|
|
|
80028a2: 687b ldr r3, [r7, #4]
|
|
|
80028a4: 685b ldr r3, [r3, #4]
|
|
|
||
|
|
|
80028a6: 429a cmp r2, r3
|
|
|
80028a8: d047 beq.n 800293a <RCCEx_PLLSAI1_Config+0xd6>
|
|
|
#endif
|
|
|
)
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
80028aa: 2301 movs r3, #1
|
|
|
80028ac: 73fb strb r3, [r7, #15]
|
|
|
80028ae: e044 b.n 800293a <RCCEx_PLLSAI1_Config+0xd6>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check PLLSAI1 clock source availability */
|
|
|
switch(PllSai1->PLLSAI1Source)
|
|
|
80028b0: 687b ldr r3, [r7, #4]
|
|
|
80028b2: 681b ldr r3, [r3, #0]
|
|
|
80028b4: 2b03 cmp r3, #3
|
|
|
80028b6: d018 beq.n 80028ea <RCCEx_PLLSAI1_Config+0x86>
|
|
|
80028b8: 2b03 cmp r3, #3
|
|
|
80028ba: d825 bhi.n 8002908 <RCCEx_PLLSAI1_Config+0xa4>
|
|
|
80028bc: 2b01 cmp r3, #1
|
|
|
80028be: d002 beq.n 80028c6 <RCCEx_PLLSAI1_Config+0x62>
|
|
|
80028c0: 2b02 cmp r3, #2
|
|
|
80028c2: d009 beq.n 80028d8 <RCCEx_PLLSAI1_Config+0x74>
|
|
|
80028c4: e020 b.n 8002908 <RCCEx_PLLSAI1_Config+0xa4>
|
|
|
{
|
|
|
case RCC_PLLSOURCE_MSI:
|
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
|
80028c6: 4b5f ldr r3, [pc, #380] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80028c8: 681b ldr r3, [r3, #0]
|
|
|
80028ca: f003 0302 and.w r3, r3, #2
|
|
|
80028ce: 2b00 cmp r3, #0
|
|
|
80028d0: d11d bne.n 800290e <RCCEx_PLLSAI1_Config+0xaa>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
80028d2: 2301 movs r3, #1
|
|
|
80028d4: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
break;
|
|
|
80028d6: e01a b.n 800290e <RCCEx_PLLSAI1_Config+0xaa>
|
|
|
case RCC_PLLSOURCE_HSI:
|
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
|
80028d8: 4b5a ldr r3, [pc, #360] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80028da: 681b ldr r3, [r3, #0]
|
|
|
80028dc: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
|
80028e0: 2b00 cmp r3, #0
|
|
|
80028e2: d116 bne.n 8002912 <RCCEx_PLLSAI1_Config+0xae>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
80028e4: 2301 movs r3, #1
|
|
|
80028e6: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
break;
|
|
|
80028e8: e013 b.n 8002912 <RCCEx_PLLSAI1_Config+0xae>
|
|
|
case RCC_PLLSOURCE_HSE:
|
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
|
80028ea: 4b56 ldr r3, [pc, #344] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80028ec: 681b ldr r3, [r3, #0]
|
|
|
80028ee: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
80028f2: 2b00 cmp r3, #0
|
|
|
80028f4: d10f bne.n 8002916 <RCCEx_PLLSAI1_Config+0xb2>
|
|
|
{
|
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
|
80028f6: 4b53 ldr r3, [pc, #332] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80028f8: 681b ldr r3, [r3, #0]
|
|
|
80028fa: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
|
|
80028fe: 2b00 cmp r3, #0
|
|
|
8002900: d109 bne.n 8002916 <RCCEx_PLLSAI1_Config+0xb2>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8002902: 2301 movs r3, #1
|
|
|
8002904: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
}
|
|
|
break;
|
|
|
8002906: e006 b.n 8002916 <RCCEx_PLLSAI1_Config+0xb2>
|
|
|
default:
|
|
|
status = HAL_ERROR;
|
|
|
8002908: 2301 movs r3, #1
|
|
|
800290a: 73fb strb r3, [r7, #15]
|
|
|
break;
|
|
|
800290c: e004 b.n 8002918 <RCCEx_PLLSAI1_Config+0xb4>
|
|
|
break;
|
|
|
800290e: bf00 nop
|
|
|
8002910: e002 b.n 8002918 <RCCEx_PLLSAI1_Config+0xb4>
|
|
|
break;
|
|
|
8002912: bf00 nop
|
|
|
8002914: e000 b.n 8002918 <RCCEx_PLLSAI1_Config+0xb4>
|
|
|
break;
|
|
|
8002916: bf00 nop
|
|
|
}
|
|
|
|
|
|
if(status == HAL_OK)
|
|
|
8002918: 7bfb ldrb r3, [r7, #15]
|
|
|
800291a: 2b00 cmp r3, #0
|
|
|
800291c: d10d bne.n 800293a <RCCEx_PLLSAI1_Config+0xd6>
|
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
|
/* Set PLLSAI1 clock source */
|
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
|
|
#else
|
|
|
/* Set PLLSAI1 clock source and divider M */
|
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
|
800291e: 4b49 ldr r3, [pc, #292] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002920: 68db ldr r3, [r3, #12]
|
|
|
8002922: f023 0273 bic.w r2, r3, #115 ; 0x73
|
|
|
8002926: 687b ldr r3, [r7, #4]
|
|
|
8002928: 6819 ldr r1, [r3, #0]
|
|
|
800292a: 687b ldr r3, [r7, #4]
|
|
|
800292c: 685b ldr r3, [r3, #4]
|
|
|
800292e: 3b01 subs r3, #1
|
|
|
8002930: 011b lsls r3, r3, #4
|
|
|
8002932: 430b orrs r3, r1
|
|
|
8002934: 4943 ldr r1, [pc, #268] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002936: 4313 orrs r3, r2
|
|
|
8002938: 60cb str r3, [r1, #12]
|
|
|
#endif
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if(status == HAL_OK)
|
|
|
800293a: 7bfb ldrb r3, [r7, #15]
|
|
|
800293c: 2b00 cmp r3, #0
|
|
|
800293e: d17c bne.n 8002a3a <RCCEx_PLLSAI1_Config+0x1d6>
|
|
|
{
|
|
|
/* Disable the PLLSAI1 */
|
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
|
8002940: 4b40 ldr r3, [pc, #256] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002942: 681b ldr r3, [r3, #0]
|
|
|
8002944: 4a3f ldr r2, [pc, #252] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002946: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
|
|
|
800294a: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
800294c: f7fe fb6c bl 8001028 <HAL_GetTick>
|
|
|
8002950: 60b8 str r0, [r7, #8]
|
|
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
|
8002952: e009 b.n 8002968 <RCCEx_PLLSAI1_Config+0x104>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
|
8002954: f7fe fb68 bl 8001028 <HAL_GetTick>
|
|
|
8002958: 4602 mov r2, r0
|
|
|
800295a: 68bb ldr r3, [r7, #8]
|
|
|
800295c: 1ad3 subs r3, r2, r3
|
|
|
800295e: 2b02 cmp r3, #2
|
|
|
8002960: d902 bls.n 8002968 <RCCEx_PLLSAI1_Config+0x104>
|
|
|
{
|
|
|
status = HAL_TIMEOUT;
|
|
|
8002962: 2303 movs r3, #3
|
|
|
8002964: 73fb strb r3, [r7, #15]
|
|
|
break;
|
|
|
8002966: e005 b.n 8002974 <RCCEx_PLLSAI1_Config+0x110>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
|
8002968: 4b36 ldr r3, [pc, #216] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
800296a: 681b ldr r3, [r3, #0]
|
|
|
800296c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
|
8002970: 2b00 cmp r3, #0
|
|
|
8002972: d1ef bne.n 8002954 <RCCEx_PLLSAI1_Config+0xf0>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if(status == HAL_OK)
|
|
|
8002974: 7bfb ldrb r3, [r7, #15]
|
|
|
8002976: 2b00 cmp r3, #0
|
|
|
8002978: d15f bne.n 8002a3a <RCCEx_PLLSAI1_Config+0x1d6>
|
|
|
{
|
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
|
800297a: 683b ldr r3, [r7, #0]
|
|
|
800297c: 2b00 cmp r3, #0
|
|
|
800297e: d110 bne.n 80029a2 <RCCEx_PLLSAI1_Config+0x13e>
|
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
|
|
#else
|
|
|
/* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
|
|
|
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
|
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
|
8002980: 4b30 ldr r3, [pc, #192] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002982: 691b ldr r3, [r3, #16]
|
|
|
8002984: f023 4378 bic.w r3, r3, #4160749568 ; 0xf8000000
|
|
|
8002988: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
|
|
800298c: 687a ldr r2, [r7, #4]
|
|
|
800298e: 6892 ldr r2, [r2, #8]
|
|
|
8002990: 0211 lsls r1, r2, #8
|
|
|
8002992: 687a ldr r2, [r7, #4]
|
|
|
8002994: 68d2 ldr r2, [r2, #12]
|
|
|
8002996: 06d2 lsls r2, r2, #27
|
|
|
8002998: 430a orrs r2, r1
|
|
|
800299a: 492a ldr r1, [pc, #168] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
800299c: 4313 orrs r3, r2
|
|
|
800299e: 610b str r3, [r1, #16]
|
|
|
80029a0: e027 b.n 80029f2 <RCCEx_PLLSAI1_Config+0x18e>
|
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
|
}
|
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
|
|
80029a2: 683b ldr r3, [r7, #0]
|
|
|
80029a4: 2b01 cmp r3, #1
|
|
|
80029a6: d112 bne.n 80029ce <RCCEx_PLLSAI1_Config+0x16a>
|
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
|
#else
|
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
|
80029a8: 4b26 ldr r3, [pc, #152] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80029aa: 691b ldr r3, [r3, #16]
|
|
|
80029ac: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000
|
|
|
80029b0: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
|
|
80029b4: 687a ldr r2, [r7, #4]
|
|
|
80029b6: 6892 ldr r2, [r2, #8]
|
|
|
80029b8: 0211 lsls r1, r2, #8
|
|
|
80029ba: 687a ldr r2, [r7, #4]
|
|
|
80029bc: 6912 ldr r2, [r2, #16]
|
|
|
80029be: 0852 lsrs r2, r2, #1
|
|
|
80029c0: 3a01 subs r2, #1
|
|
|
80029c2: 0552 lsls r2, r2, #21
|
|
|
80029c4: 430a orrs r2, r1
|
|
|
80029c6: 491f ldr r1, [pc, #124] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80029c8: 4313 orrs r3, r2
|
|
|
80029ca: 610b str r3, [r1, #16]
|
|
|
80029cc: e011 b.n 80029f2 <RCCEx_PLLSAI1_Config+0x18e>
|
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
|
#else
|
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
|
80029ce: 4b1d ldr r3, [pc, #116] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80029d0: 691b ldr r3, [r3, #16]
|
|
|
80029d2: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000
|
|
|
80029d6: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
|
|
80029da: 687a ldr r2, [r7, #4]
|
|
|
80029dc: 6892 ldr r2, [r2, #8]
|
|
|
80029de: 0211 lsls r1, r2, #8
|
|
|
80029e0: 687a ldr r2, [r7, #4]
|
|
|
80029e2: 6952 ldr r2, [r2, #20]
|
|
|
80029e4: 0852 lsrs r2, r2, #1
|
|
|
80029e6: 3a01 subs r2, #1
|
|
|
80029e8: 0652 lsls r2, r2, #25
|
|
|
80029ea: 430a orrs r2, r1
|
|
|
80029ec: 4915 ldr r1, [pc, #84] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80029ee: 4313 orrs r3, r2
|
|
|
80029f0: 610b str r3, [r1, #16]
|
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
|
}
|
|
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
|
80029f2: 4b14 ldr r3, [pc, #80] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80029f4: 681b ldr r3, [r3, #0]
|
|
|
80029f6: 4a13 ldr r2, [pc, #76] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
80029f8: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
|
|
80029fc: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Get Start Tick*/
|
|
|
tickstart = HAL_GetTick();
|
|
|
80029fe: f7fe fb13 bl 8001028 <HAL_GetTick>
|
|
|
8002a02: 60b8 str r0, [r7, #8]
|
|
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
|
8002a04: e009 b.n 8002a1a <RCCEx_PLLSAI1_Config+0x1b6>
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
|
8002a06: f7fe fb0f bl 8001028 <HAL_GetTick>
|
|
|
8002a0a: 4602 mov r2, r0
|
|
|
8002a0c: 68bb ldr r3, [r7, #8]
|
|
|
8002a0e: 1ad3 subs r3, r2, r3
|
|
|
8002a10: 2b02 cmp r3, #2
|
|
|
8002a12: d902 bls.n 8002a1a <RCCEx_PLLSAI1_Config+0x1b6>
|
|
|
{
|
|
|
status = HAL_TIMEOUT;
|
|
|
8002a14: 2303 movs r3, #3
|
|
|
8002a16: 73fb strb r3, [r7, #15]
|
|
|
break;
|
|
|
8002a18: e005 b.n 8002a26 <RCCEx_PLLSAI1_Config+0x1c2>
|
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
|
8002a1a: 4b0a ldr r3, [pc, #40] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002a1c: 681b ldr r3, [r3, #0]
|
|
|
8002a1e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
|
8002a22: 2b00 cmp r3, #0
|
|
|
8002a24: d0ef beq.n 8002a06 <RCCEx_PLLSAI1_Config+0x1a2>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if(status == HAL_OK)
|
|
|
8002a26: 7bfb ldrb r3, [r7, #15]
|
|
|
8002a28: 2b00 cmp r3, #0
|
|
|
8002a2a: d106 bne.n 8002a3a <RCCEx_PLLSAI1_Config+0x1d6>
|
|
|
{
|
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
|
|
8002a2c: 4b05 ldr r3, [pc, #20] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002a2e: 691a ldr r2, [r3, #16]
|
|
|
8002a30: 687b ldr r3, [r7, #4]
|
|
|
8002a32: 699b ldr r3, [r3, #24]
|
|
|
8002a34: 4903 ldr r1, [pc, #12] ; (8002a44 <RCCEx_PLLSAI1_Config+0x1e0>)
|
|
|
8002a36: 4313 orrs r3, r2
|
|
|
8002a38: 610b str r3, [r1, #16]
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return status;
|
|
|
8002a3a: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
8002a3c: 4618 mov r0, r3
|
|
|
8002a3e: 3710 adds r7, #16
|
|
|
8002a40: 46bd mov sp, r7
|
|
|
8002a42: bd80 pop {r7, pc}
|
|
|
8002a44: 40021000 .word 0x40021000
|
|
|
|
|
|
08002a48 <HAL_TIM_Base_Init>:
|
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
|
* @param htim TIM Base handle
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
|
{
|
|
|
8002a48: b580 push {r7, lr}
|
|
|
8002a4a: b082 sub sp, #8
|
|
|
8002a4c: af00 add r7, sp, #0
|
|
|
8002a4e: 6078 str r0, [r7, #4]
|
|
|
/* Check the TIM handle allocation */
|
|
|
if (htim == NULL)
|
|
|
8002a50: 687b ldr r3, [r7, #4]
|
|
|
8002a52: 2b00 cmp r3, #0
|
|
|
8002a54: d101 bne.n 8002a5a <HAL_TIM_Base_Init+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8002a56: 2301 movs r3, #1
|
|
|
8002a58: e049 b.n 8002aee <HAL_TIM_Base_Init+0xa6>
|
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
|
8002a5a: 687b ldr r3, [r7, #4]
|
|
|
8002a5c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8002a60: b2db uxtb r3, r3
|
|
|
8002a62: 2b00 cmp r3, #0
|
|
|
8002a64: d106 bne.n 8002a74 <HAL_TIM_Base_Init+0x2c>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
htim->Lock = HAL_UNLOCKED;
|
|
|
8002a66: 687b ldr r3, [r7, #4]
|
|
|
8002a68: 2200 movs r2, #0
|
|
|
8002a6a: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
}
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
|
htim->Base_MspInitCallback(htim);
|
|
|
#else
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
|
HAL_TIM_Base_MspInit(htim);
|
|
|
8002a6e: 6878 ldr r0, [r7, #4]
|
|
|
8002a70: f7fe f8fc bl 8000c6c <HAL_TIM_Base_MspInit>
|
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
|
}
|
|
|
|
|
|
/* Set the TIM state */
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8002a74: 687b ldr r3, [r7, #4]
|
|
|
8002a76: 2202 movs r2, #2
|
|
|
8002a78: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Set the Time Base configuration */
|
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
8002a7c: 687b ldr r3, [r7, #4]
|
|
|
8002a7e: 681a ldr r2, [r3, #0]
|
|
|
8002a80: 687b ldr r3, [r7, #4]
|
|
|
8002a82: 3304 adds r3, #4
|
|
|
8002a84: 4619 mov r1, r3
|
|
|
8002a86: 4610 mov r0, r2
|
|
|
8002a88: f000 fa74 bl 8002f74 <TIM_Base_SetConfig>
|
|
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
|
8002a8c: 687b ldr r3, [r7, #4]
|
|
|
8002a8e: 2201 movs r2, #1
|
|
|
8002a90: f883 2048 strb.w r2, [r3, #72] ; 0x48
|
|
|
|
|
|
/* Initialize the TIM channels state */
|
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
|
8002a94: 687b ldr r3, [r7, #4]
|
|
|
8002a96: 2201 movs r2, #1
|
|
|
8002a98: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
8002a9c: 687b ldr r3, [r7, #4]
|
|
|
8002a9e: 2201 movs r2, #1
|
|
|
8002aa0: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
|
8002aa4: 687b ldr r3, [r7, #4]
|
|
|
8002aa6: 2201 movs r2, #1
|
|
|
8002aa8: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
8002aac: 687b ldr r3, [r7, #4]
|
|
|
8002aae: 2201 movs r2, #1
|
|
|
8002ab0: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
8002ab4: 687b ldr r3, [r7, #4]
|
|
|
8002ab6: 2201 movs r2, #1
|
|
|
8002ab8: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
8002abc: 687b ldr r3, [r7, #4]
|
|
|
8002abe: 2201 movs r2, #1
|
|
|
8002ac0: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
|
8002ac4: 687b ldr r3, [r7, #4]
|
|
|
8002ac6: 2201 movs r2, #1
|
|
|
8002ac8: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
8002acc: 687b ldr r3, [r7, #4]
|
|
|
8002ace: 2201 movs r2, #1
|
|
|
8002ad0: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
8002ad4: 687b ldr r3, [r7, #4]
|
|
|
8002ad6: 2201 movs r2, #1
|
|
|
8002ad8: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
|
8002adc: 687b ldr r3, [r7, #4]
|
|
|
8002ade: 2201 movs r2, #1
|
|
|
8002ae0: f883 2047 strb.w r2, [r3, #71] ; 0x47
|
|
|
|
|
|
/* Initialize the TIM state*/
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
8002ae4: 687b ldr r3, [r7, #4]
|
|
|
8002ae6: 2201 movs r2, #1
|
|
|
8002ae8: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
return HAL_OK;
|
|
|
8002aec: 2300 movs r3, #0
|
|
|
}
|
|
|
8002aee: 4618 mov r0, r3
|
|
|
8002af0: 3708 adds r7, #8
|
|
|
8002af2: 46bd mov sp, r7
|
|
|
8002af4: bd80 pop {r7, pc}
|
|
|
|
|
|
08002af6 <HAL_TIM_PWM_Init>:
|
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
|
* @param htim TIM PWM handle
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
|
{
|
|
|
8002af6: b580 push {r7, lr}
|
|
|
8002af8: b082 sub sp, #8
|
|
|
8002afa: af00 add r7, sp, #0
|
|
|
8002afc: 6078 str r0, [r7, #4]
|
|
|
/* Check the TIM handle allocation */
|
|
|
if (htim == NULL)
|
|
|
8002afe: 687b ldr r3, [r7, #4]
|
|
|
8002b00: 2b00 cmp r3, #0
|
|
|
8002b02: d101 bne.n 8002b08 <HAL_TIM_PWM_Init+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8002b04: 2301 movs r3, #1
|
|
|
8002b06: e049 b.n 8002b9c <HAL_TIM_PWM_Init+0xa6>
|
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
|
8002b08: 687b ldr r3, [r7, #4]
|
|
|
8002b0a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8002b0e: b2db uxtb r3, r3
|
|
|
8002b10: 2b00 cmp r3, #0
|
|
|
8002b12: d106 bne.n 8002b22 <HAL_TIM_PWM_Init+0x2c>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
htim->Lock = HAL_UNLOCKED;
|
|
|
8002b14: 687b ldr r3, [r7, #4]
|
|
|
8002b16: 2200 movs r2, #0
|
|
|
8002b18: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
}
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
|
htim->PWM_MspInitCallback(htim);
|
|
|
#else
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
|
8002b1c: 6878 ldr r0, [r7, #4]
|
|
|
8002b1e: f000 f841 bl 8002ba4 <HAL_TIM_PWM_MspInit>
|
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
|
}
|
|
|
|
|
|
/* Set the TIM state */
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8002b22: 687b ldr r3, [r7, #4]
|
|
|
8002b24: 2202 movs r2, #2
|
|
|
8002b26: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Init the base time for the PWM */
|
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
8002b2a: 687b ldr r3, [r7, #4]
|
|
|
8002b2c: 681a ldr r2, [r3, #0]
|
|
|
8002b2e: 687b ldr r3, [r7, #4]
|
|
|
8002b30: 3304 adds r3, #4
|
|
|
8002b32: 4619 mov r1, r3
|
|
|
8002b34: 4610 mov r0, r2
|
|
|
8002b36: f000 fa1d bl 8002f74 <TIM_Base_SetConfig>
|
|
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
|
8002b3a: 687b ldr r3, [r7, #4]
|
|
|
8002b3c: 2201 movs r2, #1
|
|
|
8002b3e: f883 2048 strb.w r2, [r3, #72] ; 0x48
|
|
|
|
|
|
/* Initialize the TIM channels state */
|
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
|
8002b42: 687b ldr r3, [r7, #4]
|
|
|
8002b44: 2201 movs r2, #1
|
|
|
8002b46: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
8002b4a: 687b ldr r3, [r7, #4]
|
|
|
8002b4c: 2201 movs r2, #1
|
|
|
8002b4e: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
|
8002b52: 687b ldr r3, [r7, #4]
|
|
|
8002b54: 2201 movs r2, #1
|
|
|
8002b56: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
8002b5a: 687b ldr r3, [r7, #4]
|
|
|
8002b5c: 2201 movs r2, #1
|
|
|
8002b5e: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
8002b62: 687b ldr r3, [r7, #4]
|
|
|
8002b64: 2201 movs r2, #1
|
|
|
8002b66: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
8002b6a: 687b ldr r3, [r7, #4]
|
|
|
8002b6c: 2201 movs r2, #1
|
|
|
8002b6e: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
|
8002b72: 687b ldr r3, [r7, #4]
|
|
|
8002b74: 2201 movs r2, #1
|
|
|
8002b76: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
8002b7a: 687b ldr r3, [r7, #4]
|
|
|
8002b7c: 2201 movs r2, #1
|
|
|
8002b7e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
8002b82: 687b ldr r3, [r7, #4]
|
|
|
8002b84: 2201 movs r2, #1
|
|
|
8002b86: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
|
8002b8a: 687b ldr r3, [r7, #4]
|
|
|
8002b8c: 2201 movs r2, #1
|
|
|
8002b8e: f883 2047 strb.w r2, [r3, #71] ; 0x47
|
|
|
|
|
|
/* Initialize the TIM state*/
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
8002b92: 687b ldr r3, [r7, #4]
|
|
|
8002b94: 2201 movs r2, #1
|
|
|
8002b96: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
return HAL_OK;
|
|
|
8002b9a: 2300 movs r3, #0
|
|
|
}
|
|
|
8002b9c: 4618 mov r0, r3
|
|
|
8002b9e: 3708 adds r7, #8
|
|
|
8002ba0: 46bd mov sp, r7
|
|
|
8002ba2: bd80 pop {r7, pc}
|
|
|
|
|
|
08002ba4 <HAL_TIM_PWM_MspInit>:
|
|
|
* @brief Initializes the TIM PWM MSP.
|
|
|
* @param htim TIM PWM handle
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
|
{
|
|
|
8002ba4: b480 push {r7}
|
|
|
8002ba6: b083 sub sp, #12
|
|
|
8002ba8: af00 add r7, sp, #0
|
|
|
8002baa: 6078 str r0, [r7, #4]
|
|
|
UNUSED(htim);
|
|
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
|
the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
|
*/
|
|
|
}
|
|
|
8002bac: bf00 nop
|
|
|
8002bae: 370c adds r7, #12
|
|
|
8002bb0: 46bd mov sp, r7
|
|
|
8002bb2: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8002bb6: 4770 bx lr
|
|
|
|
|
|
08002bb8 <HAL_TIM_PWM_ConfigChannel>:
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
|
uint32_t Channel)
|
|
|
{
|
|
|
8002bb8: b580 push {r7, lr}
|
|
|
8002bba: b086 sub sp, #24
|
|
|
8002bbc: af00 add r7, sp, #0
|
|
|
8002bbe: 60f8 str r0, [r7, #12]
|
|
|
8002bc0: 60b9 str r1, [r7, #8]
|
|
|
8002bc2: 607a str r2, [r7, #4]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8002bc4: 2300 movs r3, #0
|
|
|
8002bc6: 75fb strb r3, [r7, #23]
|
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
|
|
/* Process Locked */
|
|
|
__HAL_LOCK(htim);
|
|
|
8002bc8: 68fb ldr r3, [r7, #12]
|
|
|
8002bca: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
8002bce: 2b01 cmp r3, #1
|
|
|
8002bd0: d101 bne.n 8002bd6 <HAL_TIM_PWM_ConfigChannel+0x1e>
|
|
|
8002bd2: 2302 movs r3, #2
|
|
|
8002bd4: e0ff b.n 8002dd6 <HAL_TIM_PWM_ConfigChannel+0x21e>
|
|
|
8002bd6: 68fb ldr r3, [r7, #12]
|
|
|
8002bd8: 2201 movs r2, #1
|
|
|
8002bda: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
switch (Channel)
|
|
|
8002bde: 687b ldr r3, [r7, #4]
|
|
|
8002be0: 2b14 cmp r3, #20
|
|
|
8002be2: f200 80f0 bhi.w 8002dc6 <HAL_TIM_PWM_ConfigChannel+0x20e>
|
|
|
8002be6: a201 add r2, pc, #4 ; (adr r2, 8002bec <HAL_TIM_PWM_ConfigChannel+0x34>)
|
|
|
8002be8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
8002bec: 08002c41 .word 0x08002c41
|
|
|
8002bf0: 08002dc7 .word 0x08002dc7
|
|
|
8002bf4: 08002dc7 .word 0x08002dc7
|
|
|
8002bf8: 08002dc7 .word 0x08002dc7
|
|
|
8002bfc: 08002c81 .word 0x08002c81
|
|
|
8002c00: 08002dc7 .word 0x08002dc7
|
|
|
8002c04: 08002dc7 .word 0x08002dc7
|
|
|
8002c08: 08002dc7 .word 0x08002dc7
|
|
|
8002c0c: 08002cc3 .word 0x08002cc3
|
|
|
8002c10: 08002dc7 .word 0x08002dc7
|
|
|
8002c14: 08002dc7 .word 0x08002dc7
|
|
|
8002c18: 08002dc7 .word 0x08002dc7
|
|
|
8002c1c: 08002d03 .word 0x08002d03
|
|
|
8002c20: 08002dc7 .word 0x08002dc7
|
|
|
8002c24: 08002dc7 .word 0x08002dc7
|
|
|
8002c28: 08002dc7 .word 0x08002dc7
|
|
|
8002c2c: 08002d45 .word 0x08002d45
|
|
|
8002c30: 08002dc7 .word 0x08002dc7
|
|
|
8002c34: 08002dc7 .word 0x08002dc7
|
|
|
8002c38: 08002dc7 .word 0x08002dc7
|
|
|
8002c3c: 08002d85 .word 0x08002d85
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
|
8002c40: 68fb ldr r3, [r7, #12]
|
|
|
8002c42: 681b ldr r3, [r3, #0]
|
|
|
8002c44: 68b9 ldr r1, [r7, #8]
|
|
|
8002c46: 4618 mov r0, r3
|
|
|
8002c48: f000 f9f8 bl 800303c <TIM_OC1_SetConfig>
|
|
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
|
8002c4c: 68fb ldr r3, [r7, #12]
|
|
|
8002c4e: 681b ldr r3, [r3, #0]
|
|
|
8002c50: 699a ldr r2, [r3, #24]
|
|
|
8002c52: 68fb ldr r3, [r7, #12]
|
|
|
8002c54: 681b ldr r3, [r3, #0]
|
|
|
8002c56: f042 0208 orr.w r2, r2, #8
|
|
|
8002c5a: 619a str r2, [r3, #24]
|
|
|
|
|
|
/* Configure the Output Fast mode */
|
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
|
8002c5c: 68fb ldr r3, [r7, #12]
|
|
|
8002c5e: 681b ldr r3, [r3, #0]
|
|
|
8002c60: 699a ldr r2, [r3, #24]
|
|
|
8002c62: 68fb ldr r3, [r7, #12]
|
|
|
8002c64: 681b ldr r3, [r3, #0]
|
|
|
8002c66: f022 0204 bic.w r2, r2, #4
|
|
|
8002c6a: 619a str r2, [r3, #24]
|
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
|
8002c6c: 68fb ldr r3, [r7, #12]
|
|
|
8002c6e: 681b ldr r3, [r3, #0]
|
|
|
8002c70: 6999 ldr r1, [r3, #24]
|
|
|
8002c72: 68bb ldr r3, [r7, #8]
|
|
|
8002c74: 691a ldr r2, [r3, #16]
|
|
|
8002c76: 68fb ldr r3, [r7, #12]
|
|
|
8002c78: 681b ldr r3, [r3, #0]
|
|
|
8002c7a: 430a orrs r2, r1
|
|
|
8002c7c: 619a str r2, [r3, #24]
|
|
|
break;
|
|
|
8002c7e: e0a5 b.n 8002dcc <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
|
8002c80: 68fb ldr r3, [r7, #12]
|
|
|
8002c82: 681b ldr r3, [r3, #0]
|
|
|
8002c84: 68b9 ldr r1, [r7, #8]
|
|
|
8002c86: 4618 mov r0, r3
|
|
|
8002c88: f000 fa54 bl 8003134 <TIM_OC2_SetConfig>
|
|
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
|
8002c8c: 68fb ldr r3, [r7, #12]
|
|
|
8002c8e: 681b ldr r3, [r3, #0]
|
|
|
8002c90: 699a ldr r2, [r3, #24]
|
|
|
8002c92: 68fb ldr r3, [r7, #12]
|
|
|
8002c94: 681b ldr r3, [r3, #0]
|
|
|
8002c96: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
|
8002c9a: 619a str r2, [r3, #24]
|
|
|
|
|
|
/* Configure the Output Fast mode */
|
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
|
8002c9c: 68fb ldr r3, [r7, #12]
|
|
|
8002c9e: 681b ldr r3, [r3, #0]
|
|
|
8002ca0: 699a ldr r2, [r3, #24]
|
|
|
8002ca2: 68fb ldr r3, [r7, #12]
|
|
|
8002ca4: 681b ldr r3, [r3, #0]
|
|
|
8002ca6: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
|
8002caa: 619a str r2, [r3, #24]
|
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
|
8002cac: 68fb ldr r3, [r7, #12]
|
|
|
8002cae: 681b ldr r3, [r3, #0]
|
|
|
8002cb0: 6999 ldr r1, [r3, #24]
|
|
|
8002cb2: 68bb ldr r3, [r7, #8]
|
|
|
8002cb4: 691b ldr r3, [r3, #16]
|
|
|
8002cb6: 021a lsls r2, r3, #8
|
|
|
8002cb8: 68fb ldr r3, [r7, #12]
|
|
|
8002cba: 681b ldr r3, [r3, #0]
|
|
|
8002cbc: 430a orrs r2, r1
|
|
|
8002cbe: 619a str r2, [r3, #24]
|
|
|
break;
|
|
|
8002cc0: e084 b.n 8002dcc <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
|
8002cc2: 68fb ldr r3, [r7, #12]
|
|
|
8002cc4: 681b ldr r3, [r3, #0]
|
|
|
8002cc6: 68b9 ldr r1, [r7, #8]
|
|
|
8002cc8: 4618 mov r0, r3
|
|
|
8002cca: f000 faad bl 8003228 <TIM_OC3_SetConfig>
|
|
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
|
8002cce: 68fb ldr r3, [r7, #12]
|
|
|
8002cd0: 681b ldr r3, [r3, #0]
|
|
|
8002cd2: 69da ldr r2, [r3, #28]
|
|
|
8002cd4: 68fb ldr r3, [r7, #12]
|
|
|
8002cd6: 681b ldr r3, [r3, #0]
|
|
|
8002cd8: f042 0208 orr.w r2, r2, #8
|
|
|
8002cdc: 61da str r2, [r3, #28]
|
|
|
|
|
|
/* Configure the Output Fast mode */
|
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
|
8002cde: 68fb ldr r3, [r7, #12]
|
|
|
8002ce0: 681b ldr r3, [r3, #0]
|
|
|
8002ce2: 69da ldr r2, [r3, #28]
|
|
|
8002ce4: 68fb ldr r3, [r7, #12]
|
|
|
8002ce6: 681b ldr r3, [r3, #0]
|
|
|
8002ce8: f022 0204 bic.w r2, r2, #4
|
|
|
8002cec: 61da str r2, [r3, #28]
|
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
|
8002cee: 68fb ldr r3, [r7, #12]
|
|
|
8002cf0: 681b ldr r3, [r3, #0]
|
|
|
8002cf2: 69d9 ldr r1, [r3, #28]
|
|
|
8002cf4: 68bb ldr r3, [r7, #8]
|
|
|
8002cf6: 691a ldr r2, [r3, #16]
|
|
|
8002cf8: 68fb ldr r3, [r7, #12]
|
|
|
8002cfa: 681b ldr r3, [r3, #0]
|
|
|
8002cfc: 430a orrs r2, r1
|
|
|
8002cfe: 61da str r2, [r3, #28]
|
|
|
break;
|
|
|
8002d00: e064 b.n 8002dcc <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
|
8002d02: 68fb ldr r3, [r7, #12]
|
|
|
8002d04: 681b ldr r3, [r3, #0]
|
|
|
8002d06: 68b9 ldr r1, [r7, #8]
|
|
|
8002d08: 4618 mov r0, r3
|
|
|
8002d0a: f000 fb05 bl 8003318 <TIM_OC4_SetConfig>
|
|
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
|
8002d0e: 68fb ldr r3, [r7, #12]
|
|
|
8002d10: 681b ldr r3, [r3, #0]
|
|
|
8002d12: 69da ldr r2, [r3, #28]
|
|
|
8002d14: 68fb ldr r3, [r7, #12]
|
|
|
8002d16: 681b ldr r3, [r3, #0]
|
|
|
8002d18: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
|
8002d1c: 61da str r2, [r3, #28]
|
|
|
|
|
|
/* Configure the Output Fast mode */
|
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
|
8002d1e: 68fb ldr r3, [r7, #12]
|
|
|
8002d20: 681b ldr r3, [r3, #0]
|
|
|
8002d22: 69da ldr r2, [r3, #28]
|
|
|
8002d24: 68fb ldr r3, [r7, #12]
|
|
|
8002d26: 681b ldr r3, [r3, #0]
|
|
|
8002d28: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
|
8002d2c: 61da str r2, [r3, #28]
|
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
|
8002d2e: 68fb ldr r3, [r7, #12]
|
|
|
8002d30: 681b ldr r3, [r3, #0]
|
|
|
8002d32: 69d9 ldr r1, [r3, #28]
|
|
|
8002d34: 68bb ldr r3, [r7, #8]
|
|
|
8002d36: 691b ldr r3, [r3, #16]
|
|
|
8002d38: 021a lsls r2, r3, #8
|
|
|
8002d3a: 68fb ldr r3, [r7, #12]
|
|
|
8002d3c: 681b ldr r3, [r3, #0]
|
|
|
8002d3e: 430a orrs r2, r1
|
|
|
8002d40: 61da str r2, [r3, #28]
|
|
|
break;
|
|
|
8002d42: e043 b.n 8002dcc <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
|
8002d44: 68fb ldr r3, [r7, #12]
|
|
|
8002d46: 681b ldr r3, [r3, #0]
|
|
|
8002d48: 68b9 ldr r1, [r7, #8]
|
|
|
8002d4a: 4618 mov r0, r3
|
|
|
8002d4c: f000 fb42 bl 80033d4 <TIM_OC5_SetConfig>
|
|
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
|
8002d50: 68fb ldr r3, [r7, #12]
|
|
|
8002d52: 681b ldr r3, [r3, #0]
|
|
|
8002d54: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
|
8002d56: 68fb ldr r3, [r7, #12]
|
|
|
8002d58: 681b ldr r3, [r3, #0]
|
|
|
8002d5a: f042 0208 orr.w r2, r2, #8
|
|
|
8002d5e: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
|
|
/* Configure the Output Fast mode */
|
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
|
8002d60: 68fb ldr r3, [r7, #12]
|
|
|
8002d62: 681b ldr r3, [r3, #0]
|
|
|
8002d64: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
|
8002d66: 68fb ldr r3, [r7, #12]
|
|
|
8002d68: 681b ldr r3, [r3, #0]
|
|
|
8002d6a: f022 0204 bic.w r2, r2, #4
|
|
|
8002d6e: 655a str r2, [r3, #84] ; 0x54
|
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
|
8002d70: 68fb ldr r3, [r7, #12]
|
|
|
8002d72: 681b ldr r3, [r3, #0]
|
|
|
8002d74: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
|
8002d76: 68bb ldr r3, [r7, #8]
|
|
|
8002d78: 691a ldr r2, [r3, #16]
|
|
|
8002d7a: 68fb ldr r3, [r7, #12]
|
|
|
8002d7c: 681b ldr r3, [r3, #0]
|
|
|
8002d7e: 430a orrs r2, r1
|
|
|
8002d80: 655a str r2, [r3, #84] ; 0x54
|
|
|
break;
|
|
|
8002d82: e023 b.n 8002dcc <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
|
8002d84: 68fb ldr r3, [r7, #12]
|
|
|
8002d86: 681b ldr r3, [r3, #0]
|
|
|
8002d88: 68b9 ldr r1, [r7, #8]
|
|
|
8002d8a: 4618 mov r0, r3
|
|
|
8002d8c: f000 fb7a bl 8003484 <TIM_OC6_SetConfig>
|
|
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
|
8002d90: 68fb ldr r3, [r7, #12]
|
|
|
8002d92: 681b ldr r3, [r3, #0]
|
|
|
8002d94: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
|
8002d96: 68fb ldr r3, [r7, #12]
|
|
|
8002d98: 681b ldr r3, [r3, #0]
|
|
|
8002d9a: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
|
8002d9e: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
|
|
/* Configure the Output Fast mode */
|
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
|
8002da0: 68fb ldr r3, [r7, #12]
|
|
|
8002da2: 681b ldr r3, [r3, #0]
|
|
|
8002da4: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
|
8002da6: 68fb ldr r3, [r7, #12]
|
|
|
8002da8: 681b ldr r3, [r3, #0]
|
|
|
8002daa: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
|
8002dae: 655a str r2, [r3, #84] ; 0x54
|
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
|
8002db0: 68fb ldr r3, [r7, #12]
|
|
|
8002db2: 681b ldr r3, [r3, #0]
|
|
|
8002db4: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
|
8002db6: 68bb ldr r3, [r7, #8]
|
|
|
8002db8: 691b ldr r3, [r3, #16]
|
|
|
8002dba: 021a lsls r2, r3, #8
|
|
|
8002dbc: 68fb ldr r3, [r7, #12]
|
|
|
8002dbe: 681b ldr r3, [r3, #0]
|
|
|
8002dc0: 430a orrs r2, r1
|
|
|
8002dc2: 655a str r2, [r3, #84] ; 0x54
|
|
|
break;
|
|
|
8002dc4: e002 b.n 8002dcc <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
|
}
|
|
|
|
|
|
default:
|
|
|
status = HAL_ERROR;
|
|
|
8002dc6: 2301 movs r3, #1
|
|
|
8002dc8: 75fb strb r3, [r7, #23]
|
|
|
break;
|
|
|
8002dca: bf00 nop
|
|
|
}
|
|
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
8002dcc: 68fb ldr r3, [r7, #12]
|
|
|
8002dce: 2200 movs r2, #0
|
|
|
8002dd0: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return status;
|
|
|
8002dd4: 7dfb ldrb r3, [r7, #23]
|
|
|
}
|
|
|
8002dd6: 4618 mov r0, r3
|
|
|
8002dd8: 3718 adds r7, #24
|
|
|
8002dda: 46bd mov sp, r7
|
|
|
8002ddc: bd80 pop {r7, pc}
|
|
|
8002dde: bf00 nop
|
|
|
|
|
|
08002de0 <HAL_TIM_ConfigClockSource>:
|
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
|
* contains the clock source information for the TIM peripheral.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
|
{
|
|
|
8002de0: b580 push {r7, lr}
|
|
|
8002de2: b084 sub sp, #16
|
|
|
8002de4: af00 add r7, sp, #0
|
|
|
8002de6: 6078 str r0, [r7, #4]
|
|
|
8002de8: 6039 str r1, [r7, #0]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8002dea: 2300 movs r3, #0
|
|
|
8002dec: 73fb strb r3, [r7, #15]
|
|
|
uint32_t tmpsmcr;
|
|
|
|
|
|
/* Process Locked */
|
|
|
__HAL_LOCK(htim);
|
|
|
8002dee: 687b ldr r3, [r7, #4]
|
|
|
8002df0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
8002df4: 2b01 cmp r3, #1
|
|
|
8002df6: d101 bne.n 8002dfc <HAL_TIM_ConfigClockSource+0x1c>
|
|
|
8002df8: 2302 movs r3, #2
|
|
|
8002dfa: e0b6 b.n 8002f6a <HAL_TIM_ConfigClockSource+0x18a>
|
|
|
8002dfc: 687b ldr r3, [r7, #4]
|
|
|
8002dfe: 2201 movs r2, #1
|
|
|
8002e00: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8002e04: 687b ldr r3, [r7, #4]
|
|
|
8002e06: 2202 movs r2, #2
|
|
|
8002e08: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
8002e0c: 687b ldr r3, [r7, #4]
|
|
|
8002e0e: 681b ldr r3, [r3, #0]
|
|
|
8002e10: 689b ldr r3, [r3, #8]
|
|
|
8002e12: 60bb str r3, [r7, #8]
|
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
|
8002e14: 68bb ldr r3, [r7, #8]
|
|
|
8002e16: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8002e1a: f023 0377 bic.w r3, r3, #119 ; 0x77
|
|
|
8002e1e: 60bb str r3, [r7, #8]
|
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
8002e20: 68bb ldr r3, [r7, #8]
|
|
|
8002e22: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
|
8002e26: 60bb str r3, [r7, #8]
|
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
8002e28: 687b ldr r3, [r7, #4]
|
|
|
8002e2a: 681b ldr r3, [r3, #0]
|
|
|
8002e2c: 68ba ldr r2, [r7, #8]
|
|
|
8002e2e: 609a str r2, [r3, #8]
|
|
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
|
8002e30: 683b ldr r3, [r7, #0]
|
|
|
8002e32: 681b ldr r3, [r3, #0]
|
|
|
8002e34: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
|
8002e38: d03e beq.n 8002eb8 <HAL_TIM_ConfigClockSource+0xd8>
|
|
|
8002e3a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
|
8002e3e: f200 8087 bhi.w 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e42: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8002e46: f000 8086 beq.w 8002f56 <HAL_TIM_ConfigClockSource+0x176>
|
|
|
8002e4a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8002e4e: d87f bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e50: 2b70 cmp r3, #112 ; 0x70
|
|
|
8002e52: d01a beq.n 8002e8a <HAL_TIM_ConfigClockSource+0xaa>
|
|
|
8002e54: 2b70 cmp r3, #112 ; 0x70
|
|
|
8002e56: d87b bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e58: 2b60 cmp r3, #96 ; 0x60
|
|
|
8002e5a: d050 beq.n 8002efe <HAL_TIM_ConfigClockSource+0x11e>
|
|
|
8002e5c: 2b60 cmp r3, #96 ; 0x60
|
|
|
8002e5e: d877 bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e60: 2b50 cmp r3, #80 ; 0x50
|
|
|
8002e62: d03c beq.n 8002ede <HAL_TIM_ConfigClockSource+0xfe>
|
|
|
8002e64: 2b50 cmp r3, #80 ; 0x50
|
|
|
8002e66: d873 bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e68: 2b40 cmp r3, #64 ; 0x40
|
|
|
8002e6a: d058 beq.n 8002f1e <HAL_TIM_ConfigClockSource+0x13e>
|
|
|
8002e6c: 2b40 cmp r3, #64 ; 0x40
|
|
|
8002e6e: d86f bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e70: 2b30 cmp r3, #48 ; 0x30
|
|
|
8002e72: d064 beq.n 8002f3e <HAL_TIM_ConfigClockSource+0x15e>
|
|
|
8002e74: 2b30 cmp r3, #48 ; 0x30
|
|
|
8002e76: d86b bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e78: 2b20 cmp r3, #32
|
|
|
8002e7a: d060 beq.n 8002f3e <HAL_TIM_ConfigClockSource+0x15e>
|
|
|
8002e7c: 2b20 cmp r3, #32
|
|
|
8002e7e: d867 bhi.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
8002e80: 2b00 cmp r3, #0
|
|
|
8002e82: d05c beq.n 8002f3e <HAL_TIM_ConfigClockSource+0x15e>
|
|
|
8002e84: 2b10 cmp r3, #16
|
|
|
8002e86: d05a beq.n 8002f3e <HAL_TIM_ConfigClockSource+0x15e>
|
|
|
8002e88: e062 b.n 8002f50 <HAL_TIM_ConfigClockSource+0x170>
|
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
|
|
/* Configure the ETR Clock source */
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
|
8002e8a: 687b ldr r3, [r7, #4]
|
|
|
8002e8c: 6818 ldr r0, [r3, #0]
|
|
|
sClockSourceConfig->ClockPrescaler,
|
|
|
8002e8e: 683b ldr r3, [r7, #0]
|
|
|
8002e90: 6899 ldr r1, [r3, #8]
|
|
|
sClockSourceConfig->ClockPolarity,
|
|
|
8002e92: 683b ldr r3, [r7, #0]
|
|
|
8002e94: 685a ldr r2, [r3, #4]
|
|
|
sClockSourceConfig->ClockFilter);
|
|
|
8002e96: 683b ldr r3, [r7, #0]
|
|
|
8002e98: 68db ldr r3, [r3, #12]
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
|
8002e9a: f000 fbc7 bl 800362c <TIM_ETR_SetConfig>
|
|
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
8002e9e: 687b ldr r3, [r7, #4]
|
|
|
8002ea0: 681b ldr r3, [r3, #0]
|
|
|
8002ea2: 689b ldr r3, [r3, #8]
|
|
|
8002ea4: 60bb str r3, [r7, #8]
|
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
|
8002ea6: 68bb ldr r3, [r7, #8]
|
|
|
8002ea8: f043 0377 orr.w r3, r3, #119 ; 0x77
|
|
|
8002eac: 60bb str r3, [r7, #8]
|
|
|
/* Write to TIMx SMCR */
|
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
8002eae: 687b ldr r3, [r7, #4]
|
|
|
8002eb0: 681b ldr r3, [r3, #0]
|
|
|
8002eb2: 68ba ldr r2, [r7, #8]
|
|
|
8002eb4: 609a str r2, [r3, #8]
|
|
|
break;
|
|
|
8002eb6: e04f b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
|
|
/* Configure the ETR Clock source */
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
|
8002eb8: 687b ldr r3, [r7, #4]
|
|
|
8002eba: 6818 ldr r0, [r3, #0]
|
|
|
sClockSourceConfig->ClockPrescaler,
|
|
|
8002ebc: 683b ldr r3, [r7, #0]
|
|
|
8002ebe: 6899 ldr r1, [r3, #8]
|
|
|
sClockSourceConfig->ClockPolarity,
|
|
|
8002ec0: 683b ldr r3, [r7, #0]
|
|
|
8002ec2: 685a ldr r2, [r3, #4]
|
|
|
sClockSourceConfig->ClockFilter);
|
|
|
8002ec4: 683b ldr r3, [r7, #0]
|
|
|
8002ec6: 68db ldr r3, [r3, #12]
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
|
8002ec8: f000 fbb0 bl 800362c <TIM_ETR_SetConfig>
|
|
|
/* Enable the External clock mode2 */
|
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
|
8002ecc: 687b ldr r3, [r7, #4]
|
|
|
8002ece: 681b ldr r3, [r3, #0]
|
|
|
8002ed0: 689a ldr r2, [r3, #8]
|
|
|
8002ed2: 687b ldr r3, [r7, #4]
|
|
|
8002ed4: 681b ldr r3, [r3, #0]
|
|
|
8002ed6: f442 4280 orr.w r2, r2, #16384 ; 0x4000
|
|
|
8002eda: 609a str r2, [r3, #8]
|
|
|
break;
|
|
|
8002edc: e03c b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
8002ede: 687b ldr r3, [r7, #4]
|
|
|
8002ee0: 6818 ldr r0, [r3, #0]
|
|
|
sClockSourceConfig->ClockPolarity,
|
|
|
8002ee2: 683b ldr r3, [r7, #0]
|
|
|
8002ee4: 6859 ldr r1, [r3, #4]
|
|
|
sClockSourceConfig->ClockFilter);
|
|
|
8002ee6: 683b ldr r3, [r7, #0]
|
|
|
8002ee8: 68db ldr r3, [r3, #12]
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
8002eea: 461a mov r2, r3
|
|
|
8002eec: f000 fb24 bl 8003538 <TIM_TI1_ConfigInputStage>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
|
8002ef0: 687b ldr r3, [r7, #4]
|
|
|
8002ef2: 681b ldr r3, [r3, #0]
|
|
|
8002ef4: 2150 movs r1, #80 ; 0x50
|
|
|
8002ef6: 4618 mov r0, r3
|
|
|
8002ef8: f000 fb7d bl 80035f6 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002efc: e02c b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
|
8002efe: 687b ldr r3, [r7, #4]
|
|
|
8002f00: 6818 ldr r0, [r3, #0]
|
|
|
sClockSourceConfig->ClockPolarity,
|
|
|
8002f02: 683b ldr r3, [r7, #0]
|
|
|
8002f04: 6859 ldr r1, [r3, #4]
|
|
|
sClockSourceConfig->ClockFilter);
|
|
|
8002f06: 683b ldr r3, [r7, #0]
|
|
|
8002f08: 68db ldr r3, [r3, #12]
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
|
8002f0a: 461a mov r2, r3
|
|
|
8002f0c: f000 fb43 bl 8003596 <TIM_TI2_ConfigInputStage>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
|
8002f10: 687b ldr r3, [r7, #4]
|
|
|
8002f12: 681b ldr r3, [r3, #0]
|
|
|
8002f14: 2160 movs r1, #96 ; 0x60
|
|
|
8002f16: 4618 mov r0, r3
|
|
|
8002f18: f000 fb6d bl 80035f6 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002f1c: e01c b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
8002f1e: 687b ldr r3, [r7, #4]
|
|
|
8002f20: 6818 ldr r0, [r3, #0]
|
|
|
sClockSourceConfig->ClockPolarity,
|
|
|
8002f22: 683b ldr r3, [r7, #0]
|
|
|
8002f24: 6859 ldr r1, [r3, #4]
|
|
|
sClockSourceConfig->ClockFilter);
|
|
|
8002f26: 683b ldr r3, [r7, #0]
|
|
|
8002f28: 68db ldr r3, [r3, #12]
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
8002f2a: 461a mov r2, r3
|
|
|
8002f2c: f000 fb04 bl 8003538 <TIM_TI1_ConfigInputStage>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
|
8002f30: 687b ldr r3, [r7, #4]
|
|
|
8002f32: 681b ldr r3, [r3, #0]
|
|
|
8002f34: 2140 movs r1, #64 ; 0x40
|
|
|
8002f36: 4618 mov r0, r3
|
|
|
8002f38: f000 fb5d bl 80035f6 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002f3c: e00c b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
case TIM_CLOCKSOURCE_ITR3:
|
|
|
{
|
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
|
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
|
8002f3e: 687b ldr r3, [r7, #4]
|
|
|
8002f40: 681a ldr r2, [r3, #0]
|
|
|
8002f42: 683b ldr r3, [r7, #0]
|
|
|
8002f44: 681b ldr r3, [r3, #0]
|
|
|
8002f46: 4619 mov r1, r3
|
|
|
8002f48: 4610 mov r0, r2
|
|
|
8002f4a: f000 fb54 bl 80035f6 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002f4e: e003 b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
}
|
|
|
|
|
|
default:
|
|
|
status = HAL_ERROR;
|
|
|
8002f50: 2301 movs r3, #1
|
|
|
8002f52: 73fb strb r3, [r7, #15]
|
|
|
break;
|
|
|
8002f54: e000 b.n 8002f58 <HAL_TIM_ConfigClockSource+0x178>
|
|
|
break;
|
|
|
8002f56: bf00 nop
|
|
|
}
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
8002f58: 687b ldr r3, [r7, #4]
|
|
|
8002f5a: 2201 movs r2, #1
|
|
|
8002f5c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
8002f60: 687b ldr r3, [r7, #4]
|
|
|
8002f62: 2200 movs r2, #0
|
|
|
8002f64: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return status;
|
|
|
8002f68: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
8002f6a: 4618 mov r0, r3
|
|
|
8002f6c: 3710 adds r7, #16
|
|
|
8002f6e: 46bd mov sp, r7
|
|
|
8002f70: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08002f74 <TIM_Base_SetConfig>:
|
|
|
* @param TIMx TIM peripheral
|
|
|
* @param Structure TIM Base configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
|
{
|
|
|
8002f74: b480 push {r7}
|
|
|
8002f76: b085 sub sp, #20
|
|
|
8002f78: af00 add r7, sp, #0
|
|
|
8002f7a: 6078 str r0, [r7, #4]
|
|
|
8002f7c: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpcr1;
|
|
|
tmpcr1 = TIMx->CR1;
|
|
|
8002f7e: 687b ldr r3, [r7, #4]
|
|
|
8002f80: 681b ldr r3, [r3, #0]
|
|
|
8002f82: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
|
8002f84: 687b ldr r3, [r7, #4]
|
|
|
8002f86: 4a2a ldr r2, [pc, #168] ; (8003030 <TIM_Base_SetConfig+0xbc>)
|
|
|
8002f88: 4293 cmp r3, r2
|
|
|
8002f8a: d003 beq.n 8002f94 <TIM_Base_SetConfig+0x20>
|
|
|
8002f8c: 687b ldr r3, [r7, #4]
|
|
|
8002f8e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
8002f92: d108 bne.n 8002fa6 <TIM_Base_SetConfig+0x32>
|
|
|
{
|
|
|
/* Select the Counter Mode */
|
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
|
8002f94: 68fb ldr r3, [r7, #12]
|
|
|
8002f96: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
8002f9a: 60fb str r3, [r7, #12]
|
|
|
tmpcr1 |= Structure->CounterMode;
|
|
|
8002f9c: 683b ldr r3, [r7, #0]
|
|
|
8002f9e: 685b ldr r3, [r3, #4]
|
|
|
8002fa0: 68fa ldr r2, [r7, #12]
|
|
|
8002fa2: 4313 orrs r3, r2
|
|
|
8002fa4: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
|
8002fa6: 687b ldr r3, [r7, #4]
|
|
|
8002fa8: 4a21 ldr r2, [pc, #132] ; (8003030 <TIM_Base_SetConfig+0xbc>)
|
|
|
8002faa: 4293 cmp r3, r2
|
|
|
8002fac: d00b beq.n 8002fc6 <TIM_Base_SetConfig+0x52>
|
|
|
8002fae: 687b ldr r3, [r7, #4]
|
|
|
8002fb0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
8002fb4: d007 beq.n 8002fc6 <TIM_Base_SetConfig+0x52>
|
|
|
8002fb6: 687b ldr r3, [r7, #4]
|
|
|
8002fb8: 4a1e ldr r2, [pc, #120] ; (8003034 <TIM_Base_SetConfig+0xc0>)
|
|
|
8002fba: 4293 cmp r3, r2
|
|
|
8002fbc: d003 beq.n 8002fc6 <TIM_Base_SetConfig+0x52>
|
|
|
8002fbe: 687b ldr r3, [r7, #4]
|
|
|
8002fc0: 4a1d ldr r2, [pc, #116] ; (8003038 <TIM_Base_SetConfig+0xc4>)
|
|
|
8002fc2: 4293 cmp r3, r2
|
|
|
8002fc4: d108 bne.n 8002fd8 <TIM_Base_SetConfig+0x64>
|
|
|
{
|
|
|
/* Set the clock division */
|
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
|
8002fc6: 68fb ldr r3, [r7, #12]
|
|
|
8002fc8: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
|
8002fcc: 60fb str r3, [r7, #12]
|
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
|
8002fce: 683b ldr r3, [r7, #0]
|
|
|
8002fd0: 68db ldr r3, [r3, #12]
|
|
|
8002fd2: 68fa ldr r2, [r7, #12]
|
|
|
8002fd4: 4313 orrs r3, r2
|
|
|
8002fd6: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
/* Set the auto-reload preload */
|
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
|
8002fd8: 68fb ldr r3, [r7, #12]
|
|
|
8002fda: f023 0280 bic.w r2, r3, #128 ; 0x80
|
|
|
8002fde: 683b ldr r3, [r7, #0]
|
|
|
8002fe0: 695b ldr r3, [r3, #20]
|
|
|
8002fe2: 4313 orrs r3, r2
|
|
|
8002fe4: 60fb str r3, [r7, #12]
|
|
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
|
8002fe6: 687b ldr r3, [r7, #4]
|
|
|
8002fe8: 68fa ldr r2, [r7, #12]
|
|
|
8002fea: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Set the Autoreload value */
|
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
|
8002fec: 683b ldr r3, [r7, #0]
|
|
|
8002fee: 689a ldr r2, [r3, #8]
|
|
|
8002ff0: 687b ldr r3, [r7, #4]
|
|
|
8002ff2: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
|
|
/* Set the Prescaler value */
|
|
|
TIMx->PSC = Structure->Prescaler;
|
|
|
8002ff4: 683b ldr r3, [r7, #0]
|
|
|
8002ff6: 681a ldr r2, [r3, #0]
|
|
|
8002ff8: 687b ldr r3, [r7, #4]
|
|
|
8002ffa: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
|
8002ffc: 687b ldr r3, [r7, #4]
|
|
|
8002ffe: 4a0c ldr r2, [pc, #48] ; (8003030 <TIM_Base_SetConfig+0xbc>)
|
|
|
8003000: 4293 cmp r3, r2
|
|
|
8003002: d007 beq.n 8003014 <TIM_Base_SetConfig+0xa0>
|
|
|
8003004: 687b ldr r3, [r7, #4]
|
|
|
8003006: 4a0b ldr r2, [pc, #44] ; (8003034 <TIM_Base_SetConfig+0xc0>)
|
|
|
8003008: 4293 cmp r3, r2
|
|
|
800300a: d003 beq.n 8003014 <TIM_Base_SetConfig+0xa0>
|
|
|
800300c: 687b ldr r3, [r7, #4]
|
|
|
800300e: 4a0a ldr r2, [pc, #40] ; (8003038 <TIM_Base_SetConfig+0xc4>)
|
|
|
8003010: 4293 cmp r3, r2
|
|
|
8003012: d103 bne.n 800301c <TIM_Base_SetConfig+0xa8>
|
|
|
{
|
|
|
/* Set the Repetition Counter value */
|
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
|
8003014: 683b ldr r3, [r7, #0]
|
|
|
8003016: 691a ldr r2, [r3, #16]
|
|
|
8003018: 687b ldr r3, [r7, #4]
|
|
|
800301a: 631a str r2, [r3, #48] ; 0x30
|
|
|
}
|
|
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
|
800301c: 687b ldr r3, [r7, #4]
|
|
|
800301e: 2201 movs r2, #1
|
|
|
8003020: 615a str r2, [r3, #20]
|
|
|
}
|
|
|
8003022: bf00 nop
|
|
|
8003024: 3714 adds r7, #20
|
|
|
8003026: 46bd mov sp, r7
|
|
|
8003028: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800302c: 4770 bx lr
|
|
|
800302e: bf00 nop
|
|
|
8003030: 40012c00 .word 0x40012c00
|
|
|
8003034: 40014000 .word 0x40014000
|
|
|
8003038: 40014400 .word 0x40014400
|
|
|
|
|
|
0800303c <TIM_OC1_SetConfig>:
|
|
|
* @param TIMx to select the TIM peripheral
|
|
|
* @param OC_Config The output configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
|
{
|
|
|
800303c: b480 push {r7}
|
|
|
800303e: b087 sub sp, #28
|
|
|
8003040: af00 add r7, sp, #0
|
|
|
8003042: 6078 str r0, [r7, #4]
|
|
|
8003044: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpccmrx;
|
|
|
uint32_t tmpccer;
|
|
|
uint32_t tmpcr2;
|
|
|
|
|
|
/* Get the TIMx CCER register value */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
8003046: 687b ldr r3, [r7, #4]
|
|
|
8003048: 6a1b ldr r3, [r3, #32]
|
|
|
800304a: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
|
800304c: 687b ldr r3, [r7, #4]
|
|
|
800304e: 6a1b ldr r3, [r3, #32]
|
|
|
8003050: f023 0201 bic.w r2, r3, #1
|
|
|
8003054: 687b ldr r3, [r7, #4]
|
|
|
8003056: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = TIMx->CR2;
|
|
|
8003058: 687b ldr r3, [r7, #4]
|
|
|
800305a: 685b ldr r3, [r3, #4]
|
|
|
800305c: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
|
tmpccmrx = TIMx->CCMR1;
|
|
|
800305e: 687b ldr r3, [r7, #4]
|
|
|
8003060: 699b ldr r3, [r3, #24]
|
|
|
8003062: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
|
8003064: 68fb ldr r3, [r7, #12]
|
|
|
8003066: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
800306a: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
800306e: 60fb str r3, [r7, #12]
|
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
|
8003070: 68fb ldr r3, [r7, #12]
|
|
|
8003072: f023 0303 bic.w r3, r3, #3
|
|
|
8003076: 60fb str r3, [r7, #12]
|
|
|
/* Select the Output Compare Mode */
|
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
|
8003078: 683b ldr r3, [r7, #0]
|
|
|
800307a: 681b ldr r3, [r3, #0]
|
|
|
800307c: 68fa ldr r2, [r7, #12]
|
|
|
800307e: 4313 orrs r3, r2
|
|
|
8003080: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
|
8003082: 697b ldr r3, [r7, #20]
|
|
|
8003084: f023 0302 bic.w r3, r3, #2
|
|
|
8003088: 617b str r3, [r7, #20]
|
|
|
/* Set the Output Compare Polarity */
|
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
|
800308a: 683b ldr r3, [r7, #0]
|
|
|
800308c: 689b ldr r3, [r3, #8]
|
|
|
800308e: 697a ldr r2, [r7, #20]
|
|
|
8003090: 4313 orrs r3, r2
|
|
|
8003092: 617b str r3, [r7, #20]
|
|
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
|
8003094: 687b ldr r3, [r7, #4]
|
|
|
8003096: 4a24 ldr r2, [pc, #144] ; (8003128 <TIM_OC1_SetConfig+0xec>)
|
|
|
8003098: 4293 cmp r3, r2
|
|
|
800309a: d007 beq.n 80030ac <TIM_OC1_SetConfig+0x70>
|
|
|
800309c: 687b ldr r3, [r7, #4]
|
|
|
800309e: 4a23 ldr r2, [pc, #140] ; (800312c <TIM_OC1_SetConfig+0xf0>)
|
|
|
80030a0: 4293 cmp r3, r2
|
|
|
80030a2: d003 beq.n 80030ac <TIM_OC1_SetConfig+0x70>
|
|
|
80030a4: 687b ldr r3, [r7, #4]
|
|
|
80030a6: 4a22 ldr r2, [pc, #136] ; (8003130 <TIM_OC1_SetConfig+0xf4>)
|
|
|
80030a8: 4293 cmp r3, r2
|
|
|
80030aa: d10c bne.n 80030c6 <TIM_OC1_SetConfig+0x8a>
|
|
|
{
|
|
|
/* Check parameters */
|
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
|
|
/* Reset the Output N Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
|
80030ac: 697b ldr r3, [r7, #20]
|
|
|
80030ae: f023 0308 bic.w r3, r3, #8
|
|
|
80030b2: 617b str r3, [r7, #20]
|
|
|
/* Set the Output N Polarity */
|
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
|
80030b4: 683b ldr r3, [r7, #0]
|
|
|
80030b6: 68db ldr r3, [r3, #12]
|
|
|
80030b8: 697a ldr r2, [r7, #20]
|
|
|
80030ba: 4313 orrs r3, r2
|
|
|
80030bc: 617b str r3, [r7, #20]
|
|
|
/* Reset the Output N State */
|
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
|
80030be: 697b ldr r3, [r7, #20]
|
|
|
80030c0: f023 0304 bic.w r3, r3, #4
|
|
|
80030c4: 617b str r3, [r7, #20]
|
|
|
}
|
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
80030c6: 687b ldr r3, [r7, #4]
|
|
|
80030c8: 4a17 ldr r2, [pc, #92] ; (8003128 <TIM_OC1_SetConfig+0xec>)
|
|
|
80030ca: 4293 cmp r3, r2
|
|
|
80030cc: d007 beq.n 80030de <TIM_OC1_SetConfig+0xa2>
|
|
|
80030ce: 687b ldr r3, [r7, #4]
|
|
|
80030d0: 4a16 ldr r2, [pc, #88] ; (800312c <TIM_OC1_SetConfig+0xf0>)
|
|
|
80030d2: 4293 cmp r3, r2
|
|
|
80030d4: d003 beq.n 80030de <TIM_OC1_SetConfig+0xa2>
|
|
|
80030d6: 687b ldr r3, [r7, #4]
|
|
|
80030d8: 4a15 ldr r2, [pc, #84] ; (8003130 <TIM_OC1_SetConfig+0xf4>)
|
|
|
80030da: 4293 cmp r3, r2
|
|
|
80030dc: d111 bne.n 8003102 <TIM_OC1_SetConfig+0xc6>
|
|
|
/* Check parameters */
|
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
|
80030de: 693b ldr r3, [r7, #16]
|
|
|
80030e0: f423 7380 bic.w r3, r3, #256 ; 0x100
|
|
|
80030e4: 613b str r3, [r7, #16]
|
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
|
80030e6: 693b ldr r3, [r7, #16]
|
|
|
80030e8: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
|
80030ec: 613b str r3, [r7, #16]
|
|
|
/* Set the Output Idle state */
|
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
|
80030ee: 683b ldr r3, [r7, #0]
|
|
|
80030f0: 695b ldr r3, [r3, #20]
|
|
|
80030f2: 693a ldr r2, [r7, #16]
|
|
|
80030f4: 4313 orrs r3, r2
|
|
|
80030f6: 613b str r3, [r7, #16]
|
|
|
/* Set the Output N Idle state */
|
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
|
80030f8: 683b ldr r3, [r7, #0]
|
|
|
80030fa: 699b ldr r3, [r3, #24]
|
|
|
80030fc: 693a ldr r2, [r7, #16]
|
|
|
80030fe: 4313 orrs r3, r2
|
|
|
8003100: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
|
|
|
/* Write to TIMx CR2 */
|
|
|
TIMx->CR2 = tmpcr2;
|
|
|
8003102: 687b ldr r3, [r7, #4]
|
|
|
8003104: 693a ldr r2, [r7, #16]
|
|
|
8003106: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
|
8003108: 687b ldr r3, [r7, #4]
|
|
|
800310a: 68fa ldr r2, [r7, #12]
|
|
|
800310c: 619a str r2, [r3, #24]
|
|
|
|
|
|
/* Set the Capture Compare Register value */
|
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
|
800310e: 683b ldr r3, [r7, #0]
|
|
|
8003110: 685a ldr r2, [r3, #4]
|
|
|
8003112: 687b ldr r3, [r7, #4]
|
|
|
8003114: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
|
|
/* Write to TIMx CCER */
|
|
|
TIMx->CCER = tmpccer;
|
|
|
8003116: 687b ldr r3, [r7, #4]
|
|
|
8003118: 697a ldr r2, [r7, #20]
|
|
|
800311a: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
800311c: bf00 nop
|
|
|
800311e: 371c adds r7, #28
|
|
|
8003120: 46bd mov sp, r7
|
|
|
8003122: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003126: 4770 bx lr
|
|
|
8003128: 40012c00 .word 0x40012c00
|
|
|
800312c: 40014000 .word 0x40014000
|
|
|
8003130: 40014400 .word 0x40014400
|
|
|
|
|
|
08003134 <TIM_OC2_SetConfig>:
|
|
|
* @param TIMx to select the TIM peripheral
|
|
|
* @param OC_Config The output configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
|
{
|
|
|
8003134: b480 push {r7}
|
|
|
8003136: b087 sub sp, #28
|
|
|
8003138: af00 add r7, sp, #0
|
|
|
800313a: 6078 str r0, [r7, #4]
|
|
|
800313c: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpccmrx;
|
|
|
uint32_t tmpccer;
|
|
|
uint32_t tmpcr2;
|
|
|
|
|
|
/* Get the TIMx CCER register value */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
800313e: 687b ldr r3, [r7, #4]
|
|
|
8003140: 6a1b ldr r3, [r3, #32]
|
|
|
8003142: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
|
8003144: 687b ldr r3, [r7, #4]
|
|
|
8003146: 6a1b ldr r3, [r3, #32]
|
|
|
8003148: f023 0210 bic.w r2, r3, #16
|
|
|
800314c: 687b ldr r3, [r7, #4]
|
|
|
800314e: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = TIMx->CR2;
|
|
|
8003150: 687b ldr r3, [r7, #4]
|
|
|
8003152: 685b ldr r3, [r3, #4]
|
|
|
8003154: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
|
tmpccmrx = TIMx->CCMR1;
|
|
|
8003156: 687b ldr r3, [r7, #4]
|
|
|
8003158: 699b ldr r3, [r3, #24]
|
|
|
800315a: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
|
800315c: 68fb ldr r3, [r7, #12]
|
|
|
800315e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
|
8003162: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
|
8003166: 60fb str r3, [r7, #12]
|
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
|
8003168: 68fb ldr r3, [r7, #12]
|
|
|
800316a: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
|
800316e: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Select the Output Compare Mode */
|
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
|
8003170: 683b ldr r3, [r7, #0]
|
|
|
8003172: 681b ldr r3, [r3, #0]
|
|
|
8003174: 021b lsls r3, r3, #8
|
|
|
8003176: 68fa ldr r2, [r7, #12]
|
|
|
8003178: 4313 orrs r3, r2
|
|
|
800317a: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
|
800317c: 697b ldr r3, [r7, #20]
|
|
|
800317e: f023 0320 bic.w r3, r3, #32
|
|
|
8003182: 617b str r3, [r7, #20]
|
|
|
/* Set the Output Compare Polarity */
|
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
|
8003184: 683b ldr r3, [r7, #0]
|
|
|
8003186: 689b ldr r3, [r3, #8]
|
|
|
8003188: 011b lsls r3, r3, #4
|
|
|
800318a: 697a ldr r2, [r7, #20]
|
|
|
800318c: 4313 orrs r3, r2
|
|
|
800318e: 617b str r3, [r7, #20]
|
|
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
|
8003190: 687b ldr r3, [r7, #4]
|
|
|
8003192: 4a22 ldr r2, [pc, #136] ; (800321c <TIM_OC2_SetConfig+0xe8>)
|
|
|
8003194: 4293 cmp r3, r2
|
|
|
8003196: d10d bne.n 80031b4 <TIM_OC2_SetConfig+0x80>
|
|
|
{
|
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
|
|
/* Reset the Output N Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
|
8003198: 697b ldr r3, [r7, #20]
|
|
|
800319a: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
|
800319e: 617b str r3, [r7, #20]
|
|
|
/* Set the Output N Polarity */
|
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
|
80031a0: 683b ldr r3, [r7, #0]
|
|
|
80031a2: 68db ldr r3, [r3, #12]
|
|
|
80031a4: 011b lsls r3, r3, #4
|
|
|
80031a6: 697a ldr r2, [r7, #20]
|
|
|
80031a8: 4313 orrs r3, r2
|
|
|
80031aa: 617b str r3, [r7, #20]
|
|
|
/* Reset the Output N State */
|
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
|
80031ac: 697b ldr r3, [r7, #20]
|
|
|
80031ae: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
|
80031b2: 617b str r3, [r7, #20]
|
|
|
|
|
|
}
|
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
80031b4: 687b ldr r3, [r7, #4]
|
|
|
80031b6: 4a19 ldr r2, [pc, #100] ; (800321c <TIM_OC2_SetConfig+0xe8>)
|
|
|
80031b8: 4293 cmp r3, r2
|
|
|
80031ba: d007 beq.n 80031cc <TIM_OC2_SetConfig+0x98>
|
|
|
80031bc: 687b ldr r3, [r7, #4]
|
|
|
80031be: 4a18 ldr r2, [pc, #96] ; (8003220 <TIM_OC2_SetConfig+0xec>)
|
|
|
80031c0: 4293 cmp r3, r2
|
|
|
80031c2: d003 beq.n 80031cc <TIM_OC2_SetConfig+0x98>
|
|
|
80031c4: 687b ldr r3, [r7, #4]
|
|
|
80031c6: 4a17 ldr r2, [pc, #92] ; (8003224 <TIM_OC2_SetConfig+0xf0>)
|
|
|
80031c8: 4293 cmp r3, r2
|
|
|
80031ca: d113 bne.n 80031f4 <TIM_OC2_SetConfig+0xc0>
|
|
|
/* Check parameters */
|
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
|
80031cc: 693b ldr r3, [r7, #16]
|
|
|
80031ce: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
|
80031d2: 613b str r3, [r7, #16]
|
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
|
80031d4: 693b ldr r3, [r7, #16]
|
|
|
80031d6: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
|
80031da: 613b str r3, [r7, #16]
|
|
|
/* Set the Output Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
|
80031dc: 683b ldr r3, [r7, #0]
|
|
|
80031de: 695b ldr r3, [r3, #20]
|
|
|
80031e0: 009b lsls r3, r3, #2
|
|
|
80031e2: 693a ldr r2, [r7, #16]
|
|
|
80031e4: 4313 orrs r3, r2
|
|
|
80031e6: 613b str r3, [r7, #16]
|
|
|
/* Set the Output N Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
|
80031e8: 683b ldr r3, [r7, #0]
|
|
|
80031ea: 699b ldr r3, [r3, #24]
|
|
|
80031ec: 009b lsls r3, r3, #2
|
|
|
80031ee: 693a ldr r2, [r7, #16]
|
|
|
80031f0: 4313 orrs r3, r2
|
|
|
80031f2: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
|
|
|
/* Write to TIMx CR2 */
|
|
|
TIMx->CR2 = tmpcr2;
|
|
|
80031f4: 687b ldr r3, [r7, #4]
|
|
|
80031f6: 693a ldr r2, [r7, #16]
|
|
|
80031f8: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
|
80031fa: 687b ldr r3, [r7, #4]
|
|
|
80031fc: 68fa ldr r2, [r7, #12]
|
|
|
80031fe: 619a str r2, [r3, #24]
|
|
|
|
|
|
/* Set the Capture Compare Register value */
|
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
|
8003200: 683b ldr r3, [r7, #0]
|
|
|
8003202: 685a ldr r2, [r3, #4]
|
|
|
8003204: 687b ldr r3, [r7, #4]
|
|
|
8003206: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
|
|
/* Write to TIMx CCER */
|
|
|
TIMx->CCER = tmpccer;
|
|
|
8003208: 687b ldr r3, [r7, #4]
|
|
|
800320a: 697a ldr r2, [r7, #20]
|
|
|
800320c: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
800320e: bf00 nop
|
|
|
8003210: 371c adds r7, #28
|
|
|
8003212: 46bd mov sp, r7
|
|
|
8003214: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003218: 4770 bx lr
|
|
|
800321a: bf00 nop
|
|
|
800321c: 40012c00 .word 0x40012c00
|
|
|
8003220: 40014000 .word 0x40014000
|
|
|
8003224: 40014400 .word 0x40014400
|
|
|
|
|
|
08003228 <TIM_OC3_SetConfig>:
|
|
|
* @param TIMx to select the TIM peripheral
|
|
|
* @param OC_Config The output configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
|
{
|
|
|
8003228: b480 push {r7}
|
|
|
800322a: b087 sub sp, #28
|
|
|
800322c: af00 add r7, sp, #0
|
|
|
800322e: 6078 str r0, [r7, #4]
|
|
|
8003230: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpccmrx;
|
|
|
uint32_t tmpccer;
|
|
|
uint32_t tmpcr2;
|
|
|
|
|
|
/* Get the TIMx CCER register value */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
8003232: 687b ldr r3, [r7, #4]
|
|
|
8003234: 6a1b ldr r3, [r3, #32]
|
|
|
8003236: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
|
8003238: 687b ldr r3, [r7, #4]
|
|
|
800323a: 6a1b ldr r3, [r3, #32]
|
|
|
800323c: f423 7280 bic.w r2, r3, #256 ; 0x100
|
|
|
8003240: 687b ldr r3, [r7, #4]
|
|
|
8003242: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = TIMx->CR2;
|
|
|
8003244: 687b ldr r3, [r7, #4]
|
|
|
8003246: 685b ldr r3, [r3, #4]
|
|
|
8003248: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
|
tmpccmrx = TIMx->CCMR2;
|
|
|
800324a: 687b ldr r3, [r7, #4]
|
|
|
800324c: 69db ldr r3, [r3, #28]
|
|
|
800324e: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
|
8003250: 68fb ldr r3, [r7, #12]
|
|
|
8003252: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8003256: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
800325a: 60fb str r3, [r7, #12]
|
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
|
800325c: 68fb ldr r3, [r7, #12]
|
|
|
800325e: f023 0303 bic.w r3, r3, #3
|
|
|
8003262: 60fb str r3, [r7, #12]
|
|
|
/* Select the Output Compare Mode */
|
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
|
8003264: 683b ldr r3, [r7, #0]
|
|
|
8003266: 681b ldr r3, [r3, #0]
|
|
|
8003268: 68fa ldr r2, [r7, #12]
|
|
|
800326a: 4313 orrs r3, r2
|
|
|
800326c: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
|
800326e: 697b ldr r3, [r7, #20]
|
|
|
8003270: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
|
8003274: 617b str r3, [r7, #20]
|
|
|
/* Set the Output Compare Polarity */
|
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
|
8003276: 683b ldr r3, [r7, #0]
|
|
|
8003278: 689b ldr r3, [r3, #8]
|
|
|
800327a: 021b lsls r3, r3, #8
|
|
|
800327c: 697a ldr r2, [r7, #20]
|
|
|
800327e: 4313 orrs r3, r2
|
|
|
8003280: 617b str r3, [r7, #20]
|
|
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
|
8003282: 687b ldr r3, [r7, #4]
|
|
|
8003284: 4a21 ldr r2, [pc, #132] ; (800330c <TIM_OC3_SetConfig+0xe4>)
|
|
|
8003286: 4293 cmp r3, r2
|
|
|
8003288: d10d bne.n 80032a6 <TIM_OC3_SetConfig+0x7e>
|
|
|
{
|
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
|
|
/* Reset the Output N Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
|
800328a: 697b ldr r3, [r7, #20]
|
|
|
800328c: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
|
8003290: 617b str r3, [r7, #20]
|
|
|
/* Set the Output N Polarity */
|
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
|
8003292: 683b ldr r3, [r7, #0]
|
|
|
8003294: 68db ldr r3, [r3, #12]
|
|
|
8003296: 021b lsls r3, r3, #8
|
|
|
8003298: 697a ldr r2, [r7, #20]
|
|
|
800329a: 4313 orrs r3, r2
|
|
|
800329c: 617b str r3, [r7, #20]
|
|
|
/* Reset the Output N State */
|
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
|
800329e: 697b ldr r3, [r7, #20]
|
|
|
80032a0: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
|
80032a4: 617b str r3, [r7, #20]
|
|
|
}
|
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
80032a6: 687b ldr r3, [r7, #4]
|
|
|
80032a8: 4a18 ldr r2, [pc, #96] ; (800330c <TIM_OC3_SetConfig+0xe4>)
|
|
|
80032aa: 4293 cmp r3, r2
|
|
|
80032ac: d007 beq.n 80032be <TIM_OC3_SetConfig+0x96>
|
|
|
80032ae: 687b ldr r3, [r7, #4]
|
|
|
80032b0: 4a17 ldr r2, [pc, #92] ; (8003310 <TIM_OC3_SetConfig+0xe8>)
|
|
|
80032b2: 4293 cmp r3, r2
|
|
|
80032b4: d003 beq.n 80032be <TIM_OC3_SetConfig+0x96>
|
|
|
80032b6: 687b ldr r3, [r7, #4]
|
|
|
80032b8: 4a16 ldr r2, [pc, #88] ; (8003314 <TIM_OC3_SetConfig+0xec>)
|
|
|
80032ba: 4293 cmp r3, r2
|
|
|
80032bc: d113 bne.n 80032e6 <TIM_OC3_SetConfig+0xbe>
|
|
|
/* Check parameters */
|
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
|
80032be: 693b ldr r3, [r7, #16]
|
|
|
80032c0: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
|
80032c4: 613b str r3, [r7, #16]
|
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
|
80032c6: 693b ldr r3, [r7, #16]
|
|
|
80032c8: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
|
80032cc: 613b str r3, [r7, #16]
|
|
|
/* Set the Output Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
|
80032ce: 683b ldr r3, [r7, #0]
|
|
|
80032d0: 695b ldr r3, [r3, #20]
|
|
|
80032d2: 011b lsls r3, r3, #4
|
|
|
80032d4: 693a ldr r2, [r7, #16]
|
|
|
80032d6: 4313 orrs r3, r2
|
|
|
80032d8: 613b str r3, [r7, #16]
|
|
|
/* Set the Output N Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
|
80032da: 683b ldr r3, [r7, #0]
|
|
|
80032dc: 699b ldr r3, [r3, #24]
|
|
|
80032de: 011b lsls r3, r3, #4
|
|
|
80032e0: 693a ldr r2, [r7, #16]
|
|
|
80032e2: 4313 orrs r3, r2
|
|
|
80032e4: 613b str r3, [r7, #16]
|
|
|
}
|
|
|
|
|
|
/* Write to TIMx CR2 */
|
|
|
TIMx->CR2 = tmpcr2;
|
|
|
80032e6: 687b ldr r3, [r7, #4]
|
|
|
80032e8: 693a ldr r2, [r7, #16]
|
|
|
80032ea: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
|
80032ec: 687b ldr r3, [r7, #4]
|
|
|
80032ee: 68fa ldr r2, [r7, #12]
|
|
|
80032f0: 61da str r2, [r3, #28]
|
|
|
|
|
|
/* Set the Capture Compare Register value */
|
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
|
80032f2: 683b ldr r3, [r7, #0]
|
|
|
80032f4: 685a ldr r2, [r3, #4]
|
|
|
80032f6: 687b ldr r3, [r7, #4]
|
|
|
80032f8: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Write to TIMx CCER */
|
|
|
TIMx->CCER = tmpccer;
|
|
|
80032fa: 687b ldr r3, [r7, #4]
|
|
|
80032fc: 697a ldr r2, [r7, #20]
|
|
|
80032fe: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
8003300: bf00 nop
|
|
|
8003302: 371c adds r7, #28
|
|
|
8003304: 46bd mov sp, r7
|
|
|
8003306: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800330a: 4770 bx lr
|
|
|
800330c: 40012c00 .word 0x40012c00
|
|
|
8003310: 40014000 .word 0x40014000
|
|
|
8003314: 40014400 .word 0x40014400
|
|
|
|
|
|
08003318 <TIM_OC4_SetConfig>:
|
|
|
* @param TIMx to select the TIM peripheral
|
|
|
* @param OC_Config The output configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
|
{
|
|
|
8003318: b480 push {r7}
|
|
|
800331a: b087 sub sp, #28
|
|
|
800331c: af00 add r7, sp, #0
|
|
|
800331e: 6078 str r0, [r7, #4]
|
|
|
8003320: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpccmrx;
|
|
|
uint32_t tmpccer;
|
|
|
uint32_t tmpcr2;
|
|
|
|
|
|
/* Get the TIMx CCER register value */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
8003322: 687b ldr r3, [r7, #4]
|
|
|
8003324: 6a1b ldr r3, [r3, #32]
|
|
|
8003326: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
|
8003328: 687b ldr r3, [r7, #4]
|
|
|
800332a: 6a1b ldr r3, [r3, #32]
|
|
|
800332c: f423 5280 bic.w r2, r3, #4096 ; 0x1000
|
|
|
8003330: 687b ldr r3, [r7, #4]
|
|
|
8003332: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = TIMx->CR2;
|
|
|
8003334: 687b ldr r3, [r7, #4]
|
|
|
8003336: 685b ldr r3, [r3, #4]
|
|
|
8003338: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
|
tmpccmrx = TIMx->CCMR2;
|
|
|
800333a: 687b ldr r3, [r7, #4]
|
|
|
800333c: 69db ldr r3, [r3, #28]
|
|
|
800333e: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
|
8003340: 68fb ldr r3, [r7, #12]
|
|
|
8003342: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
|
8003346: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
|
800334a: 60fb str r3, [r7, #12]
|
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
|
800334c: 68fb ldr r3, [r7, #12]
|
|
|
800334e: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
|
8003352: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Select the Output Compare Mode */
|
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
|
8003354: 683b ldr r3, [r7, #0]
|
|
|
8003356: 681b ldr r3, [r3, #0]
|
|
|
8003358: 021b lsls r3, r3, #8
|
|
|
800335a: 68fa ldr r2, [r7, #12]
|
|
|
800335c: 4313 orrs r3, r2
|
|
|
800335e: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
|
8003360: 693b ldr r3, [r7, #16]
|
|
|
8003362: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
|
8003366: 613b str r3, [r7, #16]
|
|
|
/* Set the Output Compare Polarity */
|
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
|
8003368: 683b ldr r3, [r7, #0]
|
|
|
800336a: 689b ldr r3, [r3, #8]
|
|
|
800336c: 031b lsls r3, r3, #12
|
|
|
800336e: 693a ldr r2, [r7, #16]
|
|
|
8003370: 4313 orrs r3, r2
|
|
|
8003372: 613b str r3, [r7, #16]
|
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
8003374: 687b ldr r3, [r7, #4]
|
|
|
8003376: 4a14 ldr r2, [pc, #80] ; (80033c8 <TIM_OC4_SetConfig+0xb0>)
|
|
|
8003378: 4293 cmp r3, r2
|
|
|
800337a: d007 beq.n 800338c <TIM_OC4_SetConfig+0x74>
|
|
|
800337c: 687b ldr r3, [r7, #4]
|
|
|
800337e: 4a13 ldr r2, [pc, #76] ; (80033cc <TIM_OC4_SetConfig+0xb4>)
|
|
|
8003380: 4293 cmp r3, r2
|
|
|
8003382: d003 beq.n 800338c <TIM_OC4_SetConfig+0x74>
|
|
|
8003384: 687b ldr r3, [r7, #4]
|
|
|
8003386: 4a12 ldr r2, [pc, #72] ; (80033d0 <TIM_OC4_SetConfig+0xb8>)
|
|
|
8003388: 4293 cmp r3, r2
|
|
|
800338a: d109 bne.n 80033a0 <TIM_OC4_SetConfig+0x88>
|
|
|
{
|
|
|
/* Check parameters */
|
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
|
800338c: 697b ldr r3, [r7, #20]
|
|
|
800338e: f423 4380 bic.w r3, r3, #16384 ; 0x4000
|
|
|
8003392: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Set the Output Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
|
8003394: 683b ldr r3, [r7, #0]
|
|
|
8003396: 695b ldr r3, [r3, #20]
|
|
|
8003398: 019b lsls r3, r3, #6
|
|
|
800339a: 697a ldr r2, [r7, #20]
|
|
|
800339c: 4313 orrs r3, r2
|
|
|
800339e: 617b str r3, [r7, #20]
|
|
|
}
|
|
|
|
|
|
/* Write to TIMx CR2 */
|
|
|
TIMx->CR2 = tmpcr2;
|
|
|
80033a0: 687b ldr r3, [r7, #4]
|
|
|
80033a2: 697a ldr r2, [r7, #20]
|
|
|
80033a4: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
|
80033a6: 687b ldr r3, [r7, #4]
|
|
|
80033a8: 68fa ldr r2, [r7, #12]
|
|
|
80033aa: 61da str r2, [r3, #28]
|
|
|
|
|
|
/* Set the Capture Compare Register value */
|
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
|
80033ac: 683b ldr r3, [r7, #0]
|
|
|
80033ae: 685a ldr r2, [r3, #4]
|
|
|
80033b0: 687b ldr r3, [r7, #4]
|
|
|
80033b2: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
|
|
/* Write to TIMx CCER */
|
|
|
TIMx->CCER = tmpccer;
|
|
|
80033b4: 687b ldr r3, [r7, #4]
|
|
|
80033b6: 693a ldr r2, [r7, #16]
|
|
|
80033b8: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
80033ba: bf00 nop
|
|
|
80033bc: 371c adds r7, #28
|
|
|
80033be: 46bd mov sp, r7
|
|
|
80033c0: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80033c4: 4770 bx lr
|
|
|
80033c6: bf00 nop
|
|
|
80033c8: 40012c00 .word 0x40012c00
|
|
|
80033cc: 40014000 .word 0x40014000
|
|
|
80033d0: 40014400 .word 0x40014400
|
|
|
|
|
|
080033d4 <TIM_OC5_SetConfig>:
|
|
|
* @param OC_Config The output configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
|
{
|
|
|
80033d4: b480 push {r7}
|
|
|
80033d6: b087 sub sp, #28
|
|
|
80033d8: af00 add r7, sp, #0
|
|
|
80033da: 6078 str r0, [r7, #4]
|
|
|
80033dc: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpccmrx;
|
|
|
uint32_t tmpccer;
|
|
|
uint32_t tmpcr2;
|
|
|
|
|
|
/* Get the TIMx CCER register value */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
80033de: 687b ldr r3, [r7, #4]
|
|
|
80033e0: 6a1b ldr r3, [r3, #32]
|
|
|
80033e2: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
|
80033e4: 687b ldr r3, [r7, #4]
|
|
|
80033e6: 6a1b ldr r3, [r3, #32]
|
|
|
80033e8: f423 3280 bic.w r2, r3, #65536 ; 0x10000
|
|
|
80033ec: 687b ldr r3, [r7, #4]
|
|
|
80033ee: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = TIMx->CR2;
|
|
|
80033f0: 687b ldr r3, [r7, #4]
|
|
|
80033f2: 685b ldr r3, [r3, #4]
|
|
|
80033f4: 617b str r3, [r7, #20]
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
|
tmpccmrx = TIMx->CCMR3;
|
|
|
80033f6: 687b ldr r3, [r7, #4]
|
|
|
80033f8: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
80033fa: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
|
80033fc: 68fb ldr r3, [r7, #12]
|
|
|
80033fe: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8003402: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
8003406: 60fb str r3, [r7, #12]
|
|
|
/* Select the Output Compare Mode */
|
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
|
8003408: 683b ldr r3, [r7, #0]
|
|
|
800340a: 681b ldr r3, [r3, #0]
|
|
|
800340c: 68fa ldr r2, [r7, #12]
|
|
|
800340e: 4313 orrs r3, r2
|
|
|
8003410: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Polarity level */
|
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
|
8003412: 693b ldr r3, [r7, #16]
|
|
|
8003414: f423 3300 bic.w r3, r3, #131072 ; 0x20000
|
|
|
8003418: 613b str r3, [r7, #16]
|
|
|
/* Set the Output Compare Polarity */
|
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
|
800341a: 683b ldr r3, [r7, #0]
|
|
|
800341c: 689b ldr r3, [r3, #8]
|
|
|
800341e: 041b lsls r3, r3, #16
|
|
|
8003420: 693a ldr r2, [r7, #16]
|
|
|
8003422: 4313 orrs r3, r2
|
|
|
8003424: 613b str r3, [r7, #16]
|
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
8003426: 687b ldr r3, [r7, #4]
|
|
|
8003428: 4a13 ldr r2, [pc, #76] ; (8003478 <TIM_OC5_SetConfig+0xa4>)
|
|
|
800342a: 4293 cmp r3, r2
|
|
|
800342c: d007 beq.n 800343e <TIM_OC5_SetConfig+0x6a>
|
|
|
800342e: 687b ldr r3, [r7, #4]
|
|
|
8003430: 4a12 ldr r2, [pc, #72] ; (800347c <TIM_OC5_SetConfig+0xa8>)
|
|
|
8003432: 4293 cmp r3, r2
|
|
|
8003434: d003 beq.n 800343e <TIM_OC5_SetConfig+0x6a>
|
|
|
8003436: 687b ldr r3, [r7, #4]
|
|
|
8003438: 4a11 ldr r2, [pc, #68] ; (8003480 <TIM_OC5_SetConfig+0xac>)
|
|
|
800343a: 4293 cmp r3, r2
|
|
|
800343c: d109 bne.n 8003452 <TIM_OC5_SetConfig+0x7e>
|
|
|
{
|
|
|
/* Reset the Output Compare IDLE State */
|
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
|
800343e: 697b ldr r3, [r7, #20]
|
|
|
8003440: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8003444: 617b str r3, [r7, #20]
|
|
|
/* Set the Output Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
|
8003446: 683b ldr r3, [r7, #0]
|
|
|
8003448: 695b ldr r3, [r3, #20]
|
|
|
800344a: 021b lsls r3, r3, #8
|
|
|
800344c: 697a ldr r2, [r7, #20]
|
|
|
800344e: 4313 orrs r3, r2
|
|
|
8003450: 617b str r3, [r7, #20]
|
|
|
}
|
|
|
/* Write to TIMx CR2 */
|
|
|
TIMx->CR2 = tmpcr2;
|
|
|
8003452: 687b ldr r3, [r7, #4]
|
|
|
8003454: 697a ldr r2, [r7, #20]
|
|
|
8003456: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
|
8003458: 687b ldr r3, [r7, #4]
|
|
|
800345a: 68fa ldr r2, [r7, #12]
|
|
|
800345c: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
|
|
/* Set the Capture Compare Register value */
|
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
|
800345e: 683b ldr r3, [r7, #0]
|
|
|
8003460: 685a ldr r2, [r3, #4]
|
|
|
8003462: 687b ldr r3, [r7, #4]
|
|
|
8003464: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
|
|
/* Write to TIMx CCER */
|
|
|
TIMx->CCER = tmpccer;
|
|
|
8003466: 687b ldr r3, [r7, #4]
|
|
|
8003468: 693a ldr r2, [r7, #16]
|
|
|
800346a: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
800346c: bf00 nop
|
|
|
800346e: 371c adds r7, #28
|
|
|
8003470: 46bd mov sp, r7
|
|
|
8003472: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003476: 4770 bx lr
|
|
|
8003478: 40012c00 .word 0x40012c00
|
|
|
800347c: 40014000 .word 0x40014000
|
|
|
8003480: 40014400 .word 0x40014400
|
|
|
|
|
|
08003484 <TIM_OC6_SetConfig>:
|
|
|
* @param OC_Config The output configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
|
{
|
|
|
8003484: b480 push {r7}
|
|
|
8003486: b087 sub sp, #28
|
|
|
8003488: af00 add r7, sp, #0
|
|
|
800348a: 6078 str r0, [r7, #4]
|
|
|
800348c: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpccmrx;
|
|
|
uint32_t tmpccer;
|
|
|
uint32_t tmpcr2;
|
|
|
|
|
|
/* Get the TIMx CCER register value */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
800348e: 687b ldr r3, [r7, #4]
|
|
|
8003490: 6a1b ldr r3, [r3, #32]
|
|
|
8003492: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
|
8003494: 687b ldr r3, [r7, #4]
|
|
|
8003496: 6a1b ldr r3, [r3, #32]
|
|
|
8003498: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
|
|
|
800349c: 687b ldr r3, [r7, #4]
|
|
|
800349e: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = TIMx->CR2;
|
|
|
80034a0: 687b ldr r3, [r7, #4]
|
|
|
80034a2: 685b ldr r3, [r3, #4]
|
|
|
80034a4: 617b str r3, [r7, #20]
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
|
tmpccmrx = TIMx->CCMR3;
|
|
|
80034a6: 687b ldr r3, [r7, #4]
|
|
|
80034a8: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
80034aa: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
|
80034ac: 68fb ldr r3, [r7, #12]
|
|
|
80034ae: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
|
80034b2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
|
80034b6: 60fb str r3, [r7, #12]
|
|
|
/* Select the Output Compare Mode */
|
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
|
80034b8: 683b ldr r3, [r7, #0]
|
|
|
80034ba: 681b ldr r3, [r3, #0]
|
|
|
80034bc: 021b lsls r3, r3, #8
|
|
|
80034be: 68fa ldr r2, [r7, #12]
|
|
|
80034c0: 4313 orrs r3, r2
|
|
|
80034c2: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Reset the Output Polarity level */
|
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
|
80034c4: 693b ldr r3, [r7, #16]
|
|
|
80034c6: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
|
|
|
80034ca: 613b str r3, [r7, #16]
|
|
|
/* Set the Output Compare Polarity */
|
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
|
80034cc: 683b ldr r3, [r7, #0]
|
|
|
80034ce: 689b ldr r3, [r3, #8]
|
|
|
80034d0: 051b lsls r3, r3, #20
|
|
|
80034d2: 693a ldr r2, [r7, #16]
|
|
|
80034d4: 4313 orrs r3, r2
|
|
|
80034d6: 613b str r3, [r7, #16]
|
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
80034d8: 687b ldr r3, [r7, #4]
|
|
|
80034da: 4a14 ldr r2, [pc, #80] ; (800352c <TIM_OC6_SetConfig+0xa8>)
|
|
|
80034dc: 4293 cmp r3, r2
|
|
|
80034de: d007 beq.n 80034f0 <TIM_OC6_SetConfig+0x6c>
|
|
|
80034e0: 687b ldr r3, [r7, #4]
|
|
|
80034e2: 4a13 ldr r2, [pc, #76] ; (8003530 <TIM_OC6_SetConfig+0xac>)
|
|
|
80034e4: 4293 cmp r3, r2
|
|
|
80034e6: d003 beq.n 80034f0 <TIM_OC6_SetConfig+0x6c>
|
|
|
80034e8: 687b ldr r3, [r7, #4]
|
|
|
80034ea: 4a12 ldr r2, [pc, #72] ; (8003534 <TIM_OC6_SetConfig+0xb0>)
|
|
|
80034ec: 4293 cmp r3, r2
|
|
|
80034ee: d109 bne.n 8003504 <TIM_OC6_SetConfig+0x80>
|
|
|
{
|
|
|
/* Reset the Output Compare IDLE State */
|
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
|
80034f0: 697b ldr r3, [r7, #20]
|
|
|
80034f2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
|
80034f6: 617b str r3, [r7, #20]
|
|
|
/* Set the Output Idle state */
|
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
|
80034f8: 683b ldr r3, [r7, #0]
|
|
|
80034fa: 695b ldr r3, [r3, #20]
|
|
|
80034fc: 029b lsls r3, r3, #10
|
|
|
80034fe: 697a ldr r2, [r7, #20]
|
|
|
8003500: 4313 orrs r3, r2
|
|
|
8003502: 617b str r3, [r7, #20]
|
|
|
}
|
|
|
|
|
|
/* Write to TIMx CR2 */
|
|
|
TIMx->CR2 = tmpcr2;
|
|
|
8003504: 687b ldr r3, [r7, #4]
|
|
|
8003506: 697a ldr r2, [r7, #20]
|
|
|
8003508: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
|
800350a: 687b ldr r3, [r7, #4]
|
|
|
800350c: 68fa ldr r2, [r7, #12]
|
|
|
800350e: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
|
|
/* Set the Capture Compare Register value */
|
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
|
8003510: 683b ldr r3, [r7, #0]
|
|
|
8003512: 685a ldr r2, [r3, #4]
|
|
|
8003514: 687b ldr r3, [r7, #4]
|
|
|
8003516: 65da str r2, [r3, #92] ; 0x5c
|
|
|
|
|
|
/* Write to TIMx CCER */
|
|
|
TIMx->CCER = tmpccer;
|
|
|
8003518: 687b ldr r3, [r7, #4]
|
|
|
800351a: 693a ldr r2, [r7, #16]
|
|
|
800351c: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
800351e: bf00 nop
|
|
|
8003520: 371c adds r7, #28
|
|
|
8003522: 46bd mov sp, r7
|
|
|
8003524: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003528: 4770 bx lr
|
|
|
800352a: bf00 nop
|
|
|
800352c: 40012c00 .word 0x40012c00
|
|
|
8003530: 40014000 .word 0x40014000
|
|
|
8003534: 40014400 .word 0x40014400
|
|
|
|
|
|
08003538 <TIM_TI1_ConfigInputStage>:
|
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
|
{
|
|
|
8003538: b480 push {r7}
|
|
|
800353a: b087 sub sp, #28
|
|
|
800353c: af00 add r7, sp, #0
|
|
|
800353e: 60f8 str r0, [r7, #12]
|
|
|
8003540: 60b9 str r1, [r7, #8]
|
|
|
8003542: 607a str r2, [r7, #4]
|
|
|
uint32_t tmpccmr1;
|
|
|
uint32_t tmpccer;
|
|
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
8003544: 68fb ldr r3, [r7, #12]
|
|
|
8003546: 6a1b ldr r3, [r3, #32]
|
|
|
8003548: 617b str r3, [r7, #20]
|
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
|
800354a: 68fb ldr r3, [r7, #12]
|
|
|
800354c: 6a1b ldr r3, [r3, #32]
|
|
|
800354e: f023 0201 bic.w r2, r3, #1
|
|
|
8003552: 68fb ldr r3, [r7, #12]
|
|
|
8003554: 621a str r2, [r3, #32]
|
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
|
8003556: 68fb ldr r3, [r7, #12]
|
|
|
8003558: 699b ldr r3, [r3, #24]
|
|
|
800355a: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Set the filter */
|
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
|
800355c: 693b ldr r3, [r7, #16]
|
|
|
800355e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
|
|
|
8003562: 613b str r3, [r7, #16]
|
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
|
8003564: 687b ldr r3, [r7, #4]
|
|
|
8003566: 011b lsls r3, r3, #4
|
|
|
8003568: 693a ldr r2, [r7, #16]
|
|
|
800356a: 4313 orrs r3, r2
|
|
|
800356c: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
|
800356e: 697b ldr r3, [r7, #20]
|
|
|
8003570: f023 030a bic.w r3, r3, #10
|
|
|
8003574: 617b str r3, [r7, #20]
|
|
|
tmpccer |= TIM_ICPolarity;
|
|
|
8003576: 697a ldr r2, [r7, #20]
|
|
|
8003578: 68bb ldr r3, [r7, #8]
|
|
|
800357a: 4313 orrs r3, r2
|
|
|
800357c: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
|
800357e: 68fb ldr r3, [r7, #12]
|
|
|
8003580: 693a ldr r2, [r7, #16]
|
|
|
8003582: 619a str r2, [r3, #24]
|
|
|
TIMx->CCER = tmpccer;
|
|
|
8003584: 68fb ldr r3, [r7, #12]
|
|
|
8003586: 697a ldr r2, [r7, #20]
|
|
|
8003588: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
800358a: bf00 nop
|
|
|
800358c: 371c adds r7, #28
|
|
|
800358e: 46bd mov sp, r7
|
|
|
8003590: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003594: 4770 bx lr
|
|
|
|
|
|
08003596 <TIM_TI2_ConfigInputStage>:
|
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
|
{
|
|
|
8003596: b480 push {r7}
|
|
|
8003598: b087 sub sp, #28
|
|
|
800359a: af00 add r7, sp, #0
|
|
|
800359c: 60f8 str r0, [r7, #12]
|
|
|
800359e: 60b9 str r1, [r7, #8]
|
|
|
80035a0: 607a str r2, [r7, #4]
|
|
|
uint32_t tmpccmr1;
|
|
|
uint32_t tmpccer;
|
|
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
80035a2: 68fb ldr r3, [r7, #12]
|
|
|
80035a4: 6a1b ldr r3, [r3, #32]
|
|
|
80035a6: 617b str r3, [r7, #20]
|
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
|
80035a8: 68fb ldr r3, [r7, #12]
|
|
|
80035aa: 6a1b ldr r3, [r3, #32]
|
|
|
80035ac: f023 0210 bic.w r2, r3, #16
|
|
|
80035b0: 68fb ldr r3, [r7, #12]
|
|
|
80035b2: 621a str r2, [r3, #32]
|
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
|
80035b4: 68fb ldr r3, [r7, #12]
|
|
|
80035b6: 699b ldr r3, [r3, #24]
|
|
|
80035b8: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Set the filter */
|
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
|
80035ba: 693b ldr r3, [r7, #16]
|
|
|
80035bc: f423 4370 bic.w r3, r3, #61440 ; 0xf000
|
|
|
80035c0: 613b str r3, [r7, #16]
|
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
|
80035c2: 687b ldr r3, [r7, #4]
|
|
|
80035c4: 031b lsls r3, r3, #12
|
|
|
80035c6: 693a ldr r2, [r7, #16]
|
|
|
80035c8: 4313 orrs r3, r2
|
|
|
80035ca: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
|
80035cc: 697b ldr r3, [r7, #20]
|
|
|
80035ce: f023 03a0 bic.w r3, r3, #160 ; 0xa0
|
|
|
80035d2: 617b str r3, [r7, #20]
|
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
|
80035d4: 68bb ldr r3, [r7, #8]
|
|
|
80035d6: 011b lsls r3, r3, #4
|
|
|
80035d8: 697a ldr r2, [r7, #20]
|
|
|
80035da: 4313 orrs r3, r2
|
|
|
80035dc: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
|
80035de: 68fb ldr r3, [r7, #12]
|
|
|
80035e0: 693a ldr r2, [r7, #16]
|
|
|
80035e2: 619a str r2, [r3, #24]
|
|
|
TIMx->CCER = tmpccer;
|
|
|
80035e4: 68fb ldr r3, [r7, #12]
|
|
|
80035e6: 697a ldr r2, [r7, #20]
|
|
|
80035e8: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
80035ea: bf00 nop
|
|
|
80035ec: 371c adds r7, #28
|
|
|
80035ee: 46bd mov sp, r7
|
|
|
80035f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
80035f4: 4770 bx lr
|
|
|
|
|
|
080035f6 <TIM_ITRx_SetConfig>:
|
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
|
{
|
|
|
80035f6: b480 push {r7}
|
|
|
80035f8: b085 sub sp, #20
|
|
|
80035fa: af00 add r7, sp, #0
|
|
|
80035fc: 6078 str r0, [r7, #4]
|
|
|
80035fe: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpsmcr;
|
|
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
|
8003600: 687b ldr r3, [r7, #4]
|
|
|
8003602: 689b ldr r3, [r3, #8]
|
|
|
8003604: 60fb str r3, [r7, #12]
|
|
|
/* Reset the TS Bits */
|
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
|
8003606: 68fb ldr r3, [r7, #12]
|
|
|
8003608: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
800360c: 60fb str r3, [r7, #12]
|
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
|
800360e: 683a ldr r2, [r7, #0]
|
|
|
8003610: 68fb ldr r3, [r7, #12]
|
|
|
8003612: 4313 orrs r3, r2
|
|
|
8003614: f043 0307 orr.w r3, r3, #7
|
|
|
8003618: 60fb str r3, [r7, #12]
|
|
|
/* Write to TIMx SMCR */
|
|
|
TIMx->SMCR = tmpsmcr;
|
|
|
800361a: 687b ldr r3, [r7, #4]
|
|
|
800361c: 68fa ldr r2, [r7, #12]
|
|
|
800361e: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
8003620: bf00 nop
|
|
|
8003622: 3714 adds r7, #20
|
|
|
8003624: 46bd mov sp, r7
|
|
|
8003626: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800362a: 4770 bx lr
|
|
|
|
|
|
0800362c <TIM_ETR_SetConfig>:
|
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
|
* @retval None
|
|
|
*/
|
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
|
{
|
|
|
800362c: b480 push {r7}
|
|
|
800362e: b087 sub sp, #28
|
|
|
8003630: af00 add r7, sp, #0
|
|
|
8003632: 60f8 str r0, [r7, #12]
|
|
|
8003634: 60b9 str r1, [r7, #8]
|
|
|
8003636: 607a str r2, [r7, #4]
|
|
|
8003638: 603b str r3, [r7, #0]
|
|
|
uint32_t tmpsmcr;
|
|
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
|
800363a: 68fb ldr r3, [r7, #12]
|
|
|
800363c: 689b ldr r3, [r3, #8]
|
|
|
800363e: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Reset the ETR Bits */
|
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
8003640: 697b ldr r3, [r7, #20]
|
|
|
8003642: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
|
8003646: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
|
8003648: 683b ldr r3, [r7, #0]
|
|
|
800364a: 021a lsls r2, r3, #8
|
|
|
800364c: 687b ldr r3, [r7, #4]
|
|
|
800364e: 431a orrs r2, r3
|
|
|
8003650: 68bb ldr r3, [r7, #8]
|
|
|
8003652: 4313 orrs r3, r2
|
|
|
8003654: 697a ldr r2, [r7, #20]
|
|
|
8003656: 4313 orrs r3, r2
|
|
|
8003658: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Write to TIMx SMCR */
|
|
|
TIMx->SMCR = tmpsmcr;
|
|
|
800365a: 68fb ldr r3, [r7, #12]
|
|
|
800365c: 697a ldr r2, [r7, #20]
|
|
|
800365e: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
8003660: bf00 nop
|
|
|
8003662: 371c adds r7, #28
|
|
|
8003664: 46bd mov sp, r7
|
|
|
8003666: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800366a: 4770 bx lr
|
|
|
|
|
|
0800366c <HAL_TIMEx_MasterConfigSynchronization>:
|
|
|
* mode.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
|
{
|
|
|
800366c: b480 push {r7}
|
|
|
800366e: b085 sub sp, #20
|
|
|
8003670: af00 add r7, sp, #0
|
|
|
8003672: 6078 str r0, [r7, #4]
|
|
|
8003674: 6039 str r1, [r7, #0]
|
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
|
|
/* Check input state */
|
|
|
__HAL_LOCK(htim);
|
|
|
8003676: 687b ldr r3, [r7, #4]
|
|
|
8003678: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
800367c: 2b01 cmp r3, #1
|
|
|
800367e: d101 bne.n 8003684 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
|
8003680: 2302 movs r3, #2
|
|
|
8003682: e04f b.n 8003724 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
|
8003684: 687b ldr r3, [r7, #4]
|
|
|
8003686: 2201 movs r2, #1
|
|
|
8003688: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Change the handler state */
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
800368c: 687b ldr r3, [r7, #4]
|
|
|
800368e: 2202 movs r2, #2
|
|
|
8003690: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = htim->Instance->CR2;
|
|
|
8003694: 687b ldr r3, [r7, #4]
|
|
|
8003696: 681b ldr r3, [r3, #0]
|
|
|
8003698: 685b ldr r3, [r3, #4]
|
|
|
800369a: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
800369c: 687b ldr r3, [r7, #4]
|
|
|
800369e: 681b ldr r3, [r3, #0]
|
|
|
80036a0: 689b ldr r3, [r3, #8]
|
|
|
80036a2: 60bb str r3, [r7, #8]
|
|
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
|
80036a4: 687b ldr r3, [r7, #4]
|
|
|
80036a6: 681b ldr r3, [r3, #0]
|
|
|
80036a8: 4a21 ldr r2, [pc, #132] ; (8003730 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
|
|
|
80036aa: 4293 cmp r3, r2
|
|
|
80036ac: d108 bne.n 80036c0 <HAL_TIMEx_MasterConfigSynchronization+0x54>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
|
|
/* Clear the MMS2 bits */
|
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
|
80036ae: 68fb ldr r3, [r7, #12]
|
|
|
80036b0: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
|
|
|
80036b4: 60fb str r3, [r7, #12]
|
|
|
/* Select the TRGO2 source*/
|
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
|
80036b6: 683b ldr r3, [r7, #0]
|
|
|
80036b8: 685b ldr r3, [r3, #4]
|
|
|
80036ba: 68fa ldr r2, [r7, #12]
|
|
|
80036bc: 4313 orrs r3, r2
|
|
|
80036be: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
/* Reset the MMS Bits */
|
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
|
80036c0: 68fb ldr r3, [r7, #12]
|
|
|
80036c2: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
80036c6: 60fb str r3, [r7, #12]
|
|
|
/* Select the TRGO source */
|
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
|
80036c8: 683b ldr r3, [r7, #0]
|
|
|
80036ca: 681b ldr r3, [r3, #0]
|
|
|
80036cc: 68fa ldr r2, [r7, #12]
|
|
|
80036ce: 4313 orrs r3, r2
|
|
|
80036d0: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Update TIMx CR2 */
|
|
|
htim->Instance->CR2 = tmpcr2;
|
|
|
80036d2: 687b ldr r3, [r7, #4]
|
|
|
80036d4: 681b ldr r3, [r3, #0]
|
|
|
80036d6: 68fa ldr r2, [r7, #12]
|
|
|
80036d8: 605a str r2, [r3, #4]
|
|
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
|
80036da: 687b ldr r3, [r7, #4]
|
|
|
80036dc: 681b ldr r3, [r3, #0]
|
|
|
80036de: 4a14 ldr r2, [pc, #80] ; (8003730 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
|
|
|
80036e0: 4293 cmp r3, r2
|
|
|
80036e2: d009 beq.n 80036f8 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
|
|
|
80036e4: 687b ldr r3, [r7, #4]
|
|
|
80036e6: 681b ldr r3, [r3, #0]
|
|
|
80036e8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
80036ec: d004 beq.n 80036f8 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
|
|
|
80036ee: 687b ldr r3, [r7, #4]
|
|
|
80036f0: 681b ldr r3, [r3, #0]
|
|
|
80036f2: 4a10 ldr r2, [pc, #64] ; (8003734 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
|
|
|
80036f4: 4293 cmp r3, r2
|
|
|
80036f6: d10c bne.n 8003712 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
|
{
|
|
|
/* Reset the MSM Bit */
|
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
|
80036f8: 68bb ldr r3, [r7, #8]
|
|
|
80036fa: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
|
80036fe: 60bb str r3, [r7, #8]
|
|
|
/* Set master mode */
|
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
|
8003700: 683b ldr r3, [r7, #0]
|
|
|
8003702: 689b ldr r3, [r3, #8]
|
|
|
8003704: 68ba ldr r2, [r7, #8]
|
|
|
8003706: 4313 orrs r3, r2
|
|
|
8003708: 60bb str r3, [r7, #8]
|
|
|
|
|
|
/* Update TIMx SMCR */
|
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
800370a: 687b ldr r3, [r7, #4]
|
|
|
800370c: 681b ldr r3, [r3, #0]
|
|
|
800370e: 68ba ldr r2, [r7, #8]
|
|
|
8003710: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
|
|
|
/* Change the htim state */
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
8003712: 687b ldr r3, [r7, #4]
|
|
|
8003714: 2201 movs r2, #1
|
|
|
8003716: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
800371a: 687b ldr r3, [r7, #4]
|
|
|
800371c: 2200 movs r2, #0
|
|
|
800371e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return HAL_OK;
|
|
|
8003722: 2300 movs r3, #0
|
|
|
}
|
|
|
8003724: 4618 mov r0, r3
|
|
|
8003726: 3714 adds r7, #20
|
|
|
8003728: 46bd mov sp, r7
|
|
|
800372a: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800372e: 4770 bx lr
|
|
|
8003730: 40012c00 .word 0x40012c00
|
|
|
8003734: 40014000 .word 0x40014000
|
|
|
|
|
|
08003738 <HAL_TIMEx_ConfigBreakDeadTime>:
|
|
|
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
|
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
|
|
|
{
|
|
|
8003738: b480 push {r7}
|
|
|
800373a: b085 sub sp, #20
|
|
|
800373c: af00 add r7, sp, #0
|
|
|
800373e: 6078 str r0, [r7, #4]
|
|
|
8003740: 6039 str r1, [r7, #0]
|
|
|
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
|
|
|
uint32_t tmpbdtr = 0U;
|
|
|
8003742: 2300 movs r3, #0
|
|
|
8003744: 60fb str r3, [r7, #12]
|
|
|
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
|
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
|
|
|
|
/* Check input state */
|
|
|
__HAL_LOCK(htim);
|
|
|
8003746: 687b ldr r3, [r7, #4]
|
|
|
8003748: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
800374c: 2b01 cmp r3, #1
|
|
|
800374e: d101 bne.n 8003754 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
|
|
|
8003750: 2302 movs r3, #2
|
|
|
8003752: e060 b.n 8003816 <HAL_TIMEx_ConfigBreakDeadTime+0xde>
|
|
|
8003754: 687b ldr r3, [r7, #4]
|
|
|
8003756: 2201 movs r2, #1
|
|
|
8003758: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
|
|
/* Set the BDTR bits */
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
|
800375c: 68fb ldr r3, [r7, #12]
|
|
|
800375e: f023 02ff bic.w r2, r3, #255 ; 0xff
|
|
|
8003762: 683b ldr r3, [r7, #0]
|
|
|
8003764: 68db ldr r3, [r3, #12]
|
|
|
8003766: 4313 orrs r3, r2
|
|
|
8003768: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
|
800376a: 68fb ldr r3, [r7, #12]
|
|
|
800376c: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
|
8003770: 683b ldr r3, [r7, #0]
|
|
|
8003772: 689b ldr r3, [r3, #8]
|
|
|
8003774: 4313 orrs r3, r2
|
|
|
8003776: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
|
8003778: 68fb ldr r3, [r7, #12]
|
|
|
800377a: f423 6280 bic.w r2, r3, #1024 ; 0x400
|
|
|
800377e: 683b ldr r3, [r7, #0]
|
|
|
8003780: 685b ldr r3, [r3, #4]
|
|
|
8003782: 4313 orrs r3, r2
|
|
|
8003784: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
|
8003786: 68fb ldr r3, [r7, #12]
|
|
|
8003788: f423 6200 bic.w r2, r3, #2048 ; 0x800
|
|
|
800378c: 683b ldr r3, [r7, #0]
|
|
|
800378e: 681b ldr r3, [r3, #0]
|
|
|
8003790: 4313 orrs r3, r2
|
|
|
8003792: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
|
8003794: 68fb ldr r3, [r7, #12]
|
|
|
8003796: f423 5280 bic.w r2, r3, #4096 ; 0x1000
|
|
|
800379a: 683b ldr r3, [r7, #0]
|
|
|
800379c: 691b ldr r3, [r3, #16]
|
|
|
800379e: 4313 orrs r3, r2
|
|
|
80037a0: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
|
80037a2: 68fb ldr r3, [r7, #12]
|
|
|
80037a4: f423 5200 bic.w r2, r3, #8192 ; 0x2000
|
|
|
80037a8: 683b ldr r3, [r7, #0]
|
|
|
80037aa: 695b ldr r3, [r3, #20]
|
|
|
80037ac: 4313 orrs r3, r2
|
|
|
80037ae: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
|
80037b0: 68fb ldr r3, [r7, #12]
|
|
|
80037b2: f423 4280 bic.w r2, r3, #16384 ; 0x4000
|
|
|
80037b6: 683b ldr r3, [r7, #0]
|
|
|
80037b8: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
|
80037ba: 4313 orrs r3, r2
|
|
|
80037bc: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
|
|
80037be: 68fb ldr r3, [r7, #12]
|
|
|
80037c0: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
|
|
|
80037c4: 683b ldr r3, [r7, #0]
|
|
|
80037c6: 699b ldr r3, [r3, #24]
|
|
|
80037c8: 041b lsls r3, r3, #16
|
|
|
80037ca: 4313 orrs r3, r2
|
|
|
80037cc: 60fb str r3, [r7, #12]
|
|
|
|
|
|
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
|
|
80037ce: 687b ldr r3, [r7, #4]
|
|
|
80037d0: 681b ldr r3, [r3, #0]
|
|
|
80037d2: 4a14 ldr r2, [pc, #80] ; (8003824 <HAL_TIMEx_ConfigBreakDeadTime+0xec>)
|
|
|
80037d4: 4293 cmp r3, r2
|
|
|
80037d6: d115 bne.n 8003804 <HAL_TIMEx_ConfigBreakDeadTime+0xcc>
|
|
|
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
|
|
|
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
|
|
|
|
|
/* Set the BREAK2 input related BDTR bits */
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
|
|
|
80037d8: 68fb ldr r3, [r7, #12]
|
|
|
80037da: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
|
|
|
80037de: 683b ldr r3, [r7, #0]
|
|
|
80037e0: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
80037e2: 051b lsls r3, r3, #20
|
|
|
80037e4: 4313 orrs r3, r2
|
|
|
80037e6: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
|
|
80037e8: 68fb ldr r3, [r7, #12]
|
|
|
80037ea: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
|
|
|
80037ee: 683b ldr r3, [r7, #0]
|
|
|
80037f0: 69db ldr r3, [r3, #28]
|
|
|
80037f2: 4313 orrs r3, r2
|
|
|
80037f4: 60fb str r3, [r7, #12]
|
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
|
|
80037f6: 68fb ldr r3, [r7, #12]
|
|
|
80037f8: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
|
|
|
80037fc: 683b ldr r3, [r7, #0]
|
|
|
80037fe: 6a1b ldr r3, [r3, #32]
|
|
|
8003800: 4313 orrs r3, r2
|
|
|
8003802: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
/* Set TIMx_BDTR */
|
|
|
htim->Instance->BDTR = tmpbdtr;
|
|
|
8003804: 687b ldr r3, [r7, #4]
|
|
|
8003806: 681b ldr r3, [r3, #0]
|
|
|
8003808: 68fa ldr r2, [r7, #12]
|
|
|
800380a: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
800380c: 687b ldr r3, [r7, #4]
|
|
|
800380e: 2200 movs r2, #0
|
|
|
8003810: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return HAL_OK;
|
|
|
8003814: 2300 movs r3, #0
|
|
|
}
|
|
|
8003816: 4618 mov r0, r3
|
|
|
8003818: 3714 adds r7, #20
|
|
|
800381a: 46bd mov sp, r7
|
|
|
800381c: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003820: 4770 bx lr
|
|
|
8003822: bf00 nop
|
|
|
8003824: 40012c00 .word 0x40012c00
|
|
|
|
|
|
08003828 <HAL_UART_Init>:
|
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
|
* @param huart UART handle.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8003828: b580 push {r7, lr}
|
|
|
800382a: b082 sub sp, #8
|
|
|
800382c: af00 add r7, sp, #0
|
|
|
800382e: 6078 str r0, [r7, #4]
|
|
|
/* Check the UART handle allocation */
|
|
|
if (huart == NULL)
|
|
|
8003830: 687b ldr r3, [r7, #4]
|
|
|
8003832: 2b00 cmp r3, #0
|
|
|
8003834: d101 bne.n 800383a <HAL_UART_Init+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8003836: 2301 movs r3, #1
|
|
|
8003838: e040 b.n 80038bc <HAL_UART_Init+0x94>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
|
}
|
|
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
|
800383a: 687b ldr r3, [r7, #4]
|
|
|
800383c: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
|
800383e: 2b00 cmp r3, #0
|
|
|
8003840: d106 bne.n 8003850 <HAL_UART_Init+0x28>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
huart->Lock = HAL_UNLOCKED;
|
|
|
8003842: 687b ldr r3, [r7, #4]
|
|
|
8003844: 2200 movs r2, #0
|
|
|
8003846: f883 2078 strb.w r2, [r3, #120] ; 0x78
|
|
|
|
|
|
/* Init the low level hardware */
|
|
|
huart->MspInitCallback(huart);
|
|
|
#else
|
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
|
HAL_UART_MspInit(huart);
|
|
|
800384a: 6878 ldr r0, [r7, #4]
|
|
|
800384c: f7fd f962 bl 8000b14 <HAL_UART_MspInit>
|
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
|
}
|
|
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
|
8003850: 687b ldr r3, [r7, #4]
|
|
|
8003852: 2224 movs r2, #36 ; 0x24
|
|
|
8003854: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
|
8003856: 687b ldr r3, [r7, #4]
|
|
|
8003858: 681b ldr r3, [r3, #0]
|
|
|
800385a: 681a ldr r2, [r3, #0]
|
|
|
800385c: 687b ldr r3, [r7, #4]
|
|
|
800385e: 681b ldr r3, [r3, #0]
|
|
|
8003860: f022 0201 bic.w r2, r2, #1
|
|
|
8003864: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Perform advanced settings configuration */
|
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
|
8003866: 687b ldr r3, [r7, #4]
|
|
|
8003868: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800386a: 2b00 cmp r3, #0
|
|
|
800386c: d002 beq.n 8003874 <HAL_UART_Init+0x4c>
|
|
|
{
|
|
|
UART_AdvFeatureConfig(huart);
|
|
|
800386e: 6878 ldr r0, [r7, #4]
|
|
|
8003870: f000 feb4 bl 80045dc <UART_AdvFeatureConfig>
|
|
|
}
|
|
|
|
|
|
/* Set the UART Communication parameters */
|
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
|
8003874: 6878 ldr r0, [r7, #4]
|
|
|
8003876: f000 fc57 bl 8004128 <UART_SetConfig>
|
|
|
800387a: 4603 mov r3, r0
|
|
|
800387c: 2b01 cmp r3, #1
|
|
|
800387e: d101 bne.n 8003884 <HAL_UART_Init+0x5c>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8003880: 2301 movs r3, #1
|
|
|
8003882: e01b b.n 80038bc <HAL_UART_Init+0x94>
|
|
|
}
|
|
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
|
8003884: 687b ldr r3, [r7, #4]
|
|
|
8003886: 681b ldr r3, [r3, #0]
|
|
|
8003888: 685a ldr r2, [r3, #4]
|
|
|
800388a: 687b ldr r3, [r7, #4]
|
|
|
800388c: 681b ldr r3, [r3, #0]
|
|
|
800388e: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
|
|
8003892: 605a str r2, [r3, #4]
|
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
|
8003894: 687b ldr r3, [r7, #4]
|
|
|
8003896: 681b ldr r3, [r3, #0]
|
|
|
8003898: 689a ldr r2, [r3, #8]
|
|
|
800389a: 687b ldr r3, [r7, #4]
|
|
|
800389c: 681b ldr r3, [r3, #0]
|
|
|
800389e: f022 022a bic.w r2, r2, #42 ; 0x2a
|
|
|
80038a2: 609a str r2, [r3, #8]
|
|
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
|
80038a4: 687b ldr r3, [r7, #4]
|
|
|
80038a6: 681b ldr r3, [r3, #0]
|
|
|
80038a8: 681a ldr r2, [r3, #0]
|
|
|
80038aa: 687b ldr r3, [r7, #4]
|
|
|
80038ac: 681b ldr r3, [r3, #0]
|
|
|
80038ae: f042 0201 orr.w r2, r2, #1
|
|
|
80038b2: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
|
return (UART_CheckIdleState(huart));
|
|
|
80038b4: 6878 ldr r0, [r7, #4]
|
|
|
80038b6: f000 ff33 bl 8004720 <UART_CheckIdleState>
|
|
|
80038ba: 4603 mov r3, r0
|
|
|
}
|
|
|
80038bc: 4618 mov r0, r3
|
|
|
80038be: 3708 adds r7, #8
|
|
|
80038c0: 46bd mov sp, r7
|
|
|
80038c2: bd80 pop {r7, pc}
|
|
|
|
|
|
080038c4 <HAL_UART_Transmit>:
|
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
|
* @param Timeout Timeout duration.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
|
{
|
|
|
80038c4: b580 push {r7, lr}
|
|
|
80038c6: b08a sub sp, #40 ; 0x28
|
|
|
80038c8: af02 add r7, sp, #8
|
|
|
80038ca: 60f8 str r0, [r7, #12]
|
|
|
80038cc: 60b9 str r1, [r7, #8]
|
|
|
80038ce: 603b str r3, [r7, #0]
|
|
|
80038d0: 4613 mov r3, r2
|
|
|
80038d2: 80fb strh r3, [r7, #6]
|
|
|
const uint8_t *pdata8bits;
|
|
|
const uint16_t *pdata16bits;
|
|
|
uint32_t tickstart;
|
|
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
|
80038d4: 68fb ldr r3, [r7, #12]
|
|
|
80038d6: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
|
80038d8: 2b20 cmp r3, #32
|
|
|
80038da: d178 bne.n 80039ce <HAL_UART_Transmit+0x10a>
|
|
|
{
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
|
80038dc: 68bb ldr r3, [r7, #8]
|
|
|
80038de: 2b00 cmp r3, #0
|
|
|
80038e0: d002 beq.n 80038e8 <HAL_UART_Transmit+0x24>
|
|
|
80038e2: 88fb ldrh r3, [r7, #6]
|
|
|
80038e4: 2b00 cmp r3, #0
|
|
|
80038e6: d101 bne.n 80038ec <HAL_UART_Transmit+0x28>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80038e8: 2301 movs r3, #1
|
|
|
80038ea: e071 b.n 80039d0 <HAL_UART_Transmit+0x10c>
|
|
|
}
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
80038ec: 68fb ldr r3, [r7, #12]
|
|
|
80038ee: 2200 movs r2, #0
|
|
|
80038f0: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
|
80038f4: 68fb ldr r3, [r7, #12]
|
|
|
80038f6: 2221 movs r2, #33 ; 0x21
|
|
|
80038f8: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
/* Init tickstart for timeout management */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80038fa: f7fd fb95 bl 8001028 <HAL_GetTick>
|
|
|
80038fe: 6178 str r0, [r7, #20]
|
|
|
|
|
|
huart->TxXferSize = Size;
|
|
|
8003900: 68fb ldr r3, [r7, #12]
|
|
|
8003902: 88fa ldrh r2, [r7, #6]
|
|
|
8003904: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
|
|
|
huart->TxXferCount = Size;
|
|
|
8003908: 68fb ldr r3, [r7, #12]
|
|
|
800390a: 88fa ldrh r2, [r7, #6]
|
|
|
800390c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
|
8003910: 68fb ldr r3, [r7, #12]
|
|
|
8003912: 689b ldr r3, [r3, #8]
|
|
|
8003914: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8003918: d108 bne.n 800392c <HAL_UART_Transmit+0x68>
|
|
|
800391a: 68fb ldr r3, [r7, #12]
|
|
|
800391c: 691b ldr r3, [r3, #16]
|
|
|
800391e: 2b00 cmp r3, #0
|
|
|
8003920: d104 bne.n 800392c <HAL_UART_Transmit+0x68>
|
|
|
{
|
|
|
pdata8bits = NULL;
|
|
|
8003922: 2300 movs r3, #0
|
|
|
8003924: 61fb str r3, [r7, #28]
|
|
|
pdata16bits = (const uint16_t *) pData;
|
|
|
8003926: 68bb ldr r3, [r7, #8]
|
|
|
8003928: 61bb str r3, [r7, #24]
|
|
|
800392a: e003 b.n 8003934 <HAL_UART_Transmit+0x70>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
pdata8bits = pData;
|
|
|
800392c: 68bb ldr r3, [r7, #8]
|
|
|
800392e: 61fb str r3, [r7, #28]
|
|
|
pdata16bits = NULL;
|
|
|
8003930: 2300 movs r3, #0
|
|
|
8003932: 61bb str r3, [r7, #24]
|
|
|
}
|
|
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
|
8003934: e030 b.n 8003998 <HAL_UART_Transmit+0xd4>
|
|
|
{
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
|
8003936: 683b ldr r3, [r7, #0]
|
|
|
8003938: 9300 str r3, [sp, #0]
|
|
|
800393a: 697b ldr r3, [r7, #20]
|
|
|
800393c: 2200 movs r2, #0
|
|
|
800393e: 2180 movs r1, #128 ; 0x80
|
|
|
8003940: 68f8 ldr r0, [r7, #12]
|
|
|
8003942: f000 ff95 bl 8004870 <UART_WaitOnFlagUntilTimeout>
|
|
|
8003946: 4603 mov r3, r0
|
|
|
8003948: 2b00 cmp r3, #0
|
|
|
800394a: d004 beq.n 8003956 <HAL_UART_Transmit+0x92>
|
|
|
{
|
|
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
800394c: 68fb ldr r3, [r7, #12]
|
|
|
800394e: 2220 movs r2, #32
|
|
|
8003950: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
return HAL_TIMEOUT;
|
|
|
8003952: 2303 movs r3, #3
|
|
|
8003954: e03c b.n 80039d0 <HAL_UART_Transmit+0x10c>
|
|
|
}
|
|
|
if (pdata8bits == NULL)
|
|
|
8003956: 69fb ldr r3, [r7, #28]
|
|
|
8003958: 2b00 cmp r3, #0
|
|
|
800395a: d10b bne.n 8003974 <HAL_UART_Transmit+0xb0>
|
|
|
{
|
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
|
800395c: 69bb ldr r3, [r7, #24]
|
|
|
800395e: 881a ldrh r2, [r3, #0]
|
|
|
8003960: 68fb ldr r3, [r7, #12]
|
|
|
8003962: 681b ldr r3, [r3, #0]
|
|
|
8003964: f3c2 0208 ubfx r2, r2, #0, #9
|
|
|
8003968: b292 uxth r2, r2
|
|
|
800396a: 851a strh r2, [r3, #40] ; 0x28
|
|
|
pdata16bits++;
|
|
|
800396c: 69bb ldr r3, [r7, #24]
|
|
|
800396e: 3302 adds r3, #2
|
|
|
8003970: 61bb str r3, [r7, #24]
|
|
|
8003972: e008 b.n 8003986 <HAL_UART_Transmit+0xc2>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
|
8003974: 69fb ldr r3, [r7, #28]
|
|
|
8003976: 781a ldrb r2, [r3, #0]
|
|
|
8003978: 68fb ldr r3, [r7, #12]
|
|
|
800397a: 681b ldr r3, [r3, #0]
|
|
|
800397c: b292 uxth r2, r2
|
|
|
800397e: 851a strh r2, [r3, #40] ; 0x28
|
|
|
pdata8bits++;
|
|
|
8003980: 69fb ldr r3, [r7, #28]
|
|
|
8003982: 3301 adds r3, #1
|
|
|
8003984: 61fb str r3, [r7, #28]
|
|
|
}
|
|
|
huart->TxXferCount--;
|
|
|
8003986: 68fb ldr r3, [r7, #12]
|
|
|
8003988: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
|
800398c: b29b uxth r3, r3
|
|
|
800398e: 3b01 subs r3, #1
|
|
|
8003990: b29a uxth r2, r3
|
|
|
8003992: 68fb ldr r3, [r7, #12]
|
|
|
8003994: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
while (huart->TxXferCount > 0U)
|
|
|
8003998: 68fb ldr r3, [r7, #12]
|
|
|
800399a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
|
800399e: b29b uxth r3, r3
|
|
|
80039a0: 2b00 cmp r3, #0
|
|
|
80039a2: d1c8 bne.n 8003936 <HAL_UART_Transmit+0x72>
|
|
|
}
|
|
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
|
80039a4: 683b ldr r3, [r7, #0]
|
|
|
80039a6: 9300 str r3, [sp, #0]
|
|
|
80039a8: 697b ldr r3, [r7, #20]
|
|
|
80039aa: 2200 movs r2, #0
|
|
|
80039ac: 2140 movs r1, #64 ; 0x40
|
|
|
80039ae: 68f8 ldr r0, [r7, #12]
|
|
|
80039b0: f000 ff5e bl 8004870 <UART_WaitOnFlagUntilTimeout>
|
|
|
80039b4: 4603 mov r3, r0
|
|
|
80039b6: 2b00 cmp r3, #0
|
|
|
80039b8: d004 beq.n 80039c4 <HAL_UART_Transmit+0x100>
|
|
|
{
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
80039ba: 68fb ldr r3, [r7, #12]
|
|
|
80039bc: 2220 movs r2, #32
|
|
|
80039be: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
return HAL_TIMEOUT;
|
|
|
80039c0: 2303 movs r3, #3
|
|
|
80039c2: e005 b.n 80039d0 <HAL_UART_Transmit+0x10c>
|
|
|
}
|
|
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
80039c4: 68fb ldr r3, [r7, #12]
|
|
|
80039c6: 2220 movs r2, #32
|
|
|
80039c8: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
return HAL_OK;
|
|
|
80039ca: 2300 movs r3, #0
|
|
|
80039cc: e000 b.n 80039d0 <HAL_UART_Transmit+0x10c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return HAL_BUSY;
|
|
|
80039ce: 2302 movs r3, #2
|
|
|
}
|
|
|
}
|
|
|
80039d0: 4618 mov r0, r3
|
|
|
80039d2: 3720 adds r7, #32
|
|
|
80039d4: 46bd mov sp, r7
|
|
|
80039d6: bd80 pop {r7, pc}
|
|
|
|
|
|
080039d8 <HAL_UART_Transmit_IT>:
|
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
|
{
|
|
|
80039d8: b480 push {r7}
|
|
|
80039da: b08b sub sp, #44 ; 0x2c
|
|
|
80039dc: af00 add r7, sp, #0
|
|
|
80039de: 60f8 str r0, [r7, #12]
|
|
|
80039e0: 60b9 str r1, [r7, #8]
|
|
|
80039e2: 4613 mov r3, r2
|
|
|
80039e4: 80fb strh r3, [r7, #6]
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
|
80039e6: 68fb ldr r3, [r7, #12]
|
|
|
80039e8: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
|
80039ea: 2b20 cmp r3, #32
|
|
|
80039ec: d147 bne.n 8003a7e <HAL_UART_Transmit_IT+0xa6>
|
|
|
{
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
|
80039ee: 68bb ldr r3, [r7, #8]
|
|
|
80039f0: 2b00 cmp r3, #0
|
|
|
80039f2: d002 beq.n 80039fa <HAL_UART_Transmit_IT+0x22>
|
|
|
80039f4: 88fb ldrh r3, [r7, #6]
|
|
|
80039f6: 2b00 cmp r3, #0
|
|
|
80039f8: d101 bne.n 80039fe <HAL_UART_Transmit_IT+0x26>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80039fa: 2301 movs r3, #1
|
|
|
80039fc: e040 b.n 8003a80 <HAL_UART_Transmit_IT+0xa8>
|
|
|
}
|
|
|
|
|
|
huart->pTxBuffPtr = pData;
|
|
|
80039fe: 68fb ldr r3, [r7, #12]
|
|
|
8003a00: 68ba ldr r2, [r7, #8]
|
|
|
8003a02: 64da str r2, [r3, #76] ; 0x4c
|
|
|
huart->TxXferSize = Size;
|
|
|
8003a04: 68fb ldr r3, [r7, #12]
|
|
|
8003a06: 88fa ldrh r2, [r7, #6]
|
|
|
8003a08: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
|
|
|
huart->TxXferCount = Size;
|
|
|
8003a0c: 68fb ldr r3, [r7, #12]
|
|
|
8003a0e: 88fa ldrh r2, [r7, #6]
|
|
|
8003a10: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
huart->TxISR = NULL;
|
|
|
8003a14: 68fb ldr r3, [r7, #12]
|
|
|
8003a16: 2200 movs r2, #0
|
|
|
8003a18: 66da str r2, [r3, #108] ; 0x6c
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
8003a1a: 68fb ldr r3, [r7, #12]
|
|
|
8003a1c: 2200 movs r2, #0
|
|
|
8003a1e: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
|
8003a22: 68fb ldr r3, [r7, #12]
|
|
|
8003a24: 2221 movs r2, #33 ; 0x21
|
|
|
8003a26: 67da str r2, [r3, #124] ; 0x7c
|
|
|
/* Enable the Transmit Data Register Empty interrupt */
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
|
|
}
|
|
|
#else
|
|
|
/* Set the Tx ISR function pointer according to the data word length */
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
|
8003a28: 68fb ldr r3, [r7, #12]
|
|
|
8003a2a: 689b ldr r3, [r3, #8]
|
|
|
8003a2c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8003a30: d107 bne.n 8003a42 <HAL_UART_Transmit_IT+0x6a>
|
|
|
8003a32: 68fb ldr r3, [r7, #12]
|
|
|
8003a34: 691b ldr r3, [r3, #16]
|
|
|
8003a36: 2b00 cmp r3, #0
|
|
|
8003a38: d103 bne.n 8003a42 <HAL_UART_Transmit_IT+0x6a>
|
|
|
{
|
|
|
huart->TxISR = UART_TxISR_16BIT;
|
|
|
8003a3a: 68fb ldr r3, [r7, #12]
|
|
|
8003a3c: 4a13 ldr r2, [pc, #76] ; (8003a8c <HAL_UART_Transmit_IT+0xb4>)
|
|
|
8003a3e: 66da str r2, [r3, #108] ; 0x6c
|
|
|
8003a40: e002 b.n 8003a48 <HAL_UART_Transmit_IT+0x70>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
huart->TxISR = UART_TxISR_8BIT;
|
|
|
8003a42: 68fb ldr r3, [r7, #12]
|
|
|
8003a44: 4a12 ldr r2, [pc, #72] ; (8003a90 <HAL_UART_Transmit_IT+0xb8>)
|
|
|
8003a46: 66da str r2, [r3, #108] ; 0x6c
|
|
|
}
|
|
|
|
|
|
/* Enable the Transmit Data Register Empty interrupt */
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|
|
8003a48: 68fb ldr r3, [r7, #12]
|
|
|
8003a4a: 681b ldr r3, [r3, #0]
|
|
|
8003a4c: 617b str r3, [r7, #20]
|
|
|
*/
|
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
|
{
|
|
|
uint32_t result;
|
|
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003a4e: 697b ldr r3, [r7, #20]
|
|
|
8003a50: e853 3f00 ldrex r3, [r3]
|
|
|
8003a54: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
8003a56: 693b ldr r3, [r7, #16]
|
|
|
8003a58: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
|
8003a5c: 627b str r3, [r7, #36] ; 0x24
|
|
|
8003a5e: 68fb ldr r3, [r7, #12]
|
|
|
8003a60: 681b ldr r3, [r3, #0]
|
|
|
8003a62: 461a mov r2, r3
|
|
|
8003a64: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8003a66: 623b str r3, [r7, #32]
|
|
|
8003a68: 61fa str r2, [r7, #28]
|
|
|
*/
|
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
|
{
|
|
|
uint32_t result;
|
|
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003a6a: 69f9 ldr r1, [r7, #28]
|
|
|
8003a6c: 6a3a ldr r2, [r7, #32]
|
|
|
8003a6e: e841 2300 strex r3, r2, [r1]
|
|
|
8003a72: 61bb str r3, [r7, #24]
|
|
|
return(result);
|
|
|
8003a74: 69bb ldr r3, [r7, #24]
|
|
|
8003a76: 2b00 cmp r3, #0
|
|
|
8003a78: d1e6 bne.n 8003a48 <HAL_UART_Transmit_IT+0x70>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
return HAL_OK;
|
|
|
8003a7a: 2300 movs r3, #0
|
|
|
8003a7c: e000 b.n 8003a80 <HAL_UART_Transmit_IT+0xa8>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return HAL_BUSY;
|
|
|
8003a7e: 2302 movs r3, #2
|
|
|
}
|
|
|
}
|
|
|
8003a80: 4618 mov r0, r3
|
|
|
8003a82: 372c adds r7, #44 ; 0x2c
|
|
|
8003a84: 46bd mov sp, r7
|
|
|
8003a86: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8003a8a: 4770 bx lr
|
|
|
8003a8c: 08004c79 .word 0x08004c79
|
|
|
8003a90: 08004bc1 .word 0x08004bc1
|
|
|
|
|
|
08003a94 <HAL_UART_Receive_IT>:
|
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
|
{
|
|
|
8003a94: b580 push {r7, lr}
|
|
|
8003a96: b08a sub sp, #40 ; 0x28
|
|
|
8003a98: af00 add r7, sp, #0
|
|
|
8003a9a: 60f8 str r0, [r7, #12]
|
|
|
8003a9c: 60b9 str r1, [r7, #8]
|
|
|
8003a9e: 4613 mov r3, r2
|
|
|
8003aa0: 80fb strh r3, [r7, #6]
|
|
|
/* Check that a Rx process is not already ongoing */
|
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
|
8003aa2: 68fb ldr r3, [r7, #12]
|
|
|
8003aa4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
|
8003aa8: 2b20 cmp r3, #32
|
|
|
8003aaa: d137 bne.n 8003b1c <HAL_UART_Receive_IT+0x88>
|
|
|
{
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
|
8003aac: 68bb ldr r3, [r7, #8]
|
|
|
8003aae: 2b00 cmp r3, #0
|
|
|
8003ab0: d002 beq.n 8003ab8 <HAL_UART_Receive_IT+0x24>
|
|
|
8003ab2: 88fb ldrh r3, [r7, #6]
|
|
|
8003ab4: 2b00 cmp r3, #0
|
|
|
8003ab6: d101 bne.n 8003abc <HAL_UART_Receive_IT+0x28>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8003ab8: 2301 movs r3, #1
|
|
|
8003aba: e030 b.n 8003b1e <HAL_UART_Receive_IT+0x8a>
|
|
|
}
|
|
|
|
|
|
/* Set Reception type to Standard reception */
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
8003abc: 68fb ldr r3, [r7, #12]
|
|
|
8003abe: 2200 movs r2, #0
|
|
|
8003ac0: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
|
8003ac2: 68fb ldr r3, [r7, #12]
|
|
|
8003ac4: 681b ldr r3, [r3, #0]
|
|
|
8003ac6: 4a18 ldr r2, [pc, #96] ; (8003b28 <HAL_UART_Receive_IT+0x94>)
|
|
|
8003ac8: 4293 cmp r3, r2
|
|
|
8003aca: d01f beq.n 8003b0c <HAL_UART_Receive_IT+0x78>
|
|
|
{
|
|
|
/* Check that USART RTOEN bit is set */
|
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
|
8003acc: 68fb ldr r3, [r7, #12]
|
|
|
8003ace: 681b ldr r3, [r3, #0]
|
|
|
8003ad0: 685b ldr r3, [r3, #4]
|
|
|
8003ad2: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
|
8003ad6: 2b00 cmp r3, #0
|
|
|
8003ad8: d018 beq.n 8003b0c <HAL_UART_Receive_IT+0x78>
|
|
|
{
|
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
|
8003ada: 68fb ldr r3, [r7, #12]
|
|
|
8003adc: 681b ldr r3, [r3, #0]
|
|
|
8003ade: 617b str r3, [r7, #20]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003ae0: 697b ldr r3, [r7, #20]
|
|
|
8003ae2: e853 3f00 ldrex r3, [r3]
|
|
|
8003ae6: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
8003ae8: 693b ldr r3, [r7, #16]
|
|
|
8003aea: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
|
|
8003aee: 627b str r3, [r7, #36] ; 0x24
|
|
|
8003af0: 68fb ldr r3, [r7, #12]
|
|
|
8003af2: 681b ldr r3, [r3, #0]
|
|
|
8003af4: 461a mov r2, r3
|
|
|
8003af6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8003af8: 623b str r3, [r7, #32]
|
|
|
8003afa: 61fa str r2, [r7, #28]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003afc: 69f9 ldr r1, [r7, #28]
|
|
|
8003afe: 6a3a ldr r2, [r7, #32]
|
|
|
8003b00: e841 2300 strex r3, r2, [r1]
|
|
|
8003b04: 61bb str r3, [r7, #24]
|
|
|
return(result);
|
|
|
8003b06: 69bb ldr r3, [r7, #24]
|
|
|
8003b08: 2b00 cmp r3, #0
|
|
|
8003b0a: d1e6 bne.n 8003ada <HAL_UART_Receive_IT+0x46>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return (UART_Start_Receive_IT(huart, pData, Size));
|
|
|
8003b0c: 88fb ldrh r3, [r7, #6]
|
|
|
8003b0e: 461a mov r2, r3
|
|
|
8003b10: 68b9 ldr r1, [r7, #8]
|
|
|
8003b12: 68f8 ldr r0, [r7, #12]
|
|
|
8003b14: f000 ff14 bl 8004940 <UART_Start_Receive_IT>
|
|
|
8003b18: 4603 mov r3, r0
|
|
|
8003b1a: e000 b.n 8003b1e <HAL_UART_Receive_IT+0x8a>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return HAL_BUSY;
|
|
|
8003b1c: 2302 movs r3, #2
|
|
|
}
|
|
|
}
|
|
|
8003b1e: 4618 mov r0, r3
|
|
|
8003b20: 3728 adds r7, #40 ; 0x28
|
|
|
8003b22: 46bd mov sp, r7
|
|
|
8003b24: bd80 pop {r7, pc}
|
|
|
8003b26: bf00 nop
|
|
|
8003b28: 40008000 .word 0x40008000
|
|
|
|
|
|
08003b2c <HAL_UART_IRQHandler>:
|
|
|
* @brief Handle UART interrupt request.
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8003b2c: b580 push {r7, lr}
|
|
|
8003b2e: b0ba sub sp, #232 ; 0xe8
|
|
|
8003b30: af00 add r7, sp, #0
|
|
|
8003b32: 6078 str r0, [r7, #4]
|
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
|
8003b34: 687b ldr r3, [r7, #4]
|
|
|
8003b36: 681b ldr r3, [r3, #0]
|
|
|
8003b38: 69db ldr r3, [r3, #28]
|
|
|
8003b3a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
|
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
|
8003b3e: 687b ldr r3, [r7, #4]
|
|
|
8003b40: 681b ldr r3, [r3, #0]
|
|
|
8003b42: 681b ldr r3, [r3, #0]
|
|
|
8003b44: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
|
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
|
8003b48: 687b ldr r3, [r7, #4]
|
|
|
8003b4a: 681b ldr r3, [r3, #0]
|
|
|
8003b4c: 689b ldr r3, [r3, #8]
|
|
|
8003b4e: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
|
|
|
|
|
|
uint32_t errorflags;
|
|
|
uint32_t errorcode;
|
|
|
|
|
|
/* If no error occurs */
|
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
|
8003b52: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4
|
|
|
8003b56: f640 030f movw r3, #2063 ; 0x80f
|
|
|
8003b5a: 4013 ands r3, r2
|
|
|
8003b5c: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
|
|
|
if (errorflags == 0U)
|
|
|
8003b60: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
|
|
|
8003b64: 2b00 cmp r3, #0
|
|
|
8003b66: d115 bne.n 8003b94 <HAL_UART_IRQHandler+0x68>
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
|
#else
|
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
|
8003b68: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003b6c: f003 0320 and.w r3, r3, #32
|
|
|
8003b70: 2b00 cmp r3, #0
|
|
|
8003b72: d00f beq.n 8003b94 <HAL_UART_IRQHandler+0x68>
|
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
|
8003b74: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
8003b78: f003 0320 and.w r3, r3, #32
|
|
|
8003b7c: 2b00 cmp r3, #0
|
|
|
8003b7e: d009 beq.n 8003b94 <HAL_UART_IRQHandler+0x68>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
{
|
|
|
if (huart->RxISR != NULL)
|
|
|
8003b80: 687b ldr r3, [r7, #4]
|
|
|
8003b82: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
|
8003b84: 2b00 cmp r3, #0
|
|
|
8003b86: f000 82ae beq.w 80040e6 <HAL_UART_IRQHandler+0x5ba>
|
|
|
{
|
|
|
huart->RxISR(huart);
|
|
|
8003b8a: 687b ldr r3, [r7, #4]
|
|
|
8003b8c: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
|
8003b8e: 6878 ldr r0, [r7, #4]
|
|
|
8003b90: 4798 blx r3
|
|
|
}
|
|
|
return;
|
|
|
8003b92: e2a8 b.n 80040e6 <HAL_UART_IRQHandler+0x5ba>
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
if ((errorflags != 0U)
|
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
|
#else
|
|
|
if ((errorflags != 0U)
|
|
|
8003b94: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
|
|
|
8003b98: 2b00 cmp r3, #0
|
|
|
8003b9a: f000 8117 beq.w 8003dcc <HAL_UART_IRQHandler+0x2a0>
|
|
|
&& (((cr3its & USART_CR3_EIE) != 0U)
|
|
|
8003b9e: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
|
|
|
8003ba2: f003 0301 and.w r3, r3, #1
|
|
|
8003ba6: 2b00 cmp r3, #0
|
|
|
8003ba8: d106 bne.n 8003bb8 <HAL_UART_IRQHandler+0x8c>
|
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
|
|
|
8003baa: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0
|
|
|
8003bae: 4b85 ldr r3, [pc, #532] ; (8003dc4 <HAL_UART_IRQHandler+0x298>)
|
|
|
8003bb0: 4013 ands r3, r2
|
|
|
8003bb2: 2b00 cmp r3, #0
|
|
|
8003bb4: f000 810a beq.w 8003dcc <HAL_UART_IRQHandler+0x2a0>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
{
|
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
|
8003bb8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003bbc: f003 0301 and.w r3, r3, #1
|
|
|
8003bc0: 2b00 cmp r3, #0
|
|
|
8003bc2: d011 beq.n 8003be8 <HAL_UART_IRQHandler+0xbc>
|
|
|
8003bc4: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
8003bc8: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8003bcc: 2b00 cmp r3, #0
|
|
|
8003bce: d00b beq.n 8003be8 <HAL_UART_IRQHandler+0xbc>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
|
8003bd0: 687b ldr r3, [r7, #4]
|
|
|
8003bd2: 681b ldr r3, [r3, #0]
|
|
|
8003bd4: 2201 movs r2, #1
|
|
|
8003bd6: 621a str r2, [r3, #32]
|
|
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
|
8003bd8: 687b ldr r3, [r7, #4]
|
|
|
8003bda: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003bde: f043 0201 orr.w r2, r3, #1
|
|
|
8003be2: 687b ldr r3, [r7, #4]
|
|
|
8003be4: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
}
|
|
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
|
8003be8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003bec: f003 0302 and.w r3, r3, #2
|
|
|
8003bf0: 2b00 cmp r3, #0
|
|
|
8003bf2: d011 beq.n 8003c18 <HAL_UART_IRQHandler+0xec>
|
|
|
8003bf4: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
|
|
|
8003bf8: f003 0301 and.w r3, r3, #1
|
|
|
8003bfc: 2b00 cmp r3, #0
|
|
|
8003bfe: d00b beq.n 8003c18 <HAL_UART_IRQHandler+0xec>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
|
8003c00: 687b ldr r3, [r7, #4]
|
|
|
8003c02: 681b ldr r3, [r3, #0]
|
|
|
8003c04: 2202 movs r2, #2
|
|
|
8003c06: 621a str r2, [r3, #32]
|
|
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
|
8003c08: 687b ldr r3, [r7, #4]
|
|
|
8003c0a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003c0e: f043 0204 orr.w r2, r3, #4
|
|
|
8003c12: 687b ldr r3, [r7, #4]
|
|
|
8003c14: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
}
|
|
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
|
8003c18: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003c1c: f003 0304 and.w r3, r3, #4
|
|
|
8003c20: 2b00 cmp r3, #0
|
|
|
8003c22: d011 beq.n 8003c48 <HAL_UART_IRQHandler+0x11c>
|
|
|
8003c24: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
|
|
|
8003c28: f003 0301 and.w r3, r3, #1
|
|
|
8003c2c: 2b00 cmp r3, #0
|
|
|
8003c2e: d00b beq.n 8003c48 <HAL_UART_IRQHandler+0x11c>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
|
8003c30: 687b ldr r3, [r7, #4]
|
|
|
8003c32: 681b ldr r3, [r3, #0]
|
|
|
8003c34: 2204 movs r2, #4
|
|
|
8003c36: 621a str r2, [r3, #32]
|
|
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
|
8003c38: 687b ldr r3, [r7, #4]
|
|
|
8003c3a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003c3e: f043 0202 orr.w r2, r3, #2
|
|
|
8003c42: 687b ldr r3, [r7, #4]
|
|
|
8003c44: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
|
#else
|
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
|
8003c48: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003c4c: f003 0308 and.w r3, r3, #8
|
|
|
8003c50: 2b00 cmp r3, #0
|
|
|
8003c52: d017 beq.n 8003c84 <HAL_UART_IRQHandler+0x158>
|
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
|
8003c54: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
8003c58: f003 0320 and.w r3, r3, #32
|
|
|
8003c5c: 2b00 cmp r3, #0
|
|
|
8003c5e: d105 bne.n 8003c6c <HAL_UART_IRQHandler+0x140>
|
|
|
((cr3its & USART_CR3_EIE) != 0U)))
|
|
|
8003c60: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
|
|
|
8003c64: f003 0301 and.w r3, r3, #1
|
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
|
8003c68: 2b00 cmp r3, #0
|
|
|
8003c6a: d00b beq.n 8003c84 <HAL_UART_IRQHandler+0x158>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
|
8003c6c: 687b ldr r3, [r7, #4]
|
|
|
8003c6e: 681b ldr r3, [r3, #0]
|
|
|
8003c70: 2208 movs r2, #8
|
|
|
8003c72: 621a str r2, [r3, #32]
|
|
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
|
8003c74: 687b ldr r3, [r7, #4]
|
|
|
8003c76: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003c7a: f043 0208 orr.w r2, r3, #8
|
|
|
8003c7e: 687b ldr r3, [r7, #4]
|
|
|
8003c80: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
}
|
|
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
|
8003c84: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003c88: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
|
8003c8c: 2b00 cmp r3, #0
|
|
|
8003c8e: d012 beq.n 8003cb6 <HAL_UART_IRQHandler+0x18a>
|
|
|
8003c90: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
8003c94: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
|
8003c98: 2b00 cmp r3, #0
|
|
|
8003c9a: d00c beq.n 8003cb6 <HAL_UART_IRQHandler+0x18a>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
|
8003c9c: 687b ldr r3, [r7, #4]
|
|
|
8003c9e: 681b ldr r3, [r3, #0]
|
|
|
8003ca0: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
|
8003ca4: 621a str r2, [r3, #32]
|
|
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
|
8003ca6: 687b ldr r3, [r7, #4]
|
|
|
8003ca8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003cac: f043 0220 orr.w r2, r3, #32
|
|
|
8003cb0: 687b ldr r3, [r7, #4]
|
|
|
8003cb2: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
}
|
|
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
|
8003cb6: 687b ldr r3, [r7, #4]
|
|
|
8003cb8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003cbc: 2b00 cmp r3, #0
|
|
|
8003cbe: f000 8214 beq.w 80040ea <HAL_UART_IRQHandler+0x5be>
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
|
#else
|
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
|
8003cc2: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003cc6: f003 0320 and.w r3, r3, #32
|
|
|
8003cca: 2b00 cmp r3, #0
|
|
|
8003ccc: d00d beq.n 8003cea <HAL_UART_IRQHandler+0x1be>
|
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
|
8003cce: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
8003cd2: f003 0320 and.w r3, r3, #32
|
|
|
8003cd6: 2b00 cmp r3, #0
|
|
|
8003cd8: d007 beq.n 8003cea <HAL_UART_IRQHandler+0x1be>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
{
|
|
|
if (huart->RxISR != NULL)
|
|
|
8003cda: 687b ldr r3, [r7, #4]
|
|
|
8003cdc: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
|
8003cde: 2b00 cmp r3, #0
|
|
|
8003ce0: d003 beq.n 8003cea <HAL_UART_IRQHandler+0x1be>
|
|
|
{
|
|
|
huart->RxISR(huart);
|
|
|
8003ce2: 687b ldr r3, [r7, #4]
|
|
|
8003ce4: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
|
8003ce6: 6878 ldr r0, [r7, #4]
|
|
|
8003ce8: 4798 blx r3
|
|
|
/* If Error is to be considered as blocking :
|
|
|
- Receiver Timeout error in Reception
|
|
|
- Overrun error in Reception
|
|
|
- any error occurs in DMA mode reception
|
|
|
*/
|
|
|
errorcode = huart->ErrorCode;
|
|
|
8003cea: 687b ldr r3, [r7, #4]
|
|
|
8003cec: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
|
8003cf0: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
|
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
|
8003cf4: 687b ldr r3, [r7, #4]
|
|
|
8003cf6: 681b ldr r3, [r3, #0]
|
|
|
8003cf8: 689b ldr r3, [r3, #8]
|
|
|
8003cfa: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
8003cfe: 2b40 cmp r3, #64 ; 0x40
|
|
|
8003d00: d005 beq.n 8003d0e <HAL_UART_IRQHandler+0x1e2>
|
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
|
8003d02: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4
|
|
|
8003d06: f003 0328 and.w r3, r3, #40 ; 0x28
|
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
|
8003d0a: 2b00 cmp r3, #0
|
|
|
8003d0c: d04f beq.n 8003dae <HAL_UART_IRQHandler+0x282>
|
|
|
{
|
|
|
/* Blocking error : transfer is aborted
|
|
|
Set the UART state ready to be able to start again the process,
|
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
|
UART_EndRxTransfer(huart);
|
|
|
8003d0e: 6878 ldr r0, [r7, #4]
|
|
|
8003d10: f000 fedc bl 8004acc <UART_EndRxTransfer>
|
|
|
|
|
|
/* Abort the UART DMA Rx channel if enabled */
|
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
|
8003d14: 687b ldr r3, [r7, #4]
|
|
|
8003d16: 681b ldr r3, [r3, #0]
|
|
|
8003d18: 689b ldr r3, [r3, #8]
|
|
|
8003d1a: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
8003d1e: 2b40 cmp r3, #64 ; 0x40
|
|
|
8003d20: d141 bne.n 8003da6 <HAL_UART_IRQHandler+0x27a>
|
|
|
{
|
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
|
8003d22: 687b ldr r3, [r7, #4]
|
|
|
8003d24: 681b ldr r3, [r3, #0]
|
|
|
8003d26: 3308 adds r3, #8
|
|
|
8003d28: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003d2c: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
|
|
|
8003d30: e853 3f00 ldrex r3, [r3]
|
|
|
8003d34: f8c7 3098 str.w r3, [r7, #152] ; 0x98
|
|
|
return(result);
|
|
|
8003d38: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98
|
|
|
8003d3c: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
|
8003d40: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
|
|
|
8003d44: 687b ldr r3, [r7, #4]
|
|
|
8003d46: 681b ldr r3, [r3, #0]
|
|
|
8003d48: 3308 adds r3, #8
|
|
|
8003d4a: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0
|
|
|
8003d4e: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8
|
|
|
8003d52: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003d56: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4
|
|
|
8003d5a: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8
|
|
|
8003d5e: e841 2300 strex r3, r2, [r1]
|
|
|
8003d62: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
|
return(result);
|
|
|
8003d66: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
|
|
|
8003d6a: 2b00 cmp r3, #0
|
|
|
8003d6c: d1d9 bne.n 8003d22 <HAL_UART_IRQHandler+0x1f6>
|
|
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
|
if (huart->hdmarx != NULL)
|
|
|
8003d6e: 687b ldr r3, [r7, #4]
|
|
|
8003d70: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003d72: 2b00 cmp r3, #0
|
|
|
8003d74: d013 beq.n 8003d9e <HAL_UART_IRQHandler+0x272>
|
|
|
{
|
|
|
/* Set the UART DMA Abort callback :
|
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
|
8003d76: 687b ldr r3, [r7, #4]
|
|
|
8003d78: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003d7a: 4a13 ldr r2, [pc, #76] ; (8003dc8 <HAL_UART_IRQHandler+0x29c>)
|
|
|
8003d7c: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
|
|
/* Abort DMA RX */
|
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
|
8003d7e: 687b ldr r3, [r7, #4]
|
|
|
8003d80: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003d82: 4618 mov r0, r3
|
|
|
8003d84: f7fd facf bl 8001326 <HAL_DMA_Abort_IT>
|
|
|
8003d88: 4603 mov r3, r0
|
|
|
8003d8a: 2b00 cmp r3, #0
|
|
|
8003d8c: d017 beq.n 8003dbe <HAL_UART_IRQHandler+0x292>
|
|
|
{
|
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
|
8003d8e: 687b ldr r3, [r7, #4]
|
|
|
8003d90: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003d92: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
|
8003d94: 687a ldr r2, [r7, #4]
|
|
|
8003d96: 6f52 ldr r2, [r2, #116] ; 0x74
|
|
|
8003d98: 4610 mov r0, r2
|
|
|
8003d9a: 4798 blx r3
|
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
|
8003d9c: e00f b.n 8003dbe <HAL_UART_IRQHandler+0x292>
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered error callback*/
|
|
|
huart->ErrorCallback(huart);
|
|
|
#else
|
|
|
/*Call legacy weak error callback*/
|
|
|
HAL_UART_ErrorCallback(huart);
|
|
|
8003d9e: 6878 ldr r0, [r7, #4]
|
|
|
8003da0: f000 f9b8 bl 8004114 <HAL_UART_ErrorCallback>
|
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
|
8003da4: e00b b.n 8003dbe <HAL_UART_IRQHandler+0x292>
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered error callback*/
|
|
|
huart->ErrorCallback(huart);
|
|
|
#else
|
|
|
/*Call legacy weak error callback*/
|
|
|
HAL_UART_ErrorCallback(huart);
|
|
|
8003da6: 6878 ldr r0, [r7, #4]
|
|
|
8003da8: f000 f9b4 bl 8004114 <HAL_UART_ErrorCallback>
|
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
|
8003dac: e007 b.n 8003dbe <HAL_UART_IRQHandler+0x292>
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered error callback*/
|
|
|
huart->ErrorCallback(huart);
|
|
|
#else
|
|
|
/*Call legacy weak error callback*/
|
|
|
HAL_UART_ErrorCallback(huart);
|
|
|
8003dae: 6878 ldr r0, [r7, #4]
|
|
|
8003db0: f000 f9b0 bl 8004114 <HAL_UART_ErrorCallback>
|
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
8003db4: 687b ldr r3, [r7, #4]
|
|
|
8003db6: 2200 movs r2, #0
|
|
|
8003db8: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
}
|
|
|
}
|
|
|
return;
|
|
|
8003dbc: e195 b.n 80040ea <HAL_UART_IRQHandler+0x5be>
|
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
|
8003dbe: bf00 nop
|
|
|
return;
|
|
|
8003dc0: e193 b.n 80040ea <HAL_UART_IRQHandler+0x5be>
|
|
|
8003dc2: bf00 nop
|
|
|
8003dc4: 04000120 .word 0x04000120
|
|
|
8003dc8: 08004b95 .word 0x08004b95
|
|
|
|
|
|
} /* End if some error occurs */
|
|
|
|
|
|
/* Check current reception Mode :
|
|
|
If Reception till IDLE event has been selected : */
|
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
|
8003dcc: 687b ldr r3, [r7, #4]
|
|
|
8003dce: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8003dd0: 2b01 cmp r3, #1
|
|
|
8003dd2: f040 814e bne.w 8004072 <HAL_UART_IRQHandler+0x546>
|
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
|
8003dd6: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8003dda: f003 0310 and.w r3, r3, #16
|
|
|
8003dde: 2b00 cmp r3, #0
|
|
|
8003de0: f000 8147 beq.w 8004072 <HAL_UART_IRQHandler+0x546>
|
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
|
8003de4: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
8003de8: f003 0310 and.w r3, r3, #16
|
|
|
8003dec: 2b00 cmp r3, #0
|
|
|
8003dee: f000 8140 beq.w 8004072 <HAL_UART_IRQHandler+0x546>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
|
8003df2: 687b ldr r3, [r7, #4]
|
|
|
8003df4: 681b ldr r3, [r3, #0]
|
|
|
8003df6: 2210 movs r2, #16
|
|
|
8003df8: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
|
8003dfa: 687b ldr r3, [r7, #4]
|
|
|
8003dfc: 681b ldr r3, [r3, #0]
|
|
|
8003dfe: 689b ldr r3, [r3, #8]
|
|
|
8003e00: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
8003e04: 2b40 cmp r3, #64 ; 0x40
|
|
|
8003e06: f040 80b8 bne.w 8003f7a <HAL_UART_IRQHandler+0x44e>
|
|
|
{
|
|
|
/* DMA mode enabled */
|
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
|
(DMA cplt callback will be called).
|
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
|
8003e0a: 687b ldr r3, [r7, #4]
|
|
|
8003e0c: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003e0e: 681b ldr r3, [r3, #0]
|
|
|
8003e10: 685b ldr r3, [r3, #4]
|
|
|
8003e12: f8a7 30be strh.w r3, [r7, #190] ; 0xbe
|
|
|
if ((nb_remaining_rx_data > 0U)
|
|
|
8003e16: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe
|
|
|
8003e1a: 2b00 cmp r3, #0
|
|
|
8003e1c: f000 8167 beq.w 80040ee <HAL_UART_IRQHandler+0x5c2>
|
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
|
8003e20: 687b ldr r3, [r7, #4]
|
|
|
8003e22: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
|
|
|
8003e26: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
|
|
|
8003e2a: 429a cmp r2, r3
|
|
|
8003e2c: f080 815f bcs.w 80040ee <HAL_UART_IRQHandler+0x5c2>
|
|
|
{
|
|
|
/* Reception is not complete */
|
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
|
8003e30: 687b ldr r3, [r7, #4]
|
|
|
8003e32: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
|
|
|
8003e36: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
|
8003e3a: 687b ldr r3, [r7, #4]
|
|
|
8003e3c: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003e3e: 681b ldr r3, [r3, #0]
|
|
|
8003e40: 681b ldr r3, [r3, #0]
|
|
|
8003e42: f003 0320 and.w r3, r3, #32
|
|
|
8003e46: 2b00 cmp r3, #0
|
|
|
8003e48: f040 8086 bne.w 8003f58 <HAL_UART_IRQHandler+0x42c>
|
|
|
{
|
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
|
8003e4c: 687b ldr r3, [r7, #4]
|
|
|
8003e4e: 681b ldr r3, [r3, #0]
|
|
|
8003e50: f8c7 3088 str.w r3, [r7, #136] ; 0x88
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003e54: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
|
|
|
8003e58: e853 3f00 ldrex r3, [r3]
|
|
|
8003e5c: f8c7 3084 str.w r3, [r7, #132] ; 0x84
|
|
|
return(result);
|
|
|
8003e60: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
|
|
|
8003e64: f423 7380 bic.w r3, r3, #256 ; 0x100
|
|
|
8003e68: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
|
|
|
8003e6c: 687b ldr r3, [r7, #4]
|
|
|
8003e6e: 681b ldr r3, [r3, #0]
|
|
|
8003e70: 461a mov r2, r3
|
|
|
8003e72: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8
|
|
|
8003e76: f8c7 3094 str.w r3, [r7, #148] ; 0x94
|
|
|
8003e7a: f8c7 2090 str.w r2, [r7, #144] ; 0x90
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003e7e: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90
|
|
|
8003e82: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
|
|
|
8003e86: e841 2300 strex r3, r2, [r1]
|
|
|
8003e8a: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|
|
|
return(result);
|
|
|
8003e8e: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
|
|
|
8003e92: 2b00 cmp r3, #0
|
|
|
8003e94: d1da bne.n 8003e4c <HAL_UART_IRQHandler+0x320>
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
8003e96: 687b ldr r3, [r7, #4]
|
|
|
8003e98: 681b ldr r3, [r3, #0]
|
|
|
8003e9a: 3308 adds r3, #8
|
|
|
8003e9c: 677b str r3, [r7, #116] ; 0x74
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003e9e: 6f7b ldr r3, [r7, #116] ; 0x74
|
|
|
8003ea0: e853 3f00 ldrex r3, [r3]
|
|
|
8003ea4: 673b str r3, [r7, #112] ; 0x70
|
|
|
return(result);
|
|
|
8003ea6: 6f3b ldr r3, [r7, #112] ; 0x70
|
|
|
8003ea8: f023 0301 bic.w r3, r3, #1
|
|
|
8003eac: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
|
8003eb0: 687b ldr r3, [r7, #4]
|
|
|
8003eb2: 681b ldr r3, [r3, #0]
|
|
|
8003eb4: 3308 adds r3, #8
|
|
|
8003eb6: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4
|
|
|
8003eba: f8c7 2080 str.w r2, [r7, #128] ; 0x80
|
|
|
8003ebe: 67fb str r3, [r7, #124] ; 0x7c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003ec0: 6ff9 ldr r1, [r7, #124] ; 0x7c
|
|
|
8003ec2: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80
|
|
|
8003ec6: e841 2300 strex r3, r2, [r1]
|
|
|
8003eca: 67bb str r3, [r7, #120] ; 0x78
|
|
|
return(result);
|
|
|
8003ecc: 6fbb ldr r3, [r7, #120] ; 0x78
|
|
|
8003ece: 2b00 cmp r3, #0
|
|
|
8003ed0: d1e1 bne.n 8003e96 <HAL_UART_IRQHandler+0x36a>
|
|
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
|
in the UART CR3 register */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
|
8003ed2: 687b ldr r3, [r7, #4]
|
|
|
8003ed4: 681b ldr r3, [r3, #0]
|
|
|
8003ed6: 3308 adds r3, #8
|
|
|
8003ed8: 663b str r3, [r7, #96] ; 0x60
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003eda: 6e3b ldr r3, [r7, #96] ; 0x60
|
|
|
8003edc: e853 3f00 ldrex r3, [r3]
|
|
|
8003ee0: 65fb str r3, [r7, #92] ; 0x5c
|
|
|
return(result);
|
|
|
8003ee2: 6dfb ldr r3, [r7, #92] ; 0x5c
|
|
|
8003ee4: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
|
8003ee8: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
|
|
|
8003eec: 687b ldr r3, [r7, #4]
|
|
|
8003eee: 681b ldr r3, [r3, #0]
|
|
|
8003ef0: 3308 adds r3, #8
|
|
|
8003ef2: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0
|
|
|
8003ef6: 66fa str r2, [r7, #108] ; 0x6c
|
|
|
8003ef8: 66bb str r3, [r7, #104] ; 0x68
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003efa: 6eb9 ldr r1, [r7, #104] ; 0x68
|
|
|
8003efc: 6efa ldr r2, [r7, #108] ; 0x6c
|
|
|
8003efe: e841 2300 strex r3, r2, [r1]
|
|
|
8003f02: 667b str r3, [r7, #100] ; 0x64
|
|
|
return(result);
|
|
|
8003f04: 6e7b ldr r3, [r7, #100] ; 0x64
|
|
|
8003f06: 2b00 cmp r3, #0
|
|
|
8003f08: d1e3 bne.n 8003ed2 <HAL_UART_IRQHandler+0x3a6>
|
|
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8003f0a: 687b ldr r3, [r7, #4]
|
|
|
8003f0c: 2220 movs r2, #32
|
|
|
8003f0e: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
8003f12: 687b ldr r3, [r7, #4]
|
|
|
8003f14: 2200 movs r2, #0
|
|
|
8003f16: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
|
8003f18: 687b ldr r3, [r7, #4]
|
|
|
8003f1a: 681b ldr r3, [r3, #0]
|
|
|
8003f1c: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003f1e: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
|
8003f20: e853 3f00 ldrex r3, [r3]
|
|
|
8003f24: 64bb str r3, [r7, #72] ; 0x48
|
|
|
return(result);
|
|
|
8003f26: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
|
8003f28: f023 0310 bic.w r3, r3, #16
|
|
|
8003f2c: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
|
8003f30: 687b ldr r3, [r7, #4]
|
|
|
8003f32: 681b ldr r3, [r3, #0]
|
|
|
8003f34: 461a mov r2, r3
|
|
|
8003f36: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
|
|
|
8003f3a: 65bb str r3, [r7, #88] ; 0x58
|
|
|
8003f3c: 657a str r2, [r7, #84] ; 0x54
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003f3e: 6d79 ldr r1, [r7, #84] ; 0x54
|
|
|
8003f40: 6dba ldr r2, [r7, #88] ; 0x58
|
|
|
8003f42: e841 2300 strex r3, r2, [r1]
|
|
|
8003f46: 653b str r3, [r7, #80] ; 0x50
|
|
|
return(result);
|
|
|
8003f48: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
|
8003f4a: 2b00 cmp r3, #0
|
|
|
8003f4c: d1e4 bne.n 8003f18 <HAL_UART_IRQHandler+0x3ec>
|
|
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
|
8003f4e: 687b ldr r3, [r7, #4]
|
|
|
8003f50: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
|
8003f52: 4618 mov r0, r3
|
|
|
8003f54: f7fd f9a9 bl 80012aa <HAL_DMA_Abort>
|
|
|
}
|
|
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
|
In this case, Rx Event type is Idle Event */
|
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
|
8003f58: 687b ldr r3, [r7, #4]
|
|
|
8003f5a: 2202 movs r2, #2
|
|
|
8003f5c: 665a str r2, [r3, #100] ; 0x64
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered Rx Event callback*/
|
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
|
#else
|
|
|
/*Call legacy weak Rx Event callback*/
|
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
|
8003f5e: 687b ldr r3, [r7, #4]
|
|
|
8003f60: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
|
|
|
8003f64: 687b ldr r3, [r7, #4]
|
|
|
8003f66: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8003f6a: b29b uxth r3, r3
|
|
|
8003f6c: 1ad3 subs r3, r2, r3
|
|
|
8003f6e: b29b uxth r3, r3
|
|
|
8003f70: 4619 mov r1, r3
|
|
|
8003f72: 6878 ldr r0, [r7, #4]
|
|
|
8003f74: f7fc fb6c bl 8000650 <HAL_UARTEx_RxEventCallback>
|
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
|
}
|
|
|
return;
|
|
|
8003f78: e0b9 b.n 80040ee <HAL_UART_IRQHandler+0x5c2>
|
|
|
else
|
|
|
{
|
|
|
/* DMA mode not enabled */
|
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
|
8003f7a: 687b ldr r3, [r7, #4]
|
|
|
8003f7c: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
|
|
|
8003f80: 687b ldr r3, [r7, #4]
|
|
|
8003f82: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8003f86: b29b uxth r3, r3
|
|
|
8003f88: 1ad3 subs r3, r2, r3
|
|
|
8003f8a: f8a7 30ce strh.w r3, [r7, #206] ; 0xce
|
|
|
if ((huart->RxXferCount > 0U)
|
|
|
8003f8e: 687b ldr r3, [r7, #4]
|
|
|
8003f90: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8003f94: b29b uxth r3, r3
|
|
|
8003f96: 2b00 cmp r3, #0
|
|
|
8003f98: f000 80ab beq.w 80040f2 <HAL_UART_IRQHandler+0x5c6>
|
|
|
&& (nb_rx_data > 0U))
|
|
|
8003f9c: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
|
|
|
8003fa0: 2b00 cmp r3, #0
|
|
|
8003fa2: f000 80a6 beq.w 80040f2 <HAL_UART_IRQHandler+0x5c6>
|
|
|
|
|
|
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
|
#else
|
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
|
8003fa6: 687b ldr r3, [r7, #4]
|
|
|
8003fa8: 681b ldr r3, [r3, #0]
|
|
|
8003faa: 63bb str r3, [r7, #56] ; 0x38
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003fac: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8003fae: e853 3f00 ldrex r3, [r3]
|
|
|
8003fb2: 637b str r3, [r7, #52] ; 0x34
|
|
|
return(result);
|
|
|
8003fb4: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
8003fb6: f423 7390 bic.w r3, r3, #288 ; 0x120
|
|
|
8003fba: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
|
|
|
8003fbe: 687b ldr r3, [r7, #4]
|
|
|
8003fc0: 681b ldr r3, [r3, #0]
|
|
|
8003fc2: 461a mov r2, r3
|
|
|
8003fc4: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8
|
|
|
8003fc8: 647b str r3, [r7, #68] ; 0x44
|
|
|
8003fca: 643a str r2, [r7, #64] ; 0x40
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8003fcc: 6c39 ldr r1, [r7, #64] ; 0x40
|
|
|
8003fce: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
|
8003fd0: e841 2300 strex r3, r2, [r1]
|
|
|
8003fd4: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
return(result);
|
|
|
8003fd6: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
|
8003fd8: 2b00 cmp r3, #0
|
|
|
8003fda: d1e4 bne.n 8003fa6 <HAL_UART_IRQHandler+0x47a>
|
|
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
8003fdc: 687b ldr r3, [r7, #4]
|
|
|
8003fde: 681b ldr r3, [r3, #0]
|
|
|
8003fe0: 3308 adds r3, #8
|
|
|
8003fe2: 627b str r3, [r7, #36] ; 0x24
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8003fe4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8003fe6: e853 3f00 ldrex r3, [r3]
|
|
|
8003fea: 623b str r3, [r7, #32]
|
|
|
return(result);
|
|
|
8003fec: 6a3b ldr r3, [r7, #32]
|
|
|
8003fee: f023 0301 bic.w r3, r3, #1
|
|
|
8003ff2: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
|
|
|
8003ff6: 687b ldr r3, [r7, #4]
|
|
|
8003ff8: 681b ldr r3, [r3, #0]
|
|
|
8003ffa: 3308 adds r3, #8
|
|
|
8003ffc: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4
|
|
|
8004000: 633a str r2, [r7, #48] ; 0x30
|
|
|
8004002: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004004: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
|
8004006: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
|
8004008: e841 2300 strex r3, r2, [r1]
|
|
|
800400c: 62bb str r3, [r7, #40] ; 0x28
|
|
|
return(result);
|
|
|
800400e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
8004010: 2b00 cmp r3, #0
|
|
|
8004012: d1e3 bne.n 8003fdc <HAL_UART_IRQHandler+0x4b0>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8004014: 687b ldr r3, [r7, #4]
|
|
|
8004016: 2220 movs r2, #32
|
|
|
8004018: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
800401c: 687b ldr r3, [r7, #4]
|
|
|
800401e: 2200 movs r2, #0
|
|
|
8004020: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
|
|
/* Clear RxISR function pointer */
|
|
|
huart->RxISR = NULL;
|
|
|
8004022: 687b ldr r3, [r7, #4]
|
|
|
8004024: 2200 movs r2, #0
|
|
|
8004026: 669a str r2, [r3, #104] ; 0x68
|
|
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
|
8004028: 687b ldr r3, [r7, #4]
|
|
|
800402a: 681b ldr r3, [r3, #0]
|
|
|
800402c: 613b str r3, [r7, #16]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
800402e: 693b ldr r3, [r7, #16]
|
|
|
8004030: e853 3f00 ldrex r3, [r3]
|
|
|
8004034: 60fb str r3, [r7, #12]
|
|
|
return(result);
|
|
|
8004036: 68fb ldr r3, [r7, #12]
|
|
|
8004038: f023 0310 bic.w r3, r3, #16
|
|
|
800403c: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
|
|
|
8004040: 687b ldr r3, [r7, #4]
|
|
|
8004042: 681b ldr r3, [r3, #0]
|
|
|
8004044: 461a mov r2, r3
|
|
|
8004046: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
|
|
|
800404a: 61fb str r3, [r7, #28]
|
|
|
800404c: 61ba str r2, [r7, #24]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
800404e: 69b9 ldr r1, [r7, #24]
|
|
|
8004050: 69fa ldr r2, [r7, #28]
|
|
|
8004052: e841 2300 strex r3, r2, [r1]
|
|
|
8004056: 617b str r3, [r7, #20]
|
|
|
return(result);
|
|
|
8004058: 697b ldr r3, [r7, #20]
|
|
|
800405a: 2b00 cmp r3, #0
|
|
|
800405c: d1e4 bne.n 8004028 <HAL_UART_IRQHandler+0x4fc>
|
|
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
|
In this case, Rx Event type is Idle Event */
|
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
|
800405e: 687b ldr r3, [r7, #4]
|
|
|
8004060: 2202 movs r2, #2
|
|
|
8004062: 665a str r2, [r3, #100] ; 0x64
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered Rx complete callback*/
|
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
|
#else
|
|
|
/*Call legacy weak Rx Event callback*/
|
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
|
8004064: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
|
|
|
8004068: 4619 mov r1, r3
|
|
|
800406a: 6878 ldr r0, [r7, #4]
|
|
|
800406c: f7fc faf0 bl 8000650 <HAL_UARTEx_RxEventCallback>
|
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
|
}
|
|
|
return;
|
|
|
8004070: e03f b.n 80040f2 <HAL_UART_IRQHandler+0x5c6>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
|
8004072: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
8004076: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
|
800407a: 2b00 cmp r3, #0
|
|
|
800407c: d00e beq.n 800409c <HAL_UART_IRQHandler+0x570>
|
|
|
800407e: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
|
|
|
8004082: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
|
8004086: 2b00 cmp r3, #0
|
|
|
8004088: d008 beq.n 800409c <HAL_UART_IRQHandler+0x570>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
|
800408a: 687b ldr r3, [r7, #4]
|
|
|
800408c: 681b ldr r3, [r3, #0]
|
|
|
800408e: f44f 1280 mov.w r2, #1048576 ; 0x100000
|
|
|
8004092: 621a str r2, [r3, #32]
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/* Call registered Wakeup Callback */
|
|
|
huart->WakeupCallback(huart);
|
|
|
#else
|
|
|
/* Call legacy weak Wakeup Callback */
|
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
|
8004094: 6878 ldr r0, [r7, #4]
|
|
|
8004096: f001 f835 bl 8005104 <HAL_UARTEx_WakeupCallback>
|
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
return;
|
|
|
800409a: e02d b.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
|
#else
|
|
|
if (((isrflags & USART_ISR_TXE) != 0U)
|
|
|
800409c: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
80040a0: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
|
80040a4: 2b00 cmp r3, #0
|
|
|
80040a6: d00e beq.n 80040c6 <HAL_UART_IRQHandler+0x59a>
|
|
|
&& ((cr1its & USART_CR1_TXEIE) != 0U))
|
|
|
80040a8: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
80040ac: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
|
80040b0: 2b00 cmp r3, #0
|
|
|
80040b2: d008 beq.n 80040c6 <HAL_UART_IRQHandler+0x59a>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
{
|
|
|
if (huart->TxISR != NULL)
|
|
|
80040b4: 687b ldr r3, [r7, #4]
|
|
|
80040b6: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
|
80040b8: 2b00 cmp r3, #0
|
|
|
80040ba: d01c beq.n 80040f6 <HAL_UART_IRQHandler+0x5ca>
|
|
|
{
|
|
|
huart->TxISR(huart);
|
|
|
80040bc: 687b ldr r3, [r7, #4]
|
|
|
80040be: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
|
80040c0: 6878 ldr r0, [r7, #4]
|
|
|
80040c2: 4798 blx r3
|
|
|
}
|
|
|
return;
|
|
|
80040c4: e017 b.n 80040f6 <HAL_UART_IRQHandler+0x5ca>
|
|
|
}
|
|
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
|
80040c6: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
|
|
|
80040ca: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
80040ce: 2b00 cmp r3, #0
|
|
|
80040d0: d012 beq.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
80040d2: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
|
|
|
80040d6: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
80040da: 2b00 cmp r3, #0
|
|
|
80040dc: d00c beq.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
{
|
|
|
UART_EndTransmit_IT(huart);
|
|
|
80040de: 6878 ldr r0, [r7, #4]
|
|
|
80040e0: f000 fe2a bl 8004d38 <UART_EndTransmit_IT>
|
|
|
return;
|
|
|
80040e4: e008 b.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
return;
|
|
|
80040e6: bf00 nop
|
|
|
80040e8: e006 b.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
return;
|
|
|
80040ea: bf00 nop
|
|
|
80040ec: e004 b.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
return;
|
|
|
80040ee: bf00 nop
|
|
|
80040f0: e002 b.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
return;
|
|
|
80040f2: bf00 nop
|
|
|
80040f4: e000 b.n 80040f8 <HAL_UART_IRQHandler+0x5cc>
|
|
|
return;
|
|
|
80040f6: bf00 nop
|
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
return;
|
|
|
}
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
}
|
|
|
80040f8: 37e8 adds r7, #232 ; 0xe8
|
|
|
80040fa: 46bd mov sp, r7
|
|
|
80040fc: bd80 pop {r7, pc}
|
|
|
80040fe: bf00 nop
|
|
|
|
|
|
08004100 <HAL_UART_TxCpltCallback>:
|
|
|
* @brief Tx Transfer completed callback.
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004100: b480 push {r7}
|
|
|
8004102: b083 sub sp, #12
|
|
|
8004104: af00 add r7, sp, #0
|
|
|
8004106: 6078 str r0, [r7, #4]
|
|
|
UNUSED(huart);
|
|
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
|
the HAL_UART_TxCpltCallback can be implemented in the user file.
|
|
|
*/
|
|
|
}
|
|
|
8004108: bf00 nop
|
|
|
800410a: 370c adds r7, #12
|
|
|
800410c: 46bd mov sp, r7
|
|
|
800410e: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8004112: 4770 bx lr
|
|
|
|
|
|
08004114 <HAL_UART_ErrorCallback>:
|
|
|
* @brief UART error callback.
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004114: b480 push {r7}
|
|
|
8004116: b083 sub sp, #12
|
|
|
8004118: af00 add r7, sp, #0
|
|
|
800411a: 6078 str r0, [r7, #4]
|
|
|
UNUSED(huart);
|
|
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
|
*/
|
|
|
}
|
|
|
800411c: bf00 nop
|
|
|
800411e: 370c adds r7, #12
|
|
|
8004120: 46bd mov sp, r7
|
|
|
8004122: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8004126: 4770 bx lr
|
|
|
|
|
|
08004128 <UART_SetConfig>:
|
|
|
* @brief Configure the UART peripheral.
|
|
|
* @param huart UART handle.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004128: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
|
800412c: b08a sub sp, #40 ; 0x28
|
|
|
800412e: af00 add r7, sp, #0
|
|
|
8004130: 60f8 str r0, [r7, #12]
|
|
|
uint32_t tmpreg;
|
|
|
uint16_t brrtemp;
|
|
|
UART_ClockSourceTypeDef clocksource;
|
|
|
uint32_t usartdiv;
|
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
|
8004132: 2300 movs r3, #0
|
|
|
8004134: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
|
* set the M bits according to huart->Init.WordLength value
|
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
|
8004138: 68fb ldr r3, [r7, #12]
|
|
|
800413a: 689a ldr r2, [r3, #8]
|
|
|
800413c: 68fb ldr r3, [r7, #12]
|
|
|
800413e: 691b ldr r3, [r3, #16]
|
|
|
8004140: 431a orrs r2, r3
|
|
|
8004142: 68fb ldr r3, [r7, #12]
|
|
|
8004144: 695b ldr r3, [r3, #20]
|
|
|
8004146: 431a orrs r2, r3
|
|
|
8004148: 68fb ldr r3, [r7, #12]
|
|
|
800414a: 69db ldr r3, [r3, #28]
|
|
|
800414c: 4313 orrs r3, r2
|
|
|
800414e: 627b str r3, [r7, #36] ; 0x24
|
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
|
8004150: 68fb ldr r3, [r7, #12]
|
|
|
8004152: 681b ldr r3, [r3, #0]
|
|
|
8004154: 681a ldr r2, [r3, #0]
|
|
|
8004156: 4b9e ldr r3, [pc, #632] ; (80043d0 <UART_SetConfig+0x2a8>)
|
|
|
8004158: 4013 ands r3, r2
|
|
|
800415a: 68fa ldr r2, [r7, #12]
|
|
|
800415c: 6812 ldr r2, [r2, #0]
|
|
|
800415e: 6a79 ldr r1, [r7, #36] ; 0x24
|
|
|
8004160: 430b orrs r3, r1
|
|
|
8004162: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
|
* to huart->Init.StopBits value */
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
|
8004164: 68fb ldr r3, [r7, #12]
|
|
|
8004166: 681b ldr r3, [r3, #0]
|
|
|
8004168: 685b ldr r3, [r3, #4]
|
|
|
800416a: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
|
|
800416e: 68fb ldr r3, [r7, #12]
|
|
|
8004170: 68da ldr r2, [r3, #12]
|
|
|
8004172: 68fb ldr r3, [r7, #12]
|
|
|
8004174: 681b ldr r3, [r3, #0]
|
|
|
8004176: 430a orrs r2, r1
|
|
|
8004178: 605a str r2, [r3, #4]
|
|
|
/* Configure
|
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
|
* to huart->Init.HwFlowCtl value
|
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
|
800417a: 68fb ldr r3, [r7, #12]
|
|
|
800417c: 699b ldr r3, [r3, #24]
|
|
|
800417e: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
|
8004180: 68fb ldr r3, [r7, #12]
|
|
|
8004182: 681b ldr r3, [r3, #0]
|
|
|
8004184: 4a93 ldr r2, [pc, #588] ; (80043d4 <UART_SetConfig+0x2ac>)
|
|
|
8004186: 4293 cmp r3, r2
|
|
|
8004188: d004 beq.n 8004194 <UART_SetConfig+0x6c>
|
|
|
{
|
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
|
800418a: 68fb ldr r3, [r7, #12]
|
|
|
800418c: 6a1b ldr r3, [r3, #32]
|
|
|
800418e: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
|
8004190: 4313 orrs r3, r2
|
|
|
8004192: 627b str r3, [r7, #36] ; 0x24
|
|
|
}
|
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
|
8004194: 68fb ldr r3, [r7, #12]
|
|
|
8004196: 681b ldr r3, [r3, #0]
|
|
|
8004198: 689b ldr r3, [r3, #8]
|
|
|
800419a: f423 6130 bic.w r1, r3, #2816 ; 0xb00
|
|
|
800419e: 68fb ldr r3, [r7, #12]
|
|
|
80041a0: 681b ldr r3, [r3, #0]
|
|
|
80041a2: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
|
80041a4: 430a orrs r2, r1
|
|
|
80041a6: 609a str r2, [r3, #8]
|
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
|
80041a8: 68fb ldr r3, [r7, #12]
|
|
|
80041aa: 681b ldr r3, [r3, #0]
|
|
|
80041ac: 4a8a ldr r2, [pc, #552] ; (80043d8 <UART_SetConfig+0x2b0>)
|
|
|
80041ae: 4293 cmp r3, r2
|
|
|
80041b0: d126 bne.n 8004200 <UART_SetConfig+0xd8>
|
|
|
80041b2: 4b8a ldr r3, [pc, #552] ; (80043dc <UART_SetConfig+0x2b4>)
|
|
|
80041b4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80041b8: f003 0303 and.w r3, r3, #3
|
|
|
80041bc: 2b03 cmp r3, #3
|
|
|
80041be: d81b bhi.n 80041f8 <UART_SetConfig+0xd0>
|
|
|
80041c0: a201 add r2, pc, #4 ; (adr r2, 80041c8 <UART_SetConfig+0xa0>)
|
|
|
80041c2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
80041c6: bf00 nop
|
|
|
80041c8: 080041d9 .word 0x080041d9
|
|
|
80041cc: 080041e9 .word 0x080041e9
|
|
|
80041d0: 080041e1 .word 0x080041e1
|
|
|
80041d4: 080041f1 .word 0x080041f1
|
|
|
80041d8: 2301 movs r3, #1
|
|
|
80041da: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80041de: e0ab b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80041e0: 2302 movs r3, #2
|
|
|
80041e2: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80041e6: e0a7 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80041e8: 2304 movs r3, #4
|
|
|
80041ea: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80041ee: e0a3 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80041f0: 2308 movs r3, #8
|
|
|
80041f2: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80041f6: e09f b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80041f8: 2310 movs r3, #16
|
|
|
80041fa: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80041fe: e09b b.n 8004338 <UART_SetConfig+0x210>
|
|
|
8004200: 68fb ldr r3, [r7, #12]
|
|
|
8004202: 681b ldr r3, [r3, #0]
|
|
|
8004204: 4a76 ldr r2, [pc, #472] ; (80043e0 <UART_SetConfig+0x2b8>)
|
|
|
8004206: 4293 cmp r3, r2
|
|
|
8004208: d138 bne.n 800427c <UART_SetConfig+0x154>
|
|
|
800420a: 4b74 ldr r3, [pc, #464] ; (80043dc <UART_SetConfig+0x2b4>)
|
|
|
800420c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
8004210: f003 030c and.w r3, r3, #12
|
|
|
8004214: 2b0c cmp r3, #12
|
|
|
8004216: d82d bhi.n 8004274 <UART_SetConfig+0x14c>
|
|
|
8004218: a201 add r2, pc, #4 ; (adr r2, 8004220 <UART_SetConfig+0xf8>)
|
|
|
800421a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
800421e: bf00 nop
|
|
|
8004220: 08004255 .word 0x08004255
|
|
|
8004224: 08004275 .word 0x08004275
|
|
|
8004228: 08004275 .word 0x08004275
|
|
|
800422c: 08004275 .word 0x08004275
|
|
|
8004230: 08004265 .word 0x08004265
|
|
|
8004234: 08004275 .word 0x08004275
|
|
|
8004238: 08004275 .word 0x08004275
|
|
|
800423c: 08004275 .word 0x08004275
|
|
|
8004240: 0800425d .word 0x0800425d
|
|
|
8004244: 08004275 .word 0x08004275
|
|
|
8004248: 08004275 .word 0x08004275
|
|
|
800424c: 08004275 .word 0x08004275
|
|
|
8004250: 0800426d .word 0x0800426d
|
|
|
8004254: 2300 movs r3, #0
|
|
|
8004256: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
800425a: e06d b.n 8004338 <UART_SetConfig+0x210>
|
|
|
800425c: 2302 movs r3, #2
|
|
|
800425e: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004262: e069 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
8004264: 2304 movs r3, #4
|
|
|
8004266: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
800426a: e065 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
800426c: 2308 movs r3, #8
|
|
|
800426e: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004272: e061 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
8004274: 2310 movs r3, #16
|
|
|
8004276: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
800427a: e05d b.n 8004338 <UART_SetConfig+0x210>
|
|
|
800427c: 68fb ldr r3, [r7, #12]
|
|
|
800427e: 681b ldr r3, [r3, #0]
|
|
|
8004280: 4a58 ldr r2, [pc, #352] ; (80043e4 <UART_SetConfig+0x2bc>)
|
|
|
8004282: 4293 cmp r3, r2
|
|
|
8004284: d125 bne.n 80042d2 <UART_SetConfig+0x1aa>
|
|
|
8004286: 4b55 ldr r3, [pc, #340] ; (80043dc <UART_SetConfig+0x2b4>)
|
|
|
8004288: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
800428c: f003 0330 and.w r3, r3, #48 ; 0x30
|
|
|
8004290: 2b30 cmp r3, #48 ; 0x30
|
|
|
8004292: d016 beq.n 80042c2 <UART_SetConfig+0x19a>
|
|
|
8004294: 2b30 cmp r3, #48 ; 0x30
|
|
|
8004296: d818 bhi.n 80042ca <UART_SetConfig+0x1a2>
|
|
|
8004298: 2b20 cmp r3, #32
|
|
|
800429a: d00a beq.n 80042b2 <UART_SetConfig+0x18a>
|
|
|
800429c: 2b20 cmp r3, #32
|
|
|
800429e: d814 bhi.n 80042ca <UART_SetConfig+0x1a2>
|
|
|
80042a0: 2b00 cmp r3, #0
|
|
|
80042a2: d002 beq.n 80042aa <UART_SetConfig+0x182>
|
|
|
80042a4: 2b10 cmp r3, #16
|
|
|
80042a6: d008 beq.n 80042ba <UART_SetConfig+0x192>
|
|
|
80042a8: e00f b.n 80042ca <UART_SetConfig+0x1a2>
|
|
|
80042aa: 2300 movs r3, #0
|
|
|
80042ac: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80042b0: e042 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80042b2: 2302 movs r3, #2
|
|
|
80042b4: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80042b8: e03e b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80042ba: 2304 movs r3, #4
|
|
|
80042bc: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80042c0: e03a b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80042c2: 2308 movs r3, #8
|
|
|
80042c4: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80042c8: e036 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80042ca: 2310 movs r3, #16
|
|
|
80042cc: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
80042d0: e032 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
80042d2: 68fb ldr r3, [r7, #12]
|
|
|
80042d4: 681b ldr r3, [r3, #0]
|
|
|
80042d6: 4a3f ldr r2, [pc, #252] ; (80043d4 <UART_SetConfig+0x2ac>)
|
|
|
80042d8: 4293 cmp r3, r2
|
|
|
80042da: d12a bne.n 8004332 <UART_SetConfig+0x20a>
|
|
|
80042dc: 4b3f ldr r3, [pc, #252] ; (80043dc <UART_SetConfig+0x2b4>)
|
|
|
80042de: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
|
80042e2: f403 6340 and.w r3, r3, #3072 ; 0xc00
|
|
|
80042e6: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
|
|
80042ea: d01a beq.n 8004322 <UART_SetConfig+0x1fa>
|
|
|
80042ec: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
|
|
80042f0: d81b bhi.n 800432a <UART_SetConfig+0x202>
|
|
|
80042f2: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
|
80042f6: d00c beq.n 8004312 <UART_SetConfig+0x1ea>
|
|
|
80042f8: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
|
80042fc: d815 bhi.n 800432a <UART_SetConfig+0x202>
|
|
|
80042fe: 2b00 cmp r3, #0
|
|
|
8004300: d003 beq.n 800430a <UART_SetConfig+0x1e2>
|
|
|
8004302: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
|
8004306: d008 beq.n 800431a <UART_SetConfig+0x1f2>
|
|
|
8004308: e00f b.n 800432a <UART_SetConfig+0x202>
|
|
|
800430a: 2300 movs r3, #0
|
|
|
800430c: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004310: e012 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
8004312: 2302 movs r3, #2
|
|
|
8004314: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004318: e00e b.n 8004338 <UART_SetConfig+0x210>
|
|
|
800431a: 2304 movs r3, #4
|
|
|
800431c: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004320: e00a b.n 8004338 <UART_SetConfig+0x210>
|
|
|
8004322: 2308 movs r3, #8
|
|
|
8004324: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004328: e006 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
800432a: 2310 movs r3, #16
|
|
|
800432c: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
8004330: e002 b.n 8004338 <UART_SetConfig+0x210>
|
|
|
8004332: 2310 movs r3, #16
|
|
|
8004334: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
|
|
|
|
/* Check LPUART instance */
|
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
|
8004338: 68fb ldr r3, [r7, #12]
|
|
|
800433a: 681b ldr r3, [r3, #0]
|
|
|
800433c: 4a25 ldr r2, [pc, #148] ; (80043d4 <UART_SetConfig+0x2ac>)
|
|
|
800433e: 4293 cmp r3, r2
|
|
|
8004340: f040 808a bne.w 8004458 <UART_SetConfig+0x330>
|
|
|
{
|
|
|
/* Retrieve frequency clock */
|
|
|
switch (clocksource)
|
|
|
8004344: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
|
|
8004348: 2b08 cmp r3, #8
|
|
|
800434a: d824 bhi.n 8004396 <UART_SetConfig+0x26e>
|
|
|
800434c: a201 add r2, pc, #4 ; (adr r2, 8004354 <UART_SetConfig+0x22c>)
|
|
|
800434e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
8004352: bf00 nop
|
|
|
8004354: 08004379 .word 0x08004379
|
|
|
8004358: 08004397 .word 0x08004397
|
|
|
800435c: 08004381 .word 0x08004381
|
|
|
8004360: 08004397 .word 0x08004397
|
|
|
8004364: 08004387 .word 0x08004387
|
|
|
8004368: 08004397 .word 0x08004397
|
|
|
800436c: 08004397 .word 0x08004397
|
|
|
8004370: 08004397 .word 0x08004397
|
|
|
8004374: 0800438f .word 0x0800438f
|
|
|
{
|
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
|
8004378: f7fd ffd0 bl 800231c <HAL_RCC_GetPCLK1Freq>
|
|
|
800437c: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
800437e: e010 b.n 80043a2 <UART_SetConfig+0x27a>
|
|
|
case UART_CLOCKSOURCE_HSI:
|
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
|
8004380: 4b19 ldr r3, [pc, #100] ; (80043e8 <UART_SetConfig+0x2c0>)
|
|
|
8004382: 61fb str r3, [r7, #28]
|
|
|
break;
|
|
|
8004384: e00d b.n 80043a2 <UART_SetConfig+0x27a>
|
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
|
8004386: f7fd ff31 bl 80021ec <HAL_RCC_GetSysClockFreq>
|
|
|
800438a: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
800438c: e009 b.n 80043a2 <UART_SetConfig+0x27a>
|
|
|
case UART_CLOCKSOURCE_LSE:
|
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
|
800438e: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
|
8004392: 61fb str r3, [r7, #28]
|
|
|
break;
|
|
|
8004394: e005 b.n 80043a2 <UART_SetConfig+0x27a>
|
|
|
default:
|
|
|
pclk = 0U;
|
|
|
8004396: 2300 movs r3, #0
|
|
|
8004398: 61fb str r3, [r7, #28]
|
|
|
ret = HAL_ERROR;
|
|
|
800439a: 2301 movs r3, #1
|
|
|
800439c: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
break;
|
|
|
80043a0: bf00 nop
|
|
|
}
|
|
|
|
|
|
/* If proper clock source reported */
|
|
|
if (pclk != 0U)
|
|
|
80043a2: 69fb ldr r3, [r7, #28]
|
|
|
80043a4: 2b00 cmp r3, #0
|
|
|
80043a6: f000 8109 beq.w 80045bc <UART_SetConfig+0x494>
|
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
|
#else
|
|
|
/* No Prescaler applicable */
|
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
|
80043aa: 68fb ldr r3, [r7, #12]
|
|
|
80043ac: 685a ldr r2, [r3, #4]
|
|
|
80043ae: 4613 mov r3, r2
|
|
|
80043b0: 005b lsls r3, r3, #1
|
|
|
80043b2: 4413 add r3, r2
|
|
|
80043b4: 69fa ldr r2, [r7, #28]
|
|
|
80043b6: 429a cmp r2, r3
|
|
|
80043b8: d305 bcc.n 80043c6 <UART_SetConfig+0x29e>
|
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|
|
80043ba: 68fb ldr r3, [r7, #12]
|
|
|
80043bc: 685b ldr r3, [r3, #4]
|
|
|
80043be: 031b lsls r3, r3, #12
|
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
|
80043c0: 69fa ldr r2, [r7, #28]
|
|
|
80043c2: 429a cmp r2, r3
|
|
|
80043c4: d912 bls.n 80043ec <UART_SetConfig+0x2c4>
|
|
|
{
|
|
|
ret = HAL_ERROR;
|
|
|
80043c6: 2301 movs r3, #1
|
|
|
80043c8: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
80043cc: e0f6 b.n 80045bc <UART_SetConfig+0x494>
|
|
|
80043ce: bf00 nop
|
|
|
80043d0: efff69f3 .word 0xefff69f3
|
|
|
80043d4: 40008000 .word 0x40008000
|
|
|
80043d8: 40013800 .word 0x40013800
|
|
|
80043dc: 40021000 .word 0x40021000
|
|
|
80043e0: 40004400 .word 0x40004400
|
|
|
80043e4: 40004800 .word 0x40004800
|
|
|
80043e8: 00f42400 .word 0x00f42400
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|
|
80043ec: 69fb ldr r3, [r7, #28]
|
|
|
80043ee: 2200 movs r2, #0
|
|
|
80043f0: 461c mov r4, r3
|
|
|
80043f2: 4615 mov r5, r2
|
|
|
80043f4: f04f 0200 mov.w r2, #0
|
|
|
80043f8: f04f 0300 mov.w r3, #0
|
|
|
80043fc: 022b lsls r3, r5, #8
|
|
|
80043fe: ea43 6314 orr.w r3, r3, r4, lsr #24
|
|
|
8004402: 0222 lsls r2, r4, #8
|
|
|
8004404: 68f9 ldr r1, [r7, #12]
|
|
|
8004406: 6849 ldr r1, [r1, #4]
|
|
|
8004408: 0849 lsrs r1, r1, #1
|
|
|
800440a: 2000 movs r0, #0
|
|
|
800440c: 4688 mov r8, r1
|
|
|
800440e: 4681 mov r9, r0
|
|
|
8004410: eb12 0a08 adds.w sl, r2, r8
|
|
|
8004414: eb43 0b09 adc.w fp, r3, r9
|
|
|
8004418: 68fb ldr r3, [r7, #12]
|
|
|
800441a: 685b ldr r3, [r3, #4]
|
|
|
800441c: 2200 movs r2, #0
|
|
|
800441e: 603b str r3, [r7, #0]
|
|
|
8004420: 607a str r2, [r7, #4]
|
|
|
8004422: e9d7 2300 ldrd r2, r3, [r7]
|
|
|
8004426: 4650 mov r0, sl
|
|
|
8004428: 4659 mov r1, fp
|
|
|
800442a: f7fb fed7 bl 80001dc <__aeabi_uldivmod>
|
|
|
800442e: 4602 mov r2, r0
|
|
|
8004430: 460b mov r3, r1
|
|
|
8004432: 4613 mov r3, r2
|
|
|
8004434: 61bb str r3, [r7, #24]
|
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
|
8004436: 69bb ldr r3, [r7, #24]
|
|
|
8004438: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
|
800443c: d308 bcc.n 8004450 <UART_SetConfig+0x328>
|
|
|
800443e: 69bb ldr r3, [r7, #24]
|
|
|
8004440: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
|
8004444: d204 bcs.n 8004450 <UART_SetConfig+0x328>
|
|
|
{
|
|
|
huart->Instance->BRR = usartdiv;
|
|
|
8004446: 68fb ldr r3, [r7, #12]
|
|
|
8004448: 681b ldr r3, [r3, #0]
|
|
|
800444a: 69ba ldr r2, [r7, #24]
|
|
|
800444c: 60da str r2, [r3, #12]
|
|
|
800444e: e0b5 b.n 80045bc <UART_SetConfig+0x494>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
ret = HAL_ERROR;
|
|
|
8004450: 2301 movs r3, #1
|
|
|
8004452: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
8004456: e0b1 b.n 80045bc <UART_SetConfig+0x494>
|
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
} /* if (pclk != 0) */
|
|
|
}
|
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
|
8004458: 68fb ldr r3, [r7, #12]
|
|
|
800445a: 69db ldr r3, [r3, #28]
|
|
|
800445c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
|
|
|
8004460: d15d bne.n 800451e <UART_SetConfig+0x3f6>
|
|
|
{
|
|
|
switch (clocksource)
|
|
|
8004462: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
|
|
8004466: 2b08 cmp r3, #8
|
|
|
8004468: d827 bhi.n 80044ba <UART_SetConfig+0x392>
|
|
|
800446a: a201 add r2, pc, #4 ; (adr r2, 8004470 <UART_SetConfig+0x348>)
|
|
|
800446c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
8004470: 08004495 .word 0x08004495
|
|
|
8004474: 0800449d .word 0x0800449d
|
|
|
8004478: 080044a5 .word 0x080044a5
|
|
|
800447c: 080044bb .word 0x080044bb
|
|
|
8004480: 080044ab .word 0x080044ab
|
|
|
8004484: 080044bb .word 0x080044bb
|
|
|
8004488: 080044bb .word 0x080044bb
|
|
|
800448c: 080044bb .word 0x080044bb
|
|
|
8004490: 080044b3 .word 0x080044b3
|
|
|
{
|
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
|
8004494: f7fd ff42 bl 800231c <HAL_RCC_GetPCLK1Freq>
|
|
|
8004498: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
800449a: e014 b.n 80044c6 <UART_SetConfig+0x39e>
|
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
|
800449c: f7fd ff54 bl 8002348 <HAL_RCC_GetPCLK2Freq>
|
|
|
80044a0: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
80044a2: e010 b.n 80044c6 <UART_SetConfig+0x39e>
|
|
|
case UART_CLOCKSOURCE_HSI:
|
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
|
80044a4: 4b4c ldr r3, [pc, #304] ; (80045d8 <UART_SetConfig+0x4b0>)
|
|
|
80044a6: 61fb str r3, [r7, #28]
|
|
|
break;
|
|
|
80044a8: e00d b.n 80044c6 <UART_SetConfig+0x39e>
|
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
|
80044aa: f7fd fe9f bl 80021ec <HAL_RCC_GetSysClockFreq>
|
|
|
80044ae: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
80044b0: e009 b.n 80044c6 <UART_SetConfig+0x39e>
|
|
|
case UART_CLOCKSOURCE_LSE:
|
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
|
80044b2: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
|
80044b6: 61fb str r3, [r7, #28]
|
|
|
break;
|
|
|
80044b8: e005 b.n 80044c6 <UART_SetConfig+0x39e>
|
|
|
default:
|
|
|
pclk = 0U;
|
|
|
80044ba: 2300 movs r3, #0
|
|
|
80044bc: 61fb str r3, [r7, #28]
|
|
|
ret = HAL_ERROR;
|
|
|
80044be: 2301 movs r3, #1
|
|
|
80044c0: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
break;
|
|
|
80044c4: bf00 nop
|
|
|
}
|
|
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
|
if (pclk != 0U)
|
|
|
80044c6: 69fb ldr r3, [r7, #28]
|
|
|
80044c8: 2b00 cmp r3, #0
|
|
|
80044ca: d077 beq.n 80045bc <UART_SetConfig+0x494>
|
|
|
{
|
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
|
#else
|
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
|
80044cc: 69fb ldr r3, [r7, #28]
|
|
|
80044ce: 005a lsls r2, r3, #1
|
|
|
80044d0: 68fb ldr r3, [r7, #12]
|
|
|
80044d2: 685b ldr r3, [r3, #4]
|
|
|
80044d4: 085b lsrs r3, r3, #1
|
|
|
80044d6: 441a add r2, r3
|
|
|
80044d8: 68fb ldr r3, [r7, #12]
|
|
|
80044da: 685b ldr r3, [r3, #4]
|
|
|
80044dc: fbb2 f3f3 udiv r3, r2, r3
|
|
|
80044e0: 61bb str r3, [r7, #24]
|
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
|
80044e2: 69bb ldr r3, [r7, #24]
|
|
|
80044e4: 2b0f cmp r3, #15
|
|
|
80044e6: d916 bls.n 8004516 <UART_SetConfig+0x3ee>
|
|
|
80044e8: 69bb ldr r3, [r7, #24]
|
|
|
80044ea: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
80044ee: d212 bcs.n 8004516 <UART_SetConfig+0x3ee>
|
|
|
{
|
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
|
80044f0: 69bb ldr r3, [r7, #24]
|
|
|
80044f2: b29b uxth r3, r3
|
|
|
80044f4: f023 030f bic.w r3, r3, #15
|
|
|
80044f8: 82fb strh r3, [r7, #22]
|
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
|
80044fa: 69bb ldr r3, [r7, #24]
|
|
|
80044fc: 085b lsrs r3, r3, #1
|
|
|
80044fe: b29b uxth r3, r3
|
|
|
8004500: f003 0307 and.w r3, r3, #7
|
|
|
8004504: b29a uxth r2, r3
|
|
|
8004506: 8afb ldrh r3, [r7, #22]
|
|
|
8004508: 4313 orrs r3, r2
|
|
|
800450a: 82fb strh r3, [r7, #22]
|
|
|
huart->Instance->BRR = brrtemp;
|
|
|
800450c: 68fb ldr r3, [r7, #12]
|
|
|
800450e: 681b ldr r3, [r3, #0]
|
|
|
8004510: 8afa ldrh r2, [r7, #22]
|
|
|
8004512: 60da str r2, [r3, #12]
|
|
|
8004514: e052 b.n 80045bc <UART_SetConfig+0x494>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
ret = HAL_ERROR;
|
|
|
8004516: 2301 movs r3, #1
|
|
|
8004518: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
800451c: e04e b.n 80045bc <UART_SetConfig+0x494>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
switch (clocksource)
|
|
|
800451e: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
|
|
8004522: 2b08 cmp r3, #8
|
|
|
8004524: d827 bhi.n 8004576 <UART_SetConfig+0x44e>
|
|
|
8004526: a201 add r2, pc, #4 ; (adr r2, 800452c <UART_SetConfig+0x404>)
|
|
|
8004528: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
800452c: 08004551 .word 0x08004551
|
|
|
8004530: 08004559 .word 0x08004559
|
|
|
8004534: 08004561 .word 0x08004561
|
|
|
8004538: 08004577 .word 0x08004577
|
|
|
800453c: 08004567 .word 0x08004567
|
|
|
8004540: 08004577 .word 0x08004577
|
|
|
8004544: 08004577 .word 0x08004577
|
|
|
8004548: 08004577 .word 0x08004577
|
|
|
800454c: 0800456f .word 0x0800456f
|
|
|
{
|
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
|
8004550: f7fd fee4 bl 800231c <HAL_RCC_GetPCLK1Freq>
|
|
|
8004554: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
8004556: e014 b.n 8004582 <UART_SetConfig+0x45a>
|
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
|
8004558: f7fd fef6 bl 8002348 <HAL_RCC_GetPCLK2Freq>
|
|
|
800455c: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
800455e: e010 b.n 8004582 <UART_SetConfig+0x45a>
|
|
|
case UART_CLOCKSOURCE_HSI:
|
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
|
8004560: 4b1d ldr r3, [pc, #116] ; (80045d8 <UART_SetConfig+0x4b0>)
|
|
|
8004562: 61fb str r3, [r7, #28]
|
|
|
break;
|
|
|
8004564: e00d b.n 8004582 <UART_SetConfig+0x45a>
|
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
|
8004566: f7fd fe41 bl 80021ec <HAL_RCC_GetSysClockFreq>
|
|
|
800456a: 61f8 str r0, [r7, #28]
|
|
|
break;
|
|
|
800456c: e009 b.n 8004582 <UART_SetConfig+0x45a>
|
|
|
case UART_CLOCKSOURCE_LSE:
|
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
|
800456e: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
|
8004572: 61fb str r3, [r7, #28]
|
|
|
break;
|
|
|
8004574: e005 b.n 8004582 <UART_SetConfig+0x45a>
|
|
|
default:
|
|
|
pclk = 0U;
|
|
|
8004576: 2300 movs r3, #0
|
|
|
8004578: 61fb str r3, [r7, #28]
|
|
|
ret = HAL_ERROR;
|
|
|
800457a: 2301 movs r3, #1
|
|
|
800457c: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
break;
|
|
|
8004580: bf00 nop
|
|
|
}
|
|
|
|
|
|
if (pclk != 0U)
|
|
|
8004582: 69fb ldr r3, [r7, #28]
|
|
|
8004584: 2b00 cmp r3, #0
|
|
|
8004586: d019 beq.n 80045bc <UART_SetConfig+0x494>
|
|
|
{
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
|
#else
|
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
|
8004588: 68fb ldr r3, [r7, #12]
|
|
|
800458a: 685b ldr r3, [r3, #4]
|
|
|
800458c: 085a lsrs r2, r3, #1
|
|
|
800458e: 69fb ldr r3, [r7, #28]
|
|
|
8004590: 441a add r2, r3
|
|
|
8004592: 68fb ldr r3, [r7, #12]
|
|
|
8004594: 685b ldr r3, [r3, #4]
|
|
|
8004596: fbb2 f3f3 udiv r3, r2, r3
|
|
|
800459a: 61bb str r3, [r7, #24]
|
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
|
800459c: 69bb ldr r3, [r7, #24]
|
|
|
800459e: 2b0f cmp r3, #15
|
|
|
80045a0: d909 bls.n 80045b6 <UART_SetConfig+0x48e>
|
|
|
80045a2: 69bb ldr r3, [r7, #24]
|
|
|
80045a4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
80045a8: d205 bcs.n 80045b6 <UART_SetConfig+0x48e>
|
|
|
{
|
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
|
80045aa: 69bb ldr r3, [r7, #24]
|
|
|
80045ac: b29a uxth r2, r3
|
|
|
80045ae: 68fb ldr r3, [r7, #12]
|
|
|
80045b0: 681b ldr r3, [r3, #0]
|
|
|
80045b2: 60da str r2, [r3, #12]
|
|
|
80045b4: e002 b.n 80045bc <UART_SetConfig+0x494>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
ret = HAL_ERROR;
|
|
|
80045b6: 2301 movs r3, #1
|
|
|
80045b8: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
|
|
huart->NbTxDataToProcess = 1;
|
|
|
huart->NbRxDataToProcess = 1;
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* Clear ISR function pointers */
|
|
|
huart->RxISR = NULL;
|
|
|
80045bc: 68fb ldr r3, [r7, #12]
|
|
|
80045be: 2200 movs r2, #0
|
|
|
80045c0: 669a str r2, [r3, #104] ; 0x68
|
|
|
huart->TxISR = NULL;
|
|
|
80045c2: 68fb ldr r3, [r7, #12]
|
|
|
80045c4: 2200 movs r2, #0
|
|
|
80045c6: 66da str r2, [r3, #108] ; 0x6c
|
|
|
|
|
|
return ret;
|
|
|
80045c8: f897 3022 ldrb.w r3, [r7, #34] ; 0x22
|
|
|
}
|
|
|
80045cc: 4618 mov r0, r3
|
|
|
80045ce: 3728 adds r7, #40 ; 0x28
|
|
|
80045d0: 46bd mov sp, r7
|
|
|
80045d2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
|
80045d6: bf00 nop
|
|
|
80045d8: 00f42400 .word 0x00f42400
|
|
|
|
|
|
080045dc <UART_AdvFeatureConfig>:
|
|
|
* @brief Configure the UART peripheral advanced features.
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
80045dc: b480 push {r7}
|
|
|
80045de: b083 sub sp, #12
|
|
|
80045e0: af00 add r7, sp, #0
|
|
|
80045e2: 6078 str r0, [r7, #4]
|
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
|
80045e4: 687b ldr r3, [r7, #4]
|
|
|
80045e6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
80045e8: f003 0308 and.w r3, r3, #8
|
|
|
80045ec: 2b00 cmp r3, #0
|
|
|
80045ee: d00a beq.n 8004606 <UART_AdvFeatureConfig+0x2a>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
|
80045f0: 687b ldr r3, [r7, #4]
|
|
|
80045f2: 681b ldr r3, [r3, #0]
|
|
|
80045f4: 685b ldr r3, [r3, #4]
|
|
|
80045f6: f423 4100 bic.w r1, r3, #32768 ; 0x8000
|
|
|
80045fa: 687b ldr r3, [r7, #4]
|
|
|
80045fc: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
|
80045fe: 687b ldr r3, [r7, #4]
|
|
|
8004600: 681b ldr r3, [r3, #0]
|
|
|
8004602: 430a orrs r2, r1
|
|
|
8004604: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
|
8004606: 687b ldr r3, [r7, #4]
|
|
|
8004608: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800460a: f003 0301 and.w r3, r3, #1
|
|
|
800460e: 2b00 cmp r3, #0
|
|
|
8004610: d00a beq.n 8004628 <UART_AdvFeatureConfig+0x4c>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
|
8004612: 687b ldr r3, [r7, #4]
|
|
|
8004614: 681b ldr r3, [r3, #0]
|
|
|
8004616: 685b ldr r3, [r3, #4]
|
|
|
8004618: f423 3100 bic.w r1, r3, #131072 ; 0x20000
|
|
|
800461c: 687b ldr r3, [r7, #4]
|
|
|
800461e: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
|
8004620: 687b ldr r3, [r7, #4]
|
|
|
8004622: 681b ldr r3, [r3, #0]
|
|
|
8004624: 430a orrs r2, r1
|
|
|
8004626: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
|
8004628: 687b ldr r3, [r7, #4]
|
|
|
800462a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800462c: f003 0302 and.w r3, r3, #2
|
|
|
8004630: 2b00 cmp r3, #0
|
|
|
8004632: d00a beq.n 800464a <UART_AdvFeatureConfig+0x6e>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
|
8004634: 687b ldr r3, [r7, #4]
|
|
|
8004636: 681b ldr r3, [r3, #0]
|
|
|
8004638: 685b ldr r3, [r3, #4]
|
|
|
800463a: f423 3180 bic.w r1, r3, #65536 ; 0x10000
|
|
|
800463e: 687b ldr r3, [r7, #4]
|
|
|
8004640: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
|
8004642: 687b ldr r3, [r7, #4]
|
|
|
8004644: 681b ldr r3, [r3, #0]
|
|
|
8004646: 430a orrs r2, r1
|
|
|
8004648: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
|
|
|
/* if required, configure data inversion */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
|
800464a: 687b ldr r3, [r7, #4]
|
|
|
800464c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800464e: f003 0304 and.w r3, r3, #4
|
|
|
8004652: 2b00 cmp r3, #0
|
|
|
8004654: d00a beq.n 800466c <UART_AdvFeatureConfig+0x90>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
|
8004656: 687b ldr r3, [r7, #4]
|
|
|
8004658: 681b ldr r3, [r3, #0]
|
|
|
800465a: 685b ldr r3, [r3, #4]
|
|
|
800465c: f423 2180 bic.w r1, r3, #262144 ; 0x40000
|
|
|
8004660: 687b ldr r3, [r7, #4]
|
|
|
8004662: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
|
8004664: 687b ldr r3, [r7, #4]
|
|
|
8004666: 681b ldr r3, [r3, #0]
|
|
|
8004668: 430a orrs r2, r1
|
|
|
800466a: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
|
800466c: 687b ldr r3, [r7, #4]
|
|
|
800466e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8004670: f003 0310 and.w r3, r3, #16
|
|
|
8004674: 2b00 cmp r3, #0
|
|
|
8004676: d00a beq.n 800468e <UART_AdvFeatureConfig+0xb2>
|
|
|
{
|
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
|
8004678: 687b ldr r3, [r7, #4]
|
|
|
800467a: 681b ldr r3, [r3, #0]
|
|
|
800467c: 689b ldr r3, [r3, #8]
|
|
|
800467e: f423 5180 bic.w r1, r3, #4096 ; 0x1000
|
|
|
8004682: 687b ldr r3, [r7, #4]
|
|
|
8004684: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
|
8004686: 687b ldr r3, [r7, #4]
|
|
|
8004688: 681b ldr r3, [r3, #0]
|
|
|
800468a: 430a orrs r2, r1
|
|
|
800468c: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
|
800468e: 687b ldr r3, [r7, #4]
|
|
|
8004690: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8004692: f003 0320 and.w r3, r3, #32
|
|
|
8004696: 2b00 cmp r3, #0
|
|
|
8004698: d00a beq.n 80046b0 <UART_AdvFeatureConfig+0xd4>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
|
800469a: 687b ldr r3, [r7, #4]
|
|
|
800469c: 681b ldr r3, [r3, #0]
|
|
|
800469e: 689b ldr r3, [r3, #8]
|
|
|
80046a0: f423 5100 bic.w r1, r3, #8192 ; 0x2000
|
|
|
80046a4: 687b ldr r3, [r7, #4]
|
|
|
80046a6: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
|
80046a8: 687b ldr r3, [r7, #4]
|
|
|
80046aa: 681b ldr r3, [r3, #0]
|
|
|
80046ac: 430a orrs r2, r1
|
|
|
80046ae: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
|
80046b0: 687b ldr r3, [r7, #4]
|
|
|
80046b2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
80046b4: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
|
80046b8: 2b00 cmp r3, #0
|
|
|
80046ba: d01a beq.n 80046f2 <UART_AdvFeatureConfig+0x116>
|
|
|
{
|
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
|
80046bc: 687b ldr r3, [r7, #4]
|
|
|
80046be: 681b ldr r3, [r3, #0]
|
|
|
80046c0: 685b ldr r3, [r3, #4]
|
|
|
80046c2: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
|
|
|
80046c6: 687b ldr r3, [r7, #4]
|
|
|
80046c8: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
|
80046ca: 687b ldr r3, [r7, #4]
|
|
|
80046cc: 681b ldr r3, [r3, #0]
|
|
|
80046ce: 430a orrs r2, r1
|
|
|
80046d0: 605a str r2, [r3, #4]
|
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
|
80046d2: 687b ldr r3, [r7, #4]
|
|
|
80046d4: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
|
80046d6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
|
80046da: d10a bne.n 80046f2 <UART_AdvFeatureConfig+0x116>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
|
80046dc: 687b ldr r3, [r7, #4]
|
|
|
80046de: 681b ldr r3, [r3, #0]
|
|
|
80046e0: 685b ldr r3, [r3, #4]
|
|
|
80046e2: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
|
|
|
80046e6: 687b ldr r3, [r7, #4]
|
|
|
80046e8: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
|
80046ea: 687b ldr r3, [r7, #4]
|
|
|
80046ec: 681b ldr r3, [r3, #0]
|
|
|
80046ee: 430a orrs r2, r1
|
|
|
80046f0: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
|
80046f2: 687b ldr r3, [r7, #4]
|
|
|
80046f4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
80046f6: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
|
80046fa: 2b00 cmp r3, #0
|
|
|
80046fc: d00a beq.n 8004714 <UART_AdvFeatureConfig+0x138>
|
|
|
{
|
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
|
80046fe: 687b ldr r3, [r7, #4]
|
|
|
8004700: 681b ldr r3, [r3, #0]
|
|
|
8004702: 685b ldr r3, [r3, #4]
|
|
|
8004704: f423 2100 bic.w r1, r3, #524288 ; 0x80000
|
|
|
8004708: 687b ldr r3, [r7, #4]
|
|
|
800470a: 6c9a ldr r2, [r3, #72] ; 0x48
|
|
|
800470c: 687b ldr r3, [r7, #4]
|
|
|
800470e: 681b ldr r3, [r3, #0]
|
|
|
8004710: 430a orrs r2, r1
|
|
|
8004712: 605a str r2, [r3, #4]
|
|
|
}
|
|
|
}
|
|
|
8004714: bf00 nop
|
|
|
8004716: 370c adds r7, #12
|
|
|
8004718: 46bd mov sp, r7
|
|
|
800471a: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
800471e: 4770 bx lr
|
|
|
|
|
|
08004720 <UART_CheckIdleState>:
|
|
|
* @brief Check the UART Idle State.
|
|
|
* @param huart UART handle.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004720: b580 push {r7, lr}
|
|
|
8004722: b098 sub sp, #96 ; 0x60
|
|
|
8004724: af02 add r7, sp, #8
|
|
|
8004726: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart;
|
|
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
8004728: 687b ldr r3, [r7, #4]
|
|
|
800472a: 2200 movs r2, #0
|
|
|
800472c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
|
|
|
/* Init tickstart for timeout management */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8004730: f7fc fc7a bl 8001028 <HAL_GetTick>
|
|
|
8004734: 6578 str r0, [r7, #84] ; 0x54
|
|
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
|
8004736: 687b ldr r3, [r7, #4]
|
|
|
8004738: 681b ldr r3, [r3, #0]
|
|
|
800473a: 681b ldr r3, [r3, #0]
|
|
|
800473c: f003 0308 and.w r3, r3, #8
|
|
|
8004740: 2b08 cmp r3, #8
|
|
|
8004742: d12e bne.n 80047a2 <UART_CheckIdleState+0x82>
|
|
|
{
|
|
|
/* Wait until TEACK flag is set */
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
|
8004744: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
|
|
8004748: 9300 str r3, [sp, #0]
|
|
|
800474a: 6d7b ldr r3, [r7, #84] ; 0x54
|
|
|
800474c: 2200 movs r2, #0
|
|
|
800474e: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
|
8004752: 6878 ldr r0, [r7, #4]
|
|
|
8004754: f000 f88c bl 8004870 <UART_WaitOnFlagUntilTimeout>
|
|
|
8004758: 4603 mov r3, r0
|
|
|
800475a: 2b00 cmp r3, #0
|
|
|
800475c: d021 beq.n 80047a2 <UART_CheckIdleState+0x82>
|
|
|
{
|
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
|
|
|
800475e: 687b ldr r3, [r7, #4]
|
|
|
8004760: 681b ldr r3, [r3, #0]
|
|
|
8004762: 63bb str r3, [r7, #56] ; 0x38
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004764: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8004766: e853 3f00 ldrex r3, [r3]
|
|
|
800476a: 637b str r3, [r7, #52] ; 0x34
|
|
|
return(result);
|
|
|
800476c: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
800476e: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
|
8004772: 653b str r3, [r7, #80] ; 0x50
|
|
|
8004774: 687b ldr r3, [r7, #4]
|
|
|
8004776: 681b ldr r3, [r3, #0]
|
|
|
8004778: 461a mov r2, r3
|
|
|
800477a: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
|
800477c: 647b str r3, [r7, #68] ; 0x44
|
|
|
800477e: 643a str r2, [r7, #64] ; 0x40
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004780: 6c39 ldr r1, [r7, #64] ; 0x40
|
|
|
8004782: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
|
8004784: e841 2300 strex r3, r2, [r1]
|
|
|
8004788: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
return(result);
|
|
|
800478a: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
|
800478c: 2b00 cmp r3, #0
|
|
|
800478e: d1e6 bne.n 800475e <UART_CheckIdleState+0x3e>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
8004790: 687b ldr r3, [r7, #4]
|
|
|
8004792: 2220 movs r2, #32
|
|
|
8004794: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
__HAL_UNLOCK(huart);
|
|
|
8004796: 687b ldr r3, [r7, #4]
|
|
|
8004798: 2200 movs r2, #0
|
|
|
800479a: f883 2078 strb.w r2, [r3, #120] ; 0x78
|
|
|
|
|
|
/* Timeout occurred */
|
|
|
return HAL_TIMEOUT;
|
|
|
800479e: 2303 movs r3, #3
|
|
|
80047a0: e062 b.n 8004868 <UART_CheckIdleState+0x148>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Check if the Receiver is enabled */
|
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
|
80047a2: 687b ldr r3, [r7, #4]
|
|
|
80047a4: 681b ldr r3, [r3, #0]
|
|
|
80047a6: 681b ldr r3, [r3, #0]
|
|
|
80047a8: f003 0304 and.w r3, r3, #4
|
|
|
80047ac: 2b04 cmp r3, #4
|
|
|
80047ae: d149 bne.n 8004844 <UART_CheckIdleState+0x124>
|
|
|
{
|
|
|
/* Wait until REACK flag is set */
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
|
80047b0: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
|
|
80047b4: 9300 str r3, [sp, #0]
|
|
|
80047b6: 6d7b ldr r3, [r7, #84] ; 0x54
|
|
|
80047b8: 2200 movs r2, #0
|
|
|
80047ba: f44f 0180 mov.w r1, #4194304 ; 0x400000
|
|
|
80047be: 6878 ldr r0, [r7, #4]
|
|
|
80047c0: f000 f856 bl 8004870 <UART_WaitOnFlagUntilTimeout>
|
|
|
80047c4: 4603 mov r3, r0
|
|
|
80047c6: 2b00 cmp r3, #0
|
|
|
80047c8: d03c beq.n 8004844 <UART_CheckIdleState+0x124>
|
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
|
interrupts for the interrupt process */
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
|
80047ca: 687b ldr r3, [r7, #4]
|
|
|
80047cc: 681b ldr r3, [r3, #0]
|
|
|
80047ce: 627b str r3, [r7, #36] ; 0x24
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
80047d0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
80047d2: e853 3f00 ldrex r3, [r3]
|
|
|
80047d6: 623b str r3, [r7, #32]
|
|
|
return(result);
|
|
|
80047d8: 6a3b ldr r3, [r7, #32]
|
|
|
80047da: f423 7390 bic.w r3, r3, #288 ; 0x120
|
|
|
80047de: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
80047e0: 687b ldr r3, [r7, #4]
|
|
|
80047e2: 681b ldr r3, [r3, #0]
|
|
|
80047e4: 461a mov r2, r3
|
|
|
80047e6: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
|
80047e8: 633b str r3, [r7, #48] ; 0x30
|
|
|
80047ea: 62fa str r2, [r7, #44] ; 0x2c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
80047ec: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
|
80047ee: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
|
80047f0: e841 2300 strex r3, r2, [r1]
|
|
|
80047f4: 62bb str r3, [r7, #40] ; 0x28
|
|
|
return(result);
|
|
|
80047f6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
80047f8: 2b00 cmp r3, #0
|
|
|
80047fa: d1e6 bne.n 80047ca <UART_CheckIdleState+0xaa>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
80047fc: 687b ldr r3, [r7, #4]
|
|
|
80047fe: 681b ldr r3, [r3, #0]
|
|
|
8004800: 3308 adds r3, #8
|
|
|
8004802: 613b str r3, [r7, #16]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004804: 693b ldr r3, [r7, #16]
|
|
|
8004806: e853 3f00 ldrex r3, [r3]
|
|
|
800480a: 60fb str r3, [r7, #12]
|
|
|
return(result);
|
|
|
800480c: 68fb ldr r3, [r7, #12]
|
|
|
800480e: f023 0301 bic.w r3, r3, #1
|
|
|
8004812: 64bb str r3, [r7, #72] ; 0x48
|
|
|
8004814: 687b ldr r3, [r7, #4]
|
|
|
8004816: 681b ldr r3, [r3, #0]
|
|
|
8004818: 3308 adds r3, #8
|
|
|
800481a: 6cba ldr r2, [r7, #72] ; 0x48
|
|
|
800481c: 61fa str r2, [r7, #28]
|
|
|
800481e: 61bb str r3, [r7, #24]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004820: 69b9 ldr r1, [r7, #24]
|
|
|
8004822: 69fa ldr r2, [r7, #28]
|
|
|
8004824: e841 2300 strex r3, r2, [r1]
|
|
|
8004828: 617b str r3, [r7, #20]
|
|
|
return(result);
|
|
|
800482a: 697b ldr r3, [r7, #20]
|
|
|
800482c: 2b00 cmp r3, #0
|
|
|
800482e: d1e5 bne.n 80047fc <UART_CheckIdleState+0xdc>
|
|
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8004830: 687b ldr r3, [r7, #4]
|
|
|
8004832: 2220 movs r2, #32
|
|
|
8004834: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
|
|
|
__HAL_UNLOCK(huart);
|
|
|
8004838: 687b ldr r3, [r7, #4]
|
|
|
800483a: 2200 movs r2, #0
|
|
|
800483c: f883 2078 strb.w r2, [r3, #120] ; 0x78
|
|
|
|
|
|
/* Timeout occurred */
|
|
|
return HAL_TIMEOUT;
|
|
|
8004840: 2303 movs r3, #3
|
|
|
8004842: e011 b.n 8004868 <UART_CheckIdleState+0x148>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Initialize the UART State */
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
8004844: 687b ldr r3, [r7, #4]
|
|
|
8004846: 2220 movs r2, #32
|
|
|
8004848: 67da str r2, [r3, #124] ; 0x7c
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
800484a: 687b ldr r3, [r7, #4]
|
|
|
800484c: 2220 movs r2, #32
|
|
|
800484e: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
8004852: 687b ldr r3, [r7, #4]
|
|
|
8004854: 2200 movs r2, #0
|
|
|
8004856: 661a str r2, [r3, #96] ; 0x60
|
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
|
800485a: 2200 movs r2, #0
|
|
|
800485c: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
|
|
__HAL_UNLOCK(huart);
|
|
|
800485e: 687b ldr r3, [r7, #4]
|
|
|
8004860: 2200 movs r2, #0
|
|
|
8004862: f883 2078 strb.w r2, [r3, #120] ; 0x78
|
|
|
|
|
|
return HAL_OK;
|
|
|
8004866: 2300 movs r3, #0
|
|
|
}
|
|
|
8004868: 4618 mov r0, r3
|
|
|
800486a: 3758 adds r7, #88 ; 0x58
|
|
|
800486c: 46bd mov sp, r7
|
|
|
800486e: bd80 pop {r7, pc}
|
|
|
|
|
|
08004870 <UART_WaitOnFlagUntilTimeout>:
|
|
|
* @param Timeout Timeout duration
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
|
{
|
|
|
8004870: b580 push {r7, lr}
|
|
|
8004872: b084 sub sp, #16
|
|
|
8004874: af00 add r7, sp, #0
|
|
|
8004876: 60f8 str r0, [r7, #12]
|
|
|
8004878: 60b9 str r1, [r7, #8]
|
|
|
800487a: 603b str r3, [r7, #0]
|
|
|
800487c: 4613 mov r3, r2
|
|
|
800487e: 71fb strb r3, [r7, #7]
|
|
|
/* Wait until flag is set */
|
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
|
8004880: e049 b.n 8004916 <UART_WaitOnFlagUntilTimeout+0xa6>
|
|
|
{
|
|
|
/* Check for the Timeout */
|
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
|
8004882: 69bb ldr r3, [r7, #24]
|
|
|
8004884: f1b3 3fff cmp.w r3, #4294967295
|
|
|
8004888: d045 beq.n 8004916 <UART_WaitOnFlagUntilTimeout+0xa6>
|
|
|
{
|
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
|
800488a: f7fc fbcd bl 8001028 <HAL_GetTick>
|
|
|
800488e: 4602 mov r2, r0
|
|
|
8004890: 683b ldr r3, [r7, #0]
|
|
|
8004892: 1ad3 subs r3, r2, r3
|
|
|
8004894: 69ba ldr r2, [r7, #24]
|
|
|
8004896: 429a cmp r2, r3
|
|
|
8004898: d302 bcc.n 80048a0 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
|
800489a: 69bb ldr r3, [r7, #24]
|
|
|
800489c: 2b00 cmp r3, #0
|
|
|
800489e: d101 bne.n 80048a4 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
|
{
|
|
|
|
|
|
return HAL_TIMEOUT;
|
|
|
80048a0: 2303 movs r3, #3
|
|
|
80048a2: e048 b.n 8004936 <UART_WaitOnFlagUntilTimeout+0xc6>
|
|
|
}
|
|
|
|
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
|
|
80048a4: 68fb ldr r3, [r7, #12]
|
|
|
80048a6: 681b ldr r3, [r3, #0]
|
|
|
80048a8: 681b ldr r3, [r3, #0]
|
|
|
80048aa: f003 0304 and.w r3, r3, #4
|
|
|
80048ae: 2b00 cmp r3, #0
|
|
|
80048b0: d031 beq.n 8004916 <UART_WaitOnFlagUntilTimeout+0xa6>
|
|
|
{
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
|
80048b2: 68fb ldr r3, [r7, #12]
|
|
|
80048b4: 681b ldr r3, [r3, #0]
|
|
|
80048b6: 69db ldr r3, [r3, #28]
|
|
|
80048b8: f003 0308 and.w r3, r3, #8
|
|
|
80048bc: 2b08 cmp r3, #8
|
|
|
80048be: d110 bne.n 80048e2 <UART_WaitOnFlagUntilTimeout+0x72>
|
|
|
{
|
|
|
/* Clear Overrun Error flag*/
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
|
80048c0: 68fb ldr r3, [r7, #12]
|
|
|
80048c2: 681b ldr r3, [r3, #0]
|
|
|
80048c4: 2208 movs r2, #8
|
|
|
80048c6: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Blocking error : transfer is aborted
|
|
|
Set the UART state ready to be able to start again the process,
|
|
|
Disable Rx Interrupts if ongoing */
|
|
|
UART_EndRxTransfer(huart);
|
|
|
80048c8: 68f8 ldr r0, [r7, #12]
|
|
|
80048ca: f000 f8ff bl 8004acc <UART_EndRxTransfer>
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
|
80048ce: 68fb ldr r3, [r7, #12]
|
|
|
80048d0: 2208 movs r2, #8
|
|
|
80048d2: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(huart);
|
|
|
80048d6: 68fb ldr r3, [r7, #12]
|
|
|
80048d8: 2200 movs r2, #0
|
|
|
80048da: f883 2078 strb.w r2, [r3, #120] ; 0x78
|
|
|
|
|
|
return HAL_ERROR;
|
|
|
80048de: 2301 movs r3, #1
|
|
|
80048e0: e029 b.n 8004936 <UART_WaitOnFlagUntilTimeout+0xc6>
|
|
|
}
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
|
80048e2: 68fb ldr r3, [r7, #12]
|
|
|
80048e4: 681b ldr r3, [r3, #0]
|
|
|
80048e6: 69db ldr r3, [r3, #28]
|
|
|
80048e8: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
|
80048ec: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
|
80048f0: d111 bne.n 8004916 <UART_WaitOnFlagUntilTimeout+0xa6>
|
|
|
{
|
|
|
/* Clear Receiver Timeout flag*/
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
|
80048f2: 68fb ldr r3, [r7, #12]
|
|
|
80048f4: 681b ldr r3, [r3, #0]
|
|
|
80048f6: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
|
80048fa: 621a str r2, [r3, #32]
|
|
|
|
|
|
/* Blocking error : transfer is aborted
|
|
|
Set the UART state ready to be able to start again the process,
|
|
|
Disable Rx Interrupts if ongoing */
|
|
|
UART_EndRxTransfer(huart);
|
|
|
80048fc: 68f8 ldr r0, [r7, #12]
|
|
|
80048fe: f000 f8e5 bl 8004acc <UART_EndRxTransfer>
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
|
8004902: 68fb ldr r3, [r7, #12]
|
|
|
8004904: 2220 movs r2, #32
|
|
|
8004906: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(huart);
|
|
|
800490a: 68fb ldr r3, [r7, #12]
|
|
|
800490c: 2200 movs r2, #0
|
|
|
800490e: f883 2078 strb.w r2, [r3, #120] ; 0x78
|
|
|
|
|
|
return HAL_TIMEOUT;
|
|
|
8004912: 2303 movs r3, #3
|
|
|
8004914: e00f b.n 8004936 <UART_WaitOnFlagUntilTimeout+0xc6>
|
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
|
8004916: 68fb ldr r3, [r7, #12]
|
|
|
8004918: 681b ldr r3, [r3, #0]
|
|
|
800491a: 69da ldr r2, [r3, #28]
|
|
|
800491c: 68bb ldr r3, [r7, #8]
|
|
|
800491e: 4013 ands r3, r2
|
|
|
8004920: 68ba ldr r2, [r7, #8]
|
|
|
8004922: 429a cmp r2, r3
|
|
|
8004924: bf0c ite eq
|
|
|
8004926: 2301 moveq r3, #1
|
|
|
8004928: 2300 movne r3, #0
|
|
|
800492a: b2db uxtb r3, r3
|
|
|
800492c: 461a mov r2, r3
|
|
|
800492e: 79fb ldrb r3, [r7, #7]
|
|
|
8004930: 429a cmp r2, r3
|
|
|
8004932: d0a6 beq.n 8004882 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
return HAL_OK;
|
|
|
8004934: 2300 movs r3, #0
|
|
|
}
|
|
|
8004936: 4618 mov r0, r3
|
|
|
8004938: 3710 adds r7, #16
|
|
|
800493a: 46bd mov sp, r7
|
|
|
800493c: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08004940 <UART_Start_Receive_IT>:
|
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
|
{
|
|
|
8004940: b480 push {r7}
|
|
|
8004942: b097 sub sp, #92 ; 0x5c
|
|
|
8004944: af00 add r7, sp, #0
|
|
|
8004946: 60f8 str r0, [r7, #12]
|
|
|
8004948: 60b9 str r1, [r7, #8]
|
|
|
800494a: 4613 mov r3, r2
|
|
|
800494c: 80fb strh r3, [r7, #6]
|
|
|
huart->pRxBuffPtr = pData;
|
|
|
800494e: 68fb ldr r3, [r7, #12]
|
|
|
8004950: 68ba ldr r2, [r7, #8]
|
|
|
8004952: 655a str r2, [r3, #84] ; 0x54
|
|
|
huart->RxXferSize = Size;
|
|
|
8004954: 68fb ldr r3, [r7, #12]
|
|
|
8004956: 88fa ldrh r2, [r7, #6]
|
|
|
8004958: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
|
|
|
huart->RxXferCount = Size;
|
|
|
800495c: 68fb ldr r3, [r7, #12]
|
|
|
800495e: 88fa ldrh r2, [r7, #6]
|
|
|
8004960: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
huart->RxISR = NULL;
|
|
|
8004964: 68fb ldr r3, [r7, #12]
|
|
|
8004966: 2200 movs r2, #0
|
|
|
8004968: 669a str r2, [r3, #104] ; 0x68
|
|
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
|
UART_MASK_COMPUTATION(huart);
|
|
|
800496a: 68fb ldr r3, [r7, #12]
|
|
|
800496c: 689b ldr r3, [r3, #8]
|
|
|
800496e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8004972: d10e bne.n 8004992 <UART_Start_Receive_IT+0x52>
|
|
|
8004974: 68fb ldr r3, [r7, #12]
|
|
|
8004976: 691b ldr r3, [r3, #16]
|
|
|
8004978: 2b00 cmp r3, #0
|
|
|
800497a: d105 bne.n 8004988 <UART_Start_Receive_IT+0x48>
|
|
|
800497c: 68fb ldr r3, [r7, #12]
|
|
|
800497e: f240 12ff movw r2, #511 ; 0x1ff
|
|
|
8004982: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
8004986: e02d b.n 80049e4 <UART_Start_Receive_IT+0xa4>
|
|
|
8004988: 68fb ldr r3, [r7, #12]
|
|
|
800498a: 22ff movs r2, #255 ; 0xff
|
|
|
800498c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
8004990: e028 b.n 80049e4 <UART_Start_Receive_IT+0xa4>
|
|
|
8004992: 68fb ldr r3, [r7, #12]
|
|
|
8004994: 689b ldr r3, [r3, #8]
|
|
|
8004996: 2b00 cmp r3, #0
|
|
|
8004998: d10d bne.n 80049b6 <UART_Start_Receive_IT+0x76>
|
|
|
800499a: 68fb ldr r3, [r7, #12]
|
|
|
800499c: 691b ldr r3, [r3, #16]
|
|
|
800499e: 2b00 cmp r3, #0
|
|
|
80049a0: d104 bne.n 80049ac <UART_Start_Receive_IT+0x6c>
|
|
|
80049a2: 68fb ldr r3, [r7, #12]
|
|
|
80049a4: 22ff movs r2, #255 ; 0xff
|
|
|
80049a6: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
80049aa: e01b b.n 80049e4 <UART_Start_Receive_IT+0xa4>
|
|
|
80049ac: 68fb ldr r3, [r7, #12]
|
|
|
80049ae: 227f movs r2, #127 ; 0x7f
|
|
|
80049b0: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
80049b4: e016 b.n 80049e4 <UART_Start_Receive_IT+0xa4>
|
|
|
80049b6: 68fb ldr r3, [r7, #12]
|
|
|
80049b8: 689b ldr r3, [r3, #8]
|
|
|
80049ba: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
|
|
|
80049be: d10d bne.n 80049dc <UART_Start_Receive_IT+0x9c>
|
|
|
80049c0: 68fb ldr r3, [r7, #12]
|
|
|
80049c2: 691b ldr r3, [r3, #16]
|
|
|
80049c4: 2b00 cmp r3, #0
|
|
|
80049c6: d104 bne.n 80049d2 <UART_Start_Receive_IT+0x92>
|
|
|
80049c8: 68fb ldr r3, [r7, #12]
|
|
|
80049ca: 227f movs r2, #127 ; 0x7f
|
|
|
80049cc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
80049d0: e008 b.n 80049e4 <UART_Start_Receive_IT+0xa4>
|
|
|
80049d2: 68fb ldr r3, [r7, #12]
|
|
|
80049d4: 223f movs r2, #63 ; 0x3f
|
|
|
80049d6: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
80049da: e003 b.n 80049e4 <UART_Start_Receive_IT+0xa4>
|
|
|
80049dc: 68fb ldr r3, [r7, #12]
|
|
|
80049de: 2200 movs r2, #0
|
|
|
80049e0: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
80049e4: 68fb ldr r3, [r7, #12]
|
|
|
80049e6: 2200 movs r2, #0
|
|
|
80049e8: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
|
80049ec: 68fb ldr r3, [r7, #12]
|
|
|
80049ee: 2222 movs r2, #34 ; 0x22
|
|
|
80049f0: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
80049f4: 68fb ldr r3, [r7, #12]
|
|
|
80049f6: 681b ldr r3, [r3, #0]
|
|
|
80049f8: 3308 adds r3, #8
|
|
|
80049fa: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
80049fc: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
|
80049fe: e853 3f00 ldrex r3, [r3]
|
|
|
8004a02: 63bb str r3, [r7, #56] ; 0x38
|
|
|
return(result);
|
|
|
8004a04: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8004a06: f043 0301 orr.w r3, r3, #1
|
|
|
8004a0a: 657b str r3, [r7, #84] ; 0x54
|
|
|
8004a0c: 68fb ldr r3, [r7, #12]
|
|
|
8004a0e: 681b ldr r3, [r3, #0]
|
|
|
8004a10: 3308 adds r3, #8
|
|
|
8004a12: 6d7a ldr r2, [r7, #84] ; 0x54
|
|
|
8004a14: 64ba str r2, [r7, #72] ; 0x48
|
|
|
8004a16: 647b str r3, [r7, #68] ; 0x44
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004a18: 6c79 ldr r1, [r7, #68] ; 0x44
|
|
|
8004a1a: 6cba ldr r2, [r7, #72] ; 0x48
|
|
|
8004a1c: e841 2300 strex r3, r2, [r1]
|
|
|
8004a20: 643b str r3, [r7, #64] ; 0x40
|
|
|
return(result);
|
|
|
8004a22: 6c3b ldr r3, [r7, #64] ; 0x40
|
|
|
8004a24: 2b00 cmp r3, #0
|
|
|
8004a26: d1e5 bne.n 80049f4 <UART_Start_Receive_IT+0xb4>
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
|
}
|
|
|
}
|
|
|
#else
|
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
|
8004a28: 68fb ldr r3, [r7, #12]
|
|
|
8004a2a: 689b ldr r3, [r3, #8]
|
|
|
8004a2c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8004a30: d107 bne.n 8004a42 <UART_Start_Receive_IT+0x102>
|
|
|
8004a32: 68fb ldr r3, [r7, #12]
|
|
|
8004a34: 691b ldr r3, [r3, #16]
|
|
|
8004a36: 2b00 cmp r3, #0
|
|
|
8004a38: d103 bne.n 8004a42 <UART_Start_Receive_IT+0x102>
|
|
|
{
|
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
|
8004a3a: 68fb ldr r3, [r7, #12]
|
|
|
8004a3c: 4a21 ldr r2, [pc, #132] ; (8004ac4 <UART_Start_Receive_IT+0x184>)
|
|
|
8004a3e: 669a str r2, [r3, #104] ; 0x68
|
|
|
8004a40: e002 b.n 8004a48 <UART_Start_Receive_IT+0x108>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
|
8004a42: 68fb ldr r3, [r7, #12]
|
|
|
8004a44: 4a20 ldr r2, [pc, #128] ; (8004ac8 <UART_Start_Receive_IT+0x188>)
|
|
|
8004a46: 669a str r2, [r3, #104] ; 0x68
|
|
|
}
|
|
|
|
|
|
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
|
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
|
8004a48: 68fb ldr r3, [r7, #12]
|
|
|
8004a4a: 691b ldr r3, [r3, #16]
|
|
|
8004a4c: 2b00 cmp r3, #0
|
|
|
8004a4e: d019 beq.n 8004a84 <UART_Start_Receive_IT+0x144>
|
|
|
{
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
|
|
|
8004a50: 68fb ldr r3, [r7, #12]
|
|
|
8004a52: 681b ldr r3, [r3, #0]
|
|
|
8004a54: 62bb str r3, [r7, #40] ; 0x28
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004a56: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
8004a58: e853 3f00 ldrex r3, [r3]
|
|
|
8004a5c: 627b str r3, [r7, #36] ; 0x24
|
|
|
return(result);
|
|
|
8004a5e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8004a60: f443 7390 orr.w r3, r3, #288 ; 0x120
|
|
|
8004a64: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
8004a66: 68fb ldr r3, [r7, #12]
|
|
|
8004a68: 681b ldr r3, [r3, #0]
|
|
|
8004a6a: 461a mov r2, r3
|
|
|
8004a6c: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
|
8004a6e: 637b str r3, [r7, #52] ; 0x34
|
|
|
8004a70: 633a str r2, [r7, #48] ; 0x30
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004a72: 6b39 ldr r1, [r7, #48] ; 0x30
|
|
|
8004a74: 6b7a ldr r2, [r7, #52] ; 0x34
|
|
|
8004a76: e841 2300 strex r3, r2, [r1]
|
|
|
8004a7a: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
return(result);
|
|
|
8004a7c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
|
8004a7e: 2b00 cmp r3, #0
|
|
|
8004a80: d1e6 bne.n 8004a50 <UART_Start_Receive_IT+0x110>
|
|
|
8004a82: e018 b.n 8004ab6 <UART_Start_Receive_IT+0x176>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
|
|
|
8004a84: 68fb ldr r3, [r7, #12]
|
|
|
8004a86: 681b ldr r3, [r3, #0]
|
|
|
8004a88: 617b str r3, [r7, #20]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004a8a: 697b ldr r3, [r7, #20]
|
|
|
8004a8c: e853 3f00 ldrex r3, [r3]
|
|
|
8004a90: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
8004a92: 693b ldr r3, [r7, #16]
|
|
|
8004a94: f043 0320 orr.w r3, r3, #32
|
|
|
8004a98: 653b str r3, [r7, #80] ; 0x50
|
|
|
8004a9a: 68fb ldr r3, [r7, #12]
|
|
|
8004a9c: 681b ldr r3, [r3, #0]
|
|
|
8004a9e: 461a mov r2, r3
|
|
|
8004aa0: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
|
8004aa2: 623b str r3, [r7, #32]
|
|
|
8004aa4: 61fa str r2, [r7, #28]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004aa6: 69f9 ldr r1, [r7, #28]
|
|
|
8004aa8: 6a3a ldr r2, [r7, #32]
|
|
|
8004aaa: e841 2300 strex r3, r2, [r1]
|
|
|
8004aae: 61bb str r3, [r7, #24]
|
|
|
return(result);
|
|
|
8004ab0: 69bb ldr r3, [r7, #24]
|
|
|
8004ab2: 2b00 cmp r3, #0
|
|
|
8004ab4: d1e6 bne.n 8004a84 <UART_Start_Receive_IT+0x144>
|
|
|
}
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
return HAL_OK;
|
|
|
8004ab6: 2300 movs r3, #0
|
|
|
}
|
|
|
8004ab8: 4618 mov r0, r3
|
|
|
8004aba: 375c adds r7, #92 ; 0x5c
|
|
|
8004abc: 46bd mov sp, r7
|
|
|
8004abe: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8004ac2: 4770 bx lr
|
|
|
8004ac4: 08004f49 .word 0x08004f49
|
|
|
8004ac8: 08004d8d .word 0x08004d8d
|
|
|
|
|
|
08004acc <UART_EndRxTransfer>:
|
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004acc: b480 push {r7}
|
|
|
8004ace: b095 sub sp, #84 ; 0x54
|
|
|
8004ad0: af00 add r7, sp, #0
|
|
|
8004ad2: 6078 str r0, [r7, #4]
|
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
|
8004ad4: 687b ldr r3, [r7, #4]
|
|
|
8004ad6: 681b ldr r3, [r3, #0]
|
|
|
8004ad8: 637b str r3, [r7, #52] ; 0x34
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004ada: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
8004adc: e853 3f00 ldrex r3, [r3]
|
|
|
8004ae0: 633b str r3, [r7, #48] ; 0x30
|
|
|
return(result);
|
|
|
8004ae2: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
|
8004ae4: f423 7390 bic.w r3, r3, #288 ; 0x120
|
|
|
8004ae8: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
8004aea: 687b ldr r3, [r7, #4]
|
|
|
8004aec: 681b ldr r3, [r3, #0]
|
|
|
8004aee: 461a mov r2, r3
|
|
|
8004af0: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
|
8004af2: 643b str r3, [r7, #64] ; 0x40
|
|
|
8004af4: 63fa str r2, [r7, #60] ; 0x3c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004af6: 6bf9 ldr r1, [r7, #60] ; 0x3c
|
|
|
8004af8: 6c3a ldr r2, [r7, #64] ; 0x40
|
|
|
8004afa: e841 2300 strex r3, r2, [r1]
|
|
|
8004afe: 63bb str r3, [r7, #56] ; 0x38
|
|
|
return(result);
|
|
|
8004b00: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8004b02: 2b00 cmp r3, #0
|
|
|
8004b04: d1e6 bne.n 8004ad4 <UART_EndRxTransfer+0x8>
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
8004b06: 687b ldr r3, [r7, #4]
|
|
|
8004b08: 681b ldr r3, [r3, #0]
|
|
|
8004b0a: 3308 adds r3, #8
|
|
|
8004b0c: 623b str r3, [r7, #32]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004b0e: 6a3b ldr r3, [r7, #32]
|
|
|
8004b10: e853 3f00 ldrex r3, [r3]
|
|
|
8004b14: 61fb str r3, [r7, #28]
|
|
|
return(result);
|
|
|
8004b16: 69fb ldr r3, [r7, #28]
|
|
|
8004b18: f023 0301 bic.w r3, r3, #1
|
|
|
8004b1c: 64bb str r3, [r7, #72] ; 0x48
|
|
|
8004b1e: 687b ldr r3, [r7, #4]
|
|
|
8004b20: 681b ldr r3, [r3, #0]
|
|
|
8004b22: 3308 adds r3, #8
|
|
|
8004b24: 6cba ldr r2, [r7, #72] ; 0x48
|
|
|
8004b26: 62fa str r2, [r7, #44] ; 0x2c
|
|
|
8004b28: 62bb str r3, [r7, #40] ; 0x28
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004b2a: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
|
8004b2c: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
|
8004b2e: e841 2300 strex r3, r2, [r1]
|
|
|
8004b32: 627b str r3, [r7, #36] ; 0x24
|
|
|
return(result);
|
|
|
8004b34: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8004b36: 2b00 cmp r3, #0
|
|
|
8004b38: d1e5 bne.n 8004b06 <UART_EndRxTransfer+0x3a>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
|
8004b3a: 687b ldr r3, [r7, #4]
|
|
|
8004b3c: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8004b3e: 2b01 cmp r3, #1
|
|
|
8004b40: d118 bne.n 8004b74 <UART_EndRxTransfer+0xa8>
|
|
|
{
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
|
8004b42: 687b ldr r3, [r7, #4]
|
|
|
8004b44: 681b ldr r3, [r3, #0]
|
|
|
8004b46: 60fb str r3, [r7, #12]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004b48: 68fb ldr r3, [r7, #12]
|
|
|
8004b4a: e853 3f00 ldrex r3, [r3]
|
|
|
8004b4e: 60bb str r3, [r7, #8]
|
|
|
return(result);
|
|
|
8004b50: 68bb ldr r3, [r7, #8]
|
|
|
8004b52: f023 0310 bic.w r3, r3, #16
|
|
|
8004b56: 647b str r3, [r7, #68] ; 0x44
|
|
|
8004b58: 687b ldr r3, [r7, #4]
|
|
|
8004b5a: 681b ldr r3, [r3, #0]
|
|
|
8004b5c: 461a mov r2, r3
|
|
|
8004b5e: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
|
8004b60: 61bb str r3, [r7, #24]
|
|
|
8004b62: 617a str r2, [r7, #20]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004b64: 6979 ldr r1, [r7, #20]
|
|
|
8004b66: 69ba ldr r2, [r7, #24]
|
|
|
8004b68: e841 2300 strex r3, r2, [r1]
|
|
|
8004b6c: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
8004b6e: 693b ldr r3, [r7, #16]
|
|
|
8004b70: 2b00 cmp r3, #0
|
|
|
8004b72: d1e6 bne.n 8004b42 <UART_EndRxTransfer+0x76>
|
|
|
}
|
|
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8004b74: 687b ldr r3, [r7, #4]
|
|
|
8004b76: 2220 movs r2, #32
|
|
|
8004b78: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
8004b7c: 687b ldr r3, [r7, #4]
|
|
|
8004b7e: 2200 movs r2, #0
|
|
|
8004b80: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
|
|
/* Reset RxIsr function pointer */
|
|
|
huart->RxISR = NULL;
|
|
|
8004b82: 687b ldr r3, [r7, #4]
|
|
|
8004b84: 2200 movs r2, #0
|
|
|
8004b86: 669a str r2, [r3, #104] ; 0x68
|
|
|
}
|
|
|
8004b88: bf00 nop
|
|
|
8004b8a: 3754 adds r7, #84 ; 0x54
|
|
|
8004b8c: 46bd mov sp, r7
|
|
|
8004b8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8004b92: 4770 bx lr
|
|
|
|
|
|
08004b94 <UART_DMAAbortOnError>:
|
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
|
* @param hdma DMA handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
|
{
|
|
|
8004b94: b580 push {r7, lr}
|
|
|
8004b96: b084 sub sp, #16
|
|
|
8004b98: af00 add r7, sp, #0
|
|
|
8004b9a: 6078 str r0, [r7, #4]
|
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
|
8004b9c: 687b ldr r3, [r7, #4]
|
|
|
8004b9e: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
|
8004ba0: 60fb str r3, [r7, #12]
|
|
|
huart->RxXferCount = 0U;
|
|
|
8004ba2: 68fb ldr r3, [r7, #12]
|
|
|
8004ba4: 2200 movs r2, #0
|
|
|
8004ba6: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
huart->TxXferCount = 0U;
|
|
|
8004baa: 68fb ldr r3, [r7, #12]
|
|
|
8004bac: 2200 movs r2, #0
|
|
|
8004bae: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered error callback*/
|
|
|
huart->ErrorCallback(huart);
|
|
|
#else
|
|
|
/*Call legacy weak error callback*/
|
|
|
HAL_UART_ErrorCallback(huart);
|
|
|
8004bb2: 68f8 ldr r0, [r7, #12]
|
|
|
8004bb4: f7ff faae bl 8004114 <HAL_UART_ErrorCallback>
|
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
}
|
|
|
8004bb8: bf00 nop
|
|
|
8004bba: 3710 adds r7, #16
|
|
|
8004bbc: 46bd mov sp, r7
|
|
|
8004bbe: bd80 pop {r7, pc}
|
|
|
|
|
|
08004bc0 <UART_TxISR_8BIT>:
|
|
|
* interruptions have been enabled by HAL_UART_Transmit_IT().
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004bc0: b480 push {r7}
|
|
|
8004bc2: b08f sub sp, #60 ; 0x3c
|
|
|
8004bc4: af00 add r7, sp, #0
|
|
|
8004bc6: 6078 str r0, [r7, #4]
|
|
|
/* Check that a Tx process is ongoing */
|
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
|
8004bc8: 687b ldr r3, [r7, #4]
|
|
|
8004bca: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
|
8004bcc: 2b21 cmp r3, #33 ; 0x21
|
|
|
8004bce: d14d bne.n 8004c6c <UART_TxISR_8BIT+0xac>
|
|
|
{
|
|
|
if (huart->TxXferCount == 0U)
|
|
|
8004bd0: 687b ldr r3, [r7, #4]
|
|
|
8004bd2: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
|
8004bd6: b29b uxth r3, r3
|
|
|
8004bd8: 2b00 cmp r3, #0
|
|
|
8004bda: d132 bne.n 8004c42 <UART_TxISR_8BIT+0x82>
|
|
|
{
|
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|
|
8004bdc: 687b ldr r3, [r7, #4]
|
|
|
8004bde: 681b ldr r3, [r3, #0]
|
|
|
8004be0: 623b str r3, [r7, #32]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004be2: 6a3b ldr r3, [r7, #32]
|
|
|
8004be4: e853 3f00 ldrex r3, [r3]
|
|
|
8004be8: 61fb str r3, [r7, #28]
|
|
|
return(result);
|
|
|
8004bea: 69fb ldr r3, [r7, #28]
|
|
|
8004bec: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
|
8004bf0: 637b str r3, [r7, #52] ; 0x34
|
|
|
8004bf2: 687b ldr r3, [r7, #4]
|
|
|
8004bf4: 681b ldr r3, [r3, #0]
|
|
|
8004bf6: 461a mov r2, r3
|
|
|
8004bf8: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
8004bfa: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
8004bfc: 62ba str r2, [r7, #40] ; 0x28
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004bfe: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
|
8004c00: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
|
8004c02: e841 2300 strex r3, r2, [r1]
|
|
|
8004c06: 627b str r3, [r7, #36] ; 0x24
|
|
|
return(result);
|
|
|
8004c08: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8004c0a: 2b00 cmp r3, #0
|
|
|
8004c0c: d1e6 bne.n 8004bdc <UART_TxISR_8BIT+0x1c>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
|
8004c0e: 687b ldr r3, [r7, #4]
|
|
|
8004c10: 681b ldr r3, [r3, #0]
|
|
|
8004c12: 60fb str r3, [r7, #12]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004c14: 68fb ldr r3, [r7, #12]
|
|
|
8004c16: e853 3f00 ldrex r3, [r3]
|
|
|
8004c1a: 60bb str r3, [r7, #8]
|
|
|
return(result);
|
|
|
8004c1c: 68bb ldr r3, [r7, #8]
|
|
|
8004c1e: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
|
8004c22: 633b str r3, [r7, #48] ; 0x30
|
|
|
8004c24: 687b ldr r3, [r7, #4]
|
|
|
8004c26: 681b ldr r3, [r3, #0]
|
|
|
8004c28: 461a mov r2, r3
|
|
|
8004c2a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
|
8004c2c: 61bb str r3, [r7, #24]
|
|
|
8004c2e: 617a str r2, [r7, #20]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004c30: 6979 ldr r1, [r7, #20]
|
|
|
8004c32: 69ba ldr r2, [r7, #24]
|
|
|
8004c34: e841 2300 strex r3, r2, [r1]
|
|
|
8004c38: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
8004c3a: 693b ldr r3, [r7, #16]
|
|
|
8004c3c: 2b00 cmp r3, #0
|
|
|
8004c3e: d1e6 bne.n 8004c0e <UART_TxISR_8BIT+0x4e>
|
|
|
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
|
|
|
huart->pTxBuffPtr++;
|
|
|
huart->TxXferCount--;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
8004c40: e014 b.n 8004c6c <UART_TxISR_8BIT+0xac>
|
|
|
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
|
|
|
8004c42: 687b ldr r3, [r7, #4]
|
|
|
8004c44: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8004c46: 781a ldrb r2, [r3, #0]
|
|
|
8004c48: 687b ldr r3, [r7, #4]
|
|
|
8004c4a: 681b ldr r3, [r3, #0]
|
|
|
8004c4c: b292 uxth r2, r2
|
|
|
8004c4e: 851a strh r2, [r3, #40] ; 0x28
|
|
|
huart->pTxBuffPtr++;
|
|
|
8004c50: 687b ldr r3, [r7, #4]
|
|
|
8004c52: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8004c54: 1c5a adds r2, r3, #1
|
|
|
8004c56: 687b ldr r3, [r7, #4]
|
|
|
8004c58: 64da str r2, [r3, #76] ; 0x4c
|
|
|
huart->TxXferCount--;
|
|
|
8004c5a: 687b ldr r3, [r7, #4]
|
|
|
8004c5c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
|
8004c60: b29b uxth r3, r3
|
|
|
8004c62: 3b01 subs r3, #1
|
|
|
8004c64: b29a uxth r2, r3
|
|
|
8004c66: 687b ldr r3, [r7, #4]
|
|
|
8004c68: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
}
|
|
|
8004c6c: bf00 nop
|
|
|
8004c6e: 373c adds r7, #60 ; 0x3c
|
|
|
8004c70: 46bd mov sp, r7
|
|
|
8004c72: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8004c76: 4770 bx lr
|
|
|
|
|
|
08004c78 <UART_TxISR_16BIT>:
|
|
|
* interruptions have been enabled by HAL_UART_Transmit_IT().
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004c78: b480 push {r7}
|
|
|
8004c7a: b091 sub sp, #68 ; 0x44
|
|
|
8004c7c: af00 add r7, sp, #0
|
|
|
8004c7e: 6078 str r0, [r7, #4]
|
|
|
const uint16_t *tmp;
|
|
|
|
|
|
/* Check that a Tx process is ongoing */
|
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
|
8004c80: 687b ldr r3, [r7, #4]
|
|
|
8004c82: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
|
8004c84: 2b21 cmp r3, #33 ; 0x21
|
|
|
8004c86: d151 bne.n 8004d2c <UART_TxISR_16BIT+0xb4>
|
|
|
{
|
|
|
if (huart->TxXferCount == 0U)
|
|
|
8004c88: 687b ldr r3, [r7, #4]
|
|
|
8004c8a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
|
8004c8e: b29b uxth r3, r3
|
|
|
8004c90: 2b00 cmp r3, #0
|
|
|
8004c92: d132 bne.n 8004cfa <UART_TxISR_16BIT+0x82>
|
|
|
{
|
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|
|
8004c94: 687b ldr r3, [r7, #4]
|
|
|
8004c96: 681b ldr r3, [r3, #0]
|
|
|
8004c98: 627b str r3, [r7, #36] ; 0x24
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004c9a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8004c9c: e853 3f00 ldrex r3, [r3]
|
|
|
8004ca0: 623b str r3, [r7, #32]
|
|
|
return(result);
|
|
|
8004ca2: 6a3b ldr r3, [r7, #32]
|
|
|
8004ca4: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
|
8004ca8: 63bb str r3, [r7, #56] ; 0x38
|
|
|
8004caa: 687b ldr r3, [r7, #4]
|
|
|
8004cac: 681b ldr r3, [r3, #0]
|
|
|
8004cae: 461a mov r2, r3
|
|
|
8004cb0: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8004cb2: 633b str r3, [r7, #48] ; 0x30
|
|
|
8004cb4: 62fa str r2, [r7, #44] ; 0x2c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004cb6: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
|
8004cb8: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
|
8004cba: e841 2300 strex r3, r2, [r1]
|
|
|
8004cbe: 62bb str r3, [r7, #40] ; 0x28
|
|
|
return(result);
|
|
|
8004cc0: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
8004cc2: 2b00 cmp r3, #0
|
|
|
8004cc4: d1e6 bne.n 8004c94 <UART_TxISR_16BIT+0x1c>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
|
8004cc6: 687b ldr r3, [r7, #4]
|
|
|
8004cc8: 681b ldr r3, [r3, #0]
|
|
|
8004cca: 613b str r3, [r7, #16]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004ccc: 693b ldr r3, [r7, #16]
|
|
|
8004cce: e853 3f00 ldrex r3, [r3]
|
|
|
8004cd2: 60fb str r3, [r7, #12]
|
|
|
return(result);
|
|
|
8004cd4: 68fb ldr r3, [r7, #12]
|
|
|
8004cd6: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
|
8004cda: 637b str r3, [r7, #52] ; 0x34
|
|
|
8004cdc: 687b ldr r3, [r7, #4]
|
|
|
8004cde: 681b ldr r3, [r3, #0]
|
|
|
8004ce0: 461a mov r2, r3
|
|
|
8004ce2: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
8004ce4: 61fb str r3, [r7, #28]
|
|
|
8004ce6: 61ba str r2, [r7, #24]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004ce8: 69b9 ldr r1, [r7, #24]
|
|
|
8004cea: 69fa ldr r2, [r7, #28]
|
|
|
8004cec: e841 2300 strex r3, r2, [r1]
|
|
|
8004cf0: 617b str r3, [r7, #20]
|
|
|
return(result);
|
|
|
8004cf2: 697b ldr r3, [r7, #20]
|
|
|
8004cf4: 2b00 cmp r3, #0
|
|
|
8004cf6: d1e6 bne.n 8004cc6 <UART_TxISR_16BIT+0x4e>
|
|
|
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
|
|
|
huart->pTxBuffPtr += 2U;
|
|
|
huart->TxXferCount--;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
8004cf8: e018 b.n 8004d2c <UART_TxISR_16BIT+0xb4>
|
|
|
tmp = (const uint16_t *) huart->pTxBuffPtr;
|
|
|
8004cfa: 687b ldr r3, [r7, #4]
|
|
|
8004cfc: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8004cfe: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
|
|
|
8004d00: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
|
8004d02: 881a ldrh r2, [r3, #0]
|
|
|
8004d04: 687b ldr r3, [r7, #4]
|
|
|
8004d06: 681b ldr r3, [r3, #0]
|
|
|
8004d08: f3c2 0208 ubfx r2, r2, #0, #9
|
|
|
8004d0c: b292 uxth r2, r2
|
|
|
8004d0e: 851a strh r2, [r3, #40] ; 0x28
|
|
|
huart->pTxBuffPtr += 2U;
|
|
|
8004d10: 687b ldr r3, [r7, #4]
|
|
|
8004d12: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
|
8004d14: 1c9a adds r2, r3, #2
|
|
|
8004d16: 687b ldr r3, [r7, #4]
|
|
|
8004d18: 64da str r2, [r3, #76] ; 0x4c
|
|
|
huart->TxXferCount--;
|
|
|
8004d1a: 687b ldr r3, [r7, #4]
|
|
|
8004d1c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
|
8004d20: b29b uxth r3, r3
|
|
|
8004d22: 3b01 subs r3, #1
|
|
|
8004d24: b29a uxth r2, r3
|
|
|
8004d26: 687b ldr r3, [r7, #4]
|
|
|
8004d28: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
}
|
|
|
8004d2c: bf00 nop
|
|
|
8004d2e: 3744 adds r7, #68 ; 0x44
|
|
|
8004d30: 46bd mov sp, r7
|
|
|
8004d32: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8004d36: 4770 bx lr
|
|
|
|
|
|
08004d38 <UART_EndTransmit_IT>:
|
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
|
* the configuration information for the specified UART module.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004d38: b580 push {r7, lr}
|
|
|
8004d3a: b088 sub sp, #32
|
|
|
8004d3c: af00 add r7, sp, #0
|
|
|
8004d3e: 6078 str r0, [r7, #4]
|
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
|
8004d40: 687b ldr r3, [r7, #4]
|
|
|
8004d42: 681b ldr r3, [r3, #0]
|
|
|
8004d44: 60fb str r3, [r7, #12]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004d46: 68fb ldr r3, [r7, #12]
|
|
|
8004d48: e853 3f00 ldrex r3, [r3]
|
|
|
8004d4c: 60bb str r3, [r7, #8]
|
|
|
return(result);
|
|
|
8004d4e: 68bb ldr r3, [r7, #8]
|
|
|
8004d50: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
|
8004d54: 61fb str r3, [r7, #28]
|
|
|
8004d56: 687b ldr r3, [r7, #4]
|
|
|
8004d58: 681b ldr r3, [r3, #0]
|
|
|
8004d5a: 461a mov r2, r3
|
|
|
8004d5c: 69fb ldr r3, [r7, #28]
|
|
|
8004d5e: 61bb str r3, [r7, #24]
|
|
|
8004d60: 617a str r2, [r7, #20]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004d62: 6979 ldr r1, [r7, #20]
|
|
|
8004d64: 69ba ldr r2, [r7, #24]
|
|
|
8004d66: e841 2300 strex r3, r2, [r1]
|
|
|
8004d6a: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
8004d6c: 693b ldr r3, [r7, #16]
|
|
|
8004d6e: 2b00 cmp r3, #0
|
|
|
8004d70: d1e6 bne.n 8004d40 <UART_EndTransmit_IT+0x8>
|
|
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
8004d72: 687b ldr r3, [r7, #4]
|
|
|
8004d74: 2220 movs r2, #32
|
|
|
8004d76: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
|
|
/* Cleat TxISR function pointer */
|
|
|
huart->TxISR = NULL;
|
|
|
8004d78: 687b ldr r3, [r7, #4]
|
|
|
8004d7a: 2200 movs r2, #0
|
|
|
8004d7c: 66da str r2, [r3, #108] ; 0x6c
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered Tx complete callback*/
|
|
|
huart->TxCpltCallback(huart);
|
|
|
#else
|
|
|
/*Call legacy weak Tx complete callback*/
|
|
|
HAL_UART_TxCpltCallback(huart);
|
|
|
8004d7e: 6878 ldr r0, [r7, #4]
|
|
|
8004d80: f7ff f9be bl 8004100 <HAL_UART_TxCpltCallback>
|
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
}
|
|
|
8004d84: bf00 nop
|
|
|
8004d86: 3720 adds r7, #32
|
|
|
8004d88: 46bd mov sp, r7
|
|
|
8004d8a: bd80 pop {r7, pc}
|
|
|
|
|
|
08004d8c <UART_RxISR_8BIT>:
|
|
|
* @brief RX interrupt handler for 7 or 8 bits data word length .
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004d8c: b580 push {r7, lr}
|
|
|
8004d8e: b09c sub sp, #112 ; 0x70
|
|
|
8004d90: af00 add r7, sp, #0
|
|
|
8004d92: 6078 str r0, [r7, #4]
|
|
|
uint16_t uhMask = huart->Mask;
|
|
|
8004d94: 687b ldr r3, [r7, #4]
|
|
|
8004d96: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
|
|
|
8004d9a: f8a7 306e strh.w r3, [r7, #110] ; 0x6e
|
|
|
uint16_t uhdata;
|
|
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
|
8004d9e: 687b ldr r3, [r7, #4]
|
|
|
8004da0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
|
8004da4: 2b22 cmp r3, #34 ; 0x22
|
|
|
8004da6: f040 80be bne.w 8004f26 <UART_RxISR_8BIT+0x19a>
|
|
|
{
|
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
|
8004daa: 687b ldr r3, [r7, #4]
|
|
|
8004dac: 681b ldr r3, [r3, #0]
|
|
|
8004dae: 8c9b ldrh r3, [r3, #36] ; 0x24
|
|
|
8004db0: f8a7 306c strh.w r3, [r7, #108] ; 0x6c
|
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
|
8004db4: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c
|
|
|
8004db8: b2d9 uxtb r1, r3
|
|
|
8004dba: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e
|
|
|
8004dbe: b2da uxtb r2, r3
|
|
|
8004dc0: 687b ldr r3, [r7, #4]
|
|
|
8004dc2: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
8004dc4: 400a ands r2, r1
|
|
|
8004dc6: b2d2 uxtb r2, r2
|
|
|
8004dc8: 701a strb r2, [r3, #0]
|
|
|
huart->pRxBuffPtr++;
|
|
|
8004dca: 687b ldr r3, [r7, #4]
|
|
|
8004dcc: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
8004dce: 1c5a adds r2, r3, #1
|
|
|
8004dd0: 687b ldr r3, [r7, #4]
|
|
|
8004dd2: 655a str r2, [r3, #84] ; 0x54
|
|
|
huart->RxXferCount--;
|
|
|
8004dd4: 687b ldr r3, [r7, #4]
|
|
|
8004dd6: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8004dda: b29b uxth r3, r3
|
|
|
8004ddc: 3b01 subs r3, #1
|
|
|
8004dde: b29a uxth r2, r3
|
|
|
8004de0: 687b ldr r3, [r7, #4]
|
|
|
8004de2: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
|
8004de6: 687b ldr r3, [r7, #4]
|
|
|
8004de8: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8004dec: b29b uxth r3, r3
|
|
|
8004dee: 2b00 cmp r3, #0
|
|
|
8004df0: f040 80a3 bne.w 8004f3a <UART_RxISR_8BIT+0x1ae>
|
|
|
{
|
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
|
8004df4: 687b ldr r3, [r7, #4]
|
|
|
8004df6: 681b ldr r3, [r3, #0]
|
|
|
8004df8: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004dfa: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
|
8004dfc: e853 3f00 ldrex r3, [r3]
|
|
|
8004e00: 64bb str r3, [r7, #72] ; 0x48
|
|
|
return(result);
|
|
|
8004e02: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
|
8004e04: f423 7390 bic.w r3, r3, #288 ; 0x120
|
|
|
8004e08: 66bb str r3, [r7, #104] ; 0x68
|
|
|
8004e0a: 687b ldr r3, [r7, #4]
|
|
|
8004e0c: 681b ldr r3, [r3, #0]
|
|
|
8004e0e: 461a mov r2, r3
|
|
|
8004e10: 6ebb ldr r3, [r7, #104] ; 0x68
|
|
|
8004e12: 65bb str r3, [r7, #88] ; 0x58
|
|
|
8004e14: 657a str r2, [r7, #84] ; 0x54
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004e16: 6d79 ldr r1, [r7, #84] ; 0x54
|
|
|
8004e18: 6dba ldr r2, [r7, #88] ; 0x58
|
|
|
8004e1a: e841 2300 strex r3, r2, [r1]
|
|
|
8004e1e: 653b str r3, [r7, #80] ; 0x50
|
|
|
return(result);
|
|
|
8004e20: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
|
8004e22: 2b00 cmp r3, #0
|
|
|
8004e24: d1e6 bne.n 8004df4 <UART_RxISR_8BIT+0x68>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
8004e26: 687b ldr r3, [r7, #4]
|
|
|
8004e28: 681b ldr r3, [r3, #0]
|
|
|
8004e2a: 3308 adds r3, #8
|
|
|
8004e2c: 63bb str r3, [r7, #56] ; 0x38
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004e2e: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8004e30: e853 3f00 ldrex r3, [r3]
|
|
|
8004e34: 637b str r3, [r7, #52] ; 0x34
|
|
|
return(result);
|
|
|
8004e36: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
8004e38: f023 0301 bic.w r3, r3, #1
|
|
|
8004e3c: 667b str r3, [r7, #100] ; 0x64
|
|
|
8004e3e: 687b ldr r3, [r7, #4]
|
|
|
8004e40: 681b ldr r3, [r3, #0]
|
|
|
8004e42: 3308 adds r3, #8
|
|
|
8004e44: 6e7a ldr r2, [r7, #100] ; 0x64
|
|
|
8004e46: 647a str r2, [r7, #68] ; 0x44
|
|
|
8004e48: 643b str r3, [r7, #64] ; 0x40
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004e4a: 6c39 ldr r1, [r7, #64] ; 0x40
|
|
|
8004e4c: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
|
8004e4e: e841 2300 strex r3, r2, [r1]
|
|
|
8004e52: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
return(result);
|
|
|
8004e54: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
|
8004e56: 2b00 cmp r3, #0
|
|
|
8004e58: d1e5 bne.n 8004e26 <UART_RxISR_8BIT+0x9a>
|
|
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8004e5a: 687b ldr r3, [r7, #4]
|
|
|
8004e5c: 2220 movs r2, #32
|
|
|
8004e5e: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
|
|
|
/* Clear RxISR function pointer */
|
|
|
huart->RxISR = NULL;
|
|
|
8004e62: 687b ldr r3, [r7, #4]
|
|
|
8004e64: 2200 movs r2, #0
|
|
|
8004e66: 669a str r2, [r3, #104] ; 0x68
|
|
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
|
8004e68: 687b ldr r3, [r7, #4]
|
|
|
8004e6a: 2200 movs r2, #0
|
|
|
8004e6c: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
|
8004e6e: 687b ldr r3, [r7, #4]
|
|
|
8004e70: 681b ldr r3, [r3, #0]
|
|
|
8004e72: 4a34 ldr r2, [pc, #208] ; (8004f44 <UART_RxISR_8BIT+0x1b8>)
|
|
|
8004e74: 4293 cmp r3, r2
|
|
|
8004e76: d01f beq.n 8004eb8 <UART_RxISR_8BIT+0x12c>
|
|
|
{
|
|
|
/* Check that USART RTOEN bit is set */
|
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
|
8004e78: 687b ldr r3, [r7, #4]
|
|
|
8004e7a: 681b ldr r3, [r3, #0]
|
|
|
8004e7c: 685b ldr r3, [r3, #4]
|
|
|
8004e7e: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
|
8004e82: 2b00 cmp r3, #0
|
|
|
8004e84: d018 beq.n 8004eb8 <UART_RxISR_8BIT+0x12c>
|
|
|
{
|
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
|
8004e86: 687b ldr r3, [r7, #4]
|
|
|
8004e88: 681b ldr r3, [r3, #0]
|
|
|
8004e8a: 627b str r3, [r7, #36] ; 0x24
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004e8c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8004e8e: e853 3f00 ldrex r3, [r3]
|
|
|
8004e92: 623b str r3, [r7, #32]
|
|
|
return(result);
|
|
|
8004e94: 6a3b ldr r3, [r7, #32]
|
|
|
8004e96: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
|
|
|
8004e9a: 663b str r3, [r7, #96] ; 0x60
|
|
|
8004e9c: 687b ldr r3, [r7, #4]
|
|
|
8004e9e: 681b ldr r3, [r3, #0]
|
|
|
8004ea0: 461a mov r2, r3
|
|
|
8004ea2: 6e3b ldr r3, [r7, #96] ; 0x60
|
|
|
8004ea4: 633b str r3, [r7, #48] ; 0x30
|
|
|
8004ea6: 62fa str r2, [r7, #44] ; 0x2c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004ea8: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
|
8004eaa: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
|
8004eac: e841 2300 strex r3, r2, [r1]
|
|
|
8004eb0: 62bb str r3, [r7, #40] ; 0x28
|
|
|
return(result);
|
|
|
8004eb2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
8004eb4: 2b00 cmp r3, #0
|
|
|
8004eb6: d1e6 bne.n 8004e86 <UART_RxISR_8BIT+0xfa>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Check current reception Mode :
|
|
|
If Reception till IDLE event has been selected : */
|
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
|
8004eb8: 687b ldr r3, [r7, #4]
|
|
|
8004eba: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8004ebc: 2b01 cmp r3, #1
|
|
|
8004ebe: d12e bne.n 8004f1e <UART_RxISR_8BIT+0x192>
|
|
|
{
|
|
|
/* Set reception type to Standard */
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
8004ec0: 687b ldr r3, [r7, #4]
|
|
|
8004ec2: 2200 movs r2, #0
|
|
|
8004ec4: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
|
|
/* Disable IDLE interrupt */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
|
8004ec6: 687b ldr r3, [r7, #4]
|
|
|
8004ec8: 681b ldr r3, [r3, #0]
|
|
|
8004eca: 613b str r3, [r7, #16]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004ecc: 693b ldr r3, [r7, #16]
|
|
|
8004ece: e853 3f00 ldrex r3, [r3]
|
|
|
8004ed2: 60fb str r3, [r7, #12]
|
|
|
return(result);
|
|
|
8004ed4: 68fb ldr r3, [r7, #12]
|
|
|
8004ed6: f023 0310 bic.w r3, r3, #16
|
|
|
8004eda: 65fb str r3, [r7, #92] ; 0x5c
|
|
|
8004edc: 687b ldr r3, [r7, #4]
|
|
|
8004ede: 681b ldr r3, [r3, #0]
|
|
|
8004ee0: 461a mov r2, r3
|
|
|
8004ee2: 6dfb ldr r3, [r7, #92] ; 0x5c
|
|
|
8004ee4: 61fb str r3, [r7, #28]
|
|
|
8004ee6: 61ba str r2, [r7, #24]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004ee8: 69b9 ldr r1, [r7, #24]
|
|
|
8004eea: 69fa ldr r2, [r7, #28]
|
|
|
8004eec: e841 2300 strex r3, r2, [r1]
|
|
|
8004ef0: 617b str r3, [r7, #20]
|
|
|
return(result);
|
|
|
8004ef2: 697b ldr r3, [r7, #20]
|
|
|
8004ef4: 2b00 cmp r3, #0
|
|
|
8004ef6: d1e6 bne.n 8004ec6 <UART_RxISR_8BIT+0x13a>
|
|
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
|
8004ef8: 687b ldr r3, [r7, #4]
|
|
|
8004efa: 681b ldr r3, [r3, #0]
|
|
|
8004efc: 69db ldr r3, [r3, #28]
|
|
|
8004efe: f003 0310 and.w r3, r3, #16
|
|
|
8004f02: 2b10 cmp r3, #16
|
|
|
8004f04: d103 bne.n 8004f0e <UART_RxISR_8BIT+0x182>
|
|
|
{
|
|
|
/* Clear IDLE Flag */
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
|
8004f06: 687b ldr r3, [r7, #4]
|
|
|
8004f08: 681b ldr r3, [r3, #0]
|
|
|
8004f0a: 2210 movs r2, #16
|
|
|
8004f0c: 621a str r2, [r3, #32]
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered Rx Event callback*/
|
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
|
#else
|
|
|
/*Call legacy weak Rx Event callback*/
|
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
|
8004f0e: 687b ldr r3, [r7, #4]
|
|
|
8004f10: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
|
|
|
8004f14: 4619 mov r1, r3
|
|
|
8004f16: 6878 ldr r0, [r7, #4]
|
|
|
8004f18: f7fb fb9a bl 8000650 <HAL_UARTEx_RxEventCallback>
|
|
|
else
|
|
|
{
|
|
|
/* Clear RXNE interrupt flag */
|
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
|
}
|
|
|
}
|
|
|
8004f1c: e00d b.n 8004f3a <UART_RxISR_8BIT+0x1ae>
|
|
|
HAL_UART_RxCpltCallback(huart);
|
|
|
8004f1e: 6878 ldr r0, [r7, #4]
|
|
|
8004f20: f7fb fb80 bl 8000624 <HAL_UART_RxCpltCallback>
|
|
|
}
|
|
|
8004f24: e009 b.n 8004f3a <UART_RxISR_8BIT+0x1ae>
|
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
|
8004f26: 687b ldr r3, [r7, #4]
|
|
|
8004f28: 681b ldr r3, [r3, #0]
|
|
|
8004f2a: 8b1b ldrh r3, [r3, #24]
|
|
|
8004f2c: b29a uxth r2, r3
|
|
|
8004f2e: 687b ldr r3, [r7, #4]
|
|
|
8004f30: 681b ldr r3, [r3, #0]
|
|
|
8004f32: f042 0208 orr.w r2, r2, #8
|
|
|
8004f36: b292 uxth r2, r2
|
|
|
8004f38: 831a strh r2, [r3, #24]
|
|
|
}
|
|
|
8004f3a: bf00 nop
|
|
|
8004f3c: 3770 adds r7, #112 ; 0x70
|
|
|
8004f3e: 46bd mov sp, r7
|
|
|
8004f40: bd80 pop {r7, pc}
|
|
|
8004f42: bf00 nop
|
|
|
8004f44: 40008000 .word 0x40008000
|
|
|
|
|
|
08004f48 <UART_RxISR_16BIT>:
|
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8004f48: b580 push {r7, lr}
|
|
|
8004f4a: b09c sub sp, #112 ; 0x70
|
|
|
8004f4c: af00 add r7, sp, #0
|
|
|
8004f4e: 6078 str r0, [r7, #4]
|
|
|
uint16_t *tmp;
|
|
|
uint16_t uhMask = huart->Mask;
|
|
|
8004f50: 687b ldr r3, [r7, #4]
|
|
|
8004f52: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
|
|
|
8004f56: f8a7 306e strh.w r3, [r7, #110] ; 0x6e
|
|
|
uint16_t uhdata;
|
|
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
|
8004f5a: 687b ldr r3, [r7, #4]
|
|
|
8004f5c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
|
8004f60: 2b22 cmp r3, #34 ; 0x22
|
|
|
8004f62: f040 80be bne.w 80050e2 <UART_RxISR_16BIT+0x19a>
|
|
|
{
|
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
|
8004f66: 687b ldr r3, [r7, #4]
|
|
|
8004f68: 681b ldr r3, [r3, #0]
|
|
|
8004f6a: 8c9b ldrh r3, [r3, #36] ; 0x24
|
|
|
8004f6c: f8a7 306c strh.w r3, [r7, #108] ; 0x6c
|
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
|
8004f70: 687b ldr r3, [r7, #4]
|
|
|
8004f72: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
8004f74: 66bb str r3, [r7, #104] ; 0x68
|
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
|
8004f76: f8b7 206c ldrh.w r2, [r7, #108] ; 0x6c
|
|
|
8004f7a: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e
|
|
|
8004f7e: 4013 ands r3, r2
|
|
|
8004f80: b29a uxth r2, r3
|
|
|
8004f82: 6ebb ldr r3, [r7, #104] ; 0x68
|
|
|
8004f84: 801a strh r2, [r3, #0]
|
|
|
huart->pRxBuffPtr += 2U;
|
|
|
8004f86: 687b ldr r3, [r7, #4]
|
|
|
8004f88: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
|
8004f8a: 1c9a adds r2, r3, #2
|
|
|
8004f8c: 687b ldr r3, [r7, #4]
|
|
|
8004f8e: 655a str r2, [r3, #84] ; 0x54
|
|
|
huart->RxXferCount--;
|
|
|
8004f90: 687b ldr r3, [r7, #4]
|
|
|
8004f92: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8004f96: b29b uxth r3, r3
|
|
|
8004f98: 3b01 subs r3, #1
|
|
|
8004f9a: b29a uxth r2, r3
|
|
|
8004f9c: 687b ldr r3, [r7, #4]
|
|
|
8004f9e: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
|
8004fa2: 687b ldr r3, [r7, #4]
|
|
|
8004fa4: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
|
8004fa8: b29b uxth r3, r3
|
|
|
8004faa: 2b00 cmp r3, #0
|
|
|
8004fac: f040 80a3 bne.w 80050f6 <UART_RxISR_16BIT+0x1ae>
|
|
|
{
|
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
|
|
|
#if defined(USART_CR1_FIFOEN)
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
|
#else
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
|
8004fb0: 687b ldr r3, [r7, #4]
|
|
|
8004fb2: 681b ldr r3, [r3, #0]
|
|
|
8004fb4: 64bb str r3, [r7, #72] ; 0x48
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004fb6: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
|
8004fb8: e853 3f00 ldrex r3, [r3]
|
|
|
8004fbc: 647b str r3, [r7, #68] ; 0x44
|
|
|
return(result);
|
|
|
8004fbe: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
|
8004fc0: f423 7390 bic.w r3, r3, #288 ; 0x120
|
|
|
8004fc4: 667b str r3, [r7, #100] ; 0x64
|
|
|
8004fc6: 687b ldr r3, [r7, #4]
|
|
|
8004fc8: 681b ldr r3, [r3, #0]
|
|
|
8004fca: 461a mov r2, r3
|
|
|
8004fcc: 6e7b ldr r3, [r7, #100] ; 0x64
|
|
|
8004fce: 657b str r3, [r7, #84] ; 0x54
|
|
|
8004fd0: 653a str r2, [r7, #80] ; 0x50
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8004fd2: 6d39 ldr r1, [r7, #80] ; 0x50
|
|
|
8004fd4: 6d7a ldr r2, [r7, #84] ; 0x54
|
|
|
8004fd6: e841 2300 strex r3, r2, [r1]
|
|
|
8004fda: 64fb str r3, [r7, #76] ; 0x4c
|
|
|
return(result);
|
|
|
8004fdc: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
|
8004fde: 2b00 cmp r3, #0
|
|
|
8004fe0: d1e6 bne.n 8004fb0 <UART_RxISR_16BIT+0x68>
|
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
8004fe2: 687b ldr r3, [r7, #4]
|
|
|
8004fe4: 681b ldr r3, [r3, #0]
|
|
|
8004fe6: 3308 adds r3, #8
|
|
|
8004fe8: 637b str r3, [r7, #52] ; 0x34
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8004fea: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
|
8004fec: e853 3f00 ldrex r3, [r3]
|
|
|
8004ff0: 633b str r3, [r7, #48] ; 0x30
|
|
|
return(result);
|
|
|
8004ff2: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
|
8004ff4: f023 0301 bic.w r3, r3, #1
|
|
|
8004ff8: 663b str r3, [r7, #96] ; 0x60
|
|
|
8004ffa: 687b ldr r3, [r7, #4]
|
|
|
8004ffc: 681b ldr r3, [r3, #0]
|
|
|
8004ffe: 3308 adds r3, #8
|
|
|
8005000: 6e3a ldr r2, [r7, #96] ; 0x60
|
|
|
8005002: 643a str r2, [r7, #64] ; 0x40
|
|
|
8005004: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8005006: 6bf9 ldr r1, [r7, #60] ; 0x3c
|
|
|
8005008: 6c3a ldr r2, [r7, #64] ; 0x40
|
|
|
800500a: e841 2300 strex r3, r2, [r1]
|
|
|
800500e: 63bb str r3, [r7, #56] ; 0x38
|
|
|
return(result);
|
|
|
8005010: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
|
8005012: 2b00 cmp r3, #0
|
|
|
8005014: d1e5 bne.n 8004fe2 <UART_RxISR_16BIT+0x9a>
|
|
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8005016: 687b ldr r3, [r7, #4]
|
|
|
8005018: 2220 movs r2, #32
|
|
|
800501a: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
|
|
|
/* Clear RxISR function pointer */
|
|
|
huart->RxISR = NULL;
|
|
|
800501e: 687b ldr r3, [r7, #4]
|
|
|
8005020: 2200 movs r2, #0
|
|
|
8005022: 669a str r2, [r3, #104] ; 0x68
|
|
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
|
8005024: 687b ldr r3, [r7, #4]
|
|
|
8005026: 2200 movs r2, #0
|
|
|
8005028: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
|
800502a: 687b ldr r3, [r7, #4]
|
|
|
800502c: 681b ldr r3, [r3, #0]
|
|
|
800502e: 4a34 ldr r2, [pc, #208] ; (8005100 <UART_RxISR_16BIT+0x1b8>)
|
|
|
8005030: 4293 cmp r3, r2
|
|
|
8005032: d01f beq.n 8005074 <UART_RxISR_16BIT+0x12c>
|
|
|
{
|
|
|
/* Check that USART RTOEN bit is set */
|
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
|
8005034: 687b ldr r3, [r7, #4]
|
|
|
8005036: 681b ldr r3, [r3, #0]
|
|
|
8005038: 685b ldr r3, [r3, #4]
|
|
|
800503a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
|
800503e: 2b00 cmp r3, #0
|
|
|
8005040: d018 beq.n 8005074 <UART_RxISR_16BIT+0x12c>
|
|
|
{
|
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
|
8005042: 687b ldr r3, [r7, #4]
|
|
|
8005044: 681b ldr r3, [r3, #0]
|
|
|
8005046: 623b str r3, [r7, #32]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8005048: 6a3b ldr r3, [r7, #32]
|
|
|
800504a: e853 3f00 ldrex r3, [r3]
|
|
|
800504e: 61fb str r3, [r7, #28]
|
|
|
return(result);
|
|
|
8005050: 69fb ldr r3, [r7, #28]
|
|
|
8005052: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
|
|
|
8005056: 65fb str r3, [r7, #92] ; 0x5c
|
|
|
8005058: 687b ldr r3, [r7, #4]
|
|
|
800505a: 681b ldr r3, [r3, #0]
|
|
|
800505c: 461a mov r2, r3
|
|
|
800505e: 6dfb ldr r3, [r7, #92] ; 0x5c
|
|
|
8005060: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
8005062: 62ba str r2, [r7, #40] ; 0x28
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8005064: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
|
8005066: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
|
8005068: e841 2300 strex r3, r2, [r1]
|
|
|
800506c: 627b str r3, [r7, #36] ; 0x24
|
|
|
return(result);
|
|
|
800506e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8005070: 2b00 cmp r3, #0
|
|
|
8005072: d1e6 bne.n 8005042 <UART_RxISR_16BIT+0xfa>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Check current reception Mode :
|
|
|
If Reception till IDLE event has been selected : */
|
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
|
8005074: 687b ldr r3, [r7, #4]
|
|
|
8005076: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8005078: 2b01 cmp r3, #1
|
|
|
800507a: d12e bne.n 80050da <UART_RxISR_16BIT+0x192>
|
|
|
{
|
|
|
/* Set reception type to Standard */
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
|
800507c: 687b ldr r3, [r7, #4]
|
|
|
800507e: 2200 movs r2, #0
|
|
|
8005080: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
|
|
/* Disable IDLE interrupt */
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
|
8005082: 687b ldr r3, [r7, #4]
|
|
|
8005084: 681b ldr r3, [r3, #0]
|
|
|
8005086: 60fb str r3, [r7, #12]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8005088: 68fb ldr r3, [r7, #12]
|
|
|
800508a: e853 3f00 ldrex r3, [r3]
|
|
|
800508e: 60bb str r3, [r7, #8]
|
|
|
return(result);
|
|
|
8005090: 68bb ldr r3, [r7, #8]
|
|
|
8005092: f023 0310 bic.w r3, r3, #16
|
|
|
8005096: 65bb str r3, [r7, #88] ; 0x58
|
|
|
8005098: 687b ldr r3, [r7, #4]
|
|
|
800509a: 681b ldr r3, [r3, #0]
|
|
|
800509c: 461a mov r2, r3
|
|
|
800509e: 6dbb ldr r3, [r7, #88] ; 0x58
|
|
|
80050a0: 61bb str r3, [r7, #24]
|
|
|
80050a2: 617a str r2, [r7, #20]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
80050a4: 6979 ldr r1, [r7, #20]
|
|
|
80050a6: 69ba ldr r2, [r7, #24]
|
|
|
80050a8: e841 2300 strex r3, r2, [r1]
|
|
|
80050ac: 613b str r3, [r7, #16]
|
|
|
return(result);
|
|
|
80050ae: 693b ldr r3, [r7, #16]
|
|
|
80050b0: 2b00 cmp r3, #0
|
|
|
80050b2: d1e6 bne.n 8005082 <UART_RxISR_16BIT+0x13a>
|
|
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
|
80050b4: 687b ldr r3, [r7, #4]
|
|
|
80050b6: 681b ldr r3, [r3, #0]
|
|
|
80050b8: 69db ldr r3, [r3, #28]
|
|
|
80050ba: f003 0310 and.w r3, r3, #16
|
|
|
80050be: 2b10 cmp r3, #16
|
|
|
80050c0: d103 bne.n 80050ca <UART_RxISR_16BIT+0x182>
|
|
|
{
|
|
|
/* Clear IDLE Flag */
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
|
80050c2: 687b ldr r3, [r7, #4]
|
|
|
80050c4: 681b ldr r3, [r3, #0]
|
|
|
80050c6: 2210 movs r2, #16
|
|
|
80050c8: 621a str r2, [r3, #32]
|
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
|
/*Call registered Rx Event callback*/
|
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
|
#else
|
|
|
/*Call legacy weak Rx Event callback*/
|
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
|
80050ca: 687b ldr r3, [r7, #4]
|
|
|
80050cc: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
|
|
|
80050d0: 4619 mov r1, r3
|
|
|
80050d2: 6878 ldr r0, [r7, #4]
|
|
|
80050d4: f7fb fabc bl 8000650 <HAL_UARTEx_RxEventCallback>
|
|
|
else
|
|
|
{
|
|
|
/* Clear RXNE interrupt flag */
|
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
|
}
|
|
|
}
|
|
|
80050d8: e00d b.n 80050f6 <UART_RxISR_16BIT+0x1ae>
|
|
|
HAL_UART_RxCpltCallback(huart);
|
|
|
80050da: 6878 ldr r0, [r7, #4]
|
|
|
80050dc: f7fb faa2 bl 8000624 <HAL_UART_RxCpltCallback>
|
|
|
}
|
|
|
80050e0: e009 b.n 80050f6 <UART_RxISR_16BIT+0x1ae>
|
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
|
80050e2: 687b ldr r3, [r7, #4]
|
|
|
80050e4: 681b ldr r3, [r3, #0]
|
|
|
80050e6: 8b1b ldrh r3, [r3, #24]
|
|
|
80050e8: b29a uxth r2, r3
|
|
|
80050ea: 687b ldr r3, [r7, #4]
|
|
|
80050ec: 681b ldr r3, [r3, #0]
|
|
|
80050ee: f042 0208 orr.w r2, r2, #8
|
|
|
80050f2: b292 uxth r2, r2
|
|
|
80050f4: 831a strh r2, [r3, #24]
|
|
|
}
|
|
|
80050f6: bf00 nop
|
|
|
80050f8: 3770 adds r7, #112 ; 0x70
|
|
|
80050fa: 46bd mov sp, r7
|
|
|
80050fc: bd80 pop {r7, pc}
|
|
|
80050fe: bf00 nop
|
|
|
8005100: 40008000 .word 0x40008000
|
|
|
|
|
|
08005104 <HAL_UARTEx_WakeupCallback>:
|
|
|
* @brief UART wakeup from Stop mode callback.
|
|
|
* @param huart UART handle.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8005104: b480 push {r7}
|
|
|
8005106: b083 sub sp, #12
|
|
|
8005108: af00 add r7, sp, #0
|
|
|
800510a: 6078 str r0, [r7, #4]
|
|
|
UNUSED(huart);
|
|
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
|
*/
|
|
|
}
|
|
|
800510c: bf00 nop
|
|
|
800510e: 370c adds r7, #12
|
|
|
8005110: 46bd mov sp, r7
|
|
|
8005112: f85d 7b04 ldr.w r7, [sp], #4
|
|
|
8005116: 4770 bx lr
|
|
|
|
|
|
08005118 <HAL_UARTEx_ReceiveToIdle_IT>:
|
|
|
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
|
|
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
|
{
|
|
|
8005118: b580 push {r7, lr}
|
|
|
800511a: b08c sub sp, #48 ; 0x30
|
|
|
800511c: af00 add r7, sp, #0
|
|
|
800511e: 60f8 str r0, [r7, #12]
|
|
|
8005120: 60b9 str r1, [r7, #8]
|
|
|
8005122: 4613 mov r3, r2
|
|
|
8005124: 80fb strh r3, [r7, #6]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8005126: 2300 movs r3, #0
|
|
|
8005128: f887 302f strb.w r3, [r7, #47] ; 0x2f
|
|
|
|
|
|
/* Check that a Rx process is not already ongoing */
|
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
|
800512c: 68fb ldr r3, [r7, #12]
|
|
|
800512e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
|
8005132: 2b20 cmp r3, #32
|
|
|
8005134: d13b bne.n 80051ae <HAL_UARTEx_ReceiveToIdle_IT+0x96>
|
|
|
{
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
|
8005136: 68bb ldr r3, [r7, #8]
|
|
|
8005138: 2b00 cmp r3, #0
|
|
|
800513a: d002 beq.n 8005142 <HAL_UARTEx_ReceiveToIdle_IT+0x2a>
|
|
|
800513c: 88fb ldrh r3, [r7, #6]
|
|
|
800513e: 2b00 cmp r3, #0
|
|
|
8005140: d101 bne.n 8005146 <HAL_UARTEx_ReceiveToIdle_IT+0x2e>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8005142: 2301 movs r3, #1
|
|
|
8005144: e034 b.n 80051b0 <HAL_UARTEx_ReceiveToIdle_IT+0x98>
|
|
|
}
|
|
|
|
|
|
/* Set Reception type to reception till IDLE Event*/
|
|
|
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
|
|
8005146: 68fb ldr r3, [r7, #12]
|
|
|
8005148: 2201 movs r2, #1
|
|
|
800514a: 661a str r2, [r3, #96] ; 0x60
|
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
|
800514c: 68fb ldr r3, [r7, #12]
|
|
|
800514e: 2200 movs r2, #0
|
|
|
8005150: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
|
|
(void)UART_Start_Receive_IT(huart, pData, Size);
|
|
|
8005152: 88fb ldrh r3, [r7, #6]
|
|
|
8005154: 461a mov r2, r3
|
|
|
8005156: 68b9 ldr r1, [r7, #8]
|
|
|
8005158: 68f8 ldr r0, [r7, #12]
|
|
|
800515a: f7ff fbf1 bl 8004940 <UART_Start_Receive_IT>
|
|
|
|
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
|
800515e: 68fb ldr r3, [r7, #12]
|
|
|
8005160: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
|
8005162: 2b01 cmp r3, #1
|
|
|
8005164: d11d bne.n 80051a2 <HAL_UARTEx_ReceiveToIdle_IT+0x8a>
|
|
|
{
|
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
|
8005166: 68fb ldr r3, [r7, #12]
|
|
|
8005168: 681b ldr r3, [r3, #0]
|
|
|
800516a: 2210 movs r2, #16
|
|
|
800516c: 621a str r2, [r3, #32]
|
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
|
800516e: 68fb ldr r3, [r7, #12]
|
|
|
8005170: 681b ldr r3, [r3, #0]
|
|
|
8005172: 61bb str r3, [r7, #24]
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
|
8005174: 69bb ldr r3, [r7, #24]
|
|
|
8005176: e853 3f00 ldrex r3, [r3]
|
|
|
800517a: 617b str r3, [r7, #20]
|
|
|
return(result);
|
|
|
800517c: 697b ldr r3, [r7, #20]
|
|
|
800517e: f043 0310 orr.w r3, r3, #16
|
|
|
8005182: 62bb str r3, [r7, #40] ; 0x28
|
|
|
8005184: 68fb ldr r3, [r7, #12]
|
|
|
8005186: 681b ldr r3, [r3, #0]
|
|
|
8005188: 461a mov r2, r3
|
|
|
800518a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
800518c: 627b str r3, [r7, #36] ; 0x24
|
|
|
800518e: 623a str r2, [r7, #32]
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
|
8005190: 6a39 ldr r1, [r7, #32]
|
|
|
8005192: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
|
8005194: e841 2300 strex r3, r2, [r1]
|
|
|
8005198: 61fb str r3, [r7, #28]
|
|
|
return(result);
|
|
|
800519a: 69fb ldr r3, [r7, #28]
|
|
|
800519c: 2b00 cmp r3, #0
|
|
|
800519e: d1e6 bne.n 800516e <HAL_UARTEx_ReceiveToIdle_IT+0x56>
|
|
|
80051a0: e002 b.n 80051a8 <HAL_UARTEx_ReceiveToIdle_IT+0x90>
|
|
|
{
|
|
|
/* In case of errors already pending when reception is started,
|
|
|
Interrupts may have already been raised and lead to reception abortion.
|
|
|
(Overrun error for instance).
|
|
|
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
|
|
status = HAL_ERROR;
|
|
|
80051a2: 2301 movs r3, #1
|
|
|
80051a4: f887 302f strb.w r3, [r7, #47] ; 0x2f
|
|
|
}
|
|
|
|
|
|
return status;
|
|
|
80051a8: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
|
|
|
80051ac: e000 b.n 80051b0 <HAL_UARTEx_ReceiveToIdle_IT+0x98>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return HAL_BUSY;
|
|
|
80051ae: 2302 movs r3, #2
|
|
|
}
|
|
|
}
|
|
|
80051b0: 4618 mov r0, r3
|
|
|
80051b2: 3730 adds r7, #48 ; 0x30
|
|
|
80051b4: 46bd mov sp, r7
|
|
|
80051b6: bd80 pop {r7, pc}
|
|
|
|
|
|
080051b8 <std>:
|
|
|
80051b8: 2300 movs r3, #0
|
|
|
80051ba: b510 push {r4, lr}
|
|
|
80051bc: 4604 mov r4, r0
|
|
|
80051be: e9c0 3300 strd r3, r3, [r0]
|
|
|
80051c2: e9c0 3304 strd r3, r3, [r0, #16]
|
|
|
80051c6: 6083 str r3, [r0, #8]
|
|
|
80051c8: 8181 strh r1, [r0, #12]
|
|
|
80051ca: 6643 str r3, [r0, #100] ; 0x64
|
|
|
80051cc: 81c2 strh r2, [r0, #14]
|
|
|
80051ce: 6183 str r3, [r0, #24]
|
|
|
80051d0: 4619 mov r1, r3
|
|
|
80051d2: 2208 movs r2, #8
|
|
|
80051d4: 305c adds r0, #92 ; 0x5c
|
|
|
80051d6: f000 f9e5 bl 80055a4 <memset>
|
|
|
80051da: 4b0d ldr r3, [pc, #52] ; (8005210 <std+0x58>)
|
|
|
80051dc: 6263 str r3, [r4, #36] ; 0x24
|
|
|
80051de: 4b0d ldr r3, [pc, #52] ; (8005214 <std+0x5c>)
|
|
|
80051e0: 62a3 str r3, [r4, #40] ; 0x28
|
|
|
80051e2: 4b0d ldr r3, [pc, #52] ; (8005218 <std+0x60>)
|
|
|
80051e4: 62e3 str r3, [r4, #44] ; 0x2c
|
|
|
80051e6: 4b0d ldr r3, [pc, #52] ; (800521c <std+0x64>)
|
|
|
80051e8: 6323 str r3, [r4, #48] ; 0x30
|
|
|
80051ea: 4b0d ldr r3, [pc, #52] ; (8005220 <std+0x68>)
|
|
|
80051ec: 6224 str r4, [r4, #32]
|
|
|
80051ee: 429c cmp r4, r3
|
|
|
80051f0: d006 beq.n 8005200 <std+0x48>
|
|
|
80051f2: f103 0268 add.w r2, r3, #104 ; 0x68
|
|
|
80051f6: 4294 cmp r4, r2
|
|
|
80051f8: d002 beq.n 8005200 <std+0x48>
|
|
|
80051fa: 33d0 adds r3, #208 ; 0xd0
|
|
|
80051fc: 429c cmp r4, r3
|
|
|
80051fe: d105 bne.n 800520c <std+0x54>
|
|
|
8005200: f104 0058 add.w r0, r4, #88 ; 0x58
|
|
|
8005204: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
8005208: f000 ba44 b.w 8005694 <__retarget_lock_init_recursive>
|
|
|
800520c: bd10 pop {r4, pc}
|
|
|
800520e: bf00 nop
|
|
|
8005210: 080053f5 .word 0x080053f5
|
|
|
8005214: 08005417 .word 0x08005417
|
|
|
8005218: 0800544f .word 0x0800544f
|
|
|
800521c: 08005473 .word 0x08005473
|
|
|
8005220: 20000220 .word 0x20000220
|
|
|
|
|
|
08005224 <stdio_exit_handler>:
|
|
|
8005224: 4a02 ldr r2, [pc, #8] ; (8005230 <stdio_exit_handler+0xc>)
|
|
|
8005226: 4903 ldr r1, [pc, #12] ; (8005234 <stdio_exit_handler+0x10>)
|
|
|
8005228: 4803 ldr r0, [pc, #12] ; (8005238 <stdio_exit_handler+0x14>)
|
|
|
800522a: f000 b869 b.w 8005300 <_fwalk_sglue>
|
|
|
800522e: bf00 nop
|
|
|
8005230: 20000010 .word 0x20000010
|
|
|
8005234: 08005999 .word 0x08005999
|
|
|
8005238: 2000001c .word 0x2000001c
|
|
|
|
|
|
0800523c <cleanup_stdio>:
|
|
|
800523c: 6841 ldr r1, [r0, #4]
|
|
|
800523e: 4b0c ldr r3, [pc, #48] ; (8005270 <cleanup_stdio+0x34>)
|
|
|
8005240: 4299 cmp r1, r3
|
|
|
8005242: b510 push {r4, lr}
|
|
|
8005244: 4604 mov r4, r0
|
|
|
8005246: d001 beq.n 800524c <cleanup_stdio+0x10>
|
|
|
8005248: f000 fba6 bl 8005998 <_fflush_r>
|
|
|
800524c: 68a1 ldr r1, [r4, #8]
|
|
|
800524e: 4b09 ldr r3, [pc, #36] ; (8005274 <cleanup_stdio+0x38>)
|
|
|
8005250: 4299 cmp r1, r3
|
|
|
8005252: d002 beq.n 800525a <cleanup_stdio+0x1e>
|
|
|
8005254: 4620 mov r0, r4
|
|
|
8005256: f000 fb9f bl 8005998 <_fflush_r>
|
|
|
800525a: 68e1 ldr r1, [r4, #12]
|
|
|
800525c: 4b06 ldr r3, [pc, #24] ; (8005278 <cleanup_stdio+0x3c>)
|
|
|
800525e: 4299 cmp r1, r3
|
|
|
8005260: d004 beq.n 800526c <cleanup_stdio+0x30>
|
|
|
8005262: 4620 mov r0, r4
|
|
|
8005264: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
8005268: f000 bb96 b.w 8005998 <_fflush_r>
|
|
|
800526c: bd10 pop {r4, pc}
|
|
|
800526e: bf00 nop
|
|
|
8005270: 20000220 .word 0x20000220
|
|
|
8005274: 20000288 .word 0x20000288
|
|
|
8005278: 200002f0 .word 0x200002f0
|
|
|
|
|
|
0800527c <global_stdio_init.part.0>:
|
|
|
800527c: b510 push {r4, lr}
|
|
|
800527e: 4b0b ldr r3, [pc, #44] ; (80052ac <global_stdio_init.part.0+0x30>)
|
|
|
8005280: 4c0b ldr r4, [pc, #44] ; (80052b0 <global_stdio_init.part.0+0x34>)
|
|
|
8005282: 4a0c ldr r2, [pc, #48] ; (80052b4 <global_stdio_init.part.0+0x38>)
|
|
|
8005284: 601a str r2, [r3, #0]
|
|
|
8005286: 4620 mov r0, r4
|
|
|
8005288: 2200 movs r2, #0
|
|
|
800528a: 2104 movs r1, #4
|
|
|
800528c: f7ff ff94 bl 80051b8 <std>
|
|
|
8005290: f104 0068 add.w r0, r4, #104 ; 0x68
|
|
|
8005294: 2201 movs r2, #1
|
|
|
8005296: 2109 movs r1, #9
|
|
|
8005298: f7ff ff8e bl 80051b8 <std>
|
|
|
800529c: f104 00d0 add.w r0, r4, #208 ; 0xd0
|
|
|
80052a0: 2202 movs r2, #2
|
|
|
80052a2: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
80052a6: 2112 movs r1, #18
|
|
|
80052a8: f7ff bf86 b.w 80051b8 <std>
|
|
|
80052ac: 20000358 .word 0x20000358
|
|
|
80052b0: 20000220 .word 0x20000220
|
|
|
80052b4: 08005225 .word 0x08005225
|
|
|
|
|
|
080052b8 <__sfp_lock_acquire>:
|
|
|
80052b8: 4801 ldr r0, [pc, #4] ; (80052c0 <__sfp_lock_acquire+0x8>)
|
|
|
80052ba: f000 b9ec b.w 8005696 <__retarget_lock_acquire_recursive>
|
|
|
80052be: bf00 nop
|
|
|
80052c0: 20000361 .word 0x20000361
|
|
|
|
|
|
080052c4 <__sfp_lock_release>:
|
|
|
80052c4: 4801 ldr r0, [pc, #4] ; (80052cc <__sfp_lock_release+0x8>)
|
|
|
80052c6: f000 b9e7 b.w 8005698 <__retarget_lock_release_recursive>
|
|
|
80052ca: bf00 nop
|
|
|
80052cc: 20000361 .word 0x20000361
|
|
|
|
|
|
080052d0 <__sinit>:
|
|
|
80052d0: b510 push {r4, lr}
|
|
|
80052d2: 4604 mov r4, r0
|
|
|
80052d4: f7ff fff0 bl 80052b8 <__sfp_lock_acquire>
|
|
|
80052d8: 6a23 ldr r3, [r4, #32]
|
|
|
80052da: b11b cbz r3, 80052e4 <__sinit+0x14>
|
|
|
80052dc: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
80052e0: f7ff bff0 b.w 80052c4 <__sfp_lock_release>
|
|
|
80052e4: 4b04 ldr r3, [pc, #16] ; (80052f8 <__sinit+0x28>)
|
|
|
80052e6: 6223 str r3, [r4, #32]
|
|
|
80052e8: 4b04 ldr r3, [pc, #16] ; (80052fc <__sinit+0x2c>)
|
|
|
80052ea: 681b ldr r3, [r3, #0]
|
|
|
80052ec: 2b00 cmp r3, #0
|
|
|
80052ee: d1f5 bne.n 80052dc <__sinit+0xc>
|
|
|
80052f0: f7ff ffc4 bl 800527c <global_stdio_init.part.0>
|
|
|
80052f4: e7f2 b.n 80052dc <__sinit+0xc>
|
|
|
80052f6: bf00 nop
|
|
|
80052f8: 0800523d .word 0x0800523d
|
|
|
80052fc: 20000358 .word 0x20000358
|
|
|
|
|
|
08005300 <_fwalk_sglue>:
|
|
|
8005300: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
|
8005304: 4607 mov r7, r0
|
|
|
8005306: 4688 mov r8, r1
|
|
|
8005308: 4614 mov r4, r2
|
|
|
800530a: 2600 movs r6, #0
|
|
|
800530c: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
|
8005310: f1b9 0901 subs.w r9, r9, #1
|
|
|
8005314: d505 bpl.n 8005322 <_fwalk_sglue+0x22>
|
|
|
8005316: 6824 ldr r4, [r4, #0]
|
|
|
8005318: 2c00 cmp r4, #0
|
|
|
800531a: d1f7 bne.n 800530c <_fwalk_sglue+0xc>
|
|
|
800531c: 4630 mov r0, r6
|
|
|
800531e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
|
8005322: 89ab ldrh r3, [r5, #12]
|
|
|
8005324: 2b01 cmp r3, #1
|
|
|
8005326: d907 bls.n 8005338 <_fwalk_sglue+0x38>
|
|
|
8005328: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
|
800532c: 3301 adds r3, #1
|
|
|
800532e: d003 beq.n 8005338 <_fwalk_sglue+0x38>
|
|
|
8005330: 4629 mov r1, r5
|
|
|
8005332: 4638 mov r0, r7
|
|
|
8005334: 47c0 blx r8
|
|
|
8005336: 4306 orrs r6, r0
|
|
|
8005338: 3568 adds r5, #104 ; 0x68
|
|
|
800533a: e7e9 b.n 8005310 <_fwalk_sglue+0x10>
|
|
|
|
|
|
0800533c <_puts_r>:
|
|
|
800533c: 6a03 ldr r3, [r0, #32]
|
|
|
800533e: b570 push {r4, r5, r6, lr}
|
|
|
8005340: 6884 ldr r4, [r0, #8]
|
|
|
8005342: 4605 mov r5, r0
|
|
|
8005344: 460e mov r6, r1
|
|
|
8005346: b90b cbnz r3, 800534c <_puts_r+0x10>
|
|
|
8005348: f7ff ffc2 bl 80052d0 <__sinit>
|
|
|
800534c: 6e63 ldr r3, [r4, #100] ; 0x64
|
|
|
800534e: 07db lsls r3, r3, #31
|
|
|
8005350: d405 bmi.n 800535e <_puts_r+0x22>
|
|
|
8005352: 89a3 ldrh r3, [r4, #12]
|
|
|
8005354: 0598 lsls r0, r3, #22
|
|
|
8005356: d402 bmi.n 800535e <_puts_r+0x22>
|
|
|
8005358: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
|
800535a: f000 f99c bl 8005696 <__retarget_lock_acquire_recursive>
|
|
|
800535e: 89a3 ldrh r3, [r4, #12]
|
|
|
8005360: 0719 lsls r1, r3, #28
|
|
|
8005362: d513 bpl.n 800538c <_puts_r+0x50>
|
|
|
8005364: 6923 ldr r3, [r4, #16]
|
|
|
8005366: b18b cbz r3, 800538c <_puts_r+0x50>
|
|
|
8005368: 3e01 subs r6, #1
|
|
|
800536a: 68a3 ldr r3, [r4, #8]
|
|
|
800536c: f816 1f01 ldrb.w r1, [r6, #1]!
|
|
|
8005370: 3b01 subs r3, #1
|
|
|
8005372: 60a3 str r3, [r4, #8]
|
|
|
8005374: b9e9 cbnz r1, 80053b2 <_puts_r+0x76>
|
|
|
8005376: 2b00 cmp r3, #0
|
|
|
8005378: da2e bge.n 80053d8 <_puts_r+0x9c>
|
|
|
800537a: 4622 mov r2, r4
|
|
|
800537c: 210a movs r1, #10
|
|
|
800537e: 4628 mov r0, r5
|
|
|
8005380: f000 f87b bl 800547a <__swbuf_r>
|
|
|
8005384: 3001 adds r0, #1
|
|
|
8005386: d007 beq.n 8005398 <_puts_r+0x5c>
|
|
|
8005388: 250a movs r5, #10
|
|
|
800538a: e007 b.n 800539c <_puts_r+0x60>
|
|
|
800538c: 4621 mov r1, r4
|
|
|
800538e: 4628 mov r0, r5
|
|
|
8005390: f000 f8b0 bl 80054f4 <__swsetup_r>
|
|
|
8005394: 2800 cmp r0, #0
|
|
|
8005396: d0e7 beq.n 8005368 <_puts_r+0x2c>
|
|
|
8005398: f04f 35ff mov.w r5, #4294967295
|
|
|
800539c: 6e63 ldr r3, [r4, #100] ; 0x64
|
|
|
800539e: 07da lsls r2, r3, #31
|
|
|
80053a0: d405 bmi.n 80053ae <_puts_r+0x72>
|
|
|
80053a2: 89a3 ldrh r3, [r4, #12]
|
|
|
80053a4: 059b lsls r3, r3, #22
|
|
|
80053a6: d402 bmi.n 80053ae <_puts_r+0x72>
|
|
|
80053a8: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
|
80053aa: f000 f975 bl 8005698 <__retarget_lock_release_recursive>
|
|
|
80053ae: 4628 mov r0, r5
|
|
|
80053b0: bd70 pop {r4, r5, r6, pc}
|
|
|
80053b2: 2b00 cmp r3, #0
|
|
|
80053b4: da04 bge.n 80053c0 <_puts_r+0x84>
|
|
|
80053b6: 69a2 ldr r2, [r4, #24]
|
|
|
80053b8: 429a cmp r2, r3
|
|
|
80053ba: dc06 bgt.n 80053ca <_puts_r+0x8e>
|
|
|
80053bc: 290a cmp r1, #10
|
|
|
80053be: d004 beq.n 80053ca <_puts_r+0x8e>
|
|
|
80053c0: 6823 ldr r3, [r4, #0]
|
|
|
80053c2: 1c5a adds r2, r3, #1
|
|
|
80053c4: 6022 str r2, [r4, #0]
|
|
|
80053c6: 7019 strb r1, [r3, #0]
|
|
|
80053c8: e7cf b.n 800536a <_puts_r+0x2e>
|
|
|
80053ca: 4622 mov r2, r4
|
|
|
80053cc: 4628 mov r0, r5
|
|
|
80053ce: f000 f854 bl 800547a <__swbuf_r>
|
|
|
80053d2: 3001 adds r0, #1
|
|
|
80053d4: d1c9 bne.n 800536a <_puts_r+0x2e>
|
|
|
80053d6: e7df b.n 8005398 <_puts_r+0x5c>
|
|
|
80053d8: 6823 ldr r3, [r4, #0]
|
|
|
80053da: 250a movs r5, #10
|
|
|
80053dc: 1c5a adds r2, r3, #1
|
|
|
80053de: 6022 str r2, [r4, #0]
|
|
|
80053e0: 701d strb r5, [r3, #0]
|
|
|
80053e2: e7db b.n 800539c <_puts_r+0x60>
|
|
|
|
|
|
080053e4 <puts>:
|
|
|
80053e4: 4b02 ldr r3, [pc, #8] ; (80053f0 <puts+0xc>)
|
|
|
80053e6: 4601 mov r1, r0
|
|
|
80053e8: 6818 ldr r0, [r3, #0]
|
|
|
80053ea: f7ff bfa7 b.w 800533c <_puts_r>
|
|
|
80053ee: bf00 nop
|
|
|
80053f0: 20000068 .word 0x20000068
|
|
|
|
|
|
080053f4 <__sread>:
|
|
|
80053f4: b510 push {r4, lr}
|
|
|
80053f6: 460c mov r4, r1
|
|
|
80053f8: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
|
80053fc: f000 f8fc bl 80055f8 <_read_r>
|
|
|
8005400: 2800 cmp r0, #0
|
|
|
8005402: bfab itete ge
|
|
|
8005404: 6d63 ldrge r3, [r4, #84] ; 0x54
|
|
|
8005406: 89a3 ldrhlt r3, [r4, #12]
|
|
|
8005408: 181b addge r3, r3, r0
|
|
|
800540a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
|
|
|
800540e: bfac ite ge
|
|
|
8005410: 6563 strge r3, [r4, #84] ; 0x54
|
|
|
8005412: 81a3 strhlt r3, [r4, #12]
|
|
|
8005414: bd10 pop {r4, pc}
|
|
|
|
|
|
08005416 <__swrite>:
|
|
|
8005416: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
800541a: 461f mov r7, r3
|
|
|
800541c: 898b ldrh r3, [r1, #12]
|
|
|
800541e: 05db lsls r3, r3, #23
|
|
|
8005420: 4605 mov r5, r0
|
|
|
8005422: 460c mov r4, r1
|
|
|
8005424: 4616 mov r6, r2
|
|
|
8005426: d505 bpl.n 8005434 <__swrite+0x1e>
|
|
|
8005428: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
|
800542c: 2302 movs r3, #2
|
|
|
800542e: 2200 movs r2, #0
|
|
|
8005430: f000 f8d0 bl 80055d4 <_lseek_r>
|
|
|
8005434: 89a3 ldrh r3, [r4, #12]
|
|
|
8005436: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
|
800543a: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
|
800543e: 81a3 strh r3, [r4, #12]
|
|
|
8005440: 4632 mov r2, r6
|
|
|
8005442: 463b mov r3, r7
|
|
|
8005444: 4628 mov r0, r5
|
|
|
8005446: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
800544a: f000 b8e7 b.w 800561c <_write_r>
|
|
|
|
|
|
0800544e <__sseek>:
|
|
|
800544e: b510 push {r4, lr}
|
|
|
8005450: 460c mov r4, r1
|
|
|
8005452: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
|
8005456: f000 f8bd bl 80055d4 <_lseek_r>
|
|
|
800545a: 1c43 adds r3, r0, #1
|
|
|
800545c: 89a3 ldrh r3, [r4, #12]
|
|
|
800545e: bf15 itete ne
|
|
|
8005460: 6560 strne r0, [r4, #84] ; 0x54
|
|
|
8005462: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
|
|
|
8005466: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
|
|
|
800546a: 81a3 strheq r3, [r4, #12]
|
|
|
800546c: bf18 it ne
|
|
|
800546e: 81a3 strhne r3, [r4, #12]
|
|
|
8005470: bd10 pop {r4, pc}
|
|
|
|
|
|
08005472 <__sclose>:
|
|
|
8005472: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
|
8005476: f000 b89d b.w 80055b4 <_close_r>
|
|
|
|
|
|
0800547a <__swbuf_r>:
|
|
|
800547a: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
800547c: 460e mov r6, r1
|
|
|
800547e: 4614 mov r4, r2
|
|
|
8005480: 4605 mov r5, r0
|
|
|
8005482: b118 cbz r0, 800548c <__swbuf_r+0x12>
|
|
|
8005484: 6a03 ldr r3, [r0, #32]
|
|
|
8005486: b90b cbnz r3, 800548c <__swbuf_r+0x12>
|
|
|
8005488: f7ff ff22 bl 80052d0 <__sinit>
|
|
|
800548c: 69a3 ldr r3, [r4, #24]
|
|
|
800548e: 60a3 str r3, [r4, #8]
|
|
|
8005490: 89a3 ldrh r3, [r4, #12]
|
|
|
8005492: 071a lsls r2, r3, #28
|
|
|
8005494: d525 bpl.n 80054e2 <__swbuf_r+0x68>
|
|
|
8005496: 6923 ldr r3, [r4, #16]
|
|
|
8005498: b31b cbz r3, 80054e2 <__swbuf_r+0x68>
|
|
|
800549a: 6823 ldr r3, [r4, #0]
|
|
|
800549c: 6922 ldr r2, [r4, #16]
|
|
|
800549e: 1a98 subs r0, r3, r2
|
|
|
80054a0: 6963 ldr r3, [r4, #20]
|
|
|
80054a2: b2f6 uxtb r6, r6
|
|
|
80054a4: 4283 cmp r3, r0
|
|
|
80054a6: 4637 mov r7, r6
|
|
|
80054a8: dc04 bgt.n 80054b4 <__swbuf_r+0x3a>
|
|
|
80054aa: 4621 mov r1, r4
|
|
|
80054ac: 4628 mov r0, r5
|
|
|
80054ae: f000 fa73 bl 8005998 <_fflush_r>
|
|
|
80054b2: b9e0 cbnz r0, 80054ee <__swbuf_r+0x74>
|
|
|
80054b4: 68a3 ldr r3, [r4, #8]
|
|
|
80054b6: 3b01 subs r3, #1
|
|
|
80054b8: 60a3 str r3, [r4, #8]
|
|
|
80054ba: 6823 ldr r3, [r4, #0]
|
|
|
80054bc: 1c5a adds r2, r3, #1
|
|
|
80054be: 6022 str r2, [r4, #0]
|
|
|
80054c0: 701e strb r6, [r3, #0]
|
|
|
80054c2: 6962 ldr r2, [r4, #20]
|
|
|
80054c4: 1c43 adds r3, r0, #1
|
|
|
80054c6: 429a cmp r2, r3
|
|
|
80054c8: d004 beq.n 80054d4 <__swbuf_r+0x5a>
|
|
|
80054ca: 89a3 ldrh r3, [r4, #12]
|
|
|
80054cc: 07db lsls r3, r3, #31
|
|
|
80054ce: d506 bpl.n 80054de <__swbuf_r+0x64>
|
|
|
80054d0: 2e0a cmp r6, #10
|
|
|
80054d2: d104 bne.n 80054de <__swbuf_r+0x64>
|
|
|
80054d4: 4621 mov r1, r4
|
|
|
80054d6: 4628 mov r0, r5
|
|
|
80054d8: f000 fa5e bl 8005998 <_fflush_r>
|
|
|
80054dc: b938 cbnz r0, 80054ee <__swbuf_r+0x74>
|
|
|
80054de: 4638 mov r0, r7
|
|
|
80054e0: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
|
80054e2: 4621 mov r1, r4
|
|
|
80054e4: 4628 mov r0, r5
|
|
|
80054e6: f000 f805 bl 80054f4 <__swsetup_r>
|
|
|
80054ea: 2800 cmp r0, #0
|
|
|
80054ec: d0d5 beq.n 800549a <__swbuf_r+0x20>
|
|
|
80054ee: f04f 37ff mov.w r7, #4294967295
|
|
|
80054f2: e7f4 b.n 80054de <__swbuf_r+0x64>
|
|
|
|
|
|
080054f4 <__swsetup_r>:
|
|
|
80054f4: b538 push {r3, r4, r5, lr}
|
|
|
80054f6: 4b2a ldr r3, [pc, #168] ; (80055a0 <__swsetup_r+0xac>)
|
|
|
80054f8: 4605 mov r5, r0
|
|
|
80054fa: 6818 ldr r0, [r3, #0]
|
|
|
80054fc: 460c mov r4, r1
|
|
|
80054fe: b118 cbz r0, 8005508 <__swsetup_r+0x14>
|
|
|
8005500: 6a03 ldr r3, [r0, #32]
|
|
|
8005502: b90b cbnz r3, 8005508 <__swsetup_r+0x14>
|
|
|
8005504: f7ff fee4 bl 80052d0 <__sinit>
|
|
|
8005508: 89a3 ldrh r3, [r4, #12]
|
|
|
800550a: f9b4 200c ldrsh.w r2, [r4, #12]
|
|
|
800550e: 0718 lsls r0, r3, #28
|
|
|
8005510: d422 bmi.n 8005558 <__swsetup_r+0x64>
|
|
|
8005512: 06d9 lsls r1, r3, #27
|
|
|
8005514: d407 bmi.n 8005526 <__swsetup_r+0x32>
|
|
|
8005516: 2309 movs r3, #9
|
|
|
8005518: 602b str r3, [r5, #0]
|
|
|
800551a: f042 0340 orr.w r3, r2, #64 ; 0x40
|
|
|
800551e: 81a3 strh r3, [r4, #12]
|
|
|
8005520: f04f 30ff mov.w r0, #4294967295
|
|
|
8005524: e034 b.n 8005590 <__swsetup_r+0x9c>
|
|
|
8005526: 0758 lsls r0, r3, #29
|
|
|
8005528: d512 bpl.n 8005550 <__swsetup_r+0x5c>
|
|
|
800552a: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
|
800552c: b141 cbz r1, 8005540 <__swsetup_r+0x4c>
|
|
|
800552e: f104 0344 add.w r3, r4, #68 ; 0x44
|
|
|
8005532: 4299 cmp r1, r3
|
|
|
8005534: d002 beq.n 800553c <__swsetup_r+0x48>
|
|
|
8005536: 4628 mov r0, r5
|
|
|
8005538: f000 f8b0 bl 800569c <_free_r>
|
|
|
800553c: 2300 movs r3, #0
|
|
|
800553e: 6363 str r3, [r4, #52] ; 0x34
|
|
|
8005540: 89a3 ldrh r3, [r4, #12]
|
|
|
8005542: f023 0324 bic.w r3, r3, #36 ; 0x24
|
|
|
8005546: 81a3 strh r3, [r4, #12]
|
|
|
8005548: 2300 movs r3, #0
|
|
|
800554a: 6063 str r3, [r4, #4]
|
|
|
800554c: 6923 ldr r3, [r4, #16]
|
|
|
800554e: 6023 str r3, [r4, #0]
|
|
|
8005550: 89a3 ldrh r3, [r4, #12]
|
|
|
8005552: f043 0308 orr.w r3, r3, #8
|
|
|
8005556: 81a3 strh r3, [r4, #12]
|
|
|
8005558: 6923 ldr r3, [r4, #16]
|
|
|
800555a: b94b cbnz r3, 8005570 <__swsetup_r+0x7c>
|
|
|
800555c: 89a3 ldrh r3, [r4, #12]
|
|
|
800555e: f403 7320 and.w r3, r3, #640 ; 0x280
|
|
|
8005562: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
|
8005566: d003 beq.n 8005570 <__swsetup_r+0x7c>
|
|
|
8005568: 4621 mov r1, r4
|
|
|
800556a: 4628 mov r0, r5
|
|
|
800556c: f000 fa62 bl 8005a34 <__smakebuf_r>
|
|
|
8005570: 89a0 ldrh r0, [r4, #12]
|
|
|
8005572: f9b4 200c ldrsh.w r2, [r4, #12]
|
|
|
8005576: f010 0301 ands.w r3, r0, #1
|
|
|
800557a: d00a beq.n 8005592 <__swsetup_r+0x9e>
|
|
|
800557c: 2300 movs r3, #0
|
|
|
800557e: 60a3 str r3, [r4, #8]
|
|
|
8005580: 6963 ldr r3, [r4, #20]
|
|
|
8005582: 425b negs r3, r3
|
|
|
8005584: 61a3 str r3, [r4, #24]
|
|
|
8005586: 6923 ldr r3, [r4, #16]
|
|
|
8005588: b943 cbnz r3, 800559c <__swsetup_r+0xa8>
|
|
|
800558a: f010 0080 ands.w r0, r0, #128 ; 0x80
|
|
|
800558e: d1c4 bne.n 800551a <__swsetup_r+0x26>
|
|
|
8005590: bd38 pop {r3, r4, r5, pc}
|
|
|
8005592: 0781 lsls r1, r0, #30
|
|
|
8005594: bf58 it pl
|
|
|
8005596: 6963 ldrpl r3, [r4, #20]
|
|
|
8005598: 60a3 str r3, [r4, #8]
|
|
|
800559a: e7f4 b.n 8005586 <__swsetup_r+0x92>
|
|
|
800559c: 2000 movs r0, #0
|
|
|
800559e: e7f7 b.n 8005590 <__swsetup_r+0x9c>
|
|
|
80055a0: 20000068 .word 0x20000068
|
|
|
|
|
|
080055a4 <memset>:
|
|
|
80055a4: 4402 add r2, r0
|
|
|
80055a6: 4603 mov r3, r0
|
|
|
80055a8: 4293 cmp r3, r2
|
|
|
80055aa: d100 bne.n 80055ae <memset+0xa>
|
|
|
80055ac: 4770 bx lr
|
|
|
80055ae: f803 1b01 strb.w r1, [r3], #1
|
|
|
80055b2: e7f9 b.n 80055a8 <memset+0x4>
|
|
|
|
|
|
080055b4 <_close_r>:
|
|
|
80055b4: b538 push {r3, r4, r5, lr}
|
|
|
80055b6: 4d06 ldr r5, [pc, #24] ; (80055d0 <_close_r+0x1c>)
|
|
|
80055b8: 2300 movs r3, #0
|
|
|
80055ba: 4604 mov r4, r0
|
|
|
80055bc: 4608 mov r0, r1
|
|
|
80055be: 602b str r3, [r5, #0]
|
|
|
80055c0: f7fb fc23 bl 8000e0a <_close>
|
|
|
80055c4: 1c43 adds r3, r0, #1
|
|
|
80055c6: d102 bne.n 80055ce <_close_r+0x1a>
|
|
|
80055c8: 682b ldr r3, [r5, #0]
|
|
|
80055ca: b103 cbz r3, 80055ce <_close_r+0x1a>
|
|
|
80055cc: 6023 str r3, [r4, #0]
|
|
|
80055ce: bd38 pop {r3, r4, r5, pc}
|
|
|
80055d0: 2000035c .word 0x2000035c
|
|
|
|
|
|
080055d4 <_lseek_r>:
|
|
|
80055d4: b538 push {r3, r4, r5, lr}
|
|
|
80055d6: 4d07 ldr r5, [pc, #28] ; (80055f4 <_lseek_r+0x20>)
|
|
|
80055d8: 4604 mov r4, r0
|
|
|
80055da: 4608 mov r0, r1
|
|
|
80055dc: 4611 mov r1, r2
|
|
|
80055de: 2200 movs r2, #0
|
|
|
80055e0: 602a str r2, [r5, #0]
|
|
|
80055e2: 461a mov r2, r3
|
|
|
80055e4: f7fb fc38 bl 8000e58 <_lseek>
|
|
|
80055e8: 1c43 adds r3, r0, #1
|
|
|
80055ea: d102 bne.n 80055f2 <_lseek_r+0x1e>
|
|
|
80055ec: 682b ldr r3, [r5, #0]
|
|
|
80055ee: b103 cbz r3, 80055f2 <_lseek_r+0x1e>
|
|
|
80055f0: 6023 str r3, [r4, #0]
|
|
|
80055f2: bd38 pop {r3, r4, r5, pc}
|
|
|
80055f4: 2000035c .word 0x2000035c
|
|
|
|
|
|
080055f8 <_read_r>:
|
|
|
80055f8: b538 push {r3, r4, r5, lr}
|
|
|
80055fa: 4d07 ldr r5, [pc, #28] ; (8005618 <_read_r+0x20>)
|
|
|
80055fc: 4604 mov r4, r0
|
|
|
80055fe: 4608 mov r0, r1
|
|
|
8005600: 4611 mov r1, r2
|
|
|
8005602: 2200 movs r2, #0
|
|
|
8005604: 602a str r2, [r5, #0]
|
|
|
8005606: 461a mov r2, r3
|
|
|
8005608: f7fb fbc6 bl 8000d98 <_read>
|
|
|
800560c: 1c43 adds r3, r0, #1
|
|
|
800560e: d102 bne.n 8005616 <_read_r+0x1e>
|
|
|
8005610: 682b ldr r3, [r5, #0]
|
|
|
8005612: b103 cbz r3, 8005616 <_read_r+0x1e>
|
|
|
8005614: 6023 str r3, [r4, #0]
|
|
|
8005616: bd38 pop {r3, r4, r5, pc}
|
|
|
8005618: 2000035c .word 0x2000035c
|
|
|
|
|
|
0800561c <_write_r>:
|
|
|
800561c: b538 push {r3, r4, r5, lr}
|
|
|
800561e: 4d07 ldr r5, [pc, #28] ; (800563c <_write_r+0x20>)
|
|
|
8005620: 4604 mov r4, r0
|
|
|
8005622: 4608 mov r0, r1
|
|
|
8005624: 4611 mov r1, r2
|
|
|
8005626: 2200 movs r2, #0
|
|
|
8005628: 602a str r2, [r5, #0]
|
|
|
800562a: 461a mov r2, r3
|
|
|
800562c: f7fb fbd1 bl 8000dd2 <_write>
|
|
|
8005630: 1c43 adds r3, r0, #1
|
|
|
8005632: d102 bne.n 800563a <_write_r+0x1e>
|
|
|
8005634: 682b ldr r3, [r5, #0]
|
|
|
8005636: b103 cbz r3, 800563a <_write_r+0x1e>
|
|
|
8005638: 6023 str r3, [r4, #0]
|
|
|
800563a: bd38 pop {r3, r4, r5, pc}
|
|
|
800563c: 2000035c .word 0x2000035c
|
|
|
|
|
|
08005640 <__errno>:
|
|
|
8005640: 4b01 ldr r3, [pc, #4] ; (8005648 <__errno+0x8>)
|
|
|
8005642: 6818 ldr r0, [r3, #0]
|
|
|
8005644: 4770 bx lr
|
|
|
8005646: bf00 nop
|
|
|
8005648: 20000068 .word 0x20000068
|
|
|
|
|
|
0800564c <__libc_init_array>:
|
|
|
800564c: b570 push {r4, r5, r6, lr}
|
|
|
800564e: 4d0d ldr r5, [pc, #52] ; (8005684 <__libc_init_array+0x38>)
|
|
|
8005650: 4c0d ldr r4, [pc, #52] ; (8005688 <__libc_init_array+0x3c>)
|
|
|
8005652: 1b64 subs r4, r4, r5
|
|
|
8005654: 10a4 asrs r4, r4, #2
|
|
|
8005656: 2600 movs r6, #0
|
|
|
8005658: 42a6 cmp r6, r4
|
|
|
800565a: d109 bne.n 8005670 <__libc_init_array+0x24>
|
|
|
800565c: 4d0b ldr r5, [pc, #44] ; (800568c <__libc_init_array+0x40>)
|
|
|
800565e: 4c0c ldr r4, [pc, #48] ; (8005690 <__libc_init_array+0x44>)
|
|
|
8005660: f000 fa56 bl 8005b10 <_init>
|
|
|
8005664: 1b64 subs r4, r4, r5
|
|
|
8005666: 10a4 asrs r4, r4, #2
|
|
|
8005668: 2600 movs r6, #0
|
|
|
800566a: 42a6 cmp r6, r4
|
|
|
800566c: d105 bne.n 800567a <__libc_init_array+0x2e>
|
|
|
800566e: bd70 pop {r4, r5, r6, pc}
|
|
|
8005670: f855 3b04 ldr.w r3, [r5], #4
|
|
|
8005674: 4798 blx r3
|
|
|
8005676: 3601 adds r6, #1
|
|
|
8005678: e7ee b.n 8005658 <__libc_init_array+0xc>
|
|
|
800567a: f855 3b04 ldr.w r3, [r5], #4
|
|
|
800567e: 4798 blx r3
|
|
|
8005680: 3601 adds r6, #1
|
|
|
8005682: e7f2 b.n 800566a <__libc_init_array+0x1e>
|
|
|
8005684: 08005c50 .word 0x08005c50
|
|
|
8005688: 08005c50 .word 0x08005c50
|
|
|
800568c: 08005c50 .word 0x08005c50
|
|
|
8005690: 08005c54 .word 0x08005c54
|
|
|
|
|
|
08005694 <__retarget_lock_init_recursive>:
|
|
|
8005694: 4770 bx lr
|
|
|
|
|
|
08005696 <__retarget_lock_acquire_recursive>:
|
|
|
8005696: 4770 bx lr
|
|
|
|
|
|
08005698 <__retarget_lock_release_recursive>:
|
|
|
8005698: 4770 bx lr
|
|
|
...
|
|
|
|
|
|
0800569c <_free_r>:
|
|
|
800569c: b537 push {r0, r1, r2, r4, r5, lr}
|
|
|
800569e: 2900 cmp r1, #0
|
|
|
80056a0: d044 beq.n 800572c <_free_r+0x90>
|
|
|
80056a2: f851 3c04 ldr.w r3, [r1, #-4]
|
|
|
80056a6: 9001 str r0, [sp, #4]
|
|
|
80056a8: 2b00 cmp r3, #0
|
|
|
80056aa: f1a1 0404 sub.w r4, r1, #4
|
|
|
80056ae: bfb8 it lt
|
|
|
80056b0: 18e4 addlt r4, r4, r3
|
|
|
80056b2: f000 f8df bl 8005874 <__malloc_lock>
|
|
|
80056b6: 4a1e ldr r2, [pc, #120] ; (8005730 <_free_r+0x94>)
|
|
|
80056b8: 9801 ldr r0, [sp, #4]
|
|
|
80056ba: 6813 ldr r3, [r2, #0]
|
|
|
80056bc: b933 cbnz r3, 80056cc <_free_r+0x30>
|
|
|
80056be: 6063 str r3, [r4, #4]
|
|
|
80056c0: 6014 str r4, [r2, #0]
|
|
|
80056c2: b003 add sp, #12
|
|
|
80056c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
|
|
|
80056c8: f000 b8da b.w 8005880 <__malloc_unlock>
|
|
|
80056cc: 42a3 cmp r3, r4
|
|
|
80056ce: d908 bls.n 80056e2 <_free_r+0x46>
|
|
|
80056d0: 6825 ldr r5, [r4, #0]
|
|
|
80056d2: 1961 adds r1, r4, r5
|
|
|
80056d4: 428b cmp r3, r1
|
|
|
80056d6: bf01 itttt eq
|
|
|
80056d8: 6819 ldreq r1, [r3, #0]
|
|
|
80056da: 685b ldreq r3, [r3, #4]
|
|
|
80056dc: 1949 addeq r1, r1, r5
|
|
|
80056de: 6021 streq r1, [r4, #0]
|
|
|
80056e0: e7ed b.n 80056be <_free_r+0x22>
|
|
|
80056e2: 461a mov r2, r3
|
|
|
80056e4: 685b ldr r3, [r3, #4]
|
|
|
80056e6: b10b cbz r3, 80056ec <_free_r+0x50>
|
|
|
80056e8: 42a3 cmp r3, r4
|
|
|
80056ea: d9fa bls.n 80056e2 <_free_r+0x46>
|
|
|
80056ec: 6811 ldr r1, [r2, #0]
|
|
|
80056ee: 1855 adds r5, r2, r1
|
|
|
80056f0: 42a5 cmp r5, r4
|
|
|
80056f2: d10b bne.n 800570c <_free_r+0x70>
|
|
|
80056f4: 6824 ldr r4, [r4, #0]
|
|
|
80056f6: 4421 add r1, r4
|
|
|
80056f8: 1854 adds r4, r2, r1
|
|
|
80056fa: 42a3 cmp r3, r4
|
|
|
80056fc: 6011 str r1, [r2, #0]
|
|
|
80056fe: d1e0 bne.n 80056c2 <_free_r+0x26>
|
|
|
8005700: 681c ldr r4, [r3, #0]
|
|
|
8005702: 685b ldr r3, [r3, #4]
|
|
|
8005704: 6053 str r3, [r2, #4]
|
|
|
8005706: 440c add r4, r1
|
|
|
8005708: 6014 str r4, [r2, #0]
|
|
|
800570a: e7da b.n 80056c2 <_free_r+0x26>
|
|
|
800570c: d902 bls.n 8005714 <_free_r+0x78>
|
|
|
800570e: 230c movs r3, #12
|
|
|
8005710: 6003 str r3, [r0, #0]
|
|
|
8005712: e7d6 b.n 80056c2 <_free_r+0x26>
|
|
|
8005714: 6825 ldr r5, [r4, #0]
|
|
|
8005716: 1961 adds r1, r4, r5
|
|
|
8005718: 428b cmp r3, r1
|
|
|
800571a: bf04 itt eq
|
|
|
800571c: 6819 ldreq r1, [r3, #0]
|
|
|
800571e: 685b ldreq r3, [r3, #4]
|
|
|
8005720: 6063 str r3, [r4, #4]
|
|
|
8005722: bf04 itt eq
|
|
|
8005724: 1949 addeq r1, r1, r5
|
|
|
8005726: 6021 streq r1, [r4, #0]
|
|
|
8005728: 6054 str r4, [r2, #4]
|
|
|
800572a: e7ca b.n 80056c2 <_free_r+0x26>
|
|
|
800572c: b003 add sp, #12
|
|
|
800572e: bd30 pop {r4, r5, pc}
|
|
|
8005730: 20000364 .word 0x20000364
|
|
|
|
|
|
08005734 <sbrk_aligned>:
|
|
|
8005734: b570 push {r4, r5, r6, lr}
|
|
|
8005736: 4e0e ldr r6, [pc, #56] ; (8005770 <sbrk_aligned+0x3c>)
|
|
|
8005738: 460c mov r4, r1
|
|
|
800573a: 6831 ldr r1, [r6, #0]
|
|
|
800573c: 4605 mov r5, r0
|
|
|
800573e: b911 cbnz r1, 8005746 <sbrk_aligned+0x12>
|
|
|
8005740: f000 f9d6 bl 8005af0 <_sbrk_r>
|
|
|
8005744: 6030 str r0, [r6, #0]
|
|
|
8005746: 4621 mov r1, r4
|
|
|
8005748: 4628 mov r0, r5
|
|
|
800574a: f000 f9d1 bl 8005af0 <_sbrk_r>
|
|
|
800574e: 1c43 adds r3, r0, #1
|
|
|
8005750: d00a beq.n 8005768 <sbrk_aligned+0x34>
|
|
|
8005752: 1cc4 adds r4, r0, #3
|
|
|
8005754: f024 0403 bic.w r4, r4, #3
|
|
|
8005758: 42a0 cmp r0, r4
|
|
|
800575a: d007 beq.n 800576c <sbrk_aligned+0x38>
|
|
|
800575c: 1a21 subs r1, r4, r0
|
|
|
800575e: 4628 mov r0, r5
|
|
|
8005760: f000 f9c6 bl 8005af0 <_sbrk_r>
|
|
|
8005764: 3001 adds r0, #1
|
|
|
8005766: d101 bne.n 800576c <sbrk_aligned+0x38>
|
|
|
8005768: f04f 34ff mov.w r4, #4294967295
|
|
|
800576c: 4620 mov r0, r4
|
|
|
800576e: bd70 pop {r4, r5, r6, pc}
|
|
|
8005770: 20000368 .word 0x20000368
|
|
|
|
|
|
08005774 <_malloc_r>:
|
|
|
8005774: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
|
8005778: 1ccd adds r5, r1, #3
|
|
|
800577a: f025 0503 bic.w r5, r5, #3
|
|
|
800577e: 3508 adds r5, #8
|
|
|
8005780: 2d0c cmp r5, #12
|
|
|
8005782: bf38 it cc
|
|
|
8005784: 250c movcc r5, #12
|
|
|
8005786: 2d00 cmp r5, #0
|
|
|
8005788: 4607 mov r7, r0
|
|
|
800578a: db01 blt.n 8005790 <_malloc_r+0x1c>
|
|
|
800578c: 42a9 cmp r1, r5
|
|
|
800578e: d905 bls.n 800579c <_malloc_r+0x28>
|
|
|
8005790: 230c movs r3, #12
|
|
|
8005792: 603b str r3, [r7, #0]
|
|
|
8005794: 2600 movs r6, #0
|
|
|
8005796: 4630 mov r0, r6
|
|
|
8005798: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
|
800579c: f8df 80d0 ldr.w r8, [pc, #208] ; 8005870 <_malloc_r+0xfc>
|
|
|
80057a0: f000 f868 bl 8005874 <__malloc_lock>
|
|
|
80057a4: f8d8 3000 ldr.w r3, [r8]
|
|
|
80057a8: 461c mov r4, r3
|
|
|
80057aa: bb5c cbnz r4, 8005804 <_malloc_r+0x90>
|
|
|
80057ac: 4629 mov r1, r5
|
|
|
80057ae: 4638 mov r0, r7
|
|
|
80057b0: f7ff ffc0 bl 8005734 <sbrk_aligned>
|
|
|
80057b4: 1c43 adds r3, r0, #1
|
|
|
80057b6: 4604 mov r4, r0
|
|
|
80057b8: d155 bne.n 8005866 <_malloc_r+0xf2>
|
|
|
80057ba: f8d8 4000 ldr.w r4, [r8]
|
|
|
80057be: 4626 mov r6, r4
|
|
|
80057c0: 2e00 cmp r6, #0
|
|
|
80057c2: d145 bne.n 8005850 <_malloc_r+0xdc>
|
|
|
80057c4: 2c00 cmp r4, #0
|
|
|
80057c6: d048 beq.n 800585a <_malloc_r+0xe6>
|
|
|
80057c8: 6823 ldr r3, [r4, #0]
|
|
|
80057ca: 4631 mov r1, r6
|
|
|
80057cc: 4638 mov r0, r7
|
|
|
80057ce: eb04 0903 add.w r9, r4, r3
|
|
|
80057d2: f000 f98d bl 8005af0 <_sbrk_r>
|
|
|
80057d6: 4581 cmp r9, r0
|
|
|
80057d8: d13f bne.n 800585a <_malloc_r+0xe6>
|
|
|
80057da: 6821 ldr r1, [r4, #0]
|
|
|
80057dc: 1a6d subs r5, r5, r1
|
|
|
80057de: 4629 mov r1, r5
|
|
|
80057e0: 4638 mov r0, r7
|
|
|
80057e2: f7ff ffa7 bl 8005734 <sbrk_aligned>
|
|
|
80057e6: 3001 adds r0, #1
|
|
|
80057e8: d037 beq.n 800585a <_malloc_r+0xe6>
|
|
|
80057ea: 6823 ldr r3, [r4, #0]
|
|
|
80057ec: 442b add r3, r5
|
|
|
80057ee: 6023 str r3, [r4, #0]
|
|
|
80057f0: f8d8 3000 ldr.w r3, [r8]
|
|
|
80057f4: 2b00 cmp r3, #0
|
|
|
80057f6: d038 beq.n 800586a <_malloc_r+0xf6>
|
|
|
80057f8: 685a ldr r2, [r3, #4]
|
|
|
80057fa: 42a2 cmp r2, r4
|
|
|
80057fc: d12b bne.n 8005856 <_malloc_r+0xe2>
|
|
|
80057fe: 2200 movs r2, #0
|
|
|
8005800: 605a str r2, [r3, #4]
|
|
|
8005802: e00f b.n 8005824 <_malloc_r+0xb0>
|
|
|
8005804: 6822 ldr r2, [r4, #0]
|
|
|
8005806: 1b52 subs r2, r2, r5
|
|
|
8005808: d41f bmi.n 800584a <_malloc_r+0xd6>
|
|
|
800580a: 2a0b cmp r2, #11
|
|
|
800580c: d917 bls.n 800583e <_malloc_r+0xca>
|
|
|
800580e: 1961 adds r1, r4, r5
|
|
|
8005810: 42a3 cmp r3, r4
|
|
|
8005812: 6025 str r5, [r4, #0]
|
|
|
8005814: bf18 it ne
|
|
|
8005816: 6059 strne r1, [r3, #4]
|
|
|
8005818: 6863 ldr r3, [r4, #4]
|
|
|
800581a: bf08 it eq
|
|
|
800581c: f8c8 1000 streq.w r1, [r8]
|
|
|
8005820: 5162 str r2, [r4, r5]
|
|
|
8005822: 604b str r3, [r1, #4]
|
|
|
8005824: 4638 mov r0, r7
|
|
|
8005826: f104 060b add.w r6, r4, #11
|
|
|
800582a: f000 f829 bl 8005880 <__malloc_unlock>
|
|
|
800582e: f026 0607 bic.w r6, r6, #7
|
|
|
8005832: 1d23 adds r3, r4, #4
|
|
|
8005834: 1af2 subs r2, r6, r3
|
|
|
8005836: d0ae beq.n 8005796 <_malloc_r+0x22>
|
|
|
8005838: 1b9b subs r3, r3, r6
|
|
|
800583a: 50a3 str r3, [r4, r2]
|
|
|
800583c: e7ab b.n 8005796 <_malloc_r+0x22>
|
|
|
800583e: 42a3 cmp r3, r4
|
|
|
8005840: 6862 ldr r2, [r4, #4]
|
|
|
8005842: d1dd bne.n 8005800 <_malloc_r+0x8c>
|
|
|
8005844: f8c8 2000 str.w r2, [r8]
|
|
|
8005848: e7ec b.n 8005824 <_malloc_r+0xb0>
|
|
|
800584a: 4623 mov r3, r4
|
|
|
800584c: 6864 ldr r4, [r4, #4]
|
|
|
800584e: e7ac b.n 80057aa <_malloc_r+0x36>
|
|
|
8005850: 4634 mov r4, r6
|
|
|
8005852: 6876 ldr r6, [r6, #4]
|
|
|
8005854: e7b4 b.n 80057c0 <_malloc_r+0x4c>
|
|
|
8005856: 4613 mov r3, r2
|
|
|
8005858: e7cc b.n 80057f4 <_malloc_r+0x80>
|
|
|
800585a: 230c movs r3, #12
|
|
|
800585c: 603b str r3, [r7, #0]
|
|
|
800585e: 4638 mov r0, r7
|
|
|
8005860: f000 f80e bl 8005880 <__malloc_unlock>
|
|
|
8005864: e797 b.n 8005796 <_malloc_r+0x22>
|
|
|
8005866: 6025 str r5, [r4, #0]
|
|
|
8005868: e7dc b.n 8005824 <_malloc_r+0xb0>
|
|
|
800586a: 605b str r3, [r3, #4]
|
|
|
800586c: deff udf #255 ; 0xff
|
|
|
800586e: bf00 nop
|
|
|
8005870: 20000364 .word 0x20000364
|
|
|
|
|
|
08005874 <__malloc_lock>:
|
|
|
8005874: 4801 ldr r0, [pc, #4] ; (800587c <__malloc_lock+0x8>)
|
|
|
8005876: f7ff bf0e b.w 8005696 <__retarget_lock_acquire_recursive>
|
|
|
800587a: bf00 nop
|
|
|
800587c: 20000360 .word 0x20000360
|
|
|
|
|
|
08005880 <__malloc_unlock>:
|
|
|
8005880: 4801 ldr r0, [pc, #4] ; (8005888 <__malloc_unlock+0x8>)
|
|
|
8005882: f7ff bf09 b.w 8005698 <__retarget_lock_release_recursive>
|
|
|
8005886: bf00 nop
|
|
|
8005888: 20000360 .word 0x20000360
|
|
|
|
|
|
0800588c <__sflush_r>:
|
|
|
800588c: 898a ldrh r2, [r1, #12]
|
|
|
800588e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8005892: 4605 mov r5, r0
|
|
|
8005894: 0710 lsls r0, r2, #28
|
|
|
8005896: 460c mov r4, r1
|
|
|
8005898: d458 bmi.n 800594c <__sflush_r+0xc0>
|
|
|
800589a: 684b ldr r3, [r1, #4]
|
|
|
800589c: 2b00 cmp r3, #0
|
|
|
800589e: dc05 bgt.n 80058ac <__sflush_r+0x20>
|
|
|
80058a0: 6c0b ldr r3, [r1, #64] ; 0x40
|
|
|
80058a2: 2b00 cmp r3, #0
|
|
|
80058a4: dc02 bgt.n 80058ac <__sflush_r+0x20>
|
|
|
80058a6: 2000 movs r0, #0
|
|
|
80058a8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
80058ac: 6ae6 ldr r6, [r4, #44] ; 0x2c
|
|
|
80058ae: 2e00 cmp r6, #0
|
|
|
80058b0: d0f9 beq.n 80058a6 <__sflush_r+0x1a>
|
|
|
80058b2: 2300 movs r3, #0
|
|
|
80058b4: f412 5280 ands.w r2, r2, #4096 ; 0x1000
|
|
|
80058b8: 682f ldr r7, [r5, #0]
|
|
|
80058ba: 6a21 ldr r1, [r4, #32]
|
|
|
80058bc: 602b str r3, [r5, #0]
|
|
|
80058be: d032 beq.n 8005926 <__sflush_r+0x9a>
|
|
|
80058c0: 6d60 ldr r0, [r4, #84] ; 0x54
|
|
|
80058c2: 89a3 ldrh r3, [r4, #12]
|
|
|
80058c4: 075a lsls r2, r3, #29
|
|
|
80058c6: d505 bpl.n 80058d4 <__sflush_r+0x48>
|
|
|
80058c8: 6863 ldr r3, [r4, #4]
|
|
|
80058ca: 1ac0 subs r0, r0, r3
|
|
|
80058cc: 6b63 ldr r3, [r4, #52] ; 0x34
|
|
|
80058ce: b10b cbz r3, 80058d4 <__sflush_r+0x48>
|
|
|
80058d0: 6c23 ldr r3, [r4, #64] ; 0x40
|
|
|
80058d2: 1ac0 subs r0, r0, r3
|
|
|
80058d4: 2300 movs r3, #0
|
|
|
80058d6: 4602 mov r2, r0
|
|
|
80058d8: 6ae6 ldr r6, [r4, #44] ; 0x2c
|
|
|
80058da: 6a21 ldr r1, [r4, #32]
|
|
|
80058dc: 4628 mov r0, r5
|
|
|
80058de: 47b0 blx r6
|
|
|
80058e0: 1c43 adds r3, r0, #1
|
|
|
80058e2: 89a3 ldrh r3, [r4, #12]
|
|
|
80058e4: d106 bne.n 80058f4 <__sflush_r+0x68>
|
|
|
80058e6: 6829 ldr r1, [r5, #0]
|
|
|
80058e8: 291d cmp r1, #29
|
|
|
80058ea: d82b bhi.n 8005944 <__sflush_r+0xb8>
|
|
|
80058ec: 4a29 ldr r2, [pc, #164] ; (8005994 <__sflush_r+0x108>)
|
|
|
80058ee: 410a asrs r2, r1
|
|
|
80058f0: 07d6 lsls r6, r2, #31
|
|
|
80058f2: d427 bmi.n 8005944 <__sflush_r+0xb8>
|
|
|
80058f4: 2200 movs r2, #0
|
|
|
80058f6: 6062 str r2, [r4, #4]
|
|
|
80058f8: 04d9 lsls r1, r3, #19
|
|
|
80058fa: 6922 ldr r2, [r4, #16]
|
|
|
80058fc: 6022 str r2, [r4, #0]
|
|
|
80058fe: d504 bpl.n 800590a <__sflush_r+0x7e>
|
|
|
8005900: 1c42 adds r2, r0, #1
|
|
|
8005902: d101 bne.n 8005908 <__sflush_r+0x7c>
|
|
|
8005904: 682b ldr r3, [r5, #0]
|
|
|
8005906: b903 cbnz r3, 800590a <__sflush_r+0x7e>
|
|
|
8005908: 6560 str r0, [r4, #84] ; 0x54
|
|
|
800590a: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
|
800590c: 602f str r7, [r5, #0]
|
|
|
800590e: 2900 cmp r1, #0
|
|
|
8005910: d0c9 beq.n 80058a6 <__sflush_r+0x1a>
|
|
|
8005912: f104 0344 add.w r3, r4, #68 ; 0x44
|
|
|
8005916: 4299 cmp r1, r3
|
|
|
8005918: d002 beq.n 8005920 <__sflush_r+0x94>
|
|
|
800591a: 4628 mov r0, r5
|
|
|
800591c: f7ff febe bl 800569c <_free_r>
|
|
|
8005920: 2000 movs r0, #0
|
|
|
8005922: 6360 str r0, [r4, #52] ; 0x34
|
|
|
8005924: e7c0 b.n 80058a8 <__sflush_r+0x1c>
|
|
|
8005926: 2301 movs r3, #1
|
|
|
8005928: 4628 mov r0, r5
|
|
|
800592a: 47b0 blx r6
|
|
|
800592c: 1c41 adds r1, r0, #1
|
|
|
800592e: d1c8 bne.n 80058c2 <__sflush_r+0x36>
|
|
|
8005930: 682b ldr r3, [r5, #0]
|
|
|
8005932: 2b00 cmp r3, #0
|
|
|
8005934: d0c5 beq.n 80058c2 <__sflush_r+0x36>
|
|
|
8005936: 2b1d cmp r3, #29
|
|
|
8005938: d001 beq.n 800593e <__sflush_r+0xb2>
|
|
|
800593a: 2b16 cmp r3, #22
|
|
|
800593c: d101 bne.n 8005942 <__sflush_r+0xb6>
|
|
|
800593e: 602f str r7, [r5, #0]
|
|
|
8005940: e7b1 b.n 80058a6 <__sflush_r+0x1a>
|
|
|
8005942: 89a3 ldrh r3, [r4, #12]
|
|
|
8005944: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
|
8005948: 81a3 strh r3, [r4, #12]
|
|
|
800594a: e7ad b.n 80058a8 <__sflush_r+0x1c>
|
|
|
800594c: 690f ldr r7, [r1, #16]
|
|
|
800594e: 2f00 cmp r7, #0
|
|
|
8005950: d0a9 beq.n 80058a6 <__sflush_r+0x1a>
|
|
|
8005952: 0793 lsls r3, r2, #30
|
|
|
8005954: 680e ldr r6, [r1, #0]
|
|
|
8005956: bf08 it eq
|
|
|
8005958: 694b ldreq r3, [r1, #20]
|
|
|
800595a: 600f str r7, [r1, #0]
|
|
|
800595c: bf18 it ne
|
|
|
800595e: 2300 movne r3, #0
|
|
|
8005960: eba6 0807 sub.w r8, r6, r7
|
|
|
8005964: 608b str r3, [r1, #8]
|
|
|
8005966: f1b8 0f00 cmp.w r8, #0
|
|
|
800596a: dd9c ble.n 80058a6 <__sflush_r+0x1a>
|
|
|
800596c: 6a21 ldr r1, [r4, #32]
|
|
|
800596e: 6aa6 ldr r6, [r4, #40] ; 0x28
|
|
|
8005970: 4643 mov r3, r8
|
|
|
8005972: 463a mov r2, r7
|
|
|
8005974: 4628 mov r0, r5
|
|
|
8005976: 47b0 blx r6
|
|
|
8005978: 2800 cmp r0, #0
|
|
|
800597a: dc06 bgt.n 800598a <__sflush_r+0xfe>
|
|
|
800597c: 89a3 ldrh r3, [r4, #12]
|
|
|
800597e: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
|
8005982: 81a3 strh r3, [r4, #12]
|
|
|
8005984: f04f 30ff mov.w r0, #4294967295
|
|
|
8005988: e78e b.n 80058a8 <__sflush_r+0x1c>
|
|
|
800598a: 4407 add r7, r0
|
|
|
800598c: eba8 0800 sub.w r8, r8, r0
|
|
|
8005990: e7e9 b.n 8005966 <__sflush_r+0xda>
|
|
|
8005992: bf00 nop
|
|
|
8005994: dfbffffe .word 0xdfbffffe
|
|
|
|
|
|
08005998 <_fflush_r>:
|
|
|
8005998: b538 push {r3, r4, r5, lr}
|
|
|
800599a: 690b ldr r3, [r1, #16]
|
|
|
800599c: 4605 mov r5, r0
|
|
|
800599e: 460c mov r4, r1
|
|
|
80059a0: b913 cbnz r3, 80059a8 <_fflush_r+0x10>
|
|
|
80059a2: 2500 movs r5, #0
|
|
|
80059a4: 4628 mov r0, r5
|
|
|
80059a6: bd38 pop {r3, r4, r5, pc}
|
|
|
80059a8: b118 cbz r0, 80059b2 <_fflush_r+0x1a>
|
|
|
80059aa: 6a03 ldr r3, [r0, #32]
|
|
|
80059ac: b90b cbnz r3, 80059b2 <_fflush_r+0x1a>
|
|
|
80059ae: f7ff fc8f bl 80052d0 <__sinit>
|
|
|
80059b2: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
|
80059b6: 2b00 cmp r3, #0
|
|
|
80059b8: d0f3 beq.n 80059a2 <_fflush_r+0xa>
|
|
|
80059ba: 6e62 ldr r2, [r4, #100] ; 0x64
|
|
|
80059bc: 07d0 lsls r0, r2, #31
|
|
|
80059be: d404 bmi.n 80059ca <_fflush_r+0x32>
|
|
|
80059c0: 0599 lsls r1, r3, #22
|
|
|
80059c2: d402 bmi.n 80059ca <_fflush_r+0x32>
|
|
|
80059c4: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
|
80059c6: f7ff fe66 bl 8005696 <__retarget_lock_acquire_recursive>
|
|
|
80059ca: 4628 mov r0, r5
|
|
|
80059cc: 4621 mov r1, r4
|
|
|
80059ce: f7ff ff5d bl 800588c <__sflush_r>
|
|
|
80059d2: 6e63 ldr r3, [r4, #100] ; 0x64
|
|
|
80059d4: 07da lsls r2, r3, #31
|
|
|
80059d6: 4605 mov r5, r0
|
|
|
80059d8: d4e4 bmi.n 80059a4 <_fflush_r+0xc>
|
|
|
80059da: 89a3 ldrh r3, [r4, #12]
|
|
|
80059dc: 059b lsls r3, r3, #22
|
|
|
80059de: d4e1 bmi.n 80059a4 <_fflush_r+0xc>
|
|
|
80059e0: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
|
80059e2: f7ff fe59 bl 8005698 <__retarget_lock_release_recursive>
|
|
|
80059e6: e7dd b.n 80059a4 <_fflush_r+0xc>
|
|
|
|
|
|
080059e8 <__swhatbuf_r>:
|
|
|
80059e8: b570 push {r4, r5, r6, lr}
|
|
|
80059ea: 460c mov r4, r1
|
|
|
80059ec: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
|
80059f0: 2900 cmp r1, #0
|
|
|
80059f2: b096 sub sp, #88 ; 0x58
|
|
|
80059f4: 4615 mov r5, r2
|
|
|
80059f6: 461e mov r6, r3
|
|
|
80059f8: da0d bge.n 8005a16 <__swhatbuf_r+0x2e>
|
|
|
80059fa: 89a3 ldrh r3, [r4, #12]
|
|
|
80059fc: f013 0f80 tst.w r3, #128 ; 0x80
|
|
|
8005a00: f04f 0100 mov.w r1, #0
|
|
|
8005a04: bf0c ite eq
|
|
|
8005a06: f44f 6380 moveq.w r3, #1024 ; 0x400
|
|
|
8005a0a: 2340 movne r3, #64 ; 0x40
|
|
|
8005a0c: 2000 movs r0, #0
|
|
|
8005a0e: 6031 str r1, [r6, #0]
|
|
|
8005a10: 602b str r3, [r5, #0]
|
|
|
8005a12: b016 add sp, #88 ; 0x58
|
|
|
8005a14: bd70 pop {r4, r5, r6, pc}
|
|
|
8005a16: 466a mov r2, sp
|
|
|
8005a18: f000 f848 bl 8005aac <_fstat_r>
|
|
|
8005a1c: 2800 cmp r0, #0
|
|
|
8005a1e: dbec blt.n 80059fa <__swhatbuf_r+0x12>
|
|
|
8005a20: 9901 ldr r1, [sp, #4]
|
|
|
8005a22: f401 4170 and.w r1, r1, #61440 ; 0xf000
|
|
|
8005a26: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000
|
|
|
8005a2a: 4259 negs r1, r3
|
|
|
8005a2c: 4159 adcs r1, r3
|
|
|
8005a2e: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
|
8005a32: e7eb b.n 8005a0c <__swhatbuf_r+0x24>
|
|
|
|
|
|
08005a34 <__smakebuf_r>:
|
|
|
8005a34: 898b ldrh r3, [r1, #12]
|
|
|
8005a36: b573 push {r0, r1, r4, r5, r6, lr}
|
|
|
8005a38: 079d lsls r5, r3, #30
|
|
|
8005a3a: 4606 mov r6, r0
|
|
|
8005a3c: 460c mov r4, r1
|
|
|
8005a3e: d507 bpl.n 8005a50 <__smakebuf_r+0x1c>
|
|
|
8005a40: f104 0347 add.w r3, r4, #71 ; 0x47
|
|
|
8005a44: 6023 str r3, [r4, #0]
|
|
|
8005a46: 6123 str r3, [r4, #16]
|
|
|
8005a48: 2301 movs r3, #1
|
|
|
8005a4a: 6163 str r3, [r4, #20]
|
|
|
8005a4c: b002 add sp, #8
|
|
|
8005a4e: bd70 pop {r4, r5, r6, pc}
|
|
|
8005a50: ab01 add r3, sp, #4
|
|
|
8005a52: 466a mov r2, sp
|
|
|
8005a54: f7ff ffc8 bl 80059e8 <__swhatbuf_r>
|
|
|
8005a58: 9900 ldr r1, [sp, #0]
|
|
|
8005a5a: 4605 mov r5, r0
|
|
|
8005a5c: 4630 mov r0, r6
|
|
|
8005a5e: f7ff fe89 bl 8005774 <_malloc_r>
|
|
|
8005a62: b948 cbnz r0, 8005a78 <__smakebuf_r+0x44>
|
|
|
8005a64: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
|
8005a68: 059a lsls r2, r3, #22
|
|
|
8005a6a: d4ef bmi.n 8005a4c <__smakebuf_r+0x18>
|
|
|
8005a6c: f023 0303 bic.w r3, r3, #3
|
|
|
8005a70: f043 0302 orr.w r3, r3, #2
|
|
|
8005a74: 81a3 strh r3, [r4, #12]
|
|
|
8005a76: e7e3 b.n 8005a40 <__smakebuf_r+0xc>
|
|
|
8005a78: 89a3 ldrh r3, [r4, #12]
|
|
|
8005a7a: 6020 str r0, [r4, #0]
|
|
|
8005a7c: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
|
8005a80: 81a3 strh r3, [r4, #12]
|
|
|
8005a82: 9b00 ldr r3, [sp, #0]
|
|
|
8005a84: 6163 str r3, [r4, #20]
|
|
|
8005a86: 9b01 ldr r3, [sp, #4]
|
|
|
8005a88: 6120 str r0, [r4, #16]
|
|
|
8005a8a: b15b cbz r3, 8005aa4 <__smakebuf_r+0x70>
|
|
|
8005a8c: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
|
8005a90: 4630 mov r0, r6
|
|
|
8005a92: f000 f81d bl 8005ad0 <_isatty_r>
|
|
|
8005a96: b128 cbz r0, 8005aa4 <__smakebuf_r+0x70>
|
|
|
8005a98: 89a3 ldrh r3, [r4, #12]
|
|
|
8005a9a: f023 0303 bic.w r3, r3, #3
|
|
|
8005a9e: f043 0301 orr.w r3, r3, #1
|
|
|
8005aa2: 81a3 strh r3, [r4, #12]
|
|
|
8005aa4: 89a3 ldrh r3, [r4, #12]
|
|
|
8005aa6: 431d orrs r5, r3
|
|
|
8005aa8: 81a5 strh r5, [r4, #12]
|
|
|
8005aaa: e7cf b.n 8005a4c <__smakebuf_r+0x18>
|
|
|
|
|
|
08005aac <_fstat_r>:
|
|
|
8005aac: b538 push {r3, r4, r5, lr}
|
|
|
8005aae: 4d07 ldr r5, [pc, #28] ; (8005acc <_fstat_r+0x20>)
|
|
|
8005ab0: 2300 movs r3, #0
|
|
|
8005ab2: 4604 mov r4, r0
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8005ab4: 4608 mov r0, r1
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8005ab6: 4611 mov r1, r2
|
|
|
8005ab8: 602b str r3, [r5, #0]
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8005aba: f7fb f9b2 bl 8000e22 <_fstat>
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8005abe: 1c43 adds r3, r0, #1
|
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8005ac0: d102 bne.n 8005ac8 <_fstat_r+0x1c>
|
|
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8005ac2: 682b ldr r3, [r5, #0]
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|
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8005ac4: b103 cbz r3, 8005ac8 <_fstat_r+0x1c>
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|
|
8005ac6: 6023 str r3, [r4, #0]
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|
|
8005ac8: bd38 pop {r3, r4, r5, pc}
|
|
|
8005aca: bf00 nop
|
|
|
8005acc: 2000035c .word 0x2000035c
|
|
|
|
|
|
08005ad0 <_isatty_r>:
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|
|
8005ad0: b538 push {r3, r4, r5, lr}
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|
|
8005ad2: 4d06 ldr r5, [pc, #24] ; (8005aec <_isatty_r+0x1c>)
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|
|
8005ad4: 2300 movs r3, #0
|
|
|
8005ad6: 4604 mov r4, r0
|
|
|
8005ad8: 4608 mov r0, r1
|
|
|
8005ada: 602b str r3, [r5, #0]
|
|
|
8005adc: f7fb f9b1 bl 8000e42 <_isatty>
|
|
|
8005ae0: 1c43 adds r3, r0, #1
|
|
|
8005ae2: d102 bne.n 8005aea <_isatty_r+0x1a>
|
|
|
8005ae4: 682b ldr r3, [r5, #0]
|
|
|
8005ae6: b103 cbz r3, 8005aea <_isatty_r+0x1a>
|
|
|
8005ae8: 6023 str r3, [r4, #0]
|
|
|
8005aea: bd38 pop {r3, r4, r5, pc}
|
|
|
8005aec: 2000035c .word 0x2000035c
|
|
|
|
|
|
08005af0 <_sbrk_r>:
|
|
|
8005af0: b538 push {r3, r4, r5, lr}
|
|
|
8005af2: 4d06 ldr r5, [pc, #24] ; (8005b0c <_sbrk_r+0x1c>)
|
|
|
8005af4: 2300 movs r3, #0
|
|
|
8005af6: 4604 mov r4, r0
|
|
|
8005af8: 4608 mov r0, r1
|
|
|
8005afa: 602b str r3, [r5, #0]
|
|
|
8005afc: f7fb f9ba bl 8000e74 <_sbrk>
|
|
|
8005b00: 1c43 adds r3, r0, #1
|
|
|
8005b02: d102 bne.n 8005b0a <_sbrk_r+0x1a>
|
|
|
8005b04: 682b ldr r3, [r5, #0]
|
|
|
8005b06: b103 cbz r3, 8005b0a <_sbrk_r+0x1a>
|
|
|
8005b08: 6023 str r3, [r4, #0]
|
|
|
8005b0a: bd38 pop {r3, r4, r5, pc}
|
|
|
8005b0c: 2000035c .word 0x2000035c
|
|
|
|
|
|
08005b10 <_init>:
|
|
|
8005b10: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
8005b12: bf00 nop
|
|
|
8005b14: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
8005b16: bc08 pop {r3}
|
|
|
8005b18: 469e mov lr, r3
|
|
|
8005b1a: 4770 bx lr
|
|
|
|
|
|
08005b1c <_fini>:
|
|
|
8005b1c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
8005b1e: bf00 nop
|
|
|
8005b20: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
8005b22: bc08 pop {r3}
|
|
|
8005b24: 469e mov lr, r3
|
|
|
8005b26: 4770 bx lr
|
