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iotSmart/stm32receive/chaojiwudi/Debug/chaojiwudi.list

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chaojiwudi.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000018c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005cb4 0800018c 0800018c 0001018c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000120 08005e40 08005e40 00015e40 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005f60 08005f60 0002006c 2**0
CONTENTS
4 .ARM 00000008 08005f60 08005f60 00015f60 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08005f68 08005f68 0002006c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005f68 08005f68 00015f68 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08005f6c 08005f6c 00015f6c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000006c 20000000 08005f70 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000038c 2000006c 08005fdc 0002006c 2**2
ALLOC
10 ._user_heap_stack 00000600 200003f8 08005fdc 000203f8 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002006c 2**0
CONTENTS, READONLY
12 .comment 00000043 00000000 00000000 0002009c 2**0
CONTENTS, READONLY
13 .debug_info 00011c6e 00000000 00000000 000200df 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 0000275f 00000000 00000000 00031d4d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00001038 00000000 00000000 000344b0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 00000ca3 00000000 00000000 000354e8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 000226bf 00000000 00000000 0003618b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 000130b8 00000000 00000000 0005884a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 000cfd97 00000000 00000000 0006b902 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 00004a14 00000000 00000000 0013b69c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000040 00000000 00000000 001400b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800018c <__do_global_dtors_aux>:
800018c: b510 push {r4, lr}
800018e: 4c05 ldr r4, [pc, #20] ; (80001a4 <__do_global_dtors_aux+0x18>)
8000190: 7823 ldrb r3, [r4, #0]
8000192: b933 cbnz r3, 80001a2 <__do_global_dtors_aux+0x16>
8000194: 4b04 ldr r3, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x1c>)
8000196: b113 cbz r3, 800019e <__do_global_dtors_aux+0x12>
8000198: 4804 ldr r0, [pc, #16] ; (80001ac <__do_global_dtors_aux+0x20>)
800019a: f3af 8000 nop.w
800019e: 2301 movs r3, #1
80001a0: 7023 strb r3, [r4, #0]
80001a2: bd10 pop {r4, pc}
80001a4: 2000006c .word 0x2000006c
80001a8: 00000000 .word 0x00000000
80001ac: 08005e28 .word 0x08005e28
080001b0 <frame_dummy>:
80001b0: b508 push {r3, lr}
80001b2: 4b03 ldr r3, [pc, #12] ; (80001c0 <frame_dummy+0x10>)
80001b4: b11b cbz r3, 80001be <frame_dummy+0xe>
80001b6: 4903 ldr r1, [pc, #12] ; (80001c4 <frame_dummy+0x14>)
80001b8: 4803 ldr r0, [pc, #12] ; (80001c8 <frame_dummy+0x18>)
80001ba: f3af 8000 nop.w
80001be: bd08 pop {r3, pc}
80001c0: 00000000 .word 0x00000000
80001c4: 20000070 .word 0x20000070
80001c8: 08005e28 .word 0x08005e28
080001cc <strlen>:
80001cc: 4603 mov r3, r0
80001ce: f813 2b01 ldrb.w r2, [r3], #1
80001d2: 2a00 cmp r2, #0
80001d4: d1fb bne.n 80001ce <strlen+0x2>
80001d6: 1a18 subs r0, r3, r0
80001d8: 3801 subs r0, #1
80001da: 4770 bx lr
080001dc <__aeabi_uldivmod>:
80001dc: b953 cbnz r3, 80001f4 <__aeabi_uldivmod+0x18>
80001de: b94a cbnz r2, 80001f4 <__aeabi_uldivmod+0x18>
80001e0: 2900 cmp r1, #0
80001e2: bf08 it eq
80001e4: 2800 cmpeq r0, #0
80001e6: bf1c itt ne
80001e8: f04f 31ff movne.w r1, #4294967295
80001ec: f04f 30ff movne.w r0, #4294967295
80001f0: f000 b970 b.w 80004d4 <__aeabi_idiv0>
80001f4: f1ad 0c08 sub.w ip, sp, #8
80001f8: e96d ce04 strd ip, lr, [sp, #-16]!
80001fc: f000 f806 bl 800020c <__udivmoddi4>
8000200: f8dd e004 ldr.w lr, [sp, #4]
8000204: e9dd 2302 ldrd r2, r3, [sp, #8]
8000208: b004 add sp, #16
800020a: 4770 bx lr
0800020c <__udivmoddi4>:
800020c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000210: 9e08 ldr r6, [sp, #32]
8000212: 460d mov r5, r1
8000214: 4604 mov r4, r0
8000216: 460f mov r7, r1
8000218: 2b00 cmp r3, #0
800021a: d14a bne.n 80002b2 <__udivmoddi4+0xa6>
800021c: 428a cmp r2, r1
800021e: 4694 mov ip, r2
8000220: d965 bls.n 80002ee <__udivmoddi4+0xe2>
8000222: fab2 f382 clz r3, r2
8000226: b143 cbz r3, 800023a <__udivmoddi4+0x2e>
8000228: fa02 fc03 lsl.w ip, r2, r3
800022c: f1c3 0220 rsb r2, r3, #32
8000230: 409f lsls r7, r3
8000232: fa20 f202 lsr.w r2, r0, r2
8000236: 4317 orrs r7, r2
8000238: 409c lsls r4, r3
800023a: ea4f 4e1c mov.w lr, ip, lsr #16
800023e: fa1f f58c uxth.w r5, ip
8000242: fbb7 f1fe udiv r1, r7, lr
8000246: 0c22 lsrs r2, r4, #16
8000248: fb0e 7711 mls r7, lr, r1, r7
800024c: ea42 4207 orr.w r2, r2, r7, lsl #16
8000250: fb01 f005 mul.w r0, r1, r5
8000254: 4290 cmp r0, r2
8000256: d90a bls.n 800026e <__udivmoddi4+0x62>
8000258: eb1c 0202 adds.w r2, ip, r2
800025c: f101 37ff add.w r7, r1, #4294967295
8000260: f080 811c bcs.w 800049c <__udivmoddi4+0x290>
8000264: 4290 cmp r0, r2
8000266: f240 8119 bls.w 800049c <__udivmoddi4+0x290>
800026a: 3902 subs r1, #2
800026c: 4462 add r2, ip
800026e: 1a12 subs r2, r2, r0
8000270: b2a4 uxth r4, r4
8000272: fbb2 f0fe udiv r0, r2, lr
8000276: fb0e 2210 mls r2, lr, r0, r2
800027a: ea44 4402 orr.w r4, r4, r2, lsl #16
800027e: fb00 f505 mul.w r5, r0, r5
8000282: 42a5 cmp r5, r4
8000284: d90a bls.n 800029c <__udivmoddi4+0x90>
8000286: eb1c 0404 adds.w r4, ip, r4
800028a: f100 32ff add.w r2, r0, #4294967295
800028e: f080 8107 bcs.w 80004a0 <__udivmoddi4+0x294>
8000292: 42a5 cmp r5, r4
8000294: f240 8104 bls.w 80004a0 <__udivmoddi4+0x294>
8000298: 4464 add r4, ip
800029a: 3802 subs r0, #2
800029c: ea40 4001 orr.w r0, r0, r1, lsl #16
80002a0: 1b64 subs r4, r4, r5
80002a2: 2100 movs r1, #0
80002a4: b11e cbz r6, 80002ae <__udivmoddi4+0xa2>
80002a6: 40dc lsrs r4, r3
80002a8: 2300 movs r3, #0
80002aa: e9c6 4300 strd r4, r3, [r6]
80002ae: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002b2: 428b cmp r3, r1
80002b4: d908 bls.n 80002c8 <__udivmoddi4+0xbc>
80002b6: 2e00 cmp r6, #0
80002b8: f000 80ed beq.w 8000496 <__udivmoddi4+0x28a>
80002bc: 2100 movs r1, #0
80002be: e9c6 0500 strd r0, r5, [r6]
80002c2: 4608 mov r0, r1
80002c4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c8: fab3 f183 clz r1, r3
80002cc: 2900 cmp r1, #0
80002ce: d149 bne.n 8000364 <__udivmoddi4+0x158>
80002d0: 42ab cmp r3, r5
80002d2: d302 bcc.n 80002da <__udivmoddi4+0xce>
80002d4: 4282 cmp r2, r0
80002d6: f200 80f8 bhi.w 80004ca <__udivmoddi4+0x2be>
80002da: 1a84 subs r4, r0, r2
80002dc: eb65 0203 sbc.w r2, r5, r3
80002e0: 2001 movs r0, #1
80002e2: 4617 mov r7, r2
80002e4: 2e00 cmp r6, #0
80002e6: d0e2 beq.n 80002ae <__udivmoddi4+0xa2>
80002e8: e9c6 4700 strd r4, r7, [r6]
80002ec: e7df b.n 80002ae <__udivmoddi4+0xa2>
80002ee: b902 cbnz r2, 80002f2 <__udivmoddi4+0xe6>
80002f0: deff udf #255 ; 0xff
80002f2: fab2 f382 clz r3, r2
80002f6: 2b00 cmp r3, #0
80002f8: f040 8090 bne.w 800041c <__udivmoddi4+0x210>
80002fc: 1a8a subs r2, r1, r2
80002fe: ea4f 471c mov.w r7, ip, lsr #16
8000302: fa1f fe8c uxth.w lr, ip
8000306: 2101 movs r1, #1
8000308: fbb2 f5f7 udiv r5, r2, r7
800030c: fb07 2015 mls r0, r7, r5, r2
8000310: 0c22 lsrs r2, r4, #16
8000312: ea42 4200 orr.w r2, r2, r0, lsl #16
8000316: fb0e f005 mul.w r0, lr, r5
800031a: 4290 cmp r0, r2
800031c: d908 bls.n 8000330 <__udivmoddi4+0x124>
800031e: eb1c 0202 adds.w r2, ip, r2
8000322: f105 38ff add.w r8, r5, #4294967295
8000326: d202 bcs.n 800032e <__udivmoddi4+0x122>
8000328: 4290 cmp r0, r2
800032a: f200 80cb bhi.w 80004c4 <__udivmoddi4+0x2b8>
800032e: 4645 mov r5, r8
8000330: 1a12 subs r2, r2, r0
8000332: b2a4 uxth r4, r4
8000334: fbb2 f0f7 udiv r0, r2, r7
8000338: fb07 2210 mls r2, r7, r0, r2
800033c: ea44 4402 orr.w r4, r4, r2, lsl #16
8000340: fb0e fe00 mul.w lr, lr, r0
8000344: 45a6 cmp lr, r4
8000346: d908 bls.n 800035a <__udivmoddi4+0x14e>
8000348: eb1c 0404 adds.w r4, ip, r4
800034c: f100 32ff add.w r2, r0, #4294967295
8000350: d202 bcs.n 8000358 <__udivmoddi4+0x14c>
8000352: 45a6 cmp lr, r4
8000354: f200 80bb bhi.w 80004ce <__udivmoddi4+0x2c2>
8000358: 4610 mov r0, r2
800035a: eba4 040e sub.w r4, r4, lr
800035e: ea40 4005 orr.w r0, r0, r5, lsl #16
8000362: e79f b.n 80002a4 <__udivmoddi4+0x98>
8000364: f1c1 0720 rsb r7, r1, #32
8000368: 408b lsls r3, r1
800036a: fa22 fc07 lsr.w ip, r2, r7
800036e: ea4c 0c03 orr.w ip, ip, r3
8000372: fa05 f401 lsl.w r4, r5, r1
8000376: fa20 f307 lsr.w r3, r0, r7
800037a: 40fd lsrs r5, r7
800037c: ea4f 491c mov.w r9, ip, lsr #16
8000380: 4323 orrs r3, r4
8000382: fbb5 f8f9 udiv r8, r5, r9
8000386: fa1f fe8c uxth.w lr, ip
800038a: fb09 5518 mls r5, r9, r8, r5
800038e: 0c1c lsrs r4, r3, #16
8000390: ea44 4405 orr.w r4, r4, r5, lsl #16
8000394: fb08 f50e mul.w r5, r8, lr
8000398: 42a5 cmp r5, r4
800039a: fa02 f201 lsl.w r2, r2, r1
800039e: fa00 f001 lsl.w r0, r0, r1
80003a2: d90b bls.n 80003bc <__udivmoddi4+0x1b0>
80003a4: eb1c 0404 adds.w r4, ip, r4
80003a8: f108 3aff add.w sl, r8, #4294967295
80003ac: f080 8088 bcs.w 80004c0 <__udivmoddi4+0x2b4>
80003b0: 42a5 cmp r5, r4
80003b2: f240 8085 bls.w 80004c0 <__udivmoddi4+0x2b4>
80003b6: f1a8 0802 sub.w r8, r8, #2
80003ba: 4464 add r4, ip
80003bc: 1b64 subs r4, r4, r5
80003be: b29d uxth r5, r3
80003c0: fbb4 f3f9 udiv r3, r4, r9
80003c4: fb09 4413 mls r4, r9, r3, r4
80003c8: ea45 4404 orr.w r4, r5, r4, lsl #16
80003cc: fb03 fe0e mul.w lr, r3, lr
80003d0: 45a6 cmp lr, r4
80003d2: d908 bls.n 80003e6 <__udivmoddi4+0x1da>
80003d4: eb1c 0404 adds.w r4, ip, r4
80003d8: f103 35ff add.w r5, r3, #4294967295
80003dc: d26c bcs.n 80004b8 <__udivmoddi4+0x2ac>
80003de: 45a6 cmp lr, r4
80003e0: d96a bls.n 80004b8 <__udivmoddi4+0x2ac>
80003e2: 3b02 subs r3, #2
80003e4: 4464 add r4, ip
80003e6: ea43 4308 orr.w r3, r3, r8, lsl #16
80003ea: fba3 9502 umull r9, r5, r3, r2
80003ee: eba4 040e sub.w r4, r4, lr
80003f2: 42ac cmp r4, r5
80003f4: 46c8 mov r8, r9
80003f6: 46ae mov lr, r5
80003f8: d356 bcc.n 80004a8 <__udivmoddi4+0x29c>
80003fa: d053 beq.n 80004a4 <__udivmoddi4+0x298>
80003fc: b156 cbz r6, 8000414 <__udivmoddi4+0x208>
80003fe: ebb0 0208 subs.w r2, r0, r8
8000402: eb64 040e sbc.w r4, r4, lr
8000406: fa04 f707 lsl.w r7, r4, r7
800040a: 40ca lsrs r2, r1
800040c: 40cc lsrs r4, r1
800040e: 4317 orrs r7, r2
8000410: e9c6 7400 strd r7, r4, [r6]
8000414: 4618 mov r0, r3
8000416: 2100 movs r1, #0
8000418: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800041c: f1c3 0120 rsb r1, r3, #32
8000420: fa02 fc03 lsl.w ip, r2, r3
8000424: fa20 f201 lsr.w r2, r0, r1
8000428: fa25 f101 lsr.w r1, r5, r1
800042c: 409d lsls r5, r3
800042e: 432a orrs r2, r5
8000430: ea4f 471c mov.w r7, ip, lsr #16
8000434: fa1f fe8c uxth.w lr, ip
8000438: fbb1 f0f7 udiv r0, r1, r7
800043c: fb07 1510 mls r5, r7, r0, r1
8000440: 0c11 lsrs r1, r2, #16
8000442: ea41 4105 orr.w r1, r1, r5, lsl #16
8000446: fb00 f50e mul.w r5, r0, lr
800044a: 428d cmp r5, r1
800044c: fa04 f403 lsl.w r4, r4, r3
8000450: d908 bls.n 8000464 <__udivmoddi4+0x258>
8000452: eb1c 0101 adds.w r1, ip, r1
8000456: f100 38ff add.w r8, r0, #4294967295
800045a: d22f bcs.n 80004bc <__udivmoddi4+0x2b0>
800045c: 428d cmp r5, r1
800045e: d92d bls.n 80004bc <__udivmoddi4+0x2b0>
8000460: 3802 subs r0, #2
8000462: 4461 add r1, ip
8000464: 1b49 subs r1, r1, r5
8000466: b292 uxth r2, r2
8000468: fbb1 f5f7 udiv r5, r1, r7
800046c: fb07 1115 mls r1, r7, r5, r1
8000470: ea42 4201 orr.w r2, r2, r1, lsl #16
8000474: fb05 f10e mul.w r1, r5, lr
8000478: 4291 cmp r1, r2
800047a: d908 bls.n 800048e <__udivmoddi4+0x282>
800047c: eb1c 0202 adds.w r2, ip, r2
8000480: f105 38ff add.w r8, r5, #4294967295
8000484: d216 bcs.n 80004b4 <__udivmoddi4+0x2a8>
8000486: 4291 cmp r1, r2
8000488: d914 bls.n 80004b4 <__udivmoddi4+0x2a8>
800048a: 3d02 subs r5, #2
800048c: 4462 add r2, ip
800048e: 1a52 subs r2, r2, r1
8000490: ea45 4100 orr.w r1, r5, r0, lsl #16
8000494: e738 b.n 8000308 <__udivmoddi4+0xfc>
8000496: 4631 mov r1, r6
8000498: 4630 mov r0, r6
800049a: e708 b.n 80002ae <__udivmoddi4+0xa2>
800049c: 4639 mov r1, r7
800049e: e6e6 b.n 800026e <__udivmoddi4+0x62>
80004a0: 4610 mov r0, r2
80004a2: e6fb b.n 800029c <__udivmoddi4+0x90>
80004a4: 4548 cmp r0, r9
80004a6: d2a9 bcs.n 80003fc <__udivmoddi4+0x1f0>
80004a8: ebb9 0802 subs.w r8, r9, r2
80004ac: eb65 0e0c sbc.w lr, r5, ip
80004b0: 3b01 subs r3, #1
80004b2: e7a3 b.n 80003fc <__udivmoddi4+0x1f0>
80004b4: 4645 mov r5, r8
80004b6: e7ea b.n 800048e <__udivmoddi4+0x282>
80004b8: 462b mov r3, r5
80004ba: e794 b.n 80003e6 <__udivmoddi4+0x1da>
80004bc: 4640 mov r0, r8
80004be: e7d1 b.n 8000464 <__udivmoddi4+0x258>
80004c0: 46d0 mov r8, sl
80004c2: e77b b.n 80003bc <__udivmoddi4+0x1b0>
80004c4: 3d02 subs r5, #2
80004c6: 4462 add r2, ip
80004c8: e732 b.n 8000330 <__udivmoddi4+0x124>
80004ca: 4608 mov r0, r1
80004cc: e70a b.n 80002e4 <__udivmoddi4+0xd8>
80004ce: 4464 add r4, ip
80004d0: 3802 subs r0, #2
80004d2: e742 b.n 800035a <__udivmoddi4+0x14e>
080004d4 <__aeabi_idiv0>:
80004d4: 4770 bx lr
80004d6: bf00 nop
080004d8 <LoRa_SendCmd>:
* uint8_t *result，期望获得的结果
* uint32_t timeOut，等待期望结果的时间
* uint8_t isPrintf，是否打印 Log
*/
void LoRa_SendCmd(uint8_t *cmd, uint8_t *result, uint32_t timeOut, uint8_t isPrintf)
{
80004d8: b580 push {r7, lr}
80004da: b084 sub sp, #16
80004dc: af00 add r7, sp, #0
80004de: 60f8 str r0, [r7, #12]
80004e0: 60b9 str r1, [r7, #8]
80004e2: 607a str r2, [r7, #4]
80004e4: 70fb strb r3, [r7, #3]
// char *pos;
HAL_UART_Transmit(&hlpuart1, cmd, strlen((const char *)cmd), 0xff); // 发送AT 指令
80004e6: 68f8 ldr r0, [r7, #12]
80004e8: f7ff fe70 bl 80001cc <strlen>
80004ec: 4603 mov r3, r0
80004ee: b29a uxth r2, r3
80004f0: 23ff movs r3, #255 ; 0xff
80004f2: 68f9 ldr r1, [r7, #12]
80004f4: 4804 ldr r0, [pc, #16] ; (8000508 <LoRa_SendCmd+0x30>)
80004f6: f003 fb71 bl 8003bdc <HAL_UART_Transmit>
//HAL_UART_Receive_IT(&hlpuart1, bRxBufferUart1, 1); // 启动低功耗串口接收中断
HAL_Delay(timeOut); // 延时等待
80004fa: 6878 ldr r0, [r7, #4]
80004fc: f000 fe40 bl 8001180 <HAL_Delay>
// // error 或者无应答，再次发送
// HAL_UART_Receive_IT(&hlpuart1, bRxBufferUart1, 1); // 启动低功耗串口接收中断
// HAL_Delay(timeOut);
// }
// }
}
8000500: bf00 nop
8000502: 3710 adds r7, #16
8000504: 46bd mov sp, r7
8000506: bd80 pop {r7, pc}
8000508: 20000088 .word 0x20000088
0800050c <LoRa_T_V_Attach>:
* uint8_t isPrintf:是否打印 Log
* uint8_t isReboot:是否重启
* 模块地址：0xFFFF 通信信道：10 发射功率：11dbm
*/
void LoRa_T_V_Attach(uint8_t isPrintf, uint8_t isReboot)
{
800050c: b580 push {r7, lr}
800050e: b082 sub sp, #8
8000510: af00 add r7, sp, #0
8000512: 4603 mov r3, r0
8000514: 460a mov r2, r1
8000516: 71fb strb r3, [r7, #7]
8000518: 4613 mov r3, r2
800051a: 71bb strb r3, [r7, #6]
if (isReboot == 1)
800051c: 79bb ldrb r3, [r7, #6]
800051e: 2b01 cmp r3, #1
8000520: d143 bne.n 80005aa <LoRa_T_V_Attach+0x9e>
{
//HAL_GPIO_WritePin(PA0_GPIO_Port, PA0_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_SET);
8000522: 2201 movs r2, #1
8000524: 2101 movs r1, #1
8000526: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800052a: f001 f957 bl 80017dc <HAL_GPIO_WritePin>
HAL_Delay(1000);
800052e: f44f 707a mov.w r0, #1000 ; 0x3e8
8000532: f000 fe25 bl 8001180 <HAL_Delay>
LoRa_SendCmd((uint8_t *)"AT+UART=7,0\r\n", (uint8_t *)"OK",
8000536: 4b1f ldr r3, [pc, #124] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
8000538: 681a ldr r2, [r3, #0]
800053a: 79fb ldrb r3, [r7, #7]
800053c: 491e ldr r1, [pc, #120] ; (80005b8 <LoRa_T_V_Attach+0xac>)
800053e: 481f ldr r0, [pc, #124] ; (80005bc <LoRa_T_V_Attach+0xb0>)
8000540: f7ff ffca bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
LoRa_SendCmd((uint8_t *)"AT+WLRATE=11,5\r\n", (uint8_t *)"OK",
8000544: 4b1b ldr r3, [pc, #108] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
8000546: 681a ldr r2, [r3, #0]
8000548: 79fb ldrb r3, [r7, #7]
800054a: 491b ldr r1, [pc, #108] ; (80005b8 <LoRa_T_V_Attach+0xac>)
800054c: 481c ldr r0, [pc, #112] ; (80005c0 <LoRa_T_V_Attach+0xb4>)
800054e: f7ff ffc3 bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
LoRa_SendCmd((uint8_t *)"AT+TPOWER=0\r\n", (uint8_t *)"OK",
8000552: 4b18 ldr r3, [pc, #96] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
8000554: 681a ldr r2, [r3, #0]
8000556: 79fb ldrb r3, [r7, #7]
8000558: 4917 ldr r1, [pc, #92] ; (80005b8 <LoRa_T_V_Attach+0xac>)
800055a: 481a ldr r0, [pc, #104] ; (80005c4 <LoRa_T_V_Attach+0xb8>)
800055c: f7ff ffbc bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
LoRa_SendCmd((uint8_t *)"AT+TMODE=0\r\n", (uint8_t *)"OK",
8000560: 4b14 ldr r3, [pc, #80] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
8000562: 681a ldr r2, [r3, #0]
8000564: 79fb ldrb r3, [r7, #7]
8000566: 4914 ldr r1, [pc, #80] ; (80005b8 <LoRa_T_V_Attach+0xac>)
8000568: 4817 ldr r0, [pc, #92] ; (80005c8 <LoRa_T_V_Attach+0xbc>)
800056a: f7ff ffb5 bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
LoRa_SendCmd((uint8_t *)"AT+WLTIME=0\r\n", (uint8_t *)"OK",
800056e: 4b11 ldr r3, [pc, #68] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
8000570: 681a ldr r2, [r3, #0]
8000572: 79fb ldrb r3, [r7, #7]
8000574: 4910 ldr r1, [pc, #64] ; (80005b8 <LoRa_T_V_Attach+0xac>)
8000576: 4815 ldr r0, [pc, #84] ; (80005cc <LoRa_T_V_Attach+0xc0>)
8000578: f7ff ffae bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
LoRa_SendCmd((uint8_t *)"AT+CWMODE=0\r\n", (uint8_t *)"OK",
800057c: 4b0d ldr r3, [pc, #52] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
800057e: 681a ldr r2, [r3, #0]
8000580: 79fb ldrb r3, [r7, #7]
8000582: 490d ldr r1, [pc, #52] ; (80005b8 <LoRa_T_V_Attach+0xac>)
8000584: 4812 ldr r0, [pc, #72] ; (80005d0 <LoRa_T_V_Attach+0xc4>)
8000586: f7ff ffa7 bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
LoRa_SendCmd((uint8_t *)"AT+ADDR=FF,FF\r\n", (uint8_t *)"OK",
800058a: 4b0a ldr r3, [pc, #40] ; (80005b4 <LoRa_T_V_Attach+0xa8>)
800058c: 681a ldr r2, [r3, #0]
800058e: 79fb ldrb r3, [r7, #7]
8000590: 4909 ldr r1, [pc, #36] ; (80005b8 <LoRa_T_V_Attach+0xac>)
8000592: 4810 ldr r0, [pc, #64] ; (80005d4 <LoRa_T_V_Attach+0xc8>)
8000594: f7ff ffa0 bl 80004d8 <LoRa_SendCmd>
DefaultTimeout, isPrintf);
//HAL_GPIO_WritePin(PA0_GPIO_Port, PA0_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
8000598: 2200 movs r2, #0
800059a: 2101 movs r1, #1
800059c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80005a0: f001 f91c bl 80017dc <HAL_GPIO_WritePin>
printf("Attach!\r\n");
80005a4: 480c ldr r0, [pc, #48] ; (80005d8 <LoRa_T_V_Attach+0xcc>)
80005a6: f005 f8a9 bl 80056fc <puts>
}
}
80005aa: bf00 nop
80005ac: 3708 adds r7, #8
80005ae: 46bd mov sp, r7
80005b0: bd80 pop {r7, pc}
80005b2: bf00 nop
80005b4: 20000000 .word 0x20000000
80005b8: 08005e40 .word 0x08005e40
80005bc: 08005e44 .word 0x08005e44
80005c0: 08005ec4 .word 0x08005ec4
80005c4: 08005e68 .word 0x08005e68
80005c8: 08005e78 .word 0x08005e78
80005cc: 08005e88 .word 0x08005e88
80005d0: 08005e98 .word 0x08005e98
80005d4: 08005ed8 .word 0x08005ed8
80005d8: 08005eb8 .word 0x08005eb8
080005dc <Serial1_SendArray>:
static void MX_USART1_UART_Init(void);
static void MX_TIM1_Init(void);
static void MX_USART2_UART_Init(void);
/* USER CODE BEGIN PFP */
void Serial1_SendArray(uint8_t *Array, uint16_t Length)
{
80005dc: b580 push {r7, lr}
80005de: b082 sub sp, #8
80005e0: af00 add r7, sp, #0
80005e2: 6078 str r0, [r7, #4]
80005e4: 460b mov r3, r1
80005e6: 807b strh r3, [r7, #2]
HAL_UART_Transmit_IT(&huart1, Array, Length);
80005e8: 887b ldrh r3, [r7, #2]
80005ea: 461a mov r2, r3
80005ec: 6879 ldr r1, [r7, #4]
80005ee: 4803 ldr r0, [pc, #12] ; (80005fc <Serial1_SendArray+0x20>)
80005f0: f003 fb7e bl 8003cf0 <HAL_UART_Transmit_IT>
}
80005f4: bf00 nop
80005f6: 3708 adds r7, #8
80005f8: 46bd mov sp, r7
80005fa: bd80 pop {r7, pc}
80005fc: 20000110 .word 0x20000110
08000600 <Seriallp_SendArray>:
void Seriallp_SendArray(uint8_t *Array, uint16_t Length)
{
8000600: b580 push {r7, lr}
8000602: b082 sub sp, #8
8000604: af00 add r7, sp, #0
8000606: 6078 str r0, [r7, #4]
8000608: 460b mov r3, r1
800060a: 807b strh r3, [r7, #2]
HAL_UART_Transmit_IT(&hlpuart1, Array, Length);
800060c: 887b ldrh r3, [r7, #2]
800060e: 461a mov r2, r3
8000610: 6879 ldr r1, [r7, #4]
8000612: 4803 ldr r0, [pc, #12] ; (8000620 <Seriallp_SendArray+0x20>)
8000614: f003 fb6c bl 8003cf0 <HAL_UART_Transmit_IT>
}
8000618: bf00 nop
800061a: 3708 adds r7, #8
800061c: 46bd mov sp, r7
800061e: bd80 pop {r7, pc}
8000620: 20000088 .word 0x20000088
08000624 <Serial2_SendArray>:
void Serial2_SendArray(uint8_t *Array, uint16_t Length)
{
8000624: b580 push {r7, lr}
8000626: b082 sub sp, #8
8000628: af00 add r7, sp, #0
800062a: 6078 str r0, [r7, #4]
800062c: 460b mov r3, r1
800062e: 807b strh r3, [r7, #2]
HAL_UART_Transmit_IT(&huart2, Array, Length);
8000630: 887b ldrh r3, [r7, #2]
8000632: 461a mov r2, r3
8000634: 6879 ldr r1, [r7, #4]
8000636: 4803 ldr r0, [pc, #12] ; (8000644 <Serial2_SendArray+0x20>)
8000638: f003 fb5a bl 8003cf0 <HAL_UART_Transmit_IT>
}
800063c: bf00 nop
800063e: 3708 adds r7, #8
8000640: 46bd mov sp, r7
8000642: bd80 pop {r7, pc}
8000644: 20000198 .word 0x20000198
08000648 <HAL_UART_RxCpltCallback>:
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle)
{
8000648: b580 push {r7, lr}
800064a: b082 sub sp, #8
800064c: af00 add r7, sp, #0
800064e: 6078 str r0, [r7, #4]
HAL_UART_Receive_IT(&huart1, Rarr, 5);
8000650: 2205 movs r2, #5
8000652: 4906 ldr r1, [pc, #24] ; (800066c <HAL_UART_RxCpltCallback+0x24>)
8000654: 4806 ldr r0, [pc, #24] ; (8000670 <HAL_UART_RxCpltCallback+0x28>)
8000656: f003 fba9 bl 8003dac <HAL_UART_Receive_IT>
Serial1_SendArray(Rarr, sizeof(Rarr) / sizeof(Rarr[0]));
800065a: 2132 movs r1, #50 ; 0x32
800065c: 4803 ldr r0, [pc, #12] ; (800066c <HAL_UART_RxCpltCallback+0x24>)
800065e: f7ff ffbd bl 80005dc <Serial1_SendArray>
}
8000662: bf00 nop
8000664: 3708 adds r7, #8
8000666: 46bd mov sp, r7
8000668: bd80 pop {r7, pc}
800066a: bf00 nop
800066c: 20000270 .word 0x20000270
8000670: 20000110 .word 0x20000110
08000674 <HAL_UARTEx_RxEventCallback>:
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8000674: b580 push {r7, lr}
8000676: b082 sub sp, #8
8000678: af00 add r7, sp, #0
800067a: 6078 str r0, [r7, #4]
800067c: 460b mov r3, r1
800067e: 807b strh r3, [r7, #2]
if (huart->Instance == USART1)
8000680: 687b ldr r3, [r7, #4]
8000682: 681b ldr r3, [r3, #0]
8000684: 4a1e ldr r2, [pc, #120] ; (8000700 <HAL_UARTEx_RxEventCallback+0x8c>)
8000686: 4293 cmp r3, r2
8000688: d10a bne.n 80006a0 <HAL_UARTEx_RxEventCallback+0x2c>
{
//Serial1_SendArray(Rarr, Size);
Seriallp_SendArray(Rarr, Size);
800068a: 887b ldrh r3, [r7, #2]
800068c: 4619 mov r1, r3
800068e: 481d ldr r0, [pc, #116] ; (8000704 <HAL_UARTEx_RxEventCallback+0x90>)
8000690: f7ff ffb6 bl 8000600 <Seriallp_SendArray>
HAL_UARTEx_ReceiveToIdle_IT(&huart1, Rarr, 50);
8000694: 2232 movs r2, #50 ; 0x32
8000696: 491b ldr r1, [pc, #108] ; (8000704 <HAL_UARTEx_RxEventCallback+0x90>)
8000698: 481b ldr r0, [pc, #108] ; (8000708 <HAL_UARTEx_RxEventCallback+0x94>)
800069a: f004 fec9 bl 8005430 <HAL_UARTEx_ReceiveToIdle_IT>
// uint8_t atCommand[50]={0};
// sprintf(atCommand, "AT+SEND=%d,%s\r\n", strlen(Rarr), Rarr);
// Serial1_SendArray(atCommand, strlen(atCommand));
// LoRa_SendCmd((uint8_t *)atCommand, (uint8_t *)"OK", 300, 1);
}
800069e: e02b b.n 80006f8 <HAL_UARTEx_RxEventCallback+0x84>
else if (huart->Instance == LPUART1)
80006a0: 687b ldr r3, [r7, #4]
80006a2: 681b ldr r3, [r3, #0]
80006a4: 4a19 ldr r2, [pc, #100] ; (800070c <HAL_UARTEx_RxEventCallback+0x98>)
80006a6: 4293 cmp r3, r2
80006a8: d126 bne.n 80006f8 <HAL_UARTEx_RxEventCallback+0x84>
Serial1_SendArray(Rarr, Size);
80006aa: 887b ldrh r3, [r7, #2]
80006ac: 4619 mov r1, r3
80006ae: 4815 ldr r0, [pc, #84] ; (8000704 <HAL_UARTEx_RxEventCallback+0x90>)
80006b0: f7ff ff94 bl 80005dc <Serial1_SendArray>
if(zt==0)
80006b4: 4b16 ldr r3, [pc, #88] ; (8000710 <HAL_UARTEx_RxEventCallback+0x9c>)
80006b6: 881b ldrh r3, [r3, #0]
80006b8: 2b00 cmp r3, #0
80006ba: d10a bne.n 80006d2 <HAL_UARTEx_RxEventCallback+0x5e>
pwmval=2000;
80006bc: 4b15 ldr r3, [pc, #84] ; (8000714 <HAL_UARTEx_RxEventCallback+0xa0>)
80006be: f44f 62fa mov.w r2, #2000 ; 0x7d0
80006c2: 801a strh r2, [r3, #0]
Serial2_SendArray("SOMEBODY HERE\r\n", strlen("SOMEBODY HERE\r\n"));
80006c4: 210f movs r1, #15
80006c6: 4814 ldr r0, [pc, #80] ; (8000718 <HAL_UARTEx_RxEventCallback+0xa4>)
80006c8: f7ff ffac bl 8000624 <Serial2_SendArray>
zt=1;
80006cc: 4b10 ldr r3, [pc, #64] ; (8000710 <HAL_UARTEx_RxEventCallback+0x9c>)
80006ce: 2201 movs r2, #1
80006d0: 801a strh r2, [r3, #0]
if(zt==1)
80006d2: 4b0f ldr r3, [pc, #60] ; (8000710 <HAL_UARTEx_RxEventCallback+0x9c>)
80006d4: 881b ldrh r3, [r3, #0]
80006d6: 2b01 cmp r3, #1
80006d8: d109 bne.n 80006ee <HAL_UARTEx_RxEventCallback+0x7a>
pwmval=0;
80006da: 4b0e ldr r3, [pc, #56] ; (8000714 <HAL_UARTEx_RxEventCallback+0xa0>)
80006dc: 2200 movs r2, #0
80006de: 801a strh r2, [r3, #0]
Serial2_SendArray("NOBODY HERE\r\n", strlen("NOBODY HERE\r\n"));
80006e0: 210d movs r1, #13
80006e2: 480e ldr r0, [pc, #56] ; (800071c <HAL_UARTEx_RxEventCallback+0xa8>)
80006e4: f7ff ff9e bl 8000624 <Serial2_SendArray>
zt=0;
80006e8: 4b09 ldr r3, [pc, #36] ; (8000710 <HAL_UARTEx_RxEventCallback+0x9c>)
80006ea: 2200 movs r2, #0
80006ec: 801a strh r2, [r3, #0]
HAL_UARTEx_ReceiveToIdle_IT(&hlpuart1, Rarr, 50);
80006ee: 2232 movs r2, #50 ; 0x32
80006f0: 4904 ldr r1, [pc, #16] ; (8000704 <HAL_UARTEx_RxEventCallback+0x90>)
80006f2: 480b ldr r0, [pc, #44] ; (8000720 <HAL_UARTEx_RxEventCallback+0xac>)
80006f4: f004 fe9c bl 8005430 <HAL_UARTEx_ReceiveToIdle_IT>
}
80006f8: bf00 nop
80006fa: 3708 adds r7, #8
80006fc: 46bd mov sp, r7
80006fe: bd80 pop {r7, pc}
8000700: 40013800 .word 0x40013800
8000704: 20000270 .word 0x20000270
8000708: 20000110 .word 0x20000110
800070c: 40008000 .word 0x40008000
8000710: 2000026e .word 0x2000026e
8000714: 2000026c .word 0x2000026c
8000718: 08005ef8 .word 0x08005ef8
800071c: 08005f08 .word 0x08005f08
8000720: 20000088 .word 0x20000088
08000724 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000724: b580 push {r7, lr}
8000726: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000728: f000 fcb5 bl 8001096 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800072c: f000 f838 bl 80007a0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000730: f000 f9be bl 8000ab0 <MX_GPIO_Init>
MX_LPUART1_UART_Init();
8000734: f000 f884 bl 8000840 <MX_LPUART1_UART_Init>
MX_USART1_UART_Init();
8000738: f000 f8ae bl 8000898 <MX_USART1_UART_Init>
MX_TIM1_Init();
800073c: f000 f90c bl 8000958 <MX_TIM1_Init>
MX_USART2_UART_Init();
8000740: f000 f8da bl 80008f8 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
HAL_UARTEx_ReceiveToIdle_IT(&huart1, Rarr, 50);
8000744: 2232 movs r2, #50 ; 0x32
8000746: 4911 ldr r1, [pc, #68] ; (800078c <main+0x68>)
8000748: 4811 ldr r0, [pc, #68] ; (8000790 <main+0x6c>)
800074a: f004 fe71 bl 8005430 <HAL_UARTEx_ReceiveToIdle_IT>
HAL_UARTEx_ReceiveToIdle_IT(&hlpuart1, Rarr, 50);
800074e: 2232 movs r2, #50 ; 0x32
8000750: 490e ldr r1, [pc, #56] ; (800078c <main+0x68>)
8000752: 4810 ldr r0, [pc, #64] ; (8000794 <main+0x70>)
8000754: f004 fe6c bl 8005430 <HAL_UARTEx_ReceiveToIdle_IT>
LoRa_T_V_Attach(1,1);
8000758: 2101 movs r1, #1
800075a: 2001 movs r0, #1
800075c: f7ff fed6 bl 800050c <LoRa_T_V_Attach>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
pwmval=2000;
8000760: 4b0d ldr r3, [pc, #52] ; (8000798 <main+0x74>)
8000762: f44f 62fa mov.w r2, #2000 ; 0x7d0
8000766: 801a strh r2, [r3, #0]
HAL_TIM_PWM_Start(&htim1,TIM_CHANNEL_1);
8000768: 2100 movs r1, #0
800076a: 480c ldr r0, [pc, #48] ; (800079c <main+0x78>)
800076c: f002 faac bl 8002cc8 <HAL_TIM_PWM_Start>
while (1)
{
__HAL_TIM_SetCompare(&htim1,TIM_CHANNEL_1,pwmval);
8000770: 4b09 ldr r3, [pc, #36] ; (8000798 <main+0x74>)
8000772: 881a ldrh r2, [r3, #0]
8000774: 4b09 ldr r3, [pc, #36] ; (800079c <main+0x78>)
8000776: 681b ldr r3, [r3, #0]
8000778: 635a str r2, [r3, #52] ; 0x34
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
//HAL_UART_Transmit(&hlpuart1, "HHHHH\r\n", strlen("HHHHH\r\n"),100);
HAL_Delay(20000);
800077a: f644 6020 movw r0, #20000 ; 0x4e20
800077e: f000 fcff bl 8001180 <HAL_Delay>
pwmval=0;
8000782: 4b05 ldr r3, [pc, #20] ; (8000798 <main+0x74>)
8000784: 2200 movs r2, #0
8000786: 801a strh r2, [r3, #0]
__HAL_TIM_SetCompare(&htim1,TIM_CHANNEL_1,pwmval);
8000788: e7f2 b.n 8000770 <main+0x4c>
800078a: bf00 nop
800078c: 20000270 .word 0x20000270
8000790: 20000110 .word 0x20000110
8000794: 20000088 .word 0x20000088
8000798: 2000026c .word 0x2000026c
800079c: 20000220 .word 0x20000220
080007a0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80007a0: b580 push {r7, lr}
80007a2: b096 sub sp, #88 ; 0x58
80007a4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80007a6: f107 0314 add.w r3, r7, #20
80007aa: 2244 movs r2, #68 ; 0x44
80007ac: 2100 movs r1, #0
80007ae: 4618 mov r0, r3
80007b0: f005 f884 bl 80058bc <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80007b4: 463b mov r3, r7
80007b6: 2200 movs r2, #0
80007b8: 601a str r2, [r3, #0]
80007ba: 605a str r2, [r3, #4]
80007bc: 609a str r2, [r3, #8]
80007be: 60da str r2, [r3, #12]
80007c0: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
80007c2: f44f 7000 mov.w r0, #512 ; 0x200
80007c6: f001 f82f bl 8001828 <HAL_PWREx_ControlVoltageScaling>
80007ca: 4603 mov r3, r0
80007cc: 2b00 cmp r3, #0
80007ce: d001 beq.n 80007d4 <SystemClock_Config+0x34>
{
Error_Handler();
80007d0: f000 f9ce bl 8000b70 <Error_Handler>
}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80007d4: 2301 movs r3, #1
80007d6: 617b str r3, [r7, #20]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80007d8: f44f 3380 mov.w r3, #65536 ; 0x10000
80007dc: 61bb str r3, [r7, #24]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80007de: 2302 movs r3, #2
80007e0: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80007e2: 2303 movs r3, #3
80007e4: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLM = 2;
80007e6: 2302 movs r3, #2
80007e8: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLN = 40;
80007ea: 2328 movs r3, #40 ; 0x28
80007ec: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
80007ee: 2307 movs r3, #7
80007f0: 64fb str r3, [r7, #76] ; 0x4c
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
80007f2: 2302 movs r3, #2
80007f4: 653b str r3, [r7, #80] ; 0x50
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
80007f6: 2302 movs r3, #2
80007f8: 657b str r3, [r7, #84] ; 0x54
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80007fa: f107 0314 add.w r3, r7, #20
80007fe: 4618 mov r0, r3
8000800: f001 f868 bl 80018d4 <HAL_RCC_OscConfig>
8000804: 4603 mov r3, r0
8000806: 2b00 cmp r3, #0
8000808: d001 beq.n 800080e <SystemClock_Config+0x6e>
{
Error_Handler();
800080a: f000 f9b1 bl 8000b70 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800080e: 230f movs r3, #15
8000810: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000812: 2303 movs r3, #3
8000814: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000816: 2300 movs r3, #0
8000818: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
800081a: f44f 63a0 mov.w r3, #1280 ; 0x500
800081e: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000820: 2300 movs r3, #0
8000822: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
8000824: 463b mov r3, r7
8000826: 2104 movs r1, #4
8000828: 4618 mov r0, r3
800082a: f001 fc67 bl 80020fc <HAL_RCC_ClockConfig>
800082e: 4603 mov r3, r0
8000830: 2b00 cmp r3, #0
8000832: d001 beq.n 8000838 <SystemClock_Config+0x98>
{
Error_Handler();
8000834: f000 f99c bl 8000b70 <Error_Handler>
}
}
8000838: bf00 nop
800083a: 3758 adds r7, #88 ; 0x58
800083c: 46bd mov sp, r7
800083e: bd80 pop {r7, pc}
08000840 <MX_LPUART1_UART_Init>:
* @brief LPUART1 Initialization Function
* @param None
* @retval None
*/
static void MX_LPUART1_UART_Init(void)
{
8000840: b580 push {r7, lr}
8000842: af00 add r7, sp, #0
/* USER CODE END LPUART1_Init 0 */
/* USER CODE BEGIN LPUART1_Init 1 */
/* USER CODE END LPUART1_Init 1 */
hlpuart1.Instance = LPUART1;
8000844: 4b12 ldr r3, [pc, #72] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
8000846: 4a13 ldr r2, [pc, #76] ; (8000894 <MX_LPUART1_UART_Init+0x54>)
8000848: 601a str r2, [r3, #0]
hlpuart1.Init.BaudRate = 115200;
800084a: 4b11 ldr r3, [pc, #68] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
800084c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000850: 605a str r2, [r3, #4]
hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
8000852: 4b0f ldr r3, [pc, #60] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
8000854: 2200 movs r2, #0
8000856: 609a str r2, [r3, #8]
hlpuart1.Init.StopBits = UART_STOPBITS_1;
8000858: 4b0d ldr r3, [pc, #52] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
800085a: 2200 movs r2, #0
800085c: 60da str r2, [r3, #12]
hlpuart1.Init.Parity = UART_PARITY_NONE;
800085e: 4b0c ldr r3, [pc, #48] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
8000860: 2200 movs r2, #0
8000862: 611a str r2, [r3, #16]
hlpuart1.Init.Mode = UART_MODE_TX_RX;
8000864: 4b0a ldr r3, [pc, #40] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
8000866: 220c movs r2, #12
8000868: 615a str r2, [r3, #20]
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800086a: 4b09 ldr r3, [pc, #36] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
800086c: 2200 movs r2, #0
800086e: 619a str r2, [r3, #24]
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000870: 4b07 ldr r3, [pc, #28] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
8000872: 2200 movs r2, #0
8000874: 621a str r2, [r3, #32]
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000876: 4b06 ldr r3, [pc, #24] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
8000878: 2200 movs r2, #0
800087a: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
800087c: 4804 ldr r0, [pc, #16] ; (8000890 <MX_LPUART1_UART_Init+0x50>)
800087e: f003 f95f bl 8003b40 <HAL_UART_Init>
8000882: 4603 mov r3, r0
8000884: 2b00 cmp r3, #0
8000886: d001 beq.n 800088c <MX_LPUART1_UART_Init+0x4c>
{
Error_Handler();
8000888: f000 f972 bl 8000b70 <Error_Handler>
}
/* USER CODE BEGIN LPUART1_Init 2 */
/* USER CODE END LPUART1_Init 2 */
}
800088c: bf00 nop
800088e: bd80 pop {r7, pc}
8000890: 20000088 .word 0x20000088
8000894: 40008000 .word 0x40008000
08000898 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8000898: b580 push {r7, lr}
800089a: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
800089c: 4b14 ldr r3, [pc, #80] ; (80008f0 <MX_USART1_UART_Init+0x58>)
800089e: 4a15 ldr r2, [pc, #84] ; (80008f4 <MX_USART1_UART_Init+0x5c>)
80008a0: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
80008a2: 4b13 ldr r3, [pc, #76] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008a4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80008a8: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
80008aa: 4b11 ldr r3, [pc, #68] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008ac: 2200 movs r2, #0
80008ae: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
80008b0: 4b0f ldr r3, [pc, #60] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008b2: 2200 movs r2, #0
80008b4: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
80008b6: 4b0e ldr r3, [pc, #56] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008b8: 2200 movs r2, #0
80008ba: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
80008bc: 4b0c ldr r3, [pc, #48] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008be: 220c movs r2, #12
80008c0: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80008c2: 4b0b ldr r3, [pc, #44] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008c4: 2200 movs r2, #0
80008c6: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80008c8: 4b09 ldr r3, [pc, #36] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008ca: 2200 movs r2, #0
80008cc: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80008ce: 4b08 ldr r3, [pc, #32] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008d0: 2200 movs r2, #0
80008d2: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80008d4: 4b06 ldr r3, [pc, #24] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008d6: 2200 movs r2, #0
80008d8: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
80008da: 4805 ldr r0, [pc, #20] ; (80008f0 <MX_USART1_UART_Init+0x58>)
80008dc: f003 f930 bl 8003b40 <HAL_UART_Init>
80008e0: 4603 mov r3, r0
80008e2: 2b00 cmp r3, #0
80008e4: d001 beq.n 80008ea <MX_USART1_UART_Init+0x52>
{
Error_Handler();
80008e6: f000 f943 bl 8000b70 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80008ea: bf00 nop
80008ec: bd80 pop {r7, pc}
80008ee: bf00 nop
80008f0: 20000110 .word 0x20000110
80008f4: 40013800 .word 0x40013800
080008f8 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
80008f8: b580 push {r7, lr}
80008fa: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
80008fc: 4b14 ldr r3, [pc, #80] ; (8000950 <MX_USART2_UART_Init+0x58>)
80008fe: 4a15 ldr r2, [pc, #84] ; (8000954 <MX_USART2_UART_Init+0x5c>)
8000900: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000902: 4b13 ldr r3, [pc, #76] ; (8000950 <MX_USART2_UART_Init+0x58>)
8000904: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000908: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800090a: 4b11 ldr r3, [pc, #68] ; (8000950 <MX_USART2_UART_Init+0x58>)
800090c: 2200 movs r2, #0
800090e: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000910: 4b0f ldr r3, [pc, #60] ; (8000950 <MX_USART2_UART_Init+0x58>)
8000912: 2200 movs r2, #0
8000914: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000916: 4b0e ldr r3, [pc, #56] ; (8000950 <MX_USART2_UART_Init+0x58>)
8000918: 2200 movs r2, #0
800091a: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
800091c: 4b0c ldr r3, [pc, #48] ; (8000950 <MX_USART2_UART_Init+0x58>)
800091e: 220c movs r2, #12
8000920: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000922: 4b0b ldr r3, [pc, #44] ; (8000950 <MX_USART2_UART_Init+0x58>)
8000924: 2200 movs r2, #0
8000926: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000928: 4b09 ldr r3, [pc, #36] ; (8000950 <MX_USART2_UART_Init+0x58>)
800092a: 2200 movs r2, #0
800092c: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
800092e: 4b08 ldr r3, [pc, #32] ; (8000950 <MX_USART2_UART_Init+0x58>)
8000930: 2200 movs r2, #0
8000932: 621a str r2, [r3, #32]
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000934: 4b06 ldr r3, [pc, #24] ; (8000950 <MX_USART2_UART_Init+0x58>)
8000936: 2200 movs r2, #0
8000938: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart2) != HAL_OK)
800093a: 4805 ldr r0, [pc, #20] ; (8000950 <MX_USART2_UART_Init+0x58>)
800093c: f003 f900 bl 8003b40 <HAL_UART_Init>
8000940: 4603 mov r3, r0
8000942: 2b00 cmp r3, #0
8000944: d001 beq.n 800094a <MX_USART2_UART_Init+0x52>
{
Error_Handler();
8000946: f000 f913 bl 8000b70 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
800094a: bf00 nop
800094c: bd80 pop {r7, pc}
800094e: bf00 nop
8000950: 20000198 .word 0x20000198
8000954: 40004400 .word 0x40004400
08000958 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000958: b580 push {r7, lr}
800095a: b09a sub sp, #104 ; 0x68
800095c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800095e: f107 0358 add.w r3, r7, #88 ; 0x58
8000962: 2200 movs r2, #0
8000964: 601a str r2, [r3, #0]
8000966: 605a str r2, [r3, #4]
8000968: 609a str r2, [r3, #8]
800096a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800096c: f107 034c add.w r3, r7, #76 ; 0x4c
8000970: 2200 movs r2, #0
8000972: 601a str r2, [r3, #0]
8000974: 605a str r2, [r3, #4]
8000976: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
8000978: f107 0330 add.w r3, r7, #48 ; 0x30
800097c: 2200 movs r2, #0
800097e: 601a str r2, [r3, #0]
8000980: 605a str r2, [r3, #4]
8000982: 609a str r2, [r3, #8]
8000984: 60da str r2, [r3, #12]
8000986: 611a str r2, [r3, #16]
8000988: 615a str r2, [r3, #20]
800098a: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
800098c: 1d3b adds r3, r7, #4
800098e: 222c movs r2, #44 ; 0x2c
8000990: 2100 movs r1, #0
8000992: 4618 mov r0, r3
8000994: f004 ff92 bl 80058bc <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000998: 4b43 ldr r3, [pc, #268] ; (8000aa8 <MX_TIM1_Init+0x150>)
800099a: 4a44 ldr r2, [pc, #272] ; (8000aac <MX_TIM1_Init+0x154>)
800099c: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
800099e: 4b42 ldr r3, [pc, #264] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009a0: 2200 movs r2, #0
80009a2: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80009a4: 4b40 ldr r3, [pc, #256] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009a6: 2200 movs r2, #0
80009a8: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
80009aa: 4b3f ldr r3, [pc, #252] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009ac: f64f 72ff movw r2, #65535 ; 0xffff
80009b0: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80009b2: 4b3d ldr r3, [pc, #244] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009b4: 2200 movs r2, #0
80009b6: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
80009b8: 4b3b ldr r3, [pc, #236] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009ba: 2200 movs r2, #0
80009bc: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80009be: 4b3a ldr r3, [pc, #232] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009c0: 2200 movs r2, #0
80009c2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
80009c4: 4838 ldr r0, [pc, #224] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009c6: f002 f8c7 bl 8002b58 <HAL_TIM_Base_Init>
80009ca: 4603 mov r3, r0
80009cc: 2b00 cmp r3, #0
80009ce: d001 beq.n 80009d4 <MX_TIM1_Init+0x7c>
{
Error_Handler();
80009d0: f000 f8ce bl 8000b70 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80009d4: f44f 5380 mov.w r3, #4096 ; 0x1000
80009d8: 65bb str r3, [r7, #88] ; 0x58
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
80009da: f107 0358 add.w r3, r7, #88 ; 0x58
80009de: 4619 mov r1, r3
80009e0: 4831 ldr r0, [pc, #196] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009e2: f002 fb63 bl 80030ac <HAL_TIM_ConfigClockSource>
80009e6: 4603 mov r3, r0
80009e8: 2b00 cmp r3, #0
80009ea: d001 beq.n 80009f0 <MX_TIM1_Init+0x98>
{
Error_Handler();
80009ec: f000 f8c0 bl 8000b70 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
80009f0: 482d ldr r0, [pc, #180] ; (8000aa8 <MX_TIM1_Init+0x150>)
80009f2: f002 f908 bl 8002c06 <HAL_TIM_PWM_Init>
80009f6: 4603 mov r3, r0
80009f8: 2b00 cmp r3, #0
80009fa: d001 beq.n 8000a00 <MX_TIM1_Init+0xa8>
{
Error_Handler();
80009fc: f000 f8b8 bl 8000b70 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000a00: 2300 movs r3, #0
8000a02: 64fb str r3, [r7, #76] ; 0x4c
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8000a04: 2300 movs r3, #0
8000a06: 653b str r3, [r7, #80] ; 0x50
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000a08: 2300 movs r3, #0
8000a0a: 657b str r3, [r7, #84] ; 0x54
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000a0c: f107 034c add.w r3, r7, #76 ; 0x4c
8000a10: 4619 mov r1, r3
8000a12: 4825 ldr r0, [pc, #148] ; (8000aa8 <MX_TIM1_Init+0x150>)
8000a14: f002 ffb6 bl 8003984 <HAL_TIMEx_MasterConfigSynchronization>
8000a18: 4603 mov r3, r0
8000a1a: 2b00 cmp r3, #0
8000a1c: d001 beq.n 8000a22 <MX_TIM1_Init+0xca>
{
Error_Handler();
8000a1e: f000 f8a7 bl 8000b70 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000a22: 2360 movs r3, #96 ; 0x60
8000a24: 633b str r3, [r7, #48] ; 0x30
sConfigOC.Pulse = 0;
8000a26: 2300 movs r3, #0
8000a28: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000a2a: 2300 movs r3, #0
8000a2c: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
8000a2e: 2300 movs r3, #0
8000a30: 63fb str r3, [r7, #60] ; 0x3c
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000a32: 2300 movs r3, #0
8000a34: 643b str r3, [r7, #64] ; 0x40
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8000a36: 2300 movs r3, #0
8000a38: 647b str r3, [r7, #68] ; 0x44
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8000a3a: 2300 movs r3, #0
8000a3c: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000a3e: f107 0330 add.w r3, r7, #48 ; 0x30
8000a42: 2200 movs r2, #0
8000a44: 4619 mov r1, r3
8000a46: 4818 ldr r0, [pc, #96] ; (8000aa8 <MX_TIM1_Init+0x150>)
8000a48: f002 fa1c bl 8002e84 <HAL_TIM_PWM_ConfigChannel>
8000a4c: 4603 mov r3, r0
8000a4e: 2b00 cmp r3, #0
8000a50: d001 beq.n 8000a56 <MX_TIM1_Init+0xfe>
{
Error_Handler();
8000a52: f000 f88d bl 8000b70 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
8000a56: 2300 movs r3, #0
8000a58: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8000a5a: 2300 movs r3, #0
8000a5c: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8000a5e: 2300 movs r3, #0
8000a60: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
8000a62: 2300 movs r3, #0
8000a64: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8000a66: 2300 movs r3, #0
8000a68: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000a6a: f44f 5300 mov.w r3, #8192 ; 0x2000
8000a6e: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.BreakFilter = 0;
8000a70: 2300 movs r3, #0
8000a72: 61fb str r3, [r7, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
8000a74: 2300 movs r3, #0
8000a76: 623b str r3, [r7, #32]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
8000a78: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8000a7c: 627b str r3, [r7, #36] ; 0x24
sBreakDeadTimeConfig.Break2Filter = 0;
8000a7e: 2300 movs r3, #0
8000a80: 62bb str r3, [r7, #40] ; 0x28
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8000a82: 2300 movs r3, #0
8000a84: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
8000a86: 1d3b adds r3, r7, #4
8000a88: 4619 mov r1, r3
8000a8a: 4807 ldr r0, [pc, #28] ; (8000aa8 <MX_TIM1_Init+0x150>)
8000a8c: f002 ffe0 bl 8003a50 <HAL_TIMEx_ConfigBreakDeadTime>
8000a90: 4603 mov r3, r0
8000a92: 2b00 cmp r3, #0
8000a94: d001 beq.n 8000a9a <MX_TIM1_Init+0x142>
{
Error_Handler();
8000a96: f000 f86b bl 8000b70 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
8000a9a: 4803 ldr r0, [pc, #12] ; (8000aa8 <MX_TIM1_Init+0x150>)
8000a9c: f000 f9a6 bl 8000dec <HAL_TIM_MspPostInit>
}
8000aa0: bf00 nop
8000aa2: 3768 adds r7, #104 ; 0x68
8000aa4: 46bd mov sp, r7
8000aa6: bd80 pop {r7, pc}
8000aa8: 20000220 .word 0x20000220
8000aac: 40012c00 .word 0x40012c00
08000ab0 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000ab0: b580 push {r7, lr}
8000ab2: b088 sub sp, #32
8000ab4: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ab6: f107 030c add.w r3, r7, #12
8000aba: 2200 movs r2, #0
8000abc: 601a str r2, [r3, #0]
8000abe: 605a str r2, [r3, #4]
8000ac0: 609a str r2, [r3, #8]
8000ac2: 60da str r2, [r3, #12]
8000ac4: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000ac6: 4b28 ldr r3, [pc, #160] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000ac8: 6cdb ldr r3, [r3, #76] ; 0x4c
8000aca: 4a27 ldr r2, [pc, #156] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000acc: f043 0304 orr.w r3, r3, #4
8000ad0: 64d3 str r3, [r2, #76] ; 0x4c
8000ad2: 4b25 ldr r3, [pc, #148] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000ad4: 6cdb ldr r3, [r3, #76] ; 0x4c
8000ad6: f003 0304 and.w r3, r3, #4
8000ada: 60bb str r3, [r7, #8]
8000adc: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000ade: 4b22 ldr r3, [pc, #136] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000ae0: 6cdb ldr r3, [r3, #76] ; 0x4c
8000ae2: 4a21 ldr r2, [pc, #132] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000ae4: f043 0380 orr.w r3, r3, #128 ; 0x80
8000ae8: 64d3 str r3, [r2, #76] ; 0x4c
8000aea: 4b1f ldr r3, [pc, #124] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000aec: 6cdb ldr r3, [r3, #76] ; 0x4c
8000aee: f003 0380 and.w r3, r3, #128 ; 0x80
8000af2: 607b str r3, [r7, #4]
8000af4: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000af6: 4b1c ldr r3, [pc, #112] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000af8: 6cdb ldr r3, [r3, #76] ; 0x4c
8000afa: 4a1b ldr r2, [pc, #108] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000afc: f043 0301 orr.w r3, r3, #1
8000b00: 64d3 str r3, [r2, #76] ; 0x4c
8000b02: 4b19 ldr r3, [pc, #100] ; (8000b68 <MX_GPIO_Init+0xb8>)
8000b04: 6cdb ldr r3, [r3, #76] ; 0x4c
8000b06: f003 0301 and.w r3, r3, #1
8000b0a: 603b str r3, [r7, #0]
8000b0c: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_2, GPIO_PIN_RESET);
8000b0e: 2200 movs r2, #0
8000b10: 2104 movs r1, #4
8000b12: 4816 ldr r0, [pc, #88] ; (8000b6c <MX_GPIO_Init+0xbc>)
8000b14: f000 fe62 bl 80017dc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
8000b18: 2200 movs r2, #0
8000b1a: 2101 movs r1, #1
8000b1c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000b20: f000 fe5c bl 80017dc <HAL_GPIO_WritePin>
/*Configure GPIO pin : PC2 */
GPIO_InitStruct.Pin = GPIO_PIN_2;
8000b24: 2304 movs r3, #4
8000b26: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000b28: 2301 movs r3, #1
8000b2a: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b2c: 2300 movs r3, #0
8000b2e: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b30: 2300 movs r3, #0
8000b32: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000b34: f107 030c add.w r3, r7, #12
8000b38: 4619 mov r1, r3
8000b3a: 480c ldr r0, [pc, #48] ; (8000b6c <MX_GPIO_Init+0xbc>)
8000b3c: f000 fcd4 bl 80014e8 <HAL_GPIO_Init>
/*Configure GPIO pin : PA0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000b40: 2301 movs r3, #1
8000b42: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000b44: 2301 movs r3, #1
8000b46: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b48: 2300 movs r3, #0
8000b4a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b4c: 2300 movs r3, #0
8000b4e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000b50: f107 030c add.w r3, r7, #12
8000b54: 4619 mov r1, r3
8000b56: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000b5a: f000 fcc5 bl 80014e8 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000b5e: bf00 nop
8000b60: 3720 adds r7, #32
8000b62: 46bd mov sp, r7
8000b64: bd80 pop {r7, pc}
8000b66: bf00 nop
8000b68: 40021000 .word 0x40021000
8000b6c: 48000800 .word 0x48000800
08000b70 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000b70: b480 push {r7}
8000b72: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000b74: b672 cpsid i
}
8000b76: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000b78: e7fe b.n 8000b78 <Error_Handler+0x8>
...
08000b7c <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000b7c: b480 push {r7}
8000b7e: b083 sub sp, #12
8000b80: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000b82: 4b0f ldr r3, [pc, #60] ; (8000bc0 <HAL_MspInit+0x44>)
8000b84: 6e1b ldr r3, [r3, #96] ; 0x60
8000b86: 4a0e ldr r2, [pc, #56] ; (8000bc0 <HAL_MspInit+0x44>)
8000b88: f043 0301 orr.w r3, r3, #1
8000b8c: 6613 str r3, [r2, #96] ; 0x60
8000b8e: 4b0c ldr r3, [pc, #48] ; (8000bc0 <HAL_MspInit+0x44>)
8000b90: 6e1b ldr r3, [r3, #96] ; 0x60
8000b92: f003 0301 and.w r3, r3, #1
8000b96: 607b str r3, [r7, #4]
8000b98: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000b9a: 4b09 ldr r3, [pc, #36] ; (8000bc0 <HAL_MspInit+0x44>)
8000b9c: 6d9b ldr r3, [r3, #88] ; 0x58
8000b9e: 4a08 ldr r2, [pc, #32] ; (8000bc0 <HAL_MspInit+0x44>)
8000ba0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000ba4: 6593 str r3, [r2, #88] ; 0x58
8000ba6: 4b06 ldr r3, [pc, #24] ; (8000bc0 <HAL_MspInit+0x44>)
8000ba8: 6d9b ldr r3, [r3, #88] ; 0x58
8000baa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000bae: 603b str r3, [r7, #0]
8000bb0: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000bb2: bf00 nop
8000bb4: 370c adds r7, #12
8000bb6: 46bd mov sp, r7
8000bb8: f85d 7b04 ldr.w r7, [sp], #4
8000bbc: 4770 bx lr
8000bbe: bf00 nop
8000bc0: 40021000 .word 0x40021000
08000bc4 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000bc4: b580 push {r7, lr}
8000bc6: b0a4 sub sp, #144 ; 0x90
8000bc8: af00 add r7, sp, #0
8000bca: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000bcc: f107 037c add.w r3, r7, #124 ; 0x7c
8000bd0: 2200 movs r2, #0
8000bd2: 601a str r2, [r3, #0]
8000bd4: 605a str r2, [r3, #4]
8000bd6: 609a str r2, [r3, #8]
8000bd8: 60da str r2, [r3, #12]
8000bda: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000bdc: f107 0320 add.w r3, r7, #32
8000be0: 225c movs r2, #92 ; 0x5c
8000be2: 2100 movs r1, #0
8000be4: 4618 mov r0, r3
8000be6: f004 fe69 bl 80058bc <memset>
if(huart->Instance==LPUART1)
8000bea: 687b ldr r3, [r7, #4]
8000bec: 681b ldr r3, [r3, #0]
8000bee: 4a6a ldr r2, [pc, #424] ; (8000d98 <HAL_UART_MspInit+0x1d4>)
8000bf0: 4293 cmp r3, r2
8000bf2: d142 bne.n 8000c7a <HAL_UART_MspInit+0xb6>
/* USER CODE END LPUART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
8000bf4: 2320 movs r3, #32
8000bf6: 623b str r3, [r7, #32]
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
8000bf8: 2300 movs r3, #0
8000bfa: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000bfc: f107 0320 add.w r3, r7, #32
8000c00: 4618 mov r0, r3
8000c02: f001 fc9f bl 8002544 <HAL_RCCEx_PeriphCLKConfig>
8000c06: 4603 mov r3, r0
8000c08: 2b00 cmp r3, #0
8000c0a: d001 beq.n 8000c10 <HAL_UART_MspInit+0x4c>
{
Error_Handler();
8000c0c: f7ff ffb0 bl 8000b70 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE();
8000c10: 4b62 ldr r3, [pc, #392] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000c12: 6ddb ldr r3, [r3, #92] ; 0x5c
8000c14: 4a61 ldr r2, [pc, #388] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000c16: f043 0301 orr.w r3, r3, #1
8000c1a: 65d3 str r3, [r2, #92] ; 0x5c
8000c1c: 4b5f ldr r3, [pc, #380] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000c1e: 6ddb ldr r3, [r3, #92] ; 0x5c
8000c20: f003 0301 and.w r3, r3, #1
8000c24: 61fb str r3, [r7, #28]
8000c26: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000c28: 4b5c ldr r3, [pc, #368] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000c2a: 6cdb ldr r3, [r3, #76] ; 0x4c
8000c2c: 4a5b ldr r2, [pc, #364] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000c2e: f043 0304 orr.w r3, r3, #4
8000c32: 64d3 str r3, [r2, #76] ; 0x4c
8000c34: 4b59 ldr r3, [pc, #356] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000c36: 6cdb ldr r3, [r3, #76] ; 0x4c
8000c38: f003 0304 and.w r3, r3, #4
8000c3c: 61bb str r3, [r7, #24]
8000c3e: 69bb ldr r3, [r7, #24]
/**LPUART1 GPIO Configuration
PC0 ------> LPUART1_RX
PC1 ------> LPUART1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
8000c40: 2303 movs r3, #3
8000c42: 67fb str r3, [r7, #124] ; 0x7c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c44: 2302 movs r3, #2
8000c46: f8c7 3080 str.w r3, [r7, #128] ; 0x80
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c4a: 2300 movs r3, #0
8000c4c: f8c7 3084 str.w r3, [r7, #132] ; 0x84
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c50: 2303 movs r3, #3
8000c52: f8c7 3088 str.w r3, [r7, #136] ; 0x88
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
8000c56: 2308 movs r3, #8
8000c58: f8c7 308c str.w r3, [r7, #140] ; 0x8c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000c5c: f107 037c add.w r3, r7, #124 ; 0x7c
8000c60: 4619 mov r1, r3
8000c62: 484f ldr r0, [pc, #316] ; (8000da0 <HAL_UART_MspInit+0x1dc>)
8000c64: f000 fc40 bl 80014e8 <HAL_GPIO_Init>
/* LPUART1 interrupt Init */
HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
8000c68: 2200 movs r2, #0
8000c6a: 2100 movs r1, #0
8000c6c: 2046 movs r0, #70 ; 0x46
8000c6e: f000 fb86 bl 800137e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LPUART1_IRQn);
8000c72: 2046 movs r0, #70 ; 0x46
8000c74: f000 fb9f bl 80013b6 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000c78: e089 b.n 8000d8e <HAL_UART_MspInit+0x1ca>
else if(huart->Instance==USART1)
8000c7a: 687b ldr r3, [r7, #4]
8000c7c: 681b ldr r3, [r3, #0]
8000c7e: 4a49 ldr r2, [pc, #292] ; (8000da4 <HAL_UART_MspInit+0x1e0>)
8000c80: 4293 cmp r3, r2
8000c82: d144 bne.n 8000d0e <HAL_UART_MspInit+0x14a>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
8000c84: 2301 movs r3, #1
8000c86: 623b str r3, [r7, #32]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
8000c88: 2300 movs r3, #0
8000c8a: 643b str r3, [r7, #64] ; 0x40
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000c8c: f107 0320 add.w r3, r7, #32
8000c90: 4618 mov r0, r3
8000c92: f001 fc57 bl 8002544 <HAL_RCCEx_PeriphCLKConfig>
8000c96: 4603 mov r3, r0
8000c98: 2b00 cmp r3, #0
8000c9a: d001 beq.n 8000ca0 <HAL_UART_MspInit+0xdc>
Error_Handler();
8000c9c: f7ff ff68 bl 8000b70 <Error_Handler>
__HAL_RCC_USART1_CLK_ENABLE();
8000ca0: 4b3e ldr r3, [pc, #248] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000ca2: 6e1b ldr r3, [r3, #96] ; 0x60
8000ca4: 4a3d ldr r2, [pc, #244] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000ca6: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000caa: 6613 str r3, [r2, #96] ; 0x60
8000cac: 4b3b ldr r3, [pc, #236] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000cae: 6e1b ldr r3, [r3, #96] ; 0x60
8000cb0: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000cb4: 617b str r3, [r7, #20]
8000cb6: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000cb8: 4b38 ldr r3, [pc, #224] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000cba: 6cdb ldr r3, [r3, #76] ; 0x4c
8000cbc: 4a37 ldr r2, [pc, #220] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000cbe: f043 0301 orr.w r3, r3, #1
8000cc2: 64d3 str r3, [r2, #76] ; 0x4c
8000cc4: 4b35 ldr r3, [pc, #212] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000cc6: 6cdb ldr r3, [r3, #76] ; 0x4c
8000cc8: f003 0301 and.w r3, r3, #1
8000ccc: 613b str r3, [r7, #16]
8000cce: 693b ldr r3, [r7, #16]
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
8000cd0: f44f 63c0 mov.w r3, #1536 ; 0x600
8000cd4: 67fb str r3, [r7, #124] ; 0x7c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cd6: 2302 movs r3, #2
8000cd8: f8c7 3080 str.w r3, [r7, #128] ; 0x80
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cdc: 2300 movs r3, #0
8000cde: f8c7 3084 str.w r3, [r7, #132] ; 0x84
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ce2: 2303 movs r3, #3
8000ce4: f8c7 3088 str.w r3, [r7, #136] ; 0x88
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8000ce8: 2307 movs r3, #7
8000cea: f8c7 308c str.w r3, [r7, #140] ; 0x8c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000cee: f107 037c add.w r3, r7, #124 ; 0x7c
8000cf2: 4619 mov r1, r3
8000cf4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000cf8: f000 fbf6 bl 80014e8 <HAL_GPIO_Init>
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8000cfc: 2200 movs r2, #0
8000cfe: 2100 movs r1, #0
8000d00: 2025 movs r0, #37 ; 0x25
8000d02: f000 fb3c bl 800137e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8000d06: 2025 movs r0, #37 ; 0x25
8000d08: f000 fb55 bl 80013b6 <HAL_NVIC_EnableIRQ>
}
8000d0c: e03f b.n 8000d8e <HAL_UART_MspInit+0x1ca>
else if(huart->Instance==USART2)
8000d0e: 687b ldr r3, [r7, #4]
8000d10: 681b ldr r3, [r3, #0]
8000d12: 4a25 ldr r2, [pc, #148] ; (8000da8 <HAL_UART_MspInit+0x1e4>)
8000d14: 4293 cmp r3, r2
8000d16: d13a bne.n 8000d8e <HAL_UART_MspInit+0x1ca>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
8000d18: 2302 movs r3, #2
8000d1a: 623b str r3, [r7, #32]
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
8000d1c: 2300 movs r3, #0
8000d1e: 647b str r3, [r7, #68] ; 0x44
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000d20: f107 0320 add.w r3, r7, #32
8000d24: 4618 mov r0, r3
8000d26: f001 fc0d bl 8002544 <HAL_RCCEx_PeriphCLKConfig>
8000d2a: 4603 mov r3, r0
8000d2c: 2b00 cmp r3, #0
8000d2e: d001 beq.n 8000d34 <HAL_UART_MspInit+0x170>
Error_Handler();
8000d30: f7ff ff1e bl 8000b70 <Error_Handler>
__HAL_RCC_USART2_CLK_ENABLE();
8000d34: 4b19 ldr r3, [pc, #100] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000d36: 6d9b ldr r3, [r3, #88] ; 0x58
8000d38: 4a18 ldr r2, [pc, #96] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000d3a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000d3e: 6593 str r3, [r2, #88] ; 0x58
8000d40: 4b16 ldr r3, [pc, #88] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000d42: 6d9b ldr r3, [r3, #88] ; 0x58
8000d44: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000d48: 60fb str r3, [r7, #12]
8000d4a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000d4c: 4b13 ldr r3, [pc, #76] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000d4e: 6cdb ldr r3, [r3, #76] ; 0x4c
8000d50: 4a12 ldr r2, [pc, #72] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000d52: f043 0301 orr.w r3, r3, #1
8000d56: 64d3 str r3, [r2, #76] ; 0x4c
8000d58: 4b10 ldr r3, [pc, #64] ; (8000d9c <HAL_UART_MspInit+0x1d8>)
8000d5a: 6cdb ldr r3, [r3, #76] ; 0x4c
8000d5c: f003 0301 and.w r3, r3, #1
8000d60: 60bb str r3, [r7, #8]
8000d62: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
8000d64: 230c movs r3, #12
8000d66: 67fb str r3, [r7, #124] ; 0x7c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d68: 2302 movs r3, #2
8000d6a: f8c7 3080 str.w r3, [r7, #128] ; 0x80
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d6e: 2300 movs r3, #0
8000d70: f8c7 3084 str.w r3, [r7, #132] ; 0x84
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d74: 2303 movs r3, #3
8000d76: f8c7 3088 str.w r3, [r7, #136] ; 0x88
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000d7a: 2307 movs r3, #7
8000d7c: f8c7 308c str.w r3, [r7, #140] ; 0x8c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d80: f107 037c add.w r3, r7, #124 ; 0x7c
8000d84: 4619 mov r1, r3
8000d86: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000d8a: f000 fbad bl 80014e8 <HAL_GPIO_Init>
}
8000d8e: bf00 nop
8000d90: 3790 adds r7, #144 ; 0x90
8000d92: 46bd mov sp, r7
8000d94: bd80 pop {r7, pc}
8000d96: bf00 nop
8000d98: 40008000 .word 0x40008000
8000d9c: 40021000 .word 0x40021000
8000da0: 48000800 .word 0x48000800
8000da4: 40013800 .word 0x40013800
8000da8: 40004400 .word 0x40004400
08000dac <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000dac: b480 push {r7}
8000dae: b085 sub sp, #20
8000db0: af00 add r7, sp, #0
8000db2: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000db4: 687b ldr r3, [r7, #4]
8000db6: 681b ldr r3, [r3, #0]
8000db8: 4a0a ldr r2, [pc, #40] ; (8000de4 <HAL_TIM_Base_MspInit+0x38>)
8000dba: 4293 cmp r3, r2
8000dbc: d10b bne.n 8000dd6 <HAL_TIM_Base_MspInit+0x2a>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8000dbe: 4b0a ldr r3, [pc, #40] ; (8000de8 <HAL_TIM_Base_MspInit+0x3c>)
8000dc0: 6e1b ldr r3, [r3, #96] ; 0x60
8000dc2: 4a09 ldr r2, [pc, #36] ; (8000de8 <HAL_TIM_Base_MspInit+0x3c>)
8000dc4: f443 6300 orr.w r3, r3, #2048 ; 0x800
8000dc8: 6613 str r3, [r2, #96] ; 0x60
8000dca: 4b07 ldr r3, [pc, #28] ; (8000de8 <HAL_TIM_Base_MspInit+0x3c>)
8000dcc: 6e1b ldr r3, [r3, #96] ; 0x60
8000dce: f403 6300 and.w r3, r3, #2048 ; 0x800
8000dd2: 60fb str r3, [r7, #12]
8000dd4: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM1_MspInit 1 */
/* USER CODE END TIM1_MspInit 1 */
}
}
8000dd6: bf00 nop
8000dd8: 3714 adds r7, #20
8000dda: 46bd mov sp, r7
8000ddc: f85d 7b04 ldr.w r7, [sp], #4
8000de0: 4770 bx lr
8000de2: bf00 nop
8000de4: 40012c00 .word 0x40012c00
8000de8: 40021000 .word 0x40021000
08000dec <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000dec: b580 push {r7, lr}
8000dee: b088 sub sp, #32
8000df0: af00 add r7, sp, #0
8000df2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000df4: f107 030c add.w r3, r7, #12
8000df8: 2200 movs r2, #0
8000dfa: 601a str r2, [r3, #0]
8000dfc: 605a str r2, [r3, #4]
8000dfe: 609a str r2, [r3, #8]
8000e00: 60da str r2, [r3, #12]
8000e02: 611a str r2, [r3, #16]
if(htim->Instance==TIM1)
8000e04: 687b ldr r3, [r7, #4]
8000e06: 681b ldr r3, [r3, #0]
8000e08: 4a12 ldr r2, [pc, #72] ; (8000e54 <HAL_TIM_MspPostInit+0x68>)
8000e0a: 4293 cmp r3, r2
8000e0c: d11d bne.n 8000e4a <HAL_TIM_MspPostInit+0x5e>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000e0e: 4b12 ldr r3, [pc, #72] ; (8000e58 <HAL_TIM_MspPostInit+0x6c>)
8000e10: 6cdb ldr r3, [r3, #76] ; 0x4c
8000e12: 4a11 ldr r2, [pc, #68] ; (8000e58 <HAL_TIM_MspPostInit+0x6c>)
8000e14: f043 0301 orr.w r3, r3, #1
8000e18: 64d3 str r3, [r2, #76] ; 0x4c
8000e1a: 4b0f ldr r3, [pc, #60] ; (8000e58 <HAL_TIM_MspPostInit+0x6c>)
8000e1c: 6cdb ldr r3, [r3, #76] ; 0x4c
8000e1e: f003 0301 and.w r3, r3, #1
8000e22: 60bb str r3, [r7, #8]
8000e24: 68bb ldr r3, [r7, #8]
/**TIM1 GPIO Configuration
PA8 ------> TIM1_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_8;
8000e26: f44f 7380 mov.w r3, #256 ; 0x100
8000e2a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e2c: 2302 movs r3, #2
8000e2e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e30: 2300 movs r3, #0
8000e32: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e34: 2300 movs r3, #0
8000e36: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
8000e38: 2301 movs r3, #1
8000e3a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000e3c: f107 030c add.w r3, r7, #12
8000e40: 4619 mov r1, r3
8000e42: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000e46: f000 fb4f bl 80014e8 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
8000e4a: bf00 nop
8000e4c: 3720 adds r7, #32
8000e4e: 46bd mov sp, r7
8000e50: bd80 pop {r7, pc}
8000e52: bf00 nop
8000e54: 40012c00 .word 0x40012c00
8000e58: 40021000 .word 0x40021000
08000e5c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000e5c: b480 push {r7}
8000e5e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000e60: e7fe b.n 8000e60 <NMI_Handler+0x4>
08000e62 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000e62: b480 push {r7}
8000e64: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000e66: e7fe b.n 8000e66 <HardFault_Handler+0x4>
08000e68 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000e68: b480 push {r7}
8000e6a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000e6c: e7fe b.n 8000e6c <MemManage_Handler+0x4>
08000e6e <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000e6e: b480 push {r7}
8000e70: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000e72: e7fe b.n 8000e72 <BusFault_Handler+0x4>
08000e74 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000e74: b480 push {r7}
8000e76: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000e78: e7fe b.n 8000e78 <UsageFault_Handler+0x4>
08000e7a <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000e7a: b480 push {r7}
8000e7c: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000e7e: bf00 nop
8000e80: 46bd mov sp, r7
8000e82: f85d 7b04 ldr.w r7, [sp], #4
8000e86: 4770 bx lr
08000e88 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000e88: b480 push {r7}
8000e8a: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000e8c: bf00 nop
8000e8e: 46bd mov sp, r7
8000e90: f85d 7b04 ldr.w r7, [sp], #4
8000e94: 4770 bx lr
08000e96 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000e96: b480 push {r7}
8000e98: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000e9a: bf00 nop
8000e9c: 46bd mov sp, r7
8000e9e: f85d 7b04 ldr.w r7, [sp], #4
8000ea2: 4770 bx lr
08000ea4 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000ea4: b580 push {r7, lr}
8000ea6: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000ea8: f000 f94a bl 8001140 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000eac: bf00 nop
8000eae: bd80 pop {r7, pc}
08000eb0 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
8000eb0: b580 push {r7, lr}
8000eb2: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
8000eb4: 4802 ldr r0, [pc, #8] ; (8000ec0 <USART1_IRQHandler+0x10>)
8000eb6: f002 ffc5 bl 8003e44 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8000eba: bf00 nop
8000ebc: bd80 pop {r7, pc}
8000ebe: bf00 nop
8000ec0: 20000110 .word 0x20000110
08000ec4 <LPUART1_IRQHandler>:
/**
* @brief This function handles LPUART1 global interrupt.
*/
void LPUART1_IRQHandler(void)
{
8000ec4: b580 push {r7, lr}
8000ec6: af00 add r7, sp, #0
/* USER CODE BEGIN LPUART1_IRQn 0 */
/* USER CODE END LPUART1_IRQn 0 */
HAL_UART_IRQHandler(&hlpuart1);
8000ec8: 4802 ldr r0, [pc, #8] ; (8000ed4 <LPUART1_IRQHandler+0x10>)
8000eca: f002 ffbb bl 8003e44 <HAL_UART_IRQHandler>
/* USER CODE BEGIN LPUART1_IRQn 1 */
/* USER CODE END LPUART1_IRQn 1 */
}
8000ece: bf00 nop
8000ed0: bd80 pop {r7, pc}
8000ed2: bf00 nop
8000ed4: 20000088 .word 0x20000088
08000ed8 <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8000ed8: b580 push {r7, lr}
8000eda: b086 sub sp, #24
8000edc: af00 add r7, sp, #0
8000ede: 60f8 str r0, [r7, #12]
8000ee0: 60b9 str r1, [r7, #8]
8000ee2: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000ee4: 2300 movs r3, #0
8000ee6: 617b str r3, [r7, #20]
8000ee8: e00a b.n 8000f00 <_read+0x28>
{
*ptr++ = __io_getchar();
8000eea: f3af 8000 nop.w
8000eee: 4601 mov r1, r0
8000ef0: 68bb ldr r3, [r7, #8]
8000ef2: 1c5a adds r2, r3, #1
8000ef4: 60ba str r2, [r7, #8]
8000ef6: b2ca uxtb r2, r1
8000ef8: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000efa: 697b ldr r3, [r7, #20]
8000efc: 3301 adds r3, #1
8000efe: 617b str r3, [r7, #20]
8000f00: 697a ldr r2, [r7, #20]
8000f02: 687b ldr r3, [r7, #4]
8000f04: 429a cmp r2, r3
8000f06: dbf0 blt.n 8000eea <_read+0x12>
}
return len;
8000f08: 687b ldr r3, [r7, #4]
}
8000f0a: 4618 mov r0, r3
8000f0c: 3718 adds r7, #24
8000f0e: 46bd mov sp, r7
8000f10: bd80 pop {r7, pc}
08000f12 <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
8000f12: b580 push {r7, lr}
8000f14: b086 sub sp, #24
8000f16: af00 add r7, sp, #0
8000f18: 60f8 str r0, [r7, #12]
8000f1a: 60b9 str r1, [r7, #8]
8000f1c: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000f1e: 2300 movs r3, #0
8000f20: 617b str r3, [r7, #20]
8000f22: e009 b.n 8000f38 <_write+0x26>
{
__io_putchar(*ptr++);
8000f24: 68bb ldr r3, [r7, #8]
8000f26: 1c5a adds r2, r3, #1
8000f28: 60ba str r2, [r7, #8]
8000f2a: 781b ldrb r3, [r3, #0]
8000f2c: 4618 mov r0, r3
8000f2e: f3af 8000 nop.w
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000f32: 697b ldr r3, [r7, #20]
8000f34: 3301 adds r3, #1
8000f36: 617b str r3, [r7, #20]
8000f38: 697a ldr r2, [r7, #20]
8000f3a: 687b ldr r3, [r7, #4]
8000f3c: 429a cmp r2, r3
8000f3e: dbf1 blt.n 8000f24 <_write+0x12>
}
return len;
8000f40: 687b ldr r3, [r7, #4]
}
8000f42: 4618 mov r0, r3
8000f44: 3718 adds r7, #24
8000f46: 46bd mov sp, r7
8000f48: bd80 pop {r7, pc}
08000f4a <_close>:
int _close(int file)
{
8000f4a: b480 push {r7}
8000f4c: b083 sub sp, #12
8000f4e: af00 add r7, sp, #0
8000f50: 6078 str r0, [r7, #4]
(void)file;
return -1;
8000f52: f04f 33ff mov.w r3, #4294967295
}
8000f56: 4618 mov r0, r3
8000f58: 370c adds r7, #12
8000f5a: 46bd mov sp, r7
8000f5c: f85d 7b04 ldr.w r7, [sp], #4
8000f60: 4770 bx lr
08000f62 <_fstat>:
int _fstat(int file, struct stat *st)
{
8000f62: b480 push {r7}
8000f64: b083 sub sp, #12
8000f66: af00 add r7, sp, #0
8000f68: 6078 str r0, [r7, #4]
8000f6a: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
8000f6c: 683b ldr r3, [r7, #0]
8000f6e: f44f 5200 mov.w r2, #8192 ; 0x2000
8000f72: 605a str r2, [r3, #4]
return 0;
8000f74: 2300 movs r3, #0
}
8000f76: 4618 mov r0, r3
8000f78: 370c adds r7, #12
8000f7a: 46bd mov sp, r7
8000f7c: f85d 7b04 ldr.w r7, [sp], #4
8000f80: 4770 bx lr
08000f82 <_isatty>:
int _isatty(int file)
{
8000f82: b480 push {r7}
8000f84: b083 sub sp, #12
8000f86: af00 add r7, sp, #0
8000f88: 6078 str r0, [r7, #4]
(void)file;
return 1;
8000f8a: 2301 movs r3, #1
}
8000f8c: 4618 mov r0, r3
8000f8e: 370c adds r7, #12
8000f90: 46bd mov sp, r7
8000f92: f85d 7b04 ldr.w r7, [sp], #4
8000f96: 4770 bx lr
08000f98 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8000f98: b480 push {r7}
8000f9a: b085 sub sp, #20
8000f9c: af00 add r7, sp, #0
8000f9e: 60f8 str r0, [r7, #12]
8000fa0: 60b9 str r1, [r7, #8]
8000fa2: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
8000fa4: 2300 movs r3, #0
}
8000fa6: 4618 mov r0, r3
8000fa8: 3714 adds r7, #20
8000faa: 46bd mov sp, r7
8000fac: f85d 7b04 ldr.w r7, [sp], #4
8000fb0: 4770 bx lr
...
08000fb4 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8000fb4: b580 push {r7, lr}
8000fb6: b086 sub sp, #24
8000fb8: af00 add r7, sp, #0
8000fba: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8000fbc: 4a14 ldr r2, [pc, #80] ; (8001010 <_sbrk+0x5c>)
8000fbe: 4b15 ldr r3, [pc, #84] ; (8001014 <_sbrk+0x60>)
8000fc0: 1ad3 subs r3, r2, r3
8000fc2: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8000fc4: 697b ldr r3, [r7, #20]
8000fc6: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8000fc8: 4b13 ldr r3, [pc, #76] ; (8001018 <_sbrk+0x64>)
8000fca: 681b ldr r3, [r3, #0]
8000fcc: 2b00 cmp r3, #0
8000fce: d102 bne.n 8000fd6 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8000fd0: 4b11 ldr r3, [pc, #68] ; (8001018 <_sbrk+0x64>)
8000fd2: 4a12 ldr r2, [pc, #72] ; (800101c <_sbrk+0x68>)
8000fd4: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8000fd6: 4b10 ldr r3, [pc, #64] ; (8001018 <_sbrk+0x64>)
8000fd8: 681a ldr r2, [r3, #0]
8000fda: 687b ldr r3, [r7, #4]
8000fdc: 4413 add r3, r2
8000fde: 693a ldr r2, [r7, #16]
8000fe0: 429a cmp r2, r3
8000fe2: d207 bcs.n 8000ff4 <_sbrk+0x40>
{
errno = ENOMEM;
8000fe4: f004 fcb8 bl 8005958 <__errno>
8000fe8: 4603 mov r3, r0
8000fea: 220c movs r2, #12
8000fec: 601a str r2, [r3, #0]
return (void *)-1;
8000fee: f04f 33ff mov.w r3, #4294967295
8000ff2: e009 b.n 8001008 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8000ff4: 4b08 ldr r3, [pc, #32] ; (8001018 <_sbrk+0x64>)
8000ff6: 681b ldr r3, [r3, #0]
8000ff8: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8000ffa: 4b07 ldr r3, [pc, #28] ; (8001018 <_sbrk+0x64>)
8000ffc: 681a ldr r2, [r3, #0]
8000ffe: 687b ldr r3, [r7, #4]
8001000: 4413 add r3, r2
8001002: 4a05 ldr r2, [pc, #20] ; (8001018 <_sbrk+0x64>)
8001004: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001006: 68fb ldr r3, [r7, #12]
}
8001008: 4618 mov r0, r3
800100a: 3718 adds r7, #24
800100c: 46bd mov sp, r7
800100e: bd80 pop {r7, pc}
8001010: 20010000 .word 0x20010000
8001014: 00000400 .word 0x00000400
8001018: 200002a4 .word 0x200002a4
800101c: 200003f8 .word 0x200003f8
08001020 <SystemInit>:
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
8001020: b480 push {r7}
8001022: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
8001024: 4b06 ldr r3, [pc, #24] ; (8001040 <SystemInit+0x20>)
8001026: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800102a: 4a05 ldr r2, [pc, #20] ; (8001040 <SystemInit+0x20>)
800102c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8001030: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
}
8001034: bf00 nop
8001036: 46bd mov sp, r7
8001038: f85d 7b04 ldr.w r7, [sp], #4
800103c: 4770 bx lr
800103e: bf00 nop
8001040: e000ed00 .word 0xe000ed00
08001044 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
8001044: f8df d034 ldr.w sp, [pc, #52] ; 800107c <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8001048: f7ff ffea bl 8001020 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800104c: 480c ldr r0, [pc, #48] ; (8001080 <LoopForever+0x6>)
ldr r1, =_edata
800104e: 490d ldr r1, [pc, #52] ; (8001084 <LoopForever+0xa>)
ldr r2, =_sidata
8001050: 4a0d ldr r2, [pc, #52] ; (8001088 <LoopForever+0xe>)
movs r3, #0
8001052: 2300 movs r3, #0
b LoopCopyDataInit
8001054: e002 b.n 800105c <LoopCopyDataInit>
08001056 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001056: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001058: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800105a: 3304 adds r3, #4
0800105c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800105c: 18c4 adds r4, r0, r3
cmp r4, r1
800105e: 428c cmp r4, r1
bcc CopyDataInit
8001060: d3f9 bcc.n 8001056 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001062: 4a0a ldr r2, [pc, #40] ; (800108c <LoopForever+0x12>)
ldr r4, =_ebss
8001064: 4c0a ldr r4, [pc, #40] ; (8001090 <LoopForever+0x16>)
movs r3, #0
8001066: 2300 movs r3, #0
b LoopFillZerobss
8001068: e001 b.n 800106e <LoopFillZerobss>
0800106a <FillZerobss>:
FillZerobss:
str r3, [r2]
800106a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800106c: 3204 adds r2, #4
0800106e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800106e: 42a2 cmp r2, r4
bcc FillZerobss
8001070: d3fb bcc.n 800106a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001072: f004 fc77 bl 8005964 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001076: f7ff fb55 bl 8000724 <main>
0800107a <LoopForever>:
LoopForever:
b LoopForever
800107a: e7fe b.n 800107a <LoopForever>
ldr sp, =_estack /* Set stack pointer */
800107c: 20010000 .word 0x20010000
ldr r0, =_sdata
8001080: 20000000 .word 0x20000000
ldr r1, =_edata
8001084: 2000006c .word 0x2000006c
ldr r2, =_sidata
8001088: 08005f70 .word 0x08005f70
ldr r2, =_sbss
800108c: 2000006c .word 0x2000006c
ldr r4, =_ebss
8001090: 200003f8 .word 0x200003f8
08001094 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001094: e7fe b.n 8001094 <ADC1_IRQHandler>
08001096 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001096: b580 push {r7, lr}
8001098: b082 sub sp, #8
800109a: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
800109c: 2300 movs r3, #0
800109e: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80010a0: 2003 movs r0, #3
80010a2: f000 f961 bl 8001368 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
80010a6: 200f movs r0, #15
80010a8: f000 f80e bl 80010c8 <HAL_InitTick>
80010ac: 4603 mov r3, r0
80010ae: 2b00 cmp r3, #0
80010b0: d002 beq.n 80010b8 <HAL_Init+0x22>
{
status = HAL_ERROR;
80010b2: 2301 movs r3, #1
80010b4: 71fb strb r3, [r7, #7]
80010b6: e001 b.n 80010bc <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
80010b8: f7ff fd60 bl 8000b7c <HAL_MspInit>
}
/* Return function status */
return status;
80010bc: 79fb ldrb r3, [r7, #7]
}
80010be: 4618 mov r0, r3
80010c0: 3708 adds r7, #8
80010c2: 46bd mov sp, r7
80010c4: bd80 pop {r7, pc}
...
080010c8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80010c8: b580 push {r7, lr}
80010ca: b084 sub sp, #16
80010cc: af00 add r7, sp, #0
80010ce: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80010d0: 2300 movs r3, #0
80010d2: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
80010d4: 4b17 ldr r3, [pc, #92] ; (8001134 <HAL_InitTick+0x6c>)
80010d6: 781b ldrb r3, [r3, #0]
80010d8: 2b00 cmp r3, #0
80010da: d023 beq.n 8001124 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
80010dc: 4b16 ldr r3, [pc, #88] ; (8001138 <HAL_InitTick+0x70>)
80010de: 681a ldr r2, [r3, #0]
80010e0: 4b14 ldr r3, [pc, #80] ; (8001134 <HAL_InitTick+0x6c>)
80010e2: 781b ldrb r3, [r3, #0]
80010e4: 4619 mov r1, r3
80010e6: f44f 737a mov.w r3, #1000 ; 0x3e8
80010ea: fbb3 f3f1 udiv r3, r3, r1
80010ee: fbb2 f3f3 udiv r3, r2, r3
80010f2: 4618 mov r0, r3
80010f4: f000 f96d bl 80013d2 <HAL_SYSTICK_Config>
80010f8: 4603 mov r3, r0
80010fa: 2b00 cmp r3, #0
80010fc: d10f bne.n 800111e <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80010fe: 687b ldr r3, [r7, #4]
8001100: 2b0f cmp r3, #15
8001102: d809 bhi.n 8001118 <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001104: 2200 movs r2, #0
8001106: 6879 ldr r1, [r7, #4]
8001108: f04f 30ff mov.w r0, #4294967295
800110c: f000 f937 bl 800137e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001110: 4a0a ldr r2, [pc, #40] ; (800113c <HAL_InitTick+0x74>)
8001112: 687b ldr r3, [r7, #4]
8001114: 6013 str r3, [r2, #0]
8001116: e007 b.n 8001128 <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
8001118: 2301 movs r3, #1
800111a: 73fb strb r3, [r7, #15]
800111c: e004 b.n 8001128 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
800111e: 2301 movs r3, #1
8001120: 73fb strb r3, [r7, #15]
8001122: e001 b.n 8001128 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8001124: 2301 movs r3, #1
8001126: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001128: 7bfb ldrb r3, [r7, #15]
}
800112a: 4618 mov r0, r3
800112c: 3710 adds r7, #16
800112e: 46bd mov sp, r7
8001130: bd80 pop {r7, pc}
8001132: bf00 nop
8001134: 2000000c .word 0x2000000c
8001138: 20000004 .word 0x20000004
800113c: 20000008 .word 0x20000008
08001140 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001140: b480 push {r7}
8001142: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8001144: 4b06 ldr r3, [pc, #24] ; (8001160 <HAL_IncTick+0x20>)
8001146: 781b ldrb r3, [r3, #0]
8001148: 461a mov r2, r3
800114a: 4b06 ldr r3, [pc, #24] ; (8001164 <HAL_IncTick+0x24>)
800114c: 681b ldr r3, [r3, #0]
800114e: 4413 add r3, r2
8001150: 4a04 ldr r2, [pc, #16] ; (8001164 <HAL_IncTick+0x24>)
8001152: 6013 str r3, [r2, #0]
}
8001154: bf00 nop
8001156: 46bd mov sp, r7
8001158: f85d 7b04 ldr.w r7, [sp], #4
800115c: 4770 bx lr
800115e: bf00 nop
8001160: 2000000c .word 0x2000000c
8001164: 200002a8 .word 0x200002a8
08001168 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001168: b480 push {r7}
800116a: af00 add r7, sp, #0
return uwTick;
800116c: 4b03 ldr r3, [pc, #12] ; (800117c <HAL_GetTick+0x14>)
800116e: 681b ldr r3, [r3, #0]
}
8001170: 4618 mov r0, r3
8001172: 46bd mov sp, r7
8001174: f85d 7b04 ldr.w r7, [sp], #4
8001178: 4770 bx lr
800117a: bf00 nop
800117c: 200002a8 .word 0x200002a8
08001180 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001180: b580 push {r7, lr}
8001182: b084 sub sp, #16
8001184: af00 add r7, sp, #0
8001186: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001188: f7ff ffee bl 8001168 <HAL_GetTick>
800118c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
800118e: 687b ldr r3, [r7, #4]
8001190: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
8001192: 68fb ldr r3, [r7, #12]
8001194: f1b3 3fff cmp.w r3, #4294967295
8001198: d005 beq.n 80011a6 <HAL_Delay+0x26>
{
wait += (uint32_t)uwTickFreq;
800119a: 4b0a ldr r3, [pc, #40] ; (80011c4 <HAL_Delay+0x44>)
800119c: 781b ldrb r3, [r3, #0]
800119e: 461a mov r2, r3
80011a0: 68fb ldr r3, [r7, #12]
80011a2: 4413 add r3, r2
80011a4: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
80011a6: bf00 nop
80011a8: f7ff ffde bl 8001168 <HAL_GetTick>
80011ac: 4602 mov r2, r0
80011ae: 68bb ldr r3, [r7, #8]
80011b0: 1ad3 subs r3, r2, r3
80011b2: 68fa ldr r2, [r7, #12]
80011b4: 429a cmp r2, r3
80011b6: d8f7 bhi.n 80011a8 <HAL_Delay+0x28>
{
}
}
80011b8: bf00 nop
80011ba: bf00 nop
80011bc: 3710 adds r7, #16
80011be: 46bd mov sp, r7
80011c0: bd80 pop {r7, pc}
80011c2: bf00 nop
80011c4: 2000000c .word 0x2000000c
080011c8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80011c8: b480 push {r7}
80011ca: b085 sub sp, #20
80011cc: af00 add r7, sp, #0
80011ce: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80011d0: 687b ldr r3, [r7, #4]
80011d2: f003 0307 and.w r3, r3, #7
80011d6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80011d8: 4b0c ldr r3, [pc, #48] ; (800120c <__NVIC_SetPriorityGrouping+0x44>)
80011da: 68db ldr r3, [r3, #12]
80011dc: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80011de: 68ba ldr r2, [r7, #8]
80011e0: f64f 03ff movw r3, #63743 ; 0xf8ff
80011e4: 4013 ands r3, r2
80011e6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80011e8: 68fb ldr r3, [r7, #12]
80011ea: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80011ec: 68bb ldr r3, [r7, #8]
80011ee: 4313 orrs r3, r2
reg_value = (reg_value |
80011f0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80011f4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80011f8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80011fa: 4a04 ldr r2, [pc, #16] ; (800120c <__NVIC_SetPriorityGrouping+0x44>)
80011fc: 68bb ldr r3, [r7, #8]
80011fe: 60d3 str r3, [r2, #12]
}
8001200: bf00 nop
8001202: 3714 adds r7, #20
8001204: 46bd mov sp, r7
8001206: f85d 7b04 ldr.w r7, [sp], #4
800120a: 4770 bx lr
800120c: e000ed00 .word 0xe000ed00
08001210 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001210: b480 push {r7}
8001212: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001214: 4b04 ldr r3, [pc, #16] ; (8001228 <__NVIC_GetPriorityGrouping+0x18>)
8001216: 68db ldr r3, [r3, #12]
8001218: 0a1b lsrs r3, r3, #8
800121a: f003 0307 and.w r3, r3, #7
}
800121e: 4618 mov r0, r3
8001220: 46bd mov sp, r7
8001222: f85d 7b04 ldr.w r7, [sp], #4
8001226: 4770 bx lr
8001228: e000ed00 .word 0xe000ed00
0800122c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800122c: b480 push {r7}
800122e: b083 sub sp, #12
8001230: af00 add r7, sp, #0
8001232: 4603 mov r3, r0
8001234: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001236: f997 3007 ldrsb.w r3, [r7, #7]
800123a: 2b00 cmp r3, #0
800123c: db0b blt.n 8001256 <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800123e: 79fb ldrb r3, [r7, #7]
8001240: f003 021f and.w r2, r3, #31
8001244: 4907 ldr r1, [pc, #28] ; (8001264 <__NVIC_EnableIRQ+0x38>)
8001246: f997 3007 ldrsb.w r3, [r7, #7]
800124a: 095b lsrs r3, r3, #5
800124c: 2001 movs r0, #1
800124e: fa00 f202 lsl.w r2, r0, r2
8001252: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
8001256: bf00 nop
8001258: 370c adds r7, #12
800125a: 46bd mov sp, r7
800125c: f85d 7b04 ldr.w r7, [sp], #4
8001260: 4770 bx lr
8001262: bf00 nop
8001264: e000e100 .word 0xe000e100
08001268 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001268: b480 push {r7}
800126a: b083 sub sp, #12
800126c: af00 add r7, sp, #0
800126e: 4603 mov r3, r0
8001270: 6039 str r1, [r7, #0]
8001272: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001274: f997 3007 ldrsb.w r3, [r7, #7]
8001278: 2b00 cmp r3, #0
800127a: db0a blt.n 8001292 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800127c: 683b ldr r3, [r7, #0]
800127e: b2da uxtb r2, r3
8001280: 490c ldr r1, [pc, #48] ; (80012b4 <__NVIC_SetPriority+0x4c>)
8001282: f997 3007 ldrsb.w r3, [r7, #7]
8001286: 0112 lsls r2, r2, #4
8001288: b2d2 uxtb r2, r2
800128a: 440b add r3, r1
800128c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001290: e00a b.n 80012a8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001292: 683b ldr r3, [r7, #0]
8001294: b2da uxtb r2, r3
8001296: 4908 ldr r1, [pc, #32] ; (80012b8 <__NVIC_SetPriority+0x50>)
8001298: 79fb ldrb r3, [r7, #7]
800129a: f003 030f and.w r3, r3, #15
800129e: 3b04 subs r3, #4
80012a0: 0112 lsls r2, r2, #4
80012a2: b2d2 uxtb r2, r2
80012a4: 440b add r3, r1
80012a6: 761a strb r2, [r3, #24]
}
80012a8: bf00 nop
80012aa: 370c adds r7, #12
80012ac: 46bd mov sp, r7
80012ae: f85d 7b04 ldr.w r7, [sp], #4
80012b2: 4770 bx lr
80012b4: e000e100 .word 0xe000e100
80012b8: e000ed00 .word 0xe000ed00
080012bc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80012bc: b480 push {r7}
80012be: b089 sub sp, #36 ; 0x24
80012c0: af00 add r7, sp, #0
80012c2: 60f8 str r0, [r7, #12]
80012c4: 60b9 str r1, [r7, #8]
80012c6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80012c8: 68fb ldr r3, [r7, #12]
80012ca: f003 0307 and.w r3, r3, #7
80012ce: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80012d0: 69fb ldr r3, [r7, #28]
80012d2: f1c3 0307 rsb r3, r3, #7
80012d6: 2b04 cmp r3, #4
80012d8: bf28 it cs
80012da: 2304 movcs r3, #4
80012dc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80012de: 69fb ldr r3, [r7, #28]
80012e0: 3304 adds r3, #4
80012e2: 2b06 cmp r3, #6
80012e4: d902 bls.n 80012ec <NVIC_EncodePriority+0x30>
80012e6: 69fb ldr r3, [r7, #28]
80012e8: 3b03 subs r3, #3
80012ea: e000 b.n 80012ee <NVIC_EncodePriority+0x32>
80012ec: 2300 movs r3, #0
80012ee: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80012f0: f04f 32ff mov.w r2, #4294967295
80012f4: 69bb ldr r3, [r7, #24]
80012f6: fa02 f303 lsl.w r3, r2, r3
80012fa: 43da mvns r2, r3
80012fc: 68bb ldr r3, [r7, #8]
80012fe: 401a ands r2, r3
8001300: 697b ldr r3, [r7, #20]
8001302: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001304: f04f 31ff mov.w r1, #4294967295
8001308: 697b ldr r3, [r7, #20]
800130a: fa01 f303 lsl.w r3, r1, r3
800130e: 43d9 mvns r1, r3
8001310: 687b ldr r3, [r7, #4]
8001312: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001314: 4313 orrs r3, r2
);
}
8001316: 4618 mov r0, r3
8001318: 3724 adds r7, #36 ; 0x24
800131a: 46bd mov sp, r7
800131c: f85d 7b04 ldr.w r7, [sp], #4
8001320: 4770 bx lr
...
08001324 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001324: b580 push {r7, lr}
8001326: b082 sub sp, #8
8001328: af00 add r7, sp, #0
800132a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
800132c: 687b ldr r3, [r7, #4]
800132e: 3b01 subs r3, #1
8001330: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8001334: d301 bcc.n 800133a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001336: 2301 movs r3, #1
8001338: e00f b.n 800135a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800133a: 4a0a ldr r2, [pc, #40] ; (8001364 <SysTick_Config+0x40>)
800133c: 687b ldr r3, [r7, #4]
800133e: 3b01 subs r3, #1
8001340: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001342: 210f movs r1, #15
8001344: f04f 30ff mov.w r0, #4294967295
8001348: f7ff ff8e bl 8001268 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800134c: 4b05 ldr r3, [pc, #20] ; (8001364 <SysTick_Config+0x40>)
800134e: 2200 movs r2, #0
8001350: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001352: 4b04 ldr r3, [pc, #16] ; (8001364 <SysTick_Config+0x40>)
8001354: 2207 movs r2, #7
8001356: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001358: 2300 movs r3, #0
}
800135a: 4618 mov r0, r3
800135c: 3708 adds r7, #8
800135e: 46bd mov sp, r7
8001360: bd80 pop {r7, pc}
8001362: bf00 nop
8001364: e000e010 .word 0xe000e010
08001368 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001368: b580 push {r7, lr}
800136a: b082 sub sp, #8
800136c: af00 add r7, sp, #0
800136e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001370: 6878 ldr r0, [r7, #4]
8001372: f7ff ff29 bl 80011c8 <__NVIC_SetPriorityGrouping>
}
8001376: bf00 nop
8001378: 3708 adds r7, #8
800137a: 46bd mov sp, r7
800137c: bd80 pop {r7, pc}
0800137e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800137e: b580 push {r7, lr}
8001380: b086 sub sp, #24
8001382: af00 add r7, sp, #0
8001384: 4603 mov r3, r0
8001386: 60b9 str r1, [r7, #8]
8001388: 607a str r2, [r7, #4]
800138a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
800138c: 2300 movs r3, #0
800138e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001390: f7ff ff3e bl 8001210 <__NVIC_GetPriorityGrouping>
8001394: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001396: 687a ldr r2, [r7, #4]
8001398: 68b9 ldr r1, [r7, #8]
800139a: 6978 ldr r0, [r7, #20]
800139c: f7ff ff8e bl 80012bc <NVIC_EncodePriority>
80013a0: 4602 mov r2, r0
80013a2: f997 300f ldrsb.w r3, [r7, #15]
80013a6: 4611 mov r1, r2
80013a8: 4618 mov r0, r3
80013aa: f7ff ff5d bl 8001268 <__NVIC_SetPriority>
}
80013ae: bf00 nop
80013b0: 3718 adds r7, #24
80013b2: 46bd mov sp, r7
80013b4: bd80 pop {r7, pc}
080013b6 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80013b6: b580 push {r7, lr}
80013b8: b082 sub sp, #8
80013ba: af00 add r7, sp, #0
80013bc: 4603 mov r3, r0
80013be: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80013c0: f997 3007 ldrsb.w r3, [r7, #7]
80013c4: 4618 mov r0, r3
80013c6: f7ff ff31 bl 800122c <__NVIC_EnableIRQ>
}
80013ca: bf00 nop
80013cc: 3708 adds r7, #8
80013ce: 46bd mov sp, r7
80013d0: bd80 pop {r7, pc}
080013d2 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80013d2: b580 push {r7, lr}
80013d4: b082 sub sp, #8
80013d6: af00 add r7, sp, #0
80013d8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80013da: 6878 ldr r0, [r7, #4]
80013dc: f7ff ffa2 bl 8001324 <SysTick_Config>
80013e0: 4603 mov r3, r0
}
80013e2: 4618 mov r0, r3
80013e4: 3708 adds r7, #8
80013e6: 46bd mov sp, r7
80013e8: bd80 pop {r7, pc}
080013ea <HAL_DMA_Abort>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
80013ea: b480 push {r7}
80013ec: b085 sub sp, #20
80013ee: af00 add r7, sp, #0
80013f0: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80013f2: 2300 movs r3, #0
80013f4: 73fb strb r3, [r7, #15]
/* Check the DMA peripheral state */
if (hdma->State != HAL_DMA_STATE_BUSY)
80013f6: 687b ldr r3, [r7, #4]
80013f8: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
80013fc: b2db uxtb r3, r3
80013fe: 2b02 cmp r3, #2
8001400: d008 beq.n 8001414 <HAL_DMA_Abort+0x2a>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001402: 687b ldr r3, [r7, #4]
8001404: 2204 movs r2, #4
8001406: 63da str r2, [r3, #60] ; 0x3c
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001408: 687b ldr r3, [r7, #4]
800140a: 2200 movs r2, #0
800140c: f883 2024 strb.w r2, [r3, #36] ; 0x24
return HAL_ERROR;
8001410: 2301 movs r3, #1
8001412: e022 b.n 800145a <HAL_DMA_Abort+0x70>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001414: 687b ldr r3, [r7, #4]
8001416: 681b ldr r3, [r3, #0]
8001418: 681a ldr r2, [r3, #0]
800141a: 687b ldr r3, [r7, #4]
800141c: 681b ldr r3, [r3, #0]
800141e: f022 020e bic.w r2, r2, #14
8001422: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
#endif /* DMAMUX1 */
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8001424: 687b ldr r3, [r7, #4]
8001426: 681b ldr r3, [r3, #0]
8001428: 681a ldr r2, [r3, #0]
800142a: 687b ldr r3, [r7, #4]
800142c: 681b ldr r3, [r3, #0]
800142e: f022 0201 bic.w r2, r2, #1
8001432: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
8001434: 687b ldr r3, [r7, #4]
8001436: 6c5b ldr r3, [r3, #68] ; 0x44
8001438: f003 021c and.w r2, r3, #28
800143c: 687b ldr r3, [r7, #4]
800143e: 6c1b ldr r3, [r3, #64] ; 0x40
8001440: 2101 movs r1, #1
8001442: fa01 f202 lsl.w r2, r1, r2
8001446: 605a str r2, [r3, #4]
}
#endif /* DMAMUX1 */
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001448: 687b ldr r3, [r7, #4]
800144a: 2201 movs r2, #1
800144c: f883 2025 strb.w r2, [r3, #37] ; 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001450: 687b ldr r3, [r7, #4]
8001452: 2200 movs r2, #0
8001454: f883 2024 strb.w r2, [r3, #36] ; 0x24
return status;
8001458: 7bfb ldrb r3, [r7, #15]
}
}
800145a: 4618 mov r0, r3
800145c: 3714 adds r7, #20
800145e: 46bd mov sp, r7
8001460: f85d 7b04 ldr.w r7, [sp], #4
8001464: 4770 bx lr
08001466 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8001466: b580 push {r7, lr}
8001468: b084 sub sp, #16
800146a: af00 add r7, sp, #0
800146c: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800146e: 2300 movs r3, #0
8001470: 73fb strb r3, [r7, #15]
if (HAL_DMA_STATE_BUSY != hdma->State)
8001472: 687b ldr r3, [r7, #4]
8001474: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
8001478: b2db uxtb r3, r3
800147a: 2b02 cmp r3, #2
800147c: d005 beq.n 800148a <HAL_DMA_Abort_IT+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800147e: 687b ldr r3, [r7, #4]
8001480: 2204 movs r2, #4
8001482: 63da str r2, [r3, #60] ; 0x3c
status = HAL_ERROR;
8001484: 2301 movs r3, #1
8001486: 73fb strb r3, [r7, #15]
8001488: e029 b.n 80014de <HAL_DMA_Abort_IT+0x78>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800148a: 687b ldr r3, [r7, #4]
800148c: 681b ldr r3, [r3, #0]
800148e: 681a ldr r2, [r3, #0]
8001490: 687b ldr r3, [r7, #4]
8001492: 681b ldr r3, [r3, #0]
8001494: f022 020e bic.w r2, r2, #14
8001498: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
800149a: 687b ldr r3, [r7, #4]
800149c: 681b ldr r3, [r3, #0]
800149e: 681a ldr r2, [r3, #0]
80014a0: 687b ldr r3, [r7, #4]
80014a2: 681b ldr r3, [r3, #0]
80014a4: f022 0201 bic.w r2, r2, #1
80014a8: 601a str r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
#else
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
80014aa: 687b ldr r3, [r7, #4]
80014ac: 6c5b ldr r3, [r3, #68] ; 0x44
80014ae: f003 021c and.w r2, r3, #28
80014b2: 687b ldr r3, [r7, #4]
80014b4: 6c1b ldr r3, [r3, #64] ; 0x40
80014b6: 2101 movs r1, #1
80014b8: fa01 f202 lsl.w r2, r1, r2
80014bc: 605a str r2, [r3, #4]
#endif /* DMAMUX1 */
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80014be: 687b ldr r3, [r7, #4]
80014c0: 2201 movs r2, #1
80014c2: f883 2025 strb.w r2, [r3, #37] ; 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80014c6: 687b ldr r3, [r7, #4]
80014c8: 2200 movs r2, #0
80014ca: f883 2024 strb.w r2, [r3, #36] ; 0x24
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
80014ce: 687b ldr r3, [r7, #4]
80014d0: 6b9b ldr r3, [r3, #56] ; 0x38
80014d2: 2b00 cmp r3, #0
80014d4: d003 beq.n 80014de <HAL_DMA_Abort_IT+0x78>
{
hdma->XferAbortCallback(hdma);
80014d6: 687b ldr r3, [r7, #4]
80014d8: 6b9b ldr r3, [r3, #56] ; 0x38
80014da: 6878 ldr r0, [r7, #4]
80014dc: 4798 blx r3
}
}
return status;
80014de: 7bfb ldrb r3, [r7, #15]
}
80014e0: 4618 mov r0, r3
80014e2: 3710 adds r7, #16
80014e4: 46bd mov sp, r7
80014e6: bd80 pop {r7, pc}
080014e8 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80014e8: b480 push {r7}
80014ea: b087 sub sp, #28
80014ec: af00 add r7, sp, #0
80014ee: 6078 str r0, [r7, #4]
80014f0: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80014f2: 2300 movs r3, #0
80014f4: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80014f6: e154 b.n 80017a2 <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80014f8: 683b ldr r3, [r7, #0]
80014fa: 681a ldr r2, [r3, #0]
80014fc: 2101 movs r1, #1
80014fe: 697b ldr r3, [r7, #20]
8001500: fa01 f303 lsl.w r3, r1, r3
8001504: 4013 ands r3, r2
8001506: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001508: 68fb ldr r3, [r7, #12]
800150a: 2b00 cmp r3, #0
800150c: f000 8146 beq.w 800179c <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001510: 683b ldr r3, [r7, #0]
8001512: 685b ldr r3, [r3, #4]
8001514: f003 0303 and.w r3, r3, #3
8001518: 2b01 cmp r3, #1
800151a: d005 beq.n 8001528 <HAL_GPIO_Init+0x40>
800151c: 683b ldr r3, [r7, #0]
800151e: 685b ldr r3, [r3, #4]
8001520: f003 0303 and.w r3, r3, #3
8001524: 2b02 cmp r3, #2
8001526: d130 bne.n 800158a <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001528: 687b ldr r3, [r7, #4]
800152a: 689b ldr r3, [r3, #8]
800152c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
800152e: 697b ldr r3, [r7, #20]
8001530: 005b lsls r3, r3, #1
8001532: 2203 movs r2, #3
8001534: fa02 f303 lsl.w r3, r2, r3
8001538: 43db mvns r3, r3
800153a: 693a ldr r2, [r7, #16]
800153c: 4013 ands r3, r2
800153e: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001540: 683b ldr r3, [r7, #0]
8001542: 68da ldr r2, [r3, #12]
8001544: 697b ldr r3, [r7, #20]
8001546: 005b lsls r3, r3, #1
8001548: fa02 f303 lsl.w r3, r2, r3
800154c: 693a ldr r2, [r7, #16]
800154e: 4313 orrs r3, r2
8001550: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001552: 687b ldr r3, [r7, #4]
8001554: 693a ldr r2, [r7, #16]
8001556: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001558: 687b ldr r3, [r7, #4]
800155a: 685b ldr r3, [r3, #4]
800155c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
800155e: 2201 movs r2, #1
8001560: 697b ldr r3, [r7, #20]
8001562: fa02 f303 lsl.w r3, r2, r3
8001566: 43db mvns r3, r3
8001568: 693a ldr r2, [r7, #16]
800156a: 4013 ands r3, r2
800156c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800156e: 683b ldr r3, [r7, #0]
8001570: 685b ldr r3, [r3, #4]
8001572: 091b lsrs r3, r3, #4
8001574: f003 0201 and.w r2, r3, #1
8001578: 697b ldr r3, [r7, #20]
800157a: fa02 f303 lsl.w r3, r2, r3
800157e: 693a ldr r2, [r7, #16]
8001580: 4313 orrs r3, r2
8001582: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001584: 687b ldr r3, [r7, #4]
8001586: 693a ldr r2, [r7, #16]
8001588: 605a str r2, [r3, #4]
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
800158a: 683b ldr r3, [r7, #0]
800158c: 685b ldr r3, [r3, #4]
800158e: f003 0303 and.w r3, r3, #3
8001592: 2b03 cmp r3, #3
8001594: d017 beq.n 80015c6 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
8001596: 687b ldr r3, [r7, #4]
8001598: 68db ldr r3, [r3, #12]
800159a: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
800159c: 697b ldr r3, [r7, #20]
800159e: 005b lsls r3, r3, #1
80015a0: 2203 movs r2, #3
80015a2: fa02 f303 lsl.w r3, r2, r3
80015a6: 43db mvns r3, r3
80015a8: 693a ldr r2, [r7, #16]
80015aa: 4013 ands r3, r2
80015ac: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80015ae: 683b ldr r3, [r7, #0]
80015b0: 689a ldr r2, [r3, #8]
80015b2: 697b ldr r3, [r7, #20]
80015b4: 005b lsls r3, r3, #1
80015b6: fa02 f303 lsl.w r3, r2, r3
80015ba: 693a ldr r2, [r7, #16]
80015bc: 4313 orrs r3, r2
80015be: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80015c0: 687b ldr r3, [r7, #4]
80015c2: 693a ldr r2, [r7, #16]
80015c4: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80015c6: 683b ldr r3, [r7, #0]
80015c8: 685b ldr r3, [r3, #4]
80015ca: f003 0303 and.w r3, r3, #3
80015ce: 2b02 cmp r3, #2
80015d0: d123 bne.n 800161a <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80015d2: 697b ldr r3, [r7, #20]
80015d4: 08da lsrs r2, r3, #3
80015d6: 687b ldr r3, [r7, #4]
80015d8: 3208 adds r2, #8
80015da: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80015de: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80015e0: 697b ldr r3, [r7, #20]
80015e2: f003 0307 and.w r3, r3, #7
80015e6: 009b lsls r3, r3, #2
80015e8: 220f movs r2, #15
80015ea: fa02 f303 lsl.w r3, r2, r3
80015ee: 43db mvns r3, r3
80015f0: 693a ldr r2, [r7, #16]
80015f2: 4013 ands r3, r2
80015f4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80015f6: 683b ldr r3, [r7, #0]
80015f8: 691a ldr r2, [r3, #16]
80015fa: 697b ldr r3, [r7, #20]
80015fc: f003 0307 and.w r3, r3, #7
8001600: 009b lsls r3, r3, #2
8001602: fa02 f303 lsl.w r3, r2, r3
8001606: 693a ldr r2, [r7, #16]
8001608: 4313 orrs r3, r2
800160a: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
800160c: 697b ldr r3, [r7, #20]
800160e: 08da lsrs r2, r3, #3
8001610: 687b ldr r3, [r7, #4]
8001612: 3208 adds r2, #8
8001614: 6939 ldr r1, [r7, #16]
8001616: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800161a: 687b ldr r3, [r7, #4]
800161c: 681b ldr r3, [r3, #0]
800161e: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8001620: 697b ldr r3, [r7, #20]
8001622: 005b lsls r3, r3, #1
8001624: 2203 movs r2, #3
8001626: fa02 f303 lsl.w r3, r2, r3
800162a: 43db mvns r3, r3
800162c: 693a ldr r2, [r7, #16]
800162e: 4013 ands r3, r2
8001630: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001632: 683b ldr r3, [r7, #0]
8001634: 685b ldr r3, [r3, #4]
8001636: f003 0203 and.w r2, r3, #3
800163a: 697b ldr r3, [r7, #20]
800163c: 005b lsls r3, r3, #1
800163e: fa02 f303 lsl.w r3, r2, r3
8001642: 693a ldr r2, [r7, #16]
8001644: 4313 orrs r3, r2
8001646: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001648: 687b ldr r3, [r7, #4]
800164a: 693a ldr r2, [r7, #16]
800164c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800164e: 683b ldr r3, [r7, #0]
8001650: 685b ldr r3, [r3, #4]
8001652: f403 3340 and.w r3, r3, #196608 ; 0x30000
8001656: 2b00 cmp r3, #0
8001658: f000 80a0 beq.w 800179c <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800165c: 4b58 ldr r3, [pc, #352] ; (80017c0 <HAL_GPIO_Init+0x2d8>)
800165e: 6e1b ldr r3, [r3, #96] ; 0x60
8001660: 4a57 ldr r2, [pc, #348] ; (80017c0 <HAL_GPIO_Init+0x2d8>)
8001662: f043 0301 orr.w r3, r3, #1
8001666: 6613 str r3, [r2, #96] ; 0x60
8001668: 4b55 ldr r3, [pc, #340] ; (80017c0 <HAL_GPIO_Init+0x2d8>)
800166a: 6e1b ldr r3, [r3, #96] ; 0x60
800166c: f003 0301 and.w r3, r3, #1
8001670: 60bb str r3, [r7, #8]
8001672: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001674: 4a53 ldr r2, [pc, #332] ; (80017c4 <HAL_GPIO_Init+0x2dc>)
8001676: 697b ldr r3, [r7, #20]
8001678: 089b lsrs r3, r3, #2
800167a: 3302 adds r3, #2
800167c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001680: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8001682: 697b ldr r3, [r7, #20]
8001684: f003 0303 and.w r3, r3, #3
8001688: 009b lsls r3, r3, #2
800168a: 220f movs r2, #15
800168c: fa02 f303 lsl.w r3, r2, r3
8001690: 43db mvns r3, r3
8001692: 693a ldr r2, [r7, #16]
8001694: 4013 ands r3, r2
8001696: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001698: 687b ldr r3, [r7, #4]
800169a: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
800169e: d019 beq.n 80016d4 <HAL_GPIO_Init+0x1ec>
80016a0: 687b ldr r3, [r7, #4]
80016a2: 4a49 ldr r2, [pc, #292] ; (80017c8 <HAL_GPIO_Init+0x2e0>)
80016a4: 4293 cmp r3, r2
80016a6: d013 beq.n 80016d0 <HAL_GPIO_Init+0x1e8>
80016a8: 687b ldr r3, [r7, #4]
80016aa: 4a48 ldr r2, [pc, #288] ; (80017cc <HAL_GPIO_Init+0x2e4>)
80016ac: 4293 cmp r3, r2
80016ae: d00d beq.n 80016cc <HAL_GPIO_Init+0x1e4>
80016b0: 687b ldr r3, [r7, #4]
80016b2: 4a47 ldr r2, [pc, #284] ; (80017d0 <HAL_GPIO_Init+0x2e8>)
80016b4: 4293 cmp r3, r2
80016b6: d007 beq.n 80016c8 <HAL_GPIO_Init+0x1e0>
80016b8: 687b ldr r3, [r7, #4]
80016ba: 4a46 ldr r2, [pc, #280] ; (80017d4 <HAL_GPIO_Init+0x2ec>)
80016bc: 4293 cmp r3, r2
80016be: d101 bne.n 80016c4 <HAL_GPIO_Init+0x1dc>
80016c0: 2304 movs r3, #4
80016c2: e008 b.n 80016d6 <HAL_GPIO_Init+0x1ee>
80016c4: 2307 movs r3, #7
80016c6: e006 b.n 80016d6 <HAL_GPIO_Init+0x1ee>
80016c8: 2303 movs r3, #3
80016ca: e004 b.n 80016d6 <HAL_GPIO_Init+0x1ee>
80016cc: 2302 movs r3, #2
80016ce: e002 b.n 80016d6 <HAL_GPIO_Init+0x1ee>
80016d0: 2301 movs r3, #1
80016d2: e000 b.n 80016d6 <HAL_GPIO_Init+0x1ee>
80016d4: 2300 movs r3, #0
80016d6: 697a ldr r2, [r7, #20]
80016d8: f002 0203 and.w r2, r2, #3
80016dc: 0092 lsls r2, r2, #2
80016de: 4093 lsls r3, r2
80016e0: 693a ldr r2, [r7, #16]
80016e2: 4313 orrs r3, r2
80016e4: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
80016e6: 4937 ldr r1, [pc, #220] ; (80017c4 <HAL_GPIO_Init+0x2dc>)
80016e8: 697b ldr r3, [r7, #20]
80016ea: 089b lsrs r3, r3, #2
80016ec: 3302 adds r3, #2
80016ee: 693a ldr r2, [r7, #16]
80016f0: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
80016f4: 4b38 ldr r3, [pc, #224] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
80016f6: 689b ldr r3, [r3, #8]
80016f8: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80016fa: 68fb ldr r3, [r7, #12]
80016fc: 43db mvns r3, r3
80016fe: 693a ldr r2, [r7, #16]
8001700: 4013 ands r3, r2
8001702: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001704: 683b ldr r3, [r7, #0]
8001706: 685b ldr r3, [r3, #4]
8001708: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800170c: 2b00 cmp r3, #0
800170e: d003 beq.n 8001718 <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
8001710: 693a ldr r2, [r7, #16]
8001712: 68fb ldr r3, [r7, #12]
8001714: 4313 orrs r3, r2
8001716: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8001718: 4a2f ldr r2, [pc, #188] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
800171a: 693b ldr r3, [r7, #16]
800171c: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
800171e: 4b2e ldr r3, [pc, #184] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
8001720: 68db ldr r3, [r3, #12]
8001722: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001724: 68fb ldr r3, [r7, #12]
8001726: 43db mvns r3, r3
8001728: 693a ldr r2, [r7, #16]
800172a: 4013 ands r3, r2
800172c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800172e: 683b ldr r3, [r7, #0]
8001730: 685b ldr r3, [r3, #4]
8001732: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001736: 2b00 cmp r3, #0
8001738: d003 beq.n 8001742 <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
800173a: 693a ldr r2, [r7, #16]
800173c: 68fb ldr r3, [r7, #12]
800173e: 4313 orrs r3, r2
8001740: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8001742: 4a25 ldr r2, [pc, #148] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
8001744: 693b ldr r3, [r7, #16]
8001746: 60d3 str r3, [r2, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8001748: 4b23 ldr r3, [pc, #140] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
800174a: 685b ldr r3, [r3, #4]
800174c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800174e: 68fb ldr r3, [r7, #12]
8001750: 43db mvns r3, r3
8001752: 693a ldr r2, [r7, #16]
8001754: 4013 ands r3, r2
8001756: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001758: 683b ldr r3, [r7, #0]
800175a: 685b ldr r3, [r3, #4]
800175c: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001760: 2b00 cmp r3, #0
8001762: d003 beq.n 800176c <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
8001764: 693a ldr r2, [r7, #16]
8001766: 68fb ldr r3, [r7, #12]
8001768: 4313 orrs r3, r2
800176a: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
800176c: 4a1a ldr r2, [pc, #104] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
800176e: 693b ldr r3, [r7, #16]
8001770: 6053 str r3, [r2, #4]
temp = EXTI->IMR1;
8001772: 4b19 ldr r3, [pc, #100] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
8001774: 681b ldr r3, [r3, #0]
8001776: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001778: 68fb ldr r3, [r7, #12]
800177a: 43db mvns r3, r3
800177c: 693a ldr r2, [r7, #16]
800177e: 4013 ands r3, r2
8001780: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001782: 683b ldr r3, [r7, #0]
8001784: 685b ldr r3, [r3, #4]
8001786: f403 3380 and.w r3, r3, #65536 ; 0x10000
800178a: 2b00 cmp r3, #0
800178c: d003 beq.n 8001796 <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
800178e: 693a ldr r2, [r7, #16]
8001790: 68fb ldr r3, [r7, #12]
8001792: 4313 orrs r3, r2
8001794: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8001796: 4a10 ldr r2, [pc, #64] ; (80017d8 <HAL_GPIO_Init+0x2f0>)
8001798: 693b ldr r3, [r7, #16]
800179a: 6013 str r3, [r2, #0]
}
}
position++;
800179c: 697b ldr r3, [r7, #20]
800179e: 3301 adds r3, #1
80017a0: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80017a2: 683b ldr r3, [r7, #0]
80017a4: 681a ldr r2, [r3, #0]
80017a6: 697b ldr r3, [r7, #20]
80017a8: fa22 f303 lsr.w r3, r2, r3
80017ac: 2b00 cmp r3, #0
80017ae: f47f aea3 bne.w 80014f8 <HAL_GPIO_Init+0x10>
}
}
80017b2: bf00 nop
80017b4: bf00 nop
80017b6: 371c adds r7, #28
80017b8: 46bd mov sp, r7
80017ba: f85d 7b04 ldr.w r7, [sp], #4
80017be: 4770 bx lr
80017c0: 40021000 .word 0x40021000
80017c4: 40010000 .word 0x40010000
80017c8: 48000400 .word 0x48000400
80017cc: 48000800 .word 0x48000800
80017d0: 48000c00 .word 0x48000c00
80017d4: 48001000 .word 0x48001000
80017d8: 40010400 .word 0x40010400
080017dc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80017dc: b480 push {r7}
80017de: b083 sub sp, #12
80017e0: af00 add r7, sp, #0
80017e2: 6078 str r0, [r7, #4]
80017e4: 460b mov r3, r1
80017e6: 807b strh r3, [r7, #2]
80017e8: 4613 mov r3, r2
80017ea: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80017ec: 787b ldrb r3, [r7, #1]
80017ee: 2b00 cmp r3, #0
80017f0: d003 beq.n 80017fa <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
80017f2: 887a ldrh r2, [r7, #2]
80017f4: 687b ldr r3, [r7, #4]
80017f6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
80017f8: e002 b.n 8001800 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
80017fa: 887a ldrh r2, [r7, #2]
80017fc: 687b ldr r3, [r7, #4]
80017fe: 629a str r2, [r3, #40] ; 0x28
}
8001800: bf00 nop
8001802: 370c adds r7, #12
8001804: 46bd mov sp, r7
8001806: f85d 7b04 ldr.w r7, [sp], #4
800180a: 4770 bx lr
0800180c <HAL_PWREx_GetVoltageRange>:
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
800180c: b480 push {r7}
800180e: af00 add r7, sp, #0
else
{
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
}
#else
return (PWR->CR1 & PWR_CR1_VOS);
8001810: 4b04 ldr r3, [pc, #16] ; (8001824 <HAL_PWREx_GetVoltageRange+0x18>)
8001812: 681b ldr r3, [r3, #0]
8001814: f403 63c0 and.w r3, r3, #1536 ; 0x600
#endif
}
8001818: 4618 mov r0, r3
800181a: 46bd mov sp, r7
800181c: f85d 7b04 ldr.w r7, [sp], #4
8001820: 4770 bx lr
8001822: bf00 nop
8001824: 40007000 .word 0x40007000
08001828 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8001828: b480 push {r7}
800182a: b085 sub sp, #20
800182c: af00 add r7, sp, #0
800182e: 6078 str r0, [r7, #4]
}
#else
/* If Set Range 1 */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8001830: 687b ldr r3, [r7, #4]
8001832: f5b3 7f00 cmp.w r3, #512 ; 0x200
8001836: d130 bne.n 800189a <HAL_PWREx_ControlVoltageScaling+0x72>
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
8001838: 4b23 ldr r3, [pc, #140] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
800183a: 681b ldr r3, [r3, #0]
800183c: f403 63c0 and.w r3, r3, #1536 ; 0x600
8001840: f5b3 7f00 cmp.w r3, #512 ; 0x200
8001844: d038 beq.n 80018b8 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8001846: 4b20 ldr r3, [pc, #128] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8001848: 681b ldr r3, [r3, #0]
800184a: f423 63c0 bic.w r3, r3, #1536 ; 0x600
800184e: 4a1e ldr r2, [pc, #120] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8001850: f443 7300 orr.w r3, r3, #512 ; 0x200
8001854: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8001856: 4b1d ldr r3, [pc, #116] ; (80018cc <HAL_PWREx_ControlVoltageScaling+0xa4>)
8001858: 681b ldr r3, [r3, #0]
800185a: 2232 movs r2, #50 ; 0x32
800185c: fb02 f303 mul.w r3, r2, r3
8001860: 4a1b ldr r2, [pc, #108] ; (80018d0 <HAL_PWREx_ControlVoltageScaling+0xa8>)
8001862: fba2 2303 umull r2, r3, r2, r3
8001866: 0c9b lsrs r3, r3, #18
8001868: 3301 adds r3, #1
800186a: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
800186c: e002 b.n 8001874 <HAL_PWREx_ControlVoltageScaling+0x4c>
{
wait_loop_index--;
800186e: 68fb ldr r3, [r7, #12]
8001870: 3b01 subs r3, #1
8001872: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8001874: 4b14 ldr r3, [pc, #80] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8001876: 695b ldr r3, [r3, #20]
8001878: f403 6380 and.w r3, r3, #1024 ; 0x400
800187c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8001880: d102 bne.n 8001888 <HAL_PWREx_ControlVoltageScaling+0x60>
8001882: 68fb ldr r3, [r7, #12]
8001884: 2b00 cmp r3, #0
8001886: d1f2 bne.n 800186e <HAL_PWREx_ControlVoltageScaling+0x46>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8001888: 4b0f ldr r3, [pc, #60] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
800188a: 695b ldr r3, [r3, #20]
800188c: f403 6380 and.w r3, r3, #1024 ; 0x400
8001890: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8001894: d110 bne.n 80018b8 <HAL_PWREx_ControlVoltageScaling+0x90>
{
return HAL_TIMEOUT;
8001896: 2303 movs r3, #3
8001898: e00f b.n 80018ba <HAL_PWREx_ControlVoltageScaling+0x92>
}
}
}
else
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
800189a: 4b0b ldr r3, [pc, #44] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
800189c: 681b ldr r3, [r3, #0]
800189e: f403 63c0 and.w r3, r3, #1536 ; 0x600
80018a2: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80018a6: d007 beq.n 80018b8 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
80018a8: 4b07 ldr r3, [pc, #28] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80018aa: 681b ldr r3, [r3, #0]
80018ac: f423 63c0 bic.w r3, r3, #1536 ; 0x600
80018b0: 4a05 ldr r2, [pc, #20] ; (80018c8 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80018b2: f443 6380 orr.w r3, r3, #1024 ; 0x400
80018b6: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
}
}
#endif
return HAL_OK;
80018b8: 2300 movs r3, #0
}
80018ba: 4618 mov r0, r3
80018bc: 3714 adds r7, #20
80018be: 46bd mov sp, r7
80018c0: f85d 7b04 ldr.w r7, [sp], #4
80018c4: 4770 bx lr
80018c6: bf00 nop
80018c8: 40007000 .word 0x40007000
80018cc: 20000004 .word 0x20000004
80018d0: 431bde83 .word 0x431bde83
080018d4 <HAL_RCC_OscConfig>:
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80018d4: b580 push {r7, lr}
80018d6: b088 sub sp, #32
80018d8: af00 add r7, sp, #0
80018da: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80018dc: 687b ldr r3, [r7, #4]
80018de: 2b00 cmp r3, #0
80018e0: d102 bne.n 80018e8 <HAL_RCC_OscConfig+0x14>
{
return HAL_ERROR;
80018e2: 2301 movs r3, #1
80018e4: f000 bc02 b.w 80020ec <HAL_RCC_OscConfig+0x818>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
80018e8: 4b96 ldr r3, [pc, #600] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80018ea: 689b ldr r3, [r3, #8]
80018ec: f003 030c and.w r3, r3, #12
80018f0: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
80018f2: 4b94 ldr r3, [pc, #592] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80018f4: 68db ldr r3, [r3, #12]
80018f6: f003 0303 and.w r3, r3, #3
80018fa: 617b str r3, [r7, #20]
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
80018fc: 687b ldr r3, [r7, #4]
80018fe: 681b ldr r3, [r3, #0]
8001900: f003 0310 and.w r3, r3, #16
8001904: 2b00 cmp r3, #0
8001906: f000 80e4 beq.w 8001ad2 <HAL_RCC_OscConfig+0x1fe>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
800190a: 69bb ldr r3, [r7, #24]
800190c: 2b00 cmp r3, #0
800190e: d007 beq.n 8001920 <HAL_RCC_OscConfig+0x4c>
8001910: 69bb ldr r3, [r7, #24]
8001912: 2b0c cmp r3, #12
8001914: f040 808b bne.w 8001a2e <HAL_RCC_OscConfig+0x15a>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
8001918: 697b ldr r3, [r7, #20]
800191a: 2b01 cmp r3, #1
800191c: f040 8087 bne.w 8001a2e <HAL_RCC_OscConfig+0x15a>
{
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001920: 4b88 ldr r3, [pc, #544] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001922: 681b ldr r3, [r3, #0]
8001924: f003 0302 and.w r3, r3, #2
8001928: 2b00 cmp r3, #0
800192a: d005 beq.n 8001938 <HAL_RCC_OscConfig+0x64>
800192c: 687b ldr r3, [r7, #4]
800192e: 699b ldr r3, [r3, #24]
8001930: 2b00 cmp r3, #0
8001932: d101 bne.n 8001938 <HAL_RCC_OscConfig+0x64>
{
return HAL_ERROR;
8001934: 2301 movs r3, #1
8001936: e3d9 b.n 80020ec <HAL_RCC_OscConfig+0x818>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8001938: 687b ldr r3, [r7, #4]
800193a: 6a1a ldr r2, [r3, #32]
800193c: 4b81 ldr r3, [pc, #516] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
800193e: 681b ldr r3, [r3, #0]
8001940: f003 0308 and.w r3, r3, #8
8001944: 2b00 cmp r3, #0
8001946: d004 beq.n 8001952 <HAL_RCC_OscConfig+0x7e>
8001948: 4b7e ldr r3, [pc, #504] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
800194a: 681b ldr r3, [r3, #0]
800194c: f003 03f0 and.w r3, r3, #240 ; 0xf0
8001950: e005 b.n 800195e <HAL_RCC_OscConfig+0x8a>
8001952: 4b7c ldr r3, [pc, #496] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001954: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8001958: 091b lsrs r3, r3, #4
800195a: f003 03f0 and.w r3, r3, #240 ; 0xf0
800195e: 4293 cmp r3, r2
8001960: d223 bcs.n 80019aa <HAL_RCC_OscConfig+0xd6>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001962: 687b ldr r3, [r7, #4]
8001964: 6a1b ldr r3, [r3, #32]
8001966: 4618 mov r0, r3
8001968: f000 fd8c bl 8002484 <RCC_SetFlashLatencyFromMSIRange>
800196c: 4603 mov r3, r0
800196e: 2b00 cmp r3, #0
8001970: d001 beq.n 8001976 <HAL_RCC_OscConfig+0xa2>
{
return HAL_ERROR;
8001972: 2301 movs r3, #1
8001974: e3ba b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001976: 4b73 ldr r3, [pc, #460] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001978: 681b ldr r3, [r3, #0]
800197a: 4a72 ldr r2, [pc, #456] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
800197c: f043 0308 orr.w r3, r3, #8
8001980: 6013 str r3, [r2, #0]
8001982: 4b70 ldr r3, [pc, #448] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001984: 681b ldr r3, [r3, #0]
8001986: f023 02f0 bic.w r2, r3, #240 ; 0xf0
800198a: 687b ldr r3, [r7, #4]
800198c: 6a1b ldr r3, [r3, #32]
800198e: 496d ldr r1, [pc, #436] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001990: 4313 orrs r3, r2
8001992: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001994: 4b6b ldr r3, [pc, #428] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001996: 685b ldr r3, [r3, #4]
8001998: f423 427f bic.w r2, r3, #65280 ; 0xff00
800199c: 687b ldr r3, [r7, #4]
800199e: 69db ldr r3, [r3, #28]
80019a0: 021b lsls r3, r3, #8
80019a2: 4968 ldr r1, [pc, #416] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019a4: 4313 orrs r3, r2
80019a6: 604b str r3, [r1, #4]
80019a8: e025 b.n 80019f6 <HAL_RCC_OscConfig+0x122>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80019aa: 4b66 ldr r3, [pc, #408] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019ac: 681b ldr r3, [r3, #0]
80019ae: 4a65 ldr r2, [pc, #404] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019b0: f043 0308 orr.w r3, r3, #8
80019b4: 6013 str r3, [r2, #0]
80019b6: 4b63 ldr r3, [pc, #396] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019b8: 681b ldr r3, [r3, #0]
80019ba: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80019be: 687b ldr r3, [r7, #4]
80019c0: 6a1b ldr r3, [r3, #32]
80019c2: 4960 ldr r1, [pc, #384] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019c4: 4313 orrs r3, r2
80019c6: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80019c8: 4b5e ldr r3, [pc, #376] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019ca: 685b ldr r3, [r3, #4]
80019cc: f423 427f bic.w r2, r3, #65280 ; 0xff00
80019d0: 687b ldr r3, [r7, #4]
80019d2: 69db ldr r3, [r3, #28]
80019d4: 021b lsls r3, r3, #8
80019d6: 495b ldr r1, [pc, #364] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019d8: 4313 orrs r3, r2
80019da: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
if(sysclk_source == RCC_CFGR_SWS_MSI)
80019dc: 69bb ldr r3, [r7, #24]
80019de: 2b00 cmp r3, #0
80019e0: d109 bne.n 80019f6 <HAL_RCC_OscConfig+0x122>
{
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80019e2: 687b ldr r3, [r7, #4]
80019e4: 6a1b ldr r3, [r3, #32]
80019e6: 4618 mov r0, r3
80019e8: f000 fd4c bl 8002484 <RCC_SetFlashLatencyFromMSIRange>
80019ec: 4603 mov r3, r0
80019ee: 2b00 cmp r3, #0
80019f0: d001 beq.n 80019f6 <HAL_RCC_OscConfig+0x122>
{
return HAL_ERROR;
80019f2: 2301 movs r3, #1
80019f4: e37a b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
80019f6: f000 fc81 bl 80022fc <HAL_RCC_GetSysClockFreq>
80019fa: 4602 mov r2, r0
80019fc: 4b51 ldr r3, [pc, #324] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
80019fe: 689b ldr r3, [r3, #8]
8001a00: 091b lsrs r3, r3, #4
8001a02: f003 030f and.w r3, r3, #15
8001a06: 4950 ldr r1, [pc, #320] ; (8001b48 <HAL_RCC_OscConfig+0x274>)
8001a08: 5ccb ldrb r3, [r1, r3]
8001a0a: f003 031f and.w r3, r3, #31
8001a0e: fa22 f303 lsr.w r3, r2, r3
8001a12: 4a4e ldr r2, [pc, #312] ; (8001b4c <HAL_RCC_OscConfig+0x278>)
8001a14: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8001a16: 4b4e ldr r3, [pc, #312] ; (8001b50 <HAL_RCC_OscConfig+0x27c>)
8001a18: 681b ldr r3, [r3, #0]
8001a1a: 4618 mov r0, r3
8001a1c: f7ff fb54 bl 80010c8 <HAL_InitTick>
8001a20: 4603 mov r3, r0
8001a22: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
8001a24: 7bfb ldrb r3, [r7, #15]
8001a26: 2b00 cmp r3, #0
8001a28: d052 beq.n 8001ad0 <HAL_RCC_OscConfig+0x1fc>
{
return status;
8001a2a: 7bfb ldrb r3, [r7, #15]
8001a2c: e35e b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
}
else
{
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8001a2e: 687b ldr r3, [r7, #4]
8001a30: 699b ldr r3, [r3, #24]
8001a32: 2b00 cmp r3, #0
8001a34: d032 beq.n 8001a9c <HAL_RCC_OscConfig+0x1c8>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8001a36: 4b43 ldr r3, [pc, #268] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a38: 681b ldr r3, [r3, #0]
8001a3a: 4a42 ldr r2, [pc, #264] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a3c: f043 0301 orr.w r3, r3, #1
8001a40: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8001a42: f7ff fb91 bl 8001168 <HAL_GetTick>
8001a46: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8001a48: e008 b.n 8001a5c <HAL_RCC_OscConfig+0x188>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001a4a: f7ff fb8d bl 8001168 <HAL_GetTick>
8001a4e: 4602 mov r2, r0
8001a50: 693b ldr r3, [r7, #16]
8001a52: 1ad3 subs r3, r2, r3
8001a54: 2b02 cmp r3, #2
8001a56: d901 bls.n 8001a5c <HAL_RCC_OscConfig+0x188>
{
return HAL_TIMEOUT;
8001a58: 2303 movs r3, #3
8001a5a: e347 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8001a5c: 4b39 ldr r3, [pc, #228] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a5e: 681b ldr r3, [r3, #0]
8001a60: f003 0302 and.w r3, r3, #2
8001a64: 2b00 cmp r3, #0
8001a66: d0f0 beq.n 8001a4a <HAL_RCC_OscConfig+0x176>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001a68: 4b36 ldr r3, [pc, #216] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a6a: 681b ldr r3, [r3, #0]
8001a6c: 4a35 ldr r2, [pc, #212] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a6e: f043 0308 orr.w r3, r3, #8
8001a72: 6013 str r3, [r2, #0]
8001a74: 4b33 ldr r3, [pc, #204] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a76: 681b ldr r3, [r3, #0]
8001a78: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001a7c: 687b ldr r3, [r7, #4]
8001a7e: 6a1b ldr r3, [r3, #32]
8001a80: 4930 ldr r1, [pc, #192] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a82: 4313 orrs r3, r2
8001a84: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001a86: 4b2f ldr r3, [pc, #188] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a88: 685b ldr r3, [r3, #4]
8001a8a: f423 427f bic.w r2, r3, #65280 ; 0xff00
8001a8e: 687b ldr r3, [r7, #4]
8001a90: 69db ldr r3, [r3, #28]
8001a92: 021b lsls r3, r3, #8
8001a94: 492b ldr r1, [pc, #172] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a96: 4313 orrs r3, r2
8001a98: 604b str r3, [r1, #4]
8001a9a: e01a b.n 8001ad2 <HAL_RCC_OscConfig+0x1fe>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
8001a9c: 4b29 ldr r3, [pc, #164] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001a9e: 681b ldr r3, [r3, #0]
8001aa0: 4a28 ldr r2, [pc, #160] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001aa2: f023 0301 bic.w r3, r3, #1
8001aa6: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8001aa8: f7ff fb5e bl 8001168 <HAL_GetTick>
8001aac: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8001aae: e008 b.n 8001ac2 <HAL_RCC_OscConfig+0x1ee>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001ab0: f7ff fb5a bl 8001168 <HAL_GetTick>
8001ab4: 4602 mov r2, r0
8001ab6: 693b ldr r3, [r7, #16]
8001ab8: 1ad3 subs r3, r2, r3
8001aba: 2b02 cmp r3, #2
8001abc: d901 bls.n 8001ac2 <HAL_RCC_OscConfig+0x1ee>
{
return HAL_TIMEOUT;
8001abe: 2303 movs r3, #3
8001ac0: e314 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8001ac2: 4b20 ldr r3, [pc, #128] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001ac4: 681b ldr r3, [r3, #0]
8001ac6: f003 0302 and.w r3, r3, #2
8001aca: 2b00 cmp r3, #0
8001acc: d1f0 bne.n 8001ab0 <HAL_RCC_OscConfig+0x1dc>
8001ace: e000 b.n 8001ad2 <HAL_RCC_OscConfig+0x1fe>
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001ad0: bf00 nop
}
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001ad2: 687b ldr r3, [r7, #4]
8001ad4: 681b ldr r3, [r3, #0]
8001ad6: f003 0301 and.w r3, r3, #1
8001ada: 2b00 cmp r3, #0
8001adc: d073 beq.n 8001bc6 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
8001ade: 69bb ldr r3, [r7, #24]
8001ae0: 2b08 cmp r3, #8
8001ae2: d005 beq.n 8001af0 <HAL_RCC_OscConfig+0x21c>
8001ae4: 69bb ldr r3, [r7, #24]
8001ae6: 2b0c cmp r3, #12
8001ae8: d10e bne.n 8001b08 <HAL_RCC_OscConfig+0x234>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
8001aea: 697b ldr r3, [r7, #20]
8001aec: 2b03 cmp r3, #3
8001aee: d10b bne.n 8001b08 <HAL_RCC_OscConfig+0x234>
{
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001af0: 4b14 ldr r3, [pc, #80] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001af2: 681b ldr r3, [r3, #0]
8001af4: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001af8: 2b00 cmp r3, #0
8001afa: d063 beq.n 8001bc4 <HAL_RCC_OscConfig+0x2f0>
8001afc: 687b ldr r3, [r7, #4]
8001afe: 685b ldr r3, [r3, #4]
8001b00: 2b00 cmp r3, #0
8001b02: d15f bne.n 8001bc4 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_ERROR;
8001b04: 2301 movs r3, #1
8001b06: e2f1 b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001b08: 687b ldr r3, [r7, #4]
8001b0a: 685b ldr r3, [r3, #4]
8001b0c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001b10: d106 bne.n 8001b20 <HAL_RCC_OscConfig+0x24c>
8001b12: 4b0c ldr r3, [pc, #48] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001b14: 681b ldr r3, [r3, #0]
8001b16: 4a0b ldr r2, [pc, #44] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001b18: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001b1c: 6013 str r3, [r2, #0]
8001b1e: e025 b.n 8001b6c <HAL_RCC_OscConfig+0x298>
8001b20: 687b ldr r3, [r7, #4]
8001b22: 685b ldr r3, [r3, #4]
8001b24: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8001b28: d114 bne.n 8001b54 <HAL_RCC_OscConfig+0x280>
8001b2a: 4b06 ldr r3, [pc, #24] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001b2c: 681b ldr r3, [r3, #0]
8001b2e: 4a05 ldr r2, [pc, #20] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001b30: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001b34: 6013 str r3, [r2, #0]
8001b36: 4b03 ldr r3, [pc, #12] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001b38: 681b ldr r3, [r3, #0]
8001b3a: 4a02 ldr r2, [pc, #8] ; (8001b44 <HAL_RCC_OscConfig+0x270>)
8001b3c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001b40: 6013 str r3, [r2, #0]
8001b42: e013 b.n 8001b6c <HAL_RCC_OscConfig+0x298>
8001b44: 40021000 .word 0x40021000
8001b48: 08005f18 .word 0x08005f18
8001b4c: 20000004 .word 0x20000004
8001b50: 20000008 .word 0x20000008
8001b54: 4ba0 ldr r3, [pc, #640] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001b56: 681b ldr r3, [r3, #0]
8001b58: 4a9f ldr r2, [pc, #636] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001b5a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001b5e: 6013 str r3, [r2, #0]
8001b60: 4b9d ldr r3, [pc, #628] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001b62: 681b ldr r3, [r3, #0]
8001b64: 4a9c ldr r2, [pc, #624] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001b66: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8001b6a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 685b ldr r3, [r3, #4]
8001b70: 2b00 cmp r3, #0
8001b72: d013 beq.n 8001b9c <HAL_RCC_OscConfig+0x2c8>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001b74: f7ff faf8 bl 8001168 <HAL_GetTick>
8001b78: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001b7a: e008 b.n 8001b8e <HAL_RCC_OscConfig+0x2ba>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001b7c: f7ff faf4 bl 8001168 <HAL_GetTick>
8001b80: 4602 mov r2, r0
8001b82: 693b ldr r3, [r7, #16]
8001b84: 1ad3 subs r3, r2, r3
8001b86: 2b64 cmp r3, #100 ; 0x64
8001b88: d901 bls.n 8001b8e <HAL_RCC_OscConfig+0x2ba>
{
return HAL_TIMEOUT;
8001b8a: 2303 movs r3, #3
8001b8c: e2ae b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001b8e: 4b92 ldr r3, [pc, #584] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001b90: 681b ldr r3, [r3, #0]
8001b92: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001b96: 2b00 cmp r3, #0
8001b98: d0f0 beq.n 8001b7c <HAL_RCC_OscConfig+0x2a8>
8001b9a: e014 b.n 8001bc6 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001b9c: f7ff fae4 bl 8001168 <HAL_GetTick>
8001ba0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001ba2: e008 b.n 8001bb6 <HAL_RCC_OscConfig+0x2e2>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001ba4: f7ff fae0 bl 8001168 <HAL_GetTick>
8001ba8: 4602 mov r2, r0
8001baa: 693b ldr r3, [r7, #16]
8001bac: 1ad3 subs r3, r2, r3
8001bae: 2b64 cmp r3, #100 ; 0x64
8001bb0: d901 bls.n 8001bb6 <HAL_RCC_OscConfig+0x2e2>
{
return HAL_TIMEOUT;
8001bb2: 2303 movs r3, #3
8001bb4: e29a b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001bb6: 4b88 ldr r3, [pc, #544] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001bb8: 681b ldr r3, [r3, #0]
8001bba: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001bbe: 2b00 cmp r3, #0
8001bc0: d1f0 bne.n 8001ba4 <HAL_RCC_OscConfig+0x2d0>
8001bc2: e000 b.n 8001bc6 <HAL_RCC_OscConfig+0x2f2>
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001bc4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001bc6: 687b ldr r3, [r7, #4]
8001bc8: 681b ldr r3, [r3, #0]
8001bca: f003 0302 and.w r3, r3, #2
8001bce: 2b00 cmp r3, #0
8001bd0: d060 beq.n 8001c94 <HAL_RCC_OscConfig+0x3c0>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
8001bd2: 69bb ldr r3, [r7, #24]
8001bd4: 2b04 cmp r3, #4
8001bd6: d005 beq.n 8001be4 <HAL_RCC_OscConfig+0x310>
8001bd8: 69bb ldr r3, [r7, #24]
8001bda: 2b0c cmp r3, #12
8001bdc: d119 bne.n 8001c12 <HAL_RCC_OscConfig+0x33e>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
8001bde: 697b ldr r3, [r7, #20]
8001be0: 2b02 cmp r3, #2
8001be2: d116 bne.n 8001c12 <HAL_RCC_OscConfig+0x33e>
{
/* When HSI is used as system clock it will not be disabled */
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8001be4: 4b7c ldr r3, [pc, #496] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001be6: 681b ldr r3, [r3, #0]
8001be8: f403 6380 and.w r3, r3, #1024 ; 0x400
8001bec: 2b00 cmp r3, #0
8001bee: d005 beq.n 8001bfc <HAL_RCC_OscConfig+0x328>
8001bf0: 687b ldr r3, [r7, #4]
8001bf2: 68db ldr r3, [r3, #12]
8001bf4: 2b00 cmp r3, #0
8001bf6: d101 bne.n 8001bfc <HAL_RCC_OscConfig+0x328>
{
return HAL_ERROR;
8001bf8: 2301 movs r3, #1
8001bfa: e277 b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001bfc: 4b76 ldr r3, [pc, #472] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001bfe: 685b ldr r3, [r3, #4]
8001c00: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000
8001c04: 687b ldr r3, [r7, #4]
8001c06: 691b ldr r3, [r3, #16]
8001c08: 061b lsls r3, r3, #24
8001c0a: 4973 ldr r1, [pc, #460] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c0c: 4313 orrs r3, r2
8001c0e: 604b str r3, [r1, #4]
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8001c10: e040 b.n 8001c94 <HAL_RCC_OscConfig+0x3c0>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8001c12: 687b ldr r3, [r7, #4]
8001c14: 68db ldr r3, [r3, #12]
8001c16: 2b00 cmp r3, #0
8001c18: d023 beq.n 8001c62 <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001c1a: 4b6f ldr r3, [pc, #444] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c1c: 681b ldr r3, [r3, #0]
8001c1e: 4a6e ldr r2, [pc, #440] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c20: f443 7380 orr.w r3, r3, #256 ; 0x100
8001c24: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001c26: f7ff fa9f bl 8001168 <HAL_GetTick>
8001c2a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001c2c: e008 b.n 8001c40 <HAL_RCC_OscConfig+0x36c>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001c2e: f7ff fa9b bl 8001168 <HAL_GetTick>
8001c32: 4602 mov r2, r0
8001c34: 693b ldr r3, [r7, #16]
8001c36: 1ad3 subs r3, r2, r3
8001c38: 2b02 cmp r3, #2
8001c3a: d901 bls.n 8001c40 <HAL_RCC_OscConfig+0x36c>
{
return HAL_TIMEOUT;
8001c3c: 2303 movs r3, #3
8001c3e: e255 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001c40: 4b65 ldr r3, [pc, #404] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c42: 681b ldr r3, [r3, #0]
8001c44: f403 6380 and.w r3, r3, #1024 ; 0x400
8001c48: 2b00 cmp r3, #0
8001c4a: d0f0 beq.n 8001c2e <HAL_RCC_OscConfig+0x35a>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001c4c: 4b62 ldr r3, [pc, #392] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c4e: 685b ldr r3, [r3, #4]
8001c50: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000
8001c54: 687b ldr r3, [r7, #4]
8001c56: 691b ldr r3, [r3, #16]
8001c58: 061b lsls r3, r3, #24
8001c5a: 495f ldr r1, [pc, #380] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c5c: 4313 orrs r3, r2
8001c5e: 604b str r3, [r1, #4]
8001c60: e018 b.n 8001c94 <HAL_RCC_OscConfig+0x3c0>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001c62: 4b5d ldr r3, [pc, #372] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c64: 681b ldr r3, [r3, #0]
8001c66: 4a5c ldr r2, [pc, #368] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c68: f423 7380 bic.w r3, r3, #256 ; 0x100
8001c6c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001c6e: f7ff fa7b bl 8001168 <HAL_GetTick>
8001c72: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8001c74: e008 b.n 8001c88 <HAL_RCC_OscConfig+0x3b4>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001c76: f7ff fa77 bl 8001168 <HAL_GetTick>
8001c7a: 4602 mov r2, r0
8001c7c: 693b ldr r3, [r7, #16]
8001c7e: 1ad3 subs r3, r2, r3
8001c80: 2b02 cmp r3, #2
8001c82: d901 bls.n 8001c88 <HAL_RCC_OscConfig+0x3b4>
{
return HAL_TIMEOUT;
8001c84: 2303 movs r3, #3
8001c86: e231 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8001c88: 4b53 ldr r3, [pc, #332] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001c8a: 681b ldr r3, [r3, #0]
8001c8c: f403 6380 and.w r3, r3, #1024 ; 0x400
8001c90: 2b00 cmp r3, #0
8001c92: d1f0 bne.n 8001c76 <HAL_RCC_OscConfig+0x3a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001c94: 687b ldr r3, [r7, #4]
8001c96: 681b ldr r3, [r3, #0]
8001c98: f003 0308 and.w r3, r3, #8
8001c9c: 2b00 cmp r3, #0
8001c9e: d03c beq.n 8001d1a <HAL_RCC_OscConfig+0x446>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001ca0: 687b ldr r3, [r7, #4]
8001ca2: 695b ldr r3, [r3, #20]
8001ca4: 2b00 cmp r3, #0
8001ca6: d01c beq.n 8001ce2 <HAL_RCC_OscConfig+0x40e>
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
}
#endif /* RCC_CSR_LSIPREDIV */
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001ca8: 4b4b ldr r3, [pc, #300] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001caa: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8001cae: 4a4a ldr r2, [pc, #296] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001cb0: f043 0301 orr.w r3, r3, #1
8001cb4: f8c2 3094 str.w r3, [r2, #148] ; 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cb8: f7ff fa56 bl 8001168 <HAL_GetTick>
8001cbc: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001cbe: e008 b.n 8001cd2 <HAL_RCC_OscConfig+0x3fe>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001cc0: f7ff fa52 bl 8001168 <HAL_GetTick>
8001cc4: 4602 mov r2, r0
8001cc6: 693b ldr r3, [r7, #16]
8001cc8: 1ad3 subs r3, r2, r3
8001cca: 2b02 cmp r3, #2
8001ccc: d901 bls.n 8001cd2 <HAL_RCC_OscConfig+0x3fe>
{
return HAL_TIMEOUT;
8001cce: 2303 movs r3, #3
8001cd0: e20c b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001cd2: 4b41 ldr r3, [pc, #260] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001cd4: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8001cd8: f003 0302 and.w r3, r3, #2
8001cdc: 2b00 cmp r3, #0
8001cde: d0ef beq.n 8001cc0 <HAL_RCC_OscConfig+0x3ec>
8001ce0: e01b b.n 8001d1a <HAL_RCC_OscConfig+0x446>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001ce2: 4b3d ldr r3, [pc, #244] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001ce4: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8001ce8: 4a3b ldr r2, [pc, #236] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001cea: f023 0301 bic.w r3, r3, #1
8001cee: f8c2 3094 str.w r3, [r2, #148] ; 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cf2: f7ff fa39 bl 8001168 <HAL_GetTick>
8001cf6: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8001cf8: e008 b.n 8001d0c <HAL_RCC_OscConfig+0x438>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001cfa: f7ff fa35 bl 8001168 <HAL_GetTick>
8001cfe: 4602 mov r2, r0
8001d00: 693b ldr r3, [r7, #16]
8001d02: 1ad3 subs r3, r2, r3
8001d04: 2b02 cmp r3, #2
8001d06: d901 bls.n 8001d0c <HAL_RCC_OscConfig+0x438>
{
return HAL_TIMEOUT;
8001d08: 2303 movs r3, #3
8001d0a: e1ef b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8001d0c: 4b32 ldr r3, [pc, #200] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001d0e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8001d12: f003 0302 and.w r3, r3, #2
8001d16: 2b00 cmp r3, #0
8001d18: d1ef bne.n 8001cfa <HAL_RCC_OscConfig+0x426>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001d1a: 687b ldr r3, [r7, #4]
8001d1c: 681b ldr r3, [r3, #0]
8001d1e: f003 0304 and.w r3, r3, #4
8001d22: 2b00 cmp r3, #0
8001d24: f000 80a6 beq.w 8001e74 <HAL_RCC_OscConfig+0x5a0>
{
FlagStatus pwrclkchanged = RESET;
8001d28: 2300 movs r3, #0
8001d2a: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
8001d2c: 4b2a ldr r3, [pc, #168] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001d2e: 6d9b ldr r3, [r3, #88] ; 0x58
8001d30: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001d34: 2b00 cmp r3, #0
8001d36: d10d bne.n 8001d54 <HAL_RCC_OscConfig+0x480>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001d38: 4b27 ldr r3, [pc, #156] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001d3a: 6d9b ldr r3, [r3, #88] ; 0x58
8001d3c: 4a26 ldr r2, [pc, #152] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001d3e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001d42: 6593 str r3, [r2, #88] ; 0x58
8001d44: 4b24 ldr r3, [pc, #144] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001d46: 6d9b ldr r3, [r3, #88] ; 0x58
8001d48: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001d4c: 60bb str r3, [r7, #8]
8001d4e: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001d50: 2301 movs r3, #1
8001d52: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001d54: 4b21 ldr r3, [pc, #132] ; (8001ddc <HAL_RCC_OscConfig+0x508>)
8001d56: 681b ldr r3, [r3, #0]
8001d58: f403 7380 and.w r3, r3, #256 ; 0x100
8001d5c: 2b00 cmp r3, #0
8001d5e: d118 bne.n 8001d92 <HAL_RCC_OscConfig+0x4be>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8001d60: 4b1e ldr r3, [pc, #120] ; (8001ddc <HAL_RCC_OscConfig+0x508>)
8001d62: 681b ldr r3, [r3, #0]
8001d64: 4a1d ldr r2, [pc, #116] ; (8001ddc <HAL_RCC_OscConfig+0x508>)
8001d66: f443 7380 orr.w r3, r3, #256 ; 0x100
8001d6a: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001d6c: f7ff f9fc bl 8001168 <HAL_GetTick>
8001d70: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001d72: e008 b.n 8001d86 <HAL_RCC_OscConfig+0x4b2>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001d74: f7ff f9f8 bl 8001168 <HAL_GetTick>
8001d78: 4602 mov r2, r0
8001d7a: 693b ldr r3, [r7, #16]
8001d7c: 1ad3 subs r3, r2, r3
8001d7e: 2b02 cmp r3, #2
8001d80: d901 bls.n 8001d86 <HAL_RCC_OscConfig+0x4b2>
{
return HAL_TIMEOUT;
8001d82: 2303 movs r3, #3
8001d84: e1b2 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001d86: 4b15 ldr r3, [pc, #84] ; (8001ddc <HAL_RCC_OscConfig+0x508>)
8001d88: 681b ldr r3, [r3, #0]
8001d8a: f403 7380 and.w r3, r3, #256 ; 0x100
8001d8e: 2b00 cmp r3, #0
8001d90: d0f0 beq.n 8001d74 <HAL_RCC_OscConfig+0x4a0>
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
#else
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001d92: 687b ldr r3, [r7, #4]
8001d94: 689b ldr r3, [r3, #8]
8001d96: 2b01 cmp r3, #1
8001d98: d108 bne.n 8001dac <HAL_RCC_OscConfig+0x4d8>
8001d9a: 4b0f ldr r3, [pc, #60] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001d9c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001da0: 4a0d ldr r2, [pc, #52] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001da2: f043 0301 orr.w r3, r3, #1
8001da6: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8001daa: e029 b.n 8001e00 <HAL_RCC_OscConfig+0x52c>
8001dac: 687b ldr r3, [r7, #4]
8001dae: 689b ldr r3, [r3, #8]
8001db0: 2b05 cmp r3, #5
8001db2: d115 bne.n 8001de0 <HAL_RCC_OscConfig+0x50c>
8001db4: 4b08 ldr r3, [pc, #32] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001db6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001dba: 4a07 ldr r2, [pc, #28] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001dbc: f043 0304 orr.w r3, r3, #4
8001dc0: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8001dc4: 4b04 ldr r3, [pc, #16] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001dc6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001dca: 4a03 ldr r2, [pc, #12] ; (8001dd8 <HAL_RCC_OscConfig+0x504>)
8001dcc: f043 0301 orr.w r3, r3, #1
8001dd0: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8001dd4: e014 b.n 8001e00 <HAL_RCC_OscConfig+0x52c>
8001dd6: bf00 nop
8001dd8: 40021000 .word 0x40021000
8001ddc: 40007000 .word 0x40007000
8001de0: 4b9a ldr r3, [pc, #616] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001de2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001de6: 4a99 ldr r2, [pc, #612] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001de8: f023 0301 bic.w r3, r3, #1
8001dec: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8001df0: 4b96 ldr r3, [pc, #600] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001df2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001df6: 4a95 ldr r2, [pc, #596] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001df8: f023 0304 bic.w r3, r3, #4
8001dfc: f8c2 3090 str.w r3, [r2, #144] ; 0x90
#endif /* RCC_BDCR_LSESYSDIS */
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001e00: 687b ldr r3, [r7, #4]
8001e02: 689b ldr r3, [r3, #8]
8001e04: 2b00 cmp r3, #0
8001e06: d016 beq.n 8001e36 <HAL_RCC_OscConfig+0x562>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e08: f7ff f9ae bl 8001168 <HAL_GetTick>
8001e0c: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001e0e: e00a b.n 8001e26 <HAL_RCC_OscConfig+0x552>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001e10: f7ff f9aa bl 8001168 <HAL_GetTick>
8001e14: 4602 mov r2, r0
8001e16: 693b ldr r3, [r7, #16]
8001e18: 1ad3 subs r3, r2, r3
8001e1a: f241 3288 movw r2, #5000 ; 0x1388
8001e1e: 4293 cmp r3, r2
8001e20: d901 bls.n 8001e26 <HAL_RCC_OscConfig+0x552>
{
return HAL_TIMEOUT;
8001e22: 2303 movs r3, #3
8001e24: e162 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001e26: 4b89 ldr r3, [pc, #548] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001e28: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001e2c: f003 0302 and.w r3, r3, #2
8001e30: 2b00 cmp r3, #0
8001e32: d0ed beq.n 8001e10 <HAL_RCC_OscConfig+0x53c>
8001e34: e015 b.n 8001e62 <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e36: f7ff f997 bl 8001168 <HAL_GetTick>
8001e3a: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8001e3c: e00a b.n 8001e54 <HAL_RCC_OscConfig+0x580>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001e3e: f7ff f993 bl 8001168 <HAL_GetTick>
8001e42: 4602 mov r2, r0
8001e44: 693b ldr r3, [r7, #16]
8001e46: 1ad3 subs r3, r2, r3
8001e48: f241 3288 movw r2, #5000 ; 0x1388
8001e4c: 4293 cmp r3, r2
8001e4e: d901 bls.n 8001e54 <HAL_RCC_OscConfig+0x580>
{
return HAL_TIMEOUT;
8001e50: 2303 movs r3, #3
8001e52: e14b b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8001e54: 4b7d ldr r3, [pc, #500] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001e56: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001e5a: f003 0302 and.w r3, r3, #2
8001e5e: 2b00 cmp r3, #0
8001e60: d1ed bne.n 8001e3e <HAL_RCC_OscConfig+0x56a>
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001e62: 7ffb ldrb r3, [r7, #31]
8001e64: 2b01 cmp r3, #1
8001e66: d105 bne.n 8001e74 <HAL_RCC_OscConfig+0x5a0>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001e68: 4b78 ldr r3, [pc, #480] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001e6a: 6d9b ldr r3, [r3, #88] ; 0x58
8001e6c: 4a77 ldr r2, [pc, #476] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001e6e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001e72: 6593 str r3, [r2, #88] ; 0x58
}
}
#if defined(RCC_HSI48_SUPPORT)
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8001e74: 687b ldr r3, [r7, #4]
8001e76: 681b ldr r3, [r3, #0]
8001e78: f003 0320 and.w r3, r3, #32
8001e7c: 2b00 cmp r3, #0
8001e7e: d03c beq.n 8001efa <HAL_RCC_OscConfig+0x626>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the LSI State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8001e80: 687b ldr r3, [r7, #4]
8001e82: 6a5b ldr r3, [r3, #36] ; 0x24
8001e84: 2b00 cmp r3, #0
8001e86: d01c beq.n 8001ec2 <HAL_RCC_OscConfig+0x5ee>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8001e88: 4b70 ldr r3, [pc, #448] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001e8a: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8001e8e: 4a6f ldr r2, [pc, #444] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001e90: f043 0301 orr.w r3, r3, #1
8001e94: f8c2 3098 str.w r3, [r2, #152] ; 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e98: f7ff f966 bl 8001168 <HAL_GetTick>
8001e9c: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8001e9e: e008 b.n 8001eb2 <HAL_RCC_OscConfig+0x5de>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8001ea0: f7ff f962 bl 8001168 <HAL_GetTick>
8001ea4: 4602 mov r2, r0
8001ea6: 693b ldr r3, [r7, #16]
8001ea8: 1ad3 subs r3, r2, r3
8001eaa: 2b02 cmp r3, #2
8001eac: d901 bls.n 8001eb2 <HAL_RCC_OscConfig+0x5de>
{
return HAL_TIMEOUT;
8001eae: 2303 movs r3, #3
8001eb0: e11c b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8001eb2: 4b66 ldr r3, [pc, #408] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001eb4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8001eb8: f003 0302 and.w r3, r3, #2
8001ebc: 2b00 cmp r3, #0
8001ebe: d0ef beq.n 8001ea0 <HAL_RCC_OscConfig+0x5cc>
8001ec0: e01b b.n 8001efa <HAL_RCC_OscConfig+0x626>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
8001ec2: 4b62 ldr r3, [pc, #392] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001ec4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8001ec8: 4a60 ldr r2, [pc, #384] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001eca: f023 0301 bic.w r3, r3, #1
8001ece: f8c2 3098 str.w r3, [r2, #152] ; 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ed2: f7ff f949 bl 8001168 <HAL_GetTick>
8001ed6: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8001ed8: e008 b.n 8001eec <HAL_RCC_OscConfig+0x618>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8001eda: f7ff f945 bl 8001168 <HAL_GetTick>
8001ede: 4602 mov r2, r0
8001ee0: 693b ldr r3, [r7, #16]
8001ee2: 1ad3 subs r3, r2, r3
8001ee4: 2b02 cmp r3, #2
8001ee6: d901 bls.n 8001eec <HAL_RCC_OscConfig+0x618>
{
return HAL_TIMEOUT;
8001ee8: 2303 movs r3, #3
8001eea: e0ff b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8001eec: 4b57 ldr r3, [pc, #348] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001eee: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8001ef2: f003 0302 and.w r3, r3, #2
8001ef6: 2b00 cmp r3, #0
8001ef8: d1ef bne.n 8001eda <HAL_RCC_OscConfig+0x606>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8001efa: 687b ldr r3, [r7, #4]
8001efc: 6a9b ldr r3, [r3, #40] ; 0x28
8001efe: 2b00 cmp r3, #0
8001f00: f000 80f3 beq.w 80020ea <HAL_RCC_OscConfig+0x816>
{
/* PLL On ? */
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8001f04: 687b ldr r3, [r7, #4]
8001f06: 6a9b ldr r3, [r3, #40] ; 0x28
8001f08: 2b02 cmp r3, #2
8001f0a: f040 80c9 bne.w 80020a0 <HAL_RCC_OscConfig+0x7cc>
#endif /* RCC_PLLP_SUPPORT */
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is the unchanged */
pll_config = RCC->PLLCFGR;
8001f0e: 4b4f ldr r3, [pc, #316] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001f10: 68db ldr r3, [r3, #12]
8001f12: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001f14: 697b ldr r3, [r7, #20]
8001f16: f003 0203 and.w r2, r3, #3
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 6adb ldr r3, [r3, #44] ; 0x2c
8001f1e: 429a cmp r2, r3
8001f20: d12c bne.n 8001f7c <HAL_RCC_OscConfig+0x6a8>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8001f22: 697b ldr r3, [r7, #20]
8001f24: f003 0270 and.w r2, r3, #112 ; 0x70
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 6b1b ldr r3, [r3, #48] ; 0x30
8001f2c: 3b01 subs r3, #1
8001f2e: 011b lsls r3, r3, #4
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001f30: 429a cmp r2, r3
8001f32: d123 bne.n 8001f7c <HAL_RCC_OscConfig+0x6a8>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001f34: 697b ldr r3, [r7, #20]
8001f36: f403 42fe and.w r2, r3, #32512 ; 0x7f00
8001f3a: 687b ldr r3, [r7, #4]
8001f3c: 6b5b ldr r3, [r3, #52] ; 0x34
8001f3e: 021b lsls r3, r3, #8
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8001f40: 429a cmp r2, r3
8001f42: d11b bne.n 8001f7c <HAL_RCC_OscConfig+0x6a8>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8001f44: 697b ldr r3, [r7, #20]
8001f46: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000
8001f4a: 687b ldr r3, [r7, #4]
8001f4c: 6b9b ldr r3, [r3, #56] ; 0x38
8001f4e: 06db lsls r3, r3, #27
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001f50: 429a cmp r2, r3
8001f52: d113 bne.n 8001f7c <HAL_RCC_OscConfig+0x6a8>
#else
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
#endif
#endif
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8001f54: 697b ldr r3, [r7, #20]
8001f56: f403 02c0 and.w r2, r3, #6291456 ; 0x600000
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 6bdb ldr r3, [r3, #60] ; 0x3c
8001f5e: 085b lsrs r3, r3, #1
8001f60: 3b01 subs r3, #1
8001f62: 055b lsls r3, r3, #21
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8001f64: 429a cmp r2, r3
8001f66: d109 bne.n 8001f7c <HAL_RCC_OscConfig+0x6a8>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8001f68: 697b ldr r3, [r7, #20]
8001f6a: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000
8001f6e: 687b ldr r3, [r7, #4]
8001f70: 6c1b ldr r3, [r3, #64] ; 0x40
8001f72: 085b lsrs r3, r3, #1
8001f74: 3b01 subs r3, #1
8001f76: 065b lsls r3, r3, #25
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8001f78: 429a cmp r2, r3
8001f7a: d06b beq.n 8002054 <HAL_RCC_OscConfig+0x780>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
8001f7c: 69bb ldr r3, [r7, #24]
8001f7e: 2b0c cmp r3, #12
8001f80: d062 beq.n 8002048 <HAL_RCC_OscConfig+0x774>
{
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
8001f82: 4b32 ldr r3, [pc, #200] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001f84: 681b ldr r3, [r3, #0]
8001f86: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8001f8a: 2b00 cmp r3, #0
8001f8c: d001 beq.n 8001f92 <HAL_RCC_OscConfig+0x6be>
#if defined(RCC_PLLSAI2_SUPPORT)
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
#endif
)
{
return HAL_ERROR;
8001f8e: 2301 movs r3, #1
8001f90: e0ac b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001f92: 4b2e ldr r3, [pc, #184] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001f94: 681b ldr r3, [r3, #0]
8001f96: 4a2d ldr r2, [pc, #180] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001f98: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8001f9c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f9e: f7ff f8e3 bl 8001168 <HAL_GetTick>
8001fa2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001fa4: e008 b.n 8001fb8 <HAL_RCC_OscConfig+0x6e4>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001fa6: f7ff f8df bl 8001168 <HAL_GetTick>
8001faa: 4602 mov r2, r0
8001fac: 693b ldr r3, [r7, #16]
8001fae: 1ad3 subs r3, r2, r3
8001fb0: 2b02 cmp r3, #2
8001fb2: d901 bls.n 8001fb8 <HAL_RCC_OscConfig+0x6e4>
{
return HAL_TIMEOUT;
8001fb4: 2303 movs r3, #3
8001fb6: e099 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001fb8: 4b24 ldr r3, [pc, #144] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001fba: 681b ldr r3, [r3, #0]
8001fbc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001fc0: 2b00 cmp r3, #0
8001fc2: d1f0 bne.n 8001fa6 <HAL_RCC_OscConfig+0x6d2>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001fc4: 4b21 ldr r3, [pc, #132] ; (800204c <HAL_RCC_OscConfig+0x778>)
8001fc6: 68da ldr r2, [r3, #12]
8001fc8: 4b21 ldr r3, [pc, #132] ; (8002050 <HAL_RCC_OscConfig+0x77c>)
8001fca: 4013 ands r3, r2
8001fcc: 687a ldr r2, [r7, #4]
8001fce: 6ad1 ldr r1, [r2, #44] ; 0x2c
8001fd0: 687a ldr r2, [r7, #4]
8001fd2: 6b12 ldr r2, [r2, #48] ; 0x30
8001fd4: 3a01 subs r2, #1
8001fd6: 0112 lsls r2, r2, #4
8001fd8: 4311 orrs r1, r2
8001fda: 687a ldr r2, [r7, #4]
8001fdc: 6b52 ldr r2, [r2, #52] ; 0x34
8001fde: 0212 lsls r2, r2, #8
8001fe0: 4311 orrs r1, r2
8001fe2: 687a ldr r2, [r7, #4]
8001fe4: 6bd2 ldr r2, [r2, #60] ; 0x3c
8001fe6: 0852 lsrs r2, r2, #1
8001fe8: 3a01 subs r2, #1
8001fea: 0552 lsls r2, r2, #21
8001fec: 4311 orrs r1, r2
8001fee: 687a ldr r2, [r7, #4]
8001ff0: 6c12 ldr r2, [r2, #64] ; 0x40
8001ff2: 0852 lsrs r2, r2, #1
8001ff4: 3a01 subs r2, #1
8001ff6: 0652 lsls r2, r2, #25
8001ff8: 4311 orrs r1, r2
8001ffa: 687a ldr r2, [r7, #4]
8001ffc: 6b92 ldr r2, [r2, #56] ; 0x38
8001ffe: 06d2 lsls r2, r2, #27
8002000: 430a orrs r2, r1
8002002: 4912 ldr r1, [pc, #72] ; (800204c <HAL_RCC_OscConfig+0x778>)
8002004: 4313 orrs r3, r2
8002006: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002008: 4b10 ldr r3, [pc, #64] ; (800204c <HAL_RCC_OscConfig+0x778>)
800200a: 681b ldr r3, [r3, #0]
800200c: 4a0f ldr r2, [pc, #60] ; (800204c <HAL_RCC_OscConfig+0x778>)
800200e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8002012: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8002014: 4b0d ldr r3, [pc, #52] ; (800204c <HAL_RCC_OscConfig+0x778>)
8002016: 68db ldr r3, [r3, #12]
8002018: 4a0c ldr r2, [pc, #48] ; (800204c <HAL_RCC_OscConfig+0x778>)
800201a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800201e: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002020: f7ff f8a2 bl 8001168 <HAL_GetTick>
8002024: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002026: e008 b.n 800203a <HAL_RCC_OscConfig+0x766>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002028: f7ff f89e bl 8001168 <HAL_GetTick>
800202c: 4602 mov r2, r0
800202e: 693b ldr r3, [r7, #16]
8002030: 1ad3 subs r3, r2, r3
8002032: 2b02 cmp r3, #2
8002034: d901 bls.n 800203a <HAL_RCC_OscConfig+0x766>
{
return HAL_TIMEOUT;
8002036: 2303 movs r3, #3
8002038: e058 b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800203a: 4b04 ldr r3, [pc, #16] ; (800204c <HAL_RCC_OscConfig+0x778>)
800203c: 681b ldr r3, [r3, #0]
800203e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002042: 2b00 cmp r3, #0
8002044: d0f0 beq.n 8002028 <HAL_RCC_OscConfig+0x754>
if(sysclk_source != RCC_CFGR_SWS_PLL)
8002046: e050 b.n 80020ea <HAL_RCC_OscConfig+0x816>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8002048: 2301 movs r3, #1
800204a: e04f b.n 80020ec <HAL_RCC_OscConfig+0x818>
800204c: 40021000 .word 0x40021000
8002050: 019d808c .word 0x019d808c
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002054: 4b27 ldr r3, [pc, #156] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
8002056: 681b ldr r3, [r3, #0]
8002058: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800205c: 2b00 cmp r3, #0
800205e: d144 bne.n 80020ea <HAL_RCC_OscConfig+0x816>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002060: 4b24 ldr r3, [pc, #144] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
8002062: 681b ldr r3, [r3, #0]
8002064: 4a23 ldr r2, [pc, #140] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
8002066: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800206a: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
800206c: 4b21 ldr r3, [pc, #132] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
800206e: 68db ldr r3, [r3, #12]
8002070: 4a20 ldr r2, [pc, #128] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
8002072: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8002076: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002078: f7ff f876 bl 8001168 <HAL_GetTick>
800207c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800207e: e008 b.n 8002092 <HAL_RCC_OscConfig+0x7be>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002080: f7ff f872 bl 8001168 <HAL_GetTick>
8002084: 4602 mov r2, r0
8002086: 693b ldr r3, [r7, #16]
8002088: 1ad3 subs r3, r2, r3
800208a: 2b02 cmp r3, #2
800208c: d901 bls.n 8002092 <HAL_RCC_OscConfig+0x7be>
{
return HAL_TIMEOUT;
800208e: 2303 movs r3, #3
8002090: e02c b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002092: 4b18 ldr r3, [pc, #96] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
8002094: 681b ldr r3, [r3, #0]
8002096: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800209a: 2b00 cmp r3, #0
800209c: d0f0 beq.n 8002080 <HAL_RCC_OscConfig+0x7ac>
800209e: e024 b.n 80020ea <HAL_RCC_OscConfig+0x816>
}
}
else
{
/* Check that PLL is not used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
80020a0: 69bb ldr r3, [r7, #24]
80020a2: 2b0c cmp r3, #12
80020a4: d01f beq.n 80020e6 <HAL_RCC_OscConfig+0x812>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80020a6: 4b13 ldr r3, [pc, #76] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
80020a8: 681b ldr r3, [r3, #0]
80020aa: 4a12 ldr r2, [pc, #72] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
80020ac: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80020b0: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80020b2: f7ff f859 bl 8001168 <HAL_GetTick>
80020b6: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80020b8: e008 b.n 80020cc <HAL_RCC_OscConfig+0x7f8>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80020ba: f7ff f855 bl 8001168 <HAL_GetTick>
80020be: 4602 mov r2, r0
80020c0: 693b ldr r3, [r7, #16]
80020c2: 1ad3 subs r3, r2, r3
80020c4: 2b02 cmp r3, #2
80020c6: d901 bls.n 80020cc <HAL_RCC_OscConfig+0x7f8>
{
return HAL_TIMEOUT;
80020c8: 2303 movs r3, #3
80020ca: e00f b.n 80020ec <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80020cc: 4b09 ldr r3, [pc, #36] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
80020ce: 681b ldr r3, [r3, #0]
80020d0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80020d4: 2b00 cmp r3, #0
80020d6: d1f0 bne.n 80020ba <HAL_RCC_OscConfig+0x7e6>
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
#elif defined(RCC_PLLSAI1_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
80020d8: 4b06 ldr r3, [pc, #24] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
80020da: 68da ldr r2, [r3, #12]
80020dc: 4905 ldr r1, [pc, #20] ; (80020f4 <HAL_RCC_OscConfig+0x820>)
80020de: 4b06 ldr r3, [pc, #24] ; (80020f8 <HAL_RCC_OscConfig+0x824>)
80020e0: 4013 ands r3, r2
80020e2: 60cb str r3, [r1, #12]
80020e4: e001 b.n 80020ea <HAL_RCC_OscConfig+0x816>
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
80020e6: 2301 movs r3, #1
80020e8: e000 b.n 80020ec <HAL_RCC_OscConfig+0x818>
}
}
}
return HAL_OK;
80020ea: 2300 movs r3, #0
}
80020ec: 4618 mov r0, r3
80020ee: 3720 adds r7, #32
80020f0: 46bd mov sp, r7
80020f2: bd80 pop {r7, pc}
80020f4: 40021000 .word 0x40021000
80020f8: feeefffc .word 0xfeeefffc
080020fc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80020fc: b580 push {r7, lr}
80020fe: b084 sub sp, #16
8002100: af00 add r7, sp, #0
8002102: 6078 str r0, [r7, #4]
8002104: 6039 str r1, [r7, #0]
uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002106: 687b ldr r3, [r7, #4]
8002108: 2b00 cmp r3, #0
800210a: d101 bne.n 8002110 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
800210c: 2301 movs r3, #1
800210e: e0e7 b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002110: 4b75 ldr r3, [pc, #468] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002112: 681b ldr r3, [r3, #0]
8002114: f003 0307 and.w r3, r3, #7
8002118: 683a ldr r2, [r7, #0]
800211a: 429a cmp r2, r3
800211c: d910 bls.n 8002140 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800211e: 4b72 ldr r3, [pc, #456] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002120: 681b ldr r3, [r3, #0]
8002122: f023 0207 bic.w r2, r3, #7
8002126: 4970 ldr r1, [pc, #448] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002128: 683b ldr r3, [r7, #0]
800212a: 4313 orrs r3, r2
800212c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800212e: 4b6e ldr r3, [pc, #440] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002130: 681b ldr r3, [r3, #0]
8002132: f003 0307 and.w r3, r3, #7
8002136: 683a ldr r2, [r7, #0]
8002138: 429a cmp r2, r3
800213a: d001 beq.n 8002140 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
800213c: 2301 movs r3, #1
800213e: e0cf b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002140: 687b ldr r3, [r7, #4]
8002142: 681b ldr r3, [r3, #0]
8002144: f003 0302 and.w r3, r3, #2
8002148: 2b00 cmp r3, #0
800214a: d010 beq.n 800216e <HAL_RCC_ClockConfig+0x72>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
800214c: 687b ldr r3, [r7, #4]
800214e: 689a ldr r2, [r3, #8]
8002150: 4b66 ldr r3, [pc, #408] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
8002152: 689b ldr r3, [r3, #8]
8002154: f003 03f0 and.w r3, r3, #240 ; 0xf0
8002158: 429a cmp r2, r3
800215a: d908 bls.n 800216e <HAL_RCC_ClockConfig+0x72>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800215c: 4b63 ldr r3, [pc, #396] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
800215e: 689b ldr r3, [r3, #8]
8002160: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8002164: 687b ldr r3, [r7, #4]
8002166: 689b ldr r3, [r3, #8]
8002168: 4960 ldr r1, [pc, #384] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
800216a: 4313 orrs r3, r2
800216c: 608b str r3, [r1, #8]
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800216e: 687b ldr r3, [r7, #4]
8002170: 681b ldr r3, [r3, #0]
8002172: f003 0301 and.w r3, r3, #1
8002176: 2b00 cmp r3, #0
8002178: d04c beq.n 8002214 <HAL_RCC_ClockConfig+0x118>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800217a: 687b ldr r3, [r7, #4]
800217c: 685b ldr r3, [r3, #4]
800217e: 2b03 cmp r3, #3
8002180: d107 bne.n 8002192 <HAL_RCC_ClockConfig+0x96>
{
/* Check the PLL ready flag */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002182: 4b5a ldr r3, [pc, #360] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
8002184: 681b ldr r3, [r3, #0]
8002186: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800218a: 2b00 cmp r3, #0
800218c: d121 bne.n 80021d2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800218e: 2301 movs r3, #1
8002190: e0a6 b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
#endif
}
else
{
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002192: 687b ldr r3, [r7, #4]
8002194: 685b ldr r3, [r3, #4]
8002196: 2b02 cmp r3, #2
8002198: d107 bne.n 80021aa <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800219a: 4b54 ldr r3, [pc, #336] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
800219c: 681b ldr r3, [r3, #0]
800219e: f403 3300 and.w r3, r3, #131072 ; 0x20000
80021a2: 2b00 cmp r3, #0
80021a4: d115 bne.n 80021d2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80021a6: 2301 movs r3, #1
80021a8: e09a b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
}
}
/* MSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
80021aa: 687b ldr r3, [r7, #4]
80021ac: 685b ldr r3, [r3, #4]
80021ae: 2b00 cmp r3, #0
80021b0: d107 bne.n 80021c2 <HAL_RCC_ClockConfig+0xc6>
{
/* Check the MSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
80021b2: 4b4e ldr r3, [pc, #312] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
80021b4: 681b ldr r3, [r3, #0]
80021b6: f003 0302 and.w r3, r3, #2
80021ba: 2b00 cmp r3, #0
80021bc: d109 bne.n 80021d2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80021be: 2301 movs r3, #1
80021c0: e08e b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80021c2: 4b4a ldr r3, [pc, #296] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
80021c4: 681b ldr r3, [r3, #0]
80021c6: f403 6380 and.w r3, r3, #1024 ; 0x400
80021ca: 2b00 cmp r3, #0
80021cc: d101 bne.n 80021d2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80021ce: 2301 movs r3, #1
80021d0: e086 b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
}
#endif
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80021d2: 4b46 ldr r3, [pc, #280] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
80021d4: 689b ldr r3, [r3, #8]
80021d6: f023 0203 bic.w r2, r3, #3
80021da: 687b ldr r3, [r7, #4]
80021dc: 685b ldr r3, [r3, #4]
80021de: 4943 ldr r1, [pc, #268] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
80021e0: 4313 orrs r3, r2
80021e2: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80021e4: f7fe ffc0 bl 8001168 <HAL_GetTick>
80021e8: 60f8 str r0, [r7, #12]
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80021ea: e00a b.n 8002202 <HAL_RCC_ClockConfig+0x106>
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80021ec: f7fe ffbc bl 8001168 <HAL_GetTick>
80021f0: 4602 mov r2, r0
80021f2: 68fb ldr r3, [r7, #12]
80021f4: 1ad3 subs r3, r2, r3
80021f6: f241 3288 movw r2, #5000 ; 0x1388
80021fa: 4293 cmp r3, r2
80021fc: d901 bls.n 8002202 <HAL_RCC_ClockConfig+0x106>
{
return HAL_TIMEOUT;
80021fe: 2303 movs r3, #3
8002200: e06e b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002202: 4b3a ldr r3, [pc, #232] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
8002204: 689b ldr r3, [r3, #8]
8002206: f003 020c and.w r2, r3, #12
800220a: 687b ldr r3, [r7, #4]
800220c: 685b ldr r3, [r3, #4]
800220e: 009b lsls r3, r3, #2
8002210: 429a cmp r2, r3
8002212: d1eb bne.n 80021ec <HAL_RCC_ClockConfig+0xf0>
}
#endif
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002214: 687b ldr r3, [r7, #4]
8002216: 681b ldr r3, [r3, #0]
8002218: f003 0302 and.w r3, r3, #2
800221c: 2b00 cmp r3, #0
800221e: d010 beq.n 8002242 <HAL_RCC_ClockConfig+0x146>
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
8002220: 687b ldr r3, [r7, #4]
8002222: 689a ldr r2, [r3, #8]
8002224: 4b31 ldr r3, [pc, #196] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
8002226: 689b ldr r3, [r3, #8]
8002228: f003 03f0 and.w r3, r3, #240 ; 0xf0
800222c: 429a cmp r2, r3
800222e: d208 bcs.n 8002242 <HAL_RCC_ClockConfig+0x146>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002230: 4b2e ldr r3, [pc, #184] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
8002232: 689b ldr r3, [r3, #8]
8002234: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8002238: 687b ldr r3, [r7, #4]
800223a: 689b ldr r3, [r3, #8]
800223c: 492b ldr r1, [pc, #172] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
800223e: 4313 orrs r3, r2
8002240: 608b str r3, [r1, #8]
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002242: 4b29 ldr r3, [pc, #164] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002244: 681b ldr r3, [r3, #0]
8002246: f003 0307 and.w r3, r3, #7
800224a: 683a ldr r2, [r7, #0]
800224c: 429a cmp r2, r3
800224e: d210 bcs.n 8002272 <HAL_RCC_ClockConfig+0x176>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002250: 4b25 ldr r3, [pc, #148] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002252: 681b ldr r3, [r3, #0]
8002254: f023 0207 bic.w r2, r3, #7
8002258: 4923 ldr r1, [pc, #140] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
800225a: 683b ldr r3, [r7, #0]
800225c: 4313 orrs r3, r2
800225e: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002260: 4b21 ldr r3, [pc, #132] ; (80022e8 <HAL_RCC_ClockConfig+0x1ec>)
8002262: 681b ldr r3, [r3, #0]
8002264: f003 0307 and.w r3, r3, #7
8002268: 683a ldr r2, [r7, #0]
800226a: 429a cmp r2, r3
800226c: d001 beq.n 8002272 <HAL_RCC_ClockConfig+0x176>
{
return HAL_ERROR;
800226e: 2301 movs r3, #1
8002270: e036 b.n 80022e0 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002272: 687b ldr r3, [r7, #4]
8002274: 681b ldr r3, [r3, #0]
8002276: f003 0304 and.w r3, r3, #4
800227a: 2b00 cmp r3, #0
800227c: d008 beq.n 8002290 <HAL_RCC_ClockConfig+0x194>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
800227e: 4b1b ldr r3, [pc, #108] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
8002280: 689b ldr r3, [r3, #8]
8002282: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8002286: 687b ldr r3, [r7, #4]
8002288: 68db ldr r3, [r3, #12]
800228a: 4918 ldr r1, [pc, #96] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
800228c: 4313 orrs r3, r2
800228e: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002290: 687b ldr r3, [r7, #4]
8002292: 681b ldr r3, [r3, #0]
8002294: f003 0308 and.w r3, r3, #8
8002298: 2b00 cmp r3, #0
800229a: d009 beq.n 80022b0 <HAL_RCC_ClockConfig+0x1b4>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
800229c: 4b13 ldr r3, [pc, #76] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
800229e: 689b ldr r3, [r3, #8]
80022a0: f423 5260 bic.w r2, r3, #14336 ; 0x3800
80022a4: 687b ldr r3, [r7, #4]
80022a6: 691b ldr r3, [r3, #16]
80022a8: 00db lsls r3, r3, #3
80022aa: 4910 ldr r1, [pc, #64] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
80022ac: 4313 orrs r3, r2
80022ae: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
80022b0: f000 f824 bl 80022fc <HAL_RCC_GetSysClockFreq>
80022b4: 4602 mov r2, r0
80022b6: 4b0d ldr r3, [pc, #52] ; (80022ec <HAL_RCC_ClockConfig+0x1f0>)
80022b8: 689b ldr r3, [r3, #8]
80022ba: 091b lsrs r3, r3, #4
80022bc: f003 030f and.w r3, r3, #15
80022c0: 490b ldr r1, [pc, #44] ; (80022f0 <HAL_RCC_ClockConfig+0x1f4>)
80022c2: 5ccb ldrb r3, [r1, r3]
80022c4: f003 031f and.w r3, r3, #31
80022c8: fa22 f303 lsr.w r3, r2, r3
80022cc: 4a09 ldr r2, [pc, #36] ; (80022f4 <HAL_RCC_ClockConfig+0x1f8>)
80022ce: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80022d0: 4b09 ldr r3, [pc, #36] ; (80022f8 <HAL_RCC_ClockConfig+0x1fc>)
80022d2: 681b ldr r3, [r3, #0]
80022d4: 4618 mov r0, r3
80022d6: f7fe fef7 bl 80010c8 <HAL_InitTick>
80022da: 4603 mov r3, r0
80022dc: 72fb strb r3, [r7, #11]
return status;
80022de: 7afb ldrb r3, [r7, #11]
}
80022e0: 4618 mov r0, r3
80022e2: 3710 adds r7, #16
80022e4: 46bd mov sp, r7
80022e6: bd80 pop {r7, pc}
80022e8: 40022000 .word 0x40022000
80022ec: 40021000 .word 0x40021000
80022f0: 08005f18 .word 0x08005f18
80022f4: 20000004 .word 0x20000004
80022f8: 20000008 .word 0x20000008
080022fc <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80022fc: b480 push {r7}
80022fe: b089 sub sp, #36 ; 0x24
8002300: af00 add r7, sp, #0
uint32_t msirange = 0U, sysclockfreq = 0U;
8002302: 2300 movs r3, #0
8002304: 61fb str r3, [r7, #28]
8002306: 2300 movs r3, #0
8002308: 61bb str r3, [r7, #24]
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
uint32_t sysclk_source, pll_oscsource;
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
800230a: 4b3e ldr r3, [pc, #248] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
800230c: 689b ldr r3, [r3, #8]
800230e: f003 030c and.w r3, r3, #12
8002312: 613b str r3, [r7, #16]
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
8002314: 4b3b ldr r3, [pc, #236] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
8002316: 68db ldr r3, [r3, #12]
8002318: f003 0303 and.w r3, r3, #3
800231c: 60fb str r3, [r7, #12]
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
800231e: 693b ldr r3, [r7, #16]
8002320: 2b00 cmp r3, #0
8002322: d005 beq.n 8002330 <HAL_RCC_GetSysClockFreq+0x34>
8002324: 693b ldr r3, [r7, #16]
8002326: 2b0c cmp r3, #12
8002328: d121 bne.n 800236e <HAL_RCC_GetSysClockFreq+0x72>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
800232a: 68fb ldr r3, [r7, #12]
800232c: 2b01 cmp r3, #1
800232e: d11e bne.n 800236e <HAL_RCC_GetSysClockFreq+0x72>
{
/* MSI or PLL with MSI source used as system clock source */
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
8002330: 4b34 ldr r3, [pc, #208] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
8002332: 681b ldr r3, [r3, #0]
8002334: f003 0308 and.w r3, r3, #8
8002338: 2b00 cmp r3, #0
800233a: d107 bne.n 800234c <HAL_RCC_GetSysClockFreq+0x50>
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
800233c: 4b31 ldr r3, [pc, #196] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
800233e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8002342: 0a1b lsrs r3, r3, #8
8002344: f003 030f and.w r3, r3, #15
8002348: 61fb str r3, [r7, #28]
800234a: e005 b.n 8002358 <HAL_RCC_GetSysClockFreq+0x5c>
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
800234c: 4b2d ldr r3, [pc, #180] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
800234e: 681b ldr r3, [r3, #0]
8002350: 091b lsrs r3, r3, #4
8002352: f003 030f and.w r3, r3, #15
8002356: 61fb str r3, [r7, #28]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
8002358: 4a2b ldr r2, [pc, #172] ; (8002408 <HAL_RCC_GetSysClockFreq+0x10c>)
800235a: 69fb ldr r3, [r7, #28]
800235c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8002360: 61fb str r3, [r7, #28]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8002362: 693b ldr r3, [r7, #16]
8002364: 2b00 cmp r3, #0
8002366: d10d bne.n 8002384 <HAL_RCC_GetSysClockFreq+0x88>
{
/* MSI used as system clock source */
sysclockfreq = msirange;
8002368: 69fb ldr r3, [r7, #28]
800236a: 61bb str r3, [r7, #24]
if(sysclk_source == RCC_CFGR_SWS_MSI)
800236c: e00a b.n 8002384 <HAL_RCC_GetSysClockFreq+0x88>
}
}
else if(sysclk_source == RCC_CFGR_SWS_HSI)
800236e: 693b ldr r3, [r7, #16]
8002370: 2b04 cmp r3, #4
8002372: d102 bne.n 800237a <HAL_RCC_GetSysClockFreq+0x7e>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8002374: 4b25 ldr r3, [pc, #148] ; (800240c <HAL_RCC_GetSysClockFreq+0x110>)
8002376: 61bb str r3, [r7, #24]
8002378: e004 b.n 8002384 <HAL_RCC_GetSysClockFreq+0x88>
}
else if(sysclk_source == RCC_CFGR_SWS_HSE)
800237a: 693b ldr r3, [r7, #16]
800237c: 2b08 cmp r3, #8
800237e: d101 bne.n 8002384 <HAL_RCC_GetSysClockFreq+0x88>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8002380: 4b23 ldr r3, [pc, #140] ; (8002410 <HAL_RCC_GetSysClockFreq+0x114>)
8002382: 61bb str r3, [r7, #24]
else
{
/* unexpected case: sysclockfreq at 0 */
}
if(sysclk_source == RCC_CFGR_SWS_PLL)
8002384: 693b ldr r3, [r7, #16]
8002386: 2b0c cmp r3, #12
8002388: d134 bne.n 80023f4 <HAL_RCC_GetSysClockFreq+0xf8>
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
800238a: 4b1e ldr r3, [pc, #120] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
800238c: 68db ldr r3, [r3, #12]
800238e: f003 0303 and.w r3, r3, #3
8002392: 60bb str r3, [r7, #8]
switch (pllsource)
8002394: 68bb ldr r3, [r7, #8]
8002396: 2b02 cmp r3, #2
8002398: d003 beq.n 80023a2 <HAL_RCC_GetSysClockFreq+0xa6>
800239a: 68bb ldr r3, [r7, #8]
800239c: 2b03 cmp r3, #3
800239e: d003 beq.n 80023a8 <HAL_RCC_GetSysClockFreq+0xac>
80023a0: e005 b.n 80023ae <HAL_RCC_GetSysClockFreq+0xb2>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllvco = HSI_VALUE;
80023a2: 4b1a ldr r3, [pc, #104] ; (800240c <HAL_RCC_GetSysClockFreq+0x110>)
80023a4: 617b str r3, [r7, #20]
break;
80023a6: e005 b.n 80023b4 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = HSE_VALUE;
80023a8: 4b19 ldr r3, [pc, #100] ; (8002410 <HAL_RCC_GetSysClockFreq+0x114>)
80023aa: 617b str r3, [r7, #20]
break;
80023ac: e002 b.n 80023b4 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllvco = msirange;
80023ae: 69fb ldr r3, [r7, #28]
80023b0: 617b str r3, [r7, #20]
break;
80023b2: bf00 nop
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
80023b4: 4b13 ldr r3, [pc, #76] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
80023b6: 68db ldr r3, [r3, #12]
80023b8: 091b lsrs r3, r3, #4
80023ba: f003 0307 and.w r3, r3, #7
80023be: 3301 adds r3, #1
80023c0: 607b str r3, [r7, #4]
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
80023c2: 4b10 ldr r3, [pc, #64] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
80023c4: 68db ldr r3, [r3, #12]
80023c6: 0a1b lsrs r3, r3, #8
80023c8: f003 037f and.w r3, r3, #127 ; 0x7f
80023cc: 697a ldr r2, [r7, #20]
80023ce: fb03 f202 mul.w r2, r3, r2
80023d2: 687b ldr r3, [r7, #4]
80023d4: fbb2 f3f3 udiv r3, r2, r3
80023d8: 617b str r3, [r7, #20]
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
80023da: 4b0a ldr r3, [pc, #40] ; (8002404 <HAL_RCC_GetSysClockFreq+0x108>)
80023dc: 68db ldr r3, [r3, #12]
80023de: 0e5b lsrs r3, r3, #25
80023e0: f003 0303 and.w r3, r3, #3
80023e4: 3301 adds r3, #1
80023e6: 005b lsls r3, r3, #1
80023e8: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllr;
80023ea: 697a ldr r2, [r7, #20]
80023ec: 683b ldr r3, [r7, #0]
80023ee: fbb2 f3f3 udiv r3, r2, r3
80023f2: 61bb str r3, [r7, #24]
}
return sysclockfreq;
80023f4: 69bb ldr r3, [r7, #24]
}
80023f6: 4618 mov r0, r3
80023f8: 3724 adds r7, #36 ; 0x24
80023fa: 46bd mov sp, r7
80023fc: f85d 7b04 ldr.w r7, [sp], #4
8002400: 4770 bx lr
8002402: bf00 nop
8002404: 40021000 .word 0x40021000
8002408: 08005f30 .word 0x08005f30
800240c: 00f42400 .word 0x00f42400
8002410: 007a1200 .word 0x007a1200
08002414 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002414: b480 push {r7}
8002416: af00 add r7, sp, #0
return SystemCoreClock;
8002418: 4b03 ldr r3, [pc, #12] ; (8002428 <HAL_RCC_GetHCLKFreq+0x14>)
800241a: 681b ldr r3, [r3, #0]
}
800241c: 4618 mov r0, r3
800241e: 46bd mov sp, r7
8002420: f85d 7b04 ldr.w r7, [sp], #4
8002424: 4770 bx lr
8002426: bf00 nop
8002428: 20000004 .word 0x20000004
0800242c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
800242c: b580 push {r7, lr}
800242e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8002430: f7ff fff0 bl 8002414 <HAL_RCC_GetHCLKFreq>
8002434: 4602 mov r2, r0
8002436: 4b06 ldr r3, [pc, #24] ; (8002450 <HAL_RCC_GetPCLK1Freq+0x24>)
8002438: 689b ldr r3, [r3, #8]
800243a: 0a1b lsrs r3, r3, #8
800243c: f003 0307 and.w r3, r3, #7
8002440: 4904 ldr r1, [pc, #16] ; (8002454 <HAL_RCC_GetPCLK1Freq+0x28>)
8002442: 5ccb ldrb r3, [r1, r3]
8002444: f003 031f and.w r3, r3, #31
8002448: fa22 f303 lsr.w r3, r2, r3
}
800244c: 4618 mov r0, r3
800244e: bd80 pop {r7, pc}
8002450: 40021000 .word 0x40021000
8002454: 08005f28 .word 0x08005f28
08002458 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002458: b580 push {r7, lr}
800245a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
800245c: f7ff ffda bl 8002414 <HAL_RCC_GetHCLKFreq>
8002460: 4602 mov r2, r0
8002462: 4b06 ldr r3, [pc, #24] ; (800247c <HAL_RCC_GetPCLK2Freq+0x24>)
8002464: 689b ldr r3, [r3, #8]
8002466: 0adb lsrs r3, r3, #11
8002468: f003 0307 and.w r3, r3, #7
800246c: 4904 ldr r1, [pc, #16] ; (8002480 <HAL_RCC_GetPCLK2Freq+0x28>)
800246e: 5ccb ldrb r3, [r1, r3]
8002470: f003 031f and.w r3, r3, #31
8002474: fa22 f303 lsr.w r3, r2, r3
}
8002478: 4618 mov r0, r3
800247a: bd80 pop {r7, pc}
800247c: 40021000 .word 0x40021000
8002480: 08005f28 .word 0x08005f28
08002484 <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
8002484: b580 push {r7, lr}
8002486: b086 sub sp, #24
8002488: af00 add r7, sp, #0
800248a: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
800248c: 2300 movs r3, #0
800248e: 613b str r3, [r7, #16]
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8002490: 4b2a ldr r3, [pc, #168] ; (800253c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002492: 6d9b ldr r3, [r3, #88] ; 0x58
8002494: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002498: 2b00 cmp r3, #0
800249a: d003 beq.n 80024a4 <RCC_SetFlashLatencyFromMSIRange+0x20>
{
vos = HAL_PWREx_GetVoltageRange();
800249c: f7ff f9b6 bl 800180c <HAL_PWREx_GetVoltageRange>
80024a0: 6178 str r0, [r7, #20]
80024a2: e014 b.n 80024ce <RCC_SetFlashLatencyFromMSIRange+0x4a>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
80024a4: 4b25 ldr r3, [pc, #148] ; (800253c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024a6: 6d9b ldr r3, [r3, #88] ; 0x58
80024a8: 4a24 ldr r2, [pc, #144] ; (800253c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024aa: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80024ae: 6593 str r3, [r2, #88] ; 0x58
80024b0: 4b22 ldr r3, [pc, #136] ; (800253c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024b2: 6d9b ldr r3, [r3, #88] ; 0x58
80024b4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80024b8: 60fb str r3, [r7, #12]
80024ba: 68fb ldr r3, [r7, #12]
vos = HAL_PWREx_GetVoltageRange();
80024bc: f7ff f9a6 bl 800180c <HAL_PWREx_GetVoltageRange>
80024c0: 6178 str r0, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
80024c2: 4b1e ldr r3, [pc, #120] ; (800253c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024c4: 6d9b ldr r3, [r3, #88] ; 0x58
80024c6: 4a1d ldr r2, [pc, #116] ; (800253c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024c8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80024cc: 6593 str r3, [r2, #88] ; 0x58
}
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
80024ce: 697b ldr r3, [r7, #20]
80024d0: f5b3 7f00 cmp.w r3, #512 ; 0x200
80024d4: d10b bne.n 80024ee <RCC_SetFlashLatencyFromMSIRange+0x6a>
{
if(msirange > RCC_MSIRANGE_8)
80024d6: 687b ldr r3, [r7, #4]
80024d8: 2b80 cmp r3, #128 ; 0x80
80024da: d919 bls.n 8002510 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI > 16Mhz */
if(msirange > RCC_MSIRANGE_10)
80024dc: 687b ldr r3, [r7, #4]
80024de: 2ba0 cmp r3, #160 ; 0xa0
80024e0: d902 bls.n 80024e8 <RCC_SetFlashLatencyFromMSIRange+0x64>
{
/* MSI 48Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
80024e2: 2302 movs r3, #2
80024e4: 613b str r3, [r7, #16]
80024e6: e013 b.n 8002510 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
/* MSI 24Mhz or 32Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
80024e8: 2301 movs r3, #1
80024ea: 613b str r3, [r7, #16]
80024ec: e010 b.n 8002510 <RCC_SetFlashLatencyFromMSIRange+0x8c>
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#else
if(msirange > RCC_MSIRANGE_8)
80024ee: 687b ldr r3, [r7, #4]
80024f0: 2b80 cmp r3, #128 ; 0x80
80024f2: d902 bls.n 80024fa <RCC_SetFlashLatencyFromMSIRange+0x76>
{
/* MSI > 16Mhz */
latency = FLASH_LATENCY_3; /* 3WS */
80024f4: 2303 movs r3, #3
80024f6: 613b str r3, [r7, #16]
80024f8: e00a b.n 8002510 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
if(msirange == RCC_MSIRANGE_8)
80024fa: 687b ldr r3, [r7, #4]
80024fc: 2b80 cmp r3, #128 ; 0x80
80024fe: d102 bne.n 8002506 <RCC_SetFlashLatencyFromMSIRange+0x82>
{
/* MSI 16Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8002500: 2302 movs r3, #2
8002502: 613b str r3, [r7, #16]
8002504: e004 b.n 8002510 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else if(msirange == RCC_MSIRANGE_7)
8002506: 687b ldr r3, [r7, #4]
8002508: 2b70 cmp r3, #112 ; 0x70
800250a: d101 bne.n 8002510 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
800250c: 2301 movs r3, #1
800250e: 613b str r3, [r7, #16]
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#endif
}
__HAL_FLASH_SET_LATENCY(latency);
8002510: 4b0b ldr r3, [pc, #44] ; (8002540 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002512: 681b ldr r3, [r3, #0]
8002514: f023 0207 bic.w r2, r3, #7
8002518: 4909 ldr r1, [pc, #36] ; (8002540 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800251a: 693b ldr r3, [r7, #16]
800251c: 4313 orrs r3, r2
800251e: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
8002520: 4b07 ldr r3, [pc, #28] ; (8002540 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002522: 681b ldr r3, [r3, #0]
8002524: f003 0307 and.w r3, r3, #7
8002528: 693a ldr r2, [r7, #16]
800252a: 429a cmp r2, r3
800252c: d001 beq.n 8002532 <RCC_SetFlashLatencyFromMSIRange+0xae>
{
return HAL_ERROR;
800252e: 2301 movs r3, #1
8002530: e000 b.n 8002534 <RCC_SetFlashLatencyFromMSIRange+0xb0>
}
return HAL_OK;
8002532: 2300 movs r3, #0
}
8002534: 4618 mov r0, r3
8002536: 3718 adds r7, #24
8002538: 46bd mov sp, r7
800253a: bd80 pop {r7, pc}
800253c: 40021000 .word 0x40021000
8002540: 40022000 .word 0x40022000
08002544 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002544: b580 push {r7, lr}
8002546: b086 sub sp, #24
8002548: af00 add r7, sp, #0
800254a: 6078 str r0, [r7, #4]
uint32_t tmpregister, tickstart; /* no init needed */
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
800254c: 2300 movs r3, #0
800254e: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8002550: 2300 movs r3, #0
8002552: 74bb strb r3, [r7, #18]
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
8002554: 687b ldr r3, [r7, #4]
8002556: 681b ldr r3, [r3, #0]
8002558: f403 6300 and.w r3, r3, #2048 ; 0x800
800255c: 2b00 cmp r3, #0
800255e: d031 beq.n 80025c4 <HAL_RCCEx_PeriphCLKConfig+0x80>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
switch(PeriphClkInit->Sai1ClockSelection)
8002560: 687b ldr r3, [r7, #4]
8002562: 6c5b ldr r3, [r3, #68] ; 0x44
8002564: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
8002568: d01a beq.n 80025a0 <HAL_RCCEx_PeriphCLKConfig+0x5c>
800256a: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
800256e: d814 bhi.n 800259a <HAL_RCCEx_PeriphCLKConfig+0x56>
8002570: 2b00 cmp r3, #0
8002572: d009 beq.n 8002588 <HAL_RCCEx_PeriphCLKConfig+0x44>
8002574: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
8002578: d10f bne.n 800259a <HAL_RCCEx_PeriphCLKConfig+0x56>
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
#else
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
800257a: 4b5d ldr r3, [pc, #372] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
800257c: 68db ldr r3, [r3, #12]
800257e: 4a5c ldr r2, [pc, #368] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
8002580: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002584: 60d3 str r3, [r2, #12]
#endif /* RCC_PLLSAI2_SUPPORT */
/* SAI1 clock source config set later after clock selection check */
break;
8002586: e00c b.n 80025a2 <HAL_RCCEx_PeriphCLKConfig+0x5e>
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
8002588: 687b ldr r3, [r7, #4]
800258a: 3304 adds r3, #4
800258c: 2100 movs r1, #0
800258e: 4618 mov r0, r3
8002590: f000 f9f0 bl 8002974 <RCCEx_PLLSAI1_Config>
8002594: 4603 mov r3, r0
8002596: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
8002598: e003 b.n 80025a2 <HAL_RCCEx_PeriphCLKConfig+0x5e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI1 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
800259a: 2301 movs r3, #1
800259c: 74fb strb r3, [r7, #19]
break;
800259e: e000 b.n 80025a2 <HAL_RCCEx_PeriphCLKConfig+0x5e>
break;
80025a0: bf00 nop
}
if(ret == HAL_OK)
80025a2: 7cfb ldrb r3, [r7, #19]
80025a4: 2b00 cmp r3, #0
80025a6: d10b bne.n 80025c0 <HAL_RCCEx_PeriphCLKConfig+0x7c>
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80025a8: 4b51 ldr r3, [pc, #324] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80025aa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80025ae: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
80025b2: 687b ldr r3, [r7, #4]
80025b4: 6c5b ldr r3, [r3, #68] ; 0x44
80025b6: 494e ldr r1, [pc, #312] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80025b8: 4313 orrs r3, r2
80025ba: f8c1 3088 str.w r3, [r1, #136] ; 0x88
80025be: e001 b.n 80025c4 <HAL_RCCEx_PeriphCLKConfig+0x80>
}
else
{
/* set overall return value */
status = ret;
80025c0: 7cfb ldrb r3, [r7, #19]
80025c2: 74bb strb r3, [r7, #18]
}
}
#endif /* SAI2 */
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
80025c4: 687b ldr r3, [r7, #4]
80025c6: 681b ldr r3, [r3, #0]
80025c8: f403 3300 and.w r3, r3, #131072 ; 0x20000
80025cc: 2b00 cmp r3, #0
80025ce: f000 809e beq.w 800270e <HAL_RCCEx_PeriphCLKConfig+0x1ca>
{
FlagStatus pwrclkchanged = RESET;
80025d2: 2300 movs r3, #0
80025d4: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
80025d6: 4b46 ldr r3, [pc, #280] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80025d8: 6d9b ldr r3, [r3, #88] ; 0x58
80025da: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80025de: 2b00 cmp r3, #0
80025e0: d101 bne.n 80025e6 <HAL_RCCEx_PeriphCLKConfig+0xa2>
80025e2: 2301 movs r3, #1
80025e4: e000 b.n 80025e8 <HAL_RCCEx_PeriphCLKConfig+0xa4>
80025e6: 2300 movs r3, #0
80025e8: 2b00 cmp r3, #0
80025ea: d00d beq.n 8002608 <HAL_RCCEx_PeriphCLKConfig+0xc4>
{
__HAL_RCC_PWR_CLK_ENABLE();
80025ec: 4b40 ldr r3, [pc, #256] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80025ee: 6d9b ldr r3, [r3, #88] ; 0x58
80025f0: 4a3f ldr r2, [pc, #252] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80025f2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80025f6: 6593 str r3, [r2, #88] ; 0x58
80025f8: 4b3d ldr r3, [pc, #244] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80025fa: 6d9b ldr r3, [r3, #88] ; 0x58
80025fc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002600: 60bb str r3, [r7, #8]
8002602: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002604: 2301 movs r3, #1
8002606: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8002608: 4b3a ldr r3, [pc, #232] ; (80026f4 <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
800260a: 681b ldr r3, [r3, #0]
800260c: 4a39 ldr r2, [pc, #228] ; (80026f4 <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
800260e: f443 7380 orr.w r3, r3, #256 ; 0x100
8002612: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002614: f7fe fda8 bl 8001168 <HAL_GetTick>
8002618: 60f8 str r0, [r7, #12]
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
800261a: e009 b.n 8002630 <HAL_RCCEx_PeriphCLKConfig+0xec>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800261c: f7fe fda4 bl 8001168 <HAL_GetTick>
8002620: 4602 mov r2, r0
8002622: 68fb ldr r3, [r7, #12]
8002624: 1ad3 subs r3, r2, r3
8002626: 2b02 cmp r3, #2
8002628: d902 bls.n 8002630 <HAL_RCCEx_PeriphCLKConfig+0xec>
{
ret = HAL_TIMEOUT;
800262a: 2303 movs r3, #3
800262c: 74fb strb r3, [r7, #19]
break;
800262e: e005 b.n 800263c <HAL_RCCEx_PeriphCLKConfig+0xf8>
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8002630: 4b30 ldr r3, [pc, #192] ; (80026f4 <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
8002632: 681b ldr r3, [r3, #0]
8002634: f403 7380 and.w r3, r3, #256 ; 0x100
8002638: 2b00 cmp r3, #0
800263a: d0ef beq.n 800261c <HAL_RCCEx_PeriphCLKConfig+0xd8>
}
}
if(ret == HAL_OK)
800263c: 7cfb ldrb r3, [r7, #19]
800263e: 2b00 cmp r3, #0
8002640: d15a bne.n 80026f8 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8002642: 4b2b ldr r3, [pc, #172] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
8002644: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8002648: f403 7340 and.w r3, r3, #768 ; 0x300
800264c: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
800264e: 697b ldr r3, [r7, #20]
8002650: 2b00 cmp r3, #0
8002652: d01e beq.n 8002692 <HAL_RCCEx_PeriphCLKConfig+0x14e>
8002654: 687b ldr r3, [r7, #4]
8002656: 6d9b ldr r3, [r3, #88] ; 0x58
8002658: 697a ldr r2, [r7, #20]
800265a: 429a cmp r2, r3
800265c: d019 beq.n 8002692 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
800265e: 4b24 ldr r3, [pc, #144] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
8002660: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8002664: f423 7340 bic.w r3, r3, #768 ; 0x300
8002668: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
800266a: 4b21 ldr r3, [pc, #132] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
800266c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8002670: 4a1f ldr r2, [pc, #124] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
8002672: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002676: f8c2 3090 str.w r3, [r2, #144] ; 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
800267a: 4b1d ldr r3, [pc, #116] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
800267c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8002680: 4a1b ldr r2, [pc, #108] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
8002682: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002686: f8c2 3090 str.w r3, [r2, #144] ; 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
800268a: 4a19 ldr r2, [pc, #100] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
800268c: 697b ldr r3, [r7, #20]
800268e: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8002692: 697b ldr r3, [r7, #20]
8002694: f003 0301 and.w r3, r3, #1
8002698: 2b00 cmp r3, #0
800269a: d016 beq.n 80026ca <HAL_RCCEx_PeriphCLKConfig+0x186>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800269c: f7fe fd64 bl 8001168 <HAL_GetTick>
80026a0: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80026a2: e00b b.n 80026bc <HAL_RCCEx_PeriphCLKConfig+0x178>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80026a4: f7fe fd60 bl 8001168 <HAL_GetTick>
80026a8: 4602 mov r2, r0
80026aa: 68fb ldr r3, [r7, #12]
80026ac: 1ad3 subs r3, r2, r3
80026ae: f241 3288 movw r2, #5000 ; 0x1388
80026b2: 4293 cmp r3, r2
80026b4: d902 bls.n 80026bc <HAL_RCCEx_PeriphCLKConfig+0x178>
{
ret = HAL_TIMEOUT;
80026b6: 2303 movs r3, #3
80026b8: 74fb strb r3, [r7, #19]
break;
80026ba: e006 b.n 80026ca <HAL_RCCEx_PeriphCLKConfig+0x186>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80026bc: 4b0c ldr r3, [pc, #48] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80026be: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80026c2: f003 0302 and.w r3, r3, #2
80026c6: 2b00 cmp r3, #0
80026c8: d0ec beq.n 80026a4 <HAL_RCCEx_PeriphCLKConfig+0x160>
}
}
}
if(ret == HAL_OK)
80026ca: 7cfb ldrb r3, [r7, #19]
80026cc: 2b00 cmp r3, #0
80026ce: d10b bne.n 80026e8 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
80026d0: 4b07 ldr r3, [pc, #28] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80026d2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80026d6: f423 7240 bic.w r2, r3, #768 ; 0x300
80026da: 687b ldr r3, [r7, #4]
80026dc: 6d9b ldr r3, [r3, #88] ; 0x58
80026de: 4904 ldr r1, [pc, #16] ; (80026f0 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
80026e0: 4313 orrs r3, r2
80026e2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
80026e6: e009 b.n 80026fc <HAL_RCCEx_PeriphCLKConfig+0x1b8>
}
else
{
/* set overall return value */
status = ret;
80026e8: 7cfb ldrb r3, [r7, #19]
80026ea: 74bb strb r3, [r7, #18]
80026ec: e006 b.n 80026fc <HAL_RCCEx_PeriphCLKConfig+0x1b8>
80026ee: bf00 nop
80026f0: 40021000 .word 0x40021000
80026f4: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
80026f8: 7cfb ldrb r3, [r7, #19]
80026fa: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
80026fc: 7c7b ldrb r3, [r7, #17]
80026fe: 2b01 cmp r3, #1
8002700: d105 bne.n 800270e <HAL_RCCEx_PeriphCLKConfig+0x1ca>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002702: 4b9b ldr r3, [pc, #620] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002704: 6d9b ldr r3, [r3, #88] ; 0x58
8002706: 4a9a ldr r2, [pc, #616] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002708: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
800270c: 6593 str r3, [r2, #88] ; 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800270e: 687b ldr r3, [r7, #4]
8002710: 681b ldr r3, [r3, #0]
8002712: f003 0301 and.w r3, r3, #1
8002716: 2b00 cmp r3, #0
8002718: d00a beq.n 8002730 <HAL_RCCEx_PeriphCLKConfig+0x1ec>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
800271a: 4b95 ldr r3, [pc, #596] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800271c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002720: f023 0203 bic.w r2, r3, #3
8002724: 687b ldr r3, [r7, #4]
8002726: 6a1b ldr r3, [r3, #32]
8002728: 4991 ldr r1, [pc, #580] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800272a: 4313 orrs r3, r2
800272c: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8002730: 687b ldr r3, [r7, #4]
8002732: 681b ldr r3, [r3, #0]
8002734: f003 0302 and.w r3, r3, #2
8002738: 2b00 cmp r3, #0
800273a: d00a beq.n 8002752 <HAL_RCCEx_PeriphCLKConfig+0x20e>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
800273c: 4b8c ldr r3, [pc, #560] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800273e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002742: f023 020c bic.w r2, r3, #12
8002746: 687b ldr r3, [r7, #4]
8002748: 6a5b ldr r3, [r3, #36] ; 0x24
800274a: 4989 ldr r1, [pc, #548] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800274c: 4313 orrs r3, r2
800274e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8002752: 687b ldr r3, [r7, #4]
8002754: 681b ldr r3, [r3, #0]
8002756: f003 0304 and.w r3, r3, #4
800275a: 2b00 cmp r3, #0
800275c: d00a beq.n 8002774 <HAL_RCCEx_PeriphCLKConfig+0x230>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
800275e: 4b84 ldr r3, [pc, #528] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002760: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002764: f023 0230 bic.w r2, r3, #48 ; 0x30
8002768: 687b ldr r3, [r7, #4]
800276a: 6a9b ldr r3, [r3, #40] ; 0x28
800276c: 4980 ldr r1, [pc, #512] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800276e: 4313 orrs r3, r2
8002770: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8002774: 687b ldr r3, [r7, #4]
8002776: 681b ldr r3, [r3, #0]
8002778: f003 0320 and.w r3, r3, #32
800277c: 2b00 cmp r3, #0
800277e: d00a beq.n 8002796 <HAL_RCCEx_PeriphCLKConfig+0x252>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8002780: 4b7b ldr r3, [pc, #492] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002782: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002786: f423 6240 bic.w r2, r3, #3072 ; 0xc00
800278a: 687b ldr r3, [r7, #4]
800278c: 6adb ldr r3, [r3, #44] ; 0x2c
800278e: 4978 ldr r1, [pc, #480] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002790: 4313 orrs r3, r2
8002792: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
8002796: 687b ldr r3, [r7, #4]
8002798: 681b ldr r3, [r3, #0]
800279a: f403 7300 and.w r3, r3, #512 ; 0x200
800279e: 2b00 cmp r3, #0
80027a0: d00a beq.n 80027b8 <HAL_RCCEx_PeriphCLKConfig+0x274>
{
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80027a2: 4b73 ldr r3, [pc, #460] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80027a4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80027a8: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
80027ac: 687b ldr r3, [r7, #4]
80027ae: 6bdb ldr r3, [r3, #60] ; 0x3c
80027b0: 496f ldr r1, [pc, #444] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80027b2: 4313 orrs r3, r2
80027b4: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
80027b8: 687b ldr r3, [r7, #4]
80027ba: 681b ldr r3, [r3, #0]
80027bc: f403 6380 and.w r3, r3, #1024 ; 0x400
80027c0: 2b00 cmp r3, #0
80027c2: d00a beq.n 80027da <HAL_RCCEx_PeriphCLKConfig+0x296>
{
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
80027c4: 4b6a ldr r3, [pc, #424] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80027c6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80027ca: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
80027ce: 687b ldr r3, [r7, #4]
80027d0: 6c1b ldr r3, [r3, #64] ; 0x40
80027d2: 4967 ldr r1, [pc, #412] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80027d4: 4313 orrs r3, r2
80027d6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80027da: 687b ldr r3, [r7, #4]
80027dc: 681b ldr r3, [r3, #0]
80027de: f003 0340 and.w r3, r3, #64 ; 0x40
80027e2: 2b00 cmp r3, #0
80027e4: d00a beq.n 80027fc <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80027e6: 4b62 ldr r3, [pc, #392] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80027e8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80027ec: f423 5240 bic.w r2, r3, #12288 ; 0x3000
80027f0: 687b ldr r3, [r7, #4]
80027f2: 6b1b ldr r3, [r3, #48] ; 0x30
80027f4: 495e ldr r1, [pc, #376] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80027f6: 4313 orrs r3, r2
80027f8: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(I2C2)
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80027fc: 687b ldr r3, [r7, #4]
80027fe: 681b ldr r3, [r3, #0]
8002800: f003 0380 and.w r3, r3, #128 ; 0x80
8002804: 2b00 cmp r3, #0
8002806: d00a beq.n 800281e <HAL_RCCEx_PeriphCLKConfig+0x2da>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8002808: 4b59 ldr r3, [pc, #356] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800280a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800280e: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8002812: 687b ldr r3, [r7, #4]
8002814: 6b5b ldr r3, [r3, #52] ; 0x34
8002816: 4956 ldr r1, [pc, #344] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002818: 4313 orrs r3, r2
800281a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#endif /* I2C2 */
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
800281e: 687b ldr r3, [r7, #4]
8002820: 681b ldr r3, [r3, #0]
8002822: f403 7380 and.w r3, r3, #256 ; 0x100
8002826: 2b00 cmp r3, #0
8002828: d00a beq.n 8002840 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
800282a: 4b51 ldr r3, [pc, #324] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800282c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002830: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8002834: 687b ldr r3, [r7, #4]
8002836: 6b9b ldr r3, [r3, #56] ; 0x38
8002838: 494d ldr r1, [pc, #308] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800283a: 4313 orrs r3, r2
800283c: f8c1 3088 str.w r3, [r1, #136] ; 0x88
#endif /* USB_OTG_FS || USB */
#if defined(SDMMC1)
/*-------------------------- SDMMC1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
8002840: 687b ldr r3, [r7, #4]
8002842: 681b ldr r3, [r3, #0]
8002844: f403 2300 and.w r3, r3, #524288 ; 0x80000
8002848: 2b00 cmp r3, #0
800284a: d028 beq.n 800289e <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
800284c: 4b48 ldr r3, [pc, #288] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800284e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002852: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
8002856: 687b ldr r3, [r7, #4]
8002858: 6c9b ldr r3, [r3, #72] ; 0x48
800285a: 4945 ldr r1, [pc, #276] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800285c: 4313 orrs r3, r2
800285e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
8002862: 687b ldr r3, [r7, #4]
8002864: 6c9b ldr r3, [r3, #72] ; 0x48
8002866: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
800286a: d106 bne.n 800287a <HAL_RCCEx_PeriphCLKConfig+0x336>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800286c: 4b40 ldr r3, [pc, #256] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800286e: 68db ldr r3, [r3, #12]
8002870: 4a3f ldr r2, [pc, #252] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002872: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
8002876: 60d3 str r3, [r2, #12]
8002878: e011 b.n 800289e <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Enable PLLSAI3CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
}
#endif
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
800287a: 687b ldr r3, [r7, #4]
800287c: 6c9b ldr r3, [r3, #72] ; 0x48
800287e: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
8002882: d10c bne.n 800289e <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
8002884: 687b ldr r3, [r7, #4]
8002886: 3304 adds r3, #4
8002888: 2101 movs r1, #1
800288a: 4618 mov r0, r3
800288c: f000 f872 bl 8002974 <RCCEx_PLLSAI1_Config>
8002890: 4603 mov r3, r0
8002892: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8002894: 7cfb ldrb r3, [r7, #19]
8002896: 2b00 cmp r3, #0
8002898: d001 beq.n 800289e <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* set overall return value */
status = ret;
800289a: 7cfb ldrb r3, [r7, #19]
800289c: 74bb strb r3, [r7, #18]
}
#endif /* SDMMC1 */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
800289e: 687b ldr r3, [r7, #4]
80028a0: 681b ldr r3, [r3, #0]
80028a2: f403 2380 and.w r3, r3, #262144 ; 0x40000
80028a6: 2b00 cmp r3, #0
80028a8: d028 beq.n 80028fc <HAL_RCCEx_PeriphCLKConfig+0x3b8>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
80028aa: 4b31 ldr r3, [pc, #196] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80028ac: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80028b0: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
80028b4: 687b ldr r3, [r7, #4]
80028b6: 6cdb ldr r3, [r3, #76] ; 0x4c
80028b8: 492d ldr r1, [pc, #180] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80028ba: 4313 orrs r3, r2
80028bc: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
80028c0: 687b ldr r3, [r7, #4]
80028c2: 6cdb ldr r3, [r3, #76] ; 0x4c
80028c4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80028c8: d106 bne.n 80028d8 <HAL_RCCEx_PeriphCLKConfig+0x394>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80028ca: 4b29 ldr r3, [pc, #164] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80028cc: 68db ldr r3, [r3, #12]
80028ce: 4a28 ldr r2, [pc, #160] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
80028d0: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
80028d4: 60d3 str r3, [r2, #12]
80028d6: e011 b.n 80028fc <HAL_RCCEx_PeriphCLKConfig+0x3b8>
}
#if defined(RCC_PLLSAI1_SUPPORT)
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
80028d8: 687b ldr r3, [r7, #4]
80028da: 6cdb ldr r3, [r3, #76] ; 0x4c
80028dc: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
80028e0: d10c bne.n 80028fc <HAL_RCCEx_PeriphCLKConfig+0x3b8>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
80028e2: 687b ldr r3, [r7, #4]
80028e4: 3304 adds r3, #4
80028e6: 2101 movs r1, #1
80028e8: 4618 mov r0, r3
80028ea: f000 f843 bl 8002974 <RCCEx_PLLSAI1_Config>
80028ee: 4603 mov r3, r0
80028f0: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
80028f2: 7cfb ldrb r3, [r7, #19]
80028f4: 2b00 cmp r3, #0
80028f6: d001 beq.n 80028fc <HAL_RCCEx_PeriphCLKConfig+0x3b8>
{
/* set overall return value */
status = ret;
80028f8: 7cfb ldrb r3, [r7, #19]
80028fa: 74bb strb r3, [r7, #18]
}
}
/*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
80028fc: 687b ldr r3, [r7, #4]
80028fe: 681b ldr r3, [r3, #0]
8002900: f403 4380 and.w r3, r3, #16384 ; 0x4000
8002904: 2b00 cmp r3, #0
8002906: d01c beq.n 8002942 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8002908: 4b19 ldr r3, [pc, #100] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800290a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800290e: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
8002912: 687b ldr r3, [r7, #4]
8002914: 6d1b ldr r3, [r3, #80] ; 0x50
8002916: 4916 ldr r1, [pc, #88] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002918: 4313 orrs r3, r2
800291a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
800291e: 687b ldr r3, [r7, #4]
8002920: 6d1b ldr r3, [r3, #80] ; 0x50
8002922: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
8002926: d10c bne.n 8002942 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
8002928: 687b ldr r3, [r7, #4]
800292a: 3304 adds r3, #4
800292c: 2102 movs r1, #2
800292e: 4618 mov r0, r3
8002930: f000 f820 bl 8002974 <RCCEx_PLLSAI1_Config>
8002934: 4603 mov r3, r0
8002936: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8002938: 7cfb ldrb r3, [r7, #19]
800293a: 2b00 cmp r3, #0
800293c: d001 beq.n 8002942 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* set overall return value */
status = ret;
800293e: 7cfb ldrb r3, [r7, #19]
8002940: 74bb strb r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */
#if defined(SWPMI1)
/*-------------------------- SWPMI1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
8002942: 687b ldr r3, [r7, #4]
8002944: 681b ldr r3, [r3, #0]
8002946: f403 4300 and.w r3, r3, #32768 ; 0x8000
800294a: 2b00 cmp r3, #0
800294c: d00a beq.n 8002964 <HAL_RCCEx_PeriphCLKConfig+0x420>
{
/* Check the parameters */
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
/* Configure the SWPMI1 clock source */
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
800294e: 4b08 ldr r3, [pc, #32] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
8002950: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002954: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000
8002958: 687b ldr r3, [r7, #4]
800295a: 6d5b ldr r3, [r3, #84] ; 0x54
800295c: 4904 ldr r1, [pc, #16] ; (8002970 <HAL_RCCEx_PeriphCLKConfig+0x42c>)
800295e: 4313 orrs r3, r2
8002960: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
}
#endif /* OCTOSPI1 || OCTOSPI2 */
return status;
8002964: 7cbb ldrb r3, [r7, #18]
}
8002966: 4618 mov r0, r3
8002968: 3718 adds r7, #24
800296a: 46bd mov sp, r7
800296c: bd80 pop {r7, pc}
800296e: bf00 nop
8002970: 40021000 .word 0x40021000
08002974 <RCCEx_PLLSAI1_Config>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
8002974: b580 push {r7, lr}
8002976: b084 sub sp, #16
8002978: af00 add r7, sp, #0
800297a: 6078 str r0, [r7, #4]
800297c: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
800297e: 2300 movs r3, #0
8002980: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
/* Check that PLLSAI1 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
8002982: 4b74 ldr r3, [pc, #464] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002984: 68db ldr r3, [r3, #12]
8002986: f003 0303 and.w r3, r3, #3
800298a: 2b00 cmp r3, #0
800298c: d018 beq.n 80029c0 <RCCEx_PLLSAI1_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
800298e: 4b71 ldr r3, [pc, #452] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002990: 68db ldr r3, [r3, #12]
8002992: f003 0203 and.w r2, r3, #3
8002996: 687b ldr r3, [r7, #4]
8002998: 681b ldr r3, [r3, #0]
800299a: 429a cmp r2, r3
800299c: d10d bne.n 80029ba <RCCEx_PLLSAI1_Config+0x46>
||
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
800299e: 687b ldr r3, [r7, #4]
80029a0: 681b ldr r3, [r3, #0]
||
80029a2: 2b00 cmp r3, #0
80029a4: d009 beq.n 80029ba <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
80029a6: 4b6b ldr r3, [pc, #428] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
80029a8: 68db ldr r3, [r3, #12]
80029aa: 091b lsrs r3, r3, #4
80029ac: f003 0307 and.w r3, r3, #7
80029b0: 1c5a adds r2, r3, #1
80029b2: 687b ldr r3, [r7, #4]
80029b4: 685b ldr r3, [r3, #4]
||
80029b6: 429a cmp r2, r3
80029b8: d047 beq.n 8002a4a <RCCEx_PLLSAI1_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
80029ba: 2301 movs r3, #1
80029bc: 73fb strb r3, [r7, #15]
80029be: e044 b.n 8002a4a <RCCEx_PLLSAI1_Config+0xd6>
}
}
else
{
/* Check PLLSAI1 clock source availability */
switch(PllSai1->PLLSAI1Source)
80029c0: 687b ldr r3, [r7, #4]
80029c2: 681b ldr r3, [r3, #0]
80029c4: 2b03 cmp r3, #3
80029c6: d018 beq.n 80029fa <RCCEx_PLLSAI1_Config+0x86>
80029c8: 2b03 cmp r3, #3
80029ca: d825 bhi.n 8002a18 <RCCEx_PLLSAI1_Config+0xa4>
80029cc: 2b01 cmp r3, #1
80029ce: d002 beq.n 80029d6 <RCCEx_PLLSAI1_Config+0x62>
80029d0: 2b02 cmp r3, #2
80029d2: d009 beq.n 80029e8 <RCCEx_PLLSAI1_Config+0x74>
80029d4: e020 b.n 8002a18 <RCCEx_PLLSAI1_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
80029d6: 4b5f ldr r3, [pc, #380] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
80029d8: 681b ldr r3, [r3, #0]
80029da: f003 0302 and.w r3, r3, #2
80029de: 2b00 cmp r3, #0
80029e0: d11d bne.n 8002a1e <RCCEx_PLLSAI1_Config+0xaa>
{
status = HAL_ERROR;
80029e2: 2301 movs r3, #1
80029e4: 73fb strb r3, [r7, #15]
}
break;
80029e6: e01a b.n 8002a1e <RCCEx_PLLSAI1_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
80029e8: 4b5a ldr r3, [pc, #360] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
80029ea: 681b ldr r3, [r3, #0]
80029ec: f403 6380 and.w r3, r3, #1024 ; 0x400
80029f0: 2b00 cmp r3, #0
80029f2: d116 bne.n 8002a22 <RCCEx_PLLSAI1_Config+0xae>
{
status = HAL_ERROR;
80029f4: 2301 movs r3, #1
80029f6: 73fb strb r3, [r7, #15]
}
break;
80029f8: e013 b.n 8002a22 <RCCEx_PLLSAI1_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
80029fa: 4b56 ldr r3, [pc, #344] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
80029fc: 681b ldr r3, [r3, #0]
80029fe: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002a02: 2b00 cmp r3, #0
8002a04: d10f bne.n 8002a26 <RCCEx_PLLSAI1_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8002a06: 4b53 ldr r3, [pc, #332] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a08: 681b ldr r3, [r3, #0]
8002a0a: f403 2380 and.w r3, r3, #262144 ; 0x40000
8002a0e: 2b00 cmp r3, #0
8002a10: d109 bne.n 8002a26 <RCCEx_PLLSAI1_Config+0xb2>
{
status = HAL_ERROR;
8002a12: 2301 movs r3, #1
8002a14: 73fb strb r3, [r7, #15]
}
}
break;
8002a16: e006 b.n 8002a26 <RCCEx_PLLSAI1_Config+0xb2>
default:
status = HAL_ERROR;
8002a18: 2301 movs r3, #1
8002a1a: 73fb strb r3, [r7, #15]
break;
8002a1c: e004 b.n 8002a28 <RCCEx_PLLSAI1_Config+0xb4>
break;
8002a1e: bf00 nop
8002a20: e002 b.n 8002a28 <RCCEx_PLLSAI1_Config+0xb4>
break;
8002a22: bf00 nop
8002a24: e000 b.n 8002a28 <RCCEx_PLLSAI1_Config+0xb4>
break;
8002a26: bf00 nop
}
if(status == HAL_OK)
8002a28: 7bfb ldrb r3, [r7, #15]
8002a2a: 2b00 cmp r3, #0
8002a2c: d10d bne.n 8002a4a <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* Set PLLSAI1 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
/* Set PLLSAI1 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
8002a2e: 4b49 ldr r3, [pc, #292] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a30: 68db ldr r3, [r3, #12]
8002a32: f023 0273 bic.w r2, r3, #115 ; 0x73
8002a36: 687b ldr r3, [r7, #4]
8002a38: 6819 ldr r1, [r3, #0]
8002a3a: 687b ldr r3, [r7, #4]
8002a3c: 685b ldr r3, [r3, #4]
8002a3e: 3b01 subs r3, #1
8002a40: 011b lsls r3, r3, #4
8002a42: 430b orrs r3, r1
8002a44: 4943 ldr r1, [pc, #268] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a46: 4313 orrs r3, r2
8002a48: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
8002a4a: 7bfb ldrb r3, [r7, #15]
8002a4c: 2b00 cmp r3, #0
8002a4e: d17c bne.n 8002b4a <RCCEx_PLLSAI1_Config+0x1d6>
{
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
8002a50: 4b40 ldr r3, [pc, #256] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a52: 681b ldr r3, [r3, #0]
8002a54: 4a3f ldr r2, [pc, #252] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a56: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
8002a5a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002a5c: f7fe fb84 bl 8001168 <HAL_GetTick>
8002a60: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
8002a62: e009 b.n 8002a78 <RCCEx_PLLSAI1_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
8002a64: f7fe fb80 bl 8001168 <HAL_GetTick>
8002a68: 4602 mov r2, r0
8002a6a: 68bb ldr r3, [r7, #8]
8002a6c: 1ad3 subs r3, r2, r3
8002a6e: 2b02 cmp r3, #2
8002a70: d902 bls.n 8002a78 <RCCEx_PLLSAI1_Config+0x104>
{
status = HAL_TIMEOUT;
8002a72: 2303 movs r3, #3
8002a74: 73fb strb r3, [r7, #15]
break;
8002a76: e005 b.n 8002a84 <RCCEx_PLLSAI1_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
8002a78: 4b36 ldr r3, [pc, #216] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a7a: 681b ldr r3, [r3, #0]
8002a7c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8002a80: 2b00 cmp r3, #0
8002a82: d1ef bne.n 8002a64 <RCCEx_PLLSAI1_Config+0xf0>
}
}
if(status == HAL_OK)
8002a84: 7bfb ldrb r3, [r7, #15]
8002a86: 2b00 cmp r3, #0
8002a88: d15f bne.n 8002b4a <RCCEx_PLLSAI1_Config+0x1d6>
{
if(Divider == DIVIDER_P_UPDATE)
8002a8a: 683b ldr r3, [r7, #0]
8002a8c: 2b00 cmp r3, #0
8002a8e: d110 bne.n 8002ab2 <RCCEx_PLLSAI1_Config+0x13e>
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#else
/* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
MODIFY_REG(RCC->PLLSAI1CFGR,
8002a90: 4b30 ldr r3, [pc, #192] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002a92: 691b ldr r3, [r3, #16]
8002a94: f023 4378 bic.w r3, r3, #4160749568 ; 0xf8000000
8002a98: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
8002a9c: 687a ldr r2, [r7, #4]
8002a9e: 6892 ldr r2, [r2, #8]
8002aa0: 0211 lsls r1, r2, #8
8002aa2: 687a ldr r2, [r7, #4]
8002aa4: 68d2 ldr r2, [r2, #12]
8002aa6: 06d2 lsls r2, r2, #27
8002aa8: 430a orrs r2, r1
8002aaa: 492a ldr r1, [pc, #168] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002aac: 4313 orrs r3, r2
8002aae: 610b str r3, [r1, #16]
8002ab0: e027 b.n 8002b02 <RCCEx_PLLSAI1_Config+0x18e>
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
else if(Divider == DIVIDER_Q_UPDATE)
8002ab2: 683b ldr r3, [r7, #0]
8002ab4: 2b01 cmp r3, #1
8002ab6: d112 bne.n 8002ade <RCCEx_PLLSAI1_Config+0x16a>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8002ab8: 4b26 ldr r3, [pc, #152] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002aba: 691b ldr r3, [r3, #16]
8002abc: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000
8002ac0: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
8002ac4: 687a ldr r2, [r7, #4]
8002ac6: 6892 ldr r2, [r2, #8]
8002ac8: 0211 lsls r1, r2, #8
8002aca: 687a ldr r2, [r7, #4]
8002acc: 6912 ldr r2, [r2, #16]
8002ace: 0852 lsrs r2, r2, #1
8002ad0: 3a01 subs r2, #1
8002ad2: 0552 lsls r2, r2, #21
8002ad4: 430a orrs r2, r1
8002ad6: 491f ldr r1, [pc, #124] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002ad8: 4313 orrs r3, r2
8002ada: 610b str r3, [r1, #16]
8002adc: e011 b.n 8002b02 <RCCEx_PLLSAI1_Config+0x18e>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8002ade: 4b1d ldr r3, [pc, #116] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002ae0: 691b ldr r3, [r3, #16]
8002ae2: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000
8002ae6: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
8002aea: 687a ldr r2, [r7, #4]
8002aec: 6892 ldr r2, [r2, #8]
8002aee: 0211 lsls r1, r2, #8
8002af0: 687a ldr r2, [r7, #4]
8002af2: 6952 ldr r2, [r2, #20]
8002af4: 0852 lsrs r2, r2, #1
8002af6: 3a01 subs r2, #1
8002af8: 0652 lsls r2, r2, #25
8002afa: 430a orrs r2, r1
8002afc: 4915 ldr r1, [pc, #84] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002afe: 4313 orrs r3, r2
8002b00: 610b str r3, [r1, #16]
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
8002b02: 4b14 ldr r3, [pc, #80] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002b04: 681b ldr r3, [r3, #0]
8002b06: 4a13 ldr r2, [pc, #76] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002b08: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8002b0c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002b0e: f7fe fb2b bl 8001168 <HAL_GetTick>
8002b12: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
8002b14: e009 b.n 8002b2a <RCCEx_PLLSAI1_Config+0x1b6>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
8002b16: f7fe fb27 bl 8001168 <HAL_GetTick>
8002b1a: 4602 mov r2, r0
8002b1c: 68bb ldr r3, [r7, #8]
8002b1e: 1ad3 subs r3, r2, r3
8002b20: 2b02 cmp r3, #2
8002b22: d902 bls.n 8002b2a <RCCEx_PLLSAI1_Config+0x1b6>
{
status = HAL_TIMEOUT;
8002b24: 2303 movs r3, #3
8002b26: 73fb strb r3, [r7, #15]
break;
8002b28: e005 b.n 8002b36 <RCCEx_PLLSAI1_Config+0x1c2>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
8002b2a: 4b0a ldr r3, [pc, #40] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002b2c: 681b ldr r3, [r3, #0]
8002b2e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8002b32: 2b00 cmp r3, #0
8002b34: d0ef beq.n 8002b16 <RCCEx_PLLSAI1_Config+0x1a2>
}
}
if(status == HAL_OK)
8002b36: 7bfb ldrb r3, [r7, #15]
8002b38: 2b00 cmp r3, #0
8002b3a: d106 bne.n 8002b4a <RCCEx_PLLSAI1_Config+0x1d6>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
8002b3c: 4b05 ldr r3, [pc, #20] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002b3e: 691a ldr r2, [r3, #16]
8002b40: 687b ldr r3, [r7, #4]
8002b42: 699b ldr r3, [r3, #24]
8002b44: 4903 ldr r1, [pc, #12] ; (8002b54 <RCCEx_PLLSAI1_Config+0x1e0>)
8002b46: 4313 orrs r3, r2
8002b48: 610b str r3, [r1, #16]
}
}
}
return status;
8002b4a: 7bfb ldrb r3, [r7, #15]
}
8002b4c: 4618 mov r0, r3
8002b4e: 3710 adds r7, #16
8002b50: 46bd mov sp, r7
8002b52: bd80 pop {r7, pc}
8002b54: 40021000 .word 0x40021000
08002b58 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8002b58: b580 push {r7, lr}
8002b5a: b082 sub sp, #8
8002b5c: af00 add r7, sp, #0
8002b5e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002b60: 687b ldr r3, [r7, #4]
8002b62: 2b00 cmp r3, #0
8002b64: d101 bne.n 8002b6a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8002b66: 2301 movs r3, #1
8002b68: e049 b.n 8002bfe <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002b6a: 687b ldr r3, [r7, #4]
8002b6c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002b70: b2db uxtb r3, r3
8002b72: 2b00 cmp r3, #0
8002b74: d106 bne.n 8002b84 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002b76: 687b ldr r3, [r7, #4]
8002b78: 2200 movs r2, #0
8002b7a: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002b7e: 6878 ldr r0, [r7, #4]
8002b80: f7fe f914 bl 8000dac <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002b84: 687b ldr r3, [r7, #4]
8002b86: 2202 movs r2, #2
8002b88: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002b8c: 687b ldr r3, [r7, #4]
8002b8e: 681a ldr r2, [r3, #0]
8002b90: 687b ldr r3, [r7, #4]
8002b92: 3304 adds r3, #4
8002b94: 4619 mov r1, r3
8002b96: 4610 mov r0, r2
8002b98: f000 fb52 bl 8003240 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002b9c: 687b ldr r3, [r7, #4]
8002b9e: 2201 movs r2, #1
8002ba0: f883 2048 strb.w r2, [r3, #72] ; 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002ba4: 687b ldr r3, [r7, #4]
8002ba6: 2201 movs r2, #1
8002ba8: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002bac: 687b ldr r3, [r7, #4]
8002bae: 2201 movs r2, #1
8002bb0: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002bb4: 687b ldr r3, [r7, #4]
8002bb6: 2201 movs r2, #1
8002bb8: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 2201 movs r2, #1
8002bc0: f883 2041 strb.w r2, [r3, #65] ; 0x41
8002bc4: 687b ldr r3, [r7, #4]
8002bc6: 2201 movs r2, #1
8002bc8: f883 2042 strb.w r2, [r3, #66] ; 0x42
8002bcc: 687b ldr r3, [r7, #4]
8002bce: 2201 movs r2, #1
8002bd0: f883 2043 strb.w r2, [r3, #67] ; 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002bd4: 687b ldr r3, [r7, #4]
8002bd6: 2201 movs r2, #1
8002bd8: f883 2044 strb.w r2, [r3, #68] ; 0x44
8002bdc: 687b ldr r3, [r7, #4]
8002bde: 2201 movs r2, #1
8002be0: f883 2045 strb.w r2, [r3, #69] ; 0x45
8002be4: 687b ldr r3, [r7, #4]
8002be6: 2201 movs r2, #1
8002be8: f883 2046 strb.w r2, [r3, #70] ; 0x46
8002bec: 687b ldr r3, [r7, #4]
8002bee: 2201 movs r2, #1
8002bf0: f883 2047 strb.w r2, [r3, #71] ; 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002bf4: 687b ldr r3, [r7, #4]
8002bf6: 2201 movs r2, #1
8002bf8: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8002bfc: 2300 movs r3, #0
}
8002bfe: 4618 mov r0, r3
8002c00: 3708 adds r7, #8
8002c02: 46bd mov sp, r7
8002c04: bd80 pop {r7, pc}
08002c06 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8002c06: b580 push {r7, lr}
8002c08: b082 sub sp, #8
8002c0a: af00 add r7, sp, #0
8002c0c: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002c0e: 687b ldr r3, [r7, #4]
8002c10: 2b00 cmp r3, #0
8002c12: d101 bne.n 8002c18 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8002c14: 2301 movs r3, #1
8002c16: e049 b.n 8002cac <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002c18: 687b ldr r3, [r7, #4]
8002c1a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002c1e: b2db uxtb r3, r3
8002c20: 2b00 cmp r3, #0
8002c22: d106 bne.n 8002c32 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002c24: 687b ldr r3, [r7, #4]
8002c26: 2200 movs r2, #0
8002c28: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8002c2c: 6878 ldr r0, [r7, #4]
8002c2e: f000 f841 bl 8002cb4 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002c32: 687b ldr r3, [r7, #4]
8002c34: 2202 movs r2, #2
8002c36: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002c3a: 687b ldr r3, [r7, #4]
8002c3c: 681a ldr r2, [r3, #0]
8002c3e: 687b ldr r3, [r7, #4]
8002c40: 3304 adds r3, #4
8002c42: 4619 mov r1, r3
8002c44: 4610 mov r0, r2
8002c46: f000 fafb bl 8003240 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002c4a: 687b ldr r3, [r7, #4]
8002c4c: 2201 movs r2, #1
8002c4e: f883 2048 strb.w r2, [r3, #72] ; 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002c52: 687b ldr r3, [r7, #4]
8002c54: 2201 movs r2, #1
8002c56: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002c5a: 687b ldr r3, [r7, #4]
8002c5c: 2201 movs r2, #1
8002c5e: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002c62: 687b ldr r3, [r7, #4]
8002c64: 2201 movs r2, #1
8002c66: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002c6a: 687b ldr r3, [r7, #4]
8002c6c: 2201 movs r2, #1
8002c6e: f883 2041 strb.w r2, [r3, #65] ; 0x41
8002c72: 687b ldr r3, [r7, #4]
8002c74: 2201 movs r2, #1
8002c76: f883 2042 strb.w r2, [r3, #66] ; 0x42
8002c7a: 687b ldr r3, [r7, #4]
8002c7c: 2201 movs r2, #1
8002c7e: f883 2043 strb.w r2, [r3, #67] ; 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002c82: 687b ldr r3, [r7, #4]
8002c84: 2201 movs r2, #1
8002c86: f883 2044 strb.w r2, [r3, #68] ; 0x44
8002c8a: 687b ldr r3, [r7, #4]
8002c8c: 2201 movs r2, #1
8002c8e: f883 2045 strb.w r2, [r3, #69] ; 0x45
8002c92: 687b ldr r3, [r7, #4]
8002c94: 2201 movs r2, #1
8002c96: f883 2046 strb.w r2, [r3, #70] ; 0x46
8002c9a: 687b ldr r3, [r7, #4]
8002c9c: 2201 movs r2, #1
8002c9e: f883 2047 strb.w r2, [r3, #71] ; 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002ca2: 687b ldr r3, [r7, #4]
8002ca4: 2201 movs r2, #1
8002ca6: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8002caa: 2300 movs r3, #0
}
8002cac: 4618 mov r0, r3
8002cae: 3708 adds r7, #8
8002cb0: 46bd mov sp, r7
8002cb2: bd80 pop {r7, pc}
08002cb4 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8002cb4: b480 push {r7}
8002cb6: b083 sub sp, #12
8002cb8: af00 add r7, sp, #0
8002cba: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8002cbc: bf00 nop
8002cbe: 370c adds r7, #12
8002cc0: 46bd mov sp, r7
8002cc2: f85d 7b04 ldr.w r7, [sp], #4
8002cc6: 4770 bx lr
08002cc8 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8002cc8: b580 push {r7, lr}
8002cca: b084 sub sp, #16
8002ccc: af00 add r7, sp, #0
8002cce: 6078 str r0, [r7, #4]
8002cd0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8002cd2: 683b ldr r3, [r7, #0]
8002cd4: 2b00 cmp r3, #0
8002cd6: d109 bne.n 8002cec <HAL_TIM_PWM_Start+0x24>
8002cd8: 687b ldr r3, [r7, #4]
8002cda: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8002cde: b2db uxtb r3, r3
8002ce0: 2b01 cmp r3, #1
8002ce2: bf14 ite ne
8002ce4: 2301 movne r3, #1
8002ce6: 2300 moveq r3, #0
8002ce8: b2db uxtb r3, r3
8002cea: e03c b.n 8002d66 <HAL_TIM_PWM_Start+0x9e>
8002cec: 683b ldr r3, [r7, #0]
8002cee: 2b04 cmp r3, #4
8002cf0: d109 bne.n 8002d06 <HAL_TIM_PWM_Start+0x3e>
8002cf2: 687b ldr r3, [r7, #4]
8002cf4: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
8002cf8: b2db uxtb r3, r3
8002cfa: 2b01 cmp r3, #1
8002cfc: bf14 ite ne
8002cfe: 2301 movne r3, #1
8002d00: 2300 moveq r3, #0
8002d02: b2db uxtb r3, r3
8002d04: e02f b.n 8002d66 <HAL_TIM_PWM_Start+0x9e>
8002d06: 683b ldr r3, [r7, #0]
8002d08: 2b08 cmp r3, #8
8002d0a: d109 bne.n 8002d20 <HAL_TIM_PWM_Start+0x58>
8002d0c: 687b ldr r3, [r7, #4]
8002d0e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8002d12: b2db uxtb r3, r3
8002d14: 2b01 cmp r3, #1
8002d16: bf14 ite ne
8002d18: 2301 movne r3, #1
8002d1a: 2300 moveq r3, #0
8002d1c: b2db uxtb r3, r3
8002d1e: e022 b.n 8002d66 <HAL_TIM_PWM_Start+0x9e>
8002d20: 683b ldr r3, [r7, #0]
8002d22: 2b0c cmp r3, #12
8002d24: d109 bne.n 8002d3a <HAL_TIM_PWM_Start+0x72>
8002d26: 687b ldr r3, [r7, #4]
8002d28: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8002d2c: b2db uxtb r3, r3
8002d2e: 2b01 cmp r3, #1
8002d30: bf14 ite ne
8002d32: 2301 movne r3, #1
8002d34: 2300 moveq r3, #0
8002d36: b2db uxtb r3, r3
8002d38: e015 b.n 8002d66 <HAL_TIM_PWM_Start+0x9e>
8002d3a: 683b ldr r3, [r7, #0]
8002d3c: 2b10 cmp r3, #16
8002d3e: d109 bne.n 8002d54 <HAL_TIM_PWM_Start+0x8c>
8002d40: 687b ldr r3, [r7, #4]
8002d42: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8002d46: b2db uxtb r3, r3
8002d48: 2b01 cmp r3, #1
8002d4a: bf14 ite ne
8002d4c: 2301 movne r3, #1
8002d4e: 2300 moveq r3, #0
8002d50: b2db uxtb r3, r3
8002d52: e008 b.n 8002d66 <HAL_TIM_PWM_Start+0x9e>
8002d54: 687b ldr r3, [r7, #4]
8002d56: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
8002d5a: b2db uxtb r3, r3
8002d5c: 2b01 cmp r3, #1
8002d5e: bf14 ite ne
8002d60: 2301 movne r3, #1
8002d62: 2300 moveq r3, #0
8002d64: b2db uxtb r3, r3
8002d66: 2b00 cmp r3, #0
8002d68: d001 beq.n 8002d6e <HAL_TIM_PWM_Start+0xa6>
{
return HAL_ERROR;
8002d6a: 2301 movs r3, #1
8002d6c: e07e b.n 8002e6c <HAL_TIM_PWM_Start+0x1a4>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8002d6e: 683b ldr r3, [r7, #0]
8002d70: 2b00 cmp r3, #0
8002d72: d104 bne.n 8002d7e <HAL_TIM_PWM_Start+0xb6>
8002d74: 687b ldr r3, [r7, #4]
8002d76: 2202 movs r2, #2
8002d78: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002d7c: e023 b.n 8002dc6 <HAL_TIM_PWM_Start+0xfe>
8002d7e: 683b ldr r3, [r7, #0]
8002d80: 2b04 cmp r3, #4
8002d82: d104 bne.n 8002d8e <HAL_TIM_PWM_Start+0xc6>
8002d84: 687b ldr r3, [r7, #4]
8002d86: 2202 movs r2, #2
8002d88: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002d8c: e01b b.n 8002dc6 <HAL_TIM_PWM_Start+0xfe>
8002d8e: 683b ldr r3, [r7, #0]
8002d90: 2b08 cmp r3, #8
8002d92: d104 bne.n 8002d9e <HAL_TIM_PWM_Start+0xd6>
8002d94: 687b ldr r3, [r7, #4]
8002d96: 2202 movs r2, #2
8002d98: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002d9c: e013 b.n 8002dc6 <HAL_TIM_PWM_Start+0xfe>
8002d9e: 683b ldr r3, [r7, #0]
8002da0: 2b0c cmp r3, #12
8002da2: d104 bne.n 8002dae <HAL_TIM_PWM_Start+0xe6>
8002da4: 687b ldr r3, [r7, #4]
8002da6: 2202 movs r2, #2
8002da8: f883 2041 strb.w r2, [r3, #65] ; 0x41
8002dac: e00b b.n 8002dc6 <HAL_TIM_PWM_Start+0xfe>
8002dae: 683b ldr r3, [r7, #0]
8002db0: 2b10 cmp r3, #16
8002db2: d104 bne.n 8002dbe <HAL_TIM_PWM_Start+0xf6>
8002db4: 687b ldr r3, [r7, #4]
8002db6: 2202 movs r2, #2
8002db8: f883 2042 strb.w r2, [r3, #66] ; 0x42
8002dbc: e003 b.n 8002dc6 <HAL_TIM_PWM_Start+0xfe>
8002dbe: 687b ldr r3, [r7, #4]
8002dc0: 2202 movs r2, #2
8002dc2: f883 2043 strb.w r2, [r3, #67] ; 0x43
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8002dc6: 687b ldr r3, [r7, #4]
8002dc8: 681b ldr r3, [r3, #0]
8002dca: 2201 movs r2, #1
8002dcc: 6839 ldr r1, [r7, #0]
8002dce: 4618 mov r0, r3
8002dd0: f000 fdb2 bl 8003938 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 681b ldr r3, [r3, #0]
8002dd8: 4a26 ldr r2, [pc, #152] ; (8002e74 <HAL_TIM_PWM_Start+0x1ac>)
8002dda: 4293 cmp r3, r2
8002ddc: d009 beq.n 8002df2 <HAL_TIM_PWM_Start+0x12a>
8002dde: 687b ldr r3, [r7, #4]
8002de0: 681b ldr r3, [r3, #0]
8002de2: 4a25 ldr r2, [pc, #148] ; (8002e78 <HAL_TIM_PWM_Start+0x1b0>)
8002de4: 4293 cmp r3, r2
8002de6: d004 beq.n 8002df2 <HAL_TIM_PWM_Start+0x12a>
8002de8: 687b ldr r3, [r7, #4]
8002dea: 681b ldr r3, [r3, #0]
8002dec: 4a23 ldr r2, [pc, #140] ; (8002e7c <HAL_TIM_PWM_Start+0x1b4>)
8002dee: 4293 cmp r3, r2
8002df0: d101 bne.n 8002df6 <HAL_TIM_PWM_Start+0x12e>
8002df2: 2301 movs r3, #1
8002df4: e000 b.n 8002df8 <HAL_TIM_PWM_Start+0x130>
8002df6: 2300 movs r3, #0
8002df8: 2b00 cmp r3, #0
8002dfa: d007 beq.n 8002e0c <HAL_TIM_PWM_Start+0x144>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8002dfc: 687b ldr r3, [r7, #4]
8002dfe: 681b ldr r3, [r3, #0]
8002e00: 6c5a ldr r2, [r3, #68] ; 0x44
8002e02: 687b ldr r3, [r7, #4]
8002e04: 681b ldr r3, [r3, #0]
8002e06: f442 4200 orr.w r2, r2, #32768 ; 0x8000
8002e0a: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002e0c: 687b ldr r3, [r7, #4]
8002e0e: 681b ldr r3, [r3, #0]
8002e10: 4a18 ldr r2, [pc, #96] ; (8002e74 <HAL_TIM_PWM_Start+0x1ac>)
8002e12: 4293 cmp r3, r2
8002e14: d009 beq.n 8002e2a <HAL_TIM_PWM_Start+0x162>
8002e16: 687b ldr r3, [r7, #4]
8002e18: 681b ldr r3, [r3, #0]
8002e1a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002e1e: d004 beq.n 8002e2a <HAL_TIM_PWM_Start+0x162>
8002e20: 687b ldr r3, [r7, #4]
8002e22: 681b ldr r3, [r3, #0]
8002e24: 4a14 ldr r2, [pc, #80] ; (8002e78 <HAL_TIM_PWM_Start+0x1b0>)
8002e26: 4293 cmp r3, r2
8002e28: d115 bne.n 8002e56 <HAL_TIM_PWM_Start+0x18e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002e2a: 687b ldr r3, [r7, #4]
8002e2c: 681b ldr r3, [r3, #0]
8002e2e: 689a ldr r2, [r3, #8]
8002e30: 4b13 ldr r3, [pc, #76] ; (8002e80 <HAL_TIM_PWM_Start+0x1b8>)
8002e32: 4013 ands r3, r2
8002e34: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002e36: 68fb ldr r3, [r7, #12]
8002e38: 2b06 cmp r3, #6
8002e3a: d015 beq.n 8002e68 <HAL_TIM_PWM_Start+0x1a0>
8002e3c: 68fb ldr r3, [r7, #12]
8002e3e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002e42: d011 beq.n 8002e68 <HAL_TIM_PWM_Start+0x1a0>
{
__HAL_TIM_ENABLE(htim);
8002e44: 687b ldr r3, [r7, #4]
8002e46: 681b ldr r3, [r3, #0]
8002e48: 681a ldr r2, [r3, #0]
8002e4a: 687b ldr r3, [r7, #4]
8002e4c: 681b ldr r3, [r3, #0]
8002e4e: f042 0201 orr.w r2, r2, #1
8002e52: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002e54: e008 b.n 8002e68 <HAL_TIM_PWM_Start+0x1a0>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002e56: 687b ldr r3, [r7, #4]
8002e58: 681b ldr r3, [r3, #0]
8002e5a: 681a ldr r2, [r3, #0]
8002e5c: 687b ldr r3, [r7, #4]
8002e5e: 681b ldr r3, [r3, #0]
8002e60: f042 0201 orr.w r2, r2, #1
8002e64: 601a str r2, [r3, #0]
8002e66: e000 b.n 8002e6a <HAL_TIM_PWM_Start+0x1a2>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002e68: bf00 nop
}
/* Return function status */
return HAL_OK;
8002e6a: 2300 movs r3, #0
}
8002e6c: 4618 mov r0, r3
8002e6e: 3710 adds r7, #16
8002e70: 46bd mov sp, r7
8002e72: bd80 pop {r7, pc}
8002e74: 40012c00 .word 0x40012c00
8002e78: 40014000 .word 0x40014000
8002e7c: 40014400 .word 0x40014400
8002e80: 00010007 .word 0x00010007
08002e84 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002e84: b580 push {r7, lr}
8002e86: b086 sub sp, #24
8002e88: af00 add r7, sp, #0
8002e8a: 60f8 str r0, [r7, #12]
8002e8c: 60b9 str r1, [r7, #8]
8002e8e: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002e90: 2300 movs r3, #0
8002e92: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8002e94: 68fb ldr r3, [r7, #12]
8002e96: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002e9a: 2b01 cmp r3, #1
8002e9c: d101 bne.n 8002ea2 <HAL_TIM_PWM_ConfigChannel+0x1e>
8002e9e: 2302 movs r3, #2
8002ea0: e0ff b.n 80030a2 <HAL_TIM_PWM_ConfigChannel+0x21e>
8002ea2: 68fb ldr r3, [r7, #12]
8002ea4: 2201 movs r2, #1
8002ea6: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8002eaa: 687b ldr r3, [r7, #4]
8002eac: 2b14 cmp r3, #20
8002eae: f200 80f0 bhi.w 8003092 <HAL_TIM_PWM_ConfigChannel+0x20e>
8002eb2: a201 add r2, pc, #4 ; (adr r2, 8002eb8 <HAL_TIM_PWM_ConfigChannel+0x34>)
8002eb4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002eb8: 08002f0d .word 0x08002f0d
8002ebc: 08003093 .word 0x08003093
8002ec0: 08003093 .word 0x08003093
8002ec4: 08003093 .word 0x08003093
8002ec8: 08002f4d .word 0x08002f4d
8002ecc: 08003093 .word 0x08003093
8002ed0: 08003093 .word 0x08003093
8002ed4: 08003093 .word 0x08003093
8002ed8: 08002f8f .word 0x08002f8f
8002edc: 08003093 .word 0x08003093
8002ee0: 08003093 .word 0x08003093
8002ee4: 08003093 .word 0x08003093
8002ee8: 08002fcf .word 0x08002fcf
8002eec: 08003093 .word 0x08003093
8002ef0: 08003093 .word 0x08003093
8002ef4: 08003093 .word 0x08003093
8002ef8: 08003011 .word 0x08003011
8002efc: 08003093 .word 0x08003093
8002f00: 08003093 .word 0x08003093
8002f04: 08003093 .word 0x08003093
8002f08: 08003051 .word 0x08003051
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8002f0c: 68fb ldr r3, [r7, #12]
8002f0e: 681b ldr r3, [r3, #0]
8002f10: 68b9 ldr r1, [r7, #8]
8002f12: 4618 mov r0, r3
8002f14: f000 f9f8 bl 8003308 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8002f18: 68fb ldr r3, [r7, #12]
8002f1a: 681b ldr r3, [r3, #0]
8002f1c: 699a ldr r2, [r3, #24]
8002f1e: 68fb ldr r3, [r7, #12]
8002f20: 681b ldr r3, [r3, #0]
8002f22: f042 0208 orr.w r2, r2, #8
8002f26: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8002f28: 68fb ldr r3, [r7, #12]
8002f2a: 681b ldr r3, [r3, #0]
8002f2c: 699a ldr r2, [r3, #24]
8002f2e: 68fb ldr r3, [r7, #12]
8002f30: 681b ldr r3, [r3, #0]
8002f32: f022 0204 bic.w r2, r2, #4
8002f36: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8002f38: 68fb ldr r3, [r7, #12]
8002f3a: 681b ldr r3, [r3, #0]
8002f3c: 6999 ldr r1, [r3, #24]
8002f3e: 68bb ldr r3, [r7, #8]
8002f40: 691a ldr r2, [r3, #16]
8002f42: 68fb ldr r3, [r7, #12]
8002f44: 681b ldr r3, [r3, #0]
8002f46: 430a orrs r2, r1
8002f48: 619a str r2, [r3, #24]
break;
8002f4a: e0a5 b.n 8003098 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8002f4c: 68fb ldr r3, [r7, #12]
8002f4e: 681b ldr r3, [r3, #0]
8002f50: 68b9 ldr r1, [r7, #8]
8002f52: 4618 mov r0, r3
8002f54: f000 fa54 bl 8003400 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8002f58: 68fb ldr r3, [r7, #12]
8002f5a: 681b ldr r3, [r3, #0]
8002f5c: 699a ldr r2, [r3, #24]
8002f5e: 68fb ldr r3, [r7, #12]
8002f60: 681b ldr r3, [r3, #0]
8002f62: f442 6200 orr.w r2, r2, #2048 ; 0x800
8002f66: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8002f68: 68fb ldr r3, [r7, #12]
8002f6a: 681b ldr r3, [r3, #0]
8002f6c: 699a ldr r2, [r3, #24]
8002f6e: 68fb ldr r3, [r7, #12]
8002f70: 681b ldr r3, [r3, #0]
8002f72: f422 6280 bic.w r2, r2, #1024 ; 0x400
8002f76: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8002f78: 68fb ldr r3, [r7, #12]
8002f7a: 681b ldr r3, [r3, #0]
8002f7c: 6999 ldr r1, [r3, #24]
8002f7e: 68bb ldr r3, [r7, #8]
8002f80: 691b ldr r3, [r3, #16]
8002f82: 021a lsls r2, r3, #8
8002f84: 68fb ldr r3, [r7, #12]
8002f86: 681b ldr r3, [r3, #0]
8002f88: 430a orrs r2, r1
8002f8a: 619a str r2, [r3, #24]
break;
8002f8c: e084 b.n 8003098 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8002f8e: 68fb ldr r3, [r7, #12]
8002f90: 681b ldr r3, [r3, #0]
8002f92: 68b9 ldr r1, [r7, #8]
8002f94: 4618 mov r0, r3
8002f96: f000 faad bl 80034f4 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8002f9a: 68fb ldr r3, [r7, #12]
8002f9c: 681b ldr r3, [r3, #0]
8002f9e: 69da ldr r2, [r3, #28]
8002fa0: 68fb ldr r3, [r7, #12]
8002fa2: 681b ldr r3, [r3, #0]
8002fa4: f042 0208 orr.w r2, r2, #8
8002fa8: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8002faa: 68fb ldr r3, [r7, #12]
8002fac: 681b ldr r3, [r3, #0]
8002fae: 69da ldr r2, [r3, #28]
8002fb0: 68fb ldr r3, [r7, #12]
8002fb2: 681b ldr r3, [r3, #0]
8002fb4: f022 0204 bic.w r2, r2, #4
8002fb8: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8002fba: 68fb ldr r3, [r7, #12]
8002fbc: 681b ldr r3, [r3, #0]
8002fbe: 69d9 ldr r1, [r3, #28]
8002fc0: 68bb ldr r3, [r7, #8]
8002fc2: 691a ldr r2, [r3, #16]
8002fc4: 68fb ldr r3, [r7, #12]
8002fc6: 681b ldr r3, [r3, #0]
8002fc8: 430a orrs r2, r1
8002fca: 61da str r2, [r3, #28]
break;
8002fcc: e064 b.n 8003098 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002fce: 68fb ldr r3, [r7, #12]
8002fd0: 681b ldr r3, [r3, #0]
8002fd2: 68b9 ldr r1, [r7, #8]
8002fd4: 4618 mov r0, r3
8002fd6: f000 fb05 bl 80035e4 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8002fda: 68fb ldr r3, [r7, #12]
8002fdc: 681b ldr r3, [r3, #0]
8002fde: 69da ldr r2, [r3, #28]
8002fe0: 68fb ldr r3, [r7, #12]
8002fe2: 681b ldr r3, [r3, #0]
8002fe4: f442 6200 orr.w r2, r2, #2048 ; 0x800
8002fe8: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8002fea: 68fb ldr r3, [r7, #12]
8002fec: 681b ldr r3, [r3, #0]
8002fee: 69da ldr r2, [r3, #28]
8002ff0: 68fb ldr r3, [r7, #12]
8002ff2: 681b ldr r3, [r3, #0]
8002ff4: f422 6280 bic.w r2, r2, #1024 ; 0x400
8002ff8: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8002ffa: 68fb ldr r3, [r7, #12]
8002ffc: 681b ldr r3, [r3, #0]
8002ffe: 69d9 ldr r1, [r3, #28]
8003000: 68bb ldr r3, [r7, #8]
8003002: 691b ldr r3, [r3, #16]
8003004: 021a lsls r2, r3, #8
8003006: 68fb ldr r3, [r7, #12]
8003008: 681b ldr r3, [r3, #0]
800300a: 430a orrs r2, r1
800300c: 61da str r2, [r3, #28]
break;
800300e: e043 b.n 8003098 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8003010: 68fb ldr r3, [r7, #12]
8003012: 681b ldr r3, [r3, #0]
8003014: 68b9 ldr r1, [r7, #8]
8003016: 4618 mov r0, r3
8003018: f000 fb42 bl 80036a0 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
800301c: 68fb ldr r3, [r7, #12]
800301e: 681b ldr r3, [r3, #0]
8003020: 6d5a ldr r2, [r3, #84] ; 0x54
8003022: 68fb ldr r3, [r7, #12]
8003024: 681b ldr r3, [r3, #0]
8003026: f042 0208 orr.w r2, r2, #8
800302a: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
800302c: 68fb ldr r3, [r7, #12]
800302e: 681b ldr r3, [r3, #0]
8003030: 6d5a ldr r2, [r3, #84] ; 0x54
8003032: 68fb ldr r3, [r7, #12]
8003034: 681b ldr r3, [r3, #0]
8003036: f022 0204 bic.w r2, r2, #4
800303a: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
800303c: 68fb ldr r3, [r7, #12]
800303e: 681b ldr r3, [r3, #0]
8003040: 6d59 ldr r1, [r3, #84] ; 0x54
8003042: 68bb ldr r3, [r7, #8]
8003044: 691a ldr r2, [r3, #16]
8003046: 68fb ldr r3, [r7, #12]
8003048: 681b ldr r3, [r3, #0]
800304a: 430a orrs r2, r1
800304c: 655a str r2, [r3, #84] ; 0x54
break;
800304e: e023 b.n 8003098 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8003050: 68fb ldr r3, [r7, #12]
8003052: 681b ldr r3, [r3, #0]
8003054: 68b9 ldr r1, [r7, #8]
8003056: 4618 mov r0, r3
8003058: f000 fb7a bl 8003750 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
800305c: 68fb ldr r3, [r7, #12]
800305e: 681b ldr r3, [r3, #0]
8003060: 6d5a ldr r2, [r3, #84] ; 0x54
8003062: 68fb ldr r3, [r7, #12]
8003064: 681b ldr r3, [r3, #0]
8003066: f442 6200 orr.w r2, r2, #2048 ; 0x800
800306a: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
800306c: 68fb ldr r3, [r7, #12]
800306e: 681b ldr r3, [r3, #0]
8003070: 6d5a ldr r2, [r3, #84] ; 0x54
8003072: 68fb ldr r3, [r7, #12]
8003074: 681b ldr r3, [r3, #0]
8003076: f422 6280 bic.w r2, r2, #1024 ; 0x400
800307a: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
800307c: 68fb ldr r3, [r7, #12]
800307e: 681b ldr r3, [r3, #0]
8003080: 6d59 ldr r1, [r3, #84] ; 0x54
8003082: 68bb ldr r3, [r7, #8]
8003084: 691b ldr r3, [r3, #16]
8003086: 021a lsls r2, r3, #8
8003088: 68fb ldr r3, [r7, #12]
800308a: 681b ldr r3, [r3, #0]
800308c: 430a orrs r2, r1
800308e: 655a str r2, [r3, #84] ; 0x54
break;
8003090: e002 b.n 8003098 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
8003092: 2301 movs r3, #1
8003094: 75fb strb r3, [r7, #23]
break;
8003096: bf00 nop
}
__HAL_UNLOCK(htim);
8003098: 68fb ldr r3, [r7, #12]
800309a: 2200 movs r2, #0
800309c: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
80030a0: 7dfb ldrb r3, [r7, #23]
}
80030a2: 4618 mov r0, r3
80030a4: 3718 adds r7, #24
80030a6: 46bd mov sp, r7
80030a8: bd80 pop {r7, pc}
80030aa: bf00 nop
080030ac <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
80030ac: b580 push {r7, lr}
80030ae: b084 sub sp, #16
80030b0: af00 add r7, sp, #0
80030b2: 6078 str r0, [r7, #4]
80030b4: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80030b6: 2300 movs r3, #0
80030b8: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80030ba: 687b ldr r3, [r7, #4]
80030bc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80030c0: 2b01 cmp r3, #1
80030c2: d101 bne.n 80030c8 <HAL_TIM_ConfigClockSource+0x1c>
80030c4: 2302 movs r3, #2
80030c6: e0b6 b.n 8003236 <HAL_TIM_ConfigClockSource+0x18a>
80030c8: 687b ldr r3, [r7, #4]
80030ca: 2201 movs r2, #1
80030cc: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
80030d0: 687b ldr r3, [r7, #4]
80030d2: 2202 movs r2, #2
80030d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80030d8: 687b ldr r3, [r7, #4]
80030da: 681b ldr r3, [r3, #0]
80030dc: 689b ldr r3, [r3, #8]
80030de: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80030e0: 68bb ldr r3, [r7, #8]
80030e2: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80030e6: f023 0377 bic.w r3, r3, #119 ; 0x77
80030ea: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80030ec: 68bb ldr r3, [r7, #8]
80030ee: f423 437f bic.w r3, r3, #65280 ; 0xff00
80030f2: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80030f4: 687b ldr r3, [r7, #4]
80030f6: 681b ldr r3, [r3, #0]
80030f8: 68ba ldr r2, [r7, #8]
80030fa: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80030fc: 683b ldr r3, [r7, #0]
80030fe: 681b ldr r3, [r3, #0]
8003100: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003104: d03e beq.n 8003184 <HAL_TIM_ConfigClockSource+0xd8>
8003106: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800310a: f200 8087 bhi.w 800321c <HAL_TIM_ConfigClockSource+0x170>
800310e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003112: f000 8086 beq.w 8003222 <HAL_TIM_ConfigClockSource+0x176>
8003116: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800311a: d87f bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
800311c: 2b70 cmp r3, #112 ; 0x70
800311e: d01a beq.n 8003156 <HAL_TIM_ConfigClockSource+0xaa>
8003120: 2b70 cmp r3, #112 ; 0x70
8003122: d87b bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
8003124: 2b60 cmp r3, #96 ; 0x60
8003126: d050 beq.n 80031ca <HAL_TIM_ConfigClockSource+0x11e>
8003128: 2b60 cmp r3, #96 ; 0x60
800312a: d877 bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
800312c: 2b50 cmp r3, #80 ; 0x50
800312e: d03c beq.n 80031aa <HAL_TIM_ConfigClockSource+0xfe>
8003130: 2b50 cmp r3, #80 ; 0x50
8003132: d873 bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
8003134: 2b40 cmp r3, #64 ; 0x40
8003136: d058 beq.n 80031ea <HAL_TIM_ConfigClockSource+0x13e>
8003138: 2b40 cmp r3, #64 ; 0x40
800313a: d86f bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
800313c: 2b30 cmp r3, #48 ; 0x30
800313e: d064 beq.n 800320a <HAL_TIM_ConfigClockSource+0x15e>
8003140: 2b30 cmp r3, #48 ; 0x30
8003142: d86b bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
8003144: 2b20 cmp r3, #32
8003146: d060 beq.n 800320a <HAL_TIM_ConfigClockSource+0x15e>
8003148: 2b20 cmp r3, #32
800314a: d867 bhi.n 800321c <HAL_TIM_ConfigClockSource+0x170>
800314c: 2b00 cmp r3, #0
800314e: d05c beq.n 800320a <HAL_TIM_ConfigClockSource+0x15e>
8003150: 2b10 cmp r3, #16
8003152: d05a beq.n 800320a <HAL_TIM_ConfigClockSource+0x15e>
8003154: e062 b.n 800321c <HAL_TIM_ConfigClockSource+0x170>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8003156: 687b ldr r3, [r7, #4]
8003158: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
800315a: 683b ldr r3, [r7, #0]
800315c: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800315e: 683b ldr r3, [r7, #0]
8003160: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8003162: 683b ldr r3, [r7, #0]
8003164: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8003166: f000 fbc7 bl 80038f8 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800316a: 687b ldr r3, [r7, #4]
800316c: 681b ldr r3, [r3, #0]
800316e: 689b ldr r3, [r3, #8]
8003170: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8003172: 68bb ldr r3, [r7, #8]
8003174: f043 0377 orr.w r3, r3, #119 ; 0x77
8003178: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800317a: 687b ldr r3, [r7, #4]
800317c: 681b ldr r3, [r3, #0]
800317e: 68ba ldr r2, [r7, #8]
8003180: 609a str r2, [r3, #8]
break;
8003182: e04f b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8003184: 687b ldr r3, [r7, #4]
8003186: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8003188: 683b ldr r3, [r7, #0]
800318a: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800318c: 683b ldr r3, [r7, #0]
800318e: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8003190: 683b ldr r3, [r7, #0]
8003192: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8003194: f000 fbb0 bl 80038f8 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8003198: 687b ldr r3, [r7, #4]
800319a: 681b ldr r3, [r3, #0]
800319c: 689a ldr r2, [r3, #8]
800319e: 687b ldr r3, [r7, #4]
80031a0: 681b ldr r3, [r3, #0]
80031a2: f442 4280 orr.w r2, r2, #16384 ; 0x4000
80031a6: 609a str r2, [r3, #8]
break;
80031a8: e03c b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80031aa: 687b ldr r3, [r7, #4]
80031ac: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80031ae: 683b ldr r3, [r7, #0]
80031b0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80031b2: 683b ldr r3, [r7, #0]
80031b4: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80031b6: 461a mov r2, r3
80031b8: f000 fb24 bl 8003804 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80031bc: 687b ldr r3, [r7, #4]
80031be: 681b ldr r3, [r3, #0]
80031c0: 2150 movs r1, #80 ; 0x50
80031c2: 4618 mov r0, r3
80031c4: f000 fb7d bl 80038c2 <TIM_ITRx_SetConfig>
break;
80031c8: e02c b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80031ca: 687b ldr r3, [r7, #4]
80031cc: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80031ce: 683b ldr r3, [r7, #0]
80031d0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80031d2: 683b ldr r3, [r7, #0]
80031d4: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
80031d6: 461a mov r2, r3
80031d8: f000 fb43 bl 8003862 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80031dc: 687b ldr r3, [r7, #4]
80031de: 681b ldr r3, [r3, #0]
80031e0: 2160 movs r1, #96 ; 0x60
80031e2: 4618 mov r0, r3
80031e4: f000 fb6d bl 80038c2 <TIM_ITRx_SetConfig>
break;
80031e8: e01c b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80031ea: 687b ldr r3, [r7, #4]
80031ec: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80031ee: 683b ldr r3, [r7, #0]
80031f0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80031f2: 683b ldr r3, [r7, #0]
80031f4: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80031f6: 461a mov r2, r3
80031f8: f000 fb04 bl 8003804 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80031fc: 687b ldr r3, [r7, #4]
80031fe: 681b ldr r3, [r3, #0]
8003200: 2140 movs r1, #64 ; 0x40
8003202: 4618 mov r0, r3
8003204: f000 fb5d bl 80038c2 <TIM_ITRx_SetConfig>
break;
8003208: e00c b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800320a: 687b ldr r3, [r7, #4]
800320c: 681a ldr r2, [r3, #0]
800320e: 683b ldr r3, [r7, #0]
8003210: 681b ldr r3, [r3, #0]
8003212: 4619 mov r1, r3
8003214: 4610 mov r0, r2
8003216: f000 fb54 bl 80038c2 <TIM_ITRx_SetConfig>
break;
800321a: e003 b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
}
default:
status = HAL_ERROR;
800321c: 2301 movs r3, #1
800321e: 73fb strb r3, [r7, #15]
break;
8003220: e000 b.n 8003224 <HAL_TIM_ConfigClockSource+0x178>
break;
8003222: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8003224: 687b ldr r3, [r7, #4]
8003226: 2201 movs r2, #1
8003228: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800322c: 687b ldr r3, [r7, #4]
800322e: 2200 movs r2, #0
8003230: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8003234: 7bfb ldrb r3, [r7, #15]
}
8003236: 4618 mov r0, r3
8003238: 3710 adds r7, #16
800323a: 46bd mov sp, r7
800323c: bd80 pop {r7, pc}
...
08003240 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8003240: b480 push {r7}
8003242: b085 sub sp, #20
8003244: af00 add r7, sp, #0
8003246: 6078 str r0, [r7, #4]
8003248: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800324a: 687b ldr r3, [r7, #4]
800324c: 681b ldr r3, [r3, #0]
800324e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003250: 687b ldr r3, [r7, #4]
8003252: 4a2a ldr r2, [pc, #168] ; (80032fc <TIM_Base_SetConfig+0xbc>)
8003254: 4293 cmp r3, r2
8003256: d003 beq.n 8003260 <TIM_Base_SetConfig+0x20>
8003258: 687b ldr r3, [r7, #4]
800325a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800325e: d108 bne.n 8003272 <TIM_Base_SetConfig+0x32>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8003260: 68fb ldr r3, [r7, #12]
8003262: f023 0370 bic.w r3, r3, #112 ; 0x70
8003266: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8003268: 683b ldr r3, [r7, #0]
800326a: 685b ldr r3, [r3, #4]
800326c: 68fa ldr r2, [r7, #12]
800326e: 4313 orrs r3, r2
8003270: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8003272: 687b ldr r3, [r7, #4]
8003274: 4a21 ldr r2, [pc, #132] ; (80032fc <TIM_Base_SetConfig+0xbc>)
8003276: 4293 cmp r3, r2
8003278: d00b beq.n 8003292 <TIM_Base_SetConfig+0x52>
800327a: 687b ldr r3, [r7, #4]
800327c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003280: d007 beq.n 8003292 <TIM_Base_SetConfig+0x52>
8003282: 687b ldr r3, [r7, #4]
8003284: 4a1e ldr r2, [pc, #120] ; (8003300 <TIM_Base_SetConfig+0xc0>)
8003286: 4293 cmp r3, r2
8003288: d003 beq.n 8003292 <TIM_Base_SetConfig+0x52>
800328a: 687b ldr r3, [r7, #4]
800328c: 4a1d ldr r2, [pc, #116] ; (8003304 <TIM_Base_SetConfig+0xc4>)
800328e: 4293 cmp r3, r2
8003290: d108 bne.n 80032a4 <TIM_Base_SetConfig+0x64>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003292: 68fb ldr r3, [r7, #12]
8003294: f423 7340 bic.w r3, r3, #768 ; 0x300
8003298: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800329a: 683b ldr r3, [r7, #0]
800329c: 68db ldr r3, [r3, #12]
800329e: 68fa ldr r2, [r7, #12]
80032a0: 4313 orrs r3, r2
80032a2: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80032a4: 68fb ldr r3, [r7, #12]
80032a6: f023 0280 bic.w r2, r3, #128 ; 0x80
80032aa: 683b ldr r3, [r7, #0]
80032ac: 695b ldr r3, [r3, #20]
80032ae: 4313 orrs r3, r2
80032b0: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80032b2: 687b ldr r3, [r7, #4]
80032b4: 68fa ldr r2, [r7, #12]
80032b6: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80032b8: 683b ldr r3, [r7, #0]
80032ba: 689a ldr r2, [r3, #8]
80032bc: 687b ldr r3, [r7, #4]
80032be: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80032c0: 683b ldr r3, [r7, #0]
80032c2: 681a ldr r2, [r3, #0]
80032c4: 687b ldr r3, [r7, #4]
80032c6: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80032c8: 687b ldr r3, [r7, #4]
80032ca: 4a0c ldr r2, [pc, #48] ; (80032fc <TIM_Base_SetConfig+0xbc>)
80032cc: 4293 cmp r3, r2
80032ce: d007 beq.n 80032e0 <TIM_Base_SetConfig+0xa0>
80032d0: 687b ldr r3, [r7, #4]
80032d2: 4a0b ldr r2, [pc, #44] ; (8003300 <TIM_Base_SetConfig+0xc0>)
80032d4: 4293 cmp r3, r2
80032d6: d003 beq.n 80032e0 <TIM_Base_SetConfig+0xa0>
80032d8: 687b ldr r3, [r7, #4]
80032da: 4a0a ldr r2, [pc, #40] ; (8003304 <TIM_Base_SetConfig+0xc4>)
80032dc: 4293 cmp r3, r2
80032de: d103 bne.n 80032e8 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80032e0: 683b ldr r3, [r7, #0]
80032e2: 691a ldr r2, [r3, #16]
80032e4: 687b ldr r3, [r7, #4]
80032e6: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80032e8: 687b ldr r3, [r7, #4]
80032ea: 2201 movs r2, #1
80032ec: 615a str r2, [r3, #20]
}
80032ee: bf00 nop
80032f0: 3714 adds r7, #20
80032f2: 46bd mov sp, r7
80032f4: f85d 7b04 ldr.w r7, [sp], #4
80032f8: 4770 bx lr
80032fa: bf00 nop
80032fc: 40012c00 .word 0x40012c00
8003300: 40014000 .word 0x40014000
8003304: 40014400 .word 0x40014400
08003308 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003308: b480 push {r7}
800330a: b087 sub sp, #28
800330c: af00 add r7, sp, #0
800330e: 6078 str r0, [r7, #4]
8003310: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003312: 687b ldr r3, [r7, #4]
8003314: 6a1b ldr r3, [r3, #32]
8003316: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8003318: 687b ldr r3, [r7, #4]
800331a: 6a1b ldr r3, [r3, #32]
800331c: f023 0201 bic.w r2, r3, #1
8003320: 687b ldr r3, [r7, #4]
8003322: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003324: 687b ldr r3, [r7, #4]
8003326: 685b ldr r3, [r3, #4]
8003328: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800332a: 687b ldr r3, [r7, #4]
800332c: 699b ldr r3, [r3, #24]
800332e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8003330: 68fb ldr r3, [r7, #12]
8003332: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8003336: f023 0370 bic.w r3, r3, #112 ; 0x70
800333a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800333c: 68fb ldr r3, [r7, #12]
800333e: f023 0303 bic.w r3, r3, #3
8003342: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003344: 683b ldr r3, [r7, #0]
8003346: 681b ldr r3, [r3, #0]
8003348: 68fa ldr r2, [r7, #12]
800334a: 4313 orrs r3, r2
800334c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800334e: 697b ldr r3, [r7, #20]
8003350: f023 0302 bic.w r3, r3, #2
8003354: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8003356: 683b ldr r3, [r7, #0]
8003358: 689b ldr r3, [r3, #8]
800335a: 697a ldr r2, [r7, #20]
800335c: 4313 orrs r3, r2
800335e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8003360: 687b ldr r3, [r7, #4]
8003362: 4a24 ldr r2, [pc, #144] ; (80033f4 <TIM_OC1_SetConfig+0xec>)
8003364: 4293 cmp r3, r2
8003366: d007 beq.n 8003378 <TIM_OC1_SetConfig+0x70>
8003368: 687b ldr r3, [r7, #4]
800336a: 4a23 ldr r2, [pc, #140] ; (80033f8 <TIM_OC1_SetConfig+0xf0>)
800336c: 4293 cmp r3, r2
800336e: d003 beq.n 8003378 <TIM_OC1_SetConfig+0x70>
8003370: 687b ldr r3, [r7, #4]
8003372: 4a22 ldr r2, [pc, #136] ; (80033fc <TIM_OC1_SetConfig+0xf4>)
8003374: 4293 cmp r3, r2
8003376: d10c bne.n 8003392 <TIM_OC1_SetConfig+0x8a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8003378: 697b ldr r3, [r7, #20]
800337a: f023 0308 bic.w r3, r3, #8
800337e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8003380: 683b ldr r3, [r7, #0]
8003382: 68db ldr r3, [r3, #12]
8003384: 697a ldr r2, [r7, #20]
8003386: 4313 orrs r3, r2
8003388: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800338a: 697b ldr r3, [r7, #20]
800338c: f023 0304 bic.w r3, r3, #4
8003390: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003392: 687b ldr r3, [r7, #4]
8003394: 4a17 ldr r2, [pc, #92] ; (80033f4 <TIM_OC1_SetConfig+0xec>)
8003396: 4293 cmp r3, r2
8003398: d007 beq.n 80033aa <TIM_OC1_SetConfig+0xa2>
800339a: 687b ldr r3, [r7, #4]
800339c: 4a16 ldr r2, [pc, #88] ; (80033f8 <TIM_OC1_SetConfig+0xf0>)
800339e: 4293 cmp r3, r2
80033a0: d003 beq.n 80033aa <TIM_OC1_SetConfig+0xa2>
80033a2: 687b ldr r3, [r7, #4]
80033a4: 4a15 ldr r2, [pc, #84] ; (80033fc <TIM_OC1_SetConfig+0xf4>)
80033a6: 4293 cmp r3, r2
80033a8: d111 bne.n 80033ce <TIM_OC1_SetConfig+0xc6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
80033aa: 693b ldr r3, [r7, #16]
80033ac: f423 7380 bic.w r3, r3, #256 ; 0x100
80033b0: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
80033b2: 693b ldr r3, [r7, #16]
80033b4: f423 7300 bic.w r3, r3, #512 ; 0x200
80033b8: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
80033ba: 683b ldr r3, [r7, #0]
80033bc: 695b ldr r3, [r3, #20]
80033be: 693a ldr r2, [r7, #16]
80033c0: 4313 orrs r3, r2
80033c2: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
80033c4: 683b ldr r3, [r7, #0]
80033c6: 699b ldr r3, [r3, #24]
80033c8: 693a ldr r2, [r7, #16]
80033ca: 4313 orrs r3, r2
80033cc: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80033ce: 687b ldr r3, [r7, #4]
80033d0: 693a ldr r2, [r7, #16]
80033d2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80033d4: 687b ldr r3, [r7, #4]
80033d6: 68fa ldr r2, [r7, #12]
80033d8: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80033da: 683b ldr r3, [r7, #0]
80033dc: 685a ldr r2, [r3, #4]
80033de: 687b ldr r3, [r7, #4]
80033e0: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80033e2: 687b ldr r3, [r7, #4]
80033e4: 697a ldr r2, [r7, #20]
80033e6: 621a str r2, [r3, #32]
}
80033e8: bf00 nop
80033ea: 371c adds r7, #28
80033ec: 46bd mov sp, r7
80033ee: f85d 7b04 ldr.w r7, [sp], #4
80033f2: 4770 bx lr
80033f4: 40012c00 .word 0x40012c00
80033f8: 40014000 .word 0x40014000
80033fc: 40014400 .word 0x40014400
08003400 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003400: b480 push {r7}
8003402: b087 sub sp, #28
8003404: af00 add r7, sp, #0
8003406: 6078 str r0, [r7, #4]
8003408: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800340a: 687b ldr r3, [r7, #4]
800340c: 6a1b ldr r3, [r3, #32]
800340e: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8003410: 687b ldr r3, [r7, #4]
8003412: 6a1b ldr r3, [r3, #32]
8003414: f023 0210 bic.w r2, r3, #16
8003418: 687b ldr r3, [r7, #4]
800341a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800341c: 687b ldr r3, [r7, #4]
800341e: 685b ldr r3, [r3, #4]
8003420: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003422: 687b ldr r3, [r7, #4]
8003424: 699b ldr r3, [r3, #24]
8003426: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8003428: 68fb ldr r3, [r7, #12]
800342a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
800342e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8003432: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8003434: 68fb ldr r3, [r7, #12]
8003436: f423 7340 bic.w r3, r3, #768 ; 0x300
800343a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800343c: 683b ldr r3, [r7, #0]
800343e: 681b ldr r3, [r3, #0]
8003440: 021b lsls r3, r3, #8
8003442: 68fa ldr r2, [r7, #12]
8003444: 4313 orrs r3, r2
8003446: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8003448: 697b ldr r3, [r7, #20]
800344a: f023 0320 bic.w r3, r3, #32
800344e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8003450: 683b ldr r3, [r7, #0]
8003452: 689b ldr r3, [r3, #8]
8003454: 011b lsls r3, r3, #4
8003456: 697a ldr r2, [r7, #20]
8003458: 4313 orrs r3, r2
800345a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800345c: 687b ldr r3, [r7, #4]
800345e: 4a22 ldr r2, [pc, #136] ; (80034e8 <TIM_OC2_SetConfig+0xe8>)
8003460: 4293 cmp r3, r2
8003462: d10d bne.n 8003480 <TIM_OC2_SetConfig+0x80>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8003464: 697b ldr r3, [r7, #20]
8003466: f023 0380 bic.w r3, r3, #128 ; 0x80
800346a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800346c: 683b ldr r3, [r7, #0]
800346e: 68db ldr r3, [r3, #12]
8003470: 011b lsls r3, r3, #4
8003472: 697a ldr r2, [r7, #20]
8003474: 4313 orrs r3, r2
8003476: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8003478: 697b ldr r3, [r7, #20]
800347a: f023 0340 bic.w r3, r3, #64 ; 0x40
800347e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003480: 687b ldr r3, [r7, #4]
8003482: 4a19 ldr r2, [pc, #100] ; (80034e8 <TIM_OC2_SetConfig+0xe8>)
8003484: 4293 cmp r3, r2
8003486: d007 beq.n 8003498 <TIM_OC2_SetConfig+0x98>
8003488: 687b ldr r3, [r7, #4]
800348a: 4a18 ldr r2, [pc, #96] ; (80034ec <TIM_OC2_SetConfig+0xec>)
800348c: 4293 cmp r3, r2
800348e: d003 beq.n 8003498 <TIM_OC2_SetConfig+0x98>
8003490: 687b ldr r3, [r7, #4]
8003492: 4a17 ldr r2, [pc, #92] ; (80034f0 <TIM_OC2_SetConfig+0xf0>)
8003494: 4293 cmp r3, r2
8003496: d113 bne.n 80034c0 <TIM_OC2_SetConfig+0xc0>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8003498: 693b ldr r3, [r7, #16]
800349a: f423 6380 bic.w r3, r3, #1024 ; 0x400
800349e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
80034a0: 693b ldr r3, [r7, #16]
80034a2: f423 6300 bic.w r3, r3, #2048 ; 0x800
80034a6: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
80034a8: 683b ldr r3, [r7, #0]
80034aa: 695b ldr r3, [r3, #20]
80034ac: 009b lsls r3, r3, #2
80034ae: 693a ldr r2, [r7, #16]
80034b0: 4313 orrs r3, r2
80034b2: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
80034b4: 683b ldr r3, [r7, #0]
80034b6: 699b ldr r3, [r3, #24]
80034b8: 009b lsls r3, r3, #2
80034ba: 693a ldr r2, [r7, #16]
80034bc: 4313 orrs r3, r2
80034be: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80034c0: 687b ldr r3, [r7, #4]
80034c2: 693a ldr r2, [r7, #16]
80034c4: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80034c6: 687b ldr r3, [r7, #4]
80034c8: 68fa ldr r2, [r7, #12]
80034ca: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
80034cc: 683b ldr r3, [r7, #0]
80034ce: 685a ldr r2, [r3, #4]
80034d0: 687b ldr r3, [r7, #4]
80034d2: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80034d4: 687b ldr r3, [r7, #4]
80034d6: 697a ldr r2, [r7, #20]
80034d8: 621a str r2, [r3, #32]
}
80034da: bf00 nop
80034dc: 371c adds r7, #28
80034de: 46bd mov sp, r7
80034e0: f85d 7b04 ldr.w r7, [sp], #4
80034e4: 4770 bx lr
80034e6: bf00 nop
80034e8: 40012c00 .word 0x40012c00
80034ec: 40014000 .word 0x40014000
80034f0: 40014400 .word 0x40014400
080034f4 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80034f4: b480 push {r7}
80034f6: b087 sub sp, #28
80034f8: af00 add r7, sp, #0
80034fa: 6078 str r0, [r7, #4]
80034fc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80034fe: 687b ldr r3, [r7, #4]
8003500: 6a1b ldr r3, [r3, #32]
8003502: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8003504: 687b ldr r3, [r7, #4]
8003506: 6a1b ldr r3, [r3, #32]
8003508: f423 7280 bic.w r2, r3, #256 ; 0x100
800350c: 687b ldr r3, [r7, #4]
800350e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003510: 687b ldr r3, [r7, #4]
8003512: 685b ldr r3, [r3, #4]
8003514: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8003516: 687b ldr r3, [r7, #4]
8003518: 69db ldr r3, [r3, #28]
800351a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800351c: 68fb ldr r3, [r7, #12]
800351e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8003522: f023 0370 bic.w r3, r3, #112 ; 0x70
8003526: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8003528: 68fb ldr r3, [r7, #12]
800352a: f023 0303 bic.w r3, r3, #3
800352e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003530: 683b ldr r3, [r7, #0]
8003532: 681b ldr r3, [r3, #0]
8003534: 68fa ldr r2, [r7, #12]
8003536: 4313 orrs r3, r2
8003538: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800353a: 697b ldr r3, [r7, #20]
800353c: f423 7300 bic.w r3, r3, #512 ; 0x200
8003540: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8003542: 683b ldr r3, [r7, #0]
8003544: 689b ldr r3, [r3, #8]
8003546: 021b lsls r3, r3, #8
8003548: 697a ldr r2, [r7, #20]
800354a: 4313 orrs r3, r2
800354c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800354e: 687b ldr r3, [r7, #4]
8003550: 4a21 ldr r2, [pc, #132] ; (80035d8 <TIM_OC3_SetConfig+0xe4>)
8003552: 4293 cmp r3, r2
8003554: d10d bne.n 8003572 <TIM_OC3_SetConfig+0x7e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8003556: 697b ldr r3, [r7, #20]
8003558: f423 6300 bic.w r3, r3, #2048 ; 0x800
800355c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800355e: 683b ldr r3, [r7, #0]
8003560: 68db ldr r3, [r3, #12]
8003562: 021b lsls r3, r3, #8
8003564: 697a ldr r2, [r7, #20]
8003566: 4313 orrs r3, r2
8003568: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800356a: 697b ldr r3, [r7, #20]
800356c: f423 6380 bic.w r3, r3, #1024 ; 0x400
8003570: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003572: 687b ldr r3, [r7, #4]
8003574: 4a18 ldr r2, [pc, #96] ; (80035d8 <TIM_OC3_SetConfig+0xe4>)
8003576: 4293 cmp r3, r2
8003578: d007 beq.n 800358a <TIM_OC3_SetConfig+0x96>
800357a: 687b ldr r3, [r7, #4]
800357c: 4a17 ldr r2, [pc, #92] ; (80035dc <TIM_OC3_SetConfig+0xe8>)
800357e: 4293 cmp r3, r2
8003580: d003 beq.n 800358a <TIM_OC3_SetConfig+0x96>
8003582: 687b ldr r3, [r7, #4]
8003584: 4a16 ldr r2, [pc, #88] ; (80035e0 <TIM_OC3_SetConfig+0xec>)
8003586: 4293 cmp r3, r2
8003588: d113 bne.n 80035b2 <TIM_OC3_SetConfig+0xbe>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800358a: 693b ldr r3, [r7, #16]
800358c: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8003590: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8003592: 693b ldr r3, [r7, #16]
8003594: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8003598: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800359a: 683b ldr r3, [r7, #0]
800359c: 695b ldr r3, [r3, #20]
800359e: 011b lsls r3, r3, #4
80035a0: 693a ldr r2, [r7, #16]
80035a2: 4313 orrs r3, r2
80035a4: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
80035a6: 683b ldr r3, [r7, #0]
80035a8: 699b ldr r3, [r3, #24]
80035aa: 011b lsls r3, r3, #4
80035ac: 693a ldr r2, [r7, #16]
80035ae: 4313 orrs r3, r2
80035b0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80035b2: 687b ldr r3, [r7, #4]
80035b4: 693a ldr r2, [r7, #16]
80035b6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80035b8: 687b ldr r3, [r7, #4]
80035ba: 68fa ldr r2, [r7, #12]
80035bc: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
80035be: 683b ldr r3, [r7, #0]
80035c0: 685a ldr r2, [r3, #4]
80035c2: 687b ldr r3, [r7, #4]
80035c4: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80035c6: 687b ldr r3, [r7, #4]
80035c8: 697a ldr r2, [r7, #20]
80035ca: 621a str r2, [r3, #32]
}
80035cc: bf00 nop
80035ce: 371c adds r7, #28
80035d0: 46bd mov sp, r7
80035d2: f85d 7b04 ldr.w r7, [sp], #4
80035d6: 4770 bx lr
80035d8: 40012c00 .word 0x40012c00
80035dc: 40014000 .word 0x40014000
80035e0: 40014400 .word 0x40014400
080035e4 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80035e4: b480 push {r7}
80035e6: b087 sub sp, #28
80035e8: af00 add r7, sp, #0
80035ea: 6078 str r0, [r7, #4]
80035ec: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80035ee: 687b ldr r3, [r7, #4]
80035f0: 6a1b ldr r3, [r3, #32]
80035f2: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
80035f4: 687b ldr r3, [r7, #4]
80035f6: 6a1b ldr r3, [r3, #32]
80035f8: f423 5280 bic.w r2, r3, #4096 ; 0x1000
80035fc: 687b ldr r3, [r7, #4]
80035fe: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003600: 687b ldr r3, [r7, #4]
8003602: 685b ldr r3, [r3, #4]
8003604: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8003606: 687b ldr r3, [r7, #4]
8003608: 69db ldr r3, [r3, #28]
800360a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800360c: 68fb ldr r3, [r7, #12]
800360e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8003612: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8003616: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8003618: 68fb ldr r3, [r7, #12]
800361a: f423 7340 bic.w r3, r3, #768 ; 0x300
800361e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003620: 683b ldr r3, [r7, #0]
8003622: 681b ldr r3, [r3, #0]
8003624: 021b lsls r3, r3, #8
8003626: 68fa ldr r2, [r7, #12]
8003628: 4313 orrs r3, r2
800362a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800362c: 693b ldr r3, [r7, #16]
800362e: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8003632: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8003634: 683b ldr r3, [r7, #0]
8003636: 689b ldr r3, [r3, #8]
8003638: 031b lsls r3, r3, #12
800363a: 693a ldr r2, [r7, #16]
800363c: 4313 orrs r3, r2
800363e: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003640: 687b ldr r3, [r7, #4]
8003642: 4a14 ldr r2, [pc, #80] ; (8003694 <TIM_OC4_SetConfig+0xb0>)
8003644: 4293 cmp r3, r2
8003646: d007 beq.n 8003658 <TIM_OC4_SetConfig+0x74>
8003648: 687b ldr r3, [r7, #4]
800364a: 4a13 ldr r2, [pc, #76] ; (8003698 <TIM_OC4_SetConfig+0xb4>)
800364c: 4293 cmp r3, r2
800364e: d003 beq.n 8003658 <TIM_OC4_SetConfig+0x74>
8003650: 687b ldr r3, [r7, #4]
8003652: 4a12 ldr r2, [pc, #72] ; (800369c <TIM_OC4_SetConfig+0xb8>)
8003654: 4293 cmp r3, r2
8003656: d109 bne.n 800366c <TIM_OC4_SetConfig+0x88>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8003658: 697b ldr r3, [r7, #20]
800365a: f423 4380 bic.w r3, r3, #16384 ; 0x4000
800365e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8003660: 683b ldr r3, [r7, #0]
8003662: 695b ldr r3, [r3, #20]
8003664: 019b lsls r3, r3, #6
8003666: 697a ldr r2, [r7, #20]
8003668: 4313 orrs r3, r2
800366a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800366c: 687b ldr r3, [r7, #4]
800366e: 697a ldr r2, [r7, #20]
8003670: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8003672: 687b ldr r3, [r7, #4]
8003674: 68fa ldr r2, [r7, #12]
8003676: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8003678: 683b ldr r3, [r7, #0]
800367a: 685a ldr r2, [r3, #4]
800367c: 687b ldr r3, [r7, #4]
800367e: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003680: 687b ldr r3, [r7, #4]
8003682: 693a ldr r2, [r7, #16]
8003684: 621a str r2, [r3, #32]
}
8003686: bf00 nop
8003688: 371c adds r7, #28
800368a: 46bd mov sp, r7
800368c: f85d 7b04 ldr.w r7, [sp], #4
8003690: 4770 bx lr
8003692: bf00 nop
8003694: 40012c00 .word 0x40012c00
8003698: 40014000 .word 0x40014000
800369c: 40014400 .word 0x40014400
080036a0 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80036a0: b480 push {r7}
80036a2: b087 sub sp, #28
80036a4: af00 add r7, sp, #0
80036a6: 6078 str r0, [r7, #4]
80036a8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80036aa: 687b ldr r3, [r7, #4]
80036ac: 6a1b ldr r3, [r3, #32]
80036ae: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
80036b0: 687b ldr r3, [r7, #4]
80036b2: 6a1b ldr r3, [r3, #32]
80036b4: f423 3280 bic.w r2, r3, #65536 ; 0x10000
80036b8: 687b ldr r3, [r7, #4]
80036ba: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80036bc: 687b ldr r3, [r7, #4]
80036be: 685b ldr r3, [r3, #4]
80036c0: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80036c2: 687b ldr r3, [r7, #4]
80036c4: 6d5b ldr r3, [r3, #84] ; 0x54
80036c6: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
80036c8: 68fb ldr r3, [r7, #12]
80036ca: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80036ce: f023 0370 bic.w r3, r3, #112 ; 0x70
80036d2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80036d4: 683b ldr r3, [r7, #0]
80036d6: 681b ldr r3, [r3, #0]
80036d8: 68fa ldr r2, [r7, #12]
80036da: 4313 orrs r3, r2
80036dc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
80036de: 693b ldr r3, [r7, #16]
80036e0: f423 3300 bic.w r3, r3, #131072 ; 0x20000
80036e4: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
80036e6: 683b ldr r3, [r7, #0]
80036e8: 689b ldr r3, [r3, #8]
80036ea: 041b lsls r3, r3, #16
80036ec: 693a ldr r2, [r7, #16]
80036ee: 4313 orrs r3, r2
80036f0: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80036f2: 687b ldr r3, [r7, #4]
80036f4: 4a13 ldr r2, [pc, #76] ; (8003744 <TIM_OC5_SetConfig+0xa4>)
80036f6: 4293 cmp r3, r2
80036f8: d007 beq.n 800370a <TIM_OC5_SetConfig+0x6a>
80036fa: 687b ldr r3, [r7, #4]
80036fc: 4a12 ldr r2, [pc, #72] ; (8003748 <TIM_OC5_SetConfig+0xa8>)
80036fe: 4293 cmp r3, r2
8003700: d003 beq.n 800370a <TIM_OC5_SetConfig+0x6a>
8003702: 687b ldr r3, [r7, #4]
8003704: 4a11 ldr r2, [pc, #68] ; (800374c <TIM_OC5_SetConfig+0xac>)
8003706: 4293 cmp r3, r2
8003708: d109 bne.n 800371e <TIM_OC5_SetConfig+0x7e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800370a: 697b ldr r3, [r7, #20]
800370c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8003710: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8003712: 683b ldr r3, [r7, #0]
8003714: 695b ldr r3, [r3, #20]
8003716: 021b lsls r3, r3, #8
8003718: 697a ldr r2, [r7, #20]
800371a: 4313 orrs r3, r2
800371c: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800371e: 687b ldr r3, [r7, #4]
8003720: 697a ldr r2, [r7, #20]
8003722: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8003724: 687b ldr r3, [r7, #4]
8003726: 68fa ldr r2, [r7, #12]
8003728: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800372a: 683b ldr r3, [r7, #0]
800372c: 685a ldr r2, [r3, #4]
800372e: 687b ldr r3, [r7, #4]
8003730: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003732: 687b ldr r3, [r7, #4]
8003734: 693a ldr r2, [r7, #16]
8003736: 621a str r2, [r3, #32]
}
8003738: bf00 nop
800373a: 371c adds r7, #28
800373c: 46bd mov sp, r7
800373e: f85d 7b04 ldr.w r7, [sp], #4
8003742: 4770 bx lr
8003744: 40012c00 .word 0x40012c00
8003748: 40014000 .word 0x40014000
800374c: 40014400 .word 0x40014400
08003750 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8003750: b480 push {r7}
8003752: b087 sub sp, #28
8003754: af00 add r7, sp, #0
8003756: 6078 str r0, [r7, #4]
8003758: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800375a: 687b ldr r3, [r7, #4]
800375c: 6a1b ldr r3, [r3, #32]
800375e: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8003760: 687b ldr r3, [r7, #4]
8003762: 6a1b ldr r3, [r3, #32]
8003764: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
8003768: 687b ldr r3, [r7, #4]
800376a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800376c: 687b ldr r3, [r7, #4]
800376e: 685b ldr r3, [r3, #4]
8003770: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8003772: 687b ldr r3, [r7, #4]
8003774: 6d5b ldr r3, [r3, #84] ; 0x54
8003776: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8003778: 68fb ldr r3, [r7, #12]
800377a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
800377e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8003782: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003784: 683b ldr r3, [r7, #0]
8003786: 681b ldr r3, [r3, #0]
8003788: 021b lsls r3, r3, #8
800378a: 68fa ldr r2, [r7, #12]
800378c: 4313 orrs r3, r2
800378e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8003790: 693b ldr r3, [r7, #16]
8003792: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
8003796: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8003798: 683b ldr r3, [r7, #0]
800379a: 689b ldr r3, [r3, #8]
800379c: 051b lsls r3, r3, #20
800379e: 693a ldr r2, [r7, #16]
80037a0: 4313 orrs r3, r2
80037a2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80037a4: 687b ldr r3, [r7, #4]
80037a6: 4a14 ldr r2, [pc, #80] ; (80037f8 <TIM_OC6_SetConfig+0xa8>)
80037a8: 4293 cmp r3, r2
80037aa: d007 beq.n 80037bc <TIM_OC6_SetConfig+0x6c>
80037ac: 687b ldr r3, [r7, #4]
80037ae: 4a13 ldr r2, [pc, #76] ; (80037fc <TIM_OC6_SetConfig+0xac>)
80037b0: 4293 cmp r3, r2
80037b2: d003 beq.n 80037bc <TIM_OC6_SetConfig+0x6c>
80037b4: 687b ldr r3, [r7, #4]
80037b6: 4a12 ldr r2, [pc, #72] ; (8003800 <TIM_OC6_SetConfig+0xb0>)
80037b8: 4293 cmp r3, r2
80037ba: d109 bne.n 80037d0 <TIM_OC6_SetConfig+0x80>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
80037bc: 697b ldr r3, [r7, #20]
80037be: f423 2380 bic.w r3, r3, #262144 ; 0x40000
80037c2: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
80037c4: 683b ldr r3, [r7, #0]
80037c6: 695b ldr r3, [r3, #20]
80037c8: 029b lsls r3, r3, #10
80037ca: 697a ldr r2, [r7, #20]
80037cc: 4313 orrs r3, r2
80037ce: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80037d0: 687b ldr r3, [r7, #4]
80037d2: 697a ldr r2, [r7, #20]
80037d4: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
80037d6: 687b ldr r3, [r7, #4]
80037d8: 68fa ldr r2, [r7, #12]
80037da: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
80037dc: 683b ldr r3, [r7, #0]
80037de: 685a ldr r2, [r3, #4]
80037e0: 687b ldr r3, [r7, #4]
80037e2: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80037e4: 687b ldr r3, [r7, #4]
80037e6: 693a ldr r2, [r7, #16]
80037e8: 621a str r2, [r3, #32]
}
80037ea: bf00 nop
80037ec: 371c adds r7, #28
80037ee: 46bd mov sp, r7
80037f0: f85d 7b04 ldr.w r7, [sp], #4
80037f4: 4770 bx lr
80037f6: bf00 nop
80037f8: 40012c00 .word 0x40012c00
80037fc: 40014000 .word 0x40014000
8003800: 40014400 .word 0x40014400
08003804 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003804: b480 push {r7}
8003806: b087 sub sp, #28
8003808: af00 add r7, sp, #0
800380a: 60f8 str r0, [r7, #12]
800380c: 60b9 str r1, [r7, #8]
800380e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8003810: 68fb ldr r3, [r7, #12]
8003812: 6a1b ldr r3, [r3, #32]
8003814: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8003816: 68fb ldr r3, [r7, #12]
8003818: 6a1b ldr r3, [r3, #32]
800381a: f023 0201 bic.w r2, r3, #1
800381e: 68fb ldr r3, [r7, #12]
8003820: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003822: 68fb ldr r3, [r7, #12]
8003824: 699b ldr r3, [r3, #24]
8003826: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8003828: 693b ldr r3, [r7, #16]
800382a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800382e: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8003830: 687b ldr r3, [r7, #4]
8003832: 011b lsls r3, r3, #4
8003834: 693a ldr r2, [r7, #16]
8003836: 4313 orrs r3, r2
8003838: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800383a: 697b ldr r3, [r7, #20]
800383c: f023 030a bic.w r3, r3, #10
8003840: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8003842: 697a ldr r2, [r7, #20]
8003844: 68bb ldr r3, [r7, #8]
8003846: 4313 orrs r3, r2
8003848: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800384a: 68fb ldr r3, [r7, #12]
800384c: 693a ldr r2, [r7, #16]
800384e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8003850: 68fb ldr r3, [r7, #12]
8003852: 697a ldr r2, [r7, #20]
8003854: 621a str r2, [r3, #32]
}
8003856: bf00 nop
8003858: 371c adds r7, #28
800385a: 46bd mov sp, r7
800385c: f85d 7b04 ldr.w r7, [sp], #4
8003860: 4770 bx lr
08003862 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003862: b480 push {r7}
8003864: b087 sub sp, #28
8003866: af00 add r7, sp, #0
8003868: 60f8 str r0, [r7, #12]
800386a: 60b9 str r1, [r7, #8]
800386c: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
800386e: 68fb ldr r3, [r7, #12]
8003870: 6a1b ldr r3, [r3, #32]
8003872: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8003874: 68fb ldr r3, [r7, #12]
8003876: 6a1b ldr r3, [r3, #32]
8003878: f023 0210 bic.w r2, r3, #16
800387c: 68fb ldr r3, [r7, #12]
800387e: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003880: 68fb ldr r3, [r7, #12]
8003882: 699b ldr r3, [r3, #24]
8003884: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8003886: 693b ldr r3, [r7, #16]
8003888: f423 4370 bic.w r3, r3, #61440 ; 0xf000
800388c: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
800388e: 687b ldr r3, [r7, #4]
8003890: 031b lsls r3, r3, #12
8003892: 693a ldr r2, [r7, #16]
8003894: 4313 orrs r3, r2
8003896: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8003898: 697b ldr r3, [r7, #20]
800389a: f023 03a0 bic.w r3, r3, #160 ; 0xa0
800389e: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
80038a0: 68bb ldr r3, [r7, #8]
80038a2: 011b lsls r3, r3, #4
80038a4: 697a ldr r2, [r7, #20]
80038a6: 4313 orrs r3, r2
80038a8: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80038aa: 68fb ldr r3, [r7, #12]
80038ac: 693a ldr r2, [r7, #16]
80038ae: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80038b0: 68fb ldr r3, [r7, #12]
80038b2: 697a ldr r2, [r7, #20]
80038b4: 621a str r2, [r3, #32]
}
80038b6: bf00 nop
80038b8: 371c adds r7, #28
80038ba: 46bd mov sp, r7
80038bc: f85d 7b04 ldr.w r7, [sp], #4
80038c0: 4770 bx lr
080038c2 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80038c2: b480 push {r7}
80038c4: b085 sub sp, #20
80038c6: af00 add r7, sp, #0
80038c8: 6078 str r0, [r7, #4]
80038ca: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80038cc: 687b ldr r3, [r7, #4]
80038ce: 689b ldr r3, [r3, #8]
80038d0: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80038d2: 68fb ldr r3, [r7, #12]
80038d4: f023 0370 bic.w r3, r3, #112 ; 0x70
80038d8: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80038da: 683a ldr r2, [r7, #0]
80038dc: 68fb ldr r3, [r7, #12]
80038de: 4313 orrs r3, r2
80038e0: f043 0307 orr.w r3, r3, #7
80038e4: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80038e6: 687b ldr r3, [r7, #4]
80038e8: 68fa ldr r2, [r7, #12]
80038ea: 609a str r2, [r3, #8]
}
80038ec: bf00 nop
80038ee: 3714 adds r7, #20
80038f0: 46bd mov sp, r7
80038f2: f85d 7b04 ldr.w r7, [sp], #4
80038f6: 4770 bx lr
080038f8 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
80038f8: b480 push {r7}
80038fa: b087 sub sp, #28
80038fc: af00 add r7, sp, #0
80038fe: 60f8 str r0, [r7, #12]
8003900: 60b9 str r1, [r7, #8]
8003902: 607a str r2, [r7, #4]
8003904: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8003906: 68fb ldr r3, [r7, #12]
8003908: 689b ldr r3, [r3, #8]
800390a: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800390c: 697b ldr r3, [r7, #20]
800390e: f423 437f bic.w r3, r3, #65280 ; 0xff00
8003912: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8003914: 683b ldr r3, [r7, #0]
8003916: 021a lsls r2, r3, #8
8003918: 687b ldr r3, [r7, #4]
800391a: 431a orrs r2, r3
800391c: 68bb ldr r3, [r7, #8]
800391e: 4313 orrs r3, r2
8003920: 697a ldr r2, [r7, #20]
8003922: 4313 orrs r3, r2
8003924: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003926: 68fb ldr r3, [r7, #12]
8003928: 697a ldr r2, [r7, #20]
800392a: 609a str r2, [r3, #8]
}
800392c: bf00 nop
800392e: 371c adds r7, #28
8003930: 46bd mov sp, r7
8003932: f85d 7b04 ldr.w r7, [sp], #4
8003936: 4770 bx lr
08003938 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8003938: b480 push {r7}
800393a: b087 sub sp, #28
800393c: af00 add r7, sp, #0
800393e: 60f8 str r0, [r7, #12]
8003940: 60b9 str r1, [r7, #8]
8003942: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8003944: 68bb ldr r3, [r7, #8]
8003946: f003 031f and.w r3, r3, #31
800394a: 2201 movs r2, #1
800394c: fa02 f303 lsl.w r3, r2, r3
8003950: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8003952: 68fb ldr r3, [r7, #12]
8003954: 6a1a ldr r2, [r3, #32]
8003956: 697b ldr r3, [r7, #20]
8003958: 43db mvns r3, r3
800395a: 401a ands r2, r3
800395c: 68fb ldr r3, [r7, #12]
800395e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8003960: 68fb ldr r3, [r7, #12]
8003962: 6a1a ldr r2, [r3, #32]
8003964: 68bb ldr r3, [r7, #8]
8003966: f003 031f and.w r3, r3, #31
800396a: 6879 ldr r1, [r7, #4]
800396c: fa01 f303 lsl.w r3, r1, r3
8003970: 431a orrs r2, r3
8003972: 68fb ldr r3, [r7, #12]
8003974: 621a str r2, [r3, #32]
}
8003976: bf00 nop
8003978: 371c adds r7, #28
800397a: 46bd mov sp, r7
800397c: f85d 7b04 ldr.w r7, [sp], #4
8003980: 4770 bx lr
...
08003984 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8003984: b480 push {r7}
8003986: b085 sub sp, #20
8003988: af00 add r7, sp, #0
800398a: 6078 str r0, [r7, #4]
800398c: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800398e: 687b ldr r3, [r7, #4]
8003990: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003994: 2b01 cmp r3, #1
8003996: d101 bne.n 800399c <HAL_TIMEx_MasterConfigSynchronization+0x18>
8003998: 2302 movs r3, #2
800399a: e04f b.n 8003a3c <HAL_TIMEx_MasterConfigSynchronization+0xb8>
800399c: 687b ldr r3, [r7, #4]
800399e: 2201 movs r2, #1
80039a0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80039a4: 687b ldr r3, [r7, #4]
80039a6: 2202 movs r2, #2
80039a8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80039ac: 687b ldr r3, [r7, #4]
80039ae: 681b ldr r3, [r3, #0]
80039b0: 685b ldr r3, [r3, #4]
80039b2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80039b4: 687b ldr r3, [r7, #4]
80039b6: 681b ldr r3, [r3, #0]
80039b8: 689b ldr r3, [r3, #8]
80039ba: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80039bc: 687b ldr r3, [r7, #4]
80039be: 681b ldr r3, [r3, #0]
80039c0: 4a21 ldr r2, [pc, #132] ; (8003a48 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
80039c2: 4293 cmp r3, r2
80039c4: d108 bne.n 80039d8 <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
80039c6: 68fb ldr r3, [r7, #12]
80039c8: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
80039cc: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
80039ce: 683b ldr r3, [r7, #0]
80039d0: 685b ldr r3, [r3, #4]
80039d2: 68fa ldr r2, [r7, #12]
80039d4: 4313 orrs r3, r2
80039d6: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80039d8: 68fb ldr r3, [r7, #12]
80039da: f023 0370 bic.w r3, r3, #112 ; 0x70
80039de: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80039e0: 683b ldr r3, [r7, #0]
80039e2: 681b ldr r3, [r3, #0]
80039e4: 68fa ldr r2, [r7, #12]
80039e6: 4313 orrs r3, r2
80039e8: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80039ea: 687b ldr r3, [r7, #4]
80039ec: 681b ldr r3, [r3, #0]
80039ee: 68fa ldr r2, [r7, #12]
80039f0: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80039f2: 687b ldr r3, [r7, #4]
80039f4: 681b ldr r3, [r3, #0]
80039f6: 4a14 ldr r2, [pc, #80] ; (8003a48 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
80039f8: 4293 cmp r3, r2
80039fa: d009 beq.n 8003a10 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
80039fc: 687b ldr r3, [r7, #4]
80039fe: 681b ldr r3, [r3, #0]
8003a00: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003a04: d004 beq.n 8003a10 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
8003a06: 687b ldr r3, [r7, #4]
8003a08: 681b ldr r3, [r3, #0]
8003a0a: 4a10 ldr r2, [pc, #64] ; (8003a4c <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
8003a0c: 4293 cmp r3, r2
8003a0e: d10c bne.n 8003a2a <HAL_TIMEx_MasterConfigSynchronization+0xa6>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8003a10: 68bb ldr r3, [r7, #8]
8003a12: f023 0380 bic.w r3, r3, #128 ; 0x80
8003a16: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8003a18: 683b ldr r3, [r7, #0]
8003a1a: 689b ldr r3, [r3, #8]
8003a1c: 68ba ldr r2, [r7, #8]
8003a1e: 4313 orrs r3, r2
8003a20: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8003a22: 687b ldr r3, [r7, #4]
8003a24: 681b ldr r3, [r3, #0]
8003a26: 68ba ldr r2, [r7, #8]
8003a28: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8003a2a: 687b ldr r3, [r7, #4]
8003a2c: 2201 movs r2, #1
8003a2e: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8003a32: 687b ldr r3, [r7, #4]
8003a34: 2200 movs r2, #0
8003a36: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003a3a: 2300 movs r3, #0
}
8003a3c: 4618 mov r0, r3
8003a3e: 3714 adds r7, #20
8003a40: 46bd mov sp, r7
8003a42: f85d 7b04 ldr.w r7, [sp], #4
8003a46: 4770 bx lr
8003a48: 40012c00 .word 0x40012c00
8003a4c: 40014000 .word 0x40014000
08003a50 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8003a50: b480 push {r7}
8003a52: b085 sub sp, #20
8003a54: af00 add r7, sp, #0
8003a56: 6078 str r0, [r7, #4]
8003a58: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8003a5a: 2300 movs r3, #0
8003a5c: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8003a5e: 687b ldr r3, [r7, #4]
8003a60: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003a64: 2b01 cmp r3, #1
8003a66: d101 bne.n 8003a6c <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8003a68: 2302 movs r3, #2
8003a6a: e060 b.n 8003b2e <HAL_TIMEx_ConfigBreakDeadTime+0xde>
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 2201 movs r2, #1
8003a70: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8003a74: 68fb ldr r3, [r7, #12]
8003a76: f023 02ff bic.w r2, r3, #255 ; 0xff
8003a7a: 683b ldr r3, [r7, #0]
8003a7c: 68db ldr r3, [r3, #12]
8003a7e: 4313 orrs r3, r2
8003a80: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8003a82: 68fb ldr r3, [r7, #12]
8003a84: f423 7240 bic.w r2, r3, #768 ; 0x300
8003a88: 683b ldr r3, [r7, #0]
8003a8a: 689b ldr r3, [r3, #8]
8003a8c: 4313 orrs r3, r2
8003a8e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8003a90: 68fb ldr r3, [r7, #12]
8003a92: f423 6280 bic.w r2, r3, #1024 ; 0x400
8003a96: 683b ldr r3, [r7, #0]
8003a98: 685b ldr r3, [r3, #4]
8003a9a: 4313 orrs r3, r2
8003a9c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8003a9e: 68fb ldr r3, [r7, #12]
8003aa0: f423 6200 bic.w r2, r3, #2048 ; 0x800
8003aa4: 683b ldr r3, [r7, #0]
8003aa6: 681b ldr r3, [r3, #0]
8003aa8: 4313 orrs r3, r2
8003aaa: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8003aac: 68fb ldr r3, [r7, #12]
8003aae: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8003ab2: 683b ldr r3, [r7, #0]
8003ab4: 691b ldr r3, [r3, #16]
8003ab6: 4313 orrs r3, r2
8003ab8: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8003aba: 68fb ldr r3, [r7, #12]
8003abc: f423 5200 bic.w r2, r3, #8192 ; 0x2000
8003ac0: 683b ldr r3, [r7, #0]
8003ac2: 695b ldr r3, [r3, #20]
8003ac4: 4313 orrs r3, r2
8003ac6: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8003ac8: 68fb ldr r3, [r7, #12]
8003aca: f423 4280 bic.w r2, r3, #16384 ; 0x4000
8003ace: 683b ldr r3, [r7, #0]
8003ad0: 6a9b ldr r3, [r3, #40] ; 0x28
8003ad2: 4313 orrs r3, r2
8003ad4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
8003ad6: 68fb ldr r3, [r7, #12]
8003ad8: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
8003adc: 683b ldr r3, [r7, #0]
8003ade: 699b ldr r3, [r3, #24]
8003ae0: 041b lsls r3, r3, #16
8003ae2: 4313 orrs r3, r2
8003ae4: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
8003ae6: 687b ldr r3, [r7, #4]
8003ae8: 681b ldr r3, [r3, #0]
8003aea: 4a14 ldr r2, [pc, #80] ; (8003b3c <HAL_TIMEx_ConfigBreakDeadTime+0xec>)
8003aec: 4293 cmp r3, r2
8003aee: d115 bne.n 8003b1c <HAL_TIMEx_ConfigBreakDeadTime+0xcc>
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
8003af0: 68fb ldr r3, [r7, #12]
8003af2: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
8003af6: 683b ldr r3, [r7, #0]
8003af8: 6a5b ldr r3, [r3, #36] ; 0x24
8003afa: 051b lsls r3, r3, #20
8003afc: 4313 orrs r3, r2
8003afe: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
8003b00: 68fb ldr r3, [r7, #12]
8003b02: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
8003b06: 683b ldr r3, [r7, #0]
8003b08: 69db ldr r3, [r3, #28]
8003b0a: 4313 orrs r3, r2
8003b0c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
8003b0e: 68fb ldr r3, [r7, #12]
8003b10: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
8003b14: 683b ldr r3, [r7, #0]
8003b16: 6a1b ldr r3, [r3, #32]
8003b18: 4313 orrs r3, r2
8003b1a: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8003b1c: 687b ldr r3, [r7, #4]
8003b1e: 681b ldr r3, [r3, #0]
8003b20: 68fa ldr r2, [r7, #12]
8003b22: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
8003b24: 687b ldr r3, [r7, #4]
8003b26: 2200 movs r2, #0
8003b28: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003b2c: 2300 movs r3, #0
}
8003b2e: 4618 mov r0, r3
8003b30: 3714 adds r7, #20
8003b32: 46bd mov sp, r7
8003b34: f85d 7b04 ldr.w r7, [sp], #4
8003b38: 4770 bx lr
8003b3a: bf00 nop
8003b3c: 40012c00 .word 0x40012c00
08003b40 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8003b40: b580 push {r7, lr}
8003b42: b082 sub sp, #8
8003b44: af00 add r7, sp, #0
8003b46: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 2b00 cmp r3, #0
8003b4c: d101 bne.n 8003b52 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8003b4e: 2301 movs r3, #1
8003b50: e040 b.n 8003bd4 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
8003b52: 687b ldr r3, [r7, #4]
8003b54: 6fdb ldr r3, [r3, #124] ; 0x7c
8003b56: 2b00 cmp r3, #0
8003b58: d106 bne.n 8003b68 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8003b5a: 687b ldr r3, [r7, #4]
8003b5c: 2200 movs r2, #0
8003b5e: f883 2078 strb.w r2, [r3, #120] ; 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8003b62: 6878 ldr r0, [r7, #4]
8003b64: f7fd f82e bl 8000bc4 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8003b68: 687b ldr r3, [r7, #4]
8003b6a: 2224 movs r2, #36 ; 0x24
8003b6c: 67da str r2, [r3, #124] ; 0x7c
__HAL_UART_DISABLE(huart);
8003b6e: 687b ldr r3, [r7, #4]
8003b70: 681b ldr r3, [r3, #0]
8003b72: 681a ldr r2, [r3, #0]
8003b74: 687b ldr r3, [r7, #4]
8003b76: 681b ldr r3, [r3, #0]
8003b78: f022 0201 bic.w r2, r2, #1
8003b7c: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8003b7e: 687b ldr r3, [r7, #4]
8003b80: 6a5b ldr r3, [r3, #36] ; 0x24
8003b82: 2b00 cmp r3, #0
8003b84: d002 beq.n 8003b8c <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
8003b86: 6878 ldr r0, [r7, #4]
8003b88: f000 feb4 bl 80048f4 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8003b8c: 6878 ldr r0, [r7, #4]
8003b8e: f000 fc57 bl 8004440 <UART_SetConfig>
8003b92: 4603 mov r3, r0
8003b94: 2b01 cmp r3, #1
8003b96: d101 bne.n 8003b9c <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
8003b98: 2301 movs r3, #1
8003b9a: e01b b.n 8003bd4 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8003b9c: 687b ldr r3, [r7, #4]
8003b9e: 681b ldr r3, [r3, #0]
8003ba0: 685a ldr r2, [r3, #4]
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 681b ldr r3, [r3, #0]
8003ba6: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8003baa: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8003bac: 687b ldr r3, [r7, #4]
8003bae: 681b ldr r3, [r3, #0]
8003bb0: 689a ldr r2, [r3, #8]
8003bb2: 687b ldr r3, [r7, #4]
8003bb4: 681b ldr r3, [r3, #0]
8003bb6: f022 022a bic.w r2, r2, #42 ; 0x2a
8003bba: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8003bbc: 687b ldr r3, [r7, #4]
8003bbe: 681b ldr r3, [r3, #0]
8003bc0: 681a ldr r2, [r3, #0]
8003bc2: 687b ldr r3, [r7, #4]
8003bc4: 681b ldr r3, [r3, #0]
8003bc6: f042 0201 orr.w r2, r2, #1
8003bca: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8003bcc: 6878 ldr r0, [r7, #4]
8003bce: f000 ff33 bl 8004a38 <UART_CheckIdleState>
8003bd2: 4603 mov r3, r0
}
8003bd4: 4618 mov r0, r3
8003bd6: 3708 adds r7, #8
8003bd8: 46bd mov sp, r7
8003bda: bd80 pop {r7, pc}
08003bdc <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003bdc: b580 push {r7, lr}
8003bde: b08a sub sp, #40 ; 0x28
8003be0: af02 add r7, sp, #8
8003be2: 60f8 str r0, [r7, #12]
8003be4: 60b9 str r1, [r7, #8]
8003be6: 603b str r3, [r7, #0]
8003be8: 4613 mov r3, r2
8003bea: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8003bec: 68fb ldr r3, [r7, #12]
8003bee: 6fdb ldr r3, [r3, #124] ; 0x7c
8003bf0: 2b20 cmp r3, #32
8003bf2: d178 bne.n 8003ce6 <HAL_UART_Transmit+0x10a>
{
if ((pData == NULL) || (Size == 0U))
8003bf4: 68bb ldr r3, [r7, #8]
8003bf6: 2b00 cmp r3, #0
8003bf8: d002 beq.n 8003c00 <HAL_UART_Transmit+0x24>
8003bfa: 88fb ldrh r3, [r7, #6]
8003bfc: 2b00 cmp r3, #0
8003bfe: d101 bne.n 8003c04 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
8003c00: 2301 movs r3, #1
8003c02: e071 b.n 8003ce8 <HAL_UART_Transmit+0x10c>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003c04: 68fb ldr r3, [r7, #12]
8003c06: 2200 movs r2, #0
8003c08: f8c3 2084 str.w r2, [r3, #132] ; 0x84
huart->gState = HAL_UART_STATE_BUSY_TX;
8003c0c: 68fb ldr r3, [r7, #12]
8003c0e: 2221 movs r2, #33 ; 0x21
8003c10: 67da str r2, [r3, #124] ; 0x7c
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003c12: f7fd faa9 bl 8001168 <HAL_GetTick>
8003c16: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8003c18: 68fb ldr r3, [r7, #12]
8003c1a: 88fa ldrh r2, [r7, #6]
8003c1c: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
huart->TxXferCount = Size;
8003c20: 68fb ldr r3, [r7, #12]
8003c22: 88fa ldrh r2, [r7, #6]
8003c24: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8003c28: 68fb ldr r3, [r7, #12]
8003c2a: 689b ldr r3, [r3, #8]
8003c2c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003c30: d108 bne.n 8003c44 <HAL_UART_Transmit+0x68>
8003c32: 68fb ldr r3, [r7, #12]
8003c34: 691b ldr r3, [r3, #16]
8003c36: 2b00 cmp r3, #0
8003c38: d104 bne.n 8003c44 <HAL_UART_Transmit+0x68>
{
pdata8bits = NULL;
8003c3a: 2300 movs r3, #0
8003c3c: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8003c3e: 68bb ldr r3, [r7, #8]
8003c40: 61bb str r3, [r7, #24]
8003c42: e003 b.n 8003c4c <HAL_UART_Transmit+0x70>
}
else
{
pdata8bits = pData;
8003c44: 68bb ldr r3, [r7, #8]
8003c46: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8003c48: 2300 movs r3, #0
8003c4a: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8003c4c: e030 b.n 8003cb0 <HAL_UART_Transmit+0xd4>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8003c4e: 683b ldr r3, [r7, #0]
8003c50: 9300 str r3, [sp, #0]
8003c52: 697b ldr r3, [r7, #20]
8003c54: 2200 movs r2, #0
8003c56: 2180 movs r1, #128 ; 0x80
8003c58: 68f8 ldr r0, [r7, #12]
8003c5a: f000 ff95 bl 8004b88 <UART_WaitOnFlagUntilTimeout>
8003c5e: 4603 mov r3, r0
8003c60: 2b00 cmp r3, #0
8003c62: d004 beq.n 8003c6e <HAL_UART_Transmit+0x92>
{
huart->gState = HAL_UART_STATE_READY;
8003c64: 68fb ldr r3, [r7, #12]
8003c66: 2220 movs r2, #32
8003c68: 67da str r2, [r3, #124] ; 0x7c
return HAL_TIMEOUT;
8003c6a: 2303 movs r3, #3
8003c6c: e03c b.n 8003ce8 <HAL_UART_Transmit+0x10c>
}
if (pdata8bits == NULL)
8003c6e: 69fb ldr r3, [r7, #28]
8003c70: 2b00 cmp r3, #0
8003c72: d10b bne.n 8003c8c <HAL_UART_Transmit+0xb0>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8003c74: 69bb ldr r3, [r7, #24]
8003c76: 881a ldrh r2, [r3, #0]
8003c78: 68fb ldr r3, [r7, #12]
8003c7a: 681b ldr r3, [r3, #0]
8003c7c: f3c2 0208 ubfx r2, r2, #0, #9
8003c80: b292 uxth r2, r2
8003c82: 851a strh r2, [r3, #40] ; 0x28
pdata16bits++;
8003c84: 69bb ldr r3, [r7, #24]
8003c86: 3302 adds r3, #2
8003c88: 61bb str r3, [r7, #24]
8003c8a: e008 b.n 8003c9e <HAL_UART_Transmit+0xc2>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8003c8c: 69fb ldr r3, [r7, #28]
8003c8e: 781a ldrb r2, [r3, #0]
8003c90: 68fb ldr r3, [r7, #12]
8003c92: 681b ldr r3, [r3, #0]
8003c94: b292 uxth r2, r2
8003c96: 851a strh r2, [r3, #40] ; 0x28
pdata8bits++;
8003c98: 69fb ldr r3, [r7, #28]
8003c9a: 3301 adds r3, #1
8003c9c: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8003c9e: 68fb ldr r3, [r7, #12]
8003ca0: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8003ca4: b29b uxth r3, r3
8003ca6: 3b01 subs r3, #1
8003ca8: b29a uxth r2, r3
8003caa: 68fb ldr r3, [r7, #12]
8003cac: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
while (huart->TxXferCount > 0U)
8003cb0: 68fb ldr r3, [r7, #12]
8003cb2: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8003cb6: b29b uxth r3, r3
8003cb8: 2b00 cmp r3, #0
8003cba: d1c8 bne.n 8003c4e <HAL_UART_Transmit+0x72>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8003cbc: 683b ldr r3, [r7, #0]
8003cbe: 9300 str r3, [sp, #0]
8003cc0: 697b ldr r3, [r7, #20]
8003cc2: 2200 movs r2, #0
8003cc4: 2140 movs r1, #64 ; 0x40
8003cc6: 68f8 ldr r0, [r7, #12]
8003cc8: f000 ff5e bl 8004b88 <UART_WaitOnFlagUntilTimeout>
8003ccc: 4603 mov r3, r0
8003cce: 2b00 cmp r3, #0
8003cd0: d004 beq.n 8003cdc <HAL_UART_Transmit+0x100>
{
huart->gState = HAL_UART_STATE_READY;
8003cd2: 68fb ldr r3, [r7, #12]
8003cd4: 2220 movs r2, #32
8003cd6: 67da str r2, [r3, #124] ; 0x7c
return HAL_TIMEOUT;
8003cd8: 2303 movs r3, #3
8003cda: e005 b.n 8003ce8 <HAL_UART_Transmit+0x10c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8003cdc: 68fb ldr r3, [r7, #12]
8003cde: 2220 movs r2, #32
8003ce0: 67da str r2, [r3, #124] ; 0x7c
return HAL_OK;
8003ce2: 2300 movs r3, #0
8003ce4: e000 b.n 8003ce8 <HAL_UART_Transmit+0x10c>
}
else
{
return HAL_BUSY;
8003ce6: 2302 movs r3, #2
}
}
8003ce8: 4618 mov r0, r3
8003cea: 3720 adds r7, #32
8003cec: 46bd mov sp, r7
8003cee: bd80 pop {r7, pc}
08003cf0 <HAL_UART_Transmit_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
8003cf0: b480 push {r7}
8003cf2: b08b sub sp, #44 ; 0x2c
8003cf4: af00 add r7, sp, #0
8003cf6: 60f8 str r0, [r7, #12]
8003cf8: 60b9 str r1, [r7, #8]
8003cfa: 4613 mov r3, r2
8003cfc: 80fb strh r3, [r7, #6]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8003cfe: 68fb ldr r3, [r7, #12]
8003d00: 6fdb ldr r3, [r3, #124] ; 0x7c
8003d02: 2b20 cmp r3, #32
8003d04: d147 bne.n 8003d96 <HAL_UART_Transmit_IT+0xa6>
{
if ((pData == NULL) || (Size == 0U))
8003d06: 68bb ldr r3, [r7, #8]
8003d08: 2b00 cmp r3, #0
8003d0a: d002 beq.n 8003d12 <HAL_UART_Transmit_IT+0x22>
8003d0c: 88fb ldrh r3, [r7, #6]
8003d0e: 2b00 cmp r3, #0
8003d10: d101 bne.n 8003d16 <HAL_UART_Transmit_IT+0x26>
{
return HAL_ERROR;
8003d12: 2301 movs r3, #1
8003d14: e040 b.n 8003d98 <HAL_UART_Transmit_IT+0xa8>
}
huart->pTxBuffPtr = pData;
8003d16: 68fb ldr r3, [r7, #12]
8003d18: 68ba ldr r2, [r7, #8]
8003d1a: 64da str r2, [r3, #76] ; 0x4c
huart->TxXferSize = Size;
8003d1c: 68fb ldr r3, [r7, #12]
8003d1e: 88fa ldrh r2, [r7, #6]
8003d20: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
huart->TxXferCount = Size;
8003d24: 68fb ldr r3, [r7, #12]
8003d26: 88fa ldrh r2, [r7, #6]
8003d28: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
huart->TxISR = NULL;
8003d2c: 68fb ldr r3, [r7, #12]
8003d2e: 2200 movs r2, #0
8003d30: 66da str r2, [r3, #108] ; 0x6c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003d32: 68fb ldr r3, [r7, #12]
8003d34: 2200 movs r2, #0
8003d36: f8c3 2084 str.w r2, [r3, #132] ; 0x84
huart->gState = HAL_UART_STATE_BUSY_TX;
8003d3a: 68fb ldr r3, [r7, #12]
8003d3c: 2221 movs r2, #33 ; 0x21
8003d3e: 67da str r2, [r3, #124] ; 0x7c
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
#else
/* Set the Tx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8003d40: 68fb ldr r3, [r7, #12]
8003d42: 689b ldr r3, [r3, #8]
8003d44: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003d48: d107 bne.n 8003d5a <HAL_UART_Transmit_IT+0x6a>
8003d4a: 68fb ldr r3, [r7, #12]
8003d4c: 691b ldr r3, [r3, #16]
8003d4e: 2b00 cmp r3, #0
8003d50: d103 bne.n 8003d5a <HAL_UART_Transmit_IT+0x6a>
{
huart->TxISR = UART_TxISR_16BIT;
8003d52: 68fb ldr r3, [r7, #12]
8003d54: 4a13 ldr r2, [pc, #76] ; (8003da4 <HAL_UART_Transmit_IT+0xb4>)
8003d56: 66da str r2, [r3, #108] ; 0x6c
8003d58: e002 b.n 8003d60 <HAL_UART_Transmit_IT+0x70>
}
else
{
huart->TxISR = UART_TxISR_8BIT;
8003d5a: 68fb ldr r3, [r7, #12]
8003d5c: 4a12 ldr r2, [pc, #72] ; (8003da8 <HAL_UART_Transmit_IT+0xb8>)
8003d5e: 66da str r2, [r3, #108] ; 0x6c
}
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
8003d60: 68fb ldr r3, [r7, #12]
8003d62: 681b ldr r3, [r3, #0]
8003d64: 617b str r3, [r7, #20]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003d66: 697b ldr r3, [r7, #20]
8003d68: e853 3f00 ldrex r3, [r3]
8003d6c: 613b str r3, [r7, #16]
return(result);
8003d6e: 693b ldr r3, [r7, #16]
8003d70: f043 0380 orr.w r3, r3, #128 ; 0x80
8003d74: 627b str r3, [r7, #36] ; 0x24
8003d76: 68fb ldr r3, [r7, #12]
8003d78: 681b ldr r3, [r3, #0]
8003d7a: 461a mov r2, r3
8003d7c: 6a7b ldr r3, [r7, #36] ; 0x24
8003d7e: 623b str r3, [r7, #32]
8003d80: 61fa str r2, [r7, #28]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003d82: 69f9 ldr r1, [r7, #28]
8003d84: 6a3a ldr r2, [r7, #32]
8003d86: e841 2300 strex r3, r2, [r1]
8003d8a: 61bb str r3, [r7, #24]
return(result);
8003d8c: 69bb ldr r3, [r7, #24]
8003d8e: 2b00 cmp r3, #0
8003d90: d1e6 bne.n 8003d60 <HAL_UART_Transmit_IT+0x70>
#endif /* USART_CR1_FIFOEN */
return HAL_OK;
8003d92: 2300 movs r3, #0
8003d94: e000 b.n 8003d98 <HAL_UART_Transmit_IT+0xa8>
}
else
{
return HAL_BUSY;
8003d96: 2302 movs r3, #2
}
}
8003d98: 4618 mov r0, r3
8003d9a: 372c adds r7, #44 ; 0x2c
8003d9c: 46bd mov sp, r7
8003d9e: f85d 7b04 ldr.w r7, [sp], #4
8003da2: 4770 bx lr
8003da4: 08004f91 .word 0x08004f91
8003da8: 08004ed9 .word 0x08004ed9
08003dac <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8003dac: b580 push {r7, lr}
8003dae: b08a sub sp, #40 ; 0x28
8003db0: af00 add r7, sp, #0
8003db2: 60f8 str r0, [r7, #12]
8003db4: 60b9 str r1, [r7, #8]
8003db6: 4613 mov r3, r2
8003db8: 80fb strh r3, [r7, #6]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8003dba: 68fb ldr r3, [r7, #12]
8003dbc: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8003dc0: 2b20 cmp r3, #32
8003dc2: d137 bne.n 8003e34 <HAL_UART_Receive_IT+0x88>
{
if ((pData == NULL) || (Size == 0U))
8003dc4: 68bb ldr r3, [r7, #8]
8003dc6: 2b00 cmp r3, #0
8003dc8: d002 beq.n 8003dd0 <HAL_UART_Receive_IT+0x24>
8003dca: 88fb ldrh r3, [r7, #6]
8003dcc: 2b00 cmp r3, #0
8003dce: d101 bne.n 8003dd4 <HAL_UART_Receive_IT+0x28>
{
return HAL_ERROR;
8003dd0: 2301 movs r3, #1
8003dd2: e030 b.n 8003e36 <HAL_UART_Receive_IT+0x8a>
}
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003dd4: 68fb ldr r3, [r7, #12]
8003dd6: 2200 movs r2, #0
8003dd8: 661a str r2, [r3, #96] ; 0x60
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8003dda: 68fb ldr r3, [r7, #12]
8003ddc: 681b ldr r3, [r3, #0]
8003dde: 4a18 ldr r2, [pc, #96] ; (8003e40 <HAL_UART_Receive_IT+0x94>)
8003de0: 4293 cmp r3, r2
8003de2: d01f beq.n 8003e24 <HAL_UART_Receive_IT+0x78>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8003de4: 68fb ldr r3, [r7, #12]
8003de6: 681b ldr r3, [r3, #0]
8003de8: 685b ldr r3, [r3, #4]
8003dea: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8003dee: 2b00 cmp r3, #0
8003df0: d018 beq.n 8003e24 <HAL_UART_Receive_IT+0x78>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8003df2: 68fb ldr r3, [r7, #12]
8003df4: 681b ldr r3, [r3, #0]
8003df6: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003df8: 697b ldr r3, [r7, #20]
8003dfa: e853 3f00 ldrex r3, [r3]
8003dfe: 613b str r3, [r7, #16]
return(result);
8003e00: 693b ldr r3, [r7, #16]
8003e02: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8003e06: 627b str r3, [r7, #36] ; 0x24
8003e08: 68fb ldr r3, [r7, #12]
8003e0a: 681b ldr r3, [r3, #0]
8003e0c: 461a mov r2, r3
8003e0e: 6a7b ldr r3, [r7, #36] ; 0x24
8003e10: 623b str r3, [r7, #32]
8003e12: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003e14: 69f9 ldr r1, [r7, #28]
8003e16: 6a3a ldr r2, [r7, #32]
8003e18: e841 2300 strex r3, r2, [r1]
8003e1c: 61bb str r3, [r7, #24]
return(result);
8003e1e: 69bb ldr r3, [r7, #24]
8003e20: 2b00 cmp r3, #0
8003e22: d1e6 bne.n 8003df2 <HAL_UART_Receive_IT+0x46>
}
}
return (UART_Start_Receive_IT(huart, pData, Size));
8003e24: 88fb ldrh r3, [r7, #6]
8003e26: 461a mov r2, r3
8003e28: 68b9 ldr r1, [r7, #8]
8003e2a: 68f8 ldr r0, [r7, #12]
8003e2c: f000 ff14 bl 8004c58 <UART_Start_Receive_IT>
8003e30: 4603 mov r3, r0
8003e32: e000 b.n 8003e36 <HAL_UART_Receive_IT+0x8a>
}
else
{
return HAL_BUSY;
8003e34: 2302 movs r3, #2
}
}
8003e36: 4618 mov r0, r3
8003e38: 3728 adds r7, #40 ; 0x28
8003e3a: 46bd mov sp, r7
8003e3c: bd80 pop {r7, pc}
8003e3e: bf00 nop
8003e40: 40008000 .word 0x40008000
08003e44 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8003e44: b580 push {r7, lr}
8003e46: b0ba sub sp, #232 ; 0xe8
8003e48: af00 add r7, sp, #0
8003e4a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8003e4c: 687b ldr r3, [r7, #4]
8003e4e: 681b ldr r3, [r3, #0]
8003e50: 69db ldr r3, [r3, #28]
8003e52: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8003e56: 687b ldr r3, [r7, #4]
8003e58: 681b ldr r3, [r3, #0]
8003e5a: 681b ldr r3, [r3, #0]
8003e5c: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8003e60: 687b ldr r3, [r7, #4]
8003e62: 681b ldr r3, [r3, #0]
8003e64: 689b ldr r3, [r3, #8]
8003e66: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
8003e6a: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4
8003e6e: f640 030f movw r3, #2063 ; 0x80f
8003e72: 4013 ands r3, r2
8003e74: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
if (errorflags == 0U)
8003e78: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
8003e7c: 2b00 cmp r3, #0
8003e7e: d115 bne.n 8003eac <HAL_UART_IRQHandler+0x68>
#if defined(USART_CR1_FIFOEN)
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
#else
if (((isrflags & USART_ISR_RXNE) != 0U)
8003e80: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003e84: f003 0320 and.w r3, r3, #32
8003e88: 2b00 cmp r3, #0
8003e8a: d00f beq.n 8003eac <HAL_UART_IRQHandler+0x68>
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
8003e8c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003e90: f003 0320 and.w r3, r3, #32
8003e94: 2b00 cmp r3, #0
8003e96: d009 beq.n 8003eac <HAL_UART_IRQHandler+0x68>
#endif /* USART_CR1_FIFOEN */
{
if (huart->RxISR != NULL)
8003e98: 687b ldr r3, [r7, #4]
8003e9a: 6e9b ldr r3, [r3, #104] ; 0x68
8003e9c: 2b00 cmp r3, #0
8003e9e: f000 82ae beq.w 80043fe <HAL_UART_IRQHandler+0x5ba>
{
huart->RxISR(huart);
8003ea2: 687b ldr r3, [r7, #4]
8003ea4: 6e9b ldr r3, [r3, #104] ; 0x68
8003ea6: 6878 ldr r0, [r7, #4]
8003ea8: 4798 blx r3
}
return;
8003eaa: e2a8 b.n 80043fe <HAL_UART_IRQHandler+0x5ba>
#if defined(USART_CR1_FIFOEN)
if ((errorflags != 0U)
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
#else
if ((errorflags != 0U)
8003eac: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
8003eb0: 2b00 cmp r3, #0
8003eb2: f000 8117 beq.w 80040e4 <HAL_UART_IRQHandler+0x2a0>
&& (((cr3its & USART_CR3_EIE) != 0U)
8003eb6: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8003eba: f003 0301 and.w r3, r3, #1
8003ebe: 2b00 cmp r3, #0
8003ec0: d106 bne.n 8003ed0 <HAL_UART_IRQHandler+0x8c>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
8003ec2: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0
8003ec6: 4b85 ldr r3, [pc, #532] ; (80040dc <HAL_UART_IRQHandler+0x298>)
8003ec8: 4013 ands r3, r2
8003eca: 2b00 cmp r3, #0
8003ecc: f000 810a beq.w 80040e4 <HAL_UART_IRQHandler+0x2a0>
#endif /* USART_CR1_FIFOEN */
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8003ed0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003ed4: f003 0301 and.w r3, r3, #1
8003ed8: 2b00 cmp r3, #0
8003eda: d011 beq.n 8003f00 <HAL_UART_IRQHandler+0xbc>
8003edc: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003ee0: f403 7380 and.w r3, r3, #256 ; 0x100
8003ee4: 2b00 cmp r3, #0
8003ee6: d00b beq.n 8003f00 <HAL_UART_IRQHandler+0xbc>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8003ee8: 687b ldr r3, [r7, #4]
8003eea: 681b ldr r3, [r3, #0]
8003eec: 2201 movs r2, #1
8003eee: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8003ef0: 687b ldr r3, [r7, #4]
8003ef2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003ef6: f043 0201 orr.w r2, r3, #1
8003efa: 687b ldr r3, [r7, #4]
8003efc: f8c3 2084 str.w r2, [r3, #132] ; 0x84
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8003f00: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003f04: f003 0302 and.w r3, r3, #2
8003f08: 2b00 cmp r3, #0
8003f0a: d011 beq.n 8003f30 <HAL_UART_IRQHandler+0xec>
8003f0c: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8003f10: f003 0301 and.w r3, r3, #1
8003f14: 2b00 cmp r3, #0
8003f16: d00b beq.n 8003f30 <HAL_UART_IRQHandler+0xec>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8003f18: 687b ldr r3, [r7, #4]
8003f1a: 681b ldr r3, [r3, #0]
8003f1c: 2202 movs r2, #2
8003f1e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8003f20: 687b ldr r3, [r7, #4]
8003f22: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003f26: f043 0204 orr.w r2, r3, #4
8003f2a: 687b ldr r3, [r7, #4]
8003f2c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8003f30: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003f34: f003 0304 and.w r3, r3, #4
8003f38: 2b00 cmp r3, #0
8003f3a: d011 beq.n 8003f60 <HAL_UART_IRQHandler+0x11c>
8003f3c: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8003f40: f003 0301 and.w r3, r3, #1
8003f44: 2b00 cmp r3, #0
8003f46: d00b beq.n 8003f60 <HAL_UART_IRQHandler+0x11c>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8003f48: 687b ldr r3, [r7, #4]
8003f4a: 681b ldr r3, [r3, #0]
8003f4c: 2204 movs r2, #4
8003f4e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8003f50: 687b ldr r3, [r7, #4]
8003f52: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003f56: f043 0202 orr.w r2, r3, #2
8003f5a: 687b ldr r3, [r7, #4]
8003f5c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
#if defined(USART_CR1_FIFOEN)
if (((isrflags & USART_ISR_ORE) != 0U)
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
#else
if (((isrflags & USART_ISR_ORE) != 0U)
8003f60: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003f64: f003 0308 and.w r3, r3, #8
8003f68: 2b00 cmp r3, #0
8003f6a: d017 beq.n 8003f9c <HAL_UART_IRQHandler+0x158>
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
8003f6c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003f70: f003 0320 and.w r3, r3, #32
8003f74: 2b00 cmp r3, #0
8003f76: d105 bne.n 8003f84 <HAL_UART_IRQHandler+0x140>
((cr3its & USART_CR3_EIE) != 0U)))
8003f78: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8003f7c: f003 0301 and.w r3, r3, #1
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
8003f80: 2b00 cmp r3, #0
8003f82: d00b beq.n 8003f9c <HAL_UART_IRQHandler+0x158>
#endif /* USART_CR1_FIFOEN */
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8003f84: 687b ldr r3, [r7, #4]
8003f86: 681b ldr r3, [r3, #0]
8003f88: 2208 movs r2, #8
8003f8a: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8003f8c: 687b ldr r3, [r7, #4]
8003f8e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003f92: f043 0208 orr.w r2, r3, #8
8003f96: 687b ldr r3, [r7, #4]
8003f98: f8c3 2084 str.w r2, [r3, #132] ; 0x84
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
8003f9c: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003fa0: f403 6300 and.w r3, r3, #2048 ; 0x800
8003fa4: 2b00 cmp r3, #0
8003fa6: d012 beq.n 8003fce <HAL_UART_IRQHandler+0x18a>
8003fa8: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003fac: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8003fb0: 2b00 cmp r3, #0
8003fb2: d00c beq.n 8003fce <HAL_UART_IRQHandler+0x18a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 681b ldr r3, [r3, #0]
8003fb8: f44f 6200 mov.w r2, #2048 ; 0x800
8003fbc: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
8003fbe: 687b ldr r3, [r7, #4]
8003fc0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003fc4: f043 0220 orr.w r2, r3, #32
8003fc8: 687b ldr r3, [r7, #4]
8003fca: f8c3 2084 str.w r2, [r3, #132] ; 0x84
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8003fce: 687b ldr r3, [r7, #4]
8003fd0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003fd4: 2b00 cmp r3, #0
8003fd6: f000 8214 beq.w 8004402 <HAL_UART_IRQHandler+0x5be>
#if defined(USART_CR1_FIFOEN)
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
#else
if (((isrflags & USART_ISR_RXNE) != 0U)
8003fda: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003fde: f003 0320 and.w r3, r3, #32
8003fe2: 2b00 cmp r3, #0
8003fe4: d00d beq.n 8004002 <HAL_UART_IRQHandler+0x1be>
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
8003fe6: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003fea: f003 0320 and.w r3, r3, #32
8003fee: 2b00 cmp r3, #0
8003ff0: d007 beq.n 8004002 <HAL_UART_IRQHandler+0x1be>
#endif /* USART_CR1_FIFOEN */
{
if (huart->RxISR != NULL)
8003ff2: 687b ldr r3, [r7, #4]
8003ff4: 6e9b ldr r3, [r3, #104] ; 0x68
8003ff6: 2b00 cmp r3, #0
8003ff8: d003 beq.n 8004002 <HAL_UART_IRQHandler+0x1be>
{
huart->RxISR(huart);
8003ffa: 687b ldr r3, [r7, #4]
8003ffc: 6e9b ldr r3, [r3, #104] ; 0x68
8003ffe: 6878 ldr r0, [r7, #4]
8004000: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
8004002: 687b ldr r3, [r7, #4]
8004004: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8004008: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
800400c: 687b ldr r3, [r7, #4]
800400e: 681b ldr r3, [r3, #0]
8004010: 689b ldr r3, [r3, #8]
8004012: f003 0340 and.w r3, r3, #64 ; 0x40
8004016: 2b40 cmp r3, #64 ; 0x40
8004018: d005 beq.n 8004026 <HAL_UART_IRQHandler+0x1e2>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
800401a: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4
800401e: f003 0328 and.w r3, r3, #40 ; 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004022: 2b00 cmp r3, #0
8004024: d04f beq.n 80040c6 <HAL_UART_IRQHandler+0x282>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
8004026: 6878 ldr r0, [r7, #4]
8004028: f000 fedc bl 8004de4 <UART_EndRxTransfer>
/* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800402c: 687b ldr r3, [r7, #4]
800402e: 681b ldr r3, [r3, #0]
8004030: 689b ldr r3, [r3, #8]
8004032: f003 0340 and.w r3, r3, #64 ; 0x40
8004036: 2b40 cmp r3, #64 ; 0x40
8004038: d141 bne.n 80040be <HAL_UART_IRQHandler+0x27a>
{
/* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800403a: 687b ldr r3, [r7, #4]
800403c: 681b ldr r3, [r3, #0]
800403e: 3308 adds r3, #8
8004040: f8c7 309c str.w r3, [r7, #156] ; 0x9c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004044: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8004048: e853 3f00 ldrex r3, [r3]
800404c: f8c7 3098 str.w r3, [r7, #152] ; 0x98
return(result);
8004050: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98
8004054: f023 0340 bic.w r3, r3, #64 ; 0x40
8004058: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
800405c: 687b ldr r3, [r7, #4]
800405e: 681b ldr r3, [r3, #0]
8004060: 3308 adds r3, #8
8004062: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0
8004066: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8
800406a: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800406e: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4
8004072: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8
8004076: e841 2300 strex r3, r2, [r1]
800407a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
return(result);
800407e: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
8004082: 2b00 cmp r3, #0
8004084: d1d9 bne.n 800403a <HAL_UART_IRQHandler+0x1f6>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8004086: 687b ldr r3, [r7, #4]
8004088: 6f5b ldr r3, [r3, #116] ; 0x74
800408a: 2b00 cmp r3, #0
800408c: d013 beq.n 80040b6 <HAL_UART_IRQHandler+0x272>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
800408e: 687b ldr r3, [r7, #4]
8004090: 6f5b ldr r3, [r3, #116] ; 0x74
8004092: 4a13 ldr r2, [pc, #76] ; (80040e0 <HAL_UART_IRQHandler+0x29c>)
8004094: 639a str r2, [r3, #56] ; 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
8004096: 687b ldr r3, [r7, #4]
8004098: 6f5b ldr r3, [r3, #116] ; 0x74
800409a: 4618 mov r0, r3
800409c: f7fd f9e3 bl 8001466 <HAL_DMA_Abort_IT>
80040a0: 4603 mov r3, r0
80040a2: 2b00 cmp r3, #0
80040a4: d017 beq.n 80040d6 <HAL_UART_IRQHandler+0x292>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80040a6: 687b ldr r3, [r7, #4]
80040a8: 6f5b ldr r3, [r3, #116] ; 0x74
80040aa: 6b9b ldr r3, [r3, #56] ; 0x38
80040ac: 687a ldr r2, [r7, #4]
80040ae: 6f52 ldr r2, [r2, #116] ; 0x74
80040b0: 4610 mov r0, r2
80040b2: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80040b4: e00f b.n 80040d6 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80040b6: 6878 ldr r0, [r7, #4]
80040b8: f000 f9b8 bl 800442c <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80040bc: e00b b.n 80040d6 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80040be: 6878 ldr r0, [r7, #4]
80040c0: f000 f9b4 bl 800442c <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80040c4: e007 b.n 80040d6 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80040c6: 6878 ldr r0, [r7, #4]
80040c8: f000 f9b0 bl 800442c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80040cc: 687b ldr r3, [r7, #4]
80040ce: 2200 movs r2, #0
80040d0: f8c3 2084 str.w r2, [r3, #132] ; 0x84
}
}
return;
80040d4: e195 b.n 8004402 <HAL_UART_IRQHandler+0x5be>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80040d6: bf00 nop
return;
80040d8: e193 b.n 8004402 <HAL_UART_IRQHandler+0x5be>
80040da: bf00 nop
80040dc: 04000120 .word 0x04000120
80040e0: 08004ead .word 0x08004ead
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80040e4: 687b ldr r3, [r7, #4]
80040e6: 6e1b ldr r3, [r3, #96] ; 0x60
80040e8: 2b01 cmp r3, #1
80040ea: f040 814e bne.w 800438a <HAL_UART_IRQHandler+0x546>
&& ((isrflags & USART_ISR_IDLE) != 0U)
80040ee: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80040f2: f003 0310 and.w r3, r3, #16
80040f6: 2b00 cmp r3, #0
80040f8: f000 8147 beq.w 800438a <HAL_UART_IRQHandler+0x546>
&& ((cr1its & USART_ISR_IDLE) != 0U))
80040fc: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8004100: f003 0310 and.w r3, r3, #16
8004104: 2b00 cmp r3, #0
8004106: f000 8140 beq.w 800438a <HAL_UART_IRQHandler+0x546>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800410a: 687b ldr r3, [r7, #4]
800410c: 681b ldr r3, [r3, #0]
800410e: 2210 movs r2, #16
8004110: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004112: 687b ldr r3, [r7, #4]
8004114: 681b ldr r3, [r3, #0]
8004116: 689b ldr r3, [r3, #8]
8004118: f003 0340 and.w r3, r3, #64 ; 0x40
800411c: 2b40 cmp r3, #64 ; 0x40
800411e: f040 80b8 bne.w 8004292 <HAL_UART_IRQHandler+0x44e>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8004122: 687b ldr r3, [r7, #4]
8004124: 6f5b ldr r3, [r3, #116] ; 0x74
8004126: 681b ldr r3, [r3, #0]
8004128: 685b ldr r3, [r3, #4]
800412a: f8a7 30be strh.w r3, [r7, #190] ; 0xbe
if ((nb_remaining_rx_data > 0U)
800412e: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe
8004132: 2b00 cmp r3, #0
8004134: f000 8167 beq.w 8004406 <HAL_UART_IRQHandler+0x5c2>
&& (nb_remaining_rx_data < huart->RxXferSize))
8004138: 687b ldr r3, [r7, #4]
800413a: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
800413e: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
8004142: 429a cmp r2, r3
8004144: f080 815f bcs.w 8004406 <HAL_UART_IRQHandler+0x5c2>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8004148: 687b ldr r3, [r7, #4]
800414a: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
800414e: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
8004152: 687b ldr r3, [r7, #4]
8004154: 6f5b ldr r3, [r3, #116] ; 0x74
8004156: 681b ldr r3, [r3, #0]
8004158: 681b ldr r3, [r3, #0]
800415a: f003 0320 and.w r3, r3, #32
800415e: 2b00 cmp r3, #0
8004160: f040 8086 bne.w 8004270 <HAL_UART_IRQHandler+0x42c>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8004164: 687b ldr r3, [r7, #4]
8004166: 681b ldr r3, [r3, #0]
8004168: f8c7 3088 str.w r3, [r7, #136] ; 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800416c: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
8004170: e853 3f00 ldrex r3, [r3]
8004174: f8c7 3084 str.w r3, [r7, #132] ; 0x84
return(result);
8004178: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
800417c: f423 7380 bic.w r3, r3, #256 ; 0x100
8004180: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
8004184: 687b ldr r3, [r7, #4]
8004186: 681b ldr r3, [r3, #0]
8004188: 461a mov r2, r3
800418a: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8
800418e: f8c7 3094 str.w r3, [r7, #148] ; 0x94
8004192: f8c7 2090 str.w r2, [r7, #144] ; 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004196: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90
800419a: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
800419e: e841 2300 strex r3, r2, [r1]
80041a2: f8c7 308c str.w r3, [r7, #140] ; 0x8c
return(result);
80041a6: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
80041aa: 2b00 cmp r3, #0
80041ac: d1da bne.n 8004164 <HAL_UART_IRQHandler+0x320>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80041ae: 687b ldr r3, [r7, #4]
80041b0: 681b ldr r3, [r3, #0]
80041b2: 3308 adds r3, #8
80041b4: 677b str r3, [r7, #116] ; 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80041b6: 6f7b ldr r3, [r7, #116] ; 0x74
80041b8: e853 3f00 ldrex r3, [r3]
80041bc: 673b str r3, [r7, #112] ; 0x70
return(result);
80041be: 6f3b ldr r3, [r7, #112] ; 0x70
80041c0: f023 0301 bic.w r3, r3, #1
80041c4: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
80041c8: 687b ldr r3, [r7, #4]
80041ca: 681b ldr r3, [r3, #0]
80041cc: 3308 adds r3, #8
80041ce: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4
80041d2: f8c7 2080 str.w r2, [r7, #128] ; 0x80
80041d6: 67fb str r3, [r7, #124] ; 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80041d8: 6ff9 ldr r1, [r7, #124] ; 0x7c
80041da: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80
80041de: e841 2300 strex r3, r2, [r1]
80041e2: 67bb str r3, [r7, #120] ; 0x78
return(result);
80041e4: 6fbb ldr r3, [r7, #120] ; 0x78
80041e6: 2b00 cmp r3, #0
80041e8: d1e1 bne.n 80041ae <HAL_UART_IRQHandler+0x36a>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80041ea: 687b ldr r3, [r7, #4]
80041ec: 681b ldr r3, [r3, #0]
80041ee: 3308 adds r3, #8
80041f0: 663b str r3, [r7, #96] ; 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80041f2: 6e3b ldr r3, [r7, #96] ; 0x60
80041f4: e853 3f00 ldrex r3, [r3]
80041f8: 65fb str r3, [r7, #92] ; 0x5c
return(result);
80041fa: 6dfb ldr r3, [r7, #92] ; 0x5c
80041fc: f023 0340 bic.w r3, r3, #64 ; 0x40
8004200: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8004204: 687b ldr r3, [r7, #4]
8004206: 681b ldr r3, [r3, #0]
8004208: 3308 adds r3, #8
800420a: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0
800420e: 66fa str r2, [r7, #108] ; 0x6c
8004210: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004212: 6eb9 ldr r1, [r7, #104] ; 0x68
8004214: 6efa ldr r2, [r7, #108] ; 0x6c
8004216: e841 2300 strex r3, r2, [r1]
800421a: 667b str r3, [r7, #100] ; 0x64
return(result);
800421c: 6e7b ldr r3, [r7, #100] ; 0x64
800421e: 2b00 cmp r3, #0
8004220: d1e3 bne.n 80041ea <HAL_UART_IRQHandler+0x3a6>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004222: 687b ldr r3, [r7, #4]
8004224: 2220 movs r2, #32
8004226: f8c3 2080 str.w r2, [r3, #128] ; 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800422a: 687b ldr r3, [r7, #4]
800422c: 2200 movs r2, #0
800422e: 661a str r2, [r3, #96] ; 0x60
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004230: 687b ldr r3, [r7, #4]
8004232: 681b ldr r3, [r3, #0]
8004234: 64fb str r3, [r7, #76] ; 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004236: 6cfb ldr r3, [r7, #76] ; 0x4c
8004238: e853 3f00 ldrex r3, [r3]
800423c: 64bb str r3, [r7, #72] ; 0x48
return(result);
800423e: 6cbb ldr r3, [r7, #72] ; 0x48
8004240: f023 0310 bic.w r3, r3, #16
8004244: f8c7 30ac str.w r3, [r7, #172] ; 0xac
8004248: 687b ldr r3, [r7, #4]
800424a: 681b ldr r3, [r3, #0]
800424c: 461a mov r2, r3
800424e: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
8004252: 65bb str r3, [r7, #88] ; 0x58
8004254: 657a str r2, [r7, #84] ; 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004256: 6d79 ldr r1, [r7, #84] ; 0x54
8004258: 6dba ldr r2, [r7, #88] ; 0x58
800425a: e841 2300 strex r3, r2, [r1]
800425e: 653b str r3, [r7, #80] ; 0x50
return(result);
8004260: 6d3b ldr r3, [r7, #80] ; 0x50
8004262: 2b00 cmp r3, #0
8004264: d1e4 bne.n 8004230 <HAL_UART_IRQHandler+0x3ec>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8004266: 687b ldr r3, [r7, #4]
8004268: 6f5b ldr r3, [r3, #116] ; 0x74
800426a: 4618 mov r0, r3
800426c: f7fd f8bd bl 80013ea <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8004270: 687b ldr r3, [r7, #4]
8004272: 2202 movs r2, #2
8004274: 665a str r2, [r3, #100] ; 0x64
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8004276: 687b ldr r3, [r7, #4]
8004278: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
800427c: 687b ldr r3, [r7, #4]
800427e: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
8004282: b29b uxth r3, r3
8004284: 1ad3 subs r3, r2, r3
8004286: b29b uxth r3, r3
8004288: 4619 mov r1, r3
800428a: 6878 ldr r0, [r7, #4]
800428c: f7fc f9f2 bl 8000674 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8004290: e0b9 b.n 8004406 <HAL_UART_IRQHandler+0x5c2>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8004292: 687b ldr r3, [r7, #4]
8004294: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
8004298: 687b ldr r3, [r7, #4]
800429a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
800429e: b29b uxth r3, r3
80042a0: 1ad3 subs r3, r2, r3
80042a2: f8a7 30ce strh.w r3, [r7, #206] ; 0xce
if ((huart->RxXferCount > 0U)
80042a6: 687b ldr r3, [r7, #4]
80042a8: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
80042ac: b29b uxth r3, r3
80042ae: 2b00 cmp r3, #0
80042b0: f000 80ab beq.w 800440a <HAL_UART_IRQHandler+0x5c6>
&& (nb_rx_data > 0U))
80042b4: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
80042b8: 2b00 cmp r3, #0
80042ba: f000 80a6 beq.w 800440a <HAL_UART_IRQHandler+0x5c6>
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80042be: 687b ldr r3, [r7, #4]
80042c0: 681b ldr r3, [r3, #0]
80042c2: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80042c4: 6bbb ldr r3, [r7, #56] ; 0x38
80042c6: e853 3f00 ldrex r3, [r3]
80042ca: 637b str r3, [r7, #52] ; 0x34
return(result);
80042cc: 6b7b ldr r3, [r7, #52] ; 0x34
80042ce: f423 7390 bic.w r3, r3, #288 ; 0x120
80042d2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
80042d6: 687b ldr r3, [r7, #4]
80042d8: 681b ldr r3, [r3, #0]
80042da: 461a mov r2, r3
80042dc: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8
80042e0: 647b str r3, [r7, #68] ; 0x44
80042e2: 643a str r2, [r7, #64] ; 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80042e4: 6c39 ldr r1, [r7, #64] ; 0x40
80042e6: 6c7a ldr r2, [r7, #68] ; 0x44
80042e8: e841 2300 strex r3, r2, [r1]
80042ec: 63fb str r3, [r7, #60] ; 0x3c
return(result);
80042ee: 6bfb ldr r3, [r7, #60] ; 0x3c
80042f0: 2b00 cmp r3, #0
80042f2: d1e4 bne.n 80042be <HAL_UART_IRQHandler+0x47a>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80042f4: 687b ldr r3, [r7, #4]
80042f6: 681b ldr r3, [r3, #0]
80042f8: 3308 adds r3, #8
80042fa: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80042fc: 6a7b ldr r3, [r7, #36] ; 0x24
80042fe: e853 3f00 ldrex r3, [r3]
8004302: 623b str r3, [r7, #32]
return(result);
8004304: 6a3b ldr r3, [r7, #32]
8004306: f023 0301 bic.w r3, r3, #1
800430a: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
800430e: 687b ldr r3, [r7, #4]
8004310: 681b ldr r3, [r3, #0]
8004312: 3308 adds r3, #8
8004314: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4
8004318: 633a str r2, [r7, #48] ; 0x30
800431a: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800431c: 6af9 ldr r1, [r7, #44] ; 0x2c
800431e: 6b3a ldr r2, [r7, #48] ; 0x30
8004320: e841 2300 strex r3, r2, [r1]
8004324: 62bb str r3, [r7, #40] ; 0x28
return(result);
8004326: 6abb ldr r3, [r7, #40] ; 0x28
8004328: 2b00 cmp r3, #0
800432a: d1e3 bne.n 80042f4 <HAL_UART_IRQHandler+0x4b0>
#endif /* USART_CR1_FIFOEN */
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800432c: 687b ldr r3, [r7, #4]
800432e: 2220 movs r2, #32
8004330: f8c3 2080 str.w r2, [r3, #128] ; 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004334: 687b ldr r3, [r7, #4]
8004336: 2200 movs r2, #0
8004338: 661a str r2, [r3, #96] ; 0x60
/* Clear RxISR function pointer */
huart->RxISR = NULL;
800433a: 687b ldr r3, [r7, #4]
800433c: 2200 movs r2, #0
800433e: 669a str r2, [r3, #104] ; 0x68
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004340: 687b ldr r3, [r7, #4]
8004342: 681b ldr r3, [r3, #0]
8004344: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004346: 693b ldr r3, [r7, #16]
8004348: e853 3f00 ldrex r3, [r3]
800434c: 60fb str r3, [r7, #12]
return(result);
800434e: 68fb ldr r3, [r7, #12]
8004350: f023 0310 bic.w r3, r3, #16
8004354: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
8004358: 687b ldr r3, [r7, #4]
800435a: 681b ldr r3, [r3, #0]
800435c: 461a mov r2, r3
800435e: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
8004362: 61fb str r3, [r7, #28]
8004364: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004366: 69b9 ldr r1, [r7, #24]
8004368: 69fa ldr r2, [r7, #28]
800436a: e841 2300 strex r3, r2, [r1]
800436e: 617b str r3, [r7, #20]
return(result);
8004370: 697b ldr r3, [r7, #20]
8004372: 2b00 cmp r3, #0
8004374: d1e4 bne.n 8004340 <HAL_UART_IRQHandler+0x4fc>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8004376: 687b ldr r3, [r7, #4]
8004378: 2202 movs r2, #2
800437a: 665a str r2, [r3, #100] ; 0x64
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
800437c: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
8004380: 4619 mov r1, r3
8004382: 6878 ldr r0, [r7, #4]
8004384: f7fc f976 bl 8000674 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8004388: e03f b.n 800440a <HAL_UART_IRQHandler+0x5c6>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
800438a: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
800438e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8004392: 2b00 cmp r3, #0
8004394: d00e beq.n 80043b4 <HAL_UART_IRQHandler+0x570>
8004396: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
800439a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800439e: 2b00 cmp r3, #0
80043a0: d008 beq.n 80043b4 <HAL_UART_IRQHandler+0x570>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
80043a2: 687b ldr r3, [r7, #4]
80043a4: 681b ldr r3, [r3, #0]
80043a6: f44f 1280 mov.w r2, #1048576 ; 0x100000
80043aa: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
80043ac: 6878 ldr r0, [r7, #4]
80043ae: f001 f835 bl 800541c <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
80043b2: e02d b.n 8004410 <HAL_UART_IRQHandler+0x5cc>
#if defined(USART_CR1_FIFOEN)
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
#else
if (((isrflags & USART_ISR_TXE) != 0U)
80043b4: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80043b8: f003 0380 and.w r3, r3, #128 ; 0x80
80043bc: 2b00 cmp r3, #0
80043be: d00e beq.n 80043de <HAL_UART_IRQHandler+0x59a>
&& ((cr1its & USART_CR1_TXEIE) != 0U))
80043c0: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
80043c4: f003 0380 and.w r3, r3, #128 ; 0x80
80043c8: 2b00 cmp r3, #0
80043ca: d008 beq.n 80043de <HAL_UART_IRQHandler+0x59a>
#endif /* USART_CR1_FIFOEN */
{
if (huart->TxISR != NULL)
80043cc: 687b ldr r3, [r7, #4]
80043ce: 6edb ldr r3, [r3, #108] ; 0x6c
80043d0: 2b00 cmp r3, #0
80043d2: d01c beq.n 800440e <HAL_UART_IRQHandler+0x5ca>
{
huart->TxISR(huart);
80043d4: 687b ldr r3, [r7, #4]
80043d6: 6edb ldr r3, [r3, #108] ; 0x6c
80043d8: 6878 ldr r0, [r7, #4]
80043da: 4798 blx r3
}
return;
80043dc: e017 b.n 800440e <HAL_UART_IRQHandler+0x5ca>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
80043de: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80043e2: f003 0340 and.w r3, r3, #64 ; 0x40
80043e6: 2b00 cmp r3, #0
80043e8: d012 beq.n 8004410 <HAL_UART_IRQHandler+0x5cc>
80043ea: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
80043ee: f003 0340 and.w r3, r3, #64 ; 0x40
80043f2: 2b00 cmp r3, #0
80043f4: d00c beq.n 8004410 <HAL_UART_IRQHandler+0x5cc>
{
UART_EndTransmit_IT(huart);
80043f6: 6878 ldr r0, [r7, #4]
80043f8: f000 fe2a bl 8005050 <UART_EndTransmit_IT>
return;
80043fc: e008 b.n 8004410 <HAL_UART_IRQHandler+0x5cc>
return;
80043fe: bf00 nop
8004400: e006 b.n 8004410 <HAL_UART_IRQHandler+0x5cc>
return;
8004402: bf00 nop
8004404: e004 b.n 8004410 <HAL_UART_IRQHandler+0x5cc>
return;
8004406: bf00 nop
8004408: e002 b.n 8004410 <HAL_UART_IRQHandler+0x5cc>
return;
800440a: bf00 nop
800440c: e000 b.n 8004410 <HAL_UART_IRQHandler+0x5cc>
return;
800440e: bf00 nop
HAL_UARTEx_RxFifoFullCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
}
#endif /* USART_CR1_FIFOEN */
}
8004410: 37e8 adds r7, #232 ; 0xe8
8004412: 46bd mov sp, r7
8004414: bd80 pop {r7, pc}
8004416: bf00 nop
08004418 <HAL_UART_TxCpltCallback>:
* @brief Tx Transfer completed callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8004418: b480 push {r7}
800441a: b083 sub sp, #12
800441c: af00 add r7, sp, #0
800441e: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback can be implemented in the user file.
*/
}
8004420: bf00 nop
8004422: 370c adds r7, #12
8004424: 46bd mov sp, r7
8004426: f85d 7b04 ldr.w r7, [sp], #4
800442a: 4770 bx lr
0800442c <HAL_UART_ErrorCallback>:
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
800442c: b480 push {r7}
800442e: b083 sub sp, #12
8004430: af00 add r7, sp, #0
8004432: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
8004434: bf00 nop
8004436: 370c adds r7, #12
8004438: 46bd mov sp, r7
800443a: f85d 7b04 ldr.w r7, [sp], #4
800443e: 4770 bx lr
08004440 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8004440: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8004444: b08a sub sp, #40 ; 0x28
8004446: af00 add r7, sp, #0
8004448: 60f8 str r0, [r7, #12]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
800444a: 2300 movs r3, #0
800444c: f887 3022 strb.w r3, [r7, #34] ; 0x22
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004450: 68fb ldr r3, [r7, #12]
8004452: 689a ldr r2, [r3, #8]
8004454: 68fb ldr r3, [r7, #12]
8004456: 691b ldr r3, [r3, #16]
8004458: 431a orrs r2, r3
800445a: 68fb ldr r3, [r7, #12]
800445c: 695b ldr r3, [r3, #20]
800445e: 431a orrs r2, r3
8004460: 68fb ldr r3, [r7, #12]
8004462: 69db ldr r3, [r3, #28]
8004464: 4313 orrs r3, r2
8004466: 627b str r3, [r7, #36] ; 0x24
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004468: 68fb ldr r3, [r7, #12]
800446a: 681b ldr r3, [r3, #0]
800446c: 681a ldr r2, [r3, #0]
800446e: 4b9e ldr r3, [pc, #632] ; (80046e8 <UART_SetConfig+0x2a8>)
8004470: 4013 ands r3, r2
8004472: 68fa ldr r2, [r7, #12]
8004474: 6812 ldr r2, [r2, #0]
8004476: 6a79 ldr r1, [r7, #36] ; 0x24
8004478: 430b orrs r3, r1
800447a: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
800447c: 68fb ldr r3, [r7, #12]
800447e: 681b ldr r3, [r3, #0]
8004480: 685b ldr r3, [r3, #4]
8004482: f423 5140 bic.w r1, r3, #12288 ; 0x3000
8004486: 68fb ldr r3, [r7, #12]
8004488: 68da ldr r2, [r3, #12]
800448a: 68fb ldr r3, [r7, #12]
800448c: 681b ldr r3, [r3, #0]
800448e: 430a orrs r2, r1
8004490: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8004492: 68fb ldr r3, [r7, #12]
8004494: 699b ldr r3, [r3, #24]
8004496: 627b str r3, [r7, #36] ; 0x24
if (!(UART_INSTANCE_LOWPOWER(huart)))
8004498: 68fb ldr r3, [r7, #12]
800449a: 681b ldr r3, [r3, #0]
800449c: 4a93 ldr r2, [pc, #588] ; (80046ec <UART_SetConfig+0x2ac>)
800449e: 4293 cmp r3, r2
80044a0: d004 beq.n 80044ac <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
80044a2: 68fb ldr r3, [r7, #12]
80044a4: 6a1b ldr r3, [r3, #32]
80044a6: 6a7a ldr r2, [r7, #36] ; 0x24
80044a8: 4313 orrs r3, r2
80044aa: 627b str r3, [r7, #36] ; 0x24
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80044ac: 68fb ldr r3, [r7, #12]
80044ae: 681b ldr r3, [r3, #0]
80044b0: 689b ldr r3, [r3, #8]
80044b2: f423 6130 bic.w r1, r3, #2816 ; 0xb00
80044b6: 68fb ldr r3, [r7, #12]
80044b8: 681b ldr r3, [r3, #0]
80044ba: 6a7a ldr r2, [r7, #36] ; 0x24
80044bc: 430a orrs r2, r1
80044be: 609a str r2, [r3, #8]
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
80044c0: 68fb ldr r3, [r7, #12]
80044c2: 681b ldr r3, [r3, #0]
80044c4: 4a8a ldr r2, [pc, #552] ; (80046f0 <UART_SetConfig+0x2b0>)
80044c6: 4293 cmp r3, r2
80044c8: d126 bne.n 8004518 <UART_SetConfig+0xd8>
80044ca: 4b8a ldr r3, [pc, #552] ; (80046f4 <UART_SetConfig+0x2b4>)
80044cc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80044d0: f003 0303 and.w r3, r3, #3
80044d4: 2b03 cmp r3, #3
80044d6: d81b bhi.n 8004510 <UART_SetConfig+0xd0>
80044d8: a201 add r2, pc, #4 ; (adr r2, 80044e0 <UART_SetConfig+0xa0>)
80044da: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80044de: bf00 nop
80044e0: 080044f1 .word 0x080044f1
80044e4: 08004501 .word 0x08004501
80044e8: 080044f9 .word 0x080044f9
80044ec: 08004509 .word 0x08004509
80044f0: 2301 movs r3, #1
80044f2: f887 3023 strb.w r3, [r7, #35] ; 0x23
80044f6: e0ab b.n 8004650 <UART_SetConfig+0x210>
80044f8: 2302 movs r3, #2
80044fa: f887 3023 strb.w r3, [r7, #35] ; 0x23
80044fe: e0a7 b.n 8004650 <UART_SetConfig+0x210>
8004500: 2304 movs r3, #4
8004502: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004506: e0a3 b.n 8004650 <UART_SetConfig+0x210>
8004508: 2308 movs r3, #8
800450a: f887 3023 strb.w r3, [r7, #35] ; 0x23
800450e: e09f b.n 8004650 <UART_SetConfig+0x210>
8004510: 2310 movs r3, #16
8004512: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004516: e09b b.n 8004650 <UART_SetConfig+0x210>
8004518: 68fb ldr r3, [r7, #12]
800451a: 681b ldr r3, [r3, #0]
800451c: 4a76 ldr r2, [pc, #472] ; (80046f8 <UART_SetConfig+0x2b8>)
800451e: 4293 cmp r3, r2
8004520: d138 bne.n 8004594 <UART_SetConfig+0x154>
8004522: 4b74 ldr r3, [pc, #464] ; (80046f4 <UART_SetConfig+0x2b4>)
8004524: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8004528: f003 030c and.w r3, r3, #12
800452c: 2b0c cmp r3, #12
800452e: d82d bhi.n 800458c <UART_SetConfig+0x14c>
8004530: a201 add r2, pc, #4 ; (adr r2, 8004538 <UART_SetConfig+0xf8>)
8004532: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004536: bf00 nop
8004538: 0800456d .word 0x0800456d
800453c: 0800458d .word 0x0800458d
8004540: 0800458d .word 0x0800458d
8004544: 0800458d .word 0x0800458d
8004548: 0800457d .word 0x0800457d
800454c: 0800458d .word 0x0800458d
8004550: 0800458d .word 0x0800458d
8004554: 0800458d .word 0x0800458d
8004558: 08004575 .word 0x08004575
800455c: 0800458d .word 0x0800458d
8004560: 0800458d .word 0x0800458d
8004564: 0800458d .word 0x0800458d
8004568: 08004585 .word 0x08004585
800456c: 2300 movs r3, #0
800456e: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004572: e06d b.n 8004650 <UART_SetConfig+0x210>
8004574: 2302 movs r3, #2
8004576: f887 3023 strb.w r3, [r7, #35] ; 0x23
800457a: e069 b.n 8004650 <UART_SetConfig+0x210>
800457c: 2304 movs r3, #4
800457e: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004582: e065 b.n 8004650 <UART_SetConfig+0x210>
8004584: 2308 movs r3, #8
8004586: f887 3023 strb.w r3, [r7, #35] ; 0x23
800458a: e061 b.n 8004650 <UART_SetConfig+0x210>
800458c: 2310 movs r3, #16
800458e: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004592: e05d b.n 8004650 <UART_SetConfig+0x210>
8004594: 68fb ldr r3, [r7, #12]
8004596: 681b ldr r3, [r3, #0]
8004598: 4a58 ldr r2, [pc, #352] ; (80046fc <UART_SetConfig+0x2bc>)
800459a: 4293 cmp r3, r2
800459c: d125 bne.n 80045ea <UART_SetConfig+0x1aa>
800459e: 4b55 ldr r3, [pc, #340] ; (80046f4 <UART_SetConfig+0x2b4>)
80045a0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80045a4: f003 0330 and.w r3, r3, #48 ; 0x30
80045a8: 2b30 cmp r3, #48 ; 0x30
80045aa: d016 beq.n 80045da <UART_SetConfig+0x19a>
80045ac: 2b30 cmp r3, #48 ; 0x30
80045ae: d818 bhi.n 80045e2 <UART_SetConfig+0x1a2>
80045b0: 2b20 cmp r3, #32
80045b2: d00a beq.n 80045ca <UART_SetConfig+0x18a>
80045b4: 2b20 cmp r3, #32
80045b6: d814 bhi.n 80045e2 <UART_SetConfig+0x1a2>
80045b8: 2b00 cmp r3, #0
80045ba: d002 beq.n 80045c2 <UART_SetConfig+0x182>
80045bc: 2b10 cmp r3, #16
80045be: d008 beq.n 80045d2 <UART_SetConfig+0x192>
80045c0: e00f b.n 80045e2 <UART_SetConfig+0x1a2>
80045c2: 2300 movs r3, #0
80045c4: f887 3023 strb.w r3, [r7, #35] ; 0x23
80045c8: e042 b.n 8004650 <UART_SetConfig+0x210>
80045ca: 2302 movs r3, #2
80045cc: f887 3023 strb.w r3, [r7, #35] ; 0x23
80045d0: e03e b.n 8004650 <UART_SetConfig+0x210>
80045d2: 2304 movs r3, #4
80045d4: f887 3023 strb.w r3, [r7, #35] ; 0x23
80045d8: e03a b.n 8004650 <UART_SetConfig+0x210>
80045da: 2308 movs r3, #8
80045dc: f887 3023 strb.w r3, [r7, #35] ; 0x23
80045e0: e036 b.n 8004650 <UART_SetConfig+0x210>
80045e2: 2310 movs r3, #16
80045e4: f887 3023 strb.w r3, [r7, #35] ; 0x23
80045e8: e032 b.n 8004650 <UART_SetConfig+0x210>
80045ea: 68fb ldr r3, [r7, #12]
80045ec: 681b ldr r3, [r3, #0]
80045ee: 4a3f ldr r2, [pc, #252] ; (80046ec <UART_SetConfig+0x2ac>)
80045f0: 4293 cmp r3, r2
80045f2: d12a bne.n 800464a <UART_SetConfig+0x20a>
80045f4: 4b3f ldr r3, [pc, #252] ; (80046f4 <UART_SetConfig+0x2b4>)
80045f6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80045fa: f403 6340 and.w r3, r3, #3072 ; 0xc00
80045fe: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
8004602: d01a beq.n 800463a <UART_SetConfig+0x1fa>
8004604: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
8004608: d81b bhi.n 8004642 <UART_SetConfig+0x202>
800460a: f5b3 6f00 cmp.w r3, #2048 ; 0x800
800460e: d00c beq.n 800462a <UART_SetConfig+0x1ea>
8004610: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8004614: d815 bhi.n 8004642 <UART_SetConfig+0x202>
8004616: 2b00 cmp r3, #0
8004618: d003 beq.n 8004622 <UART_SetConfig+0x1e2>
800461a: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800461e: d008 beq.n 8004632 <UART_SetConfig+0x1f2>
8004620: e00f b.n 8004642 <UART_SetConfig+0x202>
8004622: 2300 movs r3, #0
8004624: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004628: e012 b.n 8004650 <UART_SetConfig+0x210>
800462a: 2302 movs r3, #2
800462c: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004630: e00e b.n 8004650 <UART_SetConfig+0x210>
8004632: 2304 movs r3, #4
8004634: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004638: e00a b.n 8004650 <UART_SetConfig+0x210>
800463a: 2308 movs r3, #8
800463c: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004640: e006 b.n 8004650 <UART_SetConfig+0x210>
8004642: 2310 movs r3, #16
8004644: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004648: e002 b.n 8004650 <UART_SetConfig+0x210>
800464a: 2310 movs r3, #16
800464c: f887 3023 strb.w r3, [r7, #35] ; 0x23
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8004650: 68fb ldr r3, [r7, #12]
8004652: 681b ldr r3, [r3, #0]
8004654: 4a25 ldr r2, [pc, #148] ; (80046ec <UART_SetConfig+0x2ac>)
8004656: 4293 cmp r3, r2
8004658: f040 808a bne.w 8004770 <UART_SetConfig+0x330>
{
/* Retrieve frequency clock */
switch (clocksource)
800465c: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
8004660: 2b08 cmp r3, #8
8004662: d824 bhi.n 80046ae <UART_SetConfig+0x26e>
8004664: a201 add r2, pc, #4 ; (adr r2, 800466c <UART_SetConfig+0x22c>)
8004666: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800466a: bf00 nop
800466c: 08004691 .word 0x08004691
8004670: 080046af .word 0x080046af
8004674: 08004699 .word 0x08004699
8004678: 080046af .word 0x080046af
800467c: 0800469f .word 0x0800469f
8004680: 080046af .word 0x080046af
8004684: 080046af .word 0x080046af
8004688: 080046af .word 0x080046af
800468c: 080046a7 .word 0x080046a7
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004690: f7fd fecc bl 800242c <HAL_RCC_GetPCLK1Freq>
8004694: 61f8 str r0, [r7, #28]
break;
8004696: e010 b.n 80046ba <UART_SetConfig+0x27a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004698: 4b19 ldr r3, [pc, #100] ; (8004700 <UART_SetConfig+0x2c0>)
800469a: 61fb str r3, [r7, #28]
break;
800469c: e00d b.n 80046ba <UART_SetConfig+0x27a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800469e: f7fd fe2d bl 80022fc <HAL_RCC_GetSysClockFreq>
80046a2: 61f8 str r0, [r7, #28]
break;
80046a4: e009 b.n 80046ba <UART_SetConfig+0x27a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80046a6: f44f 4300 mov.w r3, #32768 ; 0x8000
80046aa: 61fb str r3, [r7, #28]
break;
80046ac: e005 b.n 80046ba <UART_SetConfig+0x27a>
default:
pclk = 0U;
80046ae: 2300 movs r3, #0
80046b0: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
80046b2: 2301 movs r3, #1
80046b4: f887 3022 strb.w r3, [r7, #34] ; 0x22
break;
80046b8: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
80046ba: 69fb ldr r3, [r7, #28]
80046bc: 2b00 cmp r3, #0
80046be: f000 8109 beq.w 80048d4 <UART_SetConfig+0x494>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
/* No Prescaler applicable */
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((pclk < (3U * huart->Init.BaudRate)) ||
80046c2: 68fb ldr r3, [r7, #12]
80046c4: 685a ldr r2, [r3, #4]
80046c6: 4613 mov r3, r2
80046c8: 005b lsls r3, r3, #1
80046ca: 4413 add r3, r2
80046cc: 69fa ldr r2, [r7, #28]
80046ce: 429a cmp r2, r3
80046d0: d305 bcc.n 80046de <UART_SetConfig+0x29e>
(pclk > (4096U * huart->Init.BaudRate)))
80046d2: 68fb ldr r3, [r7, #12]
80046d4: 685b ldr r3, [r3, #4]
80046d6: 031b lsls r3, r3, #12
if ((pclk < (3U * huart->Init.BaudRate)) ||
80046d8: 69fa ldr r2, [r7, #28]
80046da: 429a cmp r2, r3
80046dc: d912 bls.n 8004704 <UART_SetConfig+0x2c4>
{
ret = HAL_ERROR;
80046de: 2301 movs r3, #1
80046e0: f887 3022 strb.w r3, [r7, #34] ; 0x22
80046e4: e0f6 b.n 80048d4 <UART_SetConfig+0x494>
80046e6: bf00 nop
80046e8: efff69f3 .word 0xefff69f3
80046ec: 40008000 .word 0x40008000
80046f0: 40013800 .word 0x40013800
80046f4: 40021000 .word 0x40021000
80046f8: 40004400 .word 0x40004400
80046fc: 40004800 .word 0x40004800
8004700: 00f42400 .word 0x00f42400
}
else
{
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
8004704: 69fb ldr r3, [r7, #28]
8004706: 2200 movs r2, #0
8004708: 461c mov r4, r3
800470a: 4615 mov r5, r2
800470c: f04f 0200 mov.w r2, #0
8004710: f04f 0300 mov.w r3, #0
8004714: 022b lsls r3, r5, #8
8004716: ea43 6314 orr.w r3, r3, r4, lsr #24
800471a: 0222 lsls r2, r4, #8
800471c: 68f9 ldr r1, [r7, #12]
800471e: 6849 ldr r1, [r1, #4]
8004720: 0849 lsrs r1, r1, #1
8004722: 2000 movs r0, #0
8004724: 4688 mov r8, r1
8004726: 4681 mov r9, r0
8004728: eb12 0a08 adds.w sl, r2, r8
800472c: eb43 0b09 adc.w fp, r3, r9
8004730: 68fb ldr r3, [r7, #12]
8004732: 685b ldr r3, [r3, #4]
8004734: 2200 movs r2, #0
8004736: 603b str r3, [r7, #0]
8004738: 607a str r2, [r7, #4]
800473a: e9d7 2300 ldrd r2, r3, [r7]
800473e: 4650 mov r0, sl
8004740: 4659 mov r1, fp
8004742: f7fb fd4b bl 80001dc <__aeabi_uldivmod>
8004746: 4602 mov r2, r0
8004748: 460b mov r3, r1
800474a: 4613 mov r3, r2
800474c: 61bb str r3, [r7, #24]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
800474e: 69bb ldr r3, [r7, #24]
8004750: f5b3 7f40 cmp.w r3, #768 ; 0x300
8004754: d308 bcc.n 8004768 <UART_SetConfig+0x328>
8004756: 69bb ldr r3, [r7, #24]
8004758: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
800475c: d204 bcs.n 8004768 <UART_SetConfig+0x328>
{
huart->Instance->BRR = usartdiv;
800475e: 68fb ldr r3, [r7, #12]
8004760: 681b ldr r3, [r3, #0]
8004762: 69ba ldr r2, [r7, #24]
8004764: 60da str r2, [r3, #12]
8004766: e0b5 b.n 80048d4 <UART_SetConfig+0x494>
}
else
{
ret = HAL_ERROR;
8004768: 2301 movs r3, #1
800476a: f887 3022 strb.w r3, [r7, #34] ; 0x22
800476e: e0b1 b.n 80048d4 <UART_SetConfig+0x494>
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004770: 68fb ldr r3, [r7, #12]
8004772: 69db ldr r3, [r3, #28]
8004774: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8004778: d15d bne.n 8004836 <UART_SetConfig+0x3f6>
{
switch (clocksource)
800477a: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
800477e: 2b08 cmp r3, #8
8004780: d827 bhi.n 80047d2 <UART_SetConfig+0x392>
8004782: a201 add r2, pc, #4 ; (adr r2, 8004788 <UART_SetConfig+0x348>)
8004784: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004788: 080047ad .word 0x080047ad
800478c: 080047b5 .word 0x080047b5
8004790: 080047bd .word 0x080047bd
8004794: 080047d3 .word 0x080047d3
8004798: 080047c3 .word 0x080047c3
800479c: 080047d3 .word 0x080047d3
80047a0: 080047d3 .word 0x080047d3
80047a4: 080047d3 .word 0x080047d3
80047a8: 080047cb .word 0x080047cb
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80047ac: f7fd fe3e bl 800242c <HAL_RCC_GetPCLK1Freq>
80047b0: 61f8 str r0, [r7, #28]
break;
80047b2: e014 b.n 80047de <UART_SetConfig+0x39e>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80047b4: f7fd fe50 bl 8002458 <HAL_RCC_GetPCLK2Freq>
80047b8: 61f8 str r0, [r7, #28]
break;
80047ba: e010 b.n 80047de <UART_SetConfig+0x39e>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80047bc: 4b4c ldr r3, [pc, #304] ; (80048f0 <UART_SetConfig+0x4b0>)
80047be: 61fb str r3, [r7, #28]
break;
80047c0: e00d b.n 80047de <UART_SetConfig+0x39e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80047c2: f7fd fd9b bl 80022fc <HAL_RCC_GetSysClockFreq>
80047c6: 61f8 str r0, [r7, #28]
break;
80047c8: e009 b.n 80047de <UART_SetConfig+0x39e>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80047ca: f44f 4300 mov.w r3, #32768 ; 0x8000
80047ce: 61fb str r3, [r7, #28]
break;
80047d0: e005 b.n 80047de <UART_SetConfig+0x39e>
default:
pclk = 0U;
80047d2: 2300 movs r3, #0
80047d4: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
80047d6: 2301 movs r3, #1
80047d8: f887 3022 strb.w r3, [r7, #34] ; 0x22
break;
80047dc: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80047de: 69fb ldr r3, [r7, #28]
80047e0: 2b00 cmp r3, #0
80047e2: d077 beq.n 80048d4 <UART_SetConfig+0x494>
{
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
80047e4: 69fb ldr r3, [r7, #28]
80047e6: 005a lsls r2, r3, #1
80047e8: 68fb ldr r3, [r7, #12]
80047ea: 685b ldr r3, [r3, #4]
80047ec: 085b lsrs r3, r3, #1
80047ee: 441a add r2, r3
80047f0: 68fb ldr r3, [r7, #12]
80047f2: 685b ldr r3, [r3, #4]
80047f4: fbb2 f3f3 udiv r3, r2, r3
80047f8: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80047fa: 69bb ldr r3, [r7, #24]
80047fc: 2b0f cmp r3, #15
80047fe: d916 bls.n 800482e <UART_SetConfig+0x3ee>
8004800: 69bb ldr r3, [r7, #24]
8004802: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8004806: d212 bcs.n 800482e <UART_SetConfig+0x3ee>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8004808: 69bb ldr r3, [r7, #24]
800480a: b29b uxth r3, r3
800480c: f023 030f bic.w r3, r3, #15
8004810: 82fb strh r3, [r7, #22]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8004812: 69bb ldr r3, [r7, #24]
8004814: 085b lsrs r3, r3, #1
8004816: b29b uxth r3, r3
8004818: f003 0307 and.w r3, r3, #7
800481c: b29a uxth r2, r3
800481e: 8afb ldrh r3, [r7, #22]
8004820: 4313 orrs r3, r2
8004822: 82fb strh r3, [r7, #22]
huart->Instance->BRR = brrtemp;
8004824: 68fb ldr r3, [r7, #12]
8004826: 681b ldr r3, [r3, #0]
8004828: 8afa ldrh r2, [r7, #22]
800482a: 60da str r2, [r3, #12]
800482c: e052 b.n 80048d4 <UART_SetConfig+0x494>
}
else
{
ret = HAL_ERROR;
800482e: 2301 movs r3, #1
8004830: f887 3022 strb.w r3, [r7, #34] ; 0x22
8004834: e04e b.n 80048d4 <UART_SetConfig+0x494>
}
}
}
else
{
switch (clocksource)
8004836: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
800483a: 2b08 cmp r3, #8
800483c: d827 bhi.n 800488e <UART_SetConfig+0x44e>
800483e: a201 add r2, pc, #4 ; (adr r2, 8004844 <UART_SetConfig+0x404>)
8004840: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004844: 08004869 .word 0x08004869
8004848: 08004871 .word 0x08004871
800484c: 08004879 .word 0x08004879
8004850: 0800488f .word 0x0800488f
8004854: 0800487f .word 0x0800487f
8004858: 0800488f .word 0x0800488f
800485c: 0800488f .word 0x0800488f
8004860: 0800488f .word 0x0800488f
8004864: 08004887 .word 0x08004887
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004868: f7fd fde0 bl 800242c <HAL_RCC_GetPCLK1Freq>
800486c: 61f8 str r0, [r7, #28]
break;
800486e: e014 b.n 800489a <UART_SetConfig+0x45a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8004870: f7fd fdf2 bl 8002458 <HAL_RCC_GetPCLK2Freq>
8004874: 61f8 str r0, [r7, #28]
break;
8004876: e010 b.n 800489a <UART_SetConfig+0x45a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004878: 4b1d ldr r3, [pc, #116] ; (80048f0 <UART_SetConfig+0x4b0>)
800487a: 61fb str r3, [r7, #28]
break;
800487c: e00d b.n 800489a <UART_SetConfig+0x45a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800487e: f7fd fd3d bl 80022fc <HAL_RCC_GetSysClockFreq>
8004882: 61f8 str r0, [r7, #28]
break;
8004884: e009 b.n 800489a <UART_SetConfig+0x45a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8004886: f44f 4300 mov.w r3, #32768 ; 0x8000
800488a: 61fb str r3, [r7, #28]
break;
800488c: e005 b.n 800489a <UART_SetConfig+0x45a>
default:
pclk = 0U;
800488e: 2300 movs r3, #0
8004890: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
8004892: 2301 movs r3, #1
8004894: f887 3022 strb.w r3, [r7, #34] ; 0x22
break;
8004898: bf00 nop
}
if (pclk != 0U)
800489a: 69fb ldr r3, [r7, #28]
800489c: 2b00 cmp r3, #0
800489e: d019 beq.n 80048d4 <UART_SetConfig+0x494>
{
/* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
80048a0: 68fb ldr r3, [r7, #12]
80048a2: 685b ldr r3, [r3, #4]
80048a4: 085a lsrs r2, r3, #1
80048a6: 69fb ldr r3, [r7, #28]
80048a8: 441a add r2, r3
80048aa: 68fb ldr r3, [r7, #12]
80048ac: 685b ldr r3, [r3, #4]
80048ae: fbb2 f3f3 udiv r3, r2, r3
80048b2: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80048b4: 69bb ldr r3, [r7, #24]
80048b6: 2b0f cmp r3, #15
80048b8: d909 bls.n 80048ce <UART_SetConfig+0x48e>
80048ba: 69bb ldr r3, [r7, #24]
80048bc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80048c0: d205 bcs.n 80048ce <UART_SetConfig+0x48e>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80048c2: 69bb ldr r3, [r7, #24]
80048c4: b29a uxth r2, r3
80048c6: 68fb ldr r3, [r7, #12]
80048c8: 681b ldr r3, [r3, #0]
80048ca: 60da str r2, [r3, #12]
80048cc: e002 b.n 80048d4 <UART_SetConfig+0x494>
}
else
{
ret = HAL_ERROR;
80048ce: 2301 movs r3, #1
80048d0: f887 3022 strb.w r3, [r7, #34] ; 0x22
huart->NbTxDataToProcess = 1;
huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */
/* Clear ISR function pointers */
huart->RxISR = NULL;
80048d4: 68fb ldr r3, [r7, #12]
80048d6: 2200 movs r2, #0
80048d8: 669a str r2, [r3, #104] ; 0x68
huart->TxISR = NULL;
80048da: 68fb ldr r3, [r7, #12]
80048dc: 2200 movs r2, #0
80048de: 66da str r2, [r3, #108] ; 0x6c
return ret;
80048e0: f897 3022 ldrb.w r3, [r7, #34] ; 0x22
}
80048e4: 4618 mov r0, r3
80048e6: 3728 adds r7, #40 ; 0x28
80048e8: 46bd mov sp, r7
80048ea: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80048ee: bf00 nop
80048f0: 00f42400 .word 0x00f42400
080048f4 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80048f4: b480 push {r7}
80048f6: b083 sub sp, #12
80048f8: af00 add r7, sp, #0
80048fa: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80048fc: 687b ldr r3, [r7, #4]
80048fe: 6a5b ldr r3, [r3, #36] ; 0x24
8004900: f003 0308 and.w r3, r3, #8
8004904: 2b00 cmp r3, #0
8004906: d00a beq.n 800491e <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8004908: 687b ldr r3, [r7, #4]
800490a: 681b ldr r3, [r3, #0]
800490c: 685b ldr r3, [r3, #4]
800490e: f423 4100 bic.w r1, r3, #32768 ; 0x8000
8004912: 687b ldr r3, [r7, #4]
8004914: 6b5a ldr r2, [r3, #52] ; 0x34
8004916: 687b ldr r3, [r7, #4]
8004918: 681b ldr r3, [r3, #0]
800491a: 430a orrs r2, r1
800491c: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
800491e: 687b ldr r3, [r7, #4]
8004920: 6a5b ldr r3, [r3, #36] ; 0x24
8004922: f003 0301 and.w r3, r3, #1
8004926: 2b00 cmp r3, #0
8004928: d00a beq.n 8004940 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800492a: 687b ldr r3, [r7, #4]
800492c: 681b ldr r3, [r3, #0]
800492e: 685b ldr r3, [r3, #4]
8004930: f423 3100 bic.w r1, r3, #131072 ; 0x20000
8004934: 687b ldr r3, [r7, #4]
8004936: 6a9a ldr r2, [r3, #40] ; 0x28
8004938: 687b ldr r3, [r7, #4]
800493a: 681b ldr r3, [r3, #0]
800493c: 430a orrs r2, r1
800493e: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8004940: 687b ldr r3, [r7, #4]
8004942: 6a5b ldr r3, [r3, #36] ; 0x24
8004944: f003 0302 and.w r3, r3, #2
8004948: 2b00 cmp r3, #0
800494a: d00a beq.n 8004962 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
800494c: 687b ldr r3, [r7, #4]
800494e: 681b ldr r3, [r3, #0]
8004950: 685b ldr r3, [r3, #4]
8004952: f423 3180 bic.w r1, r3, #65536 ; 0x10000
8004956: 687b ldr r3, [r7, #4]
8004958: 6ada ldr r2, [r3, #44] ; 0x2c
800495a: 687b ldr r3, [r7, #4]
800495c: 681b ldr r3, [r3, #0]
800495e: 430a orrs r2, r1
8004960: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8004962: 687b ldr r3, [r7, #4]
8004964: 6a5b ldr r3, [r3, #36] ; 0x24
8004966: f003 0304 and.w r3, r3, #4
800496a: 2b00 cmp r3, #0
800496c: d00a beq.n 8004984 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
800496e: 687b ldr r3, [r7, #4]
8004970: 681b ldr r3, [r3, #0]
8004972: 685b ldr r3, [r3, #4]
8004974: f423 2180 bic.w r1, r3, #262144 ; 0x40000
8004978: 687b ldr r3, [r7, #4]
800497a: 6b1a ldr r2, [r3, #48] ; 0x30
800497c: 687b ldr r3, [r7, #4]
800497e: 681b ldr r3, [r3, #0]
8004980: 430a orrs r2, r1
8004982: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8004984: 687b ldr r3, [r7, #4]
8004986: 6a5b ldr r3, [r3, #36] ; 0x24
8004988: f003 0310 and.w r3, r3, #16
800498c: 2b00 cmp r3, #0
800498e: d00a beq.n 80049a6 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8004990: 687b ldr r3, [r7, #4]
8004992: 681b ldr r3, [r3, #0]
8004994: 689b ldr r3, [r3, #8]
8004996: f423 5180 bic.w r1, r3, #4096 ; 0x1000
800499a: 687b ldr r3, [r7, #4]
800499c: 6b9a ldr r2, [r3, #56] ; 0x38
800499e: 687b ldr r3, [r7, #4]
80049a0: 681b ldr r3, [r3, #0]
80049a2: 430a orrs r2, r1
80049a4: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80049a6: 687b ldr r3, [r7, #4]
80049a8: 6a5b ldr r3, [r3, #36] ; 0x24
80049aa: f003 0320 and.w r3, r3, #32
80049ae: 2b00 cmp r3, #0
80049b0: d00a beq.n 80049c8 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80049b2: 687b ldr r3, [r7, #4]
80049b4: 681b ldr r3, [r3, #0]
80049b6: 689b ldr r3, [r3, #8]
80049b8: f423 5100 bic.w r1, r3, #8192 ; 0x2000
80049bc: 687b ldr r3, [r7, #4]
80049be: 6bda ldr r2, [r3, #60] ; 0x3c
80049c0: 687b ldr r3, [r7, #4]
80049c2: 681b ldr r3, [r3, #0]
80049c4: 430a orrs r2, r1
80049c6: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
80049c8: 687b ldr r3, [r7, #4]
80049ca: 6a5b ldr r3, [r3, #36] ; 0x24
80049cc: f003 0340 and.w r3, r3, #64 ; 0x40
80049d0: 2b00 cmp r3, #0
80049d2: d01a beq.n 8004a0a <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80049d4: 687b ldr r3, [r7, #4]
80049d6: 681b ldr r3, [r3, #0]
80049d8: 685b ldr r3, [r3, #4]
80049da: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
80049de: 687b ldr r3, [r7, #4]
80049e0: 6c1a ldr r2, [r3, #64] ; 0x40
80049e2: 687b ldr r3, [r7, #4]
80049e4: 681b ldr r3, [r3, #0]
80049e6: 430a orrs r2, r1
80049e8: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
80049ea: 687b ldr r3, [r7, #4]
80049ec: 6c1b ldr r3, [r3, #64] ; 0x40
80049ee: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80049f2: d10a bne.n 8004a0a <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
80049f4: 687b ldr r3, [r7, #4]
80049f6: 681b ldr r3, [r3, #0]
80049f8: 685b ldr r3, [r3, #4]
80049fa: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
80049fe: 687b ldr r3, [r7, #4]
8004a00: 6c5a ldr r2, [r3, #68] ; 0x44
8004a02: 687b ldr r3, [r7, #4]
8004a04: 681b ldr r3, [r3, #0]
8004a06: 430a orrs r2, r1
8004a08: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8004a0a: 687b ldr r3, [r7, #4]
8004a0c: 6a5b ldr r3, [r3, #36] ; 0x24
8004a0e: f003 0380 and.w r3, r3, #128 ; 0x80
8004a12: 2b00 cmp r3, #0
8004a14: d00a beq.n 8004a2c <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8004a16: 687b ldr r3, [r7, #4]
8004a18: 681b ldr r3, [r3, #0]
8004a1a: 685b ldr r3, [r3, #4]
8004a1c: f423 2100 bic.w r1, r3, #524288 ; 0x80000
8004a20: 687b ldr r3, [r7, #4]
8004a22: 6c9a ldr r2, [r3, #72] ; 0x48
8004a24: 687b ldr r3, [r7, #4]
8004a26: 681b ldr r3, [r3, #0]
8004a28: 430a orrs r2, r1
8004a2a: 605a str r2, [r3, #4]
}
}
8004a2c: bf00 nop
8004a2e: 370c adds r7, #12
8004a30: 46bd mov sp, r7
8004a32: f85d 7b04 ldr.w r7, [sp], #4
8004a36: 4770 bx lr
08004a38 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8004a38: b580 push {r7, lr}
8004a3a: b098 sub sp, #96 ; 0x60
8004a3c: af02 add r7, sp, #8
8004a3e: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004a40: 687b ldr r3, [r7, #4]
8004a42: 2200 movs r2, #0
8004a44: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8004a48: f7fc fb8e bl 8001168 <HAL_GetTick>
8004a4c: 6578 str r0, [r7, #84] ; 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8004a4e: 687b ldr r3, [r7, #4]
8004a50: 681b ldr r3, [r3, #0]
8004a52: 681b ldr r3, [r3, #0]
8004a54: f003 0308 and.w r3, r3, #8
8004a58: 2b08 cmp r3, #8
8004a5a: d12e bne.n 8004aba <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004a5c: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
8004a60: 9300 str r3, [sp, #0]
8004a62: 6d7b ldr r3, [r7, #84] ; 0x54
8004a64: 2200 movs r2, #0
8004a66: f44f 1100 mov.w r1, #2097152 ; 0x200000
8004a6a: 6878 ldr r0, [r7, #4]
8004a6c: f000 f88c bl 8004b88 <UART_WaitOnFlagUntilTimeout>
8004a70: 4603 mov r3, r0
8004a72: 2b00 cmp r3, #0
8004a74: d021 beq.n 8004aba <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
8004a76: 687b ldr r3, [r7, #4]
8004a78: 681b ldr r3, [r3, #0]
8004a7a: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004a7c: 6bbb ldr r3, [r7, #56] ; 0x38
8004a7e: e853 3f00 ldrex r3, [r3]
8004a82: 637b str r3, [r7, #52] ; 0x34
return(result);
8004a84: 6b7b ldr r3, [r7, #52] ; 0x34
8004a86: f023 0380 bic.w r3, r3, #128 ; 0x80
8004a8a: 653b str r3, [r7, #80] ; 0x50
8004a8c: 687b ldr r3, [r7, #4]
8004a8e: 681b ldr r3, [r3, #0]
8004a90: 461a mov r2, r3
8004a92: 6d3b ldr r3, [r7, #80] ; 0x50
8004a94: 647b str r3, [r7, #68] ; 0x44
8004a96: 643a str r2, [r7, #64] ; 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004a98: 6c39 ldr r1, [r7, #64] ; 0x40
8004a9a: 6c7a ldr r2, [r7, #68] ; 0x44
8004a9c: e841 2300 strex r3, r2, [r1]
8004aa0: 63fb str r3, [r7, #60] ; 0x3c
return(result);
8004aa2: 6bfb ldr r3, [r7, #60] ; 0x3c
8004aa4: 2b00 cmp r3, #0
8004aa6: d1e6 bne.n 8004a76 <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */
huart->gState = HAL_UART_STATE_READY;
8004aa8: 687b ldr r3, [r7, #4]
8004aaa: 2220 movs r2, #32
8004aac: 67da str r2, [r3, #124] ; 0x7c
__HAL_UNLOCK(huart);
8004aae: 687b ldr r3, [r7, #4]
8004ab0: 2200 movs r2, #0
8004ab2: f883 2078 strb.w r2, [r3, #120] ; 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8004ab6: 2303 movs r3, #3
8004ab8: e062 b.n 8004b80 <UART_CheckIdleState+0x148>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8004aba: 687b ldr r3, [r7, #4]
8004abc: 681b ldr r3, [r3, #0]
8004abe: 681b ldr r3, [r3, #0]
8004ac0: f003 0304 and.w r3, r3, #4
8004ac4: 2b04 cmp r3, #4
8004ac6: d149 bne.n 8004b5c <UART_CheckIdleState+0x124>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004ac8: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
8004acc: 9300 str r3, [sp, #0]
8004ace: 6d7b ldr r3, [r7, #84] ; 0x54
8004ad0: 2200 movs r2, #0
8004ad2: f44f 0180 mov.w r1, #4194304 ; 0x400000
8004ad6: 6878 ldr r0, [r7, #4]
8004ad8: f000 f856 bl 8004b88 <UART_WaitOnFlagUntilTimeout>
8004adc: 4603 mov r3, r0
8004ade: 2b00 cmp r3, #0
8004ae0: d03c beq.n 8004b5c <UART_CheckIdleState+0x124>
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004ae2: 687b ldr r3, [r7, #4]
8004ae4: 681b ldr r3, [r3, #0]
8004ae6: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004ae8: 6a7b ldr r3, [r7, #36] ; 0x24
8004aea: e853 3f00 ldrex r3, [r3]
8004aee: 623b str r3, [r7, #32]
return(result);
8004af0: 6a3b ldr r3, [r7, #32]
8004af2: f423 7390 bic.w r3, r3, #288 ; 0x120
8004af6: 64fb str r3, [r7, #76] ; 0x4c
8004af8: 687b ldr r3, [r7, #4]
8004afa: 681b ldr r3, [r3, #0]
8004afc: 461a mov r2, r3
8004afe: 6cfb ldr r3, [r7, #76] ; 0x4c
8004b00: 633b str r3, [r7, #48] ; 0x30
8004b02: 62fa str r2, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004b04: 6af9 ldr r1, [r7, #44] ; 0x2c
8004b06: 6b3a ldr r2, [r7, #48] ; 0x30
8004b08: e841 2300 strex r3, r2, [r1]
8004b0c: 62bb str r3, [r7, #40] ; 0x28
return(result);
8004b0e: 6abb ldr r3, [r7, #40] ; 0x28
8004b10: 2b00 cmp r3, #0
8004b12: d1e6 bne.n 8004ae2 <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004b14: 687b ldr r3, [r7, #4]
8004b16: 681b ldr r3, [r3, #0]
8004b18: 3308 adds r3, #8
8004b1a: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004b1c: 693b ldr r3, [r7, #16]
8004b1e: e853 3f00 ldrex r3, [r3]
8004b22: 60fb str r3, [r7, #12]
return(result);
8004b24: 68fb ldr r3, [r7, #12]
8004b26: f023 0301 bic.w r3, r3, #1
8004b2a: 64bb str r3, [r7, #72] ; 0x48
8004b2c: 687b ldr r3, [r7, #4]
8004b2e: 681b ldr r3, [r3, #0]
8004b30: 3308 adds r3, #8
8004b32: 6cba ldr r2, [r7, #72] ; 0x48
8004b34: 61fa str r2, [r7, #28]
8004b36: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004b38: 69b9 ldr r1, [r7, #24]
8004b3a: 69fa ldr r2, [r7, #28]
8004b3c: e841 2300 strex r3, r2, [r1]
8004b40: 617b str r3, [r7, #20]
return(result);
8004b42: 697b ldr r3, [r7, #20]
8004b44: 2b00 cmp r3, #0
8004b46: d1e5 bne.n 8004b14 <UART_CheckIdleState+0xdc>
huart->RxState = HAL_UART_STATE_READY;
8004b48: 687b ldr r3, [r7, #4]
8004b4a: 2220 movs r2, #32
8004b4c: f8c3 2080 str.w r2, [r3, #128] ; 0x80
__HAL_UNLOCK(huart);
8004b50: 687b ldr r3, [r7, #4]
8004b52: 2200 movs r2, #0
8004b54: f883 2078 strb.w r2, [r3, #120] ; 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8004b58: 2303 movs r3, #3
8004b5a: e011 b.n 8004b80 <UART_CheckIdleState+0x148>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8004b5c: 687b ldr r3, [r7, #4]
8004b5e: 2220 movs r2, #32
8004b60: 67da str r2, [r3, #124] ; 0x7c
huart->RxState = HAL_UART_STATE_READY;
8004b62: 687b ldr r3, [r7, #4]
8004b64: 2220 movs r2, #32
8004b66: f8c3 2080 str.w r2, [r3, #128] ; 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004b6a: 687b ldr r3, [r7, #4]
8004b6c: 2200 movs r2, #0
8004b6e: 661a str r2, [r3, #96] ; 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004b70: 687b ldr r3, [r7, #4]
8004b72: 2200 movs r2, #0
8004b74: 665a str r2, [r3, #100] ; 0x64
__HAL_UNLOCK(huart);
8004b76: 687b ldr r3, [r7, #4]
8004b78: 2200 movs r2, #0
8004b7a: f883 2078 strb.w r2, [r3, #120] ; 0x78
return HAL_OK;
8004b7e: 2300 movs r3, #0
}
8004b80: 4618 mov r0, r3
8004b82: 3758 adds r7, #88 ; 0x58
8004b84: 46bd mov sp, r7
8004b86: bd80 pop {r7, pc}
08004b88 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8004b88: b580 push {r7, lr}
8004b8a: b084 sub sp, #16
8004b8c: af00 add r7, sp, #0
8004b8e: 60f8 str r0, [r7, #12]
8004b90: 60b9 str r1, [r7, #8]
8004b92: 603b str r3, [r7, #0]
8004b94: 4613 mov r3, r2
8004b96: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004b98: e049 b.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa6>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004b9a: 69bb ldr r3, [r7, #24]
8004b9c: f1b3 3fff cmp.w r3, #4294967295
8004ba0: d045 beq.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa6>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004ba2: f7fc fae1 bl 8001168 <HAL_GetTick>
8004ba6: 4602 mov r2, r0
8004ba8: 683b ldr r3, [r7, #0]
8004baa: 1ad3 subs r3, r2, r3
8004bac: 69ba ldr r2, [r7, #24]
8004bae: 429a cmp r2, r3
8004bb0: d302 bcc.n 8004bb8 <UART_WaitOnFlagUntilTimeout+0x30>
8004bb2: 69bb ldr r3, [r7, #24]
8004bb4: 2b00 cmp r3, #0
8004bb6: d101 bne.n 8004bbc <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8004bb8: 2303 movs r3, #3
8004bba: e048 b.n 8004c4e <UART_WaitOnFlagUntilTimeout+0xc6>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8004bbc: 68fb ldr r3, [r7, #12]
8004bbe: 681b ldr r3, [r3, #0]
8004bc0: 681b ldr r3, [r3, #0]
8004bc2: f003 0304 and.w r3, r3, #4
8004bc6: 2b00 cmp r3, #0
8004bc8: d031 beq.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa6>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8004bca: 68fb ldr r3, [r7, #12]
8004bcc: 681b ldr r3, [r3, #0]
8004bce: 69db ldr r3, [r3, #28]
8004bd0: f003 0308 and.w r3, r3, #8
8004bd4: 2b08 cmp r3, #8
8004bd6: d110 bne.n 8004bfa <UART_WaitOnFlagUntilTimeout+0x72>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8004bd8: 68fb ldr r3, [r7, #12]
8004bda: 681b ldr r3, [r3, #0]
8004bdc: 2208 movs r2, #8
8004bde: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8004be0: 68f8 ldr r0, [r7, #12]
8004be2: f000 f8ff bl 8004de4 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8004be6: 68fb ldr r3, [r7, #12]
8004be8: 2208 movs r2, #8
8004bea: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004bee: 68fb ldr r3, [r7, #12]
8004bf0: 2200 movs r2, #0
8004bf2: f883 2078 strb.w r2, [r3, #120] ; 0x78
return HAL_ERROR;
8004bf6: 2301 movs r3, #1
8004bf8: e029 b.n 8004c4e <UART_WaitOnFlagUntilTimeout+0xc6>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8004bfa: 68fb ldr r3, [r7, #12]
8004bfc: 681b ldr r3, [r3, #0]
8004bfe: 69db ldr r3, [r3, #28]
8004c00: f403 6300 and.w r3, r3, #2048 ; 0x800
8004c04: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8004c08: d111 bne.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa6>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8004c0a: 68fb ldr r3, [r7, #12]
8004c0c: 681b ldr r3, [r3, #0]
8004c0e: f44f 6200 mov.w r2, #2048 ; 0x800
8004c12: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8004c14: 68f8 ldr r0, [r7, #12]
8004c16: f000 f8e5 bl 8004de4 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8004c1a: 68fb ldr r3, [r7, #12]
8004c1c: 2220 movs r2, #32
8004c1e: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004c22: 68fb ldr r3, [r7, #12]
8004c24: 2200 movs r2, #0
8004c26: f883 2078 strb.w r2, [r3, #120] ; 0x78
return HAL_TIMEOUT;
8004c2a: 2303 movs r3, #3
8004c2c: e00f b.n 8004c4e <UART_WaitOnFlagUntilTimeout+0xc6>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004c2e: 68fb ldr r3, [r7, #12]
8004c30: 681b ldr r3, [r3, #0]
8004c32: 69da ldr r2, [r3, #28]
8004c34: 68bb ldr r3, [r7, #8]
8004c36: 4013 ands r3, r2
8004c38: 68ba ldr r2, [r7, #8]
8004c3a: 429a cmp r2, r3
8004c3c: bf0c ite eq
8004c3e: 2301 moveq r3, #1
8004c40: 2300 movne r3, #0
8004c42: b2db uxtb r3, r3
8004c44: 461a mov r2, r3
8004c46: 79fb ldrb r3, [r7, #7]
8004c48: 429a cmp r2, r3
8004c4a: d0a6 beq.n 8004b9a <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8004c4c: 2300 movs r3, #0
}
8004c4e: 4618 mov r0, r3
8004c50: 3710 adds r7, #16
8004c52: 46bd mov sp, r7
8004c54: bd80 pop {r7, pc}
...
08004c58 <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8004c58: b480 push {r7}
8004c5a: b097 sub sp, #92 ; 0x5c
8004c5c: af00 add r7, sp, #0
8004c5e: 60f8 str r0, [r7, #12]
8004c60: 60b9 str r1, [r7, #8]
8004c62: 4613 mov r3, r2
8004c64: 80fb strh r3, [r7, #6]
huart->pRxBuffPtr = pData;
8004c66: 68fb ldr r3, [r7, #12]
8004c68: 68ba ldr r2, [r7, #8]
8004c6a: 655a str r2, [r3, #84] ; 0x54
huart->RxXferSize = Size;
8004c6c: 68fb ldr r3, [r7, #12]
8004c6e: 88fa ldrh r2, [r7, #6]
8004c70: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
huart->RxXferCount = Size;
8004c74: 68fb ldr r3, [r7, #12]
8004c76: 88fa ldrh r2, [r7, #6]
8004c78: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
huart->RxISR = NULL;
8004c7c: 68fb ldr r3, [r7, #12]
8004c7e: 2200 movs r2, #0
8004c80: 669a str r2, [r3, #104] ; 0x68
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
8004c82: 68fb ldr r3, [r7, #12]
8004c84: 689b ldr r3, [r3, #8]
8004c86: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004c8a: d10e bne.n 8004caa <UART_Start_Receive_IT+0x52>
8004c8c: 68fb ldr r3, [r7, #12]
8004c8e: 691b ldr r3, [r3, #16]
8004c90: 2b00 cmp r3, #0
8004c92: d105 bne.n 8004ca0 <UART_Start_Receive_IT+0x48>
8004c94: 68fb ldr r3, [r7, #12]
8004c96: f240 12ff movw r2, #511 ; 0x1ff
8004c9a: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004c9e: e02d b.n 8004cfc <UART_Start_Receive_IT+0xa4>
8004ca0: 68fb ldr r3, [r7, #12]
8004ca2: 22ff movs r2, #255 ; 0xff
8004ca4: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004ca8: e028 b.n 8004cfc <UART_Start_Receive_IT+0xa4>
8004caa: 68fb ldr r3, [r7, #12]
8004cac: 689b ldr r3, [r3, #8]
8004cae: 2b00 cmp r3, #0
8004cb0: d10d bne.n 8004cce <UART_Start_Receive_IT+0x76>
8004cb2: 68fb ldr r3, [r7, #12]
8004cb4: 691b ldr r3, [r3, #16]
8004cb6: 2b00 cmp r3, #0
8004cb8: d104 bne.n 8004cc4 <UART_Start_Receive_IT+0x6c>
8004cba: 68fb ldr r3, [r7, #12]
8004cbc: 22ff movs r2, #255 ; 0xff
8004cbe: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004cc2: e01b b.n 8004cfc <UART_Start_Receive_IT+0xa4>
8004cc4: 68fb ldr r3, [r7, #12]
8004cc6: 227f movs r2, #127 ; 0x7f
8004cc8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004ccc: e016 b.n 8004cfc <UART_Start_Receive_IT+0xa4>
8004cce: 68fb ldr r3, [r7, #12]
8004cd0: 689b ldr r3, [r3, #8]
8004cd2: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
8004cd6: d10d bne.n 8004cf4 <UART_Start_Receive_IT+0x9c>
8004cd8: 68fb ldr r3, [r7, #12]
8004cda: 691b ldr r3, [r3, #16]
8004cdc: 2b00 cmp r3, #0
8004cde: d104 bne.n 8004cea <UART_Start_Receive_IT+0x92>
8004ce0: 68fb ldr r3, [r7, #12]
8004ce2: 227f movs r2, #127 ; 0x7f
8004ce4: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004ce8: e008 b.n 8004cfc <UART_Start_Receive_IT+0xa4>
8004cea: 68fb ldr r3, [r7, #12]
8004cec: 223f movs r2, #63 ; 0x3f
8004cee: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004cf2: e003 b.n 8004cfc <UART_Start_Receive_IT+0xa4>
8004cf4: 68fb ldr r3, [r7, #12]
8004cf6: 2200 movs r2, #0
8004cf8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004cfc: 68fb ldr r3, [r7, #12]
8004cfe: 2200 movs r2, #0
8004d00: f8c3 2084 str.w r2, [r3, #132] ; 0x84
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004d04: 68fb ldr r3, [r7, #12]
8004d06: 2222 movs r2, #34 ; 0x22
8004d08: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004d0c: 68fb ldr r3, [r7, #12]
8004d0e: 681b ldr r3, [r3, #0]
8004d10: 3308 adds r3, #8
8004d12: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004d14: 6bfb ldr r3, [r7, #60] ; 0x3c
8004d16: e853 3f00 ldrex r3, [r3]
8004d1a: 63bb str r3, [r7, #56] ; 0x38
return(result);
8004d1c: 6bbb ldr r3, [r7, #56] ; 0x38
8004d1e: f043 0301 orr.w r3, r3, #1
8004d22: 657b str r3, [r7, #84] ; 0x54
8004d24: 68fb ldr r3, [r7, #12]
8004d26: 681b ldr r3, [r3, #0]
8004d28: 3308 adds r3, #8
8004d2a: 6d7a ldr r2, [r7, #84] ; 0x54
8004d2c: 64ba str r2, [r7, #72] ; 0x48
8004d2e: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004d30: 6c79 ldr r1, [r7, #68] ; 0x44
8004d32: 6cba ldr r2, [r7, #72] ; 0x48
8004d34: e841 2300 strex r3, r2, [r1]
8004d38: 643b str r3, [r7, #64] ; 0x40
return(result);
8004d3a: 6c3b ldr r3, [r7, #64] ; 0x40
8004d3c: 2b00 cmp r3, #0
8004d3e: d1e5 bne.n 8004d0c <UART_Start_Receive_IT+0xb4>
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
}
#else
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004d40: 68fb ldr r3, [r7, #12]
8004d42: 689b ldr r3, [r3, #8]
8004d44: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004d48: d107 bne.n 8004d5a <UART_Start_Receive_IT+0x102>
8004d4a: 68fb ldr r3, [r7, #12]
8004d4c: 691b ldr r3, [r3, #16]
8004d4e: 2b00 cmp r3, #0
8004d50: d103 bne.n 8004d5a <UART_Start_Receive_IT+0x102>
{
huart->RxISR = UART_RxISR_16BIT;
8004d52: 68fb ldr r3, [r7, #12]
8004d54: 4a21 ldr r2, [pc, #132] ; (8004ddc <UART_Start_Receive_IT+0x184>)
8004d56: 669a str r2, [r3, #104] ; 0x68
8004d58: e002 b.n 8004d60 <UART_Start_Receive_IT+0x108>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
8004d5a: 68fb ldr r3, [r7, #12]
8004d5c: 4a20 ldr r2, [pc, #128] ; (8004de0 <UART_Start_Receive_IT+0x188>)
8004d5e: 669a str r2, [r3, #104] ; 0x68
}
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
8004d60: 68fb ldr r3, [r7, #12]
8004d62: 691b ldr r3, [r3, #16]
8004d64: 2b00 cmp r3, #0
8004d66: d019 beq.n 8004d9c <UART_Start_Receive_IT+0x144>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
8004d68: 68fb ldr r3, [r7, #12]
8004d6a: 681b ldr r3, [r3, #0]
8004d6c: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004d6e: 6abb ldr r3, [r7, #40] ; 0x28
8004d70: e853 3f00 ldrex r3, [r3]
8004d74: 627b str r3, [r7, #36] ; 0x24
return(result);
8004d76: 6a7b ldr r3, [r7, #36] ; 0x24
8004d78: f443 7390 orr.w r3, r3, #288 ; 0x120
8004d7c: 64fb str r3, [r7, #76] ; 0x4c
8004d7e: 68fb ldr r3, [r7, #12]
8004d80: 681b ldr r3, [r3, #0]
8004d82: 461a mov r2, r3
8004d84: 6cfb ldr r3, [r7, #76] ; 0x4c
8004d86: 637b str r3, [r7, #52] ; 0x34
8004d88: 633a str r2, [r7, #48] ; 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004d8a: 6b39 ldr r1, [r7, #48] ; 0x30
8004d8c: 6b7a ldr r2, [r7, #52] ; 0x34
8004d8e: e841 2300 strex r3, r2, [r1]
8004d92: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8004d94: 6afb ldr r3, [r7, #44] ; 0x2c
8004d96: 2b00 cmp r3, #0
8004d98: d1e6 bne.n 8004d68 <UART_Start_Receive_IT+0x110>
8004d9a: e018 b.n 8004dce <UART_Start_Receive_IT+0x176>
}
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
8004d9c: 68fb ldr r3, [r7, #12]
8004d9e: 681b ldr r3, [r3, #0]
8004da0: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004da2: 697b ldr r3, [r7, #20]
8004da4: e853 3f00 ldrex r3, [r3]
8004da8: 613b str r3, [r7, #16]
return(result);
8004daa: 693b ldr r3, [r7, #16]
8004dac: f043 0320 orr.w r3, r3, #32
8004db0: 653b str r3, [r7, #80] ; 0x50
8004db2: 68fb ldr r3, [r7, #12]
8004db4: 681b ldr r3, [r3, #0]
8004db6: 461a mov r2, r3
8004db8: 6d3b ldr r3, [r7, #80] ; 0x50
8004dba: 623b str r3, [r7, #32]
8004dbc: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004dbe: 69f9 ldr r1, [r7, #28]
8004dc0: 6a3a ldr r2, [r7, #32]
8004dc2: e841 2300 strex r3, r2, [r1]
8004dc6: 61bb str r3, [r7, #24]
return(result);
8004dc8: 69bb ldr r3, [r7, #24]
8004dca: 2b00 cmp r3, #0
8004dcc: d1e6 bne.n 8004d9c <UART_Start_Receive_IT+0x144>
}
#endif /* USART_CR1_FIFOEN */
return HAL_OK;
8004dce: 2300 movs r3, #0
}
8004dd0: 4618 mov r0, r3
8004dd2: 375c adds r7, #92 ; 0x5c
8004dd4: 46bd mov sp, r7
8004dd6: f85d 7b04 ldr.w r7, [sp], #4
8004dda: 4770 bx lr
8004ddc: 08005261 .word 0x08005261
8004de0: 080050a5 .word 0x080050a5
08004de4 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004de4: b480 push {r7}
8004de6: b095 sub sp, #84 ; 0x54
8004de8: af00 add r7, sp, #0
8004dea: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004dec: 687b ldr r3, [r7, #4]
8004dee: 681b ldr r3, [r3, #0]
8004df0: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004df2: 6b7b ldr r3, [r7, #52] ; 0x34
8004df4: e853 3f00 ldrex r3, [r3]
8004df8: 633b str r3, [r7, #48] ; 0x30
return(result);
8004dfa: 6b3b ldr r3, [r7, #48] ; 0x30
8004dfc: f423 7390 bic.w r3, r3, #288 ; 0x120
8004e00: 64fb str r3, [r7, #76] ; 0x4c
8004e02: 687b ldr r3, [r7, #4]
8004e04: 681b ldr r3, [r3, #0]
8004e06: 461a mov r2, r3
8004e08: 6cfb ldr r3, [r7, #76] ; 0x4c
8004e0a: 643b str r3, [r7, #64] ; 0x40
8004e0c: 63fa str r2, [r7, #60] ; 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004e0e: 6bf9 ldr r1, [r7, #60] ; 0x3c
8004e10: 6c3a ldr r2, [r7, #64] ; 0x40
8004e12: e841 2300 strex r3, r2, [r1]
8004e16: 63bb str r3, [r7, #56] ; 0x38
return(result);
8004e18: 6bbb ldr r3, [r7, #56] ; 0x38
8004e1a: 2b00 cmp r3, #0
8004e1c: d1e6 bne.n 8004dec <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004e1e: 687b ldr r3, [r7, #4]
8004e20: 681b ldr r3, [r3, #0]
8004e22: 3308 adds r3, #8
8004e24: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004e26: 6a3b ldr r3, [r7, #32]
8004e28: e853 3f00 ldrex r3, [r3]
8004e2c: 61fb str r3, [r7, #28]
return(result);
8004e2e: 69fb ldr r3, [r7, #28]
8004e30: f023 0301 bic.w r3, r3, #1
8004e34: 64bb str r3, [r7, #72] ; 0x48
8004e36: 687b ldr r3, [r7, #4]
8004e38: 681b ldr r3, [r3, #0]
8004e3a: 3308 adds r3, #8
8004e3c: 6cba ldr r2, [r7, #72] ; 0x48
8004e3e: 62fa str r2, [r7, #44] ; 0x2c
8004e40: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004e42: 6ab9 ldr r1, [r7, #40] ; 0x28
8004e44: 6afa ldr r2, [r7, #44] ; 0x2c
8004e46: e841 2300 strex r3, r2, [r1]
8004e4a: 627b str r3, [r7, #36] ; 0x24
return(result);
8004e4c: 6a7b ldr r3, [r7, #36] ; 0x24
8004e4e: 2b00 cmp r3, #0
8004e50: d1e5 bne.n 8004e1e <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004e52: 687b ldr r3, [r7, #4]
8004e54: 6e1b ldr r3, [r3, #96] ; 0x60
8004e56: 2b01 cmp r3, #1
8004e58: d118 bne.n 8004e8c <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004e5a: 687b ldr r3, [r7, #4]
8004e5c: 681b ldr r3, [r3, #0]
8004e5e: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004e60: 68fb ldr r3, [r7, #12]
8004e62: e853 3f00 ldrex r3, [r3]
8004e66: 60bb str r3, [r7, #8]
return(result);
8004e68: 68bb ldr r3, [r7, #8]
8004e6a: f023 0310 bic.w r3, r3, #16
8004e6e: 647b str r3, [r7, #68] ; 0x44
8004e70: 687b ldr r3, [r7, #4]
8004e72: 681b ldr r3, [r3, #0]
8004e74: 461a mov r2, r3
8004e76: 6c7b ldr r3, [r7, #68] ; 0x44
8004e78: 61bb str r3, [r7, #24]
8004e7a: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004e7c: 6979 ldr r1, [r7, #20]
8004e7e: 69ba ldr r2, [r7, #24]
8004e80: e841 2300 strex r3, r2, [r1]
8004e84: 613b str r3, [r7, #16]
return(result);
8004e86: 693b ldr r3, [r7, #16]
8004e88: 2b00 cmp r3, #0
8004e8a: d1e6 bne.n 8004e5a <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004e8c: 687b ldr r3, [r7, #4]
8004e8e: 2220 movs r2, #32
8004e90: f8c3 2080 str.w r2, [r3, #128] ; 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004e94: 687b ldr r3, [r7, #4]
8004e96: 2200 movs r2, #0
8004e98: 661a str r2, [r3, #96] ; 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8004e9a: 687b ldr r3, [r7, #4]
8004e9c: 2200 movs r2, #0
8004e9e: 669a str r2, [r3, #104] ; 0x68
}
8004ea0: bf00 nop
8004ea2: 3754 adds r7, #84 ; 0x54
8004ea4: 46bd mov sp, r7
8004ea6: f85d 7b04 ldr.w r7, [sp], #4
8004eaa: 4770 bx lr
08004eac <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8004eac: b580 push {r7, lr}
8004eae: b084 sub sp, #16
8004eb0: af00 add r7, sp, #0
8004eb2: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8004eb4: 687b ldr r3, [r7, #4]
8004eb6: 6a9b ldr r3, [r3, #40] ; 0x28
8004eb8: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
8004eba: 68fb ldr r3, [r7, #12]
8004ebc: 2200 movs r2, #0
8004ebe: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
huart->TxXferCount = 0U;
8004ec2: 68fb ldr r3, [r7, #12]
8004ec4: 2200 movs r2, #0
8004ec6: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004eca: 68f8 ldr r0, [r7, #12]
8004ecc: f7ff faae bl 800442c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8004ed0: bf00 nop
8004ed2: 3710 adds r7, #16
8004ed4: 46bd mov sp, r7
8004ed6: bd80 pop {r7, pc}
08004ed8 <UART_TxISR_8BIT>:
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
* @retval None
*/
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
{
8004ed8: b480 push {r7}
8004eda: b08f sub sp, #60 ; 0x3c
8004edc: af00 add r7, sp, #0
8004ede: 6078 str r0, [r7, #4]
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8004ee0: 687b ldr r3, [r7, #4]
8004ee2: 6fdb ldr r3, [r3, #124] ; 0x7c
8004ee4: 2b21 cmp r3, #33 ; 0x21
8004ee6: d14d bne.n 8004f84 <UART_TxISR_8BIT+0xac>
{
if (huart->TxXferCount == 0U)
8004ee8: 687b ldr r3, [r7, #4]
8004eea: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8004eee: b29b uxth r3, r3
8004ef0: 2b00 cmp r3, #0
8004ef2: d132 bne.n 8004f5a <UART_TxISR_8BIT+0x82>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
8004ef4: 687b ldr r3, [r7, #4]
8004ef6: 681b ldr r3, [r3, #0]
8004ef8: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004efa: 6a3b ldr r3, [r7, #32]
8004efc: e853 3f00 ldrex r3, [r3]
8004f00: 61fb str r3, [r7, #28]
return(result);
8004f02: 69fb ldr r3, [r7, #28]
8004f04: f023 0380 bic.w r3, r3, #128 ; 0x80
8004f08: 637b str r3, [r7, #52] ; 0x34
8004f0a: 687b ldr r3, [r7, #4]
8004f0c: 681b ldr r3, [r3, #0]
8004f0e: 461a mov r2, r3
8004f10: 6b7b ldr r3, [r7, #52] ; 0x34
8004f12: 62fb str r3, [r7, #44] ; 0x2c
8004f14: 62ba str r2, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004f16: 6ab9 ldr r1, [r7, #40] ; 0x28
8004f18: 6afa ldr r2, [r7, #44] ; 0x2c
8004f1a: e841 2300 strex r3, r2, [r1]
8004f1e: 627b str r3, [r7, #36] ; 0x24
return(result);
8004f20: 6a7b ldr r3, [r7, #36] ; 0x24
8004f22: 2b00 cmp r3, #0
8004f24: d1e6 bne.n 8004ef4 <UART_TxISR_8BIT+0x1c>
#endif /* USART_CR1_FIFOEN */
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8004f26: 687b ldr r3, [r7, #4]
8004f28: 681b ldr r3, [r3, #0]
8004f2a: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004f2c: 68fb ldr r3, [r7, #12]
8004f2e: e853 3f00 ldrex r3, [r3]
8004f32: 60bb str r3, [r7, #8]
return(result);
8004f34: 68bb ldr r3, [r7, #8]
8004f36: f043 0340 orr.w r3, r3, #64 ; 0x40
8004f3a: 633b str r3, [r7, #48] ; 0x30
8004f3c: 687b ldr r3, [r7, #4]
8004f3e: 681b ldr r3, [r3, #0]
8004f40: 461a mov r2, r3
8004f42: 6b3b ldr r3, [r7, #48] ; 0x30
8004f44: 61bb str r3, [r7, #24]
8004f46: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004f48: 6979 ldr r1, [r7, #20]
8004f4a: 69ba ldr r2, [r7, #24]
8004f4c: e841 2300 strex r3, r2, [r1]
8004f50: 613b str r3, [r7, #16]
return(result);
8004f52: 693b ldr r3, [r7, #16]
8004f54: 2b00 cmp r3, #0
8004f56: d1e6 bne.n 8004f26 <UART_TxISR_8BIT+0x4e>
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
huart->pTxBuffPtr++;
huart->TxXferCount--;
}
}
}
8004f58: e014 b.n 8004f84 <UART_TxISR_8BIT+0xac>
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
8004f5a: 687b ldr r3, [r7, #4]
8004f5c: 6cdb ldr r3, [r3, #76] ; 0x4c
8004f5e: 781a ldrb r2, [r3, #0]
8004f60: 687b ldr r3, [r7, #4]
8004f62: 681b ldr r3, [r3, #0]
8004f64: b292 uxth r2, r2
8004f66: 851a strh r2, [r3, #40] ; 0x28
huart->pTxBuffPtr++;
8004f68: 687b ldr r3, [r7, #4]
8004f6a: 6cdb ldr r3, [r3, #76] ; 0x4c
8004f6c: 1c5a adds r2, r3, #1
8004f6e: 687b ldr r3, [r7, #4]
8004f70: 64da str r2, [r3, #76] ; 0x4c
huart->TxXferCount--;
8004f72: 687b ldr r3, [r7, #4]
8004f74: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8004f78: b29b uxth r3, r3
8004f7a: 3b01 subs r3, #1
8004f7c: b29a uxth r2, r3
8004f7e: 687b ldr r3, [r7, #4]
8004f80: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
}
8004f84: bf00 nop
8004f86: 373c adds r7, #60 ; 0x3c
8004f88: 46bd mov sp, r7
8004f8a: f85d 7b04 ldr.w r7, [sp], #4
8004f8e: 4770 bx lr
08004f90 <UART_TxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
* @retval None
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
8004f90: b480 push {r7}
8004f92: b091 sub sp, #68 ; 0x44
8004f94: af00 add r7, sp, #0
8004f96: 6078 str r0, [r7, #4]
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8004f98: 687b ldr r3, [r7, #4]
8004f9a: 6fdb ldr r3, [r3, #124] ; 0x7c
8004f9c: 2b21 cmp r3, #33 ; 0x21
8004f9e: d151 bne.n 8005044 <UART_TxISR_16BIT+0xb4>
{
if (huart->TxXferCount == 0U)
8004fa0: 687b ldr r3, [r7, #4]
8004fa2: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8004fa6: b29b uxth r3, r3
8004fa8: 2b00 cmp r3, #0
8004faa: d132 bne.n 8005012 <UART_TxISR_16BIT+0x82>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
8004fac: 687b ldr r3, [r7, #4]
8004fae: 681b ldr r3, [r3, #0]
8004fb0: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004fb2: 6a7b ldr r3, [r7, #36] ; 0x24
8004fb4: e853 3f00 ldrex r3, [r3]
8004fb8: 623b str r3, [r7, #32]
return(result);
8004fba: 6a3b ldr r3, [r7, #32]
8004fbc: f023 0380 bic.w r3, r3, #128 ; 0x80
8004fc0: 63bb str r3, [r7, #56] ; 0x38
8004fc2: 687b ldr r3, [r7, #4]
8004fc4: 681b ldr r3, [r3, #0]
8004fc6: 461a mov r2, r3
8004fc8: 6bbb ldr r3, [r7, #56] ; 0x38
8004fca: 633b str r3, [r7, #48] ; 0x30
8004fcc: 62fa str r2, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004fce: 6af9 ldr r1, [r7, #44] ; 0x2c
8004fd0: 6b3a ldr r2, [r7, #48] ; 0x30
8004fd2: e841 2300 strex r3, r2, [r1]
8004fd6: 62bb str r3, [r7, #40] ; 0x28
return(result);
8004fd8: 6abb ldr r3, [r7, #40] ; 0x28
8004fda: 2b00 cmp r3, #0
8004fdc: d1e6 bne.n 8004fac <UART_TxISR_16BIT+0x1c>
#endif /* USART_CR1_FIFOEN */
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8004fde: 687b ldr r3, [r7, #4]
8004fe0: 681b ldr r3, [r3, #0]
8004fe2: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004fe4: 693b ldr r3, [r7, #16]
8004fe6: e853 3f00 ldrex r3, [r3]
8004fea: 60fb str r3, [r7, #12]
return(result);
8004fec: 68fb ldr r3, [r7, #12]
8004fee: f043 0340 orr.w r3, r3, #64 ; 0x40
8004ff2: 637b str r3, [r7, #52] ; 0x34
8004ff4: 687b ldr r3, [r7, #4]
8004ff6: 681b ldr r3, [r3, #0]
8004ff8: 461a mov r2, r3
8004ffa: 6b7b ldr r3, [r7, #52] ; 0x34
8004ffc: 61fb str r3, [r7, #28]
8004ffe: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005000: 69b9 ldr r1, [r7, #24]
8005002: 69fa ldr r2, [r7, #28]
8005004: e841 2300 strex r3, r2, [r1]
8005008: 617b str r3, [r7, #20]
return(result);
800500a: 697b ldr r3, [r7, #20]
800500c: 2b00 cmp r3, #0
800500e: d1e6 bne.n 8004fde <UART_TxISR_16BIT+0x4e>
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
}
}
}
8005010: e018 b.n 8005044 <UART_TxISR_16BIT+0xb4>
tmp = (const uint16_t *) huart->pTxBuffPtr;
8005012: 687b ldr r3, [r7, #4]
8005014: 6cdb ldr r3, [r3, #76] ; 0x4c
8005016: 63fb str r3, [r7, #60] ; 0x3c
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
8005018: 6bfb ldr r3, [r7, #60] ; 0x3c
800501a: 881a ldrh r2, [r3, #0]
800501c: 687b ldr r3, [r7, #4]
800501e: 681b ldr r3, [r3, #0]
8005020: f3c2 0208 ubfx r2, r2, #0, #9
8005024: b292 uxth r2, r2
8005026: 851a strh r2, [r3, #40] ; 0x28
huart->pTxBuffPtr += 2U;
8005028: 687b ldr r3, [r7, #4]
800502a: 6cdb ldr r3, [r3, #76] ; 0x4c
800502c: 1c9a adds r2, r3, #2
800502e: 687b ldr r3, [r7, #4]
8005030: 64da str r2, [r3, #76] ; 0x4c
huart->TxXferCount--;
8005032: 687b ldr r3, [r7, #4]
8005034: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8005038: b29b uxth r3, r3
800503a: 3b01 subs r3, #1
800503c: b29a uxth r2, r3
800503e: 687b ldr r3, [r7, #4]
8005040: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
}
8005044: bf00 nop
8005046: 3744 adds r7, #68 ; 0x44
8005048: 46bd mov sp, r7
800504a: f85d 7b04 ldr.w r7, [sp], #4
800504e: 4770 bx lr
08005050 <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8005050: b580 push {r7, lr}
8005052: b088 sub sp, #32
8005054: af00 add r7, sp, #0
8005056: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8005058: 687b ldr r3, [r7, #4]
800505a: 681b ldr r3, [r3, #0]
800505c: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800505e: 68fb ldr r3, [r7, #12]
8005060: e853 3f00 ldrex r3, [r3]
8005064: 60bb str r3, [r7, #8]
return(result);
8005066: 68bb ldr r3, [r7, #8]
8005068: f023 0340 bic.w r3, r3, #64 ; 0x40
800506c: 61fb str r3, [r7, #28]
800506e: 687b ldr r3, [r7, #4]
8005070: 681b ldr r3, [r3, #0]
8005072: 461a mov r2, r3
8005074: 69fb ldr r3, [r7, #28]
8005076: 61bb str r3, [r7, #24]
8005078: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800507a: 6979 ldr r1, [r7, #20]
800507c: 69ba ldr r2, [r7, #24]
800507e: e841 2300 strex r3, r2, [r1]
8005082: 613b str r3, [r7, #16]
return(result);
8005084: 693b ldr r3, [r7, #16]
8005086: 2b00 cmp r3, #0
8005088: d1e6 bne.n 8005058 <UART_EndTransmit_IT+0x8>
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800508a: 687b ldr r3, [r7, #4]
800508c: 2220 movs r2, #32
800508e: 67da str r2, [r3, #124] ; 0x7c
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
8005090: 687b ldr r3, [r7, #4]
8005092: 2200 movs r2, #0
8005094: 66da str r2, [r3, #108] ; 0x6c
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8005096: 6878 ldr r0, [r7, #4]
8005098: f7ff f9be bl 8004418 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800509c: bf00 nop
800509e: 3720 adds r7, #32
80050a0: 46bd mov sp, r7
80050a2: bd80 pop {r7, pc}
080050a4 <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
80050a4: b580 push {r7, lr}
80050a6: b09c sub sp, #112 ; 0x70
80050a8: af00 add r7, sp, #0
80050aa: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
80050ac: 687b ldr r3, [r7, #4]
80050ae: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
80050b2: f8a7 306e strh.w r3, [r7, #110] ; 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
80050b6: 687b ldr r3, [r7, #4]
80050b8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80050bc: 2b22 cmp r3, #34 ; 0x22
80050be: f040 80be bne.w 800523e <UART_RxISR_8BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
80050c2: 687b ldr r3, [r7, #4]
80050c4: 681b ldr r3, [r3, #0]
80050c6: 8c9b ldrh r3, [r3, #36] ; 0x24
80050c8: f8a7 306c strh.w r3, [r7, #108] ; 0x6c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
80050cc: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c
80050d0: b2d9 uxtb r1, r3
80050d2: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e
80050d6: b2da uxtb r2, r3
80050d8: 687b ldr r3, [r7, #4]
80050da: 6d5b ldr r3, [r3, #84] ; 0x54
80050dc: 400a ands r2, r1
80050de: b2d2 uxtb r2, r2
80050e0: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
80050e2: 687b ldr r3, [r7, #4]
80050e4: 6d5b ldr r3, [r3, #84] ; 0x54
80050e6: 1c5a adds r2, r3, #1
80050e8: 687b ldr r3, [r7, #4]
80050ea: 655a str r2, [r3, #84] ; 0x54
huart->RxXferCount--;
80050ec: 687b ldr r3, [r7, #4]
80050ee: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
80050f2: b29b uxth r3, r3
80050f4: 3b01 subs r3, #1
80050f6: b29a uxth r2, r3
80050f8: 687b ldr r3, [r7, #4]
80050fa: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
if (huart->RxXferCount == 0U)
80050fe: 687b ldr r3, [r7, #4]
8005100: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
8005104: b29b uxth r3, r3
8005106: 2b00 cmp r3, #0
8005108: f040 80a3 bne.w 8005252 <UART_RxISR_8BIT+0x1ae>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800510c: 687b ldr r3, [r7, #4]
800510e: 681b ldr r3, [r3, #0]
8005110: 64fb str r3, [r7, #76] ; 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005112: 6cfb ldr r3, [r7, #76] ; 0x4c
8005114: e853 3f00 ldrex r3, [r3]
8005118: 64bb str r3, [r7, #72] ; 0x48
return(result);
800511a: 6cbb ldr r3, [r7, #72] ; 0x48
800511c: f423 7390 bic.w r3, r3, #288 ; 0x120
8005120: 66bb str r3, [r7, #104] ; 0x68
8005122: 687b ldr r3, [r7, #4]
8005124: 681b ldr r3, [r3, #0]
8005126: 461a mov r2, r3
8005128: 6ebb ldr r3, [r7, #104] ; 0x68
800512a: 65bb str r3, [r7, #88] ; 0x58
800512c: 657a str r2, [r7, #84] ; 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800512e: 6d79 ldr r1, [r7, #84] ; 0x54
8005130: 6dba ldr r2, [r7, #88] ; 0x58
8005132: e841 2300 strex r3, r2, [r1]
8005136: 653b str r3, [r7, #80] ; 0x50
return(result);
8005138: 6d3b ldr r3, [r7, #80] ; 0x50
800513a: 2b00 cmp r3, #0
800513c: d1e6 bne.n 800510c <UART_RxISR_8BIT+0x68>
#endif /* USART_CR1_FIFOEN */
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800513e: 687b ldr r3, [r7, #4]
8005140: 681b ldr r3, [r3, #0]
8005142: 3308 adds r3, #8
8005144: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005146: 6bbb ldr r3, [r7, #56] ; 0x38
8005148: e853 3f00 ldrex r3, [r3]
800514c: 637b str r3, [r7, #52] ; 0x34
return(result);
800514e: 6b7b ldr r3, [r7, #52] ; 0x34
8005150: f023 0301 bic.w r3, r3, #1
8005154: 667b str r3, [r7, #100] ; 0x64
8005156: 687b ldr r3, [r7, #4]
8005158: 681b ldr r3, [r3, #0]
800515a: 3308 adds r3, #8
800515c: 6e7a ldr r2, [r7, #100] ; 0x64
800515e: 647a str r2, [r7, #68] ; 0x44
8005160: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005162: 6c39 ldr r1, [r7, #64] ; 0x40
8005164: 6c7a ldr r2, [r7, #68] ; 0x44
8005166: e841 2300 strex r3, r2, [r1]
800516a: 63fb str r3, [r7, #60] ; 0x3c
return(result);
800516c: 6bfb ldr r3, [r7, #60] ; 0x3c
800516e: 2b00 cmp r3, #0
8005170: d1e5 bne.n 800513e <UART_RxISR_8BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005172: 687b ldr r3, [r7, #4]
8005174: 2220 movs r2, #32
8005176: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Clear RxISR function pointer */
huart->RxISR = NULL;
800517a: 687b ldr r3, [r7, #4]
800517c: 2200 movs r2, #0
800517e: 669a str r2, [r3, #104] ; 0x68
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005180: 687b ldr r3, [r7, #4]
8005182: 2200 movs r2, #0
8005184: 665a str r2, [r3, #100] ; 0x64
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8005186: 687b ldr r3, [r7, #4]
8005188: 681b ldr r3, [r3, #0]
800518a: 4a34 ldr r2, [pc, #208] ; (800525c <UART_RxISR_8BIT+0x1b8>)
800518c: 4293 cmp r3, r2
800518e: d01f beq.n 80051d0 <UART_RxISR_8BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8005190: 687b ldr r3, [r7, #4]
8005192: 681b ldr r3, [r3, #0]
8005194: 685b ldr r3, [r3, #4]
8005196: f403 0300 and.w r3, r3, #8388608 ; 0x800000
800519a: 2b00 cmp r3, #0
800519c: d018 beq.n 80051d0 <UART_RxISR_8BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
800519e: 687b ldr r3, [r7, #4]
80051a0: 681b ldr r3, [r3, #0]
80051a2: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80051a4: 6a7b ldr r3, [r7, #36] ; 0x24
80051a6: e853 3f00 ldrex r3, [r3]
80051aa: 623b str r3, [r7, #32]
return(result);
80051ac: 6a3b ldr r3, [r7, #32]
80051ae: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
80051b2: 663b str r3, [r7, #96] ; 0x60
80051b4: 687b ldr r3, [r7, #4]
80051b6: 681b ldr r3, [r3, #0]
80051b8: 461a mov r2, r3
80051ba: 6e3b ldr r3, [r7, #96] ; 0x60
80051bc: 633b str r3, [r7, #48] ; 0x30
80051be: 62fa str r2, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80051c0: 6af9 ldr r1, [r7, #44] ; 0x2c
80051c2: 6b3a ldr r2, [r7, #48] ; 0x30
80051c4: e841 2300 strex r3, r2, [r1]
80051c8: 62bb str r3, [r7, #40] ; 0x28
return(result);
80051ca: 6abb ldr r3, [r7, #40] ; 0x28
80051cc: 2b00 cmp r3, #0
80051ce: d1e6 bne.n 800519e <UART_RxISR_8BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80051d0: 687b ldr r3, [r7, #4]
80051d2: 6e1b ldr r3, [r3, #96] ; 0x60
80051d4: 2b01 cmp r3, #1
80051d6: d12e bne.n 8005236 <UART_RxISR_8BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80051d8: 687b ldr r3, [r7, #4]
80051da: 2200 movs r2, #0
80051dc: 661a str r2, [r3, #96] ; 0x60
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80051de: 687b ldr r3, [r7, #4]
80051e0: 681b ldr r3, [r3, #0]
80051e2: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80051e4: 693b ldr r3, [r7, #16]
80051e6: e853 3f00 ldrex r3, [r3]
80051ea: 60fb str r3, [r7, #12]
return(result);
80051ec: 68fb ldr r3, [r7, #12]
80051ee: f023 0310 bic.w r3, r3, #16
80051f2: 65fb str r3, [r7, #92] ; 0x5c
80051f4: 687b ldr r3, [r7, #4]
80051f6: 681b ldr r3, [r3, #0]
80051f8: 461a mov r2, r3
80051fa: 6dfb ldr r3, [r7, #92] ; 0x5c
80051fc: 61fb str r3, [r7, #28]
80051fe: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005200: 69b9 ldr r1, [r7, #24]
8005202: 69fa ldr r2, [r7, #28]
8005204: e841 2300 strex r3, r2, [r1]
8005208: 617b str r3, [r7, #20]
return(result);
800520a: 697b ldr r3, [r7, #20]
800520c: 2b00 cmp r3, #0
800520e: d1e6 bne.n 80051de <UART_RxISR_8BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8005210: 687b ldr r3, [r7, #4]
8005212: 681b ldr r3, [r3, #0]
8005214: 69db ldr r3, [r3, #28]
8005216: f003 0310 and.w r3, r3, #16
800521a: 2b10 cmp r3, #16
800521c: d103 bne.n 8005226 <UART_RxISR_8BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800521e: 687b ldr r3, [r7, #4]
8005220: 681b ldr r3, [r3, #0]
8005222: 2210 movs r2, #16
8005224: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8005226: 687b ldr r3, [r7, #4]
8005228: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
800522c: 4619 mov r1, r3
800522e: 6878 ldr r0, [r7, #4]
8005230: f7fb fa20 bl 8000674 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8005234: e00d b.n 8005252 <UART_RxISR_8BIT+0x1ae>
HAL_UART_RxCpltCallback(huart);
8005236: 6878 ldr r0, [r7, #4]
8005238: f7fb fa06 bl 8000648 <HAL_UART_RxCpltCallback>
}
800523c: e009 b.n 8005252 <UART_RxISR_8BIT+0x1ae>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
800523e: 687b ldr r3, [r7, #4]
8005240: 681b ldr r3, [r3, #0]
8005242: 8b1b ldrh r3, [r3, #24]
8005244: b29a uxth r2, r3
8005246: 687b ldr r3, [r7, #4]
8005248: 681b ldr r3, [r3, #0]
800524a: f042 0208 orr.w r2, r2, #8
800524e: b292 uxth r2, r2
8005250: 831a strh r2, [r3, #24]
}
8005252: bf00 nop
8005254: 3770 adds r7, #112 ; 0x70
8005256: 46bd mov sp, r7
8005258: bd80 pop {r7, pc}
800525a: bf00 nop
800525c: 40008000 .word 0x40008000
08005260 <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
8005260: b580 push {r7, lr}
8005262: b09c sub sp, #112 ; 0x70
8005264: af00 add r7, sp, #0
8005266: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8005268: 687b ldr r3, [r7, #4]
800526a: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
800526e: f8a7 306e strh.w r3, [r7, #110] ; 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8005272: 687b ldr r3, [r7, #4]
8005274: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8005278: 2b22 cmp r3, #34 ; 0x22
800527a: f040 80be bne.w 80053fa <UART_RxISR_16BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
800527e: 687b ldr r3, [r7, #4]
8005280: 681b ldr r3, [r3, #0]
8005282: 8c9b ldrh r3, [r3, #36] ; 0x24
8005284: f8a7 306c strh.w r3, [r7, #108] ; 0x6c
tmp = (uint16_t *) huart->pRxBuffPtr ;
8005288: 687b ldr r3, [r7, #4]
800528a: 6d5b ldr r3, [r3, #84] ; 0x54
800528c: 66bb str r3, [r7, #104] ; 0x68
*tmp = (uint16_t)(uhdata & uhMask);
800528e: f8b7 206c ldrh.w r2, [r7, #108] ; 0x6c
8005292: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e
8005296: 4013 ands r3, r2
8005298: b29a uxth r2, r3
800529a: 6ebb ldr r3, [r7, #104] ; 0x68
800529c: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
800529e: 687b ldr r3, [r7, #4]
80052a0: 6d5b ldr r3, [r3, #84] ; 0x54
80052a2: 1c9a adds r2, r3, #2
80052a4: 687b ldr r3, [r7, #4]
80052a6: 655a str r2, [r3, #84] ; 0x54
huart->RxXferCount--;
80052a8: 687b ldr r3, [r7, #4]
80052aa: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
80052ae: b29b uxth r3, r3
80052b0: 3b01 subs r3, #1
80052b2: b29a uxth r2, r3
80052b4: 687b ldr r3, [r7, #4]
80052b6: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
if (huart->RxXferCount == 0U)
80052ba: 687b ldr r3, [r7, #4]
80052bc: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
80052c0: b29b uxth r3, r3
80052c2: 2b00 cmp r3, #0
80052c4: f040 80a3 bne.w 800540e <UART_RxISR_16BIT+0x1ae>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80052c8: 687b ldr r3, [r7, #4]
80052ca: 681b ldr r3, [r3, #0]
80052cc: 64bb str r3, [r7, #72] ; 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80052ce: 6cbb ldr r3, [r7, #72] ; 0x48
80052d0: e853 3f00 ldrex r3, [r3]
80052d4: 647b str r3, [r7, #68] ; 0x44
return(result);
80052d6: 6c7b ldr r3, [r7, #68] ; 0x44
80052d8: f423 7390 bic.w r3, r3, #288 ; 0x120
80052dc: 667b str r3, [r7, #100] ; 0x64
80052de: 687b ldr r3, [r7, #4]
80052e0: 681b ldr r3, [r3, #0]
80052e2: 461a mov r2, r3
80052e4: 6e7b ldr r3, [r7, #100] ; 0x64
80052e6: 657b str r3, [r7, #84] ; 0x54
80052e8: 653a str r2, [r7, #80] ; 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80052ea: 6d39 ldr r1, [r7, #80] ; 0x50
80052ec: 6d7a ldr r2, [r7, #84] ; 0x54
80052ee: e841 2300 strex r3, r2, [r1]
80052f2: 64fb str r3, [r7, #76] ; 0x4c
return(result);
80052f4: 6cfb ldr r3, [r7, #76] ; 0x4c
80052f6: 2b00 cmp r3, #0
80052f8: d1e6 bne.n 80052c8 <UART_RxISR_16BIT+0x68>
#endif /* USART_CR1_FIFOEN */
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80052fa: 687b ldr r3, [r7, #4]
80052fc: 681b ldr r3, [r3, #0]
80052fe: 3308 adds r3, #8
8005300: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005302: 6b7b ldr r3, [r7, #52] ; 0x34
8005304: e853 3f00 ldrex r3, [r3]
8005308: 633b str r3, [r7, #48] ; 0x30
return(result);
800530a: 6b3b ldr r3, [r7, #48] ; 0x30
800530c: f023 0301 bic.w r3, r3, #1
8005310: 663b str r3, [r7, #96] ; 0x60
8005312: 687b ldr r3, [r7, #4]
8005314: 681b ldr r3, [r3, #0]
8005316: 3308 adds r3, #8
8005318: 6e3a ldr r2, [r7, #96] ; 0x60
800531a: 643a str r2, [r7, #64] ; 0x40
800531c: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800531e: 6bf9 ldr r1, [r7, #60] ; 0x3c
8005320: 6c3a ldr r2, [r7, #64] ; 0x40
8005322: e841 2300 strex r3, r2, [r1]
8005326: 63bb str r3, [r7, #56] ; 0x38
return(result);
8005328: 6bbb ldr r3, [r7, #56] ; 0x38
800532a: 2b00 cmp r3, #0
800532c: d1e5 bne.n 80052fa <UART_RxISR_16BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800532e: 687b ldr r3, [r7, #4]
8005330: 2220 movs r2, #32
8005332: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8005336: 687b ldr r3, [r7, #4]
8005338: 2200 movs r2, #0
800533a: 669a str r2, [r3, #104] ; 0x68
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
800533c: 687b ldr r3, [r7, #4]
800533e: 2200 movs r2, #0
8005340: 665a str r2, [r3, #100] ; 0x64
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8005342: 687b ldr r3, [r7, #4]
8005344: 681b ldr r3, [r3, #0]
8005346: 4a34 ldr r2, [pc, #208] ; (8005418 <UART_RxISR_16BIT+0x1b8>)
8005348: 4293 cmp r3, r2
800534a: d01f beq.n 800538c <UART_RxISR_16BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
800534c: 687b ldr r3, [r7, #4]
800534e: 681b ldr r3, [r3, #0]
8005350: 685b ldr r3, [r3, #4]
8005352: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8005356: 2b00 cmp r3, #0
8005358: d018 beq.n 800538c <UART_RxISR_16BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
800535a: 687b ldr r3, [r7, #4]
800535c: 681b ldr r3, [r3, #0]
800535e: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005360: 6a3b ldr r3, [r7, #32]
8005362: e853 3f00 ldrex r3, [r3]
8005366: 61fb str r3, [r7, #28]
return(result);
8005368: 69fb ldr r3, [r7, #28]
800536a: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
800536e: 65fb str r3, [r7, #92] ; 0x5c
8005370: 687b ldr r3, [r7, #4]
8005372: 681b ldr r3, [r3, #0]
8005374: 461a mov r2, r3
8005376: 6dfb ldr r3, [r7, #92] ; 0x5c
8005378: 62fb str r3, [r7, #44] ; 0x2c
800537a: 62ba str r2, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800537c: 6ab9 ldr r1, [r7, #40] ; 0x28
800537e: 6afa ldr r2, [r7, #44] ; 0x2c
8005380: e841 2300 strex r3, r2, [r1]
8005384: 627b str r3, [r7, #36] ; 0x24
return(result);
8005386: 6a7b ldr r3, [r7, #36] ; 0x24
8005388: 2b00 cmp r3, #0
800538a: d1e6 bne.n 800535a <UART_RxISR_16BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800538c: 687b ldr r3, [r7, #4]
800538e: 6e1b ldr r3, [r3, #96] ; 0x60
8005390: 2b01 cmp r3, #1
8005392: d12e bne.n 80053f2 <UART_RxISR_16BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005394: 687b ldr r3, [r7, #4]
8005396: 2200 movs r2, #0
8005398: 661a str r2, [r3, #96] ; 0x60
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800539a: 687b ldr r3, [r7, #4]
800539c: 681b ldr r3, [r3, #0]
800539e: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80053a0: 68fb ldr r3, [r7, #12]
80053a2: e853 3f00 ldrex r3, [r3]
80053a6: 60bb str r3, [r7, #8]
return(result);
80053a8: 68bb ldr r3, [r7, #8]
80053aa: f023 0310 bic.w r3, r3, #16
80053ae: 65bb str r3, [r7, #88] ; 0x58
80053b0: 687b ldr r3, [r7, #4]
80053b2: 681b ldr r3, [r3, #0]
80053b4: 461a mov r2, r3
80053b6: 6dbb ldr r3, [r7, #88] ; 0x58
80053b8: 61bb str r3, [r7, #24]
80053ba: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80053bc: 6979 ldr r1, [r7, #20]
80053be: 69ba ldr r2, [r7, #24]
80053c0: e841 2300 strex r3, r2, [r1]
80053c4: 613b str r3, [r7, #16]
return(result);
80053c6: 693b ldr r3, [r7, #16]
80053c8: 2b00 cmp r3, #0
80053ca: d1e6 bne.n 800539a <UART_RxISR_16BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
80053cc: 687b ldr r3, [r7, #4]
80053ce: 681b ldr r3, [r3, #0]
80053d0: 69db ldr r3, [r3, #28]
80053d2: f003 0310 and.w r3, r3, #16
80053d6: 2b10 cmp r3, #16
80053d8: d103 bne.n 80053e2 <UART_RxISR_16BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
80053da: 687b ldr r3, [r7, #4]
80053dc: 681b ldr r3, [r3, #0]
80053de: 2210 movs r2, #16
80053e0: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80053e2: 687b ldr r3, [r7, #4]
80053e4: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
80053e8: 4619 mov r1, r3
80053ea: 6878 ldr r0, [r7, #4]
80053ec: f7fb f942 bl 8000674 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
80053f0: e00d b.n 800540e <UART_RxISR_16BIT+0x1ae>
HAL_UART_RxCpltCallback(huart);
80053f2: 6878 ldr r0, [r7, #4]
80053f4: f7fb f928 bl 8000648 <HAL_UART_RxCpltCallback>
}
80053f8: e009 b.n 800540e <UART_RxISR_16BIT+0x1ae>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
80053fa: 687b ldr r3, [r7, #4]
80053fc: 681b ldr r3, [r3, #0]
80053fe: 8b1b ldrh r3, [r3, #24]
8005400: b29a uxth r2, r3
8005402: 687b ldr r3, [r7, #4]
8005404: 681b ldr r3, [r3, #0]
8005406: f042 0208 orr.w r2, r2, #8
800540a: b292 uxth r2, r2
800540c: 831a strh r2, [r3, #24]
}
800540e: bf00 nop
8005410: 3770 adds r7, #112 ; 0x70
8005412: 46bd mov sp, r7
8005414: bd80 pop {r7, pc}
8005416: bf00 nop
8005418: 40008000 .word 0x40008000
0800541c <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
800541c: b480 push {r7}
800541e: b083 sub sp, #12
8005420: af00 add r7, sp, #0
8005422: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8005424: bf00 nop
8005426: 370c adds r7, #12
8005428: 46bd mov sp, r7
800542a: f85d 7b04 ldr.w r7, [sp], #4
800542e: 4770 bx lr
08005430 <HAL_UARTEx_ReceiveToIdle_IT>:
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8005430: b580 push {r7, lr}
8005432: b08c sub sp, #48 ; 0x30
8005434: af00 add r7, sp, #0
8005436: 60f8 str r0, [r7, #12]
8005438: 60b9 str r1, [r7, #8]
800543a: 4613 mov r3, r2
800543c: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
800543e: 2300 movs r3, #0
8005440: f887 302f strb.w r3, [r7, #47] ; 0x2f
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8005444: 68fb ldr r3, [r7, #12]
8005446: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
800544a: 2b20 cmp r3, #32
800544c: d13b bne.n 80054c6 <HAL_UARTEx_ReceiveToIdle_IT+0x96>
{
if ((pData == NULL) || (Size == 0U))
800544e: 68bb ldr r3, [r7, #8]
8005450: 2b00 cmp r3, #0
8005452: d002 beq.n 800545a <HAL_UARTEx_ReceiveToIdle_IT+0x2a>
8005454: 88fb ldrh r3, [r7, #6]
8005456: 2b00 cmp r3, #0
8005458: d101 bne.n 800545e <HAL_UARTEx_ReceiveToIdle_IT+0x2e>
{
return HAL_ERROR;
800545a: 2301 movs r3, #1
800545c: e034 b.n 80054c8 <HAL_UARTEx_ReceiveToIdle_IT+0x98>
}
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
800545e: 68fb ldr r3, [r7, #12]
8005460: 2201 movs r2, #1
8005462: 661a str r2, [r3, #96] ; 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005464: 68fb ldr r3, [r7, #12]
8005466: 2200 movs r2, #0
8005468: 665a str r2, [r3, #100] ; 0x64
(void)UART_Start_Receive_IT(huart, pData, Size);
800546a: 88fb ldrh r3, [r7, #6]
800546c: 461a mov r2, r3
800546e: 68b9 ldr r1, [r7, #8]
8005470: 68f8 ldr r0, [r7, #12]
8005472: f7ff fbf1 bl 8004c58 <UART_Start_Receive_IT>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005476: 68fb ldr r3, [r7, #12]
8005478: 6e1b ldr r3, [r3, #96] ; 0x60
800547a: 2b01 cmp r3, #1
800547c: d11d bne.n 80054ba <HAL_UARTEx_ReceiveToIdle_IT+0x8a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800547e: 68fb ldr r3, [r7, #12]
8005480: 681b ldr r3, [r3, #0]
8005482: 2210 movs r2, #16
8005484: 621a str r2, [r3, #32]
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005486: 68fb ldr r3, [r7, #12]
8005488: 681b ldr r3, [r3, #0]
800548a: 61bb str r3, [r7, #24]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800548c: 69bb ldr r3, [r7, #24]
800548e: e853 3f00 ldrex r3, [r3]
8005492: 617b str r3, [r7, #20]
return(result);
8005494: 697b ldr r3, [r7, #20]
8005496: f043 0310 orr.w r3, r3, #16
800549a: 62bb str r3, [r7, #40] ; 0x28
800549c: 68fb ldr r3, [r7, #12]
800549e: 681b ldr r3, [r3, #0]
80054a0: 461a mov r2, r3
80054a2: 6abb ldr r3, [r7, #40] ; 0x28
80054a4: 627b str r3, [r7, #36] ; 0x24
80054a6: 623a str r2, [r7, #32]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80054a8: 6a39 ldr r1, [r7, #32]
80054aa: 6a7a ldr r2, [r7, #36] ; 0x24
80054ac: e841 2300 strex r3, r2, [r1]
80054b0: 61fb str r3, [r7, #28]
return(result);
80054b2: 69fb ldr r3, [r7, #28]
80054b4: 2b00 cmp r3, #0
80054b6: d1e6 bne.n 8005486 <HAL_UARTEx_ReceiveToIdle_IT+0x56>
80054b8: e002 b.n 80054c0 <HAL_UARTEx_ReceiveToIdle_IT+0x90>
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
80054ba: 2301 movs r3, #1
80054bc: f887 302f strb.w r3, [r7, #47] ; 0x2f
}
return status;
80054c0: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
80054c4: e000 b.n 80054c8 <HAL_UARTEx_ReceiveToIdle_IT+0x98>
}
else
{
return HAL_BUSY;
80054c6: 2302 movs r3, #2
}
}
80054c8: 4618 mov r0, r3
80054ca: 3730 adds r7, #48 ; 0x30
80054cc: 46bd mov sp, r7
80054ce: bd80 pop {r7, pc}
080054d0 <std>:
80054d0: 2300 movs r3, #0
80054d2: b510 push {r4, lr}
80054d4: 4604 mov r4, r0
80054d6: e9c0 3300 strd r3, r3, [r0]
80054da: e9c0 3304 strd r3, r3, [r0, #16]
80054de: 6083 str r3, [r0, #8]
80054e0: 8181 strh r1, [r0, #12]
80054e2: 6643 str r3, [r0, #100] ; 0x64
80054e4: 81c2 strh r2, [r0, #14]
80054e6: 6183 str r3, [r0, #24]
80054e8: 4619 mov r1, r3
80054ea: 2208 movs r2, #8
80054ec: 305c adds r0, #92 ; 0x5c
80054ee: f000 f9e5 bl 80058bc <memset>
80054f2: 4b0d ldr r3, [pc, #52] ; (8005528 <std+0x58>)
80054f4: 6263 str r3, [r4, #36] ; 0x24
80054f6: 4b0d ldr r3, [pc, #52] ; (800552c <std+0x5c>)
80054f8: 62a3 str r3, [r4, #40] ; 0x28
80054fa: 4b0d ldr r3, [pc, #52] ; (8005530 <std+0x60>)
80054fc: 62e3 str r3, [r4, #44] ; 0x2c
80054fe: 4b0d ldr r3, [pc, #52] ; (8005534 <std+0x64>)
8005500: 6323 str r3, [r4, #48] ; 0x30
8005502: 4b0d ldr r3, [pc, #52] ; (8005538 <std+0x68>)
8005504: 6224 str r4, [r4, #32]
8005506: 429c cmp r4, r3
8005508: d006 beq.n 8005518 <std+0x48>
800550a: f103 0268 add.w r2, r3, #104 ; 0x68
800550e: 4294 cmp r4, r2
8005510: d002 beq.n 8005518 <std+0x48>
8005512: 33d0 adds r3, #208 ; 0xd0
8005514: 429c cmp r4, r3
8005516: d105 bne.n 8005524 <std+0x54>
8005518: f104 0058 add.w r0, r4, #88 ; 0x58
800551c: e8bd 4010 ldmia.w sp!, {r4, lr}
8005520: f000 ba44 b.w 80059ac <__retarget_lock_init_recursive>
8005524: bd10 pop {r4, pc}
8005526: bf00 nop
8005528: 0800570d .word 0x0800570d
800552c: 0800572f .word 0x0800572f
8005530: 08005767 .word 0x08005767
8005534: 0800578b .word 0x0800578b
8005538: 200002ac .word 0x200002ac
0800553c <stdio_exit_handler>:
800553c: 4a02 ldr r2, [pc, #8] ; (8005548 <stdio_exit_handler+0xc>)
800553e: 4903 ldr r1, [pc, #12] ; (800554c <stdio_exit_handler+0x10>)
8005540: 4803 ldr r0, [pc, #12] ; (8005550 <stdio_exit_handler+0x14>)
8005542: f000 b869 b.w 8005618 <_fwalk_sglue>
8005546: bf00 nop
8005548: 20000010 .word 0x20000010
800554c: 08005cb1 .word 0x08005cb1
8005550: 2000001c .word 0x2000001c
08005554 <cleanup_stdio>:
8005554: 6841 ldr r1, [r0, #4]
8005556: 4b0c ldr r3, [pc, #48] ; (8005588 <cleanup_stdio+0x34>)
8005558: 4299 cmp r1, r3
800555a: b510 push {r4, lr}
800555c: 4604 mov r4, r0
800555e: d001 beq.n 8005564 <cleanup_stdio+0x10>
8005560: f000 fba6 bl 8005cb0 <_fflush_r>
8005564: 68a1 ldr r1, [r4, #8]
8005566: 4b09 ldr r3, [pc, #36] ; (800558c <cleanup_stdio+0x38>)
8005568: 4299 cmp r1, r3
800556a: d002 beq.n 8005572 <cleanup_stdio+0x1e>
800556c: 4620 mov r0, r4
800556e: f000 fb9f bl 8005cb0 <_fflush_r>
8005572: 68e1 ldr r1, [r4, #12]
8005574: 4b06 ldr r3, [pc, #24] ; (8005590 <cleanup_stdio+0x3c>)
8005576: 4299 cmp r1, r3
8005578: d004 beq.n 8005584 <cleanup_stdio+0x30>
800557a: 4620 mov r0, r4
800557c: e8bd 4010 ldmia.w sp!, {r4, lr}
8005580: f000 bb96 b.w 8005cb0 <_fflush_r>
8005584: bd10 pop {r4, pc}
8005586: bf00 nop
8005588: 200002ac .word 0x200002ac
800558c: 20000314 .word 0x20000314
8005590: 2000037c .word 0x2000037c
08005594 <global_stdio_init.part.0>:
8005594: b510 push {r4, lr}
8005596: 4b0b ldr r3, [pc, #44] ; (80055c4 <global_stdio_init.part.0+0x30>)
8005598: 4c0b ldr r4, [pc, #44] ; (80055c8 <global_stdio_init.part.0+0x34>)
800559a: 4a0c ldr r2, [pc, #48] ; (80055cc <global_stdio_init.part.0+0x38>)
800559c: 601a str r2, [r3, #0]
800559e: 4620 mov r0, r4
80055a0: 2200 movs r2, #0
80055a2: 2104 movs r1, #4
80055a4: f7ff ff94 bl 80054d0 <std>
80055a8: f104 0068 add.w r0, r4, #104 ; 0x68
80055ac: 2201 movs r2, #1
80055ae: 2109 movs r1, #9
80055b0: f7ff ff8e bl 80054d0 <std>
80055b4: f104 00d0 add.w r0, r4, #208 ; 0xd0
80055b8: 2202 movs r2, #2
80055ba: e8bd 4010 ldmia.w sp!, {r4, lr}
80055be: 2112 movs r1, #18
80055c0: f7ff bf86 b.w 80054d0 <std>
80055c4: 200003e4 .word 0x200003e4
80055c8: 200002ac .word 0x200002ac
80055cc: 0800553d .word 0x0800553d
080055d0 <__sfp_lock_acquire>:
80055d0: 4801 ldr r0, [pc, #4] ; (80055d8 <__sfp_lock_acquire+0x8>)
80055d2: f000 b9ec b.w 80059ae <__retarget_lock_acquire_recursive>
80055d6: bf00 nop
80055d8: 200003ed .word 0x200003ed
080055dc <__sfp_lock_release>:
80055dc: 4801 ldr r0, [pc, #4] ; (80055e4 <__sfp_lock_release+0x8>)
80055de: f000 b9e7 b.w 80059b0 <__retarget_lock_release_recursive>
80055e2: bf00 nop
80055e4: 200003ed .word 0x200003ed
080055e8 <__sinit>:
80055e8: b510 push {r4, lr}
80055ea: 4604 mov r4, r0
80055ec: f7ff fff0 bl 80055d0 <__sfp_lock_acquire>
80055f0: 6a23 ldr r3, [r4, #32]
80055f2: b11b cbz r3, 80055fc <__sinit+0x14>
80055f4: e8bd 4010 ldmia.w sp!, {r4, lr}
80055f8: f7ff bff0 b.w 80055dc <__sfp_lock_release>
80055fc: 4b04 ldr r3, [pc, #16] ; (8005610 <__sinit+0x28>)
80055fe: 6223 str r3, [r4, #32]
8005600: 4b04 ldr r3, [pc, #16] ; (8005614 <__sinit+0x2c>)
8005602: 681b ldr r3, [r3, #0]
8005604: 2b00 cmp r3, #0
8005606: d1f5 bne.n 80055f4 <__sinit+0xc>
8005608: f7ff ffc4 bl 8005594 <global_stdio_init.part.0>
800560c: e7f2 b.n 80055f4 <__sinit+0xc>
800560e: bf00 nop
8005610: 08005555 .word 0x08005555
8005614: 200003e4 .word 0x200003e4
08005618 <_fwalk_sglue>:
8005618: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800561c: 4607 mov r7, r0
800561e: 4688 mov r8, r1
8005620: 4614 mov r4, r2
8005622: 2600 movs r6, #0
8005624: e9d4 9501 ldrd r9, r5, [r4, #4]
8005628: f1b9 0901 subs.w r9, r9, #1
800562c: d505 bpl.n 800563a <_fwalk_sglue+0x22>
800562e: 6824 ldr r4, [r4, #0]
8005630: 2c00 cmp r4, #0
8005632: d1f7 bne.n 8005624 <_fwalk_sglue+0xc>
8005634: 4630 mov r0, r6
8005636: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800563a: 89ab ldrh r3, [r5, #12]
800563c: 2b01 cmp r3, #1
800563e: d907 bls.n 8005650 <_fwalk_sglue+0x38>
8005640: f9b5 300e ldrsh.w r3, [r5, #14]
8005644: 3301 adds r3, #1
8005646: d003 beq.n 8005650 <_fwalk_sglue+0x38>
8005648: 4629 mov r1, r5
800564a: 4638 mov r0, r7
800564c: 47c0 blx r8
800564e: 4306 orrs r6, r0
8005650: 3568 adds r5, #104 ; 0x68
8005652: e7e9 b.n 8005628 <_fwalk_sglue+0x10>
08005654 <_puts_r>:
8005654: 6a03 ldr r3, [r0, #32]
8005656: b570 push {r4, r5, r6, lr}
8005658: 6884 ldr r4, [r0, #8]
800565a: 4605 mov r5, r0
800565c: 460e mov r6, r1
800565e: b90b cbnz r3, 8005664 <_puts_r+0x10>
8005660: f7ff ffc2 bl 80055e8 <__sinit>
8005664: 6e63 ldr r3, [r4, #100] ; 0x64
8005666: 07db lsls r3, r3, #31
8005668: d405 bmi.n 8005676 <_puts_r+0x22>
800566a: 89a3 ldrh r3, [r4, #12]
800566c: 0598 lsls r0, r3, #22
800566e: d402 bmi.n 8005676 <_puts_r+0x22>
8005670: 6da0 ldr r0, [r4, #88] ; 0x58
8005672: f000 f99c bl 80059ae <__retarget_lock_acquire_recursive>
8005676: 89a3 ldrh r3, [r4, #12]
8005678: 0719 lsls r1, r3, #28
800567a: d513 bpl.n 80056a4 <_puts_r+0x50>
800567c: 6923 ldr r3, [r4, #16]
800567e: b18b cbz r3, 80056a4 <_puts_r+0x50>
8005680: 3e01 subs r6, #1
8005682: 68a3 ldr r3, [r4, #8]
8005684: f816 1f01 ldrb.w r1, [r6, #1]!
8005688: 3b01 subs r3, #1
800568a: 60a3 str r3, [r4, #8]
800568c: b9e9 cbnz r1, 80056ca <_puts_r+0x76>
800568e: 2b00 cmp r3, #0
8005690: da2e bge.n 80056f0 <_puts_r+0x9c>
8005692: 4622 mov r2, r4
8005694: 210a movs r1, #10
8005696: 4628 mov r0, r5
8005698: f000 f87b bl 8005792 <__swbuf_r>
800569c: 3001 adds r0, #1
800569e: d007 beq.n 80056b0 <_puts_r+0x5c>
80056a0: 250a movs r5, #10
80056a2: e007 b.n 80056b4 <_puts_r+0x60>
80056a4: 4621 mov r1, r4
80056a6: 4628 mov r0, r5
80056a8: f000 f8b0 bl 800580c <__swsetup_r>
80056ac: 2800 cmp r0, #0
80056ae: d0e7 beq.n 8005680 <_puts_r+0x2c>
80056b0: f04f 35ff mov.w r5, #4294967295
80056b4: 6e63 ldr r3, [r4, #100] ; 0x64
80056b6: 07da lsls r2, r3, #31
80056b8: d405 bmi.n 80056c6 <_puts_r+0x72>
80056ba: 89a3 ldrh r3, [r4, #12]
80056bc: 059b lsls r3, r3, #22
80056be: d402 bmi.n 80056c6 <_puts_r+0x72>
80056c0: 6da0 ldr r0, [r4, #88] ; 0x58
80056c2: f000 f975 bl 80059b0 <__retarget_lock_release_recursive>
80056c6: 4628 mov r0, r5
80056c8: bd70 pop {r4, r5, r6, pc}
80056ca: 2b00 cmp r3, #0
80056cc: da04 bge.n 80056d8 <_puts_r+0x84>
80056ce: 69a2 ldr r2, [r4, #24]
80056d0: 429a cmp r2, r3
80056d2: dc06 bgt.n 80056e2 <_puts_r+0x8e>
80056d4: 290a cmp r1, #10
80056d6: d004 beq.n 80056e2 <_puts_r+0x8e>
80056d8: 6823 ldr r3, [r4, #0]
80056da: 1c5a adds r2, r3, #1
80056dc: 6022 str r2, [r4, #0]
80056de: 7019 strb r1, [r3, #0]
80056e0: e7cf b.n 8005682 <_puts_r+0x2e>
80056e2: 4622 mov r2, r4
80056e4: 4628 mov r0, r5
80056e6: f000 f854 bl 8005792 <__swbuf_r>
80056ea: 3001 adds r0, #1
80056ec: d1c9 bne.n 8005682 <_puts_r+0x2e>
80056ee: e7df b.n 80056b0 <_puts_r+0x5c>
80056f0: 6823 ldr r3, [r4, #0]
80056f2: 250a movs r5, #10
80056f4: 1c5a adds r2, r3, #1
80056f6: 6022 str r2, [r4, #0]
80056f8: 701d strb r5, [r3, #0]
80056fa: e7db b.n 80056b4 <_puts_r+0x60>
080056fc <puts>:
80056fc: 4b02 ldr r3, [pc, #8] ; (8005708 <puts+0xc>)
80056fe: 4601 mov r1, r0
8005700: 6818 ldr r0, [r3, #0]
8005702: f7ff bfa7 b.w 8005654 <_puts_r>
8005706: bf00 nop
8005708: 20000068 .word 0x20000068
0800570c <__sread>:
800570c: b510 push {r4, lr}
800570e: 460c mov r4, r1
8005710: f9b1 100e ldrsh.w r1, [r1, #14]
8005714: f000 f8fc bl 8005910 <_read_r>
8005718: 2800 cmp r0, #0
800571a: bfab itete ge
800571c: 6d63 ldrge r3, [r4, #84] ; 0x54
800571e: 89a3 ldrhlt r3, [r4, #12]
8005720: 181b addge r3, r3, r0
8005722: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
8005726: bfac ite ge
8005728: 6563 strge r3, [r4, #84] ; 0x54
800572a: 81a3 strhlt r3, [r4, #12]
800572c: bd10 pop {r4, pc}
0800572e <__swrite>:
800572e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8005732: 461f mov r7, r3
8005734: 898b ldrh r3, [r1, #12]
8005736: 05db lsls r3, r3, #23
8005738: 4605 mov r5, r0
800573a: 460c mov r4, r1
800573c: 4616 mov r6, r2
800573e: d505 bpl.n 800574c <__swrite+0x1e>
8005740: f9b1 100e ldrsh.w r1, [r1, #14]
8005744: 2302 movs r3, #2
8005746: 2200 movs r2, #0
8005748: f000 f8d0 bl 80058ec <_lseek_r>
800574c: 89a3 ldrh r3, [r4, #12]
800574e: f9b4 100e ldrsh.w r1, [r4, #14]
8005752: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8005756: 81a3 strh r3, [r4, #12]
8005758: 4632 mov r2, r6
800575a: 463b mov r3, r7
800575c: 4628 mov r0, r5
800575e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
8005762: f000 b8e7 b.w 8005934 <_write_r>
08005766 <__sseek>:
8005766: b510 push {r4, lr}
8005768: 460c mov r4, r1
800576a: f9b1 100e ldrsh.w r1, [r1, #14]
800576e: f000 f8bd bl 80058ec <_lseek_r>
8005772: 1c43 adds r3, r0, #1
8005774: 89a3 ldrh r3, [r4, #12]
8005776: bf15 itete ne
8005778: 6560 strne r0, [r4, #84] ; 0x54
800577a: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
800577e: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
8005782: 81a3 strheq r3, [r4, #12]
8005784: bf18 it ne
8005786: 81a3 strhne r3, [r4, #12]
8005788: bd10 pop {r4, pc}
0800578a <__sclose>:
800578a: f9b1 100e ldrsh.w r1, [r1, #14]
800578e: f000 b89d b.w 80058cc <_close_r>
08005792 <__swbuf_r>:
8005792: b5f8 push {r3, r4, r5, r6, r7, lr}
8005794: 460e mov r6, r1
8005796: 4614 mov r4, r2
8005798: 4605 mov r5, r0
800579a: b118 cbz r0, 80057a4 <__swbuf_r+0x12>
800579c: 6a03 ldr r3, [r0, #32]
800579e: b90b cbnz r3, 80057a4 <__swbuf_r+0x12>
80057a0: f7ff ff22 bl 80055e8 <__sinit>
80057a4: 69a3 ldr r3, [r4, #24]
80057a6: 60a3 str r3, [r4, #8]
80057a8: 89a3 ldrh r3, [r4, #12]
80057aa: 071a lsls r2, r3, #28
80057ac: d525 bpl.n 80057fa <__swbuf_r+0x68>
80057ae: 6923 ldr r3, [r4, #16]
80057b0: b31b cbz r3, 80057fa <__swbuf_r+0x68>
80057b2: 6823 ldr r3, [r4, #0]
80057b4: 6922 ldr r2, [r4, #16]
80057b6: 1a98 subs r0, r3, r2
80057b8: 6963 ldr r3, [r4, #20]
80057ba: b2f6 uxtb r6, r6
80057bc: 4283 cmp r3, r0
80057be: 4637 mov r7, r6
80057c0: dc04 bgt.n 80057cc <__swbuf_r+0x3a>
80057c2: 4621 mov r1, r4
80057c4: 4628 mov r0, r5
80057c6: f000 fa73 bl 8005cb0 <_fflush_r>
80057ca: b9e0 cbnz r0, 8005806 <__swbuf_r+0x74>
80057cc: 68a3 ldr r3, [r4, #8]
80057ce: 3b01 subs r3, #1
80057d0: 60a3 str r3, [r4, #8]
80057d2: 6823 ldr r3, [r4, #0]
80057d4: 1c5a adds r2, r3, #1
80057d6: 6022 str r2, [r4, #0]
80057d8: 701e strb r6, [r3, #0]
80057da: 6962 ldr r2, [r4, #20]
80057dc: 1c43 adds r3, r0, #1
80057de: 429a cmp r2, r3
80057e0: d004 beq.n 80057ec <__swbuf_r+0x5a>
80057e2: 89a3 ldrh r3, [r4, #12]
80057e4: 07db lsls r3, r3, #31
80057e6: d506 bpl.n 80057f6 <__swbuf_r+0x64>
80057e8: 2e0a cmp r6, #10
80057ea: d104 bne.n 80057f6 <__swbuf_r+0x64>
80057ec: 4621 mov r1, r4
80057ee: 4628 mov r0, r5
80057f0: f000 fa5e bl 8005cb0 <_fflush_r>
80057f4: b938 cbnz r0, 8005806 <__swbuf_r+0x74>
80057f6: 4638 mov r0, r7
80057f8: bdf8 pop {r3, r4, r5, r6, r7, pc}
80057fa: 4621 mov r1, r4
80057fc: 4628 mov r0, r5
80057fe: f000 f805 bl 800580c <__swsetup_r>
8005802: 2800 cmp r0, #0
8005804: d0d5 beq.n 80057b2 <__swbuf_r+0x20>
8005806: f04f 37ff mov.w r7, #4294967295
800580a: e7f4 b.n 80057f6 <__swbuf_r+0x64>
0800580c <__swsetup_r>:
800580c: b538 push {r3, r4, r5, lr}
800580e: 4b2a ldr r3, [pc, #168] ; (80058b8 <__swsetup_r+0xac>)
8005810: 4605 mov r5, r0
8005812: 6818 ldr r0, [r3, #0]
8005814: 460c mov r4, r1
8005816: b118 cbz r0, 8005820 <__swsetup_r+0x14>
8005818: 6a03 ldr r3, [r0, #32]
800581a: b90b cbnz r3, 8005820 <__swsetup_r+0x14>
800581c: f7ff fee4 bl 80055e8 <__sinit>
8005820: 89a3 ldrh r3, [r4, #12]
8005822: f9b4 200c ldrsh.w r2, [r4, #12]
8005826: 0718 lsls r0, r3, #28
8005828: d422 bmi.n 8005870 <__swsetup_r+0x64>
800582a: 06d9 lsls r1, r3, #27
800582c: d407 bmi.n 800583e <__swsetup_r+0x32>
800582e: 2309 movs r3, #9
8005830: 602b str r3, [r5, #0]
8005832: f042 0340 orr.w r3, r2, #64 ; 0x40
8005836: 81a3 strh r3, [r4, #12]
8005838: f04f 30ff mov.w r0, #4294967295
800583c: e034 b.n 80058a8 <__swsetup_r+0x9c>
800583e: 0758 lsls r0, r3, #29
8005840: d512 bpl.n 8005868 <__swsetup_r+0x5c>
8005842: 6b61 ldr r1, [r4, #52] ; 0x34
8005844: b141 cbz r1, 8005858 <__swsetup_r+0x4c>
8005846: f104 0344 add.w r3, r4, #68 ; 0x44
800584a: 4299 cmp r1, r3
800584c: d002 beq.n 8005854 <__swsetup_r+0x48>
800584e: 4628 mov r0, r5
8005850: f000 f8b0 bl 80059b4 <_free_r>
8005854: 2300 movs r3, #0
8005856: 6363 str r3, [r4, #52] ; 0x34
8005858: 89a3 ldrh r3, [r4, #12]
800585a: f023 0324 bic.w r3, r3, #36 ; 0x24
800585e: 81a3 strh r3, [r4, #12]
8005860: 2300 movs r3, #0
8005862: 6063 str r3, [r4, #4]
8005864: 6923 ldr r3, [r4, #16]
8005866: 6023 str r3, [r4, #0]
8005868: 89a3 ldrh r3, [r4, #12]
800586a: f043 0308 orr.w r3, r3, #8
800586e: 81a3 strh r3, [r4, #12]
8005870: 6923 ldr r3, [r4, #16]
8005872: b94b cbnz r3, 8005888 <__swsetup_r+0x7c>
8005874: 89a3 ldrh r3, [r4, #12]
8005876: f403 7320 and.w r3, r3, #640 ; 0x280
800587a: f5b3 7f00 cmp.w r3, #512 ; 0x200
800587e: d003 beq.n 8005888 <__swsetup_r+0x7c>
8005880: 4621 mov r1, r4
8005882: 4628 mov r0, r5
8005884: f000 fa62 bl 8005d4c <__smakebuf_r>
8005888: 89a0 ldrh r0, [r4, #12]
800588a: f9b4 200c ldrsh.w r2, [r4, #12]
800588e: f010 0301 ands.w r3, r0, #1
8005892: d00a beq.n 80058aa <__swsetup_r+0x9e>
8005894: 2300 movs r3, #0
8005896: 60a3 str r3, [r4, #8]
8005898: 6963 ldr r3, [r4, #20]
800589a: 425b negs r3, r3
800589c: 61a3 str r3, [r4, #24]
800589e: 6923 ldr r3, [r4, #16]
80058a0: b943 cbnz r3, 80058b4 <__swsetup_r+0xa8>
80058a2: f010 0080 ands.w r0, r0, #128 ; 0x80
80058a6: d1c4 bne.n 8005832 <__swsetup_r+0x26>
80058a8: bd38 pop {r3, r4, r5, pc}
80058aa: 0781 lsls r1, r0, #30
80058ac: bf58 it pl
80058ae: 6963 ldrpl r3, [r4, #20]
80058b0: 60a3 str r3, [r4, #8]
80058b2: e7f4 b.n 800589e <__swsetup_r+0x92>
80058b4: 2000 movs r0, #0
80058b6: e7f7 b.n 80058a8 <__swsetup_r+0x9c>
80058b8: 20000068 .word 0x20000068
080058bc <memset>:
80058bc: 4402 add r2, r0
80058be: 4603 mov r3, r0
80058c0: 4293 cmp r3, r2
80058c2: d100 bne.n 80058c6 <memset+0xa>
80058c4: 4770 bx lr
80058c6: f803 1b01 strb.w r1, [r3], #1
80058ca: e7f9 b.n 80058c0 <memset+0x4>
080058cc <_close_r>:
80058cc: b538 push {r3, r4, r5, lr}
80058ce: 4d06 ldr r5, [pc, #24] ; (80058e8 <_close_r+0x1c>)
80058d0: 2300 movs r3, #0
80058d2: 4604 mov r4, r0
80058d4: 4608 mov r0, r1
80058d6: 602b str r3, [r5, #0]
80058d8: f7fb fb37 bl 8000f4a <_close>
80058dc: 1c43 adds r3, r0, #1
80058de: d102 bne.n 80058e6 <_close_r+0x1a>
80058e0: 682b ldr r3, [r5, #0]
80058e2: b103 cbz r3, 80058e6 <_close_r+0x1a>
80058e4: 6023 str r3, [r4, #0]
80058e6: bd38 pop {r3, r4, r5, pc}
80058e8: 200003e8 .word 0x200003e8
080058ec <_lseek_r>:
80058ec: b538 push {r3, r4, r5, lr}
80058ee: 4d07 ldr r5, [pc, #28] ; (800590c <_lseek_r+0x20>)
80058f0: 4604 mov r4, r0
80058f2: 4608 mov r0, r1
80058f4: 4611 mov r1, r2
80058f6: 2200 movs r2, #0
80058f8: 602a str r2, [r5, #0]
80058fa: 461a mov r2, r3
80058fc: f7fb fb4c bl 8000f98 <_lseek>
8005900: 1c43 adds r3, r0, #1
8005902: d102 bne.n 800590a <_lseek_r+0x1e>
8005904: 682b ldr r3, [r5, #0]
8005906: b103 cbz r3, 800590a <_lseek_r+0x1e>
8005908: 6023 str r3, [r4, #0]
800590a: bd38 pop {r3, r4, r5, pc}
800590c: 200003e8 .word 0x200003e8
08005910 <_read_r>:
8005910: b538 push {r3, r4, r5, lr}
8005912: 4d07 ldr r5, [pc, #28] ; (8005930 <_read_r+0x20>)
8005914: 4604 mov r4, r0
8005916: 4608 mov r0, r1
8005918: 4611 mov r1, r2
800591a: 2200 movs r2, #0
800591c: 602a str r2, [r5, #0]
800591e: 461a mov r2, r3
8005920: f7fb fada bl 8000ed8 <_read>
8005924: 1c43 adds r3, r0, #1
8005926: d102 bne.n 800592e <_read_r+0x1e>
8005928: 682b ldr r3, [r5, #0]
800592a: b103 cbz r3, 800592e <_read_r+0x1e>
800592c: 6023 str r3, [r4, #0]
800592e: bd38 pop {r3, r4, r5, pc}
8005930: 200003e8 .word 0x200003e8
08005934 <_write_r>:
8005934: b538 push {r3, r4, r5, lr}
8005936: 4d07 ldr r5, [pc, #28] ; (8005954 <_write_r+0x20>)
8005938: 4604 mov r4, r0
800593a: 4608 mov r0, r1
800593c: 4611 mov r1, r2
800593e: 2200 movs r2, #0
8005940: 602a str r2, [r5, #0]
8005942: 461a mov r2, r3
8005944: f7fb fae5 bl 8000f12 <_write>
8005948: 1c43 adds r3, r0, #1
800594a: d102 bne.n 8005952 <_write_r+0x1e>
800594c: 682b ldr r3, [r5, #0]
800594e: b103 cbz r3, 8005952 <_write_r+0x1e>
8005950: 6023 str r3, [r4, #0]
8005952: bd38 pop {r3, r4, r5, pc}
8005954: 200003e8 .word 0x200003e8
08005958 <__errno>:
8005958: 4b01 ldr r3, [pc, #4] ; (8005960 <__errno+0x8>)
800595a: 6818 ldr r0, [r3, #0]
800595c: 4770 bx lr
800595e: bf00 nop
8005960: 20000068 .word 0x20000068
08005964 <__libc_init_array>:
8005964: b570 push {r4, r5, r6, lr}
8005966: 4d0d ldr r5, [pc, #52] ; (800599c <__libc_init_array+0x38>)
8005968: 4c0d ldr r4, [pc, #52] ; (80059a0 <__libc_init_array+0x3c>)
800596a: 1b64 subs r4, r4, r5
800596c: 10a4 asrs r4, r4, #2
800596e: 2600 movs r6, #0
8005970: 42a6 cmp r6, r4
8005972: d109 bne.n 8005988 <__libc_init_array+0x24>
8005974: 4d0b ldr r5, [pc, #44] ; (80059a4 <__libc_init_array+0x40>)
8005976: 4c0c ldr r4, [pc, #48] ; (80059a8 <__libc_init_array+0x44>)
8005978: f000 fa56 bl 8005e28 <_init>
800597c: 1b64 subs r4, r4, r5
800597e: 10a4 asrs r4, r4, #2
8005980: 2600 movs r6, #0
8005982: 42a6 cmp r6, r4
8005984: d105 bne.n 8005992 <__libc_init_array+0x2e>
8005986: bd70 pop {r4, r5, r6, pc}
8005988: f855 3b04 ldr.w r3, [r5], #4
800598c: 4798 blx r3
800598e: 3601 adds r6, #1
8005990: e7ee b.n 8005970 <__libc_init_array+0xc>
8005992: f855 3b04 ldr.w r3, [r5], #4
8005996: 4798 blx r3
8005998: 3601 adds r6, #1
800599a: e7f2 b.n 8005982 <__libc_init_array+0x1e>
800599c: 08005f68 .word 0x08005f68
80059a0: 08005f68 .word 0x08005f68
80059a4: 08005f68 .word 0x08005f68
80059a8: 08005f6c .word 0x08005f6c
080059ac <__retarget_lock_init_recursive>:
80059ac: 4770 bx lr
080059ae <__retarget_lock_acquire_recursive>:
80059ae: 4770 bx lr
080059b0 <__retarget_lock_release_recursive>:
80059b0: 4770 bx lr
...
080059b4 <_free_r>:
80059b4: b537 push {r0, r1, r2, r4, r5, lr}
80059b6: 2900 cmp r1, #0
80059b8: d044 beq.n 8005a44 <_free_r+0x90>
80059ba: f851 3c04 ldr.w r3, [r1, #-4]
80059be: 9001 str r0, [sp, #4]
80059c0: 2b00 cmp r3, #0
80059c2: f1a1 0404 sub.w r4, r1, #4
80059c6: bfb8 it lt
80059c8: 18e4 addlt r4, r4, r3
80059ca: f000 f8df bl 8005b8c <__malloc_lock>
80059ce: 4a1e ldr r2, [pc, #120] ; (8005a48 <_free_r+0x94>)
80059d0: 9801 ldr r0, [sp, #4]
80059d2: 6813 ldr r3, [r2, #0]
80059d4: b933 cbnz r3, 80059e4 <_free_r+0x30>
80059d6: 6063 str r3, [r4, #4]
80059d8: 6014 str r4, [r2, #0]
80059da: b003 add sp, #12
80059dc: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
80059e0: f000 b8da b.w 8005b98 <__malloc_unlock>
80059e4: 42a3 cmp r3, r4
80059e6: d908 bls.n 80059fa <_free_r+0x46>
80059e8: 6825 ldr r5, [r4, #0]
80059ea: 1961 adds r1, r4, r5
80059ec: 428b cmp r3, r1
80059ee: bf01 itttt eq
80059f0: 6819 ldreq r1, [r3, #0]
80059f2: 685b ldreq r3, [r3, #4]
80059f4: 1949 addeq r1, r1, r5
80059f6: 6021 streq r1, [r4, #0]
80059f8: e7ed b.n 80059d6 <_free_r+0x22>
80059fa: 461a mov r2, r3
80059fc: 685b ldr r3, [r3, #4]
80059fe: b10b cbz r3, 8005a04 <_free_r+0x50>
8005a00: 42a3 cmp r3, r4
8005a02: d9fa bls.n 80059fa <_free_r+0x46>
8005a04: 6811 ldr r1, [r2, #0]
8005a06: 1855 adds r5, r2, r1
8005a08: 42a5 cmp r5, r4
8005a0a: d10b bne.n 8005a24 <_free_r+0x70>
8005a0c: 6824 ldr r4, [r4, #0]
8005a0e: 4421 add r1, r4
8005a10: 1854 adds r4, r2, r1
8005a12: 42a3 cmp r3, r4
8005a14: 6011 str r1, [r2, #0]
8005a16: d1e0 bne.n 80059da <_free_r+0x26>
8005a18: 681c ldr r4, [r3, #0]
8005a1a: 685b ldr r3, [r3, #4]
8005a1c: 6053 str r3, [r2, #4]
8005a1e: 440c add r4, r1
8005a20: 6014 str r4, [r2, #0]
8005a22: e7da b.n 80059da <_free_r+0x26>
8005a24: d902 bls.n 8005a2c <_free_r+0x78>
8005a26: 230c movs r3, #12
8005a28: 6003 str r3, [r0, #0]
8005a2a: e7d6 b.n 80059da <_free_r+0x26>
8005a2c: 6825 ldr r5, [r4, #0]
8005a2e: 1961 adds r1, r4, r5
8005a30: 428b cmp r3, r1
8005a32: bf04 itt eq
8005a34: 6819 ldreq r1, [r3, #0]
8005a36: 685b ldreq r3, [r3, #4]
8005a38: 6063 str r3, [r4, #4]
8005a3a: bf04 itt eq
8005a3c: 1949 addeq r1, r1, r5
8005a3e: 6021 streq r1, [r4, #0]
8005a40: 6054 str r4, [r2, #4]
8005a42: e7ca b.n 80059da <_free_r+0x26>
8005a44: b003 add sp, #12
8005a46: bd30 pop {r4, r5, pc}
8005a48: 200003f0 .word 0x200003f0
08005a4c <sbrk_aligned>:
8005a4c: b570 push {r4, r5, r6, lr}
8005a4e: 4e0e ldr r6, [pc, #56] ; (8005a88 <sbrk_aligned+0x3c>)
8005a50: 460c mov r4, r1
8005a52: 6831 ldr r1, [r6, #0]
8005a54: 4605 mov r5, r0
8005a56: b911 cbnz r1, 8005a5e <sbrk_aligned+0x12>
8005a58: f000 f9d6 bl 8005e08 <_sbrk_r>
8005a5c: 6030 str r0, [r6, #0]
8005a5e: 4621 mov r1, r4
8005a60: 4628 mov r0, r5
8005a62: f000 f9d1 bl 8005e08 <_sbrk_r>
8005a66: 1c43 adds r3, r0, #1
8005a68: d00a beq.n 8005a80 <sbrk_aligned+0x34>
8005a6a: 1cc4 adds r4, r0, #3
8005a6c: f024 0403 bic.w r4, r4, #3
8005a70: 42a0 cmp r0, r4
8005a72: d007 beq.n 8005a84 <sbrk_aligned+0x38>
8005a74: 1a21 subs r1, r4, r0
8005a76: 4628 mov r0, r5
8005a78: f000 f9c6 bl 8005e08 <_sbrk_r>
8005a7c: 3001 adds r0, #1
8005a7e: d101 bne.n 8005a84 <sbrk_aligned+0x38>
8005a80: f04f 34ff mov.w r4, #4294967295
8005a84: 4620 mov r0, r4
8005a86: bd70 pop {r4, r5, r6, pc}
8005a88: 200003f4 .word 0x200003f4
08005a8c <_malloc_r>:
8005a8c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8005a90: 1ccd adds r5, r1, #3
8005a92: f025 0503 bic.w r5, r5, #3
8005a96: 3508 adds r5, #8
8005a98: 2d0c cmp r5, #12
8005a9a: bf38 it cc
8005a9c: 250c movcc r5, #12
8005a9e: 2d00 cmp r5, #0
8005aa0: 4607 mov r7, r0
8005aa2: db01 blt.n 8005aa8 <_malloc_r+0x1c>
8005aa4: 42a9 cmp r1, r5
8005aa6: d905 bls.n 8005ab4 <_malloc_r+0x28>
8005aa8: 230c movs r3, #12
8005aaa: 603b str r3, [r7, #0]
8005aac: 2600 movs r6, #0
8005aae: 4630 mov r0, r6
8005ab0: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8005ab4: f8df 80d0 ldr.w r8, [pc, #208] ; 8005b88 <_malloc_r+0xfc>
8005ab8: f000 f868 bl 8005b8c <__malloc_lock>
8005abc: f8d8 3000 ldr.w r3, [r8]
8005ac0: 461c mov r4, r3
8005ac2: bb5c cbnz r4, 8005b1c <_malloc_r+0x90>
8005ac4: 4629 mov r1, r5
8005ac6: 4638 mov r0, r7
8005ac8: f7ff ffc0 bl 8005a4c <sbrk_aligned>
8005acc: 1c43 adds r3, r0, #1
8005ace: 4604 mov r4, r0
8005ad0: d155 bne.n 8005b7e <_malloc_r+0xf2>
8005ad2: f8d8 4000 ldr.w r4, [r8]
8005ad6: 4626 mov r6, r4
8005ad8: 2e00 cmp r6, #0
8005ada: d145 bne.n 8005b68 <_malloc_r+0xdc>
8005adc: 2c00 cmp r4, #0
8005ade: d048 beq.n 8005b72 <_malloc_r+0xe6>
8005ae0: 6823 ldr r3, [r4, #0]
8005ae2: 4631 mov r1, r6
8005ae4: 4638 mov r0, r7
8005ae6: eb04 0903 add.w r9, r4, r3
8005aea: f000 f98d bl 8005e08 <_sbrk_r>
8005aee: 4581 cmp r9, r0
8005af0: d13f bne.n 8005b72 <_malloc_r+0xe6>
8005af2: 6821 ldr r1, [r4, #0]
8005af4: 1a6d subs r5, r5, r1
8005af6: 4629 mov r1, r5
8005af8: 4638 mov r0, r7
8005afa: f7ff ffa7 bl 8005a4c <sbrk_aligned>
8005afe: 3001 adds r0, #1
8005b00: d037 beq.n 8005b72 <_malloc_r+0xe6>
8005b02: 6823 ldr r3, [r4, #0]
8005b04: 442b add r3, r5
8005b06: 6023 str r3, [r4, #0]
8005b08: f8d8 3000 ldr.w r3, [r8]
8005b0c: 2b00 cmp r3, #0
8005b0e: d038 beq.n 8005b82 <_malloc_r+0xf6>
8005b10: 685a ldr r2, [r3, #4]
8005b12: 42a2 cmp r2, r4
8005b14: d12b bne.n 8005b6e <_malloc_r+0xe2>
8005b16: 2200 movs r2, #0
8005b18: 605a str r2, [r3, #4]
8005b1a: e00f b.n 8005b3c <_malloc_r+0xb0>
8005b1c: 6822 ldr r2, [r4, #0]
8005b1e: 1b52 subs r2, r2, r5
8005b20: d41f bmi.n 8005b62 <_malloc_r+0xd6>
8005b22: 2a0b cmp r2, #11
8005b24: d917 bls.n 8005b56 <_malloc_r+0xca>
8005b26: 1961 adds r1, r4, r5
8005b28: 42a3 cmp r3, r4
8005b2a: 6025 str r5, [r4, #0]
8005b2c: bf18 it ne
8005b2e: 6059 strne r1, [r3, #4]
8005b30: 6863 ldr r3, [r4, #4]
8005b32: bf08 it eq
8005b34: f8c8 1000 streq.w r1, [r8]
8005b38: 5162 str r2, [r4, r5]
8005b3a: 604b str r3, [r1, #4]
8005b3c: 4638 mov r0, r7
8005b3e: f104 060b add.w r6, r4, #11
8005b42: f000 f829 bl 8005b98 <__malloc_unlock>
8005b46: f026 0607 bic.w r6, r6, #7
8005b4a: 1d23 adds r3, r4, #4
8005b4c: 1af2 subs r2, r6, r3
8005b4e: d0ae beq.n 8005aae <_malloc_r+0x22>
8005b50: 1b9b subs r3, r3, r6
8005b52: 50a3 str r3, [r4, r2]
8005b54: e7ab b.n 8005aae <_malloc_r+0x22>
8005b56: 42a3 cmp r3, r4
8005b58: 6862 ldr r2, [r4, #4]
8005b5a: d1dd bne.n 8005b18 <_malloc_r+0x8c>
8005b5c: f8c8 2000 str.w r2, [r8]
8005b60: e7ec b.n 8005b3c <_malloc_r+0xb0>
8005b62: 4623 mov r3, r4
8005b64: 6864 ldr r4, [r4, #4]
8005b66: e7ac b.n 8005ac2 <_malloc_r+0x36>
8005b68: 4634 mov r4, r6
8005b6a: 6876 ldr r6, [r6, #4]
8005b6c: e7b4 b.n 8005ad8 <_malloc_r+0x4c>
8005b6e: 4613 mov r3, r2
8005b70: e7cc b.n 8005b0c <_malloc_r+0x80>
8005b72: 230c movs r3, #12
8005b74: 603b str r3, [r7, #0]
8005b76: 4638 mov r0, r7
8005b78: f000 f80e bl 8005b98 <__malloc_unlock>
8005b7c: e797 b.n 8005aae <_malloc_r+0x22>
8005b7e: 6025 str r5, [r4, #0]
8005b80: e7dc b.n 8005b3c <_malloc_r+0xb0>
8005b82: 605b str r3, [r3, #4]
8005b84: deff udf #255 ; 0xff
8005b86: bf00 nop
8005b88: 200003f0 .word 0x200003f0
08005b8c <__malloc_lock>:
8005b8c: 4801 ldr r0, [pc, #4] ; (8005b94 <__malloc_lock+0x8>)
8005b8e: f7ff bf0e b.w 80059ae <__retarget_lock_acquire_recursive>
8005b92: bf00 nop
8005b94: 200003ec .word 0x200003ec
08005b98 <__malloc_unlock>:
8005b98: 4801 ldr r0, [pc, #4] ; (8005ba0 <__malloc_unlock+0x8>)
8005b9a: f7ff bf09 b.w 80059b0 <__retarget_lock_release_recursive>
8005b9e: bf00 nop
8005ba0: 200003ec .word 0x200003ec
08005ba4 <__sflush_r>:
8005ba4: 898a ldrh r2, [r1, #12]
8005ba6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8005baa: 4605 mov r5, r0
8005bac: 0710 lsls r0, r2, #28
8005bae: 460c mov r4, r1
8005bb0: d458 bmi.n 8005c64 <__sflush_r+0xc0>
8005bb2: 684b ldr r3, [r1, #4]
8005bb4: 2b00 cmp r3, #0
8005bb6: dc05 bgt.n 8005bc4 <__sflush_r+0x20>
8005bb8: 6c0b ldr r3, [r1, #64] ; 0x40
8005bba: 2b00 cmp r3, #0
8005bbc: dc02 bgt.n 8005bc4 <__sflush_r+0x20>
8005bbe: 2000 movs r0, #0
8005bc0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8005bc4: 6ae6 ldr r6, [r4, #44] ; 0x2c
8005bc6: 2e00 cmp r6, #0
8005bc8: d0f9 beq.n 8005bbe <__sflush_r+0x1a>
8005bca: 2300 movs r3, #0
8005bcc: f412 5280 ands.w r2, r2, #4096 ; 0x1000
8005bd0: 682f ldr r7, [r5, #0]
8005bd2: 6a21 ldr r1, [r4, #32]
8005bd4: 602b str r3, [r5, #0]
8005bd6: d032 beq.n 8005c3e <__sflush_r+0x9a>
8005bd8: 6d60 ldr r0, [r4, #84] ; 0x54
8005bda: 89a3 ldrh r3, [r4, #12]
8005bdc: 075a lsls r2, r3, #29
8005bde: d505 bpl.n 8005bec <__sflush_r+0x48>
8005be0: 6863 ldr r3, [r4, #4]
8005be2: 1ac0 subs r0, r0, r3
8005be4: 6b63 ldr r3, [r4, #52] ; 0x34
8005be6: b10b cbz r3, 8005bec <__sflush_r+0x48>
8005be8: 6c23 ldr r3, [r4, #64] ; 0x40
8005bea: 1ac0 subs r0, r0, r3
8005bec: 2300 movs r3, #0
8005bee: 4602 mov r2, r0
8005bf0: 6ae6 ldr r6, [r4, #44] ; 0x2c
8005bf2: 6a21 ldr r1, [r4, #32]
8005bf4: 4628 mov r0, r5
8005bf6: 47b0 blx r6
8005bf8: 1c43 adds r3, r0, #1
8005bfa: 89a3 ldrh r3, [r4, #12]
8005bfc: d106 bne.n 8005c0c <__sflush_r+0x68>
8005bfe: 6829 ldr r1, [r5, #0]
8005c00: 291d cmp r1, #29
8005c02: d82b bhi.n 8005c5c <__sflush_r+0xb8>
8005c04: 4a29 ldr r2, [pc, #164] ; (8005cac <__sflush_r+0x108>)
8005c06: 410a asrs r2, r1
8005c08: 07d6 lsls r6, r2, #31
8005c0a: d427 bmi.n 8005c5c <__sflush_r+0xb8>
8005c0c: 2200 movs r2, #0
8005c0e: 6062 str r2, [r4, #4]
8005c10: 04d9 lsls r1, r3, #19
8005c12: 6922 ldr r2, [r4, #16]
8005c14: 6022 str r2, [r4, #0]
8005c16: d504 bpl.n 8005c22 <__sflush_r+0x7e>
8005c18: 1c42 adds r2, r0, #1
8005c1a: d101 bne.n 8005c20 <__sflush_r+0x7c>
8005c1c: 682b ldr r3, [r5, #0]
8005c1e: b903 cbnz r3, 8005c22 <__sflush_r+0x7e>
8005c20: 6560 str r0, [r4, #84] ; 0x54
8005c22: 6b61 ldr r1, [r4, #52] ; 0x34
8005c24: 602f str r7, [r5, #0]
8005c26: 2900 cmp r1, #0
8005c28: d0c9 beq.n 8005bbe <__sflush_r+0x1a>
8005c2a: f104 0344 add.w r3, r4, #68 ; 0x44
8005c2e: 4299 cmp r1, r3
8005c30: d002 beq.n 8005c38 <__sflush_r+0x94>
8005c32: 4628 mov r0, r5
8005c34: f7ff febe bl 80059b4 <_free_r>
8005c38: 2000 movs r0, #0
8005c3a: 6360 str r0, [r4, #52] ; 0x34
8005c3c: e7c0 b.n 8005bc0 <__sflush_r+0x1c>
8005c3e: 2301 movs r3, #1
8005c40: 4628 mov r0, r5
8005c42: 47b0 blx r6
8005c44: 1c41 adds r1, r0, #1
8005c46: d1c8 bne.n 8005bda <__sflush_r+0x36>
8005c48: 682b ldr r3, [r5, #0]
8005c4a: 2b00 cmp r3, #0
8005c4c: d0c5 beq.n 8005bda <__sflush_r+0x36>
8005c4e: 2b1d cmp r3, #29
8005c50: d001 beq.n 8005c56 <__sflush_r+0xb2>
8005c52: 2b16 cmp r3, #22
8005c54: d101 bne.n 8005c5a <__sflush_r+0xb6>
8005c56: 602f str r7, [r5, #0]
8005c58: e7b1 b.n 8005bbe <__sflush_r+0x1a>
8005c5a: 89a3 ldrh r3, [r4, #12]
8005c5c: f043 0340 orr.w r3, r3, #64 ; 0x40
8005c60: 81a3 strh r3, [r4, #12]
8005c62: e7ad b.n 8005bc0 <__sflush_r+0x1c>
8005c64: 690f ldr r7, [r1, #16]
8005c66: 2f00 cmp r7, #0
8005c68: d0a9 beq.n 8005bbe <__sflush_r+0x1a>
8005c6a: 0793 lsls r3, r2, #30
8005c6c: 680e ldr r6, [r1, #0]
8005c6e: bf08 it eq
8005c70: 694b ldreq r3, [r1, #20]
8005c72: 600f str r7, [r1, #0]
8005c74: bf18 it ne
8005c76: 2300 movne r3, #0
8005c78: eba6 0807 sub.w r8, r6, r7
8005c7c: 608b str r3, [r1, #8]
8005c7e: f1b8 0f00 cmp.w r8, #0
8005c82: dd9c ble.n 8005bbe <__sflush_r+0x1a>
8005c84: 6a21 ldr r1, [r4, #32]
8005c86: 6aa6 ldr r6, [r4, #40] ; 0x28
8005c88: 4643 mov r3, r8
8005c8a: 463a mov r2, r7
8005c8c: 4628 mov r0, r5
8005c8e: 47b0 blx r6
8005c90: 2800 cmp r0, #0
8005c92: dc06 bgt.n 8005ca2 <__sflush_r+0xfe>
8005c94: 89a3 ldrh r3, [r4, #12]
8005c96: f043 0340 orr.w r3, r3, #64 ; 0x40
8005c9a: 81a3 strh r3, [r4, #12]
8005c9c: f04f 30ff mov.w r0, #4294967295
8005ca0: e78e b.n 8005bc0 <__sflush_r+0x1c>
8005ca2: 4407 add r7, r0
8005ca4: eba8 0800 sub.w r8, r8, r0
8005ca8: e7e9 b.n 8005c7e <__sflush_r+0xda>
8005caa: bf00 nop
8005cac: dfbffffe .word 0xdfbffffe
08005cb0 <_fflush_r>:
8005cb0: b538 push {r3, r4, r5, lr}
8005cb2: 690b ldr r3, [r1, #16]
8005cb4: 4605 mov r5, r0
8005cb6: 460c mov r4, r1
8005cb8: b913 cbnz r3, 8005cc0 <_fflush_r+0x10>
8005cba: 2500 movs r5, #0
8005cbc: 4628 mov r0, r5
8005cbe: bd38 pop {r3, r4, r5, pc}
8005cc0: b118 cbz r0, 8005cca <_fflush_r+0x1a>
8005cc2: 6a03 ldr r3, [r0, #32]
8005cc4: b90b cbnz r3, 8005cca <_fflush_r+0x1a>
8005cc6: f7ff fc8f bl 80055e8 <__sinit>
8005cca: f9b4 300c ldrsh.w r3, [r4, #12]
8005cce: 2b00 cmp r3, #0
8005cd0: d0f3 beq.n 8005cba <_fflush_r+0xa>
8005cd2: 6e62 ldr r2, [r4, #100] ; 0x64
8005cd4: 07d0 lsls r0, r2, #31
8005cd6: d404 bmi.n 8005ce2 <_fflush_r+0x32>
8005cd8: 0599 lsls r1, r3, #22
8005cda: d402 bmi.n 8005ce2 <_fflush_r+0x32>
8005cdc: 6da0 ldr r0, [r4, #88] ; 0x58
8005cde: f7ff fe66 bl 80059ae <__retarget_lock_acquire_recursive>
8005ce2: 4628 mov r0, r5
8005ce4: 4621 mov r1, r4
8005ce6: f7ff ff5d bl 8005ba4 <__sflush_r>
8005cea: 6e63 ldr r3, [r4, #100] ; 0x64
8005cec: 07da lsls r2, r3, #31
8005cee: 4605 mov r5, r0
8005cf0: d4e4 bmi.n 8005cbc <_fflush_r+0xc>
8005cf2: 89a3 ldrh r3, [r4, #12]
8005cf4: 059b lsls r3, r3, #22
8005cf6: d4e1 bmi.n 8005cbc <_fflush_r+0xc>
8005cf8: 6da0 ldr r0, [r4, #88] ; 0x58
8005cfa: f7ff fe59 bl 80059b0 <__retarget_lock_release_recursive>
8005cfe: e7dd b.n 8005cbc <_fflush_r+0xc>
08005d00 <__swhatbuf_r>:
8005d00: b570 push {r4, r5, r6, lr}
8005d02: 460c mov r4, r1
8005d04: f9b1 100e ldrsh.w r1, [r1, #14]
8005d08: 2900 cmp r1, #0
8005d0a: b096 sub sp, #88 ; 0x58
8005d0c: 4615 mov r5, r2
8005d0e: 461e mov r6, r3
8005d10: da0d bge.n 8005d2e <__swhatbuf_r+0x2e>
8005d12: 89a3 ldrh r3, [r4, #12]
8005d14: f013 0f80 tst.w r3, #128 ; 0x80
8005d18: f04f 0100 mov.w r1, #0
8005d1c: bf0c ite eq
8005d1e: f44f 6380 moveq.w r3, #1024 ; 0x400
8005d22: 2340 movne r3, #64 ; 0x40
8005d24: 2000 movs r0, #0
8005d26: 6031 str r1, [r6, #0]
8005d28: 602b str r3, [r5, #0]
8005d2a: b016 add sp, #88 ; 0x58
8005d2c: bd70 pop {r4, r5, r6, pc}
8005d2e: 466a mov r2, sp
8005d30: f000 f848 bl 8005dc4 <_fstat_r>
8005d34: 2800 cmp r0, #0
8005d36: dbec blt.n 8005d12 <__swhatbuf_r+0x12>
8005d38: 9901 ldr r1, [sp, #4]
8005d3a: f401 4170 and.w r1, r1, #61440 ; 0xf000
8005d3e: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000
8005d42: 4259 negs r1, r3
8005d44: 4159 adcs r1, r3
8005d46: f44f 6380 mov.w r3, #1024 ; 0x400
8005d4a: e7eb b.n 8005d24 <__swhatbuf_r+0x24>
08005d4c <__smakebuf_r>:
8005d4c: 898b ldrh r3, [r1, #12]
8005d4e: b573 push {r0, r1, r4, r5, r6, lr}
8005d50: 079d lsls r5, r3, #30
8005d52: 4606 mov r6, r0
8005d54: 460c mov r4, r1
8005d56: d507 bpl.n 8005d68 <__smakebuf_r+0x1c>
8005d58: f104 0347 add.w r3, r4, #71 ; 0x47
8005d5c: 6023 str r3, [r4, #0]
8005d5e: 6123 str r3, [r4, #16]
8005d60: 2301 movs r3, #1
8005d62: 6163 str r3, [r4, #20]
8005d64: b002 add sp, #8
8005d66: bd70 pop {r4, r5, r6, pc}
8005d68: ab01 add r3, sp, #4
8005d6a: 466a mov r2, sp
8005d6c: f7ff ffc8 bl 8005d00 <__swhatbuf_r>
8005d70: 9900 ldr r1, [sp, #0]
8005d72: 4605 mov r5, r0
8005d74: 4630 mov r0, r6
8005d76: f7ff fe89 bl 8005a8c <_malloc_r>
8005d7a: b948 cbnz r0, 8005d90 <__smakebuf_r+0x44>
8005d7c: f9b4 300c ldrsh.w r3, [r4, #12]
8005d80: 059a lsls r2, r3, #22
8005d82: d4ef bmi.n 8005d64 <__smakebuf_r+0x18>
8005d84: f023 0303 bic.w r3, r3, #3
8005d88: f043 0302 orr.w r3, r3, #2
8005d8c: 81a3 strh r3, [r4, #12]
8005d8e: e7e3 b.n 8005d58 <__smakebuf_r+0xc>
8005d90: 89a3 ldrh r3, [r4, #12]
8005d92: 6020 str r0, [r4, #0]
8005d94: f043 0380 orr.w r3, r3, #128 ; 0x80
8005d98: 81a3 strh r3, [r4, #12]
8005d9a: 9b00 ldr r3, [sp, #0]
8005d9c: 6163 str r3, [r4, #20]
8005d9e: 9b01 ldr r3, [sp, #4]
8005da0: 6120 str r0, [r4, #16]
8005da2: b15b cbz r3, 8005dbc <__smakebuf_r+0x70>
8005da4: f9b4 100e ldrsh.w r1, [r4, #14]
8005da8: 4630 mov r0, r6
8005daa: f000 f81d bl 8005de8 <_isatty_r>
8005dae: b128 cbz r0, 8005dbc <__smakebuf_r+0x70>
8005db0: 89a3 ldrh r3, [r4, #12]
8005db2: f023 0303 bic.w r3, r3, #3
8005db6: f043 0301 orr.w r3, r3, #1
8005dba: 81a3 strh r3, [r4, #12]
8005dbc: 89a3 ldrh r3, [r4, #12]
8005dbe: 431d orrs r5, r3
8005dc0: 81a5 strh r5, [r4, #12]
8005dc2: e7cf b.n 8005d64 <__smakebuf_r+0x18>
08005dc4 <_fstat_r>:
8005dc4: b538 push {r3, r4, r5, lr}
8005dc6: 4d07 ldr r5, [pc, #28] ; (8005de4 <_fstat_r+0x20>)
8005dc8: 2300 movs r3, #0
8005dca: 4604 mov r4, r0
8005dcc: 4608 mov r0, r1
8005dce: 4611 mov r1, r2
8005dd0: 602b str r3, [r5, #0]
8005dd2: f7fb f8c6 bl 8000f62 <_fstat>
8005dd6: 1c43 adds r3, r0, #1
8005dd8: d102 bne.n 8005de0 <_fstat_r+0x1c>
8005dda: 682b ldr r3, [r5, #0]
8005ddc: b103 cbz r3, 8005de0 <_fstat_r+0x1c>
8005dde: 6023 str r3, [r4, #0]
8005de0: bd38 pop {r3, r4, r5, pc}
8005de2: bf00 nop
8005de4: 200003e8 .word 0x200003e8
08005de8 <_isatty_r>:
8005de8: b538 push {r3, r4, r5, lr}
8005dea: 4d06 ldr r5, [pc, #24] ; (8005e04 <_isatty_r+0x1c>)
8005dec: 2300 movs r3, #0
8005dee: 4604 mov r4, r0
8005df0: 4608 mov r0, r1
8005df2: 602b str r3, [r5, #0]
8005df4: f7fb f8c5 bl 8000f82 <_isatty>
8005df8: 1c43 adds r3, r0, #1
8005dfa: d102 bne.n 8005e02 <_isatty_r+0x1a>
8005dfc: 682b ldr r3, [r5, #0]
8005dfe: b103 cbz r3, 8005e02 <_isatty_r+0x1a>
8005e00: 6023 str r3, [r4, #0]
8005e02: bd38 pop {r3, r4, r5, pc}
8005e04: 200003e8 .word 0x200003e8
08005e08 <_sbrk_r>:
8005e08: b538 push {r3, r4, r5, lr}
8005e0a: 4d06 ldr r5, [pc, #24] ; (8005e24 <_sbrk_r+0x1c>)
8005e0c: 2300 movs r3, #0
8005e0e: 4604 mov r4, r0
8005e10: 4608 mov r0, r1
8005e12: 602b str r3, [r5, #0]
8005e14: f7fb f8ce bl 8000fb4 <_sbrk>
8005e18: 1c43 adds r3, r0, #1
8005e1a: d102 bne.n 8005e22 <_sbrk_r+0x1a>
8005e1c: 682b ldr r3, [r5, #0]
8005e1e: b103 cbz r3, 8005e22 <_sbrk_r+0x1a>
8005e20: 6023 str r3, [r4, #0]
8005e22: bd38 pop {r3, r4, r5, pc}
8005e24: 200003e8 .word 0x200003e8
08005e28 <_init>:
8005e28: b5f8 push {r3, r4, r5, r6, r7, lr}
8005e2a: bf00 nop
8005e2c: bcf8 pop {r3, r4, r5, r6, r7}
8005e2e: bc08 pop {r3}
8005e30: 469e mov lr, r3
8005e32: 4770 bx lr
08005e34 <_fini>:
8005e34: b5f8 push {r3, r4, r5, r6, r7, lr}
8005e36: bf00 nop
8005e38: bcf8 pop {r3, r4, r5, r6, r7}
8005e3a: bc08 pop {r3}
8005e3c: 469e mov lr, r3
8005e3e: 4770 bx lr
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