From b6aa9858d3785b85bba8f826d11029a9be7a1e31 Mon Sep 17 00:00:00 2001
From: Yuhao Zhou <miskcoo@gmail.com>
Date: Mon, 8 Apr 2019 04:47:36 +0800
Subject: [PATCH] Fix return register in sys_clone.

---
 kernel/Cargo.lock                   | 2 +-
 kernel/src/arch/mipsel/context.rs   | 5 +++--
 kernel/src/arch/mipsel/interrupt.rs | 7 ++++++-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/kernel/Cargo.lock b/kernel/Cargo.lock
index 18c5a5e..c89c9d5 100644
--- a/kernel/Cargo.lock
+++ b/kernel/Cargo.lock
@@ -230,7 +230,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 [[package]]
 name = "mips"
 version = "0.1.0"
-source = "git+https://github.com/Harry-Chen/rust-mips#1f3df9589869670621baa863b87a3444d80f08a6"
+source = "git+https://github.com/Harry-Chen/rust-mips#7410a6aa107fce681378e7850c03f9b6befec2d2"
 dependencies = [
  "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)",
diff --git a/kernel/src/arch/mipsel/context.rs b/kernel/src/arch/mipsel/context.rs
index 3236703..4dfdad9 100644
--- a/kernel/src/arch/mipsel/context.rs
+++ b/kernel/src/arch/mipsel/context.rs
@@ -1,4 +1,5 @@
 use mips::registers::cp0;
+use mips::tlb;
 
 /// Saved registers on a trap.
 #[derive(Clone)]
@@ -226,8 +227,8 @@ impl Context {
             tf: {
                 let mut tf = tf.clone();
                 tf.sp = ustack_top;   // sp
-                tf.v1 = tls; // tp
-                tf.v0 = 0;  // a0
+                tf.v1 = tls;
+                tf.a0 = 0;  // return value
                 tf
             },
         }.push_at(kstack_top)
diff --git a/kernel/src/arch/mipsel/interrupt.rs b/kernel/src/arch/mipsel/interrupt.rs
index 21f39f2..5a64411 100644
--- a/kernel/src/arch/mipsel/interrupt.rs
+++ b/kernel/src/arch/mipsel/interrupt.rs
@@ -155,7 +155,12 @@ fn page_fault(tf: &mut TrapFrame) {
     };
     let tlb_result = root_table.lookup(addr);
     match tlb_result {
-        Ok(tlb_entry) => tlb::write_tlb_random(tlb_entry),
+        Ok(tlb_entry) => {
+            trace!("PhysAddr = {:x}/{:x}",
+                   tlb_entry.entry_lo0.get_pfn() << 12,
+                   tlb_entry.entry_lo1.get_pfn() << 12);
+            tlb::write_tlb_random(tlb_entry)
+        },
         Err(()) => {
             if !crate::memory::handle_page_fault(addr) {
                 crate::trap::error(tf);