From b7e124930d568339c2dc44078c995b19a2e12b93 Mon Sep 17 00:00:00 2001
From: dzy <daizy15@mails.tsinghua.edu.cn>
Date: Mon, 24 Dec 2018 21:36:33 +0800
Subject: [PATCH] fix compilation errors

---
 crate/riscv                              |  2 +-
 kernel/src/arch/riscv32/boot/linker64.ld | 49 ++++++++++++++++++++++++
 kernel/src/arch/riscv32/paging.rs        | 24 ++++++------
 3 files changed, 62 insertions(+), 13 deletions(-)
 create mode 100644 kernel/src/arch/riscv32/boot/linker64.ld

diff --git a/crate/riscv b/crate/riscv
index 784fd79..e31e34a 160000
--- a/crate/riscv
+++ b/crate/riscv
@@ -1 +1 @@
-Subproject commit 784fd794840c14f6ffe77d97d339823d8749cf75
+Subproject commit e31e34a7d97a52946ed8762ddb435318c9c3b8ac
diff --git a/kernel/src/arch/riscv32/boot/linker64.ld b/kernel/src/arch/riscv32/boot/linker64.ld
new file mode 100644
index 0000000..454effa
--- /dev/null
+++ b/kernel/src/arch/riscv32/boot/linker64.ld
@@ -0,0 +1,49 @@
+/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore      */
+
+/* Simple linker script for the ucore kernel.
+   See the GNU ld 'info' manual ("info ld") to learn the syntax. */
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+BASE_ADDRESS = 0xffffffff80020000;
+
+SECTIONS
+{
+    /* Load the kernel at this address: "." means the current address */
+    . = BASE_ADDRESS;
+    start = .;
+
+    .text : {
+        stext = .;
+        *(.text.entry)
+        *(.text .text.*)
+        . = ALIGN(4K);
+        etext = .;
+    }
+
+    .rodata : {
+        srodata = .;
+        *(.rodata .rodata.*)
+        . = ALIGN(4K);
+        erodata = .;
+    }
+
+    .data : {
+        sdata = .;
+        *(.data .data.*)
+        edata = .;
+    }
+
+    .stack : {
+        *(.bss.stack)
+    }
+
+    .bss : {
+        sbss = .;
+        *(.bss .bss.*)
+        ebss = .;
+    }
+
+    PROVIDE(end = .);
+}
diff --git a/kernel/src/arch/riscv32/paging.rs b/kernel/src/arch/riscv32/paging.rs
index 2e88673..00b8de2 100644
--- a/kernel/src/arch/riscv32/paging.rs
+++ b/kernel/src/arch/riscv32/paging.rs
@@ -85,16 +85,16 @@ impl PageTable for ActivePageTable {
     #[cfg(target_arch = "riscv64")]
     fn get_entry(&mut self, vaddr: usize) -> Option<&mut PageEntry> {
         let vaddr = VirtAddr::new(vaddr);
-        let root_table: &RvPageTable = &*ROOT_PAGE_TABLE;
+        let root_table: &RvPageTable = unsafe { &*ROOT_PAGE_TABLE };
 
         let p3_table = if ! root_table[vaddr.p4_index()].flags().contains(EF::VALID) {
             return None
         } else {
             let p3_table = unsafe { &mut *(Page::from_page_table_indices(
-                self.recursive_index,
-                self.recursive_index,
-                self.recursive_index,
-                vaddr.p4_index()).start_address().as_usize() as *mut PageTable) };
+                self.0.recursive_index,
+                self.0.recursive_index,
+                self.0.recursive_index,
+                vaddr.p4_index()).start_address().as_usize() as *mut RvPageTable) };
             p3_table
         };
 
@@ -102,10 +102,10 @@ impl PageTable for ActivePageTable {
             return None
         } else {
             let p2_table = unsafe { &mut *(Page::from_page_table_indices(
-                self.recursive_index,
-                self.recursive_index,
+                self.0.recursive_index,
+                self.0.recursive_index,
                 vaddr.p4_index(),
-                vaddr.p3_index()).start_address().as_usize() as *mut PageTable) };
+                vaddr.p3_index()).start_address().as_usize() as *mut RvPageTable) };
             p2_table
         };
 
@@ -113,10 +113,10 @@ impl PageTable for ActivePageTable {
             return None
         } else {
             let p1_table = unsafe { &mut *(Page::from_page_table_indices(
-                self.recursive_index,
+                self.0.recursive_index,
                 vaddr.p4_index(),
                 vaddr.p3_index(),
-                vaddr.p2_index()).start_address().as_usize() as *mut PageTable) };
+                vaddr.p2_index()).start_address().as_usize() as *mut RvPageTable) };
             p1_table
         };
 
@@ -224,13 +224,13 @@ impl ActivePageTable {
 impl Entry for PageEntry {
     #[cfg(target_arch = "riscv64")]
     fn update(&mut self) {
-        let addr = VirtAddr::new((self as *const _ as usize) << 9);
+        let mut addr: usize = (self as *const _ as usize) << 9;
         if (addr & 0x7000_0000_0000 != 0) {
             addr |= 0xFFFF_0000_0000_0000;
         } else {
             addr &= 0x0000_FFFF_FFFF_FFFF;
         }
-        sfence_vma(0, addr);
+        sfence_vma(0, VirtAddr::new(addr));
     }
     #[cfg(target_arch = "riscv32")]
     fn update(&mut self) {