From ee80a3eeb71fe6835a8f4ff43abe076c5ab68a7d Mon Sep 17 00:00:00 2001 From: WangRunji Date: Sat, 14 Jul 2018 00:39:49 +0800 Subject: [PATCH] Fix compile user for RV32 --- user/Xargo.toml | 6 ++++++ user/riscv32-ucore.json | 2 +- user/ucore-ulib/src/lib.rs | 3 +++ 3 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 user/Xargo.toml diff --git a/user/Xargo.toml b/user/Xargo.toml new file mode 100644 index 0000000..f79cb96 --- /dev/null +++ b/user/Xargo.toml @@ -0,0 +1,6 @@ +[dependencies] +alloc = {} + +[dependencies.compiler_builtins] +features = ["mem"] +stage = 1 diff --git a/user/riscv32-ucore.json b/user/riscv32-ucore.json index ab76d65..ef98b18 100644 --- a/user/riscv32-ucore.json +++ b/user/riscv32-ucore.json @@ -9,7 +9,7 @@ "cpu": "generic-rv32", "features": "+m", "max-atomic-width": "32", - "linker": "ld.lld", + "linker": "riscv32-unknown-elf-ld", "linker-flavor": "ld", "executables": true, "panic-strategy": "abort", diff --git a/user/ucore-ulib/src/lib.rs b/user/ucore-ulib/src/lib.rs index a266b23..c1c1cb7 100644 --- a/user/ucore-ulib/src/lib.rs +++ b/user/ucore-ulib/src/lib.rs @@ -4,6 +4,9 @@ #![feature(panic_implementation)] #![feature(panic_info_message)] #![feature(linkage)] +#![feature(compiler_builtins_lib)] + +extern crate compiler_builtins; #[macro_use] pub mod syscall;