Harry Chen
6 years ago
commit
f8a62b5549
@ -0,0 +1,497 @@
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//! Driver for AHCI
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//!
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//! Spec: https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1-3-1.pdf
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use alloc::alloc::{alloc_zeroed, Layout};
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use alloc::boxed::Box;
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use alloc::string::String;
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use alloc::sync::Arc;
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use alloc::vec::Vec;
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use core::mem::size_of;
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use core::slice;
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use core::sync::atomic::spin_loop_hint;
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use bit_field::*;
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use bitflags::*;
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use log::*;
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use rcore_fs::dev::BlockDevice;
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use volatile::Volatile;
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use rcore_memory::paging::PageTable;
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use rcore_memory::{PhysAddr, VirtAddr, PAGE_SIZE};
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use crate::drivers::BlockDriver;
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use crate::memory::active_table;
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use crate::sync::SpinNoIrqLock as Mutex;
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use super::super::{DeviceType, Driver, BLK_DRIVERS, DRIVERS};
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pub struct AHCI {
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header: usize,
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size: usize,
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received_fis: &'static mut AHCIReceivedFIS,
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cmd_list: &'static mut [AHCICommandHeader],
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cmd_table: &'static mut AHCICommandTable,
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data: &'static mut [u8],
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port: &'static mut AHCIPort,
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}
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pub struct AHCIDriver(Mutex<AHCI>);
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/// AHCI Generic Host Control (3.1)
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#[repr(C)]
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pub struct AHCIGHC {
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/// Host capability
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capability: Volatile<AHCICap>,
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/// Global host control
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global_host_control: Volatile<u32>,
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/// Interrupt status
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interrupt_status: Volatile<u32>,
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/// Port implemented
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port_implemented: Volatile<u32>,
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/// Version
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version: Volatile<u32>,
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/// Command completion coalescing control
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ccc_control: Volatile<u32>,
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/// Command completion coalescing ports
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ccc_ports: Volatile<u32>,
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/// Enclosure management location
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em_location: Volatile<u32>,
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/// Enclosure management control
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em_control: Volatile<u32>,
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/// Host capabilities extended
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capabilities2: Volatile<u32>,
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/// BIOS/OS handoff control and status
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bios_os_handoff_control: Volatile<u32>,
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}
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bitflags! {
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struct AHCICap : u32 {
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const S64A = 1 << 31;
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const SNCQ = 1 << 30;
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const SSNTF = 1 << 29;
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const SMPS = 1 << 28;
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const SSS = 1 << 27;
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const SALP = 1 << 26;
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const SAL = 1 << 25;
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const SCLO = 1 << 24;
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const ISS_GEN_1 = 1 << 20;
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const ISS_GEN_2 = 2 << 20;
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const ISS_GEN_3 = 3 << 20;
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const SAM = 1 << 18;
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const SPM = 1 << 17;
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const FBSS = 1 << 16;
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const PMD = 1 << 15;
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const SSC = 1 << 14;
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const PSC = 1 << 13;
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const CCCS = 1 << 7;
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const EMS = 1 << 6;
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const SXS = 1 << 5;
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// number of ports - 1
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const NUM_MASK = 0b11111;
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}
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}
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impl AHCIGHC {
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fn enable(&mut self) {
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self.global_host_control.update(|v| {
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v.set_bit(13, true);
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});
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}
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fn num_ports(&self) -> usize {
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(self.capability.read() & AHCICap::NUM_MASK).bits() as usize + 1
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}
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fn has_port(&self, port_num: usize) -> bool {
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self.port_implemented.read().get_bit(port_num)
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}
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}
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/// AHCI Port Registers (3.3) (one set per port)
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#[repr(C)]
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pub struct AHCIPort {
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command_list_base_address: Volatile<u64>,
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fis_base_address: Volatile<u64>,
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interrupt_status: Volatile<u32>,
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interrupt_enable: Volatile<u32>,
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command: Volatile<u32>,
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reserved: Volatile<u32>,
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task_file_data: Volatile<u32>,
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signature: Volatile<u32>,
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sata_status: Volatile<u32>,
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sata_control: Volatile<u32>,
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sata_error: Volatile<u32>,
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sata_active: Volatile<u32>,
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command_issue: Volatile<u32>,
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sata_notification: Volatile<u32>,
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fis_based_switch_control: Volatile<u32>,
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}
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impl AHCIPort {
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fn spin_on_slot(&mut self, slot: usize) {
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loop {
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let ci = self.command_issue.read();
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if !ci.get_bit(slot) {
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break;
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}
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spin_loop_hint();
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}
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}
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fn issue_command(&mut self, slot: usize) {
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assert!(slot < 32);
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self.command_issue.write(1 << (slot as u32));
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}
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}
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/// AHCI Received FIS Structure (4.2.1)
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#[repr(C)]
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pub struct AHCIReceivedFIS {
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dma: [u8; 0x20],
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pio: [u8; 0x20],
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d2h: [u8; 0x18],
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sdbfis: [u8; 0x8],
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ufis: [u8; 0x40],
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reserved: [u8; 0x60],
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}
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/// # AHCI Command List Structure (4.2.2)
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///
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/// Host sends commands to the device through Command List.
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///
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/// Command List consists of 1 to 32 command headers, each one is called a slot.
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///
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/// Each command header describes an ATA or ATAPI command, including a
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/// Command FIS, an ATAPI command buffer and a bunch of Physical Region
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/// Descriptor Tables specifying the data payload address and size.
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///
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/// https://wiki.osdev.org/images/e/e8/Command_list.jpg
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#[repr(C)]
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pub struct AHCICommandHeader {
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///
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flags: CommandHeaderFlags,
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/// Physical region descriptor table length in entries
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prdt_length: u16,
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/// Physical region descriptor byte count transferred
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prd_byte_count: u32,
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/// Command table descriptor base address
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command_table_base_address: u64,
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/// Reserved
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reserved: [u32; 4],
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}
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bitflags! {
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pub struct CommandHeaderFlags: u16 {
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/// Command FIS length in DWORDS, 2 ~ 16
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const CFL_MASK = 0b11111;
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/// ATAPI
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const ATAPI = 1 << 5;
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/// Write, 1: H2D, 0: D2H
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const WRITE = 1 << 6;
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/// Prefetchable
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const PREFETCHABLE = 1 << 7;
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/// Reset
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const RESET = 1 << 8;
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/// BIST
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const BIST = 1 << 9;
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/// Clear busy upon R_OK
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const CLEAR = 1 << 10;
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/// Port multiplier port
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const PORT_MULTIPLIER_PORT_MASK = 0b1111 << 12;
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}
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}
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/// AHCI Command Table (4.2.3)
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#[repr(C)]
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pub struct AHCICommandTable {
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/// Command FIS
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cfis: SATAFISRegH2D,
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/// ATAPI command, 12 or 16 bytes
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acmd: [u8; 16],
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/// Reserved
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reserved: [u8; 48],
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/// Physical region descriptor table entries, 0 ~ 65535
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prdt: [AHCIPrdtEntry; 1],
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}
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/// Physical region descriptor table entry
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#[repr(C)]
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pub struct AHCIPrdtEntry {
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/// Data base address
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data_base_address: u64,
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/// Reserved
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reserved: u32,
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/// Bit 21-0: Byte count, 4M max
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/// Bit 31: Interrupt on completion
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dbc_i: u32,
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}
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const FIS_REG_H2D: u8 = 0x27;
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const CMD_READ_DMA_EXT: u8 = 0x25;
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const CMD_WRITE_DMA_EXT: u8 = 0x35;
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const CMD_IDENTIFY_DEVICE: u8 = 0xec;
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/// SATA Register FIS - Host to Device
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///
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/// https://wiki.osdev.org/AHCI Figure 5-2
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#[repr(C)]
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pub struct SATAFISRegH2D {
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fis_type: u8,
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cflags: u8,
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command: u8,
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feature_lo: u8,
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lba_0: u8, // LBA 7:0
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lba_1: u8, // LBA 15:8
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lba_2: u8, // LBA 23:16
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dev_head: u8,
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lba_3: u8, // LBA 31:24
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lba_4: u8, // LBA 39:32
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lba_5: u8, // LBA 47:40
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feature_hi: u8,
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sector_count: u16,
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reserved: u8,
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control: u8,
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_padding: [u8; 48],
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}
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impl SATAFISRegH2D {
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fn set_lba(&mut self, lba: u64) {
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self.lba_0 = (lba >> 0) as u8;
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self.lba_1 = (lba >> 8) as u8;
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self.lba_2 = (lba >> 16) as u8;
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self.lba_3 = (lba >> 24) as u8;
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self.lba_4 = (lba >> 32) as u8;
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self.lba_5 = (lba >> 40) as u8;
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}
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}
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/// IDENTIFY DEVICE data
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///
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/// ATA8-ACS Table 29
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#[repr(C)]
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pub struct ATAIdentifyPacket {
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_1: [u16; 10],
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serial: [u8; 20], // words 10-19
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_2: [u16; 3],
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firmware: [u8; 8], // words 23-26
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model: [u8; 40], // words 27-46
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_3: [u16; 13],
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lba_sectors: u32, // words 60-61
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_4: [u16; 38],
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lba48_sectors: u64, // words 100-103
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}
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impl AHCI {
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fn read_block(&mut self, block_id: usize, buf: &mut [u8]) -> usize {
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self.cmd_list[0].flags = CommandHeaderFlags::empty();
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let fis = &mut self.cmd_table.cfis;
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// Register FIS from HBA to device
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fis.fis_type = FIS_REG_H2D;
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fis.cflags = 1 << 7;
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// 7.25 READ DMA EXT - 25h, DMA
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fis.command = CMD_READ_DMA_EXT;
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fis.sector_count = 1;
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fis.dev_head = 0x40; // LBA
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fis.control = 0x80; // LBA48
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fis.set_lba(block_id as u64);
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self.port.issue_command(0);
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self.port.spin_on_slot(0);
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let len = buf.len().min(BLOCK_SIZE);
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buf[..len].clone_from_slice(&self.data[0..len]);
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len
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}
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fn write_block(&mut self, block_id: usize, buf: &[u8]) -> usize {
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self.cmd_list[0].flags = CommandHeaderFlags::WRITE; // device write
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let len = buf.len().min(BLOCK_SIZE);
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self.data[0..len].clone_from_slice(&buf[..len]);
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let fis = &mut self.cmd_table.cfis;
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// Register FIS from HBA to device
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fis.fis_type = FIS_REG_H2D;
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fis.cflags = 1 << 7;
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// ATA8-ACS
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// 7.63 WRITE DMA EXT - 35h, DMA
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fis.command = CMD_WRITE_DMA_EXT;
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fis.sector_count = 1;
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fis.dev_head = 0x40; // LBA
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fis.control = 0x80; // LBA48
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fis.set_lba(block_id as u64);
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self.port.issue_command(0);
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self.port.spin_on_slot(0);
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len
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}
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}
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impl Driver for AHCIDriver {
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fn try_handle_interrupt(&self, _irq: Option<u32>) -> bool {
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false
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}
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fn device_type(&self) -> DeviceType {
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DeviceType::Block
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}
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fn get_id(&self) -> String {
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format!("ahci")
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}
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fn read_block(&self, block_id: usize, buf: &mut [u8]) -> bool {
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let mut driver = self.0.lock();
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driver.read_block(block_id, buf);
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true
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}
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fn write_block(&self, block_id: usize, buf: &[u8]) -> bool {
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if buf.len() < BLOCK_SIZE {
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return false;
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}
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let mut driver = self.0.lock();
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driver.write_block(block_id, buf);
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true
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}
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}
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const BLOCK_SIZE: usize = 512;
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fn from_ata_string(data: &[u8]) -> String {
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let mut swapped_data = Vec::new();
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assert_eq!(data.len() % 2, 0);
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for i in (0..data.len()).step_by(2) {
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swapped_data.push(data[i + 1]);
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swapped_data.push(data[i]);
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}
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return String::from_utf8(swapped_data).unwrap();
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}
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/// Allocate consequent physical frames for DMA
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fn alloc_dma(page_num: usize) -> (VirtAddr, PhysAddr) {
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let layout = Layout::from_size_align(PAGE_SIZE * page_num, PAGE_SIZE).unwrap();
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let vaddr = unsafe { alloc_zeroed(layout) } as usize;
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let paddr = active_table().get_entry(vaddr).unwrap().target();
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(vaddr, paddr)
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}
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pub fn ahci_init(irq: Option<u32>, header: usize, size: usize) -> Arc<AHCIDriver> {
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let ghc = unsafe { &mut *(header as *mut AHCIGHC) };
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ghc.enable();
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for port_num in 0..ghc.num_ports() {
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if ghc.has_port(port_num) {
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let addr = header + 0x100 + 0x80 * port_num;
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let port = unsafe { &mut *(addr as *mut AHCIPort) };
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// SSTS IPM Active
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if port.sata_status.read().get_bits(8..12) != 1 {
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continue;
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}
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// SSTS DET Present
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if port.sata_status.read().get_bits(0..4) != 3 {
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continue;
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}
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debug!("probing port {}", port_num);
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// Disable Port First
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port.command.update(|c| {
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c.set_bit(4, false);
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c.set_bit(0, false);
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});
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let (rfis_va, rfis_pa) = alloc_dma(1);
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let (cmd_list_va, cmd_list_pa) = alloc_dma(1);
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let (cmd_table_va, cmd_table_pa) = alloc_dma(1);
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let (data_va, data_pa) = alloc_dma(1);
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let received_fis = unsafe { &mut *(rfis_va as *mut AHCIReceivedFIS) };
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let cmd_list = unsafe {
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slice::from_raw_parts_mut(
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cmd_list_va as *mut AHCICommandHeader,
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PAGE_SIZE / size_of::<AHCICommandHeader>(),
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)
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};
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let cmd_table = unsafe { &mut *(cmd_table_va as *mut AHCICommandTable) };
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let identify_data = unsafe { &*(data_va as *mut ATAIdentifyPacket) };
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cmd_table.prdt[0].data_base_address = data_pa as u64;
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cmd_table.prdt[0].dbc_i = (BLOCK_SIZE - 1) as u32;
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cmd_list[0].command_table_base_address = cmd_table_pa as u64;
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cmd_list[0].prdt_length = 1;
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cmd_list[0].prd_byte_count = 0;
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port.command_list_base_address.write(cmd_list_pa as u64);
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port.fis_base_address.write(rfis_pa as u64);
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// clear status and errors
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port.command_issue.write(0);
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port.sata_active.write(0);
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port.sata_error.write(0);
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// enable port
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port.command.update(|c| {
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*c |= 1 << 0 | 1 << 1 | 1 << 2 | 1 << 4 | 1 << 28;
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});
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let stat = port.sata_status.read();
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if stat == 0 {
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warn!("port is not connected to external drive?");
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}
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let fis = &mut cmd_table.cfis;
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// Register FIS from HBA to device
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fis.fis_type = FIS_REG_H2D;
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fis.cflags = 1 << 7;
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// 7.15 IDENTIFY DEVICE - ECh, PIO Data-In
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fis.command = CMD_IDENTIFY_DEVICE;
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fis.sector_count = 1;
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port.issue_command(0);
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port.spin_on_slot(0);
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unsafe {
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debug!(
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"Found ATA Device serial {} firmware {} model {} sectors 24bit={} 48bit={}",
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from_ata_string(&identify_data.serial).trim_end(),
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from_ata_string(&identify_data.firmware).trim_end(),
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from_ata_string(&identify_data.model).trim_end(),
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identify_data.lba_sectors,
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identify_data.lba48_sectors,
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);
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}
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|
||||
let data = unsafe { slice::from_raw_parts_mut(data_va as *mut u8, BLOCK_SIZE) };
|
||||
|
||||
let driver = AHCIDriver(Mutex::new(AHCI {
|
||||
header,
|
||||
size,
|
||||
received_fis,
|
||||
cmd_list,
|
||||
cmd_table,
|
||||
data,
|
||||
port,
|
||||
}));
|
||||
|
||||
let driver = Arc::new(driver);
|
||||
DRIVERS.write().push(driver.clone());
|
||||
BLK_DRIVERS
|
||||
.write()
|
||||
.push(Arc::new(BlockDriver(driver.clone())));
|
||||
|
||||
return driver;
|
||||
}
|
||||
}
|
||||
|
||||
unimplemented!();
|
||||
}
|
||||
@ -1 +1,2 @@
|
||||
pub mod ahci;
|
||||
pub mod virtio_blk;
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit 69febc9fcc64df60329687b4f24b9b5309c99adf
|
||||
Subproject commit b1e7a2d07e81ce5035a1cc25b0ade9367aee1a94
|
||||
Loading…
Reference in new issue