From ef213d60bb29c9acee1eb47211cb341d89f89a6d Mon Sep 17 00:00:00 2001 From: koumingyang <1761674434@qq.com> Date: Thu, 15 Nov 2018 14:22:57 +0800 Subject: [PATCH 01/16] mmu --- crate/aarch64/Cargo.lock | 68 +++ crate/aarch64/Cargo.toml | 16 + crate/aarch64/src/addr.rs | 418 ++++++++++++++ crate/aarch64/src/asm.rs | 162 ++++++ crate/aarch64/src/barrier.rs | 87 +++ crate/aarch64/src/lib.rs | 29 + crate/aarch64/src/paging/frame_alloc.rs | 15 + crate/aarch64/src/paging/mod.rs | 528 +++++++++++++++++ crate/aarch64/src/paging/page_table.rs | 185 ++++++ crate/aarch64/src/paging/recursive.rs | 623 +++++++++++++++++++++ crate/aarch64/src/regs/cntfrq_el0.rs | 31 + crate/aarch64/src/regs/cnthctl_el2.rs | 75 +++ crate/aarch64/src/regs/cntp_ctl_el0.rs | 62 ++ crate/aarch64/src/regs/cntp_tval_el0.rs | 30 + crate/aarch64/src/regs/cntpct_el0.rs | 29 + crate/aarch64/src/regs/cntvoff_el2.rs | 32 ++ crate/aarch64/src/regs/currentel.rs | 52 ++ crate/aarch64/src/regs/daif.rs | 90 +++ crate/aarch64/src/regs/elr_el2.rs | 30 + crate/aarch64/src/regs/hcr_el2.rs | 123 ++++ crate/aarch64/src/regs/id_aa64mmfr0_el1.rs | 82 +++ crate/aarch64/src/regs/macros.rs | 85 +++ crate/aarch64/src/regs/mair_el1.rs | 105 ++++ crate/aarch64/src/regs/mod.rs | 51 ++ crate/aarch64/src/regs/mpidr_el1.rs | 30 + crate/aarch64/src/regs/sctlr_el1.rs | 103 ++++ crate/aarch64/src/regs/sp.rs | 28 + crate/aarch64/src/regs/sp_el0.rs | 31 + crate/aarch64/src/regs/sp_el1.rs | 36 ++ crate/aarch64/src/regs/spsel.rs | 48 ++ crate/aarch64/src/regs/spsr_el2.rs | 106 ++++ crate/aarch64/src/regs/tcr_el1.rs | 178 ++++++ crate/aarch64/src/regs/ttbr0_el1.rs | 56 ++ kernel/Cargo.lock | 14 + kernel/Cargo.toml | 1 + kernel/src/arch/aarch64/memory.rs | 65 ++- kernel/src/arch/aarch64/paging.rs | 339 ++++++----- kernel/src/lib.rs | 2 + 38 files changed, 3896 insertions(+), 149 deletions(-) create mode 100644 crate/aarch64/Cargo.lock create mode 100644 crate/aarch64/Cargo.toml create mode 100644 crate/aarch64/src/addr.rs create mode 100644 crate/aarch64/src/asm.rs create mode 100644 crate/aarch64/src/barrier.rs create mode 100644 crate/aarch64/src/lib.rs create mode 100644 crate/aarch64/src/paging/frame_alloc.rs create mode 100644 crate/aarch64/src/paging/mod.rs create mode 100644 crate/aarch64/src/paging/page_table.rs create mode 100644 crate/aarch64/src/paging/recursive.rs create mode 100644 crate/aarch64/src/regs/cntfrq_el0.rs create mode 100644 crate/aarch64/src/regs/cnthctl_el2.rs create mode 100644 crate/aarch64/src/regs/cntp_ctl_el0.rs create mode 100644 crate/aarch64/src/regs/cntp_tval_el0.rs create mode 100644 crate/aarch64/src/regs/cntpct_el0.rs create mode 100644 crate/aarch64/src/regs/cntvoff_el2.rs create mode 100644 crate/aarch64/src/regs/currentel.rs create mode 100644 crate/aarch64/src/regs/daif.rs create mode 100644 crate/aarch64/src/regs/elr_el2.rs create mode 100644 crate/aarch64/src/regs/hcr_el2.rs create mode 100644 crate/aarch64/src/regs/id_aa64mmfr0_el1.rs create mode 100644 crate/aarch64/src/regs/macros.rs create mode 100644 crate/aarch64/src/regs/mair_el1.rs create mode 100644 crate/aarch64/src/regs/mod.rs create mode 100644 crate/aarch64/src/regs/mpidr_el1.rs create mode 100644 crate/aarch64/src/regs/sctlr_el1.rs create mode 100644 crate/aarch64/src/regs/sp.rs create mode 100644 crate/aarch64/src/regs/sp_el0.rs create mode 100644 crate/aarch64/src/regs/sp_el1.rs create mode 100644 crate/aarch64/src/regs/spsel.rs create mode 100644 crate/aarch64/src/regs/spsr_el2.rs create mode 100644 crate/aarch64/src/regs/tcr_el1.rs create mode 100644 crate/aarch64/src/regs/ttbr0_el1.rs diff --git a/crate/aarch64/Cargo.lock b/crate/aarch64/Cargo.lock new file mode 100644 index 0000000..2d0a329 --- /dev/null +++ b/crate/aarch64/Cargo.lock @@ -0,0 +1,68 @@ +[[package]] +name = "aarch64" +version = "0.1.0" +dependencies = [ + "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", + "bitflags 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0000000..7514dd0 --- /dev/null +++ b/crate/aarch64/Cargo.toml @@ -0,0 +1,16 @@ +[package] +name = "aarch64" +version = "0.1.0" +authors = ["koumingyang <1761674434@qq.com>"] + +[dependencies] +register = "0.2.0" +bit_field = "0.9.0" +bitflags = "1.0.1" +usize_conversions = "0.2.0" +os_bootinfo = "0.2.0" +bare-metal = "0.2.0" + +[dependencies.ux] +default-features = false +version = "0.1.0" \ No newline at end of file diff --git a/crate/aarch64/src/addr.rs b/crate/aarch64/src/addr.rs new file mode 100644 index 0000000..e347567 --- /dev/null +++ b/crate/aarch64/src/addr.rs @@ -0,0 +1,418 @@ +use core::convert::{Into, TryInto}; +use core::fmt; +use core::ops::{Add, AddAssign, Sub, SubAssign}; + +use bit_field::BitField; +use usize_conversions::FromUsize; +use ux::*; + +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +#[repr(transparent)] +pub struct VirtAddr(u64); + +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +#[repr(transparent)] +pub struct PhysAddr(u64); + +#[derive(Debug)] +pub struct VirtAddrNotValid(u64); + +impl VirtAddr { + /// Creates a new canonical virtual address. + /// + /// This function performs sign extension of bit 47 to make the address canonical. Panics + /// if the bits in the range 48 to 64 contain data (i.e. are not null and no sign extension). + pub fn new(addr: u64) -> VirtAddr { + Self::try_new(addr).expect( + "invalid virtual address", + ) + } + + /// Tries to create a new canonical virtual address. + /// in aarch64, valid virtual address starts with 0x0000 or 0xffff. + pub fn try_new(addr: u64) -> Result { + match addr.get_bits(48..64) { + 0 | 0xffff => Ok(VirtAddr(addr)), // address is canonical + other => Err(VirtAddrNotValid(other)), + } + } + + pub fn new_unchecked(addr: u64) -> VirtAddr { + VirtAddr(addr) + } + + /// Creates a virtual address that points to `0`. + pub const fn zero() -> VirtAddr { + VirtAddr(0) + } + + /// Converts the address to an `u64`. + pub fn as_u64(self) -> u64 { + self.0 + } + + /// Creates a virtual address from the given pointer + pub fn from_ptr(ptr: *const T) -> Self { + use usize_conversions::FromUsize; + + Self::new(u64::from_usize(ptr as usize)) + } + + /// Converts the address to a raw pointer. + #[cfg(target_pointer_width = "64")] + pub fn as_ptr(self) -> *const T { + use usize_conversions::usize_from; + + usize_from(self.as_u64()) as *const T + } + + /// Converts the address to a mutable raw pointer. + #[cfg(target_pointer_width = "64")] + pub fn as_mut_ptr(self) -> *mut T { + self.as_ptr::() as *mut T + } + + /// Aligns the virtual address upwards to the given alignment. + /// + /// See the `align_up` function for more information. + pub fn align_up(self, align: U) -> Self + where + U: Into, + { + VirtAddr(align_up(self.0, align.into())) + } + + /// Aligns the virtual address downwards to the given alignment. + /// + /// See the `align_down` function for more information. + pub fn align_down(self, align: U) -> Self + where + U: Into, + { + VirtAddr(align_down(self.0, align.into())) + } + + /// Checks whether the virtual address has the demanded alignment. + pub fn is_aligned(self, align: U) -> bool + where + U: Into, + { + self.align_down(align) == self + } + + /// Returns the 12-bit page offset of this virtual address. + pub fn page_offset(&self) -> u12 { + u12::new((self.0 & 0xfff).try_into().unwrap()) + } + + /// Returns the 9-bit level 1 page table index. + pub fn p1_index(&self) -> u9 { + u9::new(((self.0 >> 12) & 0o777).try_into().unwrap()) + } + + /// Returns the 9-bit level 2 page table index. + pub fn p2_index(&self) -> u9 { + u9::new(((self.0 >> 12 >> 9) & 0o777).try_into().unwrap()) + } + + /// Returns the 9-bit level 3 page table index. + pub fn p3_index(&self) -> u9 { + u9::new(((self.0 >> 12 >> 9 >> 9) & 0o777).try_into().unwrap()) + } + + /// Returns the 9-bit level 4 page table index. + pub fn p4_index(&self) -> u9 { + u9::new(((self.0 >> 12 >> 9 >> 9 >> 9) & 0o777).try_into().unwrap()) + } +} + +impl fmt::Debug for VirtAddr { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "VirtAddr({:#x})", self.0) + } +} + +impl Add for VirtAddr { + type Output = Self; + fn add(self, rhs: u64) -> Self::Output { + VirtAddr::new(self.0 + rhs) + } +} + +impl AddAssign for VirtAddr { + fn add_assign(&mut self, rhs: u64) { + *self = *self + rhs; + } +} + +impl Add for VirtAddr +where + u64: FromUsize, +{ + type Output = Self; + fn add(self, rhs: usize) -> Self::Output { + self + u64::from_usize(rhs) + } +} + +impl AddAssign for VirtAddr +where + u64: FromUsize, +{ + fn add_assign(&mut self, rhs: usize) { + self.add_assign(u64::from_usize(rhs)) + } +} + +impl Sub for VirtAddr { + type Output = Self; + fn sub(self, rhs: u64) -> Self::Output { + VirtAddr::new(self.0.checked_sub(rhs).unwrap()) + } +} + +impl SubAssign for VirtAddr { + fn sub_assign(&mut self, rhs: u64) { + *self = *self - rhs; + } +} + +impl Sub for VirtAddr +where + u64: FromUsize, +{ + type Output = Self; + fn sub(self, rhs: usize) -> Self::Output { + self - u64::from_usize(rhs) + } +} + +impl SubAssign for VirtAddr +where + u64: FromUsize, +{ + fn sub_assign(&mut self, rhs: usize) { + self.sub_assign(u64::from_usize(rhs)) + } +} + +impl Sub for VirtAddr { + type Output = u64; + fn sub(self, rhs: VirtAddr) -> Self::Output { + self.as_u64().checked_sub(rhs.as_u64()).unwrap() + } +} + +/// A passed `u64` was not a valid physical address. +/// +/// This means that bits 52 to 64 are not were not all null. +#[derive(Debug)] +pub struct PhysAddrNotValid(u64); + +impl PhysAddr { + /// Creates a new physical address. + /// + /// Panics if a bit in the range 52 to 64 is set. + pub fn new(addr: u64) -> PhysAddr { + assert_eq!( + addr.get_bits(52..64), + 0, + "physical addresses must not have any bits in the range 52 to 64 set" + ); + PhysAddr(addr) + } + + /// Tries to create a new physical address. + /// + /// Fails if any bits in the range 52 to 64 are set. + pub fn try_new(addr: u64) -> Result { + match addr.get_bits(52..64) { + 0 => Ok(PhysAddr(addr)), // address is valid + other => Err(PhysAddrNotValid(other)), + } + } + + /// Converts the address to an `u64`. + pub fn as_u64(self) -> u64 { + self.0 + } + + /// Convenience method for checking if a physical address is null. + pub fn is_null(&self) -> bool { + self.0 == 0 + } + + /// Aligns the physical address upwards to the given alignment. + /// + /// See the `align_up` function for more information. + pub fn align_up(self, align: U) -> Self + where + U: Into, + { + PhysAddr(align_up(self.0, align.into())) + } + + /// Aligns the physical address downwards to the given alignment. + /// + /// See the `align_down` function for more information. + pub fn align_down(self, align: U) -> Self + where + U: Into, + { + PhysAddr(align_down(self.0, align.into())) + } + + /// Checks whether the physical address has the demanded alignment. + pub fn is_aligned(self, align: U) -> bool + where + U: Into, + { + self.align_down(align) == self + } +} + +impl fmt::Debug for PhysAddr { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "PhysAddr({:#x})", self.0) + } +} + +impl fmt::Binary for PhysAddr { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + self.0.fmt(f) + } +} + +impl fmt::LowerHex for PhysAddr { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + self.0.fmt(f) + } +} + +impl fmt::Octal for PhysAddr { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + self.0.fmt(f) + } +} + +impl fmt::UpperHex for PhysAddr { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + self.0.fmt(f) + } +} + +impl Add for PhysAddr { + type Output = Self; + fn add(self, rhs: u64) -> Self::Output { + PhysAddr::new(self.0 + rhs) + } +} + +impl AddAssign for PhysAddr { + fn add_assign(&mut self, rhs: u64) { + *self = *self + rhs; + } +} + +impl Add for PhysAddr +where + u64: FromUsize, +{ + type Output = Self; + fn add(self, rhs: usize) -> Self::Output { + self + u64::from_usize(rhs) + } +} + +impl AddAssign for PhysAddr +where + u64: FromUsize, +{ + fn add_assign(&mut self, rhs: usize) { + self.add_assign(u64::from_usize(rhs)) + } +} + +impl Sub for PhysAddr { + type Output = Self; + fn sub(self, rhs: u64) -> Self::Output { + PhysAddr::new(self.0.checked_sub(rhs).unwrap()) + } +} + +impl SubAssign for PhysAddr { + fn sub_assign(&mut self, rhs: u64) { + *self = *self - rhs; + } +} + +impl Sub for PhysAddr +where + u64: FromUsize, +{ + type Output = Self; + fn sub(self, rhs: usize) -> Self::Output { + self - u64::from_usize(rhs) + } +} + +impl SubAssign for PhysAddr +where + u64: FromUsize, +{ + fn sub_assign(&mut self, rhs: usize) { + self.sub_assign(u64::from_usize(rhs)) + } +} + +impl Sub for PhysAddr { + type Output = u64; + fn sub(self, rhs: PhysAddr) -> Self::Output { + self.as_u64().checked_sub(rhs.as_u64()).unwrap() + } +} + +/// Align address downwards. +/// +/// Returns the greatest x with alignment `align` so that x <= addr. The alignment must be +/// a power of 2. +pub fn align_down(addr: u64, align: u64) -> u64 { + assert!(align.is_power_of_two(), "`align` must be a power of two"); + addr & !(align - 1) +} + +/// Align address upwards. +/// +/// Returns the smallest x with alignment `align` so that x >= addr. The alignment must be +/// a power of 2. +pub fn align_up(addr: u64, align: u64) -> u64 { + assert!(align.is_power_of_two(), "`align` must be a power of two"); + let align_mask = align - 1; + if addr & align_mask == 0 { + addr // already aligned + } else { + (addr | align_mask) + 1 + } +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + pub fn test_align_up() { + // align 1 + assert_eq!(align_up(0, 1), 0); + assert_eq!(align_up(1234, 1), 1234); + assert_eq!(align_up(0xffffffffffffffff, 1), 0xffffffffffffffff); + // align 2 + assert_eq!(align_up(0, 2), 0); + assert_eq!(align_up(1233, 2), 1234); + assert_eq!(align_up(0xfffffffffffffffe, 2), 0xfffffffffffffffe); + // address 0 + assert_eq!(align_up(0, 128), 0); + assert_eq!(align_up(0, 1), 0); + assert_eq!(align_up(0, 2), 0); + assert_eq!(align_up(0, 0x8000000000000000), 0); + } +} diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs new file mode 100644 index 0000000..d97fa78 --- /dev/null +++ b/crate/aarch64/src/asm.rs @@ -0,0 +1,162 @@ +use paging::PhysFrame; +use addr::PhysAddr; +use regs::*; + +#[inline(always)] +pub fn tlb_invalidate() { + unsafe{ + asm!("dsb ishst + tlbi vmalle1is + dsb ish + tlbi vmalle1is + isb"); + } +} + +/// Returns the current stack pointer. +#[inline(always)] +pub fn sp() -> *const u8 { + let ptr: usize; + unsafe { + asm!("mov $0, sp" : "=r"(ptr)); + } + + ptr as *const u8 +} + +#[inline(always)] +pub unsafe fn get_pc() -> usize { + let pc: usize; + asm!("ADR $0, ." : "=r"(pc)); + pc +} + +/// Returns the current exception level. +/// +/// # Safety +/// This function should only be called when EL is >= 1. +#[inline(always)] +pub unsafe fn current_el() -> u8 { + let el_reg: u64; + asm!("mrs $0, CurrentEL" : "=r"(el_reg)); + ((el_reg & 0b1100) >> 2) as u8 +} + +#[inline(always)] +pub unsafe fn get_far() -> usize { + let far: usize; + asm!("mrs $0, far_el1" : "=r"(far)); + far +} + +#[inline(always)] +pub unsafe fn get_ttbr0() -> usize { + let ttbr0: usize; + asm!("mrs $0, ttbr0_el1" : "=r"(ttbr0)); + ttbr0 +} + +#[inline(always)] +pub unsafe fn get_ttbr1() -> usize { + let ttbr0: usize; + asm!("mrs $0, ttbr1_el1" : "=r"(ttbr0)); + ttbr0 +} + +/// Returns the SPSel value. +#[inline(always)] +pub fn sp_sel() -> u8 { + let ptr: u32; + unsafe { + asm!("mrs $0, SPSel" : "=r"(ptr)); + } + + (ptr & 1) as u8 +} + +/// Returns the core currently executing. +/// +/// # Safety +/// +/// This function should only be called when EL is >= 1. +pub unsafe fn affinity() -> usize { + let x: usize; + asm!("mrs $0, mpidr_el1 + and $0, $0, #3" + : "=r"(x)); + + x +} + +pub fn wfi() { + unsafe { + asm!("wfi" :::: "volatile"); + } +} + + +/// The classic no-op +#[inline] +pub fn nop() { + match () { + #[cfg(target_arch = "aarch64")] + () => unsafe { asm!("nop" :::: "volatile") }, + + #[cfg(not(target_arch = "aarch64"))] + () => unimplemented!(), + } +} + +/// Wait For Event +#[inline] +pub fn wfe() { + match () { + #[cfg(target_arch = "aarch64")] + () => unsafe { asm!("wfe" :::: "volatile") }, + + #[cfg(not(target_arch = "aarch64"))] + () => unimplemented!(), + } +} + +/// Exception return +/// +/// Will jump to wherever the corresponding link register points to, and +/// therefore never return. +#[inline] +pub fn eret() -> ! { + use core; + + match () { + #[cfg(target_arch = "aarch64")] + () => unsafe { + asm!("eret" :::: "volatile"); + core::intrinsics::unreachable() + }, + + #[cfg(not(target_arch = "aarch64"))] + () => unimplemented!(), + } +} + +bitflags! { + /// Controls cache settings for the level 4 page table. + pub struct ttbr0_el1_Flags: u64 { + + const COMMON_NOT_PRIVATE = 1 << 0; + } +} + +pub fn ttbr0_el1_read() -> (PhysFrame, ttbr0_el1_Flags) { + let value = TTBR0_EL1.get(); + let flags = ttbr0_el1_Flags::from_bits_truncate(value); + let addr = PhysAddr::new(value & 0x_000f_ffff_ffff_f000); + let frame = PhysFrame::containing_address(addr); + (frame, flags) +} + +pub fn ttbr0_el1_write(frame: PhysFrame) { + let addr = frame.start_address(); + let value = addr.as_u64(); + TTBR0_EL1.set_baddr(value); +} diff --git a/crate/aarch64/src/barrier.rs b/crate/aarch64/src/barrier.rs new file mode 100644 index 0000000..0e48209 --- /dev/null +++ b/crate/aarch64/src/barrier.rs @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +// Borrow implementations from the pending upstream ACLE implementation until it +// is merged. Afterwards, we'll probably just reexport them, hoping that the API +// doesn't change. +// +// https://github.com/rust-lang-nursery/stdsimd/pull/557 + +mod sealed { + pub trait Dmb { + unsafe fn __dmb(&self); + } + + pub trait Dsb { + unsafe fn __dsb(&self); + } + + pub trait Isb { + unsafe fn __isb(&self); + } +} + +macro_rules! dmb_dsb { + ($A:ident) => { + impl sealed::Dmb for $A { + #[inline(always)] + unsafe fn __dmb(&self) { + asm!(concat!("DMB ", stringify!($A)) : : : "memory" : "volatile") + } + } + impl sealed::Dsb for $A { + #[inline(always)] + unsafe fn __dsb(&self) { + asm!(concat!("DSB ", stringify!($A)) : : : "memory" : "volatile") + } + } + }; +} + +pub struct SY; + +dmb_dsb!(SY); + +impl sealed::Isb for SY { + #[inline(always)] + unsafe fn __isb(&self) { + asm!("ISB SY" : : : "memory" : "volatile") + } +} + +#[inline(always)] +pub unsafe fn dmb(arg: A) +where + A: sealed::Dmb, +{ + arg.__dmb() +} + +#[inline(always)] +pub unsafe fn dsb(arg: A) +where + A: sealed::Dsb, +{ + arg.__dsb() +} + +#[inline(always)] +pub unsafe fn isb(arg: A) +where + A: sealed::Isb, +{ + arg.__isb() +} diff --git a/crate/aarch64/src/lib.rs b/crate/aarch64/src/lib.rs new file mode 100644 index 0000000..bb8bf72 --- /dev/null +++ b/crate/aarch64/src/lib.rs @@ -0,0 +1,29 @@ +#![no_std] +//#![deny(warnings)] +#![feature(asm)] +#![feature(const_fn)] +#![feature(core_intrinsics)] +#![feature(try_from)] + +extern crate bare_metal; +#[macro_use] +extern crate register; +#[macro_use] +extern crate bitflags; +extern crate bit_field; +extern crate os_bootinfo; +extern crate usize_conversions; + +/// Provides the non-standard-width integer types `u2`–`u63`. +/// +/// We use these integer types in various APIs, for example `u9` for page tables indices. +pub extern crate ux; + +pub use addr::{align_down, align_up, PhysAddr, VirtAddr}; + +pub mod asm; +pub mod addr; +pub mod paging; +pub mod barrier; +pub mod regs; + diff --git a/crate/aarch64/src/paging/frame_alloc.rs b/crate/aarch64/src/paging/frame_alloc.rs new file mode 100644 index 0000000..f3ea4c8 --- /dev/null +++ b/crate/aarch64/src/paging/frame_alloc.rs @@ -0,0 +1,15 @@ +//! Traits for abstracting away frame allocation and deallocation. + +use paging::{PageSize, PhysFrame}; + +/// A trait for types that can allocate a frame of memory. +pub trait FrameAllocator { + /// Allocate a frame of the appropriate size and return it if possible. + fn alloc(&mut self) -> Option>; +} + +/// A trait for types that can deallocate a frame of memory. +pub trait FrameDeallocator { + /// Deallocate the given frame of memory. + fn dealloc(&mut self, frame: PhysFrame); +} diff --git a/crate/aarch64/src/paging/mod.rs b/crate/aarch64/src/paging/mod.rs new file mode 100644 index 0000000..56073b2 --- /dev/null +++ b/crate/aarch64/src/paging/mod.rs @@ -0,0 +1,528 @@ +//! Abstractions for page tables and other paging related structures. +//! +//! Page tables translate virtual memory “pages” to physical memory “frames”. + +pub use self::frame_alloc::*; +pub use self::page_table::*; +#[cfg(target_arch = "aarch64")] +pub use self::recursive::*; + +use core::fmt; +use core::marker::PhantomData; +use core::ops::{Add, AddAssign, Sub, SubAssign}; +use os_bootinfo; +use ux::*; +use addr::{PhysAddr, VirtAddr}; + +mod frame_alloc; +mod page_table; +mod recursive; + +/// Trait for abstracting over the three possible page sizes on x86_64, 4KiB, 2MiB, 1GiB. +pub trait PageSize: Copy + Eq + PartialOrd + Ord { + /// The page size in bytes. + const SIZE: u64; + + /// A string representation of the page size for debug output. + const SIZE_AS_DEBUG_STR: &'static str; +} + +/// This trait is implemented for 4KiB and 2MiB pages, but not for 1GiB pages. +pub trait NotGiantPageSize: PageSize {} + +/// A standard 4KiB page. +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub enum Size4KiB {} + +/// A “huge” 2MiB page. +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub enum Size2MiB {} + +/// A “giant” 1GiB page. +/// +/// (Only available on newer x86_64 CPUs.) +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub enum Size1GiB {} + +impl PageSize for Size4KiB { + const SIZE: u64 = 4096; + const SIZE_AS_DEBUG_STR: &'static str = "4KiB"; +} + +impl NotGiantPageSize for Size4KiB {} + +impl PageSize for Size2MiB { + const SIZE: u64 = Size4KiB::SIZE * 512; + const SIZE_AS_DEBUG_STR: &'static str = "2MiB"; +} + +impl NotGiantPageSize for Size2MiB {} + +impl PageSize for Size1GiB { + const SIZE: u64 = Size2MiB::SIZE * 512; + const SIZE_AS_DEBUG_STR: &'static str = "1GiB"; +} + +/// A virtual memory page. +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +#[repr(C)] +pub struct Page { + start_address: VirtAddr, + size: PhantomData, +} + +impl Page { + /// Returns the page that starts at the given virtual address. + /// + /// Returns an error if the address is not correctly aligned (i.e. is not a valid page start). + pub fn from_start_address(address: VirtAddr) -> Result { + if !address.is_aligned(S::SIZE) { + return Err(()); + } + Ok(Page::containing_address(address)) + } + + /// Returns the page that contains the given virtual address. + pub fn containing_address(address: VirtAddr) -> Self { + Page { + start_address: address.align_down(S::SIZE), + size: PhantomData, + } + } + + /// Returns the start address of the page. + pub fn start_address(&self) -> VirtAddr { + self.start_address + } + + /// Returns the size the page (4KB, 2MB or 1GB). + pub const fn size(&self) -> u64 { + S::SIZE + } + + /// Returns the level 4 page table index of this page. + pub fn p4_index(&self) -> u9 { + self.start_address().p4_index() + } + + /// Returns the level 3 page table index of this page. + pub fn p3_index(&self) -> u9 { + self.start_address().p3_index() + } + + /// Returns a range of pages, exclusive `end`. + pub fn range(start: Self, end: Self) -> PageRange { + PageRange { start, end } + } + + /// Returns a range of pages, inclusive `end`. + pub fn range_inclusive(start: Self, end: Self) -> PageRangeInclusive { + PageRangeInclusive { start, end } + } +} + +impl Page { + /// Returns the level 2 page table index of this page. + pub fn p2_index(&self) -> u9 { + self.start_address().p2_index() + } +} + +impl Page { + /// Returns the 1GiB memory page with the specified page table indices. + pub fn from_page_table_indices_1gib(p4_index: u9, p3_index: u9) -> Self { + use bit_field::BitField; + + let mut addr = 0; + addr.set_bits(39..48, u64::from(p4_index)); + addr.set_bits(30..39, u64::from(p3_index)); + Page::containing_address(VirtAddr::new(addr)) + } +} + +impl Page { + /// Returns the 2MiB memory page with the specified page table indices. + pub fn from_page_table_indices_2mib(p4_index: u9, p3_index: u9, p2_index: u9) -> Self { + use bit_field::BitField; + + let mut addr = 0; + addr.set_bits(39..48, u64::from(p4_index)); + addr.set_bits(30..39, u64::from(p3_index)); + addr.set_bits(21..30, u64::from(p2_index)); + Page::containing_address(VirtAddr::new(addr)) + } +} + +impl Page { + /// Returns the 4KiB memory page with the specified page table indices. + pub fn from_page_table_indices(p4_index: u9, p3_index: u9, p2_index: u9, p1_index: u9) -> Self { + use bit_field::BitField; + + let mut addr = 0; + addr.set_bits(39..48, u64::from(p4_index)); + addr.set_bits(30..39, u64::from(p3_index)); + addr.set_bits(21..30, u64::from(p2_index)); + addr.set_bits(12..21, u64::from(p1_index)); + Page::containing_address(VirtAddr::new(addr)) + } + + /// Returns the level 1 page table index of this page. + pub fn p1_index(&self) -> u9 { + self.start_address().p1_index() + } +} + +impl fmt::Debug for Page { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.write_fmt(format_args!( + "Page[{}]({:#x})", + S::SIZE_AS_DEBUG_STR, + self.start_address().as_u64() + )) + } +} + +impl Add for Page { + type Output = Self; + fn add(self, rhs: u64) -> Self::Output { + Page::containing_address(self.start_address() + rhs * u64::from(S::SIZE)) + } +} + +impl AddAssign for Page { + fn add_assign(&mut self, rhs: u64) { + *self = self.clone() + rhs; + } +} + +impl Sub for Page { + type Output = Self; + fn sub(self, rhs: u64) -> Self::Output { + Page::containing_address(self.start_address() - rhs * u64::from(S::SIZE)) + } +} + +impl SubAssign for Page { + fn sub_assign(&mut self, rhs: u64) { + *self = self.clone() - rhs; + } +} + +impl Sub for Page { + type Output = u64; + fn sub(self, rhs: Self) -> Self::Output { + (self.start_address - rhs.start_address) / S::SIZE + } +} + +/// A range of pages with exclusive upper bound. +#[derive(Clone, Copy, PartialEq, Eq)] +#[repr(C)] +pub struct PageRange { + /// The start of the range, inclusive. + pub start: Page, + /// The end of the range, exclusive. + pub end: Page, +} + +impl PageRange { + /// Returns wether this range contains no pages. + pub fn is_empty(&self) -> bool { + !(self.start < self.end) + } +} + +impl Iterator for PageRange { + type Item = Page; + + fn next(&mut self) -> Option { + if self.start < self.end { + let page = self.start.clone(); + self.start += 1; + Some(page) + } else { + None + } + } +} + +impl PageRange { + /// Converts the range of 2MiB pages to a range of 4KiB pages. + pub fn as_4kib_page_range(self) -> PageRange { + PageRange { + start: Page::containing_address(self.start.start_address()), + end: Page::containing_address(self.end.start_address()), + } + } +} + +impl fmt::Debug for PageRange { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("PageRange") + .field("start", &self.start) + .field("end", &self.end) + .finish() + } +} + +/// A range of pages with inclusive upper bound. +#[derive(Clone, Copy, PartialEq, Eq)] +#[repr(C)] +pub struct PageRangeInclusive { + /// The start of the range, inclusive. + pub start: Page, + /// The end of the range, inclusive. + pub end: Page, +} + +impl PageRangeInclusive { + /// Returns wether this range contains no pages. + pub fn is_empty(&self) -> bool { + !(self.start <= self.end) + } +} + +impl Iterator for PageRangeInclusive { + type Item = Page; + + fn next(&mut self) -> Option { + if self.start <= self.end { + let page = self.start.clone(); + self.start += 1; + Some(page) + } else { + None + } + } +} + +impl fmt::Debug for PageRangeInclusive { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("PageRangeInclusive") + .field("start", &self.start) + .field("end", &self.end) + .finish() + } +} + +/// A physical memory frame. +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +#[repr(C)] +pub struct PhysFrame { + start_address: PhysAddr, + size: PhantomData, +} + +impl PhysFrame { + /// Returns the frame that starts at the given virtual address. + /// + /// Returns an error if the address is not correctly aligned (i.e. is not a valid frame start). + pub fn from_start_address(address: PhysAddr) -> Result { + if !address.is_aligned(S::SIZE) { + return Err(()); + } + Ok(PhysFrame::containing_address(address)) + } + + /// Returns the frame that contains the given physical address. + pub fn containing_address(address: PhysAddr) -> Self { + PhysFrame { + start_address: address.align_down(S::SIZE), + size: PhantomData, + } + } + + /// Returns the start address of the frame. + pub fn start_address(&self) -> PhysAddr { + self.start_address + } + + /// Returns the size the frame (4KB, 2MB or 1GB). + pub fn size(&self) -> u64 { + S::SIZE + } + + /// Returns a range of frames, exclusive `end`. + pub fn range(start: PhysFrame, end: PhysFrame) -> PhysFrameRange { + PhysFrameRange { start, end } + } + + /// Returns a range of frames, inclusive `end`. + pub fn range_inclusive(start: PhysFrame, end: PhysFrame) -> PhysFrameRangeInclusive { + PhysFrameRangeInclusive { start, end } + } +} + +impl fmt::Debug for PhysFrame { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.write_fmt(format_args!( + "PhysFrame[{}]({:#x})", + S::SIZE_AS_DEBUG_STR, + self.start_address().as_u64() + )) + } +} + +impl Add for PhysFrame { + type Output = Self; + fn add(self, rhs: u64) -> Self::Output { + PhysFrame::containing_address(self.start_address() + rhs * u64::from(S::SIZE)) + } +} + +impl AddAssign for PhysFrame { + fn add_assign(&mut self, rhs: u64) { + *self = self.clone() + rhs; + } +} + +impl Sub for PhysFrame { + type Output = Self; + fn sub(self, rhs: u64) -> Self::Output { + PhysFrame::containing_address(self.start_address() - rhs * u64::from(S::SIZE)) + } +} + +impl SubAssign for PhysFrame { + fn sub_assign(&mut self, rhs: u64) { + *self = self.clone() - rhs; + } +} + +impl Sub> for PhysFrame { + type Output = u64; + fn sub(self, rhs: PhysFrame) -> Self::Output { + (self.start_address - rhs.start_address) / S::SIZE + } +} + +/// An range of physical memory frames, exclusive the upper bound. +#[derive(Clone, Copy, PartialEq, Eq)] +#[repr(C)] +pub struct PhysFrameRange { + /// The start of the range, inclusive. + pub start: PhysFrame, + /// The end of the range, exclusive. + pub end: PhysFrame, +} + +impl PhysFrameRange { + /// Returns whether the range contains no frames. + pub fn is_empty(&self) -> bool { + !(self.start < self.end) + } +} + +impl Iterator for PhysFrameRange { + type Item = PhysFrame; + + fn next(&mut self) -> Option { + if self.start < self.end { + let frame = self.start.clone(); + self.start += 1; + Some(frame) + } else { + None + } + } +} + +impl From for PhysFrameRange { + fn from(range: os_bootinfo::FrameRange) -> Self { + PhysFrameRange { + start: PhysFrame::from_start_address(PhysAddr::new(range.start_addr())).unwrap(), + end: PhysFrame::from_start_address(PhysAddr::new(range.end_addr())).unwrap(), + } + } +} + +impl Into for PhysFrameRange { + fn into(self) -> os_bootinfo::FrameRange { + os_bootinfo::FrameRange::new( + self.start.start_address().as_u64(), + self.end.start_address().as_u64(), + ) + } +} + +impl fmt::Debug for PhysFrameRange { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("PhysFrameRange") + .field("start", &self.start) + .field("end", &self.end) + .finish() + } +} + +/// An range of physical memory frames, inclusive the upper bound. +#[derive(Clone, Copy, PartialEq, Eq)] +#[repr(C)] +pub struct PhysFrameRangeInclusive { + /// The start of the range, inclusive. + pub start: PhysFrame, + /// The start of the range, exclusive. + pub end: PhysFrame, +} + +impl PhysFrameRangeInclusive { + /// Returns whether the range contains no frames. + pub fn is_empty(&self) -> bool { + !(self.start <= self.end) + } +} + +impl Iterator for PhysFrameRangeInclusive { + type Item = PhysFrame; + + fn next(&mut self) -> Option { + if self.start <= self.end { + let frame = self.start.clone(); + self.start += 1; + Some(frame) + } else { + None + } + } +} + +impl fmt::Debug for PhysFrameRangeInclusive { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("PhysFrameRangeInclusive") + .field("start", &self.start) + .field("end", &self.end) + .finish() + } +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + pub fn test_page_ranges() { + let page_size = Size4KiB::SIZE; + let number = 1000; + + let start_addr = VirtAddr::new(0xdeadbeaf); + let start: Page = Page::containing_address(start_addr); + let end = start.clone() + number; + + let mut range = Page::range(start.clone(), end.clone()); + for i in 0..number { + assert_eq!( + range.next(), + Some(Page::containing_address(start_addr + page_size * i)) + ); + } + assert_eq!(range.next(), None); + + let mut range_inclusive = Page::range_inclusive(start, end); + for i in 0..=number { + assert_eq!( + range_inclusive.next(), + Some(Page::containing_address(start_addr + page_size * i)) + ); + } + assert_eq!(range_inclusive.next(), None); + } +} diff --git a/crate/aarch64/src/paging/page_table.rs b/crate/aarch64/src/paging/page_table.rs new file mode 100644 index 0000000..b074768 --- /dev/null +++ b/crate/aarch64/src/paging/page_table.rs @@ -0,0 +1,185 @@ +use core::fmt; +use core::ops::{Index, IndexMut}; + +use super::{PageSize, PhysFrame, Size4KiB}; +use addr::PhysAddr; + +use usize_conversions::usize_from; +use ux::*; + +/// The error returned by the `PageTableEntry::frame` method. +#[derive(Debug, Clone, Copy, PartialEq)] +pub enum FrameError { + /// The entry does not have the `PRESENT` flag set, so it isn't currently mapped to a frame. + FrameNotPresent, + /// The entry does have the `HUGE_PAGE` flag set. The `frame` method has a standard 4KiB frame + /// as return type, so a huge frame can't be returned. + HugeFrame, +} + +/// A 64-bit page table entry. +#[derive(Clone)] +#[repr(transparent)] +pub struct PageTableEntry { + entry: u64, +} + +impl PageTableEntry { + /// Returns whether this entry is zero. + pub fn is_unused(&self) -> bool { + self.entry == 0 + } + + /// Sets this entry to zero. + pub fn set_unused(&mut self) { + self.entry = 0; + } + + /// Returns the flags of this entry. + pub fn flags(&self) -> PageTableFlags { + PageTableFlags::from_bits_truncate(self.entry) + } + + /// Returns the physical address mapped by this entry, might be zero. + pub fn addr(&self) -> PhysAddr { + PhysAddr::new(self.entry & 0x000fffff_fffff000) + } + + /// Returns the physical frame mapped by this entry. + /// + /// Returns the following errors: + /// + /// - `FrameError::FrameNotPresent` if the entry doesn't have the `PRESENT` flag set. + /// - `FrameError::HugeFrame` if the entry has the `HUGE_PAGE` flag set (for huge pages the + /// `addr` function must be used) + pub fn frame(&self) -> Result { + if !self.flags().contains(PageTableFlags::PRESENT) { + Err(FrameError::FrameNotPresent) + } else if self.flags().contains(PageTableFlags::HUGE_PAGE) { + Err(FrameError::HugeFrame) + } else { + Ok(PhysFrame::containing_address(self.addr())) + } + } + + /// Map the entry to the specified physical address with the specified flags. + pub fn set_addr(&mut self, addr: PhysAddr, flags: PageTableFlags) { + assert!(addr.is_aligned(Size4KiB::SIZE)); + self.entry = (addr.as_u64()) | flags.bits(); + } + + /// Map the entry to the specified physical frame with the specified flags. + pub fn set_frame(&mut self, frame: PhysFrame, flags: PageTableFlags) { + assert!(!flags.contains(PageTableFlags::HUGE_PAGE)); + self.set_addr(frame.start_address(), flags) + } + + /// Sets the flags of this entry. + pub fn set_flags(&mut self, flags: PageTableFlags) { + self.entry = self.addr().as_u64() | flags.bits(); + } +} + +impl fmt::Debug for PageTableEntry { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + let mut f = f.debug_struct("PageTableEntry"); + f.field("addr", &self.addr()); + f.field("flags", &self.flags()); + f.finish() + } +} + +bitflags! { + /// Possible flags for a page table entry. + pub struct PageTableFlags: u64 { + const ALL = 0xffffffff_ffffffff; + const TYPE_MASK = 3 << 0; + const TYPE_FAULT = 0 << 0; + const TYPE_PAGE = 3 << 0; + const TABLE_BIT = 1 << 1; + + const PRESENT = 1 << 0; + const USER_ACCESSIBLE = 1 << 6; /* AP[1] */ + const RDONLY = 1 << 7; /* AP[2] */ + const SHARED = 3 << 8; /* SH[1:0], inner shareable */ + const BIT_8 = 1 << 8; + const BIT_9 = 1 << 9; + /* + pub const ATTRIB_SH_NON_SHAREABLE: usize = 0x0 << 8; + pub const ATTRIB_SH_OUTER_SHAREABLE: usize = 0x2 << 8; + pub const ATTRIB_SH_INNER_SHAREABLE: usize = 0x3 << 8; + */ + + const ACCESSED = 1 << 10; /* AF, Access Flag */ + const NONE_GLOBAL = 1 << 11; /* None Global */ + const GLOBAL = (!(1 << 11)); + const DBM = 1 << 51; /* Dirty Bit Management */ + const WRITE = 1 << 51; /* DBM */ + const CONT = 1 << 52; /* Contiguous range */ + const PXN = 1 << 53; /* Privileged XN */ + const UXN = 1 << 54; /* User XN */ + const HYP_XN = 1 << 54; /* HYP XN */ + const DIRTY = 1 << 55; + const SWAPPED = 1 << 56; + const HUGE_PAGE = 1 << 57; + const PROT_NONE = 1 << 58; + + } +} + +/// The number of entries in a page table. +const ENTRY_COUNT: usize = 512; + +/// Represents a page table. +/// +/// Always page-sized. +/// +/// This struct implements the `Index` and `IndexMut` traits, so the entries can be accessed +/// through index operations. For example, `page_table[15]` returns the 15th page table entry. +#[repr(transparent)] +pub struct PageTable { + entries: [PageTableEntry; ENTRY_COUNT], +} + +impl PageTable { + /// Clears all entries. + pub fn zero(&mut self) { + for entry in self.entries.iter_mut() { + entry.set_unused(); + } + } +} + +impl Index for PageTable { + type Output = PageTableEntry; + + fn index(&self, index: usize) -> &Self::Output { + &self.entries[index] + } +} + +impl IndexMut for PageTable { + fn index_mut(&mut self, index: usize) -> &mut Self::Output { + &mut self.entries[index] + } +} + +impl Index for PageTable { + type Output = PageTableEntry; + + fn index(&self, index: u9) -> &Self::Output { + &self.entries[usize_from(u16::from(index))] + } +} + +impl IndexMut for PageTable { + fn index_mut(&mut self, index: u9) -> &mut Self::Output { + &mut self.entries[usize_from(u16::from(index))] + } +} + +impl fmt::Debug for PageTable { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + self.entries[..].fmt(f) + } +} diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs new file mode 100644 index 0000000..0cbc6d0 --- /dev/null +++ b/crate/aarch64/src/paging/recursive.rs @@ -0,0 +1,623 @@ +#![cfg(target_arch = "aarch64")] + +use asm::tlb_invalidate; +use paging::{ + frame_alloc::FrameAllocator, + page_table::{FrameError, PageTable, PageTableEntry, PageTableFlags}, + NotGiantPageSize, Page, PageSize, PhysFrame, Size1GiB, Size2MiB, Size4KiB, +}; +use paging::page_table::PageTableFlags as Flags; +use asm::ttbr0_el1_read; +use ux::u9; +use addr::{PhysAddr, VirtAddr}; + +/// This type represents a page whose mapping has changed in the page table. +/// +/// The old mapping might be still cached in the translation lookaside buffer (TLB), so it needs +/// to be flushed from the TLB before it's accessed. This type is returned from function that +/// change the mapping of a page to ensure that the TLB flush is not forgotten. +#[derive(Debug)] +#[must_use = "Page Table changes must be flushed or ignored."] +pub struct MapperFlush(Page); + +impl MapperFlush { + /// Create a new flush promise + fn new(page: Page) -> Self { + MapperFlush(page) + } + + /// Flush the page from the TLB to ensure that the newest mapping is used. + pub fn flush(self) { + tlb_invalidate(); + } + + /// Don't flush the TLB and silence the “must be used” warning. + pub fn ignore(self) {} +} + +/// A trait for common page table operations. +pub trait Mapper { + /// Creates a new mapping in the page table. + /// + /// This function might need additional physical frames to create new page tables. These + /// frames are allocated from the `allocator` argument. At most three frames are required. + fn map_to( + &mut self, + page: Page, + frame: PhysFrame, + flags: PageTableFlags, + allocator: &mut A, + ) -> Result, MapToError> + where + A: FrameAllocator; + + /// Removes a mapping from the page table and returns the frame that used to be mapped. + /// + /// Note that no page tables or pages are deallocated. + fn unmap(&mut self, page: Page) -> Result<(PhysFrame, MapperFlush), UnmapError>; + + /// Updates the flags of an existing mapping. + fn update_flags( + &mut self, + page: Page, + flags: PageTableFlags, + ) -> Result, FlagUpdateError>; + + /// Return the frame that the specified page is mapped to. + fn translate_page(&self, page: Page) -> Option>; + + /// Maps the given frame to the virtual page with the same address. + fn identity_map( + &mut self, + frame: PhysFrame, + flags: PageTableFlags, + allocator: &mut A, + ) -> Result, MapToError> + where + A: FrameAllocator, + S: PageSize, + Self: Mapper, + { + let page = Page::containing_address(VirtAddr::new(frame.start_address().as_u64())); + self.map_to(page, frame, flags, allocator) + } +} + +/// A recursive page table is a last level page table with an entry mapped to the table itself. +/// +/// This recursive mapping allows accessing all page tables in the hierarchy: +/// +/// - To access the level 4 page table, we “loop“ (i.e. follow the recursively mapped entry) four +/// times. +/// - To access a level 3 page table, we “loop” three times and then use the level 4 index. +/// - To access a level 2 page table, we “loop” two times, then use the level 4 index, then the +/// level 3 index. +/// - To access a level 1 page table, we “loop” once, then use the level 4 index, then the +/// level 3 index, then the level 2 index. +/// +/// This struct implements the `Mapper` trait. +#[derive(Debug)] +pub struct RecursivePageTable<'a> { + p4: &'a mut PageTable, + recursive_index: u9, +} + +/// An error indicating that the given page table is not recursively mapped. +/// +/// Returned from `RecursivePageTable::new`. +#[derive(Debug)] +pub struct NotRecursivelyMapped; + +/// This error is returned from `map_to` and similar methods. +#[derive(Debug)] +pub enum MapToError { + /// An additional frame was needed for the mapping process, but the frame allocator + /// returned `None`. + FrameAllocationFailed, + /// An upper level page table entry has the `HUGE_PAGE` flag set, which means that the + /// given page is part of an already mapped huge page. + ParentEntryHugePage, + /// The given page is already mapped to a physical frame. + PageAlreadyMapped, +} + +/// An error indicating that an `unmap` call failed. +#[derive(Debug)] +pub enum UnmapError { + /// An upper level page table entry has the `HUGE_PAGE` flag set, which means that the + /// given page is part of a huge page and can't be freed individually. + ParentEntryHugePage, + /// The given page is not mapped to a physical frame. + PageNotMapped, + /// The page table entry for the given page points to an invalid physical address. + InvalidFrameAddress(PhysAddr), +} + +/// An error indicating that an `update_flags` call failed. +#[derive(Debug)] +pub enum FlagUpdateError { + /// The given page is not mapped to a physical frame. + PageNotMapped, +} + +impl<'a> RecursivePageTable<'a> { + /// Creates a new RecursivePageTable from the passed level 4 PageTable. + /// + /// The page table must be recursively mapped, that means: + /// + /// - The page table must have one recursive entry, i.e. an entry that points to the table + /// itself. + /// - The reference must use that “loop”, i.e. be of the form `0o_xxx_xxx_xxx_xxx_0000` + /// where `xxx` is the recursive entry. + /// - The page table must be active, i.e. the CR3 register must contain its physical address. + /// + /// Otherwise `Err(NotRecursivelyMapped)` is returned. + pub fn new(table: &'a mut PageTable) -> Result { + let page = Page::containing_address(VirtAddr::new(table as *const _ as u64)); + let recursive_index = page.p4_index(); + + if page.p3_index() != recursive_index + || page.p2_index() != recursive_index + || page.p1_index() != recursive_index + { + return Err(NotRecursivelyMapped); + } + if Ok(ttbr0_el1_read().0) != table[recursive_index].frame() { + return Err(NotRecursivelyMapped); + } + + Ok(RecursivePageTable { + p4: table, + recursive_index, + }) + } + + /// Creates a new RecursivePageTable without performing any checks. + /// + /// The `recursive_index` parameter must be the index of the recursively mapped entry. + pub unsafe fn new_unchecked(table: &'a mut PageTable, recursive_index: u9) -> Self { + RecursivePageTable { + p4: table, + recursive_index, + } + } + + /// Internal helper function to create the page table of the next level if needed. + /// + /// If the passed entry is unused, a new frame is allocated from the given allocator, zeroed, + /// and the entry is updated to that address. If the passed entry is already mapped, the next + /// table is returned directly. + /// + /// The `next_page_table` page must be the page of the next page table in the hierarchy. + /// + /// Returns `MapToError::FrameAllocationFailed` if the entry is unused and the allocator + /// returned `None`. Returns `MapToError::ParentEntryHugePage` if the `HUGE_PAGE` flag is set + /// in the passed entry. + unsafe fn create_next_table<'b, A>( + entry: &'b mut PageTableEntry, + next_table_page: Page, + allocator: &mut A, + ) -> Result<&'b mut PageTable, MapToError> + where + A: FrameAllocator, + { + /// This inner function is used to limit the scope of `unsafe`. + /// + /// This is a safe function, so we need to use `unsafe` blocks when we do something unsafe. + fn inner<'b, A>( + entry: &'b mut PageTableEntry, + next_table_page: Page, + allocator: &mut A, + ) -> Result<&'b mut PageTable, MapToError> + where + A: FrameAllocator, + { + + let created; + + if entry.is_unused() { + if let Some(frame) = allocator.alloc() { + entry.set_frame(frame, Flags::PRESENT | Flags::WRITE); + created = true; + } else { + return Err(MapToError::FrameAllocationFailed); + } + } else { + created = false; + } + if entry.flags().contains(Flags::HUGE_PAGE) { + return Err(MapToError::ParentEntryHugePage); + } + + let page_table_ptr = next_table_page.start_address().as_mut_ptr(); + let page_table: &mut PageTable = unsafe { &mut *(page_table_ptr) }; + if created { + page_table.zero(); + } + Ok(page_table) + } + + inner(entry, next_table_page, allocator) + } +} + +impl<'a> Mapper for RecursivePageTable<'a> { + fn map_to( + &mut self, + page: Page, + frame: PhysFrame, + flags: PageTableFlags, + allocator: &mut A, + ) -> Result, MapToError> + where + A: FrameAllocator, + { + let p4 = &mut self.p4; + + let p3_page = p3_page(page, self.recursive_index); + let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; + + if !p3[page.p3_index()].is_unused() { + return Err(MapToError::PageAlreadyMapped); + } + p3[page.p3_index()].set_addr(frame.start_address(), flags | Flags::HUGE_PAGE); + + Ok(MapperFlush::new(page)) + } + + fn unmap( + &mut self, + page: Page, + ) -> Result<(PhysFrame, MapperFlush), UnmapError> { + let p4 = &mut self.p4; + let p4_entry = &p4[page.p4_index()]; + + p4_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + let p3_entry = &mut p3[page.p3_index()]; + let flags = p3_entry.flags(); + + if !flags.contains(PageTableFlags::PRESENT) { + return Err(UnmapError::PageNotMapped); + } + if !flags.contains(PageTableFlags::HUGE_PAGE) { + return Err(UnmapError::ParentEntryHugePage); + } + + let frame = PhysFrame::from_start_address(p3_entry.addr()) + .map_err(|()| UnmapError::InvalidFrameAddress(p3_entry.addr()))?; + + p3_entry.set_unused(); + Ok((frame, MapperFlush::new(page))) + } + + fn update_flags( + &mut self, + page: Page, + flags: PageTableFlags, + ) -> Result, FlagUpdateError> { + let p4 = &mut self.p4; + + if p4[page.p4_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + + if p3[page.p3_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + p3[page.p3_index()].set_flags(flags | Flags::HUGE_PAGE); + + Ok(MapperFlush::new(page)) + } + + fn translate_page(&self, page: Page) -> Option> { + let p4 = &self.p4; + + if p4[page.p4_index()].is_unused() { + return None; + } + + let p3 = unsafe { &*(p3_ptr(page, self.recursive_index)) }; + let p3_entry = &p3[page.p3_index()]; + + if p3_entry.is_unused() { + return None; + } + + PhysFrame::from_start_address(p3_entry.addr()).ok() + } +} + +impl<'a> Mapper for RecursivePageTable<'a> { + fn map_to( + &mut self, + page: Page, + frame: PhysFrame, + flags: PageTableFlags, + allocator: &mut A, + ) -> Result, MapToError> + where + A: FrameAllocator, + { + let p4 = &mut self.p4; + + let p3_page = p3_page(page, self.recursive_index); + let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; + + let p2_page = p2_page(page, self.recursive_index); + let p2 = unsafe { Self::create_next_table(&mut p3[page.p3_index()], p2_page, allocator)? }; + + if !p2[page.p2_index()].is_unused() { + return Err(MapToError::PageAlreadyMapped); + } + p2[page.p2_index()].set_addr(frame.start_address(), flags | Flags::HUGE_PAGE); + + Ok(MapperFlush::new(page)) + } + + fn unmap( + &mut self, + page: Page, + ) -> Result<(PhysFrame, MapperFlush), UnmapError> { + let p4 = &mut self.p4; + let p4_entry = &p4[page.p4_index()]; + p4_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + let p3_entry = &p3[page.p3_index()]; + p3_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; + let p2_entry = &mut p2[page.p2_index()]; + let flags = p2_entry.flags(); + + if !flags.contains(PageTableFlags::PRESENT) { + return Err(UnmapError::PageNotMapped); + } + if !flags.contains(PageTableFlags::HUGE_PAGE) { + return Err(UnmapError::ParentEntryHugePage); + } + + let frame = PhysFrame::from_start_address(p2_entry.addr()) + .map_err(|()| UnmapError::InvalidFrameAddress(p2_entry.addr()))?; + + p2_entry.set_unused(); + Ok((frame, MapperFlush::new(page))) + } + + fn update_flags( + &mut self, + page: Page, + flags: PageTableFlags, + ) -> Result, FlagUpdateError> { + let p4 = &mut self.p4; + + if p4[page.p4_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + + if p3[page.p3_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; + + if p2[page.p2_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + p2[page.p2_index()].set_flags(flags | Flags::HUGE_PAGE); + + Ok(MapperFlush::new(page)) + } + + fn translate_page(&self, page: Page) -> Option> { + let p4 = &self.p4; + + if p4[page.p4_index()].is_unused() { + return None; + } + + let p3 = unsafe { &*(p3_ptr(page, self.recursive_index)) }; + let p3_entry = &p3[page.p3_index()]; + + if p3_entry.is_unused() { + return None; + } + + let p2 = unsafe { &*(p2_ptr(page, self.recursive_index)) }; + let p2_entry = &p2[page.p2_index()]; + + if p2_entry.is_unused() { + return None; + } + + PhysFrame::from_start_address(p2_entry.addr()).ok() + } +} + +impl<'a> Mapper for RecursivePageTable<'a> { + fn map_to( + &mut self, + page: Page, + frame: PhysFrame, + flags: PageTableFlags, + allocator: &mut A, + ) -> Result, MapToError> + where + A: FrameAllocator, + { + let p4 = &mut self.p4; + + let p3_page = p3_page(page, self.recursive_index); + let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; + + let p2_page = p2_page(page, self.recursive_index); + let p2 = unsafe { Self::create_next_table(&mut p3[page.p3_index()], p2_page, allocator)? }; + + let p1_page = p1_page(page, self.recursive_index); + let p1 = unsafe { Self::create_next_table(&mut p2[page.p2_index()], p1_page, allocator)? }; + + if !p1[page.p1_index()].is_unused() { + return Err(MapToError::PageAlreadyMapped); + } + p1[page.p1_index()].set_frame(frame, flags); + + Ok(MapperFlush::new(page)) + } + + fn unmap( + &mut self, + page: Page, + ) -> Result<(PhysFrame, MapperFlush), UnmapError> { + let p4 = &mut self.p4; + let p4_entry = &p4[page.p4_index()]; + p4_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + let p3_entry = &p3[page.p3_index()]; + p3_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; + let p2_entry = &p2[page.p2_index()]; + p2_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + let p1 = unsafe { &mut *(p1_ptr(page, self.recursive_index)) }; + let p1_entry = &mut p1[page.p1_index()]; + + let frame = p1_entry.frame().map_err(|err| match err { + FrameError::FrameNotPresent => UnmapError::PageNotMapped, + FrameError::HugeFrame => UnmapError::ParentEntryHugePage, + })?; + + p1_entry.set_unused(); + Ok((frame, MapperFlush::new(page))) + } + + fn update_flags( + &mut self, + page: Page, + flags: PageTableFlags, + ) -> Result, FlagUpdateError> { + let p4 = &mut self.p4; + + if p4[page.p4_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + + if p3[page.p3_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; + + if p2[page.p2_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + let p1 = unsafe { &mut *(p1_ptr(page, self.recursive_index)) }; + + if p1[page.p1_index()].is_unused() { + return Err(FlagUpdateError::PageNotMapped); + } + + p1[page.p1_index()].set_flags(flags); + + Ok(MapperFlush::new(page)) + } + + fn translate_page(&self, page: Page) -> Option> { + let p4 = &self.p4; + + if p4[page.p4_index()].is_unused() { + return None; + } + + let p3 = unsafe { &*(p3_ptr(page, self.recursive_index)) }; + let p3_entry = &p3[page.p3_index()]; + + if p3_entry.is_unused() { + return None; + } + + let p2 = unsafe { &*(p2_ptr(page, self.recursive_index)) }; + let p2_entry = &p2[page.p2_index()]; + + if p2_entry.is_unused() { + return None; + } + + let p1 = unsafe { &*(p1_ptr(page, self.recursive_index)) }; + let p1_entry = &p1[page.p1_index()]; + + if p1_entry.is_unused() { + return None; + } + + PhysFrame::from_start_address(p1_entry.addr()).ok() + } +} + +fn p3_ptr(page: Page, recursive_index: u9) -> *mut PageTable { + p3_page(page, recursive_index).start_address().as_mut_ptr() +} + +fn p3_page(page: Page, recursive_index: u9) -> Page { + Page::from_page_table_indices( + recursive_index, + recursive_index, + recursive_index, + page.p4_index(), + ) +} + +fn p2_ptr(page: Page, recursive_index: u9) -> *mut PageTable { + p2_page(page, recursive_index).start_address().as_mut_ptr() +} + +fn p2_page(page: Page, recursive_index: u9) -> Page { + Page::from_page_table_indices( + recursive_index, + recursive_index, + page.p4_index(), + page.p3_index(), + ) +} + +fn p1_ptr(page: Page, recursive_index: u9) -> *mut PageTable { + p1_page(page, recursive_index).start_address().as_mut_ptr() +} + +fn p1_page(page: Page, recursive_index: u9) -> Page { + Page::from_page_table_indices( + recursive_index, + page.p4_index(), + page.p3_index(), + page.p2_index(), + ) +} diff --git a/crate/aarch64/src/regs/cntfrq_el0.rs b/crate/aarch64/src/regs/cntfrq_el0.rs new file mode 100644 index 0000000..df56ac9 --- /dev/null +++ b/crate/aarch64/src/regs/cntfrq_el0.rs @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Counter-timer Frequency register - EL0 +//! +//! This register is provided so that software can discover the frequency of the +//! system counter. It must be programmed with this value as part of system +//! initialization. The value of the register is not interpreted by hardware. + +use register::cpu::RegisterReadOnly; + +pub struct Reg; + +impl RegisterReadOnly for Reg { + sys_coproc_read_raw!(u32, "CNTFRQ_EL0"); +} + +pub static CNTFRQ_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cnthctl_el2.rs b/crate/aarch64/src/regs/cnthctl_el2.rs new file mode 100644 index 0000000..f5e3c2c --- /dev/null +++ b/crate/aarch64/src/regs/cnthctl_el2.rs @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Counter-timer Hypervisor Control register - EL2 +//! +//! Controls the generation of an event stream from the physical counter, and +//! access from Non-secure EL1 to the physical counter and the Non-secure EL1 +//! physical timer. + +use register::cpu::RegisterReadWrite; + +// When HCR_EL2.E2H == 0: +// TODO: Figure out how we can differentiate depending on HCR_EL2.E2H state +// +// For now, implement the HCR_EL2.E2H == 0 version +register_bitfields! {u32, + CNTHCTL_EL2 [ + /// Traps Non-secure EL0 and EL1 accesses to the physical timer + /// registers to EL2. + /// + /// 0 From AArch64 state: Non-secure EL0 and EL1 accesses to the + /// CNTP_CTL_EL0, CNTP_CVAL_EL0, and CNTP_TVAL_EL0 are trapped to EL2, + /// unless it is trapped by CNTKCTL_EL1.EL0PTEN. + /// + /// From AArch32 state: Non-secure EL0 and EL1 accesses to the + /// CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to EL2, unless it + /// is trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN. + /// + /// 1 This control does not cause any instructions to be trapped. + /// + /// If EL3 is implemented and EL2 is not implemented, behavior is as if + /// this bit is 1 other than for the purpose of a direct read. + EL1PCEN OFFSET(1) NUMBITS(1) [], + + /// Traps Non-secure EL0 and EL1 accesses to the physical counter + /// register to EL2. + /// + /// 0 From AArch64 state: Non-secure EL0 and EL1 accesses to the + /// CNTPCT_EL0 are trapped to EL2, unless it is trapped by + /// CNTKCTL_EL1.EL0PCTEN. + /// + /// From AArch32 state: Non-secure EL0 and EL1 accesses to the CNTPCT + /// are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PCTEN + /// or CNTKCTL.PL0PCTEN. + /// + /// 1 This control does not cause any instructions to be trapped. + /// + /// If EL3 is implemented and EL2 is not implemented, behavior is as if + /// this bit is 1 other than for the purpose of a direct read. + EL1PCTEN OFFSET(0) NUMBITS(1) [] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "CNTHCTL_EL2"); + sys_coproc_write_raw!(u32, "CNTHCTL_EL2"); +} + +#[allow(non_upper_case_globals)] +pub static CNTHCTL_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntp_ctl_el0.rs b/crate/aarch64/src/regs/cntp_ctl_el0.rs new file mode 100644 index 0000000..76991eb --- /dev/null +++ b/crate/aarch64/src/regs/cntp_ctl_el0.rs @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Counter-timer Physical Timer Control register - EL0 +//! +//! Control register for the EL1 physical timer. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u32, + CNTP_CTL_EL0 [ + /// The status of the timer. This bit indicates whether the timer + /// condition is met: + /// + /// 0 Timer condition is not met. + /// 1 Timer condition is met. + /// + /// When the value of the ENABLE bit is 1, ISTATUS indicates whether the + /// timer condition is met. ISTATUS takes no account of the value of the + /// IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 + /// then the timer interrupt is asserted. + /// + /// When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN. + /// + /// This bit is read-only. + ISTATUS OFFSET(2) NUMBITS(1) [], + + /// Timer interrupt mask bit. Permitted values are: + /// + /// 0 Timer interrupt is not masked by the IMASK bit. + /// 1 Timer interrupt is masked by the IMASK bit. + IMASK OFFSET(1) NUMBITS(1) [], + + /// Enables the timer. Permitted values are: + /// + /// 0 Timer disabled. + /// 1 Timer enabled. + ENABLE OFFSET(0) NUMBITS(1) [] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "CNTP_CTL_EL0"); + sys_coproc_write_raw!(u32, "CNTP_CTL_EL0"); +} + +pub static CNTP_CTL_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntp_tval_el0.rs b/crate/aarch64/src/regs/cntp_tval_el0.rs new file mode 100644 index 0000000..bdf5f6a --- /dev/null +++ b/crate/aarch64/src/regs/cntp_tval_el0.rs @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Counter-timer Physical Timer TimerValue register - EL0 +//! +//! Holds the timer value for the EL1 physical timer. + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "CNTP_TVAL_EL0"); + sys_coproc_write_raw!(u32, "CNTP_TVAL_EL0"); +} + +pub static CNTP_TVAL_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntpct_el0.rs b/crate/aarch64/src/regs/cntpct_el0.rs new file mode 100644 index 0000000..b381d99 --- /dev/null +++ b/crate/aarch64/src/regs/cntpct_el0.rs @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Counter-timer Physical Count register - EL0 +//! +//! Holds the 64-bit physical count value. + +use register::cpu::RegisterReadOnly; + +pub struct Reg; + +impl RegisterReadOnly for Reg { + sys_coproc_read_raw!(u64, "CNTPCT_EL0"); +} + +pub static CNTPCT_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntvoff_el2.rs b/crate/aarch64/src/regs/cntvoff_el2.rs new file mode 100644 index 0000000..aff7074 --- /dev/null +++ b/crate/aarch64/src/regs/cntvoff_el2.rs @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Counter-timer Virtual Offset register - EL2 +//! +//! Holds the 64-bit virtual offset. This is the offset between the physical +//! count value visible in CNTPCT_EL0 and the virtual count value visible in +//! CNTVCT_EL0. + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "CNTVOFF_EL2"); + sys_coproc_write_raw!(u64, "CNTVOFF_EL2"); +} + +pub static CNTVOFF_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/currentel.rs b/crate/aarch64/src/regs/currentel.rs new file mode 100644 index 0000000..91b8e0a --- /dev/null +++ b/crate/aarch64/src/regs/currentel.rs @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Current Exception Level +//! +//! Holds the current Exception level. + +use register::cpu::RegisterReadOnly; + +register_bitfields! {u32, + CurrentEL [ + /// Current Exception level. Possible values of this field are: + /// + /// 00 EL0 + /// 01 EL1 + /// 10 EL2 + /// 11 EL3 + /// + /// When the HCR_EL2.NV bit is 1, Non-secure EL1 read accesses to the + /// CurrentEL register return the value of 0x2 in this field. + /// + /// This field resets to a value that is architecturally UNKNOWN. + EL OFFSET(2) NUMBITS(2) [ + EL0 = 0, + EL1 = 1, + EL2 = 2, + EL3 = 3 + ] + ] +} + +pub struct Reg; + +impl RegisterReadOnly for Reg { + sys_coproc_read_raw!(u32, "CurrentEL"); +} + +#[allow(non_upper_case_globals)] +pub static CurrentEL: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/daif.rs b/crate/aarch64/src/regs/daif.rs new file mode 100644 index 0000000..bf810a2 --- /dev/null +++ b/crate/aarch64/src/regs/daif.rs @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Interrupt Mask Bits +//! +//! Allows access to the interrupt mask bits. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u32, + DAIF [ + /// Process state D mask. The possible values of this bit are: + /// + /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at + /// the current Exception level are not masked. + /// + /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at + /// the current Exception level are masked. + /// + /// When the target Exception level of the debug exception is higher + /// than the current Exception level, the exception is not masked by + /// this bit. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 1. + D OFFSET(9) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// SError interrupt mask bit. The possible values of this bit are: + /// + /// 0 Exception not masked. + /// 1 Exception masked. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 1 . + A OFFSET(8) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// IRQ mask bit. The possible values of this bit are: + /// + /// 0 Exception not masked. + /// 1 Exception masked. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 1 . + I OFFSET(7) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// FIQ mask bit. The possible values of this bit are: + /// + /// 0 Exception not masked. + /// 1 Exception masked. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 1 . + F OFFSET(6) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ] + ] +} + + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "DAIF"); + sys_coproc_write_raw!(u32, "DAIF"); +} + +pub static DAIF: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/elr_el2.rs b/crate/aarch64/src/regs/elr_el2.rs new file mode 100644 index 0000000..0786fbb --- /dev/null +++ b/crate/aarch64/src/regs/elr_el2.rs @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Exception Link Register - EL2 +//! +//! When taking an exception to EL2, holds the address to return to. + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "ELR_EL2"); + sys_coproc_write_raw!(u64, "ELR_EL2"); +} + +pub static ELR_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/hcr_el2.rs b/crate/aarch64/src/regs/hcr_el2.rs new file mode 100644 index 0000000..683bbef --- /dev/null +++ b/crate/aarch64/src/regs/hcr_el2.rs @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Hypervisor Configuration Register - EL2 +//! +//! Provides configuration controls for virtualization, including defining +//! whether various Non-secure operations are trapped to EL2. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u64, + HCR_EL2 [ + /// Execution state control for lower Exception levels: + /// + /// 0 Lower levels are all AArch32. + /// 1 The Execution state for EL1 is AArch64. The Execution state for + /// EL0 is determined by the current value of PSTATE.nRW when + /// executing at EL0. + /// + /// If all lower Exception levels cannot use AArch32 then this bit is + /// RAO/WI. + /// + /// In an implementation that includes EL3, when SCR_EL3.NS==0, the PE + /// behaves as if this bit has the same value as the SCR_EL3.RW bit for + /// all purposes other than a direct read or write access of HCR_EL2. + /// + /// The RW bit is permitted to be cached in a TLB. + /// + /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} + /// is {1, 1}, this field behaves as 1 for all purposes other than a + /// direct read of the value of this bit. + RW OFFSET(31) NUMBITS(1) [ + AllLowerELsAreAarch32 = 0, + EL1IsAarch64 = 1 + ], + + /// Default Cacheability. + /// + /// 0 This control has no effect on the Non-secure EL1&0 translation + /// regime. + /// + /// 1 In Non-secure state: + /// - When EL1 is using AArch64, the PE behaves as if the value of + /// the SCTLR_EL1.M field is 0 for all purposes other than + /// returning the value of a direct read of SCTLR_EL1. + /// + /// - When EL1 is using AArch32, the PE behaves as if the value of + /// the SCTLR.M field is 0 for all purposes other than returning + /// the value of a direct read of SCTLR. + /// + /// - The PE behaves as if the value of the HCR_EL2.VM field is 1 + /// for all purposes other than returning the value of a direct + /// read of HCR_EL2. + /// + /// - The memory type produced by stage 1 of the EL1&0 translation + /// regime is Normal Non-Shareable, Inner Write-Back Read-Allocate + /// Write-Allocate, Outer Write-Back Read-Allocate Write-Allocate. + /// + /// This field has no effect on the EL2, EL2&0, and EL3 translation + /// regimes. + /// + /// This field is permitted to be cached in a TLB. + /// + /// In an implementation that includes EL3, when the value of SCR_EL3.NS + /// is 0 the PE behaves as if this field is 0 for all purposes other + /// than a direct read or write access of HCR_EL2. + /// + /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} + /// is {1, 1}, this field behaves as 0 for all purposes other than a + /// direct read of the value of this field. + DC OFFSET(12) NUMBITS(1) [], + + /// Set/Way Invalidation Override. Causes Non-secure EL1 execution of + /// the data cache invalidate by set/way instructions to perform a data + /// cache clean and invalidate by set/way: + /// + /// 0 This control has no effect on the operation of data cache + /// invalidate by set/way instructions. + /// + /// 1 Data cache invalidate by set/way instructions perform a data cache + /// clean and invalidate by set/way. + /// + /// When the value of this bit is 1: + /// + /// AArch32: DCISW performs the same invalidation as a DCCISW + /// instruction. + /// + /// AArch64: DC ISW performs the same invalidation as a DC CISW + /// instruction. + /// + /// This bit can be implemented as RES 1. + /// + /// In an implementation that includes EL3, when the value of SCR_EL3.NS + /// is 0 the PE behaves as if this field is 0 for all purposes other + /// than a direct read or write access of HCR_EL2. + /// + /// When HCR_EL2.TGE is 1, the PE ignores the value of this field for + /// all purposes other than a direct read of this field. + SWIO OFFSET(1) NUMBITS(1) [] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "HCR_EL2"); + sys_coproc_write_raw!(u64, "HCR_EL2"); +} + +pub static HCR_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/id_aa64mmfr0_el1.rs b/crate/aarch64/src/regs/id_aa64mmfr0_el1.rs new file mode 100644 index 0000000..f75813c --- /dev/null +++ b/crate/aarch64/src/regs/id_aa64mmfr0_el1.rs @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! AArch64 Memory Model Feature Register 0 - EL1 +//! +//! Provides information about the implemented memory model and memory +//! management support in AArch64 state. + +use register::cpu::RegisterReadOnly; + +register_bitfields! {u64, + ID_AA64MMFR0_EL1 [ + /// Support for 4KiB memory translation granule size. Defined values + /// are: + /// + /// 0000 4KiB granule supported. + /// 1111 4KiB granule not supported. + /// + /// All other values are reserved. + TGran4 OFFSET(28) NUMBITS(4) [ + Supported = 0b0000, + NotSupported = 0b1111 + ], + + /// Support for 64KiB memory translation granule size. Defined values + /// are: + /// + /// 0000 64KiB granule supported. + /// 1111 64KiB granule not supported. + /// + /// All other values are reserved. + TGran64 OFFSET(24) NUMBITS(4) [ + Supported = 0b0000, + NotSupported = 0b1111 + ], + + /// Physical Address range supported. Defined values are: + /// + /// 0000 32 bits, 4GiB. + /// 0001 36 bits, 64GiB. + /// 0010 40 bits, 1TiB. + /// 0011 42 bits, 4TiB. + /// 0100 44 bits, 16TiB. + /// 0101 48 bits, 256TiB. + /// 0110 52 bits, 4PiB. + /// + /// All other values are reserved. + /// + /// The value 0110 is permitted only if the implementation includes + /// ARMv8.2-LPA, otherwise it is reserved. + PARange OFFSET(0) NUMBITS(4) [ + Bits_32 = 0b0000, + Bits_36 = 0b0001, + Bits_40 = 0b0010, + Bits_42 = 0b0011, + Bits_44 = 0b0100, + Bits_48 = 0b0101, + Bits_52 = 0b0110 + ] + ] +} + +pub struct Reg; + +impl RegisterReadOnly for Reg { + sys_coproc_read_raw!(u64, "ID_AA64MMFR0_EL1"); +} + +pub static ID_AA64MMFR0_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/macros.rs b/crate/aarch64/src/regs/macros.rs new file mode 100644 index 0000000..bd4439c --- /dev/null +++ b/crate/aarch64/src/regs/macros.rs @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +macro_rules! __read_raw { + ($width:ty, $asm_instr:tt, $asm_reg_name:tt) => { + /// Reads the raw bits of the CPU register. + #[inline] + fn get(&self) -> $width { + match () { + #[cfg(target_arch = "aarch64")] + () => { + let reg; + unsafe { + asm!(concat!($asm_instr, " $0, ", $asm_reg_name) : "=r"(reg) ::: "volatile"); + } + reg + } + + #[cfg(not(target_arch = "aarch64"))] + () => unimplemented!(), + } + } + }; +} + +macro_rules! __write_raw { + ($width:ty, $asm_instr:tt, $asm_reg_name:tt) => { + /// Writes raw bits to the CPU register. + #[cfg_attr(not(target_arch = "aarch64"), allow(unused_variables))] + #[inline] + fn set(&self, value: $width) { + match () { + #[cfg(target_arch = "aarch64")] + () => { + unsafe { + asm!(concat!($asm_instr, " ", $asm_reg_name, ", $0") :: "r"(value) :: "volatile") + } + } + + #[cfg(not(target_arch = "aarch64"))] + () => unimplemented!(), + } + } + }; +} + +/// Raw read from system coprocessor registers +macro_rules! sys_coproc_read_raw { + ($width:ty, $asm_reg_name:tt) => { + __read_raw!($width, "mrs", $asm_reg_name); + }; +} + +/// Raw write to system coprocessor registers +macro_rules! sys_coproc_write_raw { + ($width:ty, $asm_reg_name:tt) => { + __write_raw!($width, "msr", $asm_reg_name); + }; +} + +/// Raw read from (ordinary) registers +macro_rules! read_raw { + ($width:ty, $asm_reg_name:tt) => { + __read_raw!($width, "mov", $asm_reg_name); + }; +} +/// Raw write to (ordinary) registers +macro_rules! write_raw { + ($width:ty, $asm_reg_name:tt) => { + __write_raw!($width, "mov", $asm_reg_name); + }; +} diff --git a/crate/aarch64/src/regs/mair_el1.rs b/crate/aarch64/src/regs/mair_el1.rs new file mode 100644 index 0000000..2c7c7da --- /dev/null +++ b/crate/aarch64/src/regs/mair_el1.rs @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Memory Attribute Indirection Register - EL1 +//! +//! Provides the memory attribute encodings corresponding to the possible +//! AttrIndx values in a Long-descriptor format translation table entry for +//! stage 1 translations at EL1. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u64, + MAIR_EL1 [ + // TODO: Macrofy this + + /// Attribute 7 + Attr7_HIGH OFFSET(60) NUMBITS(4) [], + Attr7_LOW_DEVICE OFFSET(56) NUMBITS(4) [], + Attr7_LOW_MEMORY OFFSET(56) NUMBITS(4) [], + + /// Attribute 6 + Attr6_HIGH OFFSET(52) NUMBITS(4) [], + Attr6_LOW_DEVICE OFFSET(48) NUMBITS(4) [], + Attr6_LOW_MEMORY OFFSET(48) NUMBITS(4) [], + + /// Attribute 5 + Attr5_HIGH OFFSET(44) NUMBITS(4) [], + Attr5_LOW_DEVICE OFFSET(40) NUMBITS(4) [], + Attr5_LOW_MEMORY OFFSET(40) NUMBITS(4) [], + + /// Attribute 4 + Attr4_HIGH OFFSET(36) NUMBITS(4) [], + Attr4_LOW_DEVICE OFFSET(32) NUMBITS(4) [], + Attr4_LOW_MEMORY OFFSET(32) NUMBITS(4) [], + + /// Attribute 3 + Attr3_HIGH OFFSET(28) NUMBITS(4) [], + Attr3_LOW_DEVICE OFFSET(24) NUMBITS(4) [], + Attr3_LOW_MEMORY OFFSET(24) NUMBITS(4) [], + + /// Attribute 2 + Attr2_HIGH OFFSET(20) NUMBITS(4) [ + Device = 0b0000, + Memory_OuterNonCacheable = 0b0100, + Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 + ], + Attr2_LOW_DEVICE OFFSET(16) NUMBITS(4) [ + Device_nGnRE = 0b0100 + ], + Attr2_LOW_MEMORY OFFSET(16) NUMBITS(4) [ + InnerNonCacheable = 0b0100, + InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 + ], + + /// Attribute 1 + Attr1_HIGH OFFSET(12) NUMBITS(4) [ + Device = 0b0000, + Memory_OuterNonCacheable = 0b0100, + Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 + ], + Attr1_LOW_DEVICE OFFSET(8) NUMBITS(4) [ + Device_nGnRE = 0b0100 + ], + Attr1_LOW_MEMORY OFFSET(8) NUMBITS(4) [ + InnerNonCacheable = 0b0100, + InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 + ], + + /// Attribute 0 + Attr0_HIGH OFFSET(4) NUMBITS(4) [ + Device = 0b0000, + Memory_OuterNonCacheable = 0b0100, + Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 + ], + Attr0_LOW_DEVICE OFFSET(0) NUMBITS(4) [ + Device_nGnRE = 0b0100 + ], + Attr0_LOW_MEMORY OFFSET(0) NUMBITS(4) [ + InnerNonCacheable = 0b0100, + InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 + ] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "MAIR_EL1"); + sys_coproc_write_raw!(u64, "MAIR_EL1"); +} + +pub static MAIR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/mod.rs b/crate/aarch64/src/regs/mod.rs new file mode 100644 index 0000000..f6a0e3d --- /dev/null +++ b/crate/aarch64/src/regs/mod.rs @@ -0,0 +1,51 @@ +//! Processor core registers + +#[macro_use] +mod macros; + +mod cntfrq_el0; +mod cnthctl_el2; +mod cntp_ctl_el0; +mod cntp_tval_el0; +mod cntpct_el0; +mod cntvoff_el2; +mod currentel; +mod daif; +mod elr_el2; +mod hcr_el2; +mod id_aa64mmfr0_el1; +mod mair_el1; +mod mpidr_el1; +mod sctlr_el1; +mod sp; +mod sp_el0; +mod sp_el1; +mod spsel; +mod spsr_el2; +mod tcr_el1; +mod ttbr0_el1; + +// Export only the R/W traits and the static reg definitions +pub use register::cpu::*; + +pub use self::cntfrq_el0::CNTFRQ_EL0; +pub use self::cnthctl_el2::CNTHCTL_EL2; +pub use self::cntp_ctl_el0::CNTP_CTL_EL0; +pub use self::cntp_tval_el0::CNTP_TVAL_EL0; +pub use self::cntpct_el0::CNTPCT_EL0; +pub use self::cntvoff_el2::CNTVOFF_EL2; +pub use self::currentel::CurrentEL; +pub use self::daif::DAIF; +pub use self::elr_el2::ELR_EL2; +pub use self::hcr_el2::HCR_EL2; +pub use self::id_aa64mmfr0_el1::ID_AA64MMFR0_EL1; +pub use self::mair_el1::MAIR_EL1; +pub use self::mpidr_el1::MPIDR_EL1; +pub use self::sctlr_el1::SCTLR_EL1; +pub use self::sp::SP; +pub use self::sp_el0::SP_EL0; +pub use self::sp_el1::SP_EL1; +pub use self::spsel::SPSel; +pub use self::spsr_el2::SPSR_EL2; +pub use self::tcr_el1::TCR_EL1; +pub use self::ttbr0_el1::TTBR0_EL1; diff --git a/crate/aarch64/src/regs/mpidr_el1.rs b/crate/aarch64/src/regs/mpidr_el1.rs new file mode 100644 index 0000000..6fbfea0 --- /dev/null +++ b/crate/aarch64/src/regs/mpidr_el1.rs @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Multiprocessor Affinity Register - EL1 +//! +//! In a multiprocessor system, provides an additional PE +//! identification mechanism for scheduling purposes. + +use register::cpu::RegisterReadOnly; + +pub struct Reg; + +impl RegisterReadOnly for Reg { + sys_coproc_read_raw!(u64, "MPIDR_EL1"); +} + +pub static MPIDR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sctlr_el1.rs b/crate/aarch64/src/regs/sctlr_el1.rs new file mode 100644 index 0000000..1f463b4 --- /dev/null +++ b/crate/aarch64/src/regs/sctlr_el1.rs @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! System Control Register - EL1 +//! +//! Provides top level control of the system, including its memory system, at +//! EL1 and EL0. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u32, + SCTLR_EL1 [ + /// Instruction access Cacheability control, for accesses at EL0 and + /// EL1: + /// + /// 0 All instruction access to Normal memory from EL0 and EL1 are + /// Non-cacheable for all levels of instruction and unified cache. + /// + /// If the value of SCTLR_EL1.M is 0, instruction accesses from stage + /// 1 of the EL1&0 translation regime are to Normal, Outer Shareable, + /// Inner Non-cacheable, Outer Non-cacheable memory. + /// + /// 1 This control has no effect on the Cacheability of instruction + /// access to Normal memory from EL0 and EL1. + /// + /// If the value of SCTLR_EL1.M is 0, instruction accesses from stage + /// 1 of the EL1&0 translation regime are to Normal, Outer Shareable, + /// Inner Write-Through, Outer Write-Through memory. + /// + /// When the value of the HCR_EL2.DC bit is 1, then instruction access + /// to Normal memory from EL0 and EL1 are Cacheable regardless of the + /// value of the SCTLR_EL1.I bit. + /// + /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} + /// is {1, 1}, this bit has no effect on the PE. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 0. + I OFFSET(12) NUMBITS(1) [ + NonCacheable = 0, + Cacheable = 1 + ], + + /// Cacheability control, for data accesses. + /// + /// 0 All data access to Normal memory from EL0 and EL1, and all Normal + /// memory accesses to the EL1&0 stage 1 translation tables, are + /// Non-cacheable for all levels of data and unified cache. + /// + /// 1 This control has no effect on the Cacheability of: + /// - Data access to Normal memory from EL0 and EL1. + /// - Normal memory accesses to the EL1&0 stage 1 translation + /// tables. + /// + /// When the value of the HCR_EL2.DC bit is 1, the PE ignores + /// SCLTR.C. This means that Non-secure EL0 and Non-secure EL1 data + /// accesses to Normal memory are Cacheable. + /// + /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} + /// is {1, 1}, this bit has no effect on the PE. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 0. + C OFFSET(2) NUMBITS(1) [ + NonCacheable = 0, + Cacheable = 1 + ], + + /// MMU enable for EL1 and EL0 stage 1 address translation. Possible + /// values of this bit are: + /// + /// 0 EL1 and EL0 stage 1 address translation disabled. + /// See the SCTLR_EL1.I field for the behavior of instruction accesses + /// to Normal memory. + /// 1 EL1 and EL0 stage 1 address translation enabled. + M OFFSET(0) NUMBITS(1) [ + Disable = 0, + Enable = 1 + ] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "SCTLR_EL1"); + sys_coproc_write_raw!(u32, "SCTLR_EL1"); +} + +pub static SCTLR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sp.rs b/crate/aarch64/src/regs/sp.rs new file mode 100644 index 0000000..f9f578b --- /dev/null +++ b/crate/aarch64/src/regs/sp.rs @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! The stack pointer + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + read_raw!(u64, "sp"); + write_raw!(u64, "sp"); +} + +pub static SP: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sp_el0.rs b/crate/aarch64/src/regs/sp_el0.rs new file mode 100644 index 0000000..aa82fdb --- /dev/null +++ b/crate/aarch64/src/regs/sp_el0.rs @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! The stack pointer - EL0 +//! +//! Holds the stack pointer associated with EL0. At higher Exception levels, +//! this is used as the current stack pointer when the value of SPSel.SP is 0. + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "SP_EL0"); + sys_coproc_write_raw!(u64, "SP_EL0"); +} + +pub static SP_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sp_el1.rs b/crate/aarch64/src/regs/sp_el1.rs new file mode 100644 index 0000000..4357412 --- /dev/null +++ b/crate/aarch64/src/regs/sp_el1.rs @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! The stack pointer - EL1 +//! +//! Holds the stack pointer associated with EL1. When executing at EL1, the +//! value of SPSel.SP determines the current stack pointer: +//! +//! SPSel.SP | current stack pointer +//! -------------------------------- +//! 0 | SP_EL0 +//! 1 | SP_EL1 + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "SP_EL1"); + sys_coproc_write_raw!(u64, "SP_EL1"); +} + +pub static SP_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/spsel.rs b/crate/aarch64/src/regs/spsel.rs new file mode 100644 index 0000000..91e3694 --- /dev/null +++ b/crate/aarch64/src/regs/spsel.rs @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Stack Pointer Select +//! +//! Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u32, + SPSel [ + /// Stack pointer to use. Possible values of this bit are: + /// + /// 0 Use SP_EL0 at all Exception levels. + /// 1 Use SP_ELx for Exception level ELx. + /// + /// When this register has an architecturally-defined reset value, this + /// field resets to 1. + SP OFFSET(0) NUMBITS(1) [ + EL0 = 0, + ELx = 1 + ] + ] +} + + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "SPSEL"); + sys_coproc_write_raw!(u32, "SPSEL"); +} + +#[allow(non_upper_case_globals)] +pub static SPSel: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/spsr_el2.rs b/crate/aarch64/src/regs/spsr_el2.rs new file mode 100644 index 0000000..56078a4 --- /dev/null +++ b/crate/aarch64/src/regs/spsr_el2.rs @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Saved Program Status Register - EL2 +//! +//! Holds the saved process state when an exception is taken to EL2. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u32, + SPSR_EL2 [ + /// Process state D mask. The possible values of this bit are: + /// + /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at + /// the current Exception level are not masked. + /// + /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at + /// the current Exception level are masked. + /// + /// When the target Exception level of the debug exception is higher + /// than the current Exception level, the exception is not masked by + /// this bit. + D OFFSET(9) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// SError interrupt mask bit. The possible values of this bit are: + /// + /// 0 Exception not masked. + /// 1 Exception masked. + A OFFSET(8) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// IRQ mask bit. The possible values of this bit are: + /// + /// 0 Exception not masked. + /// 1 Exception masked. + I OFFSET(7) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// FIQ mask bit. The possible values of this bit are: + /// + /// 0 Exception not masked. + /// 1 Exception masked. + F OFFSET(6) NUMBITS(1) [ + Unmasked = 0, + Masked = 1 + ], + + /// AArch64 state (Exception level and selected SP) that an exception + /// was taken from. The possible values are: + /// + /// M[3:0] | State + /// -------------- + /// 0b0000 | EL0t + /// 0b0100 | EL1t + /// 0b0101 | EL1h + /// 0b1000 | EL2t + /// 0b1001 | EL2h + /// + /// Other values are reserved, and returning to an Exception level that + /// is using AArch64 with a reserved value in this field is treated as + /// an illegal exception return. + /// + /// The bits in this field are interpreted as follows: + /// - M[3:2] holds the Exception Level. + /// - M[1] is unused and is RES 0 for all non-reserved values. + /// - M[0] is used to select the SP: + /// - 0 means the SP is always SP0. + /// - 1 means the exception SP is determined by the EL. + M OFFSET(0) NUMBITS(4) [ + EL0t = 0b0000, + EL1t = 0b0100, + EL1h = 0b0101, + EL2t = 0b1000, + EL2h = 0b1001 + ] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u32, "SPSR_EL2"); + sys_coproc_write_raw!(u32, "SPSR_EL2"); +} + +pub static SPSR_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/tcr_el1.rs b/crate/aarch64/src/regs/tcr_el1.rs new file mode 100644 index 0000000..bcd0425 --- /dev/null +++ b/crate/aarch64/src/regs/tcr_el1.rs @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Translation Control Register - EL1 +//! +//! The control register for stage 1 of the EL1&0 translation regime. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u64, + TCR_EL1 [ + /// Top Byte ignored - indicates whether the top byte of an address is + /// used for address match for the TTBR0_EL1 region, or ignored and used + /// for tagged addresses. Defined values are: + /// + /// 0 Top Byte used in the address calculation. + /// 1 Top Byte ignored in the address calculation. + TBI0 OFFSET(37) NUMBITS(1) [ + Used = 0, + Ignored = 1 + ], + + /// Intermediate Physical Address Size. + /// + /// 000 32 bits, 4GiB. + /// 001 36 bits, 64GiB. + /// 010 40 bits, 1TiB. + /// 011 42 bits, 4TiB. + /// 100 44 bits, 16TiB. + /// 101 48 bits, 256TiB. + /// 110 52 bits, 4PiB + /// + /// Other values are reserved. + /// + /// The reserved values behave in the same way as the 101 or 110 + /// encoding, but software must not rely on this property as the + /// behavior of the reserved values might change in a future revision of + /// the architecture. + /// + /// The value 110 is permitted only if ARMv8.2-LPA is implemented and + /// the translation granule size is 64KiB. + /// + /// In an implementation that supports 52-bit PAs, if the value of this + /// field is not 110 , then bits[51:48] of every translation table base + /// address for the stage of translation controlled by TCR_EL1 are 0000 + /// . + IPS OFFSET(32) NUMBITS(3) [ + Bits_32 = 0b000, + Bits_36 = 0b001, + Bits_40 = 0b010, + Bits_42 = 0b011, + Bits_44 = 0b100, + Bits_48 = 0b101, + Bits_52 = 0b110 + ], + + /// Granule size for the TTBR0_EL1. + /// + /// 00 4KiB + /// 01 64KiB + /// 10 16KiB + /// + /// Other values are reserved. + /// + /// If the value is programmed to either a reserved value, or a size + /// that has not been implemented, then the hardware will treat the + /// field as if it has been programmed to an IMPLEMENTATION DEFINED + /// choice of the sizes that has been implemented for all purposes other + /// than the value read back from this register. + /// + /// It is IMPLEMENTATION DEFINED whether the value read back is the + /// value programmed or the value that corresponds to the size chosen. + TG0 OFFSET(14) NUMBITS(2) [ + KiB_4 = 0b00, + KiB_16 = 0b10, + KiB_64 = 0b01 + ], + + /// Shareability attribute for memory associated with translation table + /// walks using TTBR0_EL1. + /// + /// 00 Non-shareable + /// 10 Outer Shareable + /// 11 Inner Shareable + /// + /// Other values are reserved. + SH0 OFFSET(12) NUMBITS(2) [ + None = 0b00, + Outer = 0b10, + Inner = 0b11 + ], + + /// Outer cacheability attribute for memory associated with translation + /// table walks using TTBR0_EL1. + /// + /// 00 Normal memory, Outer Non-cacheable + /// + /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate + /// Cacheable + /// + /// 10 Normal memory, Outer Write-Through Read-Allocate No + /// Write-Allocate Cacheable + /// + /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate + /// Cacheable + ORGN0 OFFSET(10) NUMBITS(2) [ + NonCacheable = 0b00, + WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, + WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, + WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 + ], + + /// Inner cacheability attribute for memory associated with translation + /// table walks using TTBR0_EL1. + /// + /// 00 Normal memory, Inner Non-cacheable + /// + /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate + /// Cacheable + /// + /// 10 Normal memory, Inner Write-Through Read-Allocate No + /// Write-Allocate Cacheable + /// + /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate + /// Cacheable + IRGN0 OFFSET(8) NUMBITS(2) [ + NonCacheable = 0b00, + WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, + WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, + WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 + ], + + /// Translation table walk disable for translations using + /// TTBR0_EL1. This bit controls whether a translation table walk is + /// performed on a TLB miss, for an address that is translated using + /// TTBR0_EL1. The encoding of this bit is: + /// + /// 0 Perform translation table walks using TTBR0_EL1. + /// + /// 1 A TLB miss on an address that is translated using TTBR0_EL1 + /// generates a Translation fault. No translation table walk is + /// performed. + EPD0 OFFSET(7) NUMBITS(1) [ + EnableTTBR0Walks = 0, + DisableTTBR0Walks = 1 + ], + + /// The size offset of the memory region addressed by TTBR0_EL1. The + /// region size is 2^(64-T0SZ) bytes. + /// + /// The maximum and minimum possible values for T0SZ depend on the level + /// of translation table and the memory translation granule size, as + /// described in the AArch64 Virtual Memory System Architecture chapter. + T0SZ OFFSET(0) NUMBITS(6) [] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "TCR_EL1"); + sys_coproc_write_raw!(u64, "TCR_EL1"); +} + +pub static TCR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/ttbr0_el1.rs b/crate/aarch64/src/regs/ttbr0_el1.rs new file mode 100644 index 0000000..c111256 --- /dev/null +++ b/crate/aarch64/src/regs/ttbr0_el1.rs @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Translation Table Base Register 0 - EL1 +//! +//! Holds the base address of the translation table for the initial lookup for +//! stage 1 of the translation of an address from the lower VA range in the +//! EL1&0 translation regime, and other information for this translation regime. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u64, + TTBR0_EL1 [ + /// An ASID for the translation table base address. The TCR_EL1.A1 field + /// selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID. + /// + /// If the implementation has only 8 bits of ASID, then the upper 8 bits + /// of this field are RES 0. + ASID OFFSET(48) NUMBITS(16) [], + + /// Translation table base address + BADDR OFFSET(1) NUMBITS(47) [], + + /// Common not Private + CnP OFFSET(0) NUMBITS(1) [] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "TTBR0_EL1"); + sys_coproc_write_raw!(u64, "TTBR0_EL1"); +} + +impl Reg { + #[inline] + pub fn set_baddr(&self, addr: u64) { + self.write(TTBR0_EL1::BADDR.val(addr >> 1)); + } +} + +pub static TTBR0_EL1: Reg = Reg {}; diff --git a/kernel/Cargo.lock b/kernel/Cargo.lock index e1b7d05..05f0710 100644 --- a/kernel/Cargo.lock +++ b/kernel/Cargo.lock @@ -1,3 +1,16 @@ +[[package]] +name = "aarch64" +version = "0.1.0" +dependencies = [ + "bare-metal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)", + "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", + "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)", + "os_bootinfo 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)", + "register 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)", + "usize_conversions 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", + "ux 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "atags" version = "0.1.0" @@ -243,6 +256,7 @@ dependencies = [ name = "ucore" version = "0.1.0" dependencies = [ + "aarch64 0.1.0", "atags 0.1.0", "bbl 0.1.0", "bcm2837 0.1.0", diff --git a/kernel/Cargo.toml b/kernel/Cargo.toml index e2bba97..c80b6ef 100644 --- a/kernel/Cargo.toml +++ b/kernel/Cargo.toml @@ -45,6 +45,7 @@ bbl = { path = "../crate/bbl" } [target.'cfg(target_arch = "aarch64")'.dependencies] cortex-a = "2.2.1" +aarch64 = { path = "../crate/aarch64" } atags = { path = "../crate/atags" } bcm2837 = { path = "../crate/bcm2837", features = ["use_generic_timer"] } diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index bf55354..32990d2 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -1,22 +1,78 @@ //! Memory initialization for aarch64. +use bit_allocator::BitAlloc; use ucore_memory::PAGE_SIZE; +use memory::{FRAME_ALLOCATOR, init_heap}; use super::atags::atags::Atags; -use super::super::HEAP_ALLOCATOR; +//use super::super::HEAP_ALLOCATOR; +use aarch64::{barrier, regs::*}; +use core::ops::Range; /// Memory initialization. pub fn init() { - let (start, end) = memory_map().expect("failed to find memory map"); + /*let (start, end) = memory_map().expect("failed to find memory map"); unsafe { HEAP_ALLOCATOR.lock().init(start, end - start); - } - info!("memory: init end"); + }*/ + + init_frame_allocator(); + init_heap(); + init_mmu(); } extern "C" { static _end: u8; } + +fn init_frame_allocator() { + let mut ba = FRAME_ALLOCATOR.lock(); + let (start, end) = memory_map().expect("failed to find memory map"); + ba.insert(to_range(start, end)); + info!("FrameAllocator init end"); + + fn to_range(start: usize, end: usize) -> Range { + let page_start = start / PAGE_SIZE; + let page_end = (end - 1) / PAGE_SIZE + 1; + page_start..page_end + } +} + +fn init_mmu() { + // device. + MAIR_EL1.write( + // Attribute 1 + MAIR_EL1::Attr1_HIGH::Device + + MAIR_EL1::Attr1_LOW_DEVICE::Device_nGnRE + // Attribute 0 + + MAIR_EL1::Attr0_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc + + MAIR_EL1::Attr0_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc, + ); + // Configure various settings of stage 1 of the EL1 translation regime. + let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange); + TCR_EL1.write( + TCR_EL1::TBI0::Ignored + + TCR_EL1::IPS.val(ips) + + TCR_EL1::TG0::KiB_4 // 4 KiB granule + + TCR_EL1::SH0::Inner + + TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable + + TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable + + TCR_EL1::EPD0::EnableTTBR0Walks + + TCR_EL1::T0SZ.val(34), // Start walks at level 2 + ); + + // Switch the MMU on. + // + // First, force all previous changes to be seen before the MMU is enabled. + unsafe { barrier::isb(barrier::SY); } + + // Enable the MMU and turn on data and instruction caching. + SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable); + + // Force MMU init to complete before next instruction + unsafe { barrier::isb(barrier::SY); } +} + /// Returns the (start address, end address) of the available memory on this /// system if it can be determined. If it cannot, `None` is returned. /// @@ -33,3 +89,4 @@ pub fn memory_map() -> Option<(usize, usize)> { None } + diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index e9cc43e..b468f8b 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -1,218 +1,233 @@ //! Page table implementations for aarch64. - +use bit_allocator::{BitAlloc}; +// Depends on kernel +use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame}; use ucore_memory::memory_set::*; +use ucore_memory::PAGE_SIZE; use ucore_memory::paging::*; - -type VirtAddr = usize; -type PhysAddr = usize; - -use alloc::alloc::{alloc, Layout}; -use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame}; - -/// TODO -pub struct ActivePageTable { - // TODO +use aarch64::asm::{tlb_invalidate, ttbr0_el1_read, ttbr0_el1_write}; +use aarch64::{PhysAddr, VirtAddr}; +use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; +use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB}; +use aarch64::{regs::*}; + +pub trait PageExt { + fn of_addr(address: usize) -> Self; + fn range_of(begin: usize, end: usize) -> PageRange; } -impl ActivePageTable { - /// TODO - pub unsafe fn new() -> Self { - unimplemented!() - } -} - -impl PageTable for ActivePageTable { - type Entry = PageEntry; - - fn map(&mut self, addr: VirtAddr, target: PhysAddr) -> &mut Self::Entry { - unimplemented!() - } - fn unmap(&mut self, addr: VirtAddr) { - unimplemented!() - } - - fn get_entry(&mut self, addr: VirtAddr) -> &mut Self::Entry { - unimplemented!() - } - - // For testing with mock - fn get_page_slice_mut<'a, 'b>(&'a mut self, addr: VirtAddr) -> &'b mut [u8] { - unimplemented!() +impl PageExt for Page { + fn of_addr(address: usize) -> Self { + Page::containing_address(VirtAddr::new(address as u64)) } - - fn read(&mut self, addr: VirtAddr) -> u8 { - unimplemented!() - } - - fn write(&mut self, addr: VirtAddr, data: u8) { - unimplemented!() + fn range_of(begin: usize, end: usize) -> PageRange { + Page::range(Page::of_addr(begin), Page::of_addr(end - 1) + 1) } } -/// TODO -pub struct PageEntry { - // TODO +pub trait FrameExt { + fn of_addr(address: usize) -> Self; } -impl Entry for PageEntry { - /// IMPORTANT! - /// This must be called after any change to ensure it become effective. - /// Usually this will make a flush to TLB/MMU. - fn update(&mut self) { - unimplemented!() - } - - /// Will be set when accessed - fn accessed(&self) -> bool { - unimplemented!() +impl FrameExt for Frame { + fn of_addr(address: usize) -> Self { + Frame::containing_address(PhysAddr::new(address as u64)) } +} - /// Will be set when written - fn dirty(&self) -> bool { - unimplemented!() - } +pub struct ActivePageTable(RecursivePageTable<'static>); - /// Will PageFault when try to write page where writable=0 - fn writable(&self) -> bool { - unimplemented!() - } +pub struct PageEntry(PageTableEntry); - /// Will PageFault when try to access page where present=0 - fn present(&self) -> bool { - unimplemented!() - } - - fn clear_accessed(&mut self) { - unimplemented!() - } +impl PageTable for ActivePageTable { + type Entry = PageEntry; - fn clear_dirty(&mut self) { - unimplemented!() + fn map(&mut self, addr: usize, target: usize) -> &mut PageEntry { + let flags = EF::PRESENT | EF::WRITE | EF::UXN; + self.0.map_to(Page::of_addr(addr), Frame::of_addr(target), flags, &mut FrameAllocatorForAarch64) + .unwrap().flush(); + self.get_entry(addr) } - fn set_writable(&mut self, value: bool) { - unimplemented!() + fn unmap(&mut self, addr: usize) { + let (frame, flush) = self.0.unmap(Page::of_addr(addr)).unwrap(); + flush.flush(); } - fn set_present(&mut self, value: bool) { - unimplemented!() + fn get_entry(&mut self, addr: usize) -> &mut PageEntry { + let entry_addr = ((addr >> 9) & 0o777_777_777_7770) | 0xffffff80_00000000; + unsafe { &mut *(entry_addr as *mut PageEntry) } } - fn target(&self) -> PhysAddr { - unimplemented!() + fn get_page_slice_mut<'a, 'b>(&'a mut self, addr: usize) -> &'b mut [u8] { + use core::slice; + unsafe { slice::from_raw_parts_mut((addr & !0xfffusize) as *mut u8, PAGE_SIZE) } } - fn set_target(&mut self, target: PhysAddr) { - unimplemented!() + fn read(&mut self, addr: usize) -> u8 { + unsafe { *(addr as *const u8) } } - // For Copy-on-write extension - fn writable_shared(&self) -> bool { - unimplemented!() + fn write(&mut self, addr: usize, data: u8) { + unsafe { *(addr as *mut u8) = data; } } +} - fn readonly_shared(&self) -> bool { - unimplemented!() +impl ActivePageTable { + pub unsafe fn new() -> Self { + ActivePageTable(RecursivePageTable::new(&mut *(0xffffffff_fffff000 as *mut _)).unwrap()) + } + fn with_temporary_map(&mut self, frame: &Frame, f: impl FnOnce(&mut ActivePageTable, &mut Aarch64PageTable)) { + // Create a temporary page + let page = Page::of_addr(0xcafebabe); + assert!(self.0.translate_page(page).is_none(), "temporary page is already mapped"); + // Map it to table + self.map(page.start_address().as_u64() as usize, frame.start_address().as_u64() as usize); + // Call f + let table = unsafe { &mut *page.start_address().as_mut_ptr() }; + f(self, table); + // Unmap the page + self.unmap(0xcafebabe); } +} - fn set_shared(&mut self, writable: bool) { - unimplemented!() +impl Entry for PageEntry { + fn update(&mut self) { + tlb_invalidate(); } - fn clear_shared(&mut self) { - unimplemented!() - } + fn present(&self) -> bool { self.0.flags().contains(EF::PRESENT) } + fn accessed(&self) -> bool { self.0.flags().contains(EF::ACCESSED) } + fn writable(&self) -> bool { self.0.flags().contains(EF::WRITE) } + fn dirty(&self) -> bool { self.hw_dirty() && self.sw_dirty() } - // For Swap extension - fn swapped(&self) -> bool { - unimplemented!() + fn clear_accessed(&mut self) { self.as_flags().remove(EF::ACCESSED); } + fn clear_dirty(&mut self) + { + self.as_flags().remove(EF::DIRTY); + self.as_flags().insert(EF::RDONLY); } - - fn set_swapped(&mut self, value: bool) { - unimplemented!() + fn set_writable(&mut self, value: bool) + { + self.as_flags().set(EF::RDONLY, !value); + self.as_flags().set(EF::WRITE, value); } - - fn user(&self) -> bool { - unimplemented!() + fn set_present(&mut self, value: bool) { self.as_flags().set(EF::PRESENT, value); } + fn target(&self) -> usize { self.0.addr().as_u64() as usize } + fn set_target(&mut self, target: usize) { + let flags = self.0.flags(); + self.0.set_addr(PhysAddr::new(target as u64), flags); } - + fn writable_shared(&self) -> bool { self.0.flags().contains(EF::BIT_9) } + fn readonly_shared(&self) -> bool { self.0.flags().contains(EF::BIT_9) } + fn set_shared(&mut self, writable: bool) { + let flags = self.as_flags(); + flags.set(EF::BIT_8, writable); + flags.set(EF::BIT_9, writable); + } + fn clear_shared(&mut self) { self.as_flags().remove(EF::BIT_8 | EF::BIT_9); } + fn user(&self) -> bool { self.0.flags().contains(EF::USER_ACCESSIBLE) } + fn swapped(&self) -> bool { self.0.flags().contains(EF::SWAPPED) } + fn set_swapped(&mut self, value: bool) { self.as_flags().set(EF::SWAPPED, value); } fn set_user(&mut self, value: bool) { - unimplemented!() - } - - fn execute(&self) -> bool { - unimplemented!() - } - - fn set_execute(&mut self, value: bool) { - unimplemented!() + self.as_flags().set(EF::USER_ACCESSIBLE, value); + if value { + let mut addr = self as *const _ as usize; + for _ in 0..3 { + // Upper level entry + addr = ((addr >> 9) & 0o777_777_777_7770) | 0xffffff80_00000000; + // set USER_ACCESSIBLE + unsafe { (*(addr as *mut EF)).insert(EF::USER_ACCESSIBLE) }; + } + } } + fn execute(&self) -> bool { !self.0.flags().contains(EF::UXN) } + fn set_execute(&mut self, value: bool) { self.as_flags().set(EF::UXN, !value); } } -#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord)] -pub struct MockFrame(PhysAddr); - -impl MockFrame { - pub fn of_addr(addr: PhysAddr) -> Self { - MockFrame(addr) - } - pub fn start_address(&self) -> PhysAddr { - unimplemented!() - } - pub fn p2_index(&self) -> usize { - unimplemented!() - } - pub fn p1_index(&self) -> usize { - unimplemented!() - } - pub fn number(&self) -> usize { - unimplemented!() +impl PageEntry { + fn read_only(&self) -> bool { self.0.flags().contains(EF::RDONLY) } + fn hw_dirty(&self) -> bool { self.writable() && !self.read_only() } + fn sw_dirty(&self) -> bool { self.0.flags().contains(EF::DIRTY) } + fn as_flags(&mut self) -> &mut EF { + unsafe { &mut *(self as *mut _ as *mut EF) } } } -/// TODO +#[derive(Debug)] pub struct InactivePageTable0 { - p4_frame: MockFrame, + p4_frame: Frame, } -/// TODO impl InactivePageTable for InactivePageTable0 { type Active = ActivePageTable; fn new() -> Self { - unsafe { - let layout = Layout::new::(); - let ptr = alloc(layout); - let frame = MockFrame::of_addr(*ptr as usize); - InactivePageTable0 { p4_frame: frame } - } + let mut pt = Self::new_bare(); + pt.map_kernel(); + pt } fn new_bare() -> Self { - unimplemented!() + let frame = Self::alloc_frame().map(|target| Frame::of_addr(target)) + .expect("failed to allocate frame"); + active_table().with_temporary_map(&frame, |_, table: &mut Aarch64PageTable| { + table.zero(); + // set up recursive mapping for the table + table[511].set_frame(frame.clone(), EF::PRESENT | EF::WRITE); + }); + InactivePageTable0 { p4_frame: frame } } fn edit(&mut self, f: impl FnOnce(&mut Self::Active)) { - unimplemented!() + active_table().with_temporary_map(&ttbr0_el1_read().0, |active_table, p4_table: &mut Aarch64PageTable| { + let backup = p4_table[0o777].clone(); + + // overwrite recursive mapping + p4_table[0o777].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE); + tlb_invalidate(); + + // execute f in the new context + f(active_table); + + // restore recursive mapping to original p4 table + p4_table[0o777] = backup; + tlb_invalidate(); + }); } unsafe fn activate(&self) { - unimplemented!() + let old_frame = ttbr0_el1_read().0; + let new_frame = self.p4_frame.clone(); + debug!("switch table {:?} -> {:?}", old_frame, new_frame); + if old_frame != new_frame { + ttbr0_el1_write(new_frame); + } } unsafe fn with(&self, f: impl FnOnce()) { - unimplemented!() + let old_frame = ttbr0_el1_read().0; + let new_frame = self.p4_frame.clone(); + debug!("switch table {:?} -> {:?}", old_frame, new_frame); + if old_frame != new_frame { + ttbr0_el1_write(new_frame); + } + f(); + debug!("switch table {:?} -> {:?}", new_frame, old_frame); + if old_frame != new_frame { + ttbr0_el1_write(old_frame); + } } fn token(&self) -> usize { - 0 + self.p4_frame.start_address().as_u64() as usize // as CR3 } - fn alloc_frame() -> Option { + fn alloc_frame() -> Option { alloc_frame() } - fn dealloc_frame(target: PhysAddr) { + fn dealloc_frame(target: usize) { dealloc_frame(target) } @@ -220,3 +235,37 @@ impl InactivePageTable for InactivePageTable0 { alloc_stack() } } + +impl InactivePageTable0 { + fn map_kernel(&mut self) { + let mut table = unsafe { &mut *(0xffffffff_fffff000 as *mut Aarch64PageTable) }; + // Kernel at 0xffff_ff00_0000_0000 + // Kernel stack at 0x0000_57ac_0000_0000 (defined in bootloader crate) + let e0 = table[0].clone(); + self.edit(|_| { + table[0].set_addr(e0.addr(), e0.flags() & EF::GLOBAL); + //table[175].set_addr(estack.addr(), estack.flags() & EF::GLOBAL); + }); + } +} + +impl Drop for InactivePageTable0 { + fn drop(&mut self) { + info!("PageTable dropping: {:?}", self); + Self::dealloc_frame(self.p4_frame.start_address().as_u64() as usize); + } +} + +struct FrameAllocatorForAarch64; + +impl FrameAllocator for FrameAllocatorForAarch64 { + fn alloc(&mut self) -> Option { + alloc_frame().map(|addr| Frame::of_addr(addr)) + } +} + +impl FrameDeallocator for FrameAllocatorForAarch64 { + fn dealloc(&mut self, frame: Frame) { + dealloc_frame(frame.start_address().as_u64() as usize); + } +} \ No newline at end of file diff --git a/kernel/src/lib.rs b/kernel/src/lib.rs index 4474c9c..063b1d0 100644 --- a/kernel/src/lib.rs +++ b/kernel/src/lib.rs @@ -33,6 +33,8 @@ extern crate volatile; #[cfg(target_arch = "x86_64")] extern crate x86_64; extern crate xmas_elf; +#[cfg(target_arch = "aarch64")] +extern crate aarch64; use linked_list_allocator::LockedHeap; From 576ae1d9111050ae57f66bef39a74f272ed3dfc5 Mon Sep 17 00:00:00 2001 From: equation314 Date: Thu, 15 Nov 2018 19:12:02 +0800 Subject: [PATCH 02/16] add setup_page_table --- crate/aarch64/src/paging/page_table.rs | 16 ++++++--- kernel/src/arch/aarch64/memory.rs | 46 ++++++++++++++++++++++---- kernel/src/arch/aarch64/paging.rs | 32 ++++++++++++++++-- 3 files changed, 80 insertions(+), 14 deletions(-) diff --git a/crate/aarch64/src/paging/page_table.rs b/crate/aarch64/src/paging/page_table.rs index b074768..1525b17 100644 --- a/crate/aarch64/src/paging/page_table.rs +++ b/crate/aarch64/src/paging/page_table.rs @@ -104,11 +104,10 @@ bitflags! { const SHARED = 3 << 8; /* SH[1:0], inner shareable */ const BIT_8 = 1 << 8; const BIT_9 = 1 << 9; - /* - pub const ATTRIB_SH_NON_SHAREABLE: usize = 0x0 << 8; - pub const ATTRIB_SH_OUTER_SHAREABLE: usize = 0x2 << 8; - pub const ATTRIB_SH_INNER_SHAREABLE: usize = 0x3 << 8; - */ + + // pub const ATTRIB_SH_NON_SHAREABLE: usize = 0x0 << 8; + const OUTER_SHAREABLE = 0b10 << 8; + const INNER_SHAREABLE = 0b11 << 8; const ACCESSED = 1 << 10; /* AF, Access Flag */ const NONE_GLOBAL = 1 << 11; /* None Global */ @@ -148,6 +147,13 @@ impl PageTable { entry.set_unused(); } } + + /// Setup identity map: VirtPage at pagenumber -> PhysFrame at pagenumber + /// pn: pagenumber = addr>>12 in riscv32. + pub fn map_identity(&mut self, p4num: usize, flags: PageTableFlags) { + let entry = self.entries[p4num].clone(); + self.entries[p4num].set_addr(entry.addr(), flags); + } } impl Index for PageTable { diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index 32990d2..126cf57 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -5,7 +5,8 @@ use ucore_memory::PAGE_SIZE; use memory::{FRAME_ALLOCATOR, init_heap}; use super::atags::atags::Atags; //use super::super::HEAP_ALLOCATOR; -use aarch64::{barrier, regs::*}; +use aarch64::{barrier, regs::*, addr::*}; +use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB}; use core::ops::Range; /// Memory initialization. @@ -15,9 +16,27 @@ pub fn init() { HEAP_ALLOCATOR.lock().init(start, end - start); }*/ + + + #[repr(align(4096))] + struct PageData([u8; PAGE_SIZE]); + static PAGE_TABLE_ROOT: PageData = PageData([0; PAGE_SIZE]); + + let frame = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_ROOT as *const _ as u64)); + super::paging::setup_page_table(frame); + + init_mmu(); + init_frame_allocator(); init_heap(); - init_mmu(); + + let (start, end) = memory_map().expect("failed to find memory map"); + let mut v = vec![]; + for i in 0..(20 + (start & 0xf)) { + v.push(i); + println!("{:x?} {:x?}", &v[i] as * const _ as usize, v); + } + } extern "C" { @@ -26,19 +45,30 @@ extern "C" { fn init_frame_allocator() { - let mut ba = FRAME_ALLOCATOR.lock(); + use consts::{MEMORY_OFFSET}; let (start, end) = memory_map().expect("failed to find memory map"); + info!("{:x?} {:x?}", start, end); + + let mut ba = FRAME_ALLOCATOR.lock(); + use core::mem::size_of; + use ::memory::FrameAlloc; + info!("{:x?} {:x?}", &FRAME_ALLOCATOR as *const _ as usize, size_of::()); + use consts::{KERNEL_HEAP_OFFSET, KERNEL_HEAP_SIZE}; + info!("{:x?} {:x?}", KERNEL_HEAP_OFFSET + KERNEL_HEAP_SIZE, end); ba.insert(to_range(start, end)); info!("FrameAllocator init end"); fn to_range(start: usize, end: usize) -> Range { - let page_start = start / PAGE_SIZE; - let page_end = (end - 1) / PAGE_SIZE + 1; + let page_start = (start - MEMORY_OFFSET) / PAGE_SIZE; + let page_end = (end - MEMORY_OFFSET - 1) / PAGE_SIZE + 1; + // info!("{:x?} {:x?}", page_start, page_end); page_start..page_end } } fn init_mmu() { + info!("init_mmu"); + // device. MAIR_EL1.write( // Attribute 1 @@ -50,6 +80,7 @@ fn init_mmu() { ); // Configure various settings of stage 1 of the EL1 translation regime. let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange); + info!("{:x?}", ips); TCR_EL1.write( TCR_EL1::TBI0::Ignored + TCR_EL1::IPS.val(ips) @@ -58,7 +89,7 @@ fn init_mmu() { + TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable + TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable + TCR_EL1::EPD0::EnableTTBR0Walks - + TCR_EL1::T0SZ.val(34), // Start walks at level 2 + + TCR_EL1::T0SZ.val(16), // Start walks at level 2 ); // Switch the MMU on. @@ -66,11 +97,14 @@ fn init_mmu() { // First, force all previous changes to be seen before the MMU is enabled. unsafe { barrier::isb(barrier::SY); } + info!("{:x?}", TCR_EL1.get()); // Enable the MMU and turn on data and instruction caching. SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable); // Force MMU init to complete before next instruction unsafe { barrier::isb(barrier::SY); } + + info!("mmu enabled!"); } /// Returns the (start address, end address) of the available memory on this diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index b468f8b..603346d 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -11,6 +11,32 @@ use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, Pag use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB}; use aarch64::{regs::*}; +// need 1 page +pub fn setup_page_table(frame: Frame) { + let p4 = unsafe { &mut *(frame.start_address().as_u64() as *mut Aarch64PageTable) }; + p4.zero(); + + + // p4.set_recursive(RECURSIVE_PAGE_PML4, frame.clone()); + + // Set kernel identity map + // 0x10000000 ~ 1K area + p4.map_identity(0o777, EF::PRESENT | EF::PXN | EF::UXN); + + // 0x80000000 ~ 8K area + p4.map_identity(0, EF::PRESENT); + // p2.map_identity(KERNEL_PML4, EF::PRESENT | EF::READABLE | EF::WRITABLE); + // p2.map_identity(KERNEL_PML4 + 1, EF::VALID | EF::READABLE | EF::WRITABLE | EF::EXECUTABLE); + + // use super::riscv::register::satp; + // unsafe { satp::set(satp::Mode::Sv32, 0, frame); } + // sfence_vma_all(); + + ttbr0_el1_write(frame); + tlb_invalidate(); + info!("setup init page table end"); +} + pub trait PageExt { fn of_addr(address: usize) -> Self; fn range_of(begin: usize, end: usize) -> PageRange; @@ -75,7 +101,7 @@ impl PageTable for ActivePageTable { impl ActivePageTable { pub unsafe fn new() -> Self { - ActivePageTable(RecursivePageTable::new(&mut *(0xffffffff_fffff000 as *mut _)).unwrap()) + ActivePageTable(RecursivePageTable::new(&mut *(0xffff_ffff_ffff_f000 as *mut _)).unwrap()) } fn with_temporary_map(&mut self, frame: &Frame, f: impl FnOnce(&mut ActivePageTable, &mut Aarch64PageTable)) { // Create a temporary page @@ -238,7 +264,7 @@ impl InactivePageTable for InactivePageTable0 { impl InactivePageTable0 { fn map_kernel(&mut self) { - let mut table = unsafe { &mut *(0xffffffff_fffff000 as *mut Aarch64PageTable) }; + let mut table = unsafe { &mut *(0xffff_ffff_ffff_f000 as *mut Aarch64PageTable) }; // Kernel at 0xffff_ff00_0000_0000 // Kernel stack at 0x0000_57ac_0000_0000 (defined in bootloader crate) let e0 = table[0].clone(); @@ -268,4 +294,4 @@ impl FrameDeallocator for FrameAllocatorForAarch64 { fn dealloc(&mut self, frame: Frame) { dealloc_frame(frame.start_address().as_u64() as usize); } -} \ No newline at end of file +} From 9e8124abbbf4dace6e2eef451db74793c536fdc2 Mon Sep 17 00:00:00 2001 From: equation314 Date: Tue, 20 Nov 2018 16:46:16 +0800 Subject: [PATCH 03/16] aarch64/mmu: mmu enabled --- crate/aarch64/Cargo.lock | 68 ------ crate/aarch64/src/asm.rs | 27 ++- crate/aarch64/src/paging/mod.rs | 57 ----- crate/aarch64/src/paging/page_table.rs | 9 +- crate/aarch64/src/paging/recursive.rs | 212 +------------------ kernel/Cargo.lock | 17 ++ kernel/Cargo.toml | 1 + kernel/src/arch/aarch64/boot/boot.S | 2 + kernel/src/arch/aarch64/interrupt/handler.rs | 5 +- kernel/src/arch/aarch64/memory.rs | 55 ++--- kernel/src/arch/aarch64/paging.rs | 163 +++++++++++--- kernel/src/consts.rs | 17 +- kernel/src/lib.rs | 4 + kernel/src/memory.rs | 6 +- 14 files changed, 215 insertions(+), 428 deletions(-) delete mode 100644 crate/aarch64/Cargo.lock diff --git a/crate/aarch64/Cargo.lock b/crate/aarch64/Cargo.lock deleted file mode 100644 index 2d0a329..0000000 --- a/crate/aarch64/Cargo.lock +++ /dev/null @@ -1,68 +0,0 @@ -[[package]] -name = "aarch64" -version = "0.1.0" -dependencies = [ - "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", - "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)", - "cortex-a 2.2.2 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-source = "registry+https://github.com/rust-lang/crates.io-index" -dependencies = [ - "tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - -[[package]] -name = "tock-registers" -version = "0.2.0" -source = "registry+https://github.com/rust-lang/crates.io-index" - -[[package]] -name = "usize_conversions" -version = "0.2.0" -source = "registry+https://github.com/rust-lang/crates.io-index" - -[[package]] -name = "ux" -version = "0.1.2" -source = "registry+https://github.com/rust-lang/crates.io-index" - -[metadata] -"checksum bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "ed8765909f9009617974ab6b7d332625b320b33c326b1e9321382ef1999b5d56" -"checksum bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)" = "228047a76f468627ca71776ecdebd732a3423081fcf5125585bcd7c49886ce12" -"checksum cortex-a 2.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "2b187d0d728b4a99ba1d79f9671b976bcdd71a8a2c719585218fd2dc14a4d08c" -"checksum os_bootinfo 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "66481dbeb5e773e7bd85b63cd6042c30786f834338288c5ec4f3742673db360a" -"checksum register 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "e10f31b6d2299e5620986ad9fcdd66463e125ad72af4f403f9aedf7592d5ccdb" -"checksum tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3a385d94f3f62e60445a0adb9ff8d9621faa272234530d4c0f848ec98f88e316" -"checksum usize_conversions 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "f70329e2cbe45d6c97a5112daad40c34cd9a4e18edb5a2a18fefeb584d8d25e5" -"checksum ux 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)" = "53d8df5dd8d07fedccd202de1887d94481fadaea3db70479f459e8163a1fab41" diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs index d97fa78..17e6c29 100644 --- a/crate/aarch64/src/asm.rs +++ b/crate/aarch64/src/asm.rs @@ -4,12 +4,13 @@ use regs::*; #[inline(always)] pub fn tlb_invalidate() { - unsafe{ - asm!("dsb ishst - tlbi vmalle1is - dsb ish - tlbi vmalle1is - isb"); + unsafe { + asm!( + "dsb ishst + tlbi vmalle1is + dsb ish + isb" + ); } } @@ -63,6 +64,15 @@ pub unsafe fn get_ttbr1() -> usize { ttbr0 } +#[inline(always)] +pub fn address_translate(vaddr: usize) -> usize { + let paddr: usize; + unsafe { + asm!("at S1E1R, $1; mrs $0, par_el1" : "=r"(paddr) : "r"(vaddr)); + } + paddr +} + /// Returns the SPSel value. #[inline(always)] pub fn sp_sel() -> u8 { @@ -94,7 +104,6 @@ pub fn wfi() { } } - /// The classic no-op #[inline] pub fn nop() { @@ -142,7 +151,7 @@ pub fn eret() -> ! { bitflags! { /// Controls cache settings for the level 4 page table. pub struct ttbr0_el1_Flags: u64 { - + const COMMON_NOT_PRIVATE = 1 << 0; } } @@ -150,7 +159,7 @@ bitflags! { pub fn ttbr0_el1_read() -> (PhysFrame, ttbr0_el1_Flags) { let value = TTBR0_EL1.get(); let flags = ttbr0_el1_Flags::from_bits_truncate(value); - let addr = PhysAddr::new(value & 0x_000f_ffff_ffff_f000); + let addr = PhysAddr::new(value & 0x_0000_ffff_ffff_f000); let frame = PhysFrame::containing_address(addr); (frame, flags) } diff --git a/crate/aarch64/src/paging/mod.rs b/crate/aarch64/src/paging/mod.rs index 56073b2..ebc00dc 100644 --- a/crate/aarch64/src/paging/mod.rs +++ b/crate/aarch64/src/paging/mod.rs @@ -34,16 +34,6 @@ pub trait NotGiantPageSize: PageSize {} #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] pub enum Size4KiB {} -/// A “huge” 2MiB page. -#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -pub enum Size2MiB {} - -/// A “giant” 1GiB page. -/// -/// (Only available on newer x86_64 CPUs.) -#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -pub enum Size1GiB {} - impl PageSize for Size4KiB { const SIZE: u64 = 4096; const SIZE_AS_DEBUG_STR: &'static str = "4KiB"; @@ -51,18 +41,6 @@ impl PageSize for Size4KiB { impl NotGiantPageSize for Size4KiB {} -impl PageSize for Size2MiB { - const SIZE: u64 = Size4KiB::SIZE * 512; - const SIZE_AS_DEBUG_STR: &'static str = "2MiB"; -} - -impl NotGiantPageSize for Size2MiB {} - -impl PageSize for Size1GiB { - const SIZE: u64 = Size2MiB::SIZE * 512; - const SIZE_AS_DEBUG_STR: &'static str = "1GiB"; -} - /// A virtual memory page. #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] #[repr(C)] @@ -128,31 +106,6 @@ impl Page { } } -impl Page { - /// Returns the 1GiB memory page with the specified page table indices. - pub fn from_page_table_indices_1gib(p4_index: u9, p3_index: u9) -> Self { - use bit_field::BitField; - - let mut addr = 0; - addr.set_bits(39..48, u64::from(p4_index)); - addr.set_bits(30..39, u64::from(p3_index)); - Page::containing_address(VirtAddr::new(addr)) - } -} - -impl Page { - /// Returns the 2MiB memory page with the specified page table indices. - pub fn from_page_table_indices_2mib(p4_index: u9, p3_index: u9, p2_index: u9) -> Self { - use bit_field::BitField; - - let mut addr = 0; - addr.set_bits(39..48, u64::from(p4_index)); - addr.set_bits(30..39, u64::from(p3_index)); - addr.set_bits(21..30, u64::from(p2_index)); - Page::containing_address(VirtAddr::new(addr)) - } -} - impl Page { /// Returns the 4KiB memory page with the specified page table indices. pub fn from_page_table_indices(p4_index: u9, p3_index: u9, p2_index: u9, p1_index: u9) -> Self { @@ -246,16 +199,6 @@ impl Iterator for PageRange { } } -impl PageRange { - /// Converts the range of 2MiB pages to a range of 4KiB pages. - pub fn as_4kib_page_range(self) -> PageRange { - PageRange { - start: Page::containing_address(self.start.start_address()), - end: Page::containing_address(self.end.start_address()), - } - } -} - impl fmt::Debug for PageRange { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.debug_struct("PageRange") diff --git a/crate/aarch64/src/paging/page_table.rs b/crate/aarch64/src/paging/page_table.rs index 1525b17..c06123e 100644 --- a/crate/aarch64/src/paging/page_table.rs +++ b/crate/aarch64/src/paging/page_table.rs @@ -21,7 +21,7 @@ pub enum FrameError { #[derive(Clone)] #[repr(transparent)] pub struct PageTableEntry { - entry: u64, + pub entry: u64, } impl PageTableEntry { @@ -42,7 +42,7 @@ impl PageTableEntry { /// Returns the physical address mapped by this entry, might be zero. pub fn addr(&self) -> PhysAddr { - PhysAddr::new(self.entry & 0x000fffff_fffff000) + PhysAddr::new(self.entry & 0x0000_ffff_ffff_f000) } /// Returns the physical frame mapped by this entry. @@ -83,6 +83,7 @@ impl PageTableEntry { impl fmt::Debug for PageTableEntry { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { let mut f = f.debug_struct("PageTableEntry"); + f.field("value", &self.entry); f.field("addr", &self.addr()); f.field("flags", &self.flags()); f.finish() @@ -94,9 +95,11 @@ bitflags! { pub struct PageTableFlags: u64 { const ALL = 0xffffffff_ffffffff; const TYPE_MASK = 3 << 0; - const TYPE_FAULT = 0 << 0; + // const TYPE_FAULT = 0 << 0; const TYPE_PAGE = 3 << 0; const TABLE_BIT = 1 << 1; + // const BLOCK_BIT = 0 << 1; + const PAGE_BIT = 1 << 1; const PRESENT = 1 << 0; const USER_ACCESSIBLE = 1 << 6; /* AP[1] */ diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index 0cbc6d0..d735216 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -4,7 +4,7 @@ use asm::tlb_invalidate; use paging::{ frame_alloc::FrameAllocator, page_table::{FrameError, PageTable, PageTableEntry, PageTableFlags}, - NotGiantPageSize, Page, PageSize, PhysFrame, Size1GiB, Size2MiB, Size4KiB, + NotGiantPageSize, Page, PageSize, PhysFrame, Size4KiB, }; use paging::page_table::PageTableFlags as Flags; use asm::ttbr0_el1_read; @@ -217,7 +217,7 @@ impl<'a> RecursivePageTable<'a> { if entry.is_unused() { if let Some(frame) = allocator.alloc() { - entry.set_frame(frame, Flags::PRESENT | Flags::WRITE); + entry.set_frame(frame, Flags::PRESENT | Flags::WRITE | Flags::ACCESSED | Flags::PAGE_BIT); created = true; } else { return Err(MapToError::FrameAllocationFailed); @@ -241,214 +241,6 @@ impl<'a> RecursivePageTable<'a> { } } -impl<'a> Mapper for RecursivePageTable<'a> { - fn map_to( - &mut self, - page: Page, - frame: PhysFrame, - flags: PageTableFlags, - allocator: &mut A, - ) -> Result, MapToError> - where - A: FrameAllocator, - { - let p4 = &mut self.p4; - - let p3_page = p3_page(page, self.recursive_index); - let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; - - if !p3[page.p3_index()].is_unused() { - return Err(MapToError::PageAlreadyMapped); - } - p3[page.p3_index()].set_addr(frame.start_address(), flags | Flags::HUGE_PAGE); - - Ok(MapperFlush::new(page)) - } - - fn unmap( - &mut self, - page: Page, - ) -> Result<(PhysFrame, MapperFlush), UnmapError> { - let p4 = &mut self.p4; - let p4_entry = &p4[page.p4_index()]; - - p4_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; - let p3_entry = &mut p3[page.p3_index()]; - let flags = p3_entry.flags(); - - if !flags.contains(PageTableFlags::PRESENT) { - return Err(UnmapError::PageNotMapped); - } - if !flags.contains(PageTableFlags::HUGE_PAGE) { - return Err(UnmapError::ParentEntryHugePage); - } - - let frame = PhysFrame::from_start_address(p3_entry.addr()) - .map_err(|()| UnmapError::InvalidFrameAddress(p3_entry.addr()))?; - - p3_entry.set_unused(); - Ok((frame, MapperFlush::new(page))) - } - - fn update_flags( - &mut self, - page: Page, - flags: PageTableFlags, - ) -> Result, FlagUpdateError> { - let p4 = &mut self.p4; - - if p4[page.p4_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; - - if p3[page.p3_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - p3[page.p3_index()].set_flags(flags | Flags::HUGE_PAGE); - - Ok(MapperFlush::new(page)) - } - - fn translate_page(&self, page: Page) -> Option> { - let p4 = &self.p4; - - if p4[page.p4_index()].is_unused() { - return None; - } - - let p3 = unsafe { &*(p3_ptr(page, self.recursive_index)) }; - let p3_entry = &p3[page.p3_index()]; - - if p3_entry.is_unused() { - return None; - } - - PhysFrame::from_start_address(p3_entry.addr()).ok() - } -} - -impl<'a> Mapper for RecursivePageTable<'a> { - fn map_to( - &mut self, - page: Page, - frame: PhysFrame, - flags: PageTableFlags, - allocator: &mut A, - ) -> Result, MapToError> - where - A: FrameAllocator, - { - let p4 = &mut self.p4; - - let p3_page = p3_page(page, self.recursive_index); - let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; - - let p2_page = p2_page(page, self.recursive_index); - let p2 = unsafe { Self::create_next_table(&mut p3[page.p3_index()], p2_page, allocator)? }; - - if !p2[page.p2_index()].is_unused() { - return Err(MapToError::PageAlreadyMapped); - } - p2[page.p2_index()].set_addr(frame.start_address(), flags | Flags::HUGE_PAGE); - - Ok(MapperFlush::new(page)) - } - - fn unmap( - &mut self, - page: Page, - ) -> Result<(PhysFrame, MapperFlush), UnmapError> { - let p4 = &mut self.p4; - let p4_entry = &p4[page.p4_index()]; - p4_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; - let p3_entry = &p3[page.p3_index()]; - p3_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; - let p2_entry = &mut p2[page.p2_index()]; - let flags = p2_entry.flags(); - - if !flags.contains(PageTableFlags::PRESENT) { - return Err(UnmapError::PageNotMapped); - } - if !flags.contains(PageTableFlags::HUGE_PAGE) { - return Err(UnmapError::ParentEntryHugePage); - } - - let frame = PhysFrame::from_start_address(p2_entry.addr()) - .map_err(|()| UnmapError::InvalidFrameAddress(p2_entry.addr()))?; - - p2_entry.set_unused(); - Ok((frame, MapperFlush::new(page))) - } - - fn update_flags( - &mut self, - page: Page, - flags: PageTableFlags, - ) -> Result, FlagUpdateError> { - let p4 = &mut self.p4; - - if p4[page.p4_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; - - if p3[page.p3_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; - - if p2[page.p2_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - p2[page.p2_index()].set_flags(flags | Flags::HUGE_PAGE); - - Ok(MapperFlush::new(page)) - } - - fn translate_page(&self, page: Page) -> Option> { - let p4 = &self.p4; - - if p4[page.p4_index()].is_unused() { - return None; - } - - let p3 = unsafe { &*(p3_ptr(page, self.recursive_index)) }; - let p3_entry = &p3[page.p3_index()]; - - if p3_entry.is_unused() { - return None; - } - - let p2 = unsafe { &*(p2_ptr(page, self.recursive_index)) }; - let p2_entry = &p2[page.p2_index()]; - - if p2_entry.is_unused() { - return None; - } - - PhysFrame::from_start_address(p2_entry.addr()).ok() - } -} impl<'a> Mapper for RecursivePageTable<'a> { fn map_to( diff --git a/kernel/Cargo.lock b/kernel/Cargo.lock index 05f0710..7795f1f 100644 --- a/kernel/Cargo.lock +++ b/kernel/Cargo.lock @@ -5,6 +5,7 @@ dependencies = [ "bare-metal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)", "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)", + "log 0.4.5 (registry+https://github.com/rust-lang/crates.io-index)", "os_bootinfo 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)", "register 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)", "usize_conversions 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -176,6 +177,14 @@ name = "redox_syscall" version = "0.1.40" source = "registry+https://github.com/rust-lang/crates.io-index" +[[package]] +name = "register" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "tock-registers 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "register" version = "0.2.1" @@ -238,6 +247,11 @@ dependencies = [ "remove_dir_all 0.5.1 (registry+https://github.com/rust-lang/crates.io-index)", ] +[[package]] +name = "tock-registers" +version = "0.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" + [[package]] name = "tock-registers" version = "0.2.0" @@ -271,6 +285,7 @@ dependencies = [ "log 0.4.5 (registry+https://github.com/rust-lang/crates.io-index)", "once 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)", "redox_syscall 0.1.40 (registry+https://github.com/rust-lang/crates.io-index)", + "register 0.1.1 (registry+https://github.com/rust-lang/crates.io-index)", "riscv 0.3.0", "simple-filesystem 0.0.1 (git+https://github.com/wangrunji0408/SimpleFileSystem-Rust)", "spin 0.4.9 (registry+https://github.com/rust-lang/crates.io-index)", @@ -384,6 +399,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" "checksum pulldown-cmark 0.0.3 (registry+https://github.com/rust-lang/crates.io-index)" = "8361e81576d2e02643b04950e487ec172b687180da65c731c03cf336784e6c07" "checksum rand 0.4.3 (registry+https://github.com/rust-lang/crates.io-index)" = "8356f47b32624fef5b3301c1be97e5944ecdd595409cc5da11d05f211db6cfbd" "checksum redox_syscall 0.1.40 (registry+https://github.com/rust-lang/crates.io-index)" = "c214e91d3ecf43e9a4e41e578973adeb14b474f2bee858742d127af75a0112b1" +"checksum register 0.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "0e985243ba7e1c336b62444ef2a10d7bd87cf41a222285ae3de605c859006479" "checksum register 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "e10f31b6d2299e5620986ad9fcdd66463e125ad72af4f403f9aedf7592d5ccdb" "checksum remove_dir_all 0.5.1 (registry+https://github.com/rust-lang/crates.io-index)" = "3488ba1b9a2084d38645c4c08276a1752dcbf2c7130d74f1569681ad5d2799c5" "checksum simple-filesystem 0.0.1 (git+https://github.com/wangrunji0408/SimpleFileSystem-Rust)" = "" @@ -391,6 +407,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" "checksum spin 0.4.9 (registry+https://github.com/rust-lang/crates.io-index)" = "37b5646825922b96b5d7d676b5bb3458a54498e96ed7b0ce09dc43a07038fea4" "checksum static_assertions 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)" = "c19be23126415861cb3a23e501d34a708f7f9b2183c5252d690941c2e69199d5" "checksum tempdir 0.3.7 (registry+https://github.com/rust-lang/crates.io-index)" = "15f2b5fb00ccdf689e0149d1b1b3c03fead81c2b37735d812fa8bddbbf41b6d8" +"checksum tock-registers 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "2acc33f980e23cee18d234a32d0637fbc1ea55e13ab04012fa857b899fa1b7a9" "checksum tock-registers 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3a385d94f3f62e60445a0adb9ff8d9621faa272234530d4c0f848ec98f88e316" "checksum uart_16550 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "269f953d8de3226f7c065c589c7b4a3e83d10a419c7c3b5e2e0f197e6acc966e" "checksum unicode-width 0.1.5 (registry+https://github.com/rust-lang/crates.io-index)" = "882386231c45df4700b275c7ff55b6f3698780a650026380e72dabe76fa46526" diff --git a/kernel/Cargo.toml b/kernel/Cargo.toml index c80b6ef..06ea088 100644 --- a/kernel/Cargo.toml +++ b/kernel/Cargo.toml @@ -32,6 +32,7 @@ bit-allocator = { path = "../crate/bit-allocator" } ucore-memory = { path = "../crate/memory" } ucore-process = { path = "../crate/process" } simple-filesystem = { git = "https://github.com/wangrunji0408/SimpleFileSystem-Rust" } +register="0.1.0" [target.'cfg(target_arch = "x86_64")'.dependencies] bootloader = "0.3" diff --git a/kernel/src/arch/aarch64/boot/boot.S b/kernel/src/arch/aarch64/boot/boot.S index b8a142e..57a4239 100644 --- a/kernel/src/arch/aarch64/boot/boot.S +++ b/kernel/src/arch/aarch64/boot/boot.S @@ -17,6 +17,8 @@ halt: setup: # store the desired EL1 stack pointer in x1 adr x1, _start + # FIXME + lsl x1, x1, #2 # use SP_ELx for Exception level ELx msr SPsel, #1 diff --git a/kernel/src/arch/aarch64/interrupt/handler.rs b/kernel/src/arch/aarch64/interrupt/handler.rs index 85d1faf..787cbf5 100644 --- a/kernel/src/arch/aarch64/interrupt/handler.rs +++ b/kernel/src/arch/aarch64/interrupt/handler.rs @@ -38,10 +38,11 @@ pub struct Info { /// the trap frame for the exception. #[no_mangle] pub extern "C" fn rust_trap(info: Info, esr: u32, tf: &mut TrapFrame) { - let syndrome = Syndrome::from(esr); - trace!("Interrupt: {:?} from: {:?}", syndrome, info); + trace!("Interrupt: {:?}, ELR: {:#x?}", info, tf.elr); match info.kind { Kind::Synchronous => { + let syndrome = Syndrome::from(esr); + trace!("ESR: {:#x?}, Syndrome: {:?}", esr, syndrome); // syndrome is only valid with sync match syndrome { Syndrome::Brk(brk) => handle_break(brk, tf), diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index 126cf57..3e7f6d8 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -11,64 +11,55 @@ use core::ops::Range; /// Memory initialization. pub fn init() { - /*let (start, end) = memory_map().expect("failed to find memory map"); - unsafe { - HEAP_ALLOCATOR.lock().init(start, end - start); - }*/ - - - #[repr(align(4096))] struct PageData([u8; PAGE_SIZE]); - static PAGE_TABLE_ROOT: PageData = PageData([0; PAGE_SIZE]); + static PAGE_TABLE_LVL4: PageData = PageData([0; PAGE_SIZE]); + static PAGE_TABLE_LVL3: PageData = PageData([0; PAGE_SIZE]); + static PAGE_TABLE_LVL2: PageData = PageData([0; PAGE_SIZE]); - let frame = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_ROOT as *const _ as u64)); - super::paging::setup_page_table(frame); + let frame_lvl4 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL4 as *const _ as u64)); + let frame_lvl3 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL3 as *const _ as u64)); + let frame_lvl2 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL2 as *const _ as u64)); + super::paging::setup_page_table(frame_lvl4, frame_lvl3, frame_lvl2); init_mmu(); - init_frame_allocator(); init_heap(); - let (start, end) = memory_map().expect("failed to find memory map"); - let mut v = vec![]; - for i in 0..(20 + (start & 0xf)) { - v.push(i); - println!("{:x?} {:x?}", &v[i] as * const _ as usize, v); - } - + info!("memory: init end"); } extern "C" { static _end: u8; } - fn init_frame_allocator() { + use bit_allocator::BitAlloc; + use core::ops::Range; use consts::{MEMORY_OFFSET}; - let (start, end) = memory_map().expect("failed to find memory map"); - info!("{:x?} {:x?}", start, end); + let (start, end) = memory_map().expect("failed to find memory map"); let mut ba = FRAME_ALLOCATOR.lock(); - use core::mem::size_of; - use ::memory::FrameAlloc; - info!("{:x?} {:x?}", &FRAME_ALLOCATOR as *const _ as usize, size_of::()); - use consts::{KERNEL_HEAP_OFFSET, KERNEL_HEAP_SIZE}; - info!("{:x?} {:x?}", KERNEL_HEAP_OFFSET + KERNEL_HEAP_SIZE, end); ba.insert(to_range(start, end)); info!("FrameAllocator init end"); + /* + * @param: + * start: start address + * end: end address + * @brief: + * transform the memory address to the page number + * @retval: + * the page number range from start address to end address + */ fn to_range(start: usize, end: usize) -> Range { let page_start = (start - MEMORY_OFFSET) / PAGE_SIZE; let page_end = (end - MEMORY_OFFSET - 1) / PAGE_SIZE + 1; - // info!("{:x?} {:x?}", page_start, page_end); page_start..page_end } } fn init_mmu() { - info!("init_mmu"); - // device. MAIR_EL1.write( // Attribute 1 @@ -80,7 +71,6 @@ fn init_mmu() { ); // Configure various settings of stage 1 of the EL1 translation regime. let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange); - info!("{:x?}", ips); TCR_EL1.write( TCR_EL1::TBI0::Ignored + TCR_EL1::IPS.val(ips) @@ -97,21 +87,20 @@ fn init_mmu() { // First, force all previous changes to be seen before the MMU is enabled. unsafe { barrier::isb(barrier::SY); } - info!("{:x?}", TCR_EL1.get()); // Enable the MMU and turn on data and instruction caching. SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable); // Force MMU init to complete before next instruction unsafe { barrier::isb(barrier::SY); } - info!("mmu enabled!"); + info!("mmu enabled"); } /// Returns the (start address, end address) of the available memory on this /// system if it can be determined. If it cannot, `None` is returned. /// /// This function is expected to return `Some` under all normal cirumstances. -pub fn memory_map() -> Option<(usize, usize)> { +fn memory_map() -> Option<(usize, usize)> { let binary_end = unsafe { (&_end as *const u8) as u32 }; let mut atags: Atags = Atags::get(); diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index 603346d..9696db9 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -1,6 +1,6 @@ //! Page table implementations for aarch64. -use bit_allocator::{BitAlloc}; // Depends on kernel +use consts::{KERNEL_PML4, RECURSIVE_INDEX}; use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame}; use ucore_memory::memory_set::*; use ucore_memory::PAGE_SIZE; @@ -11,29 +11,121 @@ use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, Pag use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB}; use aarch64::{regs::*}; -// need 1 page -pub fn setup_page_table(frame: Frame) { - let p4 = unsafe { &mut *(frame.start_address().as_u64() as *mut Aarch64PageTable) }; - p4.zero(); - - - // p4.set_recursive(RECURSIVE_PAGE_PML4, frame.clone()); +register_bitfields! {u64, + // AArch64 Reference Manual page 2150 + STAGE1_DESCRIPTOR [ + /// Execute-never + XN OFFSET(54) NUMBITS(1) [ + False = 0, + True = 1 + ], + + /// Various address fields, depending on use case + LVL4_OUTPUT_ADDR_4KiB OFFSET(39) NUMBITS(9) [], // [47:39] + LVL3_OUTPUT_ADDR_4KiB OFFSET(30) NUMBITS(18) [], // [47:30] + LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21] + NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12] + + /// Access flag + AF OFFSET(10) NUMBITS(1) [ + False = 0, + True = 1 + ], + + /// Shareability field + SH OFFSET(8) NUMBITS(2) [ + OuterShareable = 0b10, + InnerShareable = 0b11 + ], + + /// Access Permissions + AP OFFSET(6) NUMBITS(2) [ + RW_EL1 = 0b00, + RW_EL1_EL0 = 0b01, + RO_EL1 = 0b10, + RO_EL1_EL0 = 0b11 + ], + + /// Memory attributes index into the MAIR_EL1 register + AttrIndx OFFSET(2) NUMBITS(3) [], + + TYPE OFFSET(1) NUMBITS(1) [ + Block = 0, + Table = 1 + ], + + VALID OFFSET(0) NUMBITS(1) [ + False = 0, + True = 1 + ] + ] +} - // Set kernel identity map - // 0x10000000 ~ 1K area - p4.map_identity(0o777, EF::PRESENT | EF::PXN | EF::UXN); +// need 3 page +pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) { + let p4 = unsafe { &mut *(frame_lvl4.start_address().as_u64() as *mut Aarch64PageTable) }; + let p3 = unsafe { &mut *(frame_lvl3.start_address().as_u64() as *mut Aarch64PageTable) }; + let p2 = unsafe { &mut *(frame_lvl2.start_address().as_u64() as *mut Aarch64PageTable) }; + p4.zero(); + p3.zero(); + p2.zero(); - // 0x80000000 ~ 8K area - p4.map_identity(0, EF::PRESENT); - // p2.map_identity(KERNEL_PML4, EF::PRESENT | EF::READABLE | EF::WRITABLE); - // p2.map_identity(KERNEL_PML4 + 1, EF::VALID | EF::READABLE | EF::WRITABLE | EF::EXECUTABLE); + mod mair { + pub const NORMAL: u64 = 0; + pub const DEVICE: u64 = 1; + } - // use super::riscv::register::satp; - // unsafe { satp::set(satp::Mode::Sv32, 0, frame); } - // sfence_vma_all(); + // Fill the rest of the LVL2 (2MiB) entries as block + // descriptors. Differentiate between normal and device mem. + const MMIO_BASE: u64 = 0x3F000000; + let mmio_base: u64 = MMIO_BASE >> 21; + let mut common = STAGE1_DESCRIPTOR::VALID::True + + STAGE1_DESCRIPTOR::TYPE::Block + + STAGE1_DESCRIPTOR::AP::RW_EL1 + + STAGE1_DESCRIPTOR::AF::True; + // + STAGE1_DESCRIPTOR::XN::True; + + for i in 0..512 { + let j: u64 = i as u64; + + let mem_attr = if j >= mmio_base { + STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE) + } else { + STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL) + }; + + p2[i].entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(j)).value; + } - ttbr0_el1_write(frame); + common = common + STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL); + + p3[0].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl2.start_address().as_u64() >> 12)).value; + p3[1].entry = (common + STAGE1_DESCRIPTOR::LVL3_OUTPUT_ADDR_4KiB.val(1)).value; + p4[0].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl3.start_address().as_u64() >> 12)).value; + p4[RECURSIVE_INDEX].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl4.start_address().as_u64() >> 12)).value; + + // warn!("p2"); + // for i in 0..512 { + // if p2[i].flags().bits() != 0 { + // info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]); + // } + // } + // warn!("p3"); + // for i in 0..512 { + // if p3[i].flags().bits() != 0 { + // info!("{:x?} {:x?} {:x?}",i, &p3[i] as *const _ as usize, p3[i]); + // } + // } + // warn!("p4"); + // for i in 0..512 { + // if p4[i].flags().bits() != 0 { + // info!("{:x?} {:x?} {:x?}",i, &p4[i] as *const _ as usize, p4[i]); + // } + // } + + ttbr0_el1_write(frame_lvl4); tlb_invalidate(); + info!("setup init page table end"); } @@ -69,7 +161,7 @@ impl PageTable for ActivePageTable { type Entry = PageEntry; fn map(&mut self, addr: usize, target: usize) -> &mut PageEntry { - let flags = EF::PRESENT | EF::WRITE | EF::UXN; + let flags = EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::UXN | EF::PAGE_BIT; self.0.map_to(Page::of_addr(addr), Frame::of_addr(target), flags, &mut FrameAllocatorForAarch64) .unwrap().flush(); self.get_entry(addr) @@ -81,7 +173,7 @@ impl PageTable for ActivePageTable { } fn get_entry(&mut self, addr: usize) -> &mut PageEntry { - let entry_addr = ((addr >> 9) & 0o777_777_777_7770) | 0xffffff80_00000000; + let entry_addr = ((addr >> 9) & 0o777_777_777_7770) | (RECURSIVE_INDEX << 39); unsafe { &mut *(entry_addr as *mut PageEntry) } } @@ -99,9 +191,12 @@ impl PageTable for ActivePageTable { } } +const ROOT_PAGE_TABLE: *mut Aarch64PageTable = + ((RECURSIVE_INDEX << 39) | (RECURSIVE_INDEX << 30) | (RECURSIVE_INDEX << 21) | (RECURSIVE_INDEX << 12)) as *mut Aarch64PageTable; + impl ActivePageTable { pub unsafe fn new() -> Self { - ActivePageTable(RecursivePageTable::new(&mut *(0xffff_ffff_ffff_f000 as *mut _)).unwrap()) + ActivePageTable(RecursivePageTable::new(&mut *(ROOT_PAGE_TABLE as *mut _)).unwrap()) } fn with_temporary_map(&mut self, frame: &Frame, f: impl FnOnce(&mut ActivePageTable, &mut Aarch64PageTable)) { // Create a temporary page @@ -161,7 +256,7 @@ impl Entry for PageEntry { let mut addr = self as *const _ as usize; for _ in 0..3 { // Upper level entry - addr = ((addr >> 9) & 0o777_777_777_7770) | 0xffffff80_00000000; + addr = ((addr >> 9) & 0o777_777_777_7770) | (RECURSIVE_INDEX << 39); // set USER_ACCESSIBLE unsafe { (*(addr as *mut EF)).insert(EF::USER_ACCESSIBLE) }; } @@ -200,24 +295,24 @@ impl InactivePageTable for InactivePageTable0 { active_table().with_temporary_map(&frame, |_, table: &mut Aarch64PageTable| { table.zero(); // set up recursive mapping for the table - table[511].set_frame(frame.clone(), EF::PRESENT | EF::WRITE); + table[RECURSIVE_INDEX].set_frame(frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT); }); InactivePageTable0 { p4_frame: frame } } fn edit(&mut self, f: impl FnOnce(&mut Self::Active)) { active_table().with_temporary_map(&ttbr0_el1_read().0, |active_table, p4_table: &mut Aarch64PageTable| { - let backup = p4_table[0o777].clone(); + let backup = p4_table[RECURSIVE_INDEX].clone(); // overwrite recursive mapping - p4_table[0o777].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE); + p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT); tlb_invalidate(); // execute f in the new context f(active_table); // restore recursive mapping to original p4 table - p4_table[0o777] = backup; + p4_table[RECURSIVE_INDEX] = backup; tlb_invalidate(); }); } @@ -228,6 +323,7 @@ impl InactivePageTable for InactivePageTable0 { debug!("switch table {:?} -> {:?}", old_frame, new_frame); if old_frame != new_frame { ttbr0_el1_write(new_frame); + tlb_invalidate(); } } @@ -237,11 +333,13 @@ impl InactivePageTable for InactivePageTable0 { debug!("switch table {:?} -> {:?}", old_frame, new_frame); if old_frame != new_frame { ttbr0_el1_write(new_frame); + tlb_invalidate(); } f(); debug!("switch table {:?} -> {:?}", new_frame, old_frame); if old_frame != new_frame { ttbr0_el1_write(old_frame); + tlb_invalidate(); } } @@ -264,13 +362,12 @@ impl InactivePageTable for InactivePageTable0 { impl InactivePageTable0 { fn map_kernel(&mut self) { - let mut table = unsafe { &mut *(0xffff_ffff_ffff_f000 as *mut Aarch64PageTable) }; - // Kernel at 0xffff_ff00_0000_0000 - // Kernel stack at 0x0000_57ac_0000_0000 (defined in bootloader crate) - let e0 = table[0].clone(); + let table = unsafe { &mut *ROOT_PAGE_TABLE }; + let e0 = table[KERNEL_PML4].clone(); + assert!(!e0.is_unused()); + self.edit(|_| { - table[0].set_addr(e0.addr(), e0.flags() & EF::GLOBAL); - //table[175].set_addr(estack.addr(), estack.flags() & EF::GLOBAL); + table[KERNEL_PML4].set_addr(e0.addr(), e0.flags() & EF::GLOBAL); }); } } diff --git a/kernel/src/consts.rs b/kernel/src/consts.rs index b2cdefe..e879173 100644 --- a/kernel/src/consts.rs +++ b/kernel/src/consts.rs @@ -131,15 +131,12 @@ mod x86_64 { #[cfg(target_arch = "aarch64")] mod aarch64 { - //! TODO: replace unmiplemented consts with real value - const UNIMPLEMENTED: usize = 0; - pub const KERNEL_OFFSET: usize = UNIMPLEMENTED; - pub const KERNEL_PML4: usize = UNIMPLEMENTED; - pub const KERNEL_HEAP_OFFSET: usize = UNIMPLEMENTED; + pub const RECURSIVE_INDEX: usize = 0o777; + pub const KERNEL_OFFSET: usize = 0; + pub const KERNEL_PML4: usize = 0; pub const KERNEL_HEAP_SIZE: usize = 8 * 1024 * 1024; - pub const MEMORY_OFFSET: usize = UNIMPLEMENTED; - pub const MEMORY_END: usize = UNIMPLEMENTED; - pub const USER_STACK_OFFSET: usize = UNIMPLEMENTED; - pub const USER_STACK_SIZE: usize = UNIMPLEMENTED; - pub const USER32_STACK_OFFSET: usize = UNIMPLEMENTED; + pub const MEMORY_OFFSET: usize = 0; + pub const USER_STACK_OFFSET: usize = 0x3000_0000; + pub const USER_STACK_SIZE: usize = 1 * 1024 * 1024; + pub const USER32_STACK_OFFSET: usize = USER_STACK_OFFSET; } diff --git a/kernel/src/lib.rs b/kernel/src/lib.rs index 063b1d0..05cc181 100644 --- a/kernel/src/lib.rs +++ b/kernel/src/lib.rs @@ -38,6 +38,10 @@ extern crate aarch64; use linked_list_allocator::LockedHeap; + +#[macro_use] +extern crate register; + #[macro_use] // print! pub mod logging; mod memory; diff --git a/kernel/src/memory.rs b/kernel/src/memory.rs index bbe78db..100925e 100644 --- a/kernel/src/memory.rs +++ b/kernel/src/memory.rs @@ -1,5 +1,5 @@ pub use arch::paging::*; -use bit_allocator::{BitAlloc, BitAlloc4K, BitAlloc64K}; +use bit_allocator::{BitAlloc, BitAlloc4K, BitAlloc64K, BitAlloc1M}; use consts::MEMORY_OFFSET; use spin::{Mutex, MutexGuard}; use super::HEAP_ALLOCATOR; @@ -19,7 +19,7 @@ pub type FrameAlloc = BitAlloc4K; // Raspberry Pi 3 has 1G memory #[cfg(target_arch = "aarch64")] -pub type FrameAlloc = BitAlloc64K; +pub type FrameAlloc = BitAlloc1M; lazy_static! { pub static ref FRAME_ALLOCATOR: Mutex = Mutex::new(FrameAlloc::default()); @@ -76,4 +76,4 @@ pub fn init_heap() { // use ucore_memory::cow::test::test_with; // test_with(&mut active_table()); // } -//} \ No newline at end of file +//} From a9de99d3a9edc73e1b555efb38de5cc0e49886c1 Mon Sep 17 00:00:00 2001 From: equation314 Date: Wed, 21 Nov 2018 01:50:34 +0800 Subject: [PATCH 04/16] aarch64/mmu: remap kernel memory ranges at the end of memory::init() --- crate/aarch64/src/paging/mod.rs | 69 ++++++++++++++- crate/aarch64/src/paging/recursive.rs | 115 +++++++++++++------------ crate/memory/src/memory_set.rs | 5 +- kernel/src/arch/aarch64/boot/boot.S | 2 +- kernel/src/arch/aarch64/boot/linker.ld | 18 +++- kernel/src/arch/aarch64/memory.rs | 52 ++++++++--- kernel/src/arch/aarch64/paging.rs | 64 ++++++++------ 7 files changed, 224 insertions(+), 101 deletions(-) diff --git a/crate/aarch64/src/paging/mod.rs b/crate/aarch64/src/paging/mod.rs index ebc00dc..855b876 100644 --- a/crate/aarch64/src/paging/mod.rs +++ b/crate/aarch64/src/paging/mod.rs @@ -18,7 +18,7 @@ mod frame_alloc; mod page_table; mod recursive; -/// Trait for abstracting over the three possible page sizes on x86_64, 4KiB, 2MiB, 1GiB. +/// Trait for abstracting over the three possible block/page sizes on aarch64, 4KiB, 2MiB, 1GiB. pub trait PageSize: Copy + Eq + PartialOrd + Ord { /// The page size in bytes. const SIZE: u64; @@ -34,6 +34,14 @@ pub trait NotGiantPageSize: PageSize {} #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] pub enum Size4KiB {} +/// A “huge” 2MiB page. +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub enum Size2MiB {} + +/// A “giant” 1GiB page. +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub enum Size1GiB {} + impl PageSize for Size4KiB { const SIZE: u64 = 4096; const SIZE_AS_DEBUG_STR: &'static str = "4KiB"; @@ -41,6 +49,18 @@ impl PageSize for Size4KiB { impl NotGiantPageSize for Size4KiB {} +impl PageSize for Size2MiB { + const SIZE: u64 = Size4KiB::SIZE * 512; + const SIZE_AS_DEBUG_STR: &'static str = "2MiB"; +} + +impl NotGiantPageSize for Size2MiB {} + +impl PageSize for Size1GiB { + const SIZE: u64 = Size2MiB::SIZE * 512; + const SIZE_AS_DEBUG_STR: &'static str = "1GiB"; +} + /// A virtual memory page. #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] #[repr(C)] @@ -97,6 +117,14 @@ impl Page { pub fn range_inclusive(start: Self, end: Self) -> PageRangeInclusive { PageRangeInclusive { start, end } } + + pub fn of_addr(address: usize) -> Self { + Self::containing_address(VirtAddr::new(address as u64)) + } + + pub fn range_of(begin: usize, end: usize) -> PageRange { + Self::range(Page::of_addr(begin), Page::of_addr(end - 1) + 1) + } } impl Page { @@ -106,6 +134,31 @@ impl Page { } } +impl Page { + /// Returns the 1GiB memory page with the specified page table indices. + pub fn from_page_table_indices_1gib(p4_index: u9, p3_index: u9) -> Self { + use bit_field::BitField; + + let mut addr = 0; + addr.set_bits(39..48, u64::from(p4_index)); + addr.set_bits(30..39, u64::from(p3_index)); + Page::containing_address(VirtAddr::new(addr)) + } +} + +impl Page { + /// Returns the 2MiB memory page with the specified page table indices. + pub fn from_page_table_indices_2mib(p4_index: u9, p3_index: u9, p2_index: u9) -> Self { + use bit_field::BitField; + + let mut addr = 0; + addr.set_bits(39..48, u64::from(p4_index)); + addr.set_bits(30..39, u64::from(p3_index)); + addr.set_bits(21..30, u64::from(p2_index)); + Page::containing_address(VirtAddr::new(addr)) + } +} + impl Page { /// Returns the 4KiB memory page with the specified page table indices. pub fn from_page_table_indices(p4_index: u9, p3_index: u9, p2_index: u9, p1_index: u9) -> Self { @@ -199,6 +252,16 @@ impl Iterator for PageRange { } } +impl PageRange { + /// Converts the range of 2MiB pages to a range of 4KiB pages. + pub fn as_4kib_page_range(self) -> PageRange { + PageRange { + start: Page::containing_address(self.start.start_address()), + end: Page::containing_address(self.end.start_address()), + } + } +} + impl fmt::Debug for PageRange { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.debug_struct("PageRange") @@ -294,6 +357,10 @@ impl PhysFrame { pub fn range_inclusive(start: PhysFrame, end: PhysFrame) -> PhysFrameRangeInclusive { PhysFrameRangeInclusive { start, end } } + + pub fn of_addr(address: usize) -> Self { + Self::containing_address(PhysAddr::new(address as u64)) + } } impl fmt::Debug for PhysFrame { diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index d735216..31d1802 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -239,6 +239,45 @@ impl<'a> RecursivePageTable<'a> { inner(entry, next_table_page, allocator) } + + pub fn p3_ptr(&self, page: Page) -> *mut PageTable { + self.p3_page(page).start_address().as_mut_ptr() + } + + pub fn p2_ptr(&self, page: Page) -> *mut PageTable { + self.p2_page(page).start_address().as_mut_ptr() + } + + pub fn p1_ptr(&self, page: Page) -> *mut PageTable { + self.p1_page(page).start_address().as_mut_ptr() + } + + fn p3_page(&self, page: Page) -> Page { + Page::from_page_table_indices( + self.recursive_index, + self.recursive_index, + self.recursive_index, + page.p4_index(), + ) + } + + fn p2_page(&self, page: Page) -> Page { + Page::from_page_table_indices( + self.recursive_index, + self.recursive_index, + page.p4_index(), + page.p3_index(), + ) + } + + fn p1_page(&self, page: Page) -> Page { + Page::from_page_table_indices( + self.recursive_index, + page.p4_index(), + page.p3_index(), + page.p2_index(), + ) + } } @@ -253,15 +292,16 @@ impl<'a> Mapper for RecursivePageTable<'a> { where A: FrameAllocator, { - let p4 = &mut self.p4; + let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let p4 = &mut self_mut.p4; - let p3_page = p3_page(page, self.recursive_index); + let p3_page = self.p3_page(page); let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; - let p2_page = p2_page(page, self.recursive_index); + let p2_page = self.p2_page(page); let p2 = unsafe { Self::create_next_table(&mut p3[page.p3_index()], p2_page, allocator)? }; - let p1_page = p1_page(page, self.recursive_index); + let p1_page = self.p1_page(page); let p1 = unsafe { Self::create_next_table(&mut p2[page.p2_index()], p1_page, allocator)? }; if !p1[page.p1_index()].is_unused() { @@ -276,28 +316,30 @@ impl<'a> Mapper for RecursivePageTable<'a> { &mut self, page: Page, ) -> Result<(PhysFrame, MapperFlush), UnmapError> { - let p4 = &mut self.p4; + let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let p4 = &mut self_mut.p4; + let p4_entry = &p4[page.p4_index()]; p4_entry.frame().map_err(|err| match err { FrameError::FrameNotPresent => UnmapError::PageNotMapped, FrameError::HugeFrame => UnmapError::ParentEntryHugePage, })?; - let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + let p3 = unsafe { &mut *(self.p3_ptr(page)) }; let p3_entry = &p3[page.p3_index()]; p3_entry.frame().map_err(|err| match err { FrameError::FrameNotPresent => UnmapError::PageNotMapped, FrameError::HugeFrame => UnmapError::ParentEntryHugePage, })?; - let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; + let p2 = unsafe { &mut *(self.p2_ptr(page)) }; let p2_entry = &p2[page.p2_index()]; p2_entry.frame().map_err(|err| match err { FrameError::FrameNotPresent => UnmapError::PageNotMapped, FrameError::HugeFrame => UnmapError::ParentEntryHugePage, })?; - let p1 = unsafe { &mut *(p1_ptr(page, self.recursive_index)) }; + let p1 = unsafe { &mut *(self.p1_ptr(page)) }; let p1_entry = &mut p1[page.p1_index()]; let frame = p1_entry.frame().map_err(|err| match err { @@ -314,25 +356,26 @@ impl<'a> Mapper for RecursivePageTable<'a> { page: Page, flags: PageTableFlags, ) -> Result, FlagUpdateError> { - let p4 = &mut self.p4; + let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let p4 = &mut self_mut.p4; if p4[page.p4_index()].is_unused() { return Err(FlagUpdateError::PageNotMapped); } - let p3 = unsafe { &mut *(p3_ptr(page, self.recursive_index)) }; + let p3 = unsafe { &mut *(self.p3_ptr(page)) }; if p3[page.p3_index()].is_unused() { return Err(FlagUpdateError::PageNotMapped); } - let p2 = unsafe { &mut *(p2_ptr(page, self.recursive_index)) }; + let p2 = unsafe { &mut *(self.p2_ptr(page)) }; if p2[page.p2_index()].is_unused() { return Err(FlagUpdateError::PageNotMapped); } - let p1 = unsafe { &mut *(p1_ptr(page, self.recursive_index)) }; + let p1 = unsafe { &mut *(self.p1_ptr(page)) }; if p1[page.p1_index()].is_unused() { return Err(FlagUpdateError::PageNotMapped); @@ -344,27 +387,28 @@ impl<'a> Mapper for RecursivePageTable<'a> { } fn translate_page(&self, page: Page) -> Option> { - let p4 = &self.p4; + let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let p4 = &mut self_mut.p4; if p4[page.p4_index()].is_unused() { return None; } - let p3 = unsafe { &*(p3_ptr(page, self.recursive_index)) }; + let p3 = unsafe { &*(self.p3_ptr(page)) }; let p3_entry = &p3[page.p3_index()]; if p3_entry.is_unused() { return None; } - let p2 = unsafe { &*(p2_ptr(page, self.recursive_index)) }; + let p2 = unsafe { &*(self.p2_ptr(page)) }; let p2_entry = &p2[page.p2_index()]; if p2_entry.is_unused() { return None; } - let p1 = unsafe { &*(p1_ptr(page, self.recursive_index)) }; + let p1 = unsafe { &*(self.p1_ptr(page)) }; let p1_entry = &p1[page.p1_index()]; if p1_entry.is_unused() { @@ -374,42 +418,3 @@ impl<'a> Mapper for RecursivePageTable<'a> { PhysFrame::from_start_address(p1_entry.addr()).ok() } } - -fn p3_ptr(page: Page, recursive_index: u9) -> *mut PageTable { - p3_page(page, recursive_index).start_address().as_mut_ptr() -} - -fn p3_page(page: Page, recursive_index: u9) -> Page { - Page::from_page_table_indices( - recursive_index, - recursive_index, - recursive_index, - page.p4_index(), - ) -} - -fn p2_ptr(page: Page, recursive_index: u9) -> *mut PageTable { - p2_page(page, recursive_index).start_address().as_mut_ptr() -} - -fn p2_page(page: Page, recursive_index: u9) -> Page { - Page::from_page_table_indices( - recursive_index, - recursive_index, - page.p4_index(), - page.p3_index(), - ) -} - -fn p1_ptr(page: Page, recursive_index: u9) -> *mut PageTable { - p1_page(page, recursive_index).start_address().as_mut_ptr() -} - -fn p1_page(page: Page, recursive_index: u9) -> Page { - Page::from_page_table_indices( - recursive_index, - page.p4_index(), - page.p3_index(), - page.p2_index(), - ) -} diff --git a/crate/memory/src/memory_set.rs b/crate/memory/src/memory_set.rs index ca3e7dc..f67c956 100644 --- a/crate/memory/src/memory_set.rs +++ b/crate/memory/src/memory_set.rs @@ -166,6 +166,9 @@ impl MemorySet { pub fn iter(&self) -> impl Iterator { self.areas.iter() } + pub fn edit(&mut self, f: impl FnOnce(&mut T::Active)) { + self.page_table.edit(f); + } pub unsafe fn with(&self, f: impl FnOnce()) { self.page_table.with(f); } @@ -223,4 +226,4 @@ impl Debug for MemorySet { pub struct Stack { pub top: usize, pub bottom: usize, -} \ No newline at end of file +} diff --git a/kernel/src/arch/aarch64/boot/boot.S b/kernel/src/arch/aarch64/boot/boot.S index e525340..7a126bd 100644 --- a/kernel/src/arch/aarch64/boot/boot.S +++ b/kernel/src/arch/aarch64/boot/boot.S @@ -93,7 +93,7 @@ set_stack: zero_bss: # load the start address and number of bytes in BSS section - ldr x1, =__bss_start + ldr x1, =sbss ldr x2, =__bss_length zero_bss_loop: diff --git a/kernel/src/arch/aarch64/boot/linker.ld b/kernel/src/arch/aarch64/boot/linker.ld index 34858e3..2c7bdce 100644 --- a/kernel/src/arch/aarch64/boot/linker.ld +++ b/kernel/src/arch/aarch64/boot/linker.ld @@ -8,34 +8,44 @@ SECTIONS { } . = 0x100000; /* Load the kernel at this address. It's also kernel stack top address */ + bootstacktop = .; .text : { + stext = .; *(.text.entry) *(.text .text.* .gnu.linkonce.t*) + . = ALIGN(4K); + etext = .; } .rodata : { + srodata = .; *(.rodata .rodata.* .gnu.linkonce.r*) + . = ALIGN(4K); + erodata = .; } .data : { + sdata = .; *(.data .data.* .gnu.linkonce.d*) + . = ALIGN(4K); + edata = .; } .bss (NOLOAD) : { . = ALIGN(32); - __bss_start = .; + sbss = .; *(.bss .bss.*) *(COMMON) - . = ALIGN(8); - __bss_end = .; + . = ALIGN(4K); + ebss = .; } /* end of the binary */ _end = ALIGN(8); /* number of bytes in BSS section and complete binary */ - __bss_length = (__bss_end - __bss_start); + __bss_length = (ebss - sbss); __binary_length = (_end - _start); /DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) } diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index 3e7f6d8..c04e9c3 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -1,13 +1,9 @@ //! Memory initialization for aarch64. -use bit_allocator::BitAlloc; use ucore_memory::PAGE_SIZE; -use memory::{FRAME_ALLOCATOR, init_heap}; +use memory::{FRAME_ALLOCATOR, init_heap, MemoryArea, MemoryAttr, MemorySet, Stack}; use super::atags::atags::Atags; -//use super::super::HEAP_ALLOCATOR; -use aarch64::{barrier, regs::*, addr::*}; -use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB}; -use core::ops::Range; +use aarch64::{barrier, regs::*, addr::*, paging::PhysFrame as Frame}; /// Memory initialization. pub fn init() { @@ -25,14 +21,11 @@ pub fn init() { init_mmu(); init_frame_allocator(); init_heap(); + remap_the_kernel(); info!("memory: init end"); } -extern "C" { - static _end: u8; -} - fn init_frame_allocator() { use bit_allocator::BitAlloc; use core::ops::Range; @@ -96,12 +89,36 @@ fn init_mmu() { info!("mmu enabled"); } +fn remap_the_kernel() { + let (bottom, top) = (0, bootstacktop as usize); + let kstack = Stack { + top, + bottom, + }; + static mut SPACE: [u8; 0x1000] = [0; 0x1000]; + let mut ms = unsafe { MemorySet::new_from_raw_space(&mut SPACE, kstack) }; + ms.push(MemoryArea::new_identity(bottom, top, MemoryAttr::default(), "kstack")); + ms.push(MemoryArea::new_identity(stext as usize, etext as usize, MemoryAttr::default().execute().readonly(), "text")); + ms.push(MemoryArea::new_identity(sdata as usize, edata as usize, MemoryAttr::default(), "data")); + ms.push(MemoryArea::new_identity(srodata as usize, erodata as usize, MemoryAttr::default().readonly(), "rodata")); + ms.push(MemoryArea::new_identity(sbss as usize, ebss as usize, MemoryAttr::default(), "bss")); + + // ensure the level 2 page table exists + ms.push(MemoryArea::new_identity(0x40000000, 0x40200000, MemoryAttr::default(), "arm_control")); + super::paging::remap_device_2mib(&mut ms, 0x3F000000, 0x40200000); + + unsafe { ms.activate(); } + use core::mem::forget; + forget(ms); + info!("kernel remap end"); +} + /// Returns the (start address, end address) of the available memory on this /// system if it can be determined. If it cannot, `None` is returned. /// /// This function is expected to return `Some` under all normal cirumstances. fn memory_map() -> Option<(usize, usize)> { - let binary_end = unsafe { (&_end as *const u8) as u32 }; + let binary_end = unsafe { _end as u32 }; let mut atags: Atags = Atags::get(); while let Some(atag) = atags.next() { @@ -113,3 +130,16 @@ fn memory_map() -> Option<(usize, usize)> { None } +extern { + fn bootstacktop(); + fn stext(); + fn etext(); + fn sdata(); + fn edata(); + fn srodata(); + fn erodata(); + fn sbss(); + fn ebss(); + fn _start(); + fn _end(); +} diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index 9696db9..a023237 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -8,8 +8,7 @@ use ucore_memory::paging::*; use aarch64::asm::{tlb_invalidate, ttbr0_el1_read, ttbr0_el1_write}; use aarch64::{PhysAddr, VirtAddr}; use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; -use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB}; -use aarch64::{regs::*}; +use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB, Size2MiB}; register_bitfields! {u64, // AArch64 Reference Manual page 2150 @@ -61,6 +60,11 @@ register_bitfields! {u64, ] } +mod mair { + pub const NORMAL: u64 = 0; + pub const DEVICE: u64 = 1; +} + // need 3 page pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) { let p4 = unsafe { &mut *(frame_lvl4.start_address().as_u64() as *mut Aarch64PageTable) }; @@ -70,11 +74,6 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) p3.zero(); p2.zero(); - mod mair { - pub const NORMAL: u64 = 0; - pub const DEVICE: u64 = 1; - } - // Fill the rest of the LVL2 (2MiB) entries as block // descriptors. Differentiate between normal and device mem. const MMIO_BASE: u64 = 0x3F000000; @@ -129,28 +128,37 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) info!("setup init page table end"); } -pub trait PageExt { - fn of_addr(address: usize) -> Self; - fn range_of(begin: usize, end: usize) -> PageRange; -} - -impl PageExt for Page { - fn of_addr(address: usize) -> Self { - Page::containing_address(VirtAddr::new(address as u64)) - } - fn range_of(begin: usize, end: usize) -> PageRange { - Page::range(Page::of_addr(begin), Page::of_addr(end - 1) + 1) - } -} - -pub trait FrameExt { - fn of_addr(address: usize) -> Self; -} +/// map the range [start, end) as device memory, insert to the MemorySet +pub fn remap_device_2mib(ms: &mut MemorySet, start_addr: usize, end_addr: usize) { + ms.edit(|active_table| { + let common = STAGE1_DESCRIPTOR::VALID::True + + STAGE1_DESCRIPTOR::TYPE::Block + + STAGE1_DESCRIPTOR::AP::RW_EL1 + + STAGE1_DESCRIPTOR::AF::True + + STAGE1_DESCRIPTOR::XN::True; + + let mem_attr = STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE); + + type Page2MiB = Page; + for page in Page2MiB::range_of(start_addr, end_addr) { + let p2 = unsafe { &mut *active_table.0.p2_ptr(page) }; + p2[page.p2_index()].entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(page.start_address().as_u64() >> 21)).value; + } -impl FrameExt for Frame { - fn of_addr(address: usize) -> Self { - Frame::containing_address(PhysAddr::new(address as u64)) - } + // let p2 = unsafe { &mut *(0o777_777_000_000_0000 as *mut Aarch64PageTable) }; + // for i in 0..512 { + // if p2[i].flags().bits() != 0 { + // info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]); + // } + // } + + // let p2 = unsafe { &mut *(0o777_777_000_001_0000 as *mut Aarch64PageTable) }; + // for i in 0..512 { + // if p2[i].flags().bits() != 0 { + // info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]); + // } + // } + }); } pub struct ActivePageTable(RecursivePageTable<'static>); From bb1c1abaa480d21c920082950effb5d35df8c55e Mon Sep 17 00:00:00 2001 From: equation314 Date: Wed, 21 Nov 2018 20:02:34 +0800 Subject: [PATCH 05/16] aarch64/mmu: can run on the real raspi3 --- crate/aarch64/src/asm.rs | 16 ++++- crate/aarch64/src/paging/recursive.rs | 3 +- kernel/src/arch/aarch64/board/raspi3/mod.rs | 7 +- .../src/arch/aarch64/board/raspi3/serial.rs | 8 +-- kernel/src/arch/aarch64/io.rs | 12 ++-- kernel/src/arch/aarch64/memory.rs | 70 +++++++++---------- kernel/src/arch/aarch64/mod.rs | 6 +- kernel/src/arch/aarch64/paging.rs | 19 +++-- 8 files changed, 72 insertions(+), 69 deletions(-) diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs index 17e6c29..63ce23a 100644 --- a/crate/aarch64/src/asm.rs +++ b/crate/aarch64/src/asm.rs @@ -1,9 +1,9 @@ use paging::PhysFrame; -use addr::PhysAddr; +use addr::{PhysAddr, VirtAddr}; use regs::*; #[inline(always)] -pub fn tlb_invalidate() { +pub fn tlb_invalidate_all() { unsafe { asm!( "dsb ishst @@ -14,6 +14,18 @@ pub fn tlb_invalidate() { } } +#[inline(always)] +pub fn tlb_invalidate(vaddr: VirtAddr) { + unsafe { + asm!( + "dsb ishst + tlbi vaae1is, $0 + dsb ish + isb" :: "r"(vaddr.as_u64() >> 12) + ); + } +} + /// Returns the current stack pointer. #[inline(always)] pub fn sp() -> *const u8 { diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index 31d1802..79b0a0d 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -28,7 +28,7 @@ impl MapperFlush { /// Flush the page from the TLB to ensure that the newest mapping is used. pub fn flush(self) { - tlb_invalidate(); + tlb_invalidate(self.0.start_address()); } /// Don't flush the TLB and silence the “must be used” warning. @@ -232,6 +232,7 @@ impl<'a> RecursivePageTable<'a> { let page_table_ptr = next_table_page.start_address().as_mut_ptr(); let page_table: &mut PageTable = unsafe { &mut *(page_table_ptr) }; if created { + tlb_invalidate(next_table_page.start_address()); page_table.zero(); } Ok(page_table) diff --git a/kernel/src/arch/aarch64/board/raspi3/mod.rs b/kernel/src/arch/aarch64/board/raspi3/mod.rs index 2b32a10..2d13315 100644 --- a/kernel/src/arch/aarch64/board/raspi3/mod.rs +++ b/kernel/src/arch/aarch64/board/raspi3/mod.rs @@ -7,12 +7,9 @@ pub mod timer; pub mod serial; pub fn init() { - // FIXME - // assert_has_not_been_called!("board::init must be called only once"); + assert_has_not_been_called!("board::init must be called only once"); - unsafe { - serial::SERIAL_PORT.init(); - } + serial::SERIAL_PORT.lock().init(); println!("Hello Raspberry Pi!"); } diff --git a/kernel/src/arch/aarch64/board/raspi3/serial.rs b/kernel/src/arch/aarch64/board/raspi3/serial.rs index 5434071..b6c29f7 100644 --- a/kernel/src/arch/aarch64/board/raspi3/serial.rs +++ b/kernel/src/arch/aarch64/board/raspi3/serial.rs @@ -20,8 +20,7 @@ impl SerialPort { /// Init a newly created SerialPort, can only be called once. pub fn init(&mut self) { - // FIXME - // assert_has_not_been_called!("SerialPort::init must be called only once"); + assert_has_not_been_called!("SerialPort::init must be called only once"); self.mu = Some(MiniUart::new()); } @@ -71,7 +70,4 @@ impl fmt::Write for SerialPort { } } -// FIXME -// pub static SERIAL_PORT: Mutex = Mutex::new(SerialPort::new()); -pub static mut SERIAL_PORT: SerialPort = SerialPort::new(); - +pub static SERIAL_PORT: Mutex = Mutex::new(SerialPort::new()); diff --git a/kernel/src/arch/aarch64/io.rs b/kernel/src/arch/aarch64/io.rs index deda39c..1a9d1d4 100644 --- a/kernel/src/arch/aarch64/io.rs +++ b/kernel/src/arch/aarch64/io.rs @@ -4,15 +4,11 @@ use core::fmt::{Arguments, Write}; use super::board::serial::{SerialRead, SERIAL_PORT}; pub fn getchar() -> char { - // FIXME - unsafe { - SERIAL_PORT.receive() as char - } + unsafe { SERIAL_PORT.force_unlock(); } + SERIAL_PORT.lock().receive() as char } pub fn putfmt(fmt: Arguments) { - // FIXME - unsafe { - SERIAL_PORT.write_fmt(fmt).unwrap() - } + unsafe { SERIAL_PORT.force_unlock(); } + SERIAL_PORT.lock().write_fmt(fmt).unwrap() } diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index c04e9c3..3f93e31 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -7,6 +7,14 @@ use aarch64::{barrier, regs::*, addr::*, paging::PhysFrame as Frame}; /// Memory initialization. pub fn init() { + init_frame_allocator(); + init_heap(); + remap_the_kernel(); + info!("memory: init end"); +} + +/// initialize temporary paging and enable mmu immediately after boot. Serial port is disabled at this time. +pub fn init_mmu_early() { #[repr(align(4096))] struct PageData([u8; PAGE_SIZE]); static PAGE_TABLE_LVL4: PageData = PageData([0; PAGE_SIZE]); @@ -18,41 +26,6 @@ pub fn init() { let frame_lvl2 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL2 as *const _ as u64)); super::paging::setup_page_table(frame_lvl4, frame_lvl3, frame_lvl2); - init_mmu(); - init_frame_allocator(); - init_heap(); - remap_the_kernel(); - - info!("memory: init end"); -} - -fn init_frame_allocator() { - use bit_allocator::BitAlloc; - use core::ops::Range; - use consts::{MEMORY_OFFSET}; - - let (start, end) = memory_map().expect("failed to find memory map"); - let mut ba = FRAME_ALLOCATOR.lock(); - ba.insert(to_range(start, end)); - info!("FrameAllocator init end"); - - /* - * @param: - * start: start address - * end: end address - * @brief: - * transform the memory address to the page number - * @retval: - * the page number range from start address to end address - */ - fn to_range(start: usize, end: usize) -> Range { - let page_start = (start - MEMORY_OFFSET) / PAGE_SIZE; - let page_end = (end - MEMORY_OFFSET - 1) / PAGE_SIZE + 1; - page_start..page_end - } -} - -fn init_mmu() { // device. MAIR_EL1.write( // Attribute 1 @@ -85,10 +58,35 @@ fn init_mmu() { // Force MMU init to complete before next instruction unsafe { barrier::isb(barrier::SY); } +} + +fn init_frame_allocator() { + use bit_allocator::BitAlloc; + use core::ops::Range; + use consts::{MEMORY_OFFSET}; + + let (start, end) = memory_map().expect("failed to find memory map"); + let mut ba = FRAME_ALLOCATOR.lock(); + ba.insert(to_range(start, end)); + info!("FrameAllocator init end"); - info!("mmu enabled"); + /* + * @param: + * start: start address + * end: end address + * @brief: + * transform the memory address to the page number + * @retval: + * the page number range from start address to end address + */ + fn to_range(start: usize, end: usize) -> Range { + let page_start = (start - MEMORY_OFFSET) / PAGE_SIZE; + let page_end = (end - MEMORY_OFFSET - 1) / PAGE_SIZE + 1; + page_start..page_end + } } +/// remap kernel page table after all initialization. fn remap_the_kernel() { let (bottom, top) = (0, bootstacktop as usize); let kstack = Stack { diff --git a/kernel/src/arch/aarch64/mod.rs b/kernel/src/arch/aarch64/mod.rs index 35613ab..ccd6230 100644 --- a/kernel/src/arch/aarch64/mod.rs +++ b/kernel/src/arch/aarch64/mod.rs @@ -17,9 +17,13 @@ pub use self::board::timer; /// The entry point of kernel #[no_mangle] // don't mangle the name of this function pub extern "C" fn rust_main() -> ! { + // Enable mmu and paging + memory::init_mmu_early(); + // Init board to enable serial port. board::init(); - ::logging::init(); // FIXME + + ::logging::init(); interrupt::init(); memory::init(); timer::init(); diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index a023237..c7c4e99 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -5,7 +5,7 @@ use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame}; use ucore_memory::memory_set::*; use ucore_memory::PAGE_SIZE; use ucore_memory::paging::*; -use aarch64::asm::{tlb_invalidate, ttbr0_el1_read, ttbr0_el1_write}; +use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, ttbr0_el1_read, ttbr0_el1_write}; use aarch64::{PhysAddr, VirtAddr}; use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB, Size2MiB}; @@ -123,9 +123,7 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) // } ttbr0_el1_write(frame_lvl4); - tlb_invalidate(); - - info!("setup init page table end"); + tlb_invalidate_all(); } /// map the range [start, end) as device memory, insert to the MemorySet @@ -222,7 +220,8 @@ impl ActivePageTable { impl Entry for PageEntry { fn update(&mut self) { - tlb_invalidate(); + let addr = VirtAddr::new_unchecked((self as *const _ as u64) << 9); + tlb_invalidate(addr); } fn present(&self) -> bool { self.0.flags().contains(EF::PRESENT) } @@ -314,14 +313,14 @@ impl InactivePageTable for InactivePageTable0 { // overwrite recursive mapping p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT); - tlb_invalidate(); + tlb_invalidate_all(); // execute f in the new context f(active_table); // restore recursive mapping to original p4 table p4_table[RECURSIVE_INDEX] = backup; - tlb_invalidate(); + tlb_invalidate_all(); }); } @@ -331,7 +330,7 @@ impl InactivePageTable for InactivePageTable0 { debug!("switch table {:?} -> {:?}", old_frame, new_frame); if old_frame != new_frame { ttbr0_el1_write(new_frame); - tlb_invalidate(); + tlb_invalidate_all(); } } @@ -341,13 +340,13 @@ impl InactivePageTable for InactivePageTable0 { debug!("switch table {:?} -> {:?}", old_frame, new_frame); if old_frame != new_frame { ttbr0_el1_write(new_frame); - tlb_invalidate(); + tlb_invalidate_all(); } f(); debug!("switch table {:?} -> {:?}", new_frame, old_frame); if old_frame != new_frame { ttbr0_el1_write(old_frame); - tlb_invalidate(); + tlb_invalidate_all(); } } From 55087fc5a2dbfc7d3ea9e6d15a1170f1548ff503 Mon Sep 17 00:00:00 2001 From: equation314 Date: Fri, 23 Nov 2018 00:43:18 +0800 Subject: [PATCH 06/16] aarch64/mmu: use both TTBR0_EL1 & TTBR1_EL1 --- crate/aarch64/src/addr.rs | 23 ++++ crate/aarch64/src/asm.rs | 36 +++-- crate/aarch64/src/paging/mod.rs | 5 + crate/aarch64/src/paging/recursive.rs | 16 +-- crate/aarch64/src/regs/mod.rs | 2 + crate/aarch64/src/regs/tcr_el1.rs | 135 +++++++++++++++++++ crate/aarch64/src/regs/ttbr0_el1.rs | 5 + crate/aarch64/src/regs/ttbr1_el1.rs | 61 +++++++++ kernel/src/arch/aarch64/interrupt/context.rs | 23 ++-- kernel/src/arch/aarch64/memory.rs | 31 +++-- kernel/src/arch/aarch64/paging.rs | 31 ++--- kernel/src/consts.rs | 2 +- kernel/src/process/context.rs | 4 + 13 files changed, 309 insertions(+), 65 deletions(-) create mode 100644 crate/aarch64/src/regs/ttbr1_el1.rs diff --git a/crate/aarch64/src/addr.rs b/crate/aarch64/src/addr.rs index e347567..cf3f092 100644 --- a/crate/aarch64/src/addr.rs +++ b/crate/aarch64/src/addr.rs @@ -6,6 +6,15 @@ use bit_field::BitField; use usize_conversions::FromUsize; use ux::*; +#[derive(Debug)] +#[repr(u8)] +pub enum VirtAddrRange { + /// 0x0000000000000000 to 0x0000FFFFFFFFFFFF + BottomRange = 0, + /// 0xFFFF000000000000 to 0xFFFFFFFFFFFFFFFF. + TopRange = 1, +} + #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] #[repr(transparent)] pub struct VirtAddr(u64); @@ -105,6 +114,20 @@ impl VirtAddr { u12::new((self.0 & 0xfff).try_into().unwrap()) } + /// Returns the VA range + pub fn va_range(&self) -> Result { + match self.va_range_bits() { + 0x0000 => Ok(VirtAddrRange::BottomRange), + 0xffff => Ok(VirtAddrRange::TopRange), + _ => Err(VirtAddrNotValid(self.0)), + } + } + + /// Returns the top 16 bits + pub fn va_range_bits(&self) -> u16 { + ((self.0 >> 48) & 0xffff) as u16 + } + /// Returns the 9-bit level 1 page table index. pub fn p1_index(&self) -> u9 { u9::new(((self.0 >> 12) & 0o777).try_into().unwrap()) diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs index 63ce23a..a5b16d5 100644 --- a/crate/aarch64/src/asm.rs +++ b/crate/aarch64/src/asm.rs @@ -160,24 +160,20 @@ pub fn eret() -> ! { } } -bitflags! { - /// Controls cache settings for the level 4 page table. - pub struct ttbr0_el1_Flags: u64 { - - const COMMON_NOT_PRIVATE = 1 << 0; - } -} - -pub fn ttbr0_el1_read() -> (PhysFrame, ttbr0_el1_Flags) { - let value = TTBR0_EL1.get(); - let flags = ttbr0_el1_Flags::from_bits_truncate(value); - let addr = PhysAddr::new(value & 0x_0000_ffff_ffff_f000); - let frame = PhysFrame::containing_address(addr); - (frame, flags) -} - -pub fn ttbr0_el1_write(frame: PhysFrame) { - let addr = frame.start_address(); - let value = addr.as_u64(); - TTBR0_EL1.set_baddr(value); +pub fn ttbr_el1_read(which: u8) -> (PhysFrame) { + let baddr = match which { + 0 => TTBR0_EL1.get_baddr(), + 1 => TTBR1_EL1.get_baddr(), + _ => 0, + }; + PhysFrame::containing_address(PhysAddr::new(baddr)) +} + +pub fn ttbr_el1_write(which: u8, frame: PhysFrame) { + let baddr = frame.start_address().as_u64(); + match which { + 0 => TTBR0_EL1.set_baddr(baddr), + 1 => TTBR1_EL1.set_baddr(baddr), + _ => {} + }; } diff --git a/crate/aarch64/src/paging/mod.rs b/crate/aarch64/src/paging/mod.rs index 855b876..c73d5b4 100644 --- a/crate/aarch64/src/paging/mod.rs +++ b/crate/aarch64/src/paging/mod.rs @@ -98,6 +98,11 @@ impl Page { S::SIZE } + /// Returns the level 4 page table index of this page. + pub fn va_range_bits(&self) -> u16 { + self.start_address().va_range_bits() + } + /// Returns the level 4 page table index of this page. pub fn p4_index(&self) -> u9 { self.start_address().p4_index() diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index 79b0a0d..ee61cba 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -7,7 +7,7 @@ use paging::{ NotGiantPageSize, Page, PageSize, PhysFrame, Size4KiB, }; use paging::page_table::PageTableFlags as Flags; -use asm::ttbr0_el1_read; +use asm::ttbr_el1_read; use ux::u9; use addr::{PhysAddr, VirtAddr}; @@ -162,7 +162,9 @@ impl<'a> RecursivePageTable<'a> { { return Err(NotRecursivelyMapped); } - if Ok(ttbr0_el1_read().0) != table[recursive_index].frame() { + if Ok(ttbr_el1_read(page.start_address().va_range().unwrap() as u8)) != + table[recursive_index].frame() + { return Err(NotRecursivelyMapped); } @@ -212,7 +214,6 @@ impl<'a> RecursivePageTable<'a> { where A: FrameAllocator, { - let created; if entry.is_unused() { @@ -281,7 +282,6 @@ impl<'a> RecursivePageTable<'a> { } } - impl<'a> Mapper for RecursivePageTable<'a> { fn map_to( &mut self, @@ -293,7 +293,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { where A: FrameAllocator, { - let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; let p4 = &mut self_mut.p4; let p3_page = self.p3_page(page); @@ -317,7 +317,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { &mut self, page: Page, ) -> Result<(PhysFrame, MapperFlush), UnmapError> { - let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; let p4 = &mut self_mut.p4; let p4_entry = &p4[page.p4_index()]; @@ -357,7 +357,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { page: Page, flags: PageTableFlags, ) -> Result, FlagUpdateError> { - let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; let p4 = &mut self_mut.p4; if p4[page.p4_index()].is_unused() { @@ -388,7 +388,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { } fn translate_page(&self, page: Page) -> Option> { - let self_mut = unsafe{ &mut *(self as *const _ as *mut Self) }; + let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; let p4 = &mut self_mut.p4; if p4[page.p4_index()].is_unused() { diff --git a/crate/aarch64/src/regs/mod.rs b/crate/aarch64/src/regs/mod.rs index f6a0e3d..5a7e556 100644 --- a/crate/aarch64/src/regs/mod.rs +++ b/crate/aarch64/src/regs/mod.rs @@ -24,6 +24,7 @@ mod spsel; mod spsr_el2; mod tcr_el1; mod ttbr0_el1; +mod ttbr1_el1; // Export only the R/W traits and the static reg definitions pub use register::cpu::*; @@ -49,3 +50,4 @@ pub use self::spsel::SPSel; pub use self::spsr_el2::SPSR_EL2; pub use self::tcr_el1::TCR_EL1; pub use self::ttbr0_el1::TTBR0_EL1; +pub use self::ttbr1_el1::TTBR1_EL1; diff --git a/crate/aarch64/src/regs/tcr_el1.rs b/crate/aarch64/src/regs/tcr_el1.rs index bcd0425..9ebb6d7 100644 --- a/crate/aarch64/src/regs/tcr_el1.rs +++ b/crate/aarch64/src/regs/tcr_el1.rs @@ -22,6 +22,17 @@ use register::cpu::RegisterReadWrite; register_bitfields! {u64, TCR_EL1 [ + /// Top Byte ignored - indicates whether the top byte of an address is + /// used for address match for the TTBR1_EL1 region, or ignored and used + /// for tagged addresses. Defined values are: + /// + /// 0 Top Byte used in the address calculation. + /// 1 Top Byte ignored in the address calculation. + TBI1 OFFSET(38) NUMBITS(1) [ + Used = 0, + Ignored = 1 + ], + /// Top Byte ignored - indicates whether the top byte of an address is /// used for address match for the TTBR0_EL1 region, or ignored and used /// for tagged addresses. Defined values are: @@ -33,6 +44,20 @@ register_bitfields! {u64, Ignored = 1 ], + /// ASID Size. Defined values are: + /// + /// 0 8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by + /// hardware for every purpose except reading back the register, and are + /// treated as if they are all zeros for when used for allocation and matching entries in the TLB. + /// 1 16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for + /// allocation and matching in the TLB. + /// + /// If the implementation has only 8 bits of ASID, this field is RES0. + AS OFFSET(36) NUMBITS(1) [ + Bits_8 = 0, + Bits_16 = 1 + ], + /// Intermediate Physical Address Size. /// /// 000 32 bits, 4GiB. @@ -67,6 +92,116 @@ register_bitfields! {u64, Bits_52 = 0b110 ], + /// Granule size for the TTBR1_EL1. + /// + /// 01 16KiB + /// 10 4KiB + /// 11 64KiB + /// + /// Other values are reserved. + /// + /// If the value is programmed to either a reserved value, or a size + /// that has not been implemented, then the hardware will treat the + /// field as if it has been programmed to an IMPLEMENTATION DEFINED + /// choice of the sizes that has been implemented for all purposes other + /// than the value read back from this register. + /// + /// It is IMPLEMENTATION DEFINED whether the value read back is the + /// value programmed or the value that corresponds to the size chosen. + TG1 OFFSET(30) NUMBITS(2) [ + KiB_4 = 0b10, + KiB_16 = 0b01, + KiB_64 = 0b11 + ], + + /// Shareability attribute for memory associated with translation table + /// walks using TTBR1_EL1. + /// + /// 00 Non-shareable + /// 10 Outer Shareable + /// 11 Inner Shareable + /// + /// Other values are reserved. + SH1 OFFSET(28) NUMBITS(2) [ + None = 0b00, + Outer = 0b10, + Inner = 0b11 + ], + + /// Outer cacheability attribute for memory associated with translation + /// table walks using TTBR1_EL1. + /// + /// 00 Normal memory, Outer Non-cacheable + /// + /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate + /// Cacheable + /// + /// 10 Normal memory, Outer Write-Through Read-Allocate No + /// Write-Allocate Cacheable + /// + /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate + /// Cacheable + ORGN1 OFFSET(26) NUMBITS(2) [ + NonCacheable = 0b00, + WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, + WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, + WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 + ], + + /// Inner cacheability attribute for memory associated with translation + /// table walks using TTBR1_EL1. + /// + /// 00 Normal memory, Inner Non-cacheable + /// + /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate + /// Cacheable + /// + /// 10 Normal memory, Inner Write-Through Read-Allocate No + /// Write-Allocate Cacheable + /// + /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate + /// Cacheable + IRGN1 OFFSET(24) NUMBITS(2) [ + NonCacheable = 0b00, + WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, + WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, + WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 + ], + + /// Translation table walk disable for translations using + /// TTBR1_EL1. This bit controls whether a translation table walk is + /// performed on a TLB miss, for an address that is translated using + /// TTBR1_EL1. The encoding of this bit is: + /// + /// 0 Perform translation table walks using TTBR1_EL1. + /// + /// 1 A TLB miss on an address that is translated using TTBR1_EL1 + /// generates a Translation fault. No translation table walk is + /// performed. + EPD1 OFFSET(23) NUMBITS(1) [ + EnableTTBR1Walks = 0, + DisableTTBR1Walks = 1 + ], + + /// Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding + /// of this bit is: + /// + /// 0 TTBR0_EL1.ASID defines the ASID. + /// + /// 1 TTBR1_EL1.ASID defines the ASID. + A1 OFFSET(22) NUMBITS(1) [ + UseTTBR0ASID = 0b0, + UseTTBR1ASID = 0b1 + ], + + /// The size offset of the memory region addressed by TTBR1_EL1. The + /// region size is 2^(64-T1SZ) bytes. + /// + /// The maximum and minimum possible values for T1SZ depend on the level + /// of translation table and the memory translation granule size, as + /// described in the AArch64 Virtual Memory System Architecture chapter. + T1SZ OFFSET(16) NUMBITS(6) [], + /// Granule size for the TTBR0_EL1. /// /// 00 4KiB diff --git a/crate/aarch64/src/regs/ttbr0_el1.rs b/crate/aarch64/src/regs/ttbr0_el1.rs index c111256..a29ff79 100644 --- a/crate/aarch64/src/regs/ttbr0_el1.rs +++ b/crate/aarch64/src/regs/ttbr0_el1.rs @@ -47,6 +47,11 @@ impl RegisterReadWrite for Reg { } impl Reg { + #[inline] + pub fn get_baddr(&self) -> u64 { + self.read(TTBR0_EL1::BADDR) << 1 + } + #[inline] pub fn set_baddr(&self, addr: u64) { self.write(TTBR0_EL1::BADDR.val(addr >> 1)); diff --git a/crate/aarch64/src/regs/ttbr1_el1.rs b/crate/aarch64/src/regs/ttbr1_el1.rs new file mode 100644 index 0000000..7df383c --- /dev/null +++ b/crate/aarch64/src/regs/ttbr1_el1.rs @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Translation Table Base Register 1 - EL1 +//! +//! Holds the base address of the translation table for the initial lookup for +//! stage 1 of the translation of an address from the upper VA range in the +//! EL1&0 translation regime, and other information for this translation regime. + +use register::cpu::RegisterReadWrite; + +register_bitfields! {u64, + TTBR1_EL1 [ + /// An ASID for the translation table base address. The TCR_EL1.A1 field + /// selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID. + /// + /// If the implementation has only 8 bits of ASID, then the upper 8 bits + /// of this field are RES 0. + ASID OFFSET(48) NUMBITS(16) [], + + /// Translation table base address + BADDR OFFSET(1) NUMBITS(47) [], + + /// Common not Private + CnP OFFSET(0) NUMBITS(1) [] + ] +} + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "TTBR1_EL1"); + sys_coproc_write_raw!(u64, "TTBR1_EL1"); +} + +impl Reg { + #[inline] + pub fn get_baddr(&self) -> u64 { + self.read(TTBR1_EL1::BADDR) << 1 + } + + #[inline] + pub fn set_baddr(&self, addr: u64) { + self.write(TTBR1_EL1::BADDR.val(addr >> 1)); + } +} + +pub static TTBR1_EL1: Reg = Reg {}; diff --git a/kernel/src/arch/aarch64/interrupt/context.rs b/kernel/src/arch/aarch64/interrupt/context.rs index df2b5b3..5bff366 100644 --- a/kernel/src/arch/aarch64/interrupt/context.rs +++ b/kernel/src/arch/aarch64/interrupt/context.rs @@ -63,12 +63,12 @@ extern { struct ContextData { x19to29: [usize; 11], lr: usize, - ttbr0: usize, + ttbr1: usize, } impl ContextData { - fn new(ttbr0: usize) -> Self { - ContextData { lr: __trapret as usize, ttbr0, ..ContextData::default() } + fn new(ttbr1: usize) -> Self { + ContextData { lr: __trapret as usize, ttbr1, ..ContextData::default() } } } @@ -98,7 +98,7 @@ impl Context { stp x25, x26, [x8], #16 stp x27, x28, [x8], #16 stp x29, lr, [x8], #16 - mrs x9, ttbr0_el1 + mrs x9, ttbr1_el1 str x9, [x8], #8 ldr x8, [x1] @@ -111,7 +111,8 @@ impl Context { ldr x9, [x8], #8 mov sp, x8 - msr ttbr0_el1, x9 // set new page directory + msr ttbr1_el1, x9 // set new page directory + // TODO: with ASID we needn't flush TLB dsb ishst // ensure write has completed tlbi vmalle1is // invalidate the TLB entry for the entry that changes dsb ish // ensure TLB invalidation is complete @@ -126,21 +127,21 @@ impl Context { Context(0) } - pub unsafe fn new_kernel_thread(entry: extern fn(usize) -> !, arg: usize, kstack_top: usize, ttbr0: usize) -> Self { + pub unsafe fn new_kernel_thread(entry: extern fn(usize) -> !, arg: usize, kstack_top: usize, ttbr: usize) -> Self { InitStack { - context: ContextData::new(ttbr0), + context: ContextData::new(ttbr), tf: TrapFrame::new_kernel_thread(entry, arg, kstack_top), }.push_at(kstack_top) } - pub unsafe fn new_user_thread(entry_addr: usize, ustack_top: usize, kstack_top: usize, is32: bool, ttbr0: usize) -> Self { + pub unsafe fn new_user_thread(entry_addr: usize, ustack_top: usize, kstack_top: usize, is32: bool, ttbr: usize) -> Self { InitStack { - context: ContextData::new(ttbr0), + context: ContextData::new(ttbr), // TODO: set ASID tf: TrapFrame::new_user_thread(entry_addr, ustack_top), }.push_at(kstack_top) } - pub unsafe fn new_fork(tf: &TrapFrame, kstack_top: usize, ttbr0: usize) -> Self { + pub unsafe fn new_fork(tf: &TrapFrame, kstack_top: usize, ttbr: usize) -> Self { InitStack { - context: ContextData::new(ttbr0), + context: ContextData::new(ttbr), // TODO: set ASID tf: { let mut tf = tf.clone(); tf.x0 = 0; diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index 3f93e31..1c486d2 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -38,14 +38,25 @@ pub fn init_mmu_early() { // Configure various settings of stage 1 of the EL1 translation regime. let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange); TCR_EL1.write( - TCR_EL1::TBI0::Ignored - + TCR_EL1::IPS.val(ips) - + TCR_EL1::TG0::KiB_4 // 4 KiB granule - + TCR_EL1::SH0::Inner - + TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable - + TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable - + TCR_EL1::EPD0::EnableTTBR0Walks - + TCR_EL1::T0SZ.val(16), // Start walks at level 2 + TCR_EL1::TBI1::Ignored + + TCR_EL1::TBI0::Ignored + + TCR_EL1::AS::Bits_16 + + TCR_EL1::IPS.val(ips) + + + TCR_EL1::TG1::KiB_4 + + TCR_EL1::SH1::Inner + + TCR_EL1::ORGN1::WriteBack_ReadAlloc_WriteAlloc_Cacheable + + TCR_EL1::IRGN1::WriteBack_ReadAlloc_WriteAlloc_Cacheable + + TCR_EL1::EPD1::EnableTTBR1Walks + + TCR_EL1::A1::UseTTBR1ASID + + TCR_EL1::T1SZ.val(16) + + + TCR_EL1::TG0::KiB_4 + + TCR_EL1::SH0::Inner + + TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable + + TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable + + TCR_EL1::EPD0::EnableTTBR0Walks + + TCR_EL1::T0SZ.val(16), ); // Switch the MMU on. @@ -63,7 +74,7 @@ pub fn init_mmu_early() { fn init_frame_allocator() { use bit_allocator::BitAlloc; use core::ops::Range; - use consts::{MEMORY_OFFSET}; + use consts::MEMORY_OFFSET; let (start, end) = memory_map().expect("failed to find memory map"); let mut ba = FRAME_ALLOCATOR.lock(); @@ -116,7 +127,7 @@ fn remap_the_kernel() { /// /// This function is expected to return `Some` under all normal cirumstances. fn memory_map() -> Option<(usize, usize)> { - let binary_end = unsafe { _end as u32 }; + let binary_end = _end as u32; let mut atags: Atags = Atags::get(); while let Some(atag) = atags.next() { diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index c7c4e99..09606a6 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -5,7 +5,7 @@ use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame}; use ucore_memory::memory_set::*; use ucore_memory::PAGE_SIZE; use ucore_memory::paging::*; -use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, ttbr0_el1_read, ttbr0_el1_write}; +use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, ttbr_el1_read, ttbr_el1_write}; use aarch64::{PhysAddr, VirtAddr}; use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB, Size2MiB}; @@ -122,7 +122,7 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) // } // } - ttbr0_el1_write(frame_lvl4); + ttbr_el1_write(0, frame_lvl4); tlb_invalidate_all(); } @@ -291,9 +291,9 @@ impl InactivePageTable for InactivePageTable0 { type Active = ActivePageTable; fn new() -> Self { - let mut pt = Self::new_bare(); - pt.map_kernel(); - pt + // When the new InactivePageTable is created for the user MemorySet, it's use ttbr1 as the + // TTBR. And the kernel TTBR ttbr0 will never changed, so we needn't call map_kernel() + Self::new_bare() } fn new_bare() -> Self { @@ -308,7 +308,7 @@ impl InactivePageTable for InactivePageTable0 { } fn edit(&mut self, f: impl FnOnce(&mut Self::Active)) { - active_table().with_temporary_map(&ttbr0_el1_read().0, |active_table, p4_table: &mut Aarch64PageTable| { + active_table().with_temporary_map(&ttbr_el1_read(0), |active_table, p4_table: &mut Aarch64PageTable| { let backup = p4_table[RECURSIVE_INDEX].clone(); // overwrite recursive mapping @@ -325,33 +325,34 @@ impl InactivePageTable for InactivePageTable0 { } unsafe fn activate(&self) { - let old_frame = ttbr0_el1_read().0; + let old_frame = ttbr_el1_read(0); let new_frame = self.p4_frame.clone(); - debug!("switch table {:?} -> {:?}", old_frame, new_frame); + debug!("switch TTBR0 {:?} -> {:?}", old_frame, new_frame); if old_frame != new_frame { - ttbr0_el1_write(new_frame); + ttbr_el1_write(0, new_frame); tlb_invalidate_all(); } } unsafe fn with(&self, f: impl FnOnce()) { - let old_frame = ttbr0_el1_read().0; + // Just need to switch the user TTBR + let old_frame = ttbr_el1_read(1); let new_frame = self.p4_frame.clone(); - debug!("switch table {:?} -> {:?}", old_frame, new_frame); + debug!("switch TTBR1 {:?} -> {:?}", old_frame, new_frame); if old_frame != new_frame { - ttbr0_el1_write(new_frame); + ttbr_el1_write(1, new_frame); tlb_invalidate_all(); } f(); - debug!("switch table {:?} -> {:?}", new_frame, old_frame); + debug!("switch TTBR1 {:?} -> {:?}", new_frame, old_frame); if old_frame != new_frame { - ttbr0_el1_write(old_frame); + ttbr_el1_write(1, old_frame); tlb_invalidate_all(); } } fn token(&self) -> usize { - self.p4_frame.start_address().as_u64() as usize // as CR3 + self.p4_frame.start_address().as_u64() as usize // as TTBRx_EL1 } fn alloc_frame() -> Option { diff --git a/kernel/src/consts.rs b/kernel/src/consts.rs index e879173..487b6a6 100644 --- a/kernel/src/consts.rs +++ b/kernel/src/consts.rs @@ -136,7 +136,7 @@ mod aarch64 { pub const KERNEL_PML4: usize = 0; pub const KERNEL_HEAP_SIZE: usize = 8 * 1024 * 1024; pub const MEMORY_OFFSET: usize = 0; - pub const USER_STACK_OFFSET: usize = 0x3000_0000; + pub const USER_STACK_OFFSET: usize = 0xffff_ffff_0000_0000; pub const USER_STACK_SIZE: usize = 1 * 1024 * 1024; pub const USER32_STACK_OFFSET: usize = USER_STACK_OFFSET; } diff --git a/kernel/src/process/context.rs b/kernel/src/process/context.rs index f20d209..088b1b8 100644 --- a/kernel/src/process/context.rs +++ b/kernel/src/process/context.rs @@ -142,6 +142,10 @@ fn memory_set_from<'a>(elf: &'a ElfFile<'a>) -> MemorySet { ProgramHeader::Ph32(ph) => (ph.virtual_addr as usize, ph.mem_size as usize, ph.flags), ProgramHeader::Ph64(ph) => (ph.virtual_addr as usize, ph.mem_size as usize, ph.flags), }; + + #[cfg(target_arch = "aarch64")] + assert_eq!((virt_addr >> 48), 0xffff, "Segment Fault"); + set.push(MemoryArea::new(virt_addr, virt_addr + mem_size, memory_attr_from(flags), "")); } set From 33d4b6975b54bdc77a14c1133cd6793cc976139e Mon Sep 17 00:00:00 2001 From: equation314 Date: Fri, 23 Nov 2018 15:23:00 +0800 Subject: [PATCH 07/16] aarch64/mmu: use DSB instead of TLB flush after modifying PTE --- crate/aarch64/src/barrier.rs | 4 ++++ crate/aarch64/src/paging/recursive.rs | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/crate/aarch64/src/barrier.rs b/crate/aarch64/src/barrier.rs index 0e48209..3211480 100644 --- a/crate/aarch64/src/barrier.rs +++ b/crate/aarch64/src/barrier.rs @@ -52,8 +52,12 @@ macro_rules! dmb_dsb { } pub struct SY; +pub struct ISH; +pub struct ISHST; dmb_dsb!(SY); +dmb_dsb!(ISH); +dmb_dsb!(ISHST); impl sealed::Isb for SY { #[inline(always)] diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index ee61cba..31039d5 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -1,13 +1,13 @@ #![cfg(target_arch = "aarch64")] -use asm::tlb_invalidate; use paging::{ frame_alloc::FrameAllocator, page_table::{FrameError, PageTable, PageTableEntry, PageTableFlags}, NotGiantPageSize, Page, PageSize, PhysFrame, Size4KiB, }; use paging::page_table::PageTableFlags as Flags; -use asm::ttbr_el1_read; +use asm::{ttbr_el1_read, tlb_invalidate}; +use barrier; use ux::u9; use addr::{PhysAddr, VirtAddr}; @@ -233,7 +233,7 @@ impl<'a> RecursivePageTable<'a> { let page_table_ptr = next_table_page.start_address().as_mut_ptr(); let page_table: &mut PageTable = unsafe { &mut *(page_table_ptr) }; if created { - tlb_invalidate(next_table_page.start_address()); + unsafe { barrier::dsb(barrier::ISHST); } page_table.zero(); } Ok(page_table) From de6354ddd338060726d6cce659b3b7796ed97146 Mon Sep 17 00:00:00 2001 From: equation314 Date: Fri, 23 Nov 2018 23:25:06 +0800 Subject: [PATCH 08/16] aarch64/mmu: use ASID to avoid flush TLB frequently in context switch --- crate/aarch64/src/asm.rs | 9 ++ kernel/src/arch/aarch64/interrupt/context.rs | 109 ++++++++++++++----- kernel/src/arch/aarch64/paging.rs | 10 +- 3 files changed, 92 insertions(+), 36 deletions(-) diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs index a5b16d5..1c1ee6d 100644 --- a/crate/aarch64/src/asm.rs +++ b/crate/aarch64/src/asm.rs @@ -177,3 +177,12 @@ pub fn ttbr_el1_write(which: u8, frame: PhysFrame) { _ => {} }; } + +pub fn ttbr_el1_write_asid(which: u8, asid: u16, frame: PhysFrame) { + let baddr = frame.start_address().as_u64(); + match which { + 0 => TTBR0_EL1.write(TTBR0_EL1::ASID.val(asid as u64) + TTBR0_EL1::BADDR.val(baddr >> 1)), + 1 => TTBR1_EL1.write(TTBR1_EL1::ASID.val(asid as u64) + TTBR1_EL1::BADDR.val(baddr >> 1)), + _ => {} + }; +} diff --git a/kernel/src/arch/aarch64/interrupt/context.rs b/kernel/src/arch/aarch64/interrupt/context.rs index 5bff366..fe93839 100644 --- a/kernel/src/arch/aarch64/interrupt/context.rs +++ b/kernel/src/arch/aarch64/interrupt/context.rs @@ -1,12 +1,20 @@ //! TrapFrame and context definitions for aarch64. +extern crate aarch64; + +use spin::{Mutex}; +use aarch64::barrier; +use aarch64::addr::PhysAddr; +use aarch64::paging::PhysFrame; +use aarch64::asm::{tlb_invalidate_all, ttbr_el1_write_asid}; + #[repr(C)] #[derive(Default, Debug, Copy, Clone)] pub struct TrapFrame { pub elr: usize, pub spsr: usize, pub sp: usize, - pub tpidr: usize, + pub tpidr: usize, // currently unused // pub q0to31: [u128; 32], // disable SIMD/FP registers pub x1to29: [usize; 29], pub __reserved: usize, @@ -47,10 +55,14 @@ pub struct InitStack { } impl InitStack { - unsafe fn push_at(self, stack_top: usize) -> Context { + unsafe fn push_at(self, stack_top: usize, ttbr: usize) -> Context { let ptr = (stack_top as *mut Self).offset(-1); *ptr = self; - Context(ptr as usize) + Context { + stack_top: ptr as usize, + ttbr: PhysFrame::containing_address(PhysAddr::new(ttbr as u64)), + asid: Asid::default(), + } } } @@ -63,18 +75,20 @@ extern { struct ContextData { x19to29: [usize; 11], lr: usize, - ttbr1: usize, } impl ContextData { - fn new(ttbr1: usize) -> Self { - ContextData { lr: __trapret as usize, ttbr1, ..ContextData::default() } + fn new() -> Self { + ContextData { lr: __trapret as usize, ..ContextData::default() } } } - #[derive(Debug)] -pub struct Context(usize); +pub struct Context { + stack_top: usize, + ttbr: PhysFrame, + asid: Asid, +} impl Context { /// Switch to another kernel thread. @@ -86,10 +100,10 @@ impl Context { /// Pop all callee-saved registers, then return to the target. #[naked] #[inline(never)] - pub unsafe extern fn switch(&mut self, target: &mut Self) { + unsafe extern fn __switch(self_stack: &mut usize, target_stack: &mut usize) { asm!( " - mov x10, #-(13 * 8) + mov x10, #-(12 * 8) add x8, sp, x10 str x8, [x0] stp x19, x20, [x8], #16 // store callee-saved registers @@ -98,8 +112,6 @@ impl Context { stp x25, x26, [x8], #16 stp x27, x28, [x8], #16 stp x29, lr, [x8], #16 - mrs x9, ttbr1_el1 - str x9, [x8], #8 ldr x8, [x1] ldp x19, x20, [x8], #16 // restore callee-saved registers @@ -108,45 +120,88 @@ impl Context { ldp x25, x26, [x8], #16 ldp x27, x28, [x8], #16 ldp x29, lr, [x8], #16 - ldr x9, [x8], #8 mov sp, x8 - msr ttbr1_el1, x9 // set new page directory - // TODO: with ASID we needn't flush TLB - dsb ishst // ensure write has completed - tlbi vmalle1is // invalidate the TLB entry for the entry that changes - dsb ish // ensure TLB invalidation is complete - isb // synchronize context on this processor - str xzr, [x1] ret" : : : : "volatile" ); } + pub unsafe fn switch(&mut self, target: &mut Self) { + target.asid = ASID_ALLOCATOR.lock().alloc(target.asid); + + // with ASID we needn't flush TLB frequently + ttbr_el1_write_asid(1, target.asid.value, target.ttbr); + barrier::dsb(barrier::ISH); + Self::__switch(&mut self.stack_top, &mut target.stack_top); + } + pub unsafe fn null() -> Self { - Context(0) + Context { + stack_top: 0, + ttbr: PhysFrame::containing_address(PhysAddr::new(0)), + asid: Asid::default(), + } } pub unsafe fn new_kernel_thread(entry: extern fn(usize) -> !, arg: usize, kstack_top: usize, ttbr: usize) -> Self { InitStack { - context: ContextData::new(ttbr), + context: ContextData::new(), tf: TrapFrame::new_kernel_thread(entry, arg, kstack_top), - }.push_at(kstack_top) + }.push_at(kstack_top, ttbr) } pub unsafe fn new_user_thread(entry_addr: usize, ustack_top: usize, kstack_top: usize, is32: bool, ttbr: usize) -> Self { InitStack { - context: ContextData::new(ttbr), // TODO: set ASID + context: ContextData::new(), tf: TrapFrame::new_user_thread(entry_addr, ustack_top), - }.push_at(kstack_top) + }.push_at(kstack_top, ttbr) } pub unsafe fn new_fork(tf: &TrapFrame, kstack_top: usize, ttbr: usize) -> Self { InitStack { - context: ContextData::new(ttbr), // TODO: set ASID + context: ContextData::new(), tf: { let mut tf = tf.clone(); tf.x0 = 0; tf }, - }.push_at(kstack_top) + }.push_at(kstack_top, ttbr) } } + +const ASID_MASK: u16 = 0xffff; + +#[derive(Debug, Copy, Clone, Default)] +#[repr(C)] +struct Asid { + value: u16, + generation: u16, +} + +struct AsidAllocator(Asid); + +impl AsidAllocator { + fn new() -> Self { + AsidAllocator(Asid { value: 0, generation: 1 }) + } + + fn alloc(&mut self, old_asid: Asid) -> Asid { + if self.0.generation == old_asid.generation { + return old_asid; + } + + if self.0.value == ASID_MASK { + self.0.value = 0; + self.0.generation = self.0.generation.wrapping_add(1); + if self.0.generation == 0 { + self.0.generation += 1; + } + tlb_invalidate_all(); + } + self.0.value += 1; + return self.0; + } +} + +lazy_static! { + static ref ASID_ALLOCATOR: Mutex = Mutex::new(AsidAllocator::new()); +} diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index 09606a6..f1df051 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -259,15 +259,7 @@ impl Entry for PageEntry { fn set_swapped(&mut self, value: bool) { self.as_flags().set(EF::SWAPPED, value); } fn set_user(&mut self, value: bool) { self.as_flags().set(EF::USER_ACCESSIBLE, value); - if value { - let mut addr = self as *const _ as usize; - for _ in 0..3 { - // Upper level entry - addr = ((addr >> 9) & 0o777_777_777_7770) | (RECURSIVE_INDEX << 39); - // set USER_ACCESSIBLE - unsafe { (*(addr as *mut EF)).insert(EF::USER_ACCESSIBLE) }; - } - } + self.as_flags().set(EF::NONE_GLOBAL, value); // set non-global to use ASID } fn execute(&self) -> bool { !self.0.flags().contains(EF::UXN) } fn set_execute(&mut self, value: bool) { self.as_flags().set(EF::UXN, !value); } From f9e47b2fd8f142cbbbb4bd98f826a85149ff96ef Mon Sep 17 00:00:00 2001 From: equation314 Date: Sun, 25 Nov 2018 00:29:39 +0800 Subject: [PATCH 09/16] aarch64/mmu: refactor PageTableFlags --- crate/aarch64/src/paging/page_table.rs | 172 ++++++++++++++++++------- crate/aarch64/src/paging/recursive.rs | 7 +- kernel/src/arch/aarch64/paging.rs | 57 ++++---- kernel/src/consts.rs | 2 +- 4 files changed, 163 insertions(+), 75 deletions(-) diff --git a/crate/aarch64/src/paging/page_table.rs b/crate/aarch64/src/paging/page_table.rs index c06123e..2047e6b 100644 --- a/crate/aarch64/src/paging/page_table.rs +++ b/crate/aarch64/src/paging/page_table.rs @@ -1,12 +1,27 @@ use core::fmt; use core::ops::{Index, IndexMut}; -use super::{PageSize, PhysFrame, Size4KiB}; +use super::PhysFrame; use addr::PhysAddr; use usize_conversions::usize_from; use ux::*; +use register::FieldValue; +use register::cpu::RegisterReadWrite; + +/// Memory attribute fields mask +const MEMORY_ATTR_MASK: u64 = (MEMORY_ATTRIBUTE::SH.mask << MEMORY_ATTRIBUTE::SH.shift) + | (MEMORY_ATTRIBUTE::AttrIndx.mask << MEMORY_ATTRIBUTE::AttrIndx.shift); +/// Output address mask +const ADDR_MASK: u64 = 0x0000_ffff_ffff_f000; +/// Other flags mask +const FLAGS_MASK: u64 = !(MEMORY_ATTR_MASK | ADDR_MASK); + +/// Memory attribute fields +type PageTableAttributeFieldValue = FieldValue; +pub struct PageTableAttribute(PageTableAttributeFieldValue); + /// The error returned by the `PageTableEntry::frame` method. #[derive(Debug, Clone, Copy, PartialEq)] pub enum FrameError { @@ -24,6 +39,18 @@ pub struct PageTableEntry { pub entry: u64, } +impl RegisterReadWrite for PageTableEntry { + #[inline] + fn get(&self) -> u64 { + self.entry + } + + #[inline] + fn set(&self, value: u64) { + unsafe { *(&self.entry as *const u64 as *mut u64) = value } + } +} + impl PageTableEntry { /// Returns whether this entry is zero. pub fn is_unused(&self) -> bool { @@ -42,7 +69,16 @@ impl PageTableEntry { /// Returns the physical address mapped by this entry, might be zero. pub fn addr(&self) -> PhysAddr { - PhysAddr::new(self.entry & 0x0000_ffff_ffff_f000) + PhysAddr::new(self.entry & ADDR_MASK) + } + + /// Returns the memory attribute fields of this entry. + pub fn attr(&self) -> PageTableAttribute { + PageTableAttribute(PageTableAttributeFieldValue::new( + MEMORY_ATTR_MASK, + 0, + self.entry & MEMORY_ATTR_MASK, + )) } /// Returns the physical frame mapped by this entry. @@ -53,30 +89,36 @@ impl PageTableEntry { /// - `FrameError::HugeFrame` if the entry has the `HUGE_PAGE` flag set (for huge pages the /// `addr` function must be used) pub fn frame(&self) -> Result { - if !self.flags().contains(PageTableFlags::PRESENT) { + if !self.flags().contains(PageTableFlags::VALID) { Err(FrameError::FrameNotPresent) - } else if self.flags().contains(PageTableFlags::HUGE_PAGE) { + } else if !self.flags().contains(PageTableFlags::TABLE_OR_PAGE) { + // is a huge page (block) Err(FrameError::HugeFrame) } else { Ok(PhysFrame::containing_address(self.addr())) } } + /// Map the entry to the specified physical frame with the specified flags. + pub fn set_frame(&mut self, frame: PhysFrame, flags: PageTableFlags) { + // is not a huge page (block) + assert!(flags.contains(PageTableFlags::TABLE_OR_PAGE)); + self.set(frame.start_address().as_u64() | flags.bits()); + } + /// Map the entry to the specified physical address with the specified flags. - pub fn set_addr(&mut self, addr: PhysAddr, flags: PageTableFlags) { - assert!(addr.is_aligned(Size4KiB::SIZE)); - self.entry = (addr.as_u64()) | flags.bits(); + pub fn modify_addr(&mut self, addr: PhysAddr) { + self.entry = (self.entry & !ADDR_MASK) | addr.as_u64(); } - /// Map the entry to the specified physical frame with the specified flags. - pub fn set_frame(&mut self, frame: PhysFrame, flags: PageTableFlags) { - assert!(!flags.contains(PageTableFlags::HUGE_PAGE)); - self.set_addr(frame.start_address(), flags) + /// Sets the flags of this entry. + pub fn modify_flags(&mut self, flags: PageTableFlags) { + self.entry = (self.entry & !FLAGS_MASK) | flags.bits(); } /// Sets the flags of this entry. - pub fn set_flags(&mut self, flags: PageTableFlags) { - self.entry = self.addr().as_u64() | flags.bits(); + pub fn modify_attr(&mut self, attr: PageTableAttribute) { + self.entry = (self.entry & !MEMORY_ATTR_MASK) | attr.0.value; } } @@ -90,42 +132,78 @@ impl fmt::Debug for PageTableEntry { } } +register_bitfields! {u64, + // Memory attribute fields in the VMSAv8-64 translation table format descriptors (Page 2148~2152) + MEMORY_ATTRIBUTE [ + /// Shareability field + SH OFFSET(8) NUMBITS(2) [ + NonShareable = 0b00, + OuterShareable = 0b10, + InnerShareable = 0b11 + ], + + /// Memory attributes index into the MAIR_EL1 register + AttrIndx OFFSET(2) NUMBITS(3) [] + ] +} + bitflags! { /// Possible flags for a page table entry. pub struct PageTableFlags: u64 { - const ALL = 0xffffffff_ffffffff; - const TYPE_MASK = 3 << 0; - // const TYPE_FAULT = 0 << 0; - const TYPE_PAGE = 3 << 0; - const TABLE_BIT = 1 << 1; - // const BLOCK_BIT = 0 << 1; - const PAGE_BIT = 1 << 1; - - const PRESENT = 1 << 0; - const USER_ACCESSIBLE = 1 << 6; /* AP[1] */ - const RDONLY = 1 << 7; /* AP[2] */ - const SHARED = 3 << 8; /* SH[1:0], inner shareable */ - const BIT_8 = 1 << 8; - const BIT_9 = 1 << 9; + // const SHARED = 3 << 8; /* SH[1:0], inner shareable */ + // const BIT_8 = 1 << 8; + // const BIT_9 = 1 << 9; // pub const ATTRIB_SH_NON_SHAREABLE: usize = 0x0 << 8; - const OUTER_SHAREABLE = 0b10 << 8; - const INNER_SHAREABLE = 0b11 << 8; - - const ACCESSED = 1 << 10; /* AF, Access Flag */ - const NONE_GLOBAL = 1 << 11; /* None Global */ - const GLOBAL = (!(1 << 11)); - const DBM = 1 << 51; /* Dirty Bit Management */ - const WRITE = 1 << 51; /* DBM */ - const CONT = 1 << 52; /* Contiguous range */ - const PXN = 1 << 53; /* Privileged XN */ - const UXN = 1 << 54; /* User XN */ - const HYP_XN = 1 << 54; /* HYP XN */ + // const OUTER_SHAREABLE = 0b10 << 8; + // const INNER_SHAREABLE = 0b11 << 8; + + /// identifies whether the descriptor is valid + const VALID = 1 << 0; + /// the descriptor type + /// 0, Block + /// 1, Table/Page + const TABLE_OR_PAGE = 1 << 1; + /// Access permission: accessable at EL0 + const AP_EL0 = 1 << 6; + /// Access permission: read-only + const AP_RO = 1 << 7; + /// Access flag + const AF = 1 << 10; + /// not global bit + const nG = 1 << 11; + /// Dirty Bit Modifier + const DBM = 1 << 51; + + /// A hint bit indicating that the translation table entry is one of a contiguous set or + /// entries + const Contiguous = 1 << 52; + /// Privileged Execute-never + const PXN = 1 << 53; + /// Execute-never/Unprivileged execute-never + const XN = 1 << 54; + + /// Software Dirty Bit Modifier + const WRITE = 1 << 51; + /// Software dirty bit const DIRTY = 1 << 55; + /// Software swapped bit const SWAPPED = 1 << 56; - const HUGE_PAGE = 1 << 57; - const PROT_NONE = 1 << 58; + /// Software writable shared bit for COW + const WRITABLE_SHARED = 1 << 57; + /// Software readonly shared bit for COW + const READONLY_SHARED = 1 << 58; + + /// Privileged Execute-never for table descriptors + const PXNTable = 1 << 59; + /// Execute-never/Unprivileged execute-never for table descriptors + const XNTable = 1 << 60; + } +} +impl Default for PageTableFlags { + fn default() -> Self { + Self::VALID | Self::TABLE_OR_PAGE | Self::AF | Self::WRITE | Self::PXN | Self::XN } } @@ -151,12 +229,12 @@ impl PageTable { } } - /// Setup identity map: VirtPage at pagenumber -> PhysFrame at pagenumber - /// pn: pagenumber = addr>>12 in riscv32. - pub fn map_identity(&mut self, p4num: usize, flags: PageTableFlags) { - let entry = self.entries[p4num].clone(); - self.entries[p4num].set_addr(entry.addr(), flags); - } + // Setup identity map: VirtPage at pagenumber -> PhysFrame at pagenumber + // pn: pagenumber = addr>>12 in riscv32. + // pub fn map_identity(&mut self, p4num: usize, flags: PageTableFlags) { + // let entry = self.entries[p4num].clone(); + // self.entries[p4num].set_addr(entry.addr(), flags); + // } } impl Index for PageTable { diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index 31039d5..e878f98 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -218,7 +218,7 @@ impl<'a> RecursivePageTable<'a> { if entry.is_unused() { if let Some(frame) = allocator.alloc() { - entry.set_frame(frame, Flags::PRESENT | Flags::WRITE | Flags::ACCESSED | Flags::PAGE_BIT); + entry.set_frame(frame, Flags::default()); created = true; } else { return Err(MapToError::FrameAllocationFailed); @@ -226,7 +226,8 @@ impl<'a> RecursivePageTable<'a> { } else { created = false; } - if entry.flags().contains(Flags::HUGE_PAGE) { + // is a huge page (block) + if !entry.flags().contains(Flags::TABLE_OR_PAGE) { return Err(MapToError::ParentEntryHugePage); } @@ -382,7 +383,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { return Err(FlagUpdateError::PageNotMapped); } - p1[page.p1_index()].set_flags(flags); + p1[page.p1_index()].modify_flags(flags); Ok(MapperFlush::new(page)) } diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index f1df051..9986faa 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -8,7 +8,7 @@ use ucore_memory::paging::*; use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, ttbr_el1_read, ttbr_el1_write}; use aarch64::{PhysAddr, VirtAddr}; use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; -use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB, Size2MiB}; +use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PhysFrame as Frame, Size4KiB, Size2MiB}; register_bitfields! {u64, // AArch64 Reference Manual page 2150 @@ -167,7 +167,7 @@ impl PageTable for ActivePageTable { type Entry = PageEntry; fn map(&mut self, addr: usize, target: usize) -> &mut PageEntry { - let flags = EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::UXN | EF::PAGE_BIT; + let flags = EF::default(); self.0.map_to(Page::of_addr(addr), Frame::of_addr(target), flags, &mut FrameAllocatorForAarch64) .unwrap().flush(); self.get_entry(addr) @@ -224,49 +224,58 @@ impl Entry for PageEntry { tlb_invalidate(addr); } - fn present(&self) -> bool { self.0.flags().contains(EF::PRESENT) } - fn accessed(&self) -> bool { self.0.flags().contains(EF::ACCESSED) } + fn present(&self) -> bool { self.0.flags().contains(EF::VALID) } + fn accessed(&self) -> bool { self.0.flags().contains(EF::AF) } fn writable(&self) -> bool { self.0.flags().contains(EF::WRITE) } fn dirty(&self) -> bool { self.hw_dirty() && self.sw_dirty() } - fn clear_accessed(&mut self) { self.as_flags().remove(EF::ACCESSED); } + fn clear_accessed(&mut self) { self.as_flags().remove(EF::AF); } fn clear_dirty(&mut self) { self.as_flags().remove(EF::DIRTY); - self.as_flags().insert(EF::RDONLY); + self.as_flags().insert(EF::AP_RO); } fn set_writable(&mut self, value: bool) { - self.as_flags().set(EF::RDONLY, !value); + self.as_flags().set(EF::AP_RO, !value); self.as_flags().set(EF::WRITE, value); } - fn set_present(&mut self, value: bool) { self.as_flags().set(EF::PRESENT, value); } + fn set_present(&mut self, value: bool) { self.as_flags().set(EF::VALID, value); } fn target(&self) -> usize { self.0.addr().as_u64() as usize } fn set_target(&mut self, target: usize) { - let flags = self.0.flags(); - self.0.set_addr(PhysAddr::new(target as u64), flags); + self.0.modify_addr(PhysAddr::new(target as u64)); } - fn writable_shared(&self) -> bool { self.0.flags().contains(EF::BIT_9) } - fn readonly_shared(&self) -> bool { self.0.flags().contains(EF::BIT_9) } + fn writable_shared(&self) -> bool { self.0.flags().contains(EF::WRITABLE_SHARED) } + fn readonly_shared(&self) -> bool { self.0.flags().contains(EF::READONLY_SHARED) } fn set_shared(&mut self, writable: bool) { let flags = self.as_flags(); - flags.set(EF::BIT_8, writable); - flags.set(EF::BIT_9, writable); + flags.set(EF::WRITABLE_SHARED, writable); + flags.set(EF::READONLY_SHARED, !writable); } - fn clear_shared(&mut self) { self.as_flags().remove(EF::BIT_8 | EF::BIT_9); } - fn user(&self) -> bool { self.0.flags().contains(EF::USER_ACCESSIBLE) } + fn clear_shared(&mut self) { self.as_flags().remove(EF::WRITABLE_SHARED | EF::READONLY_SHARED); } + fn user(&self) -> bool { self.0.flags().contains(EF::AP_EL0) } fn swapped(&self) -> bool { self.0.flags().contains(EF::SWAPPED) } fn set_swapped(&mut self, value: bool) { self.as_flags().set(EF::SWAPPED, value); } fn set_user(&mut self, value: bool) { - self.as_flags().set(EF::USER_ACCESSIBLE, value); - self.as_flags().set(EF::NONE_GLOBAL, value); // set non-global to use ASID + self.as_flags().set(EF::AP_EL0, value); + self.as_flags().set(EF::nG, value); // set non-global to use ASID + } + fn execute(&self) -> bool { + match self.user() { + true => !self.0.flags().contains(EF::XN), + false => !self.0.flags().contains(EF::PXN), + } + } + fn set_execute(&mut self, value: bool) { + match self.user() { + true => self.as_flags().set(EF::XN, !value), + false => self.as_flags().set(EF::PXN, !value), + } } - fn execute(&self) -> bool { !self.0.flags().contains(EF::UXN) } - fn set_execute(&mut self, value: bool) { self.as_flags().set(EF::UXN, !value); } } impl PageEntry { - fn read_only(&self) -> bool { self.0.flags().contains(EF::RDONLY) } + fn read_only(&self) -> bool { self.0.flags().contains(EF::AP_RO) } fn hw_dirty(&self) -> bool { self.writable() && !self.read_only() } fn sw_dirty(&self) -> bool { self.0.flags().contains(EF::DIRTY) } fn as_flags(&mut self) -> &mut EF { @@ -294,7 +303,7 @@ impl InactivePageTable for InactivePageTable0 { active_table().with_temporary_map(&frame, |_, table: &mut Aarch64PageTable| { table.zero(); // set up recursive mapping for the table - table[RECURSIVE_INDEX].set_frame(frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT); + table[RECURSIVE_INDEX].set_frame(frame.clone(), EF::default()); }); InactivePageTable0 { p4_frame: frame } } @@ -304,7 +313,7 @@ impl InactivePageTable for InactivePageTable0 { let backup = p4_table[RECURSIVE_INDEX].clone(); // overwrite recursive mapping - p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT); + p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::default()); tlb_invalidate_all(); // execute f in the new context @@ -367,7 +376,7 @@ impl InactivePageTable0 { assert!(!e0.is_unused()); self.edit(|_| { - table[KERNEL_PML4].set_addr(e0.addr(), e0.flags() & EF::GLOBAL); + table[KERNEL_PML4].set_frame(Frame::containing_address(e0.addr()), EF::default()); }); } } diff --git a/kernel/src/consts.rs b/kernel/src/consts.rs index 487b6a6..b2be26c 100644 --- a/kernel/src/consts.rs +++ b/kernel/src/consts.rs @@ -136,7 +136,7 @@ mod aarch64 { pub const KERNEL_PML4: usize = 0; pub const KERNEL_HEAP_SIZE: usize = 8 * 1024 * 1024; pub const MEMORY_OFFSET: usize = 0; - pub const USER_STACK_OFFSET: usize = 0xffff_ffff_0000_0000; + pub const USER_STACK_OFFSET: usize = 0xffff_8000_0000_0000; pub const USER_STACK_SIZE: usize = 1 * 1024 * 1024; pub const USER32_STACK_OFFSET: usize = USER_STACK_OFFSET; } From a8b334123adf8f3b56e097efbfde194c70e8d499 Mon Sep 17 00:00:00 2001 From: equation314 Date: Sun, 25 Nov 2018 17:58:17 +0800 Subject: [PATCH 10/16] aarch64/mmu: add memory region attribute config --- crate/aarch64/src/paging/memory_attribute.rs | 64 ++++++++++ crate/aarch64/src/paging/mod.rs | 6 + crate/aarch64/src/paging/page_table.rs | 51 ++++---- crate/aarch64/src/paging/recursive.rs | 11 +- crate/aarch64/src/regs/mair_el1.rs | 67 ++++------- crate/aarch64/src/regs/mod.rs | 2 +- kernel/src/arch/aarch64/board/raspi3/mod.rs | 2 + kernel/src/arch/aarch64/memory.rs | 13 +- kernel/src/arch/aarch64/paging.rs | 119 ++++--------------- 9 files changed, 155 insertions(+), 180 deletions(-) create mode 100644 crate/aarch64/src/paging/memory_attribute.rs diff --git a/crate/aarch64/src/paging/memory_attribute.rs b/crate/aarch64/src/paging/memory_attribute.rs new file mode 100644 index 0000000..beb9b69 --- /dev/null +++ b/crate/aarch64/src/paging/memory_attribute.rs @@ -0,0 +1,64 @@ +//!Memory region attributes (D4.5, page 2174) + +use super::{PageTableAttribute, MEMORY_ATTRIBUTE}; +use regs::*; + +pub trait MairType { + const INDEX: u64; + + #[inline] + fn config_value() -> u64; + + #[inline] + fn attr_value() -> PageTableAttribute; +} + +pub enum MairDevice {} +pub enum MairNormal {} +pub enum MairNormalNonCacheable {} + +impl MairType for MairDevice { + const INDEX: u64 = 0; + + #[inline] + fn config_value() -> u64 { + (MAIR_ATTR::Attr_HIGH::Device + MAIR_ATTR::Attr_LOW_DEVICE::Device_nGnRE).value + } + + #[inline] + fn attr_value() -> PageTableAttribute { + MEMORY_ATTRIBUTE::SH::OuterShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) + } +} + +impl MairType for MairNormal { + const INDEX: u64 = 1; + + #[inline] + fn config_value() -> u64 { + (MAIR_ATTR::Attr_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc + + MAIR_ATTR::Attr_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc) + .value + } + + #[inline] + fn attr_value() -> PageTableAttribute { + MEMORY_ATTRIBUTE::SH::InnerShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) + } +} + +impl MairType for MairNormalNonCacheable { + const INDEX: u64 = 2; + + #[inline] + fn config_value() -> u64 { + (MAIR_ATTR::Attr_HIGH::Memory_OuterNonCacheable + + MAIR_ATTR::Attr_LOW_MEMORY::InnerNonCacheable) + .value + } + + #[inline] + fn attr_value() -> PageTableAttribute { + MEMORY_ATTRIBUTE::SH::NonShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) + } +} diff --git a/crate/aarch64/src/paging/mod.rs b/crate/aarch64/src/paging/mod.rs index c73d5b4..552d6f6 100644 --- a/crate/aarch64/src/paging/mod.rs +++ b/crate/aarch64/src/paging/mod.rs @@ -18,6 +18,8 @@ mod frame_alloc; mod page_table; mod recursive; +pub mod memory_attribute; + /// Trait for abstracting over the three possible block/page sizes on aarch64, 4KiB, 2MiB, 1GiB. pub trait PageSize: Copy + Eq + PartialOrd + Ord { /// The page size in bytes. @@ -366,6 +368,10 @@ impl PhysFrame { pub fn of_addr(address: usize) -> Self { Self::containing_address(PhysAddr::new(address as u64)) } + + pub fn range_of(begin: usize, end: usize) -> PhysFrameRange { + Self::range(Self::of_addr(begin), Self::of_addr(end - 1) + 1) + } } impl fmt::Debug for PhysFrame { diff --git a/crate/aarch64/src/paging/page_table.rs b/crate/aarch64/src/paging/page_table.rs index 2047e6b..6d33fa6 100644 --- a/crate/aarch64/src/paging/page_table.rs +++ b/crate/aarch64/src/paging/page_table.rs @@ -1,7 +1,7 @@ use core::fmt; use core::ops::{Index, IndexMut}; -use super::PhysFrame; +use super::{PhysFrame, PageSize}; use addr::PhysAddr; use usize_conversions::usize_from; @@ -19,8 +19,7 @@ const ADDR_MASK: u64 = 0x0000_ffff_ffff_f000; const FLAGS_MASK: u64 = !(MEMORY_ATTR_MASK | ADDR_MASK); /// Memory attribute fields -type PageTableAttributeFieldValue = FieldValue; -pub struct PageTableAttribute(PageTableAttributeFieldValue); +pub type PageTableAttribute = FieldValue; /// The error returned by the `PageTableEntry::frame` method. #[derive(Debug, Clone, Copy, PartialEq)] @@ -53,32 +52,33 @@ impl RegisterReadWrite for PageTableEntry { impl PageTableEntry { /// Returns whether this entry is zero. + #[inline] pub fn is_unused(&self) -> bool { self.entry == 0 } /// Sets this entry to zero. + #[inline] pub fn set_unused(&mut self) { self.entry = 0; } /// Returns the flags of this entry. + #[inline] pub fn flags(&self) -> PageTableFlags { PageTableFlags::from_bits_truncate(self.entry) } /// Returns the physical address mapped by this entry, might be zero. + #[inline] pub fn addr(&self) -> PhysAddr { PhysAddr::new(self.entry & ADDR_MASK) } /// Returns the memory attribute fields of this entry. + #[inline] pub fn attr(&self) -> PageTableAttribute { - PageTableAttribute(PageTableAttributeFieldValue::new( - MEMORY_ATTR_MASK, - 0, - self.entry & MEMORY_ATTR_MASK, - )) + PageTableAttribute::new(MEMORY_ATTR_MASK, 0, self.entry & MEMORY_ATTR_MASK) } /// Returns the physical frame mapped by this entry. @@ -99,11 +99,19 @@ impl PageTableEntry { } } - /// Map the entry to the specified physical frame with the specified flags. - pub fn set_frame(&mut self, frame: PhysFrame, flags: PageTableFlags) { - // is not a huge page (block) + /// Map the entry to the specified physical frame with the specified flags and memory attribute. + pub fn set_frame(&mut self, frame: PhysFrame, flags: PageTableFlags, attr: PageTableAttribute) { + // is not a block assert!(flags.contains(PageTableFlags::TABLE_OR_PAGE)); - self.set(frame.start_address().as_u64() | flags.bits()); + self.set(frame.start_address().as_u64() | flags.bits() | attr.value); + } + + /// The descriptor gives the base address of a block of memory, and the attributes for that + /// memory region. + pub fn set_block(&mut self, addr: PhysAddr, flags: PageTableFlags, attr: PageTableAttribute) { + // is a block + assert!(!flags.contains(PageTableFlags::TABLE_OR_PAGE)); + self.set(addr.align_down(S::SIZE).as_u64() | flags.bits() | attr.value); } /// Map the entry to the specified physical address with the specified flags. @@ -118,7 +126,7 @@ impl PageTableEntry { /// Sets the flags of this entry. pub fn modify_attr(&mut self, attr: PageTableAttribute) { - self.entry = (self.entry & !MEMORY_ATTR_MASK) | attr.0.value; + self.entry = (self.entry & !MEMORY_ATTR_MASK) | attr.value; } } @@ -128,6 +136,7 @@ impl fmt::Debug for PageTableEntry { f.field("value", &self.entry); f.field("addr", &self.addr()); f.field("flags", &self.flags()); + f.field("attr", &self.attr().value); f.finish() } } @@ -150,14 +159,6 @@ register_bitfields! {u64, bitflags! { /// Possible flags for a page table entry. pub struct PageTableFlags: u64 { - // const SHARED = 3 << 8; /* SH[1:0], inner shareable */ - // const BIT_8 = 1 << 8; - // const BIT_9 = 1 << 9; - - // pub const ATTRIB_SH_NON_SHAREABLE: usize = 0x0 << 8; - // const OUTER_SHAREABLE = 0b10 << 8; - // const INNER_SHAREABLE = 0b11 << 8; - /// identifies whether the descriptor is valid const VALID = 1 << 0; /// the descriptor type @@ -202,6 +203,7 @@ bitflags! { } impl Default for PageTableFlags { + #[inline] fn default() -> Self { Self::VALID | Self::TABLE_OR_PAGE | Self::AF | Self::WRITE | Self::PXN | Self::XN } @@ -228,13 +230,6 @@ impl PageTable { entry.set_unused(); } } - - // Setup identity map: VirtPage at pagenumber -> PhysFrame at pagenumber - // pn: pagenumber = addr>>12 in riscv32. - // pub fn map_identity(&mut self, p4num: usize, flags: PageTableFlags) { - // let entry = self.entries[p4num].clone(); - // self.entries[p4num].set_addr(entry.addr(), flags); - // } } impl Index for PageTable { diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs index e878f98..a1633ff 100644 --- a/crate/aarch64/src/paging/recursive.rs +++ b/crate/aarch64/src/paging/recursive.rs @@ -5,7 +5,7 @@ use paging::{ page_table::{FrameError, PageTable, PageTableEntry, PageTableFlags}, NotGiantPageSize, Page, PageSize, PhysFrame, Size4KiB, }; -use paging::page_table::PageTableFlags as Flags; +use paging::{page_table::PageTableFlags as Flags, PageTableAttribute, memory_attribute::*}; use asm::{ttbr_el1_read, tlb_invalidate}; use barrier; use ux::u9; @@ -46,6 +46,7 @@ pub trait Mapper { page: Page, frame: PhysFrame, flags: PageTableFlags, + attr: PageTableAttribute, allocator: &mut A, ) -> Result, MapToError> where @@ -71,6 +72,7 @@ pub trait Mapper { &mut self, frame: PhysFrame, flags: PageTableFlags, + attr: PageTableAttribute, allocator: &mut A, ) -> Result, MapToError> where @@ -79,7 +81,7 @@ pub trait Mapper { Self: Mapper, { let page = Page::containing_address(VirtAddr::new(frame.start_address().as_u64())); - self.map_to(page, frame, flags, allocator) + self.map_to(page, frame, flags, attr, allocator) } } @@ -218,7 +220,7 @@ impl<'a> RecursivePageTable<'a> { if entry.is_unused() { if let Some(frame) = allocator.alloc() { - entry.set_frame(frame, Flags::default()); + entry.set_frame(frame, Flags::default(), MairNormal::attr_value()); created = true; } else { return Err(MapToError::FrameAllocationFailed); @@ -289,6 +291,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { page: Page, frame: PhysFrame, flags: PageTableFlags, + attr: PageTableAttribute, allocator: &mut A, ) -> Result, MapToError> where @@ -309,7 +312,7 @@ impl<'a> Mapper for RecursivePageTable<'a> { if !p1[page.p1_index()].is_unused() { return Err(MapToError::PageAlreadyMapped); } - p1[page.p1_index()].set_frame(frame, flags); + p1[page.p1_index()].set_frame(frame, flags, attr); Ok(MapperFlush::new(page)) } diff --git a/crate/aarch64/src/regs/mair_el1.rs b/crate/aarch64/src/regs/mair_el1.rs index 2c7c7da..dbd7f9d 100644 --- a/crate/aarch64/src/regs/mair_el1.rs +++ b/crate/aarch64/src/regs/mair_el1.rs @@ -24,72 +24,49 @@ use register::cpu::RegisterReadWrite; register_bitfields! {u64, MAIR_EL1 [ - // TODO: Macrofy this - /// Attribute 7 - Attr7_HIGH OFFSET(60) NUMBITS(4) [], - Attr7_LOW_DEVICE OFFSET(56) NUMBITS(4) [], - Attr7_LOW_MEMORY OFFSET(56) NUMBITS(4) [], + Attr7 OFFSET(56) NUMBITS(8) [], /// Attribute 6 - Attr6_HIGH OFFSET(52) NUMBITS(4) [], - Attr6_LOW_DEVICE OFFSET(48) NUMBITS(4) [], - Attr6_LOW_MEMORY OFFSET(48) NUMBITS(4) [], + Attr6 OFFSET(48) NUMBITS(8) [], /// Attribute 5 - Attr5_HIGH OFFSET(44) NUMBITS(4) [], - Attr5_LOW_DEVICE OFFSET(40) NUMBITS(4) [], - Attr5_LOW_MEMORY OFFSET(40) NUMBITS(4) [], + Attr5 OFFSET(40) NUMBITS(8) [], /// Attribute 4 - Attr4_HIGH OFFSET(36) NUMBITS(4) [], - Attr4_LOW_DEVICE OFFSET(32) NUMBITS(4) [], - Attr4_LOW_MEMORY OFFSET(32) NUMBITS(4) [], + Attr4 OFFSET(32) NUMBITS(8) [], /// Attribute 3 - Attr3_HIGH OFFSET(28) NUMBITS(4) [], - Attr3_LOW_DEVICE OFFSET(24) NUMBITS(4) [], - Attr3_LOW_MEMORY OFFSET(24) NUMBITS(4) [], + Attr3 OFFSET(24) NUMBITS(8) [], /// Attribute 2 - Attr2_HIGH OFFSET(20) NUMBITS(4) [ - Device = 0b0000, - Memory_OuterNonCacheable = 0b0100, - Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 - ], - Attr2_LOW_DEVICE OFFSET(16) NUMBITS(4) [ - Device_nGnRE = 0b0100 - ], - Attr2_LOW_MEMORY OFFSET(16) NUMBITS(4) [ - InnerNonCacheable = 0b0100, - InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 - ], + Attr2 OFFSET(16) NUMBITS(8) [], /// Attribute 1 - Attr1_HIGH OFFSET(12) NUMBITS(4) [ - Device = 0b0000, - Memory_OuterNonCacheable = 0b0100, - Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 - ], - Attr1_LOW_DEVICE OFFSET(8) NUMBITS(4) [ - Device_nGnRE = 0b0100 - ], - Attr1_LOW_MEMORY OFFSET(8) NUMBITS(4) [ - InnerNonCacheable = 0b0100, - InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 - ], + Attr1 OFFSET(8) NUMBITS(8) [], /// Attribute 0 - Attr0_HIGH OFFSET(4) NUMBITS(4) [ + Attr0 OFFSET(0) NUMBITS(8) [] + ] +} + +register_bitfields! {u64, + MAIR_ATTR [ + Attr_HIGH OFFSET(4) NUMBITS(4) [ Device = 0b0000, Memory_OuterNonCacheable = 0b0100, + Memory_OuterWriteThrough_NonTransient_ReadAlloc_WriteAlloc = 0b1011, Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 ], - Attr0_LOW_DEVICE OFFSET(0) NUMBITS(4) [ - Device_nGnRE = 0b0100 + Attr_LOW_DEVICE OFFSET(0) NUMBITS(4) [ + Device_nGnRnE = 0b0000, + Device_nGnRE = 0b0100, + Device_nGRE = 0b1000, + Device_GRE = 0b1100 ], - Attr0_LOW_MEMORY OFFSET(0) NUMBITS(4) [ + Attr_LOW_MEMORY OFFSET(0) NUMBITS(4) [ InnerNonCacheable = 0b0100, + InnerWriteThrough_NonTransient_ReadAlloc_WriteAlloc = 0b1011, InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 ] ] diff --git a/crate/aarch64/src/regs/mod.rs b/crate/aarch64/src/regs/mod.rs index 5a7e556..f69f0c4 100644 --- a/crate/aarch64/src/regs/mod.rs +++ b/crate/aarch64/src/regs/mod.rs @@ -40,7 +40,7 @@ pub use self::daif::DAIF; pub use self::elr_el2::ELR_EL2; pub use self::hcr_el2::HCR_EL2; pub use self::id_aa64mmfr0_el1::ID_AA64MMFR0_EL1; -pub use self::mair_el1::MAIR_EL1; +pub use self::mair_el1::{MAIR_EL1, MAIR_ATTR}; pub use self::mpidr_el1::MPIDR_EL1; pub use self::sctlr_el1::SCTLR_EL1; pub use self::sp::SP; diff --git a/kernel/src/arch/aarch64/board/raspi3/mod.rs b/kernel/src/arch/aarch64/board/raspi3/mod.rs index 2d13315..0db5133 100644 --- a/kernel/src/arch/aarch64/board/raspi3/mod.rs +++ b/kernel/src/arch/aarch64/board/raspi3/mod.rs @@ -6,6 +6,8 @@ pub mod irq; pub mod timer; pub mod serial; +pub const IO_BASE: usize = bcm2837::IO_BASE; + pub fn init() { assert_has_not_been_called!("board::init must be called only once"); diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index 1c486d2..7536dc4 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -3,7 +3,8 @@ use ucore_memory::PAGE_SIZE; use memory::{FRAME_ALLOCATOR, init_heap, MemoryArea, MemoryAttr, MemorySet, Stack}; use super::atags::atags::Atags; -use aarch64::{barrier, regs::*, addr::*, paging::PhysFrame as Frame}; +use aarch64::{barrier, regs::*, addr::*}; +use aarch64::paging::{PhysFrame as Frame, memory_attribute::*}; /// Memory initialization. pub fn init() { @@ -28,13 +29,11 @@ pub fn init_mmu_early() { // device. MAIR_EL1.write( - // Attribute 1 - MAIR_EL1::Attr1_HIGH::Device - + MAIR_EL1::Attr1_LOW_DEVICE::Device_nGnRE - // Attribute 0 - + MAIR_EL1::Attr0_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc - + MAIR_EL1::Attr0_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc, + MAIR_EL1::Attr0.val(MairDevice::config_value()) + + MAIR_EL1::Attr1.val(MairNormal::config_value()) + + MAIR_EL1::Attr2.val(MairNormalNonCacheable::config_value()), ); + // Configure various settings of stage 1 of the EL1 translation regime. let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange); TCR_EL1.write( diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index 9986faa..f11820c 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -8,62 +8,8 @@ use ucore_memory::paging::*; use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, ttbr_el1_read, ttbr_el1_write}; use aarch64::{PhysAddr, VirtAddr}; use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; -use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PhysFrame as Frame, Size4KiB, Size2MiB}; - -register_bitfields! {u64, - // AArch64 Reference Manual page 2150 - STAGE1_DESCRIPTOR [ - /// Execute-never - XN OFFSET(54) NUMBITS(1) [ - False = 0, - True = 1 - ], - - /// Various address fields, depending on use case - LVL4_OUTPUT_ADDR_4KiB OFFSET(39) NUMBITS(9) [], // [47:39] - LVL3_OUTPUT_ADDR_4KiB OFFSET(30) NUMBITS(18) [], // [47:30] - LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21] - NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12] - - /// Access flag - AF OFFSET(10) NUMBITS(1) [ - False = 0, - True = 1 - ], - - /// Shareability field - SH OFFSET(8) NUMBITS(2) [ - OuterShareable = 0b10, - InnerShareable = 0b11 - ], - - /// Access Permissions - AP OFFSET(6) NUMBITS(2) [ - RW_EL1 = 0b00, - RW_EL1_EL0 = 0b01, - RO_EL1 = 0b10, - RO_EL1_EL0 = 0b11 - ], - - /// Memory attributes index into the MAIR_EL1 register - AttrIndx OFFSET(2) NUMBITS(3) [], - - TYPE OFFSET(1) NUMBITS(1) [ - Block = 0, - Table = 1 - ], - - VALID OFFSET(0) NUMBITS(1) [ - False = 0, - True = 1 - ] - ] -} - -mod mair { - pub const NORMAL: u64 = 0; - pub const DEVICE: u64 = 1; -} +use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PhysFrame as Frame, Size4KiB, Size2MiB, Size1GiB}; +use aarch64::paging::memory_attribute::*; // need 3 page pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) { @@ -74,34 +20,24 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) p3.zero(); p2.zero(); - // Fill the rest of the LVL2 (2MiB) entries as block - // descriptors. Differentiate between normal and device mem. - const MMIO_BASE: u64 = 0x3F000000; - let mmio_base: u64 = MMIO_BASE >> 21; - let mut common = STAGE1_DESCRIPTOR::VALID::True - + STAGE1_DESCRIPTOR::TYPE::Block - + STAGE1_DESCRIPTOR::AP::RW_EL1 - + STAGE1_DESCRIPTOR::AF::True; - // + STAGE1_DESCRIPTOR::XN::True; - - for i in 0..512 { - let j: u64 = i as u64; - - let mem_attr = if j >= mmio_base { - STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE) - } else { - STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL) - }; + let (start_addr, end_addr) = (0, 0x40000000); + let block_flags = EF::VALID | EF::AF | EF::WRITE | EF::XN; + for page in Page::::range_of(start_addr, end_addr) { + let paddr = PhysAddr::new(page.start_address().as_u64()); - p2[i].entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(j)).value; + use arch::board::IO_BASE; + if paddr.as_u64() >= IO_BASE as u64 { + p2[page.p2_index()].set_block::(paddr, block_flags | EF::PXN, MairDevice::attr_value()); + } else { + p2[page.p2_index()].set_block::(paddr, block_flags, MairNormal::attr_value()); + } } - common = common + STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL); + p3[0].set_frame(frame_lvl2, EF::default(), MairNormal::attr_value()); + p3[1].set_block::(PhysAddr::new(0x40000000), block_flags | EF::PXN, MairDevice::attr_value()); - p3[0].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl2.start_address().as_u64() >> 12)).value; - p3[1].entry = (common + STAGE1_DESCRIPTOR::LVL3_OUTPUT_ADDR_4KiB.val(1)).value; - p4[0].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl3.start_address().as_u64() >> 12)).value; - p4[RECURSIVE_INDEX].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl4.start_address().as_u64() >> 12)).value; + p4[0].set_frame(frame_lvl3, EF::default(), MairNormal::attr_value()); + p4[RECURSIVE_INDEX].set_frame(frame_lvl4, EF::default(), MairNormal::attr_value()); // warn!("p2"); // for i in 0..512 { @@ -129,18 +65,10 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) /// map the range [start, end) as device memory, insert to the MemorySet pub fn remap_device_2mib(ms: &mut MemorySet, start_addr: usize, end_addr: usize) { ms.edit(|active_table| { - let common = STAGE1_DESCRIPTOR::VALID::True - + STAGE1_DESCRIPTOR::TYPE::Block - + STAGE1_DESCRIPTOR::AP::RW_EL1 - + STAGE1_DESCRIPTOR::AF::True - + STAGE1_DESCRIPTOR::XN::True; - - let mem_attr = STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE); - - type Page2MiB = Page; - for page in Page2MiB::range_of(start_addr, end_addr) { + for page in Page::::range_of(start_addr, end_addr) { + let paddr = PhysAddr::new(page.start_address().as_u64()); let p2 = unsafe { &mut *active_table.0.p2_ptr(page) }; - p2[page.p2_index()].entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(page.start_address().as_u64() >> 21)).value; + p2[page.p2_index()].set_block::(paddr, EF::default() - EF::TABLE_OR_PAGE, MairDevice::attr_value()); } // let p2 = unsafe { &mut *(0o777_777_000_000_0000 as *mut Aarch64PageTable) }; @@ -168,7 +96,8 @@ impl PageTable for ActivePageTable { fn map(&mut self, addr: usize, target: usize) -> &mut PageEntry { let flags = EF::default(); - self.0.map_to(Page::of_addr(addr), Frame::of_addr(target), flags, &mut FrameAllocatorForAarch64) + let attr = MairNormal::attr_value(); + self.0.map_to(Page::of_addr(addr), Frame::of_addr(target), flags, attr, &mut FrameAllocatorForAarch64) .unwrap().flush(); self.get_entry(addr) } @@ -303,7 +232,7 @@ impl InactivePageTable for InactivePageTable0 { active_table().with_temporary_map(&frame, |_, table: &mut Aarch64PageTable| { table.zero(); // set up recursive mapping for the table - table[RECURSIVE_INDEX].set_frame(frame.clone(), EF::default()); + table[RECURSIVE_INDEX].set_frame(frame.clone(), EF::default(), MairNormal::attr_value()); }); InactivePageTable0 { p4_frame: frame } } @@ -313,7 +242,7 @@ impl InactivePageTable for InactivePageTable0 { let backup = p4_table[RECURSIVE_INDEX].clone(); // overwrite recursive mapping - p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::default()); + p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::default(), MairNormal::attr_value()); tlb_invalidate_all(); // execute f in the new context @@ -376,7 +305,7 @@ impl InactivePageTable0 { assert!(!e0.is_unused()); self.edit(|_| { - table[KERNEL_PML4].set_frame(Frame::containing_address(e0.addr()), EF::default()); + table[KERNEL_PML4].set_frame(Frame::containing_address(e0.addr()), EF::default(), MairNormal::attr_value()); }); } } From 264600f145465bce0411b3600303c412db05e1fc Mon Sep 17 00:00:00 2001 From: equation314 Date: Sun, 25 Nov 2018 18:27:31 +0800 Subject: [PATCH 11/16] aarch64/mmu: add io remap --- crate/memory/src/memory_set.rs | 8 +++- crate/memory/src/paging/mod.rs | 2 + kernel/src/arch/aarch64/board/raspi3/mod.rs | 3 +- kernel/src/arch/aarch64/memory.rs | 7 ++- kernel/src/arch/aarch64/paging.rs | 52 ++------------------- kernel/src/arch/riscv32/paging.rs | 2 + kernel/src/arch/x86_64/paging.rs | 4 +- 7 files changed, 24 insertions(+), 54 deletions(-) diff --git a/crate/memory/src/memory_set.rs b/crate/memory/src/memory_set.rs index f67c956..316c28b 100644 --- a/crate/memory/src/memory_set.rs +++ b/crate/memory/src/memory_set.rs @@ -98,6 +98,7 @@ pub struct MemoryAttr { user: bool, readonly: bool, execute: bool, + mmio: bool, hide: bool, } @@ -114,6 +115,10 @@ impl MemoryAttr { self.execute = true; self } + pub fn mmio(mut self) -> Self { + self.mmio = true; + self + } pub fn hide(mut self) -> Self { self.hide = true; self @@ -122,8 +127,9 @@ impl MemoryAttr { if self.user { entry.set_user(true); } if self.readonly { entry.set_writable(false); } if self.execute { entry.set_execute(true); } + if self.mmio { entry.set_mmio(false); } if self.hide { entry.set_present(false); } - if self.user || self.readonly || self.execute || self.hide { entry.update(); } + if self.user || self.readonly || self.execute || self.mmio || self.hide { entry.update(); } } } diff --git a/crate/memory/src/paging/mod.rs b/crate/memory/src/paging/mod.rs index 0a3d4c0..0f38ef1 100644 --- a/crate/memory/src/paging/mod.rs +++ b/crate/memory/src/paging/mod.rs @@ -57,4 +57,6 @@ pub trait Entry { fn set_user(&mut self, value: bool); fn execute(&self) -> bool; fn set_execute(&mut self, value: bool); + fn mmio(&self) -> bool; + fn set_mmio(&mut self, value: bool); } diff --git a/kernel/src/arch/aarch64/board/raspi3/mod.rs b/kernel/src/arch/aarch64/board/raspi3/mod.rs index 0db5133..98e59e0 100644 --- a/kernel/src/arch/aarch64/board/raspi3/mod.rs +++ b/kernel/src/arch/aarch64/board/raspi3/mod.rs @@ -6,7 +6,8 @@ pub mod irq; pub mod timer; pub mod serial; -pub const IO_BASE: usize = bcm2837::IO_BASE; +pub const IO_REMAP_BASE: usize = bcm2837::IO_BASE; +pub const IO_REMAP_END: usize = 0x40001000; pub fn init() { assert_has_not_been_called!("board::init must be called only once"); diff --git a/kernel/src/arch/aarch64/memory.rs b/kernel/src/arch/aarch64/memory.rs index 7536dc4..29f3009 100644 --- a/kernel/src/arch/aarch64/memory.rs +++ b/kernel/src/arch/aarch64/memory.rs @@ -25,7 +25,7 @@ pub fn init_mmu_early() { let frame_lvl4 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL4 as *const _ as u64)); let frame_lvl3 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL3 as *const _ as u64)); let frame_lvl2 = Frame::containing_address(PhysAddr::new(&PAGE_TABLE_LVL2 as *const _ as u64)); - super::paging::setup_page_table(frame_lvl4, frame_lvl3, frame_lvl2); + super::paging::setup_temp_page_table(frame_lvl4, frame_lvl3, frame_lvl2); // device. MAIR_EL1.write( @@ -111,9 +111,8 @@ fn remap_the_kernel() { ms.push(MemoryArea::new_identity(srodata as usize, erodata as usize, MemoryAttr::default().readonly(), "rodata")); ms.push(MemoryArea::new_identity(sbss as usize, ebss as usize, MemoryAttr::default(), "bss")); - // ensure the level 2 page table exists - ms.push(MemoryArea::new_identity(0x40000000, 0x40200000, MemoryAttr::default(), "arm_control")); - super::paging::remap_device_2mib(&mut ms, 0x3F000000, 0x40200000); + use arch::board::{IO_REMAP_BASE, IO_REMAP_END}; + ms.push(MemoryArea::new_identity(IO_REMAP_BASE, IO_REMAP_END, MemoryAttr::default().mmio(), "io_remap")); unsafe { ms.activate(); } use core::mem::forget; diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index f11820c..eab53f4 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -12,7 +12,7 @@ use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PhysFrame as Frame use aarch64::paging::memory_attribute::*; // need 3 page -pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) { +pub fn setup_temp_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) { let p4 = unsafe { &mut *(frame_lvl4.start_address().as_u64() as *mut Aarch64PageTable) }; let p3 = unsafe { &mut *(frame_lvl3.start_address().as_u64() as *mut Aarch64PageTable) }; let p2 = unsafe { &mut *(frame_lvl2.start_address().as_u64() as *mut Aarch64PageTable) }; @@ -25,8 +25,8 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) for page in Page::::range_of(start_addr, end_addr) { let paddr = PhysAddr::new(page.start_address().as_u64()); - use arch::board::IO_BASE; - if paddr.as_u64() >= IO_BASE as u64 { + use arch::board::IO_REMAP_BASE; + if paddr.as_u64() >= IO_REMAP_BASE as u64 { p2[page.p2_index()].set_block::(paddr, block_flags | EF::PXN, MairDevice::attr_value()); } else { p2[page.p2_index()].set_block::(paddr, block_flags, MairNormal::attr_value()); @@ -39,54 +39,10 @@ pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) p4[0].set_frame(frame_lvl3, EF::default(), MairNormal::attr_value()); p4[RECURSIVE_INDEX].set_frame(frame_lvl4, EF::default(), MairNormal::attr_value()); - // warn!("p2"); - // for i in 0..512 { - // if p2[i].flags().bits() != 0 { - // info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]); - // } - // } - // warn!("p3"); - // for i in 0..512 { - // if p3[i].flags().bits() != 0 { - // info!("{:x?} {:x?} {:x?}",i, &p3[i] as *const _ as usize, p3[i]); - // } - // } - // warn!("p4"); - // for i in 0..512 { - // if p4[i].flags().bits() != 0 { - // info!("{:x?} {:x?} {:x?}",i, &p4[i] as *const _ as usize, p4[i]); - // } - // } - ttbr_el1_write(0, frame_lvl4); tlb_invalidate_all(); } -/// map the range [start, end) as device memory, insert to the MemorySet -pub fn remap_device_2mib(ms: &mut MemorySet, start_addr: usize, end_addr: usize) { - ms.edit(|active_table| { - for page in Page::::range_of(start_addr, end_addr) { - let paddr = PhysAddr::new(page.start_address().as_u64()); - let p2 = unsafe { &mut *active_table.0.p2_ptr(page) }; - p2[page.p2_index()].set_block::(paddr, EF::default() - EF::TABLE_OR_PAGE, MairDevice::attr_value()); - } - - // let p2 = unsafe { &mut *(0o777_777_000_000_0000 as *mut Aarch64PageTable) }; - // for i in 0..512 { - // if p2[i].flags().bits() != 0 { - // info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]); - // } - // } - - // let p2 = unsafe { &mut *(0o777_777_000_001_0000 as *mut Aarch64PageTable) }; - // for i in 0..512 { - // if p2[i].flags().bits() != 0 { - // info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]); - // } - // } - }); -} - pub struct ActivePageTable(RecursivePageTable<'static>); pub struct PageEntry(PageTableEntry); @@ -201,6 +157,8 @@ impl Entry for PageEntry { false => self.as_flags().set(EF::PXN, !value), } } + fn mmio(&self) -> bool { self.0.attr().value == MairDevice::attr_value().value } + fn set_mmio(&mut self, value: bool) { self.0.modify_attr(MairDevice::attr_value()); } } impl PageEntry { diff --git a/kernel/src/arch/riscv32/paging.rs b/kernel/src/arch/riscv32/paging.rs index 680448b..ef0710f 100644 --- a/kernel/src/arch/riscv32/paging.rs +++ b/kernel/src/arch/riscv32/paging.rs @@ -126,6 +126,8 @@ impl Entry for PageEntry { fn set_user(&mut self, value: bool) { self.as_flags().set(EF::USER, value); } fn execute(&self) -> bool { self.0.flags().contains(EF::EXECUTABLE) } fn set_execute(&mut self, value: bool) { self.as_flags().set(EF::EXECUTABLE, value); } + fn mmio(&self) -> bool { unimplemented!() } + fn set_mmio(&mut self, value: bool) { unimplemented!() } } impl PageEntry { diff --git a/kernel/src/arch/x86_64/paging.rs b/kernel/src/arch/x86_64/paging.rs index 8717703..9e164bb 100644 --- a/kernel/src/arch/x86_64/paging.rs +++ b/kernel/src/arch/x86_64/paging.rs @@ -138,6 +138,8 @@ impl Entry for PageEntry { } fn execute(&self) -> bool { !self.0.flags().contains(EF::NO_EXECUTE) } fn set_execute(&mut self, value: bool) { self.as_flags().set(EF::NO_EXECUTE, !value); } + fn mmio(&self) -> bool { unimplemented!() } + fn set_mmio(&mut self, value: bool) { unimplemented!() } } impl PageEntry { @@ -261,4 +263,4 @@ impl FrameDeallocator for FrameAllocatorForX86 { fn dealloc(&mut self, frame: Frame) { dealloc_frame(frame.start_address().as_u64() as usize); } -} \ No newline at end of file +} From d30c7e59cabfc2a1d7b3e5e2bf1b22d1539b6b35 Mon Sep 17 00:00:00 2001 From: equation314 Date: Sun, 25 Nov 2018 20:01:13 +0800 Subject: [PATCH 12/16] aarch64: minor modify --- crate/aarch64/Cargo.lock | 108 ++++++++++++++++ crate/aarch64/src/asm.rs | 152 ++++++++--------------- kernel/Cargo.lock | 18 --- kernel/Cargo.toml | 2 - kernel/src/arch/aarch64/interrupt/mod.rs | 3 +- kernel/src/arch/aarch64/mod.rs | 1 - kernel/src/arch/aarch64/paging.rs | 26 ++-- 7 files changed, 183 insertions(+), 127 deletions(-) create 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"53d8df5dd8d07fedccd202de1887d94481fadaea3db70479f459e8163a1fab41" diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs index 1c1ee6d..4cd37d7 100644 --- a/crate/aarch64/src/asm.rs +++ b/crate/aarch64/src/asm.rs @@ -1,31 +1,9 @@ +//! Miscellaneous assembly instructions and functions + use paging::PhysFrame; use addr::{PhysAddr, VirtAddr}; use regs::*; -#[inline(always)] -pub fn tlb_invalidate_all() { - unsafe { - asm!( - "dsb ishst - tlbi vmalle1is - dsb ish - isb" - ); - } -} - -#[inline(always)] -pub fn tlb_invalidate(vaddr: VirtAddr) { - unsafe { - asm!( - "dsb ishst - tlbi vaae1is, $0 - dsb ish - isb" :: "r"(vaddr.as_u64() >> 12) - ); - } -} - /// Returns the current stack pointer. #[inline(always)] pub fn sp() -> *const u8 { @@ -37,91 +15,32 @@ pub fn sp() -> *const u8 { ptr as *const u8 } +/// Returns the current point counter. #[inline(always)] pub unsafe fn get_pc() -> usize { let pc: usize; - asm!("ADR $0, ." : "=r"(pc)); + asm!("adr $0, ." : "=r"(pc)); pc } -/// Returns the current exception level. -/// -/// # Safety -/// This function should only be called when EL is >= 1. -#[inline(always)] -pub unsafe fn current_el() -> u8 { - let el_reg: u64; - asm!("mrs $0, CurrentEL" : "=r"(el_reg)); - ((el_reg & 0b1100) >> 2) as u8 -} - -#[inline(always)] -pub unsafe fn get_far() -> usize { - let far: usize; - asm!("mrs $0, far_el1" : "=r"(far)); - far -} - -#[inline(always)] -pub unsafe fn get_ttbr0() -> usize { - let ttbr0: usize; - asm!("mrs $0, ttbr0_el1" : "=r"(ttbr0)); - ttbr0 -} - -#[inline(always)] -pub unsafe fn get_ttbr1() -> usize { - let ttbr0: usize; - asm!("mrs $0, ttbr1_el1" : "=r"(ttbr0)); - ttbr0 -} - -#[inline(always)] -pub fn address_translate(vaddr: usize) -> usize { - let paddr: usize; - unsafe { - asm!("at S1E1R, $1; mrs $0, par_el1" : "=r"(paddr) : "r"(vaddr)); - } - paddr -} - -/// Returns the SPSel value. -#[inline(always)] -pub fn sp_sel() -> u8 { - let ptr: u32; - unsafe { - asm!("mrs $0, SPSel" : "=r"(ptr)); - } - - (ptr & 1) as u8 -} - -/// Returns the core currently executing. -/// -/// # Safety -/// -/// This function should only be called when EL is >= 1. -pub unsafe fn affinity() -> usize { - let x: usize; - asm!("mrs $0, mpidr_el1 - and $0, $0, #3" - : "=r"(x)); - - x -} +/// The classic no-op +#[inline] +pub fn nop() { + match () { + #[cfg(target_arch = "aarch64")] + () => unsafe { asm!("nop" :::: "volatile") }, -pub fn wfi() { - unsafe { - asm!("wfi" :::: "volatile"); + #[cfg(not(target_arch = "aarch64"))] + () => unimplemented!(), } } -/// The classic no-op +/// Wait For Interrupt #[inline] -pub fn nop() { +pub fn wfi() { match () { #[cfg(target_arch = "aarch64")] - () => unsafe { asm!("nop" :::: "volatile") }, + () => unsafe { asm!("wfi" :::: "volatile") }, #[cfg(not(target_arch = "aarch64"))] () => unimplemented!(), @@ -160,7 +79,44 @@ pub fn eret() -> ! { } } -pub fn ttbr_el1_read(which: u8) -> (PhysFrame) { +/// Invalidate all TLB entries. +#[inline(always)] +pub fn tlb_invalidate_all() { + unsafe { + asm!( + "dsb ishst + tlbi vmalle1is + dsb ish + isb" + ); + } +} + +/// Invalidate TLB entries that would be used to translate the specified address. +#[inline(always)] +pub fn tlb_invalidate(vaddr: VirtAddr) { + unsafe { + asm!( + "dsb ishst + tlbi vaae1is, $0 + dsb ish + isb" :: "r"(vaddr.as_u64() >> 12) + ); + } +} + +/// Address Translate. +#[inline(always)] +pub fn address_translate(vaddr: usize) -> usize { + let paddr: usize; + unsafe { + asm!("at S1E1R, $1; mrs $0, par_el1" : "=r"(paddr) : "r"(vaddr)); + } + paddr +} + +/// Read TTBRx_EL1 as PhysFrame +pub fn ttbr_el1_read(which: u8) -> PhysFrame { let baddr = match which { 0 => TTBR0_EL1.get_baddr(), 1 => TTBR1_EL1.get_baddr(), @@ -169,6 +125,7 @@ pub fn ttbr_el1_read(which: u8) -> (PhysFrame) { PhysFrame::containing_address(PhysAddr::new(baddr)) } +/// Write TTBRx_EL1 from PhysFrame pub fn ttbr_el1_write(which: u8, frame: PhysFrame) { let baddr = frame.start_address().as_u64(); match which { @@ -178,6 +135,7 @@ pub fn ttbr_el1_write(which: u8, frame: PhysFrame) { }; } +/// write TTBRx_EL1 from PhysFrame and ASID pub fn ttbr_el1_write_asid(which: u8, asid: u16, frame: PhysFrame) { let baddr = frame.start_address().as_u64(); match which { diff --git a/kernel/Cargo.lock b/kernel/Cargo.lock index 7795f1f..4e2b6dc 100644 --- a/kernel/Cargo.lock +++ b/kernel/Cargo.lock @@ -5,7 +5,6 @@ dependencies = [ "bare-metal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)", "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)", - 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Entrance and initialization for aarch64. extern crate atags; -extern crate cortex_a; pub mod io; pub mod paging; diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index eab53f4..0093385 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -146,19 +146,29 @@ impl Entry for PageEntry { self.as_flags().set(EF::nG, value); // set non-global to use ASID } fn execute(&self) -> bool { - match self.user() { - true => !self.0.flags().contains(EF::XN), - false => !self.0.flags().contains(EF::PXN), + if self.user() { + !self.0.flags().contains(EF::XN) + } else { + !self.0.flags().contains(EF::PXN) } } fn set_execute(&mut self, value: bool) { - match self.user() { - true => self.as_flags().set(EF::XN, !value), - false => self.as_flags().set(EF::PXN, !value), + if self.user() { + self.as_flags().set(EF::XN, !value) + } else { + self.as_flags().set(EF::PXN, !value) + } + } + fn mmio(&self) -> bool { + self.0.attr().value == MairDevice::attr_value().value + } + fn set_mmio(&mut self, value: bool) { + if value { + self.0.modify_attr(MairDevice::attr_value()) + } else { + self.0.modify_attr(MairNormal::attr_value()) } } - fn mmio(&self) -> bool { self.0.attr().value == MairDevice::attr_value().value } - fn set_mmio(&mut self, value: bool) { self.0.modify_attr(MairDevice::attr_value()); } } impl PageEntry { From 0eb33b661f152c5de3a97c9bd0e3f0aaf82bf6aa Mon Sep 17 00:00:00 2001 From: equation314 Date: Fri, 30 Nov 2018 14:13:27 +0800 Subject: [PATCH 13/16] aarch64/mmu: fix some bugs --- crate/aarch64/Cargo.lock | 108 ------------------- crate/aarch64/src/paging/memory_attribute.rs | 2 +- crate/memory/src/memory_set.rs | 2 +- kernel/src/lib.rs | 4 - 4 files changed, 2 insertions(+), 114 deletions(-) delete mode 100644 crate/aarch64/Cargo.lock diff --git a/crate/aarch64/Cargo.lock b/crate/aarch64/Cargo.lock deleted file mode 100644 index 1038287..0000000 --- a/crate/aarch64/Cargo.lock +++ /dev/null @@ -1,108 +0,0 @@ -[[package]] -name = "aarch64" -version = "0.1.0" -dependencies = [ - "bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)", - "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", - 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MEMORY_ATTRIBUTE::SH::NonShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) + MEMORY_ATTRIBUTE::SH::OuterShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) } } diff --git a/crate/memory/src/memory_set.rs b/crate/memory/src/memory_set.rs index 316c28b..b47a6c2 100644 --- a/crate/memory/src/memory_set.rs +++ b/crate/memory/src/memory_set.rs @@ -127,7 +127,7 @@ impl MemoryAttr { if self.user { entry.set_user(true); } if self.readonly { entry.set_writable(false); } if self.execute { entry.set_execute(true); } - if self.mmio { entry.set_mmio(false); } + if self.mmio { entry.set_mmio(true); } if self.hide { entry.set_present(false); } if self.user || self.readonly || self.execute || self.mmio || self.hide { entry.update(); } } diff --git a/kernel/src/lib.rs b/kernel/src/lib.rs index 05cc181..063b1d0 100644 --- a/kernel/src/lib.rs +++ b/kernel/src/lib.rs @@ -38,10 +38,6 @@ extern crate aarch64; use linked_list_allocator::LockedHeap; - -#[macro_use] -extern crate register; - #[macro_use] // print! pub mod logging; mod memory; From d6a54496f0aaa479ae06ac0b80a7d85f98dc17ae Mon Sep 17 00:00:00 2001 From: equation314 Date: Sat, 1 Dec 2018 19:43:49 +0800 Subject: [PATCH 14/16] arch64/mmu: invalidate all icaches in InactivePageTable::with() --- crate/aarch64/src/asm.rs | 12 ++++++++++++ kernel/src/arch/aarch64/paging.rs | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs index 4cd37d7..bada049 100644 --- a/crate/aarch64/src/asm.rs +++ b/crate/aarch64/src/asm.rs @@ -105,6 +105,18 @@ pub fn tlb_invalidate(vaddr: VirtAddr) { } } +/// Invalidate all instruction caches in Inner Shareable domain to Point of Unification. +#[inline(always)] +pub fn flush_icache_all() { + unsafe { + asm!( + "ic ialluis + dsb ish + isb" + ); + } +} + /// Address Translate. #[inline(always)] pub fn address_translate(vaddr: usize) -> usize { diff --git a/kernel/src/arch/aarch64/paging.rs b/kernel/src/arch/aarch64/paging.rs index 0093385..0b7546e 100644 --- a/kernel/src/arch/aarch64/paging.rs +++ b/kernel/src/arch/aarch64/paging.rs @@ -5,7 +5,7 @@ use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame}; use ucore_memory::memory_set::*; use ucore_memory::PAGE_SIZE; use ucore_memory::paging::*; -use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, ttbr_el1_read, ttbr_el1_write}; +use aarch64::asm::{tlb_invalidate, tlb_invalidate_all, flush_icache_all, ttbr_el1_read, ttbr_el1_write}; use aarch64::{PhysAddr, VirtAddr}; use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, PageTableFlags as EF, RecursivePageTable}; use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PhysFrame as Frame, Size4KiB, Size2MiB, Size1GiB}; @@ -246,6 +246,7 @@ impl InactivePageTable for InactivePageTable0 { if old_frame != new_frame { ttbr_el1_write(1, old_frame); tlb_invalidate_all(); + flush_icache_all(); } } From a59a7fbe9a3e4878bcd8abbc913e87b46c6c717d Mon Sep 17 00:00:00 2001 From: equation314 Date: Sat, 1 Dec 2018 20:00:35 +0800 Subject: [PATCH 15/16] aarch64/mmu: simply handle page fault --- crate/aarch64/src/regs/far_el1.rs | 31 ++++++++++++++++++++ crate/aarch64/src/regs/mod.rs | 2 ++ kernel/src/arch/aarch64/interrupt/handler.rs | 28 +++++++++++++++--- 3 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 crate/aarch64/src/regs/far_el1.rs diff --git a/crate/aarch64/src/regs/far_el1.rs b/crate/aarch64/src/regs/far_el1.rs new file mode 100644 index 0000000..fc809fa --- /dev/null +++ b/crate/aarch64/src/regs/far_el1.rs @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018 by the author(s) + * + * ============================================================================= + * + * Licensed under either of + * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) + * - MIT License (http://opensource.org/licenses/MIT) + * at your option. + * + * ============================================================================= + * + * Author(s): + * - Andre Richter + */ + +//! Fault Address Register - EL1 +//! +//! Holds the faulting Virtual Address for all synchronous Instruction or Data +//! Abort, PC alignment fault and Watchpoint exceptions that are taken to EL1. + +use register::cpu::RegisterReadWrite; + +pub struct Reg; + +impl RegisterReadWrite for Reg { + sys_coproc_read_raw!(u64, "FAR_EL1"); + sys_coproc_write_raw!(u64, "FAR_EL1"); +} + +pub static FAR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/mod.rs b/crate/aarch64/src/regs/mod.rs index f69f0c4..11a6d3f 100644 --- a/crate/aarch64/src/regs/mod.rs +++ b/crate/aarch64/src/regs/mod.rs @@ -12,6 +12,7 @@ mod cntvoff_el2; mod currentel; mod daif; mod elr_el2; +mod far_el1; mod hcr_el2; mod id_aa64mmfr0_el1; mod mair_el1; @@ -38,6 +39,7 @@ pub use self::cntvoff_el2::CNTVOFF_EL2; pub use self::currentel::CurrentEL; pub use self::daif::DAIF; pub use self::elr_el2::ELR_EL2; +pub use self::far_el1::FAR_EL1; pub use self::hcr_el2::HCR_EL2; pub use self::id_aa64mmfr0_el1::ID_AA64MMFR0_EL1; pub use self::mair_el1::{MAIR_EL1, MAIR_ATTR}; diff --git a/kernel/src/arch/aarch64/interrupt/handler.rs b/kernel/src/arch/aarch64/interrupt/handler.rs index 787cbf5..21142f9 100644 --- a/kernel/src/arch/aarch64/interrupt/handler.rs +++ b/kernel/src/arch/aarch64/interrupt/handler.rs @@ -2,7 +2,9 @@ use arch::board::irq::handle_irq; use super::context::TrapFrame; -use super::syndrome::Syndrome; +use super::syndrome::{Fault, Syndrome}; + +use aarch64::regs::*; global_asm!(include_str!("trap.S")); global_asm!(include_str!("vector.S")); @@ -46,7 +48,14 @@ pub extern "C" fn rust_trap(info: Info, esr: u32, tf: &mut TrapFrame) { // syndrome is only valid with sync match syndrome { Syndrome::Brk(brk) => handle_break(brk, tf), - Syndrome::Svc(_) => handle_syscall(tf), + Syndrome::Svc(svc) => handle_syscall(svc, tf), + Syndrome::DataAbort { kind, level: _ } + | Syndrome::InstructionAbort { kind, level: _ } => match kind { + Fault::Translation | Fault::AccessFlag | Fault::Permission => { + handle_page_fault(tf) + } + _ => ::trap::error(tf), + }, _ => ::trap::error(tf), } } @@ -57,12 +66,16 @@ pub extern "C" fn rust_trap(info: Info, esr: u32, tf: &mut TrapFrame) { trace!("Interrupt end"); } -fn handle_break(num: u16, tf: &mut TrapFrame) { +fn handle_break(_num: u16, tf: &mut TrapFrame) { // Skip the current brk instruction (ref: J1.1.2, page 6147) tf.elr += 4; } -fn handle_syscall(tf: &mut TrapFrame) { +fn handle_syscall(num: u16, tf: &mut TrapFrame) { + if num != 0 { + ::trap::error(tf); + } + // svc instruction has been skipped in syscall (ref: J1.1.2, page 6152) let ret = ::syscall::syscall( tf.x1to29[7] as usize, @@ -78,3 +91,10 @@ fn handle_syscall(tf: &mut TrapFrame) { ); tf.x0 = ret as usize; } + +fn handle_page_fault(tf: &mut TrapFrame) { + let addr = FAR_EL1.get(); + trace!("\nEXCEPTION: Page Fault @ {:#x}", addr); + + ::trap::error(tf); +} From 75b039c924db37c1d0c8befc76e0ac462c630b20 Mon Sep 17 00:00:00 2001 From: equation314 Date: Sat, 1 Dec 2018 22:26:55 +0800 Subject: [PATCH 16/16] aarch64/mmu: move crate aarch64 to remote --- crate/aarch64/Cargo.toml | 16 - crate/aarch64/src/addr.rs | 441 --------------- crate/aarch64/src/asm.rs | 158 ------ crate/aarch64/src/barrier.rs | 91 --- crate/aarch64/src/lib.rs | 29 - crate/aarch64/src/paging/frame_alloc.rs | 15 - crate/aarch64/src/paging/memory_attribute.rs | 64 --- crate/aarch64/src/paging/mod.rs | 549 ------------------- crate/aarch64/src/paging/page_table.rs | 267 --------- crate/aarch64/src/paging/recursive.rs | 425 -------------- crate/aarch64/src/regs/cntfrq_el0.rs | 31 -- crate/aarch64/src/regs/cnthctl_el2.rs | 75 --- crate/aarch64/src/regs/cntp_ctl_el0.rs | 62 --- crate/aarch64/src/regs/cntp_tval_el0.rs | 30 - crate/aarch64/src/regs/cntpct_el0.rs | 29 - crate/aarch64/src/regs/cntvoff_el2.rs | 32 -- crate/aarch64/src/regs/currentel.rs | 52 -- crate/aarch64/src/regs/daif.rs | 90 --- crate/aarch64/src/regs/elr_el2.rs | 30 - crate/aarch64/src/regs/far_el1.rs | 31 -- crate/aarch64/src/regs/hcr_el2.rs | 123 ----- crate/aarch64/src/regs/id_aa64mmfr0_el1.rs | 82 --- crate/aarch64/src/regs/macros.rs | 85 --- crate/aarch64/src/regs/mair_el1.rs | 82 --- crate/aarch64/src/regs/mod.rs | 55 -- crate/aarch64/src/regs/mpidr_el1.rs | 30 - crate/aarch64/src/regs/sctlr_el1.rs | 103 ---- crate/aarch64/src/regs/sp.rs | 28 - crate/aarch64/src/regs/sp_el0.rs | 31 -- crate/aarch64/src/regs/sp_el1.rs | 36 -- crate/aarch64/src/regs/spsel.rs | 48 -- crate/aarch64/src/regs/spsr_el2.rs | 106 ---- crate/aarch64/src/regs/tcr_el1.rs | 313 ----------- crate/aarch64/src/regs/ttbr0_el1.rs | 61 --- crate/aarch64/src/regs/ttbr1_el1.rs | 61 --- kernel/Cargo.lock | 6 +- kernel/Cargo.toml | 2 +- 37 files changed, 5 insertions(+), 3764 deletions(-) delete mode 100644 crate/aarch64/Cargo.toml delete mode 100644 crate/aarch64/src/addr.rs delete mode 100644 crate/aarch64/src/asm.rs delete mode 100644 crate/aarch64/src/barrier.rs delete mode 100644 crate/aarch64/src/lib.rs delete mode 100644 crate/aarch64/src/paging/frame_alloc.rs delete mode 100644 crate/aarch64/src/paging/memory_attribute.rs delete mode 100644 crate/aarch64/src/paging/mod.rs delete mode 100644 crate/aarch64/src/paging/page_table.rs delete mode 100644 crate/aarch64/src/paging/recursive.rs delete mode 100644 crate/aarch64/src/regs/cntfrq_el0.rs delete mode 100644 crate/aarch64/src/regs/cnthctl_el2.rs delete mode 100644 crate/aarch64/src/regs/cntp_ctl_el0.rs delete mode 100644 crate/aarch64/src/regs/cntp_tval_el0.rs delete mode 100644 crate/aarch64/src/regs/cntpct_el0.rs delete mode 100644 crate/aarch64/src/regs/cntvoff_el2.rs delete mode 100644 crate/aarch64/src/regs/currentel.rs delete mode 100644 crate/aarch64/src/regs/daif.rs delete mode 100644 crate/aarch64/src/regs/elr_el2.rs delete mode 100644 crate/aarch64/src/regs/far_el1.rs delete mode 100644 crate/aarch64/src/regs/hcr_el2.rs delete mode 100644 crate/aarch64/src/regs/id_aa64mmfr0_el1.rs delete mode 100644 crate/aarch64/src/regs/macros.rs delete mode 100644 crate/aarch64/src/regs/mair_el1.rs delete mode 100644 crate/aarch64/src/regs/mod.rs delete mode 100644 crate/aarch64/src/regs/mpidr_el1.rs delete mode 100644 crate/aarch64/src/regs/sctlr_el1.rs delete mode 100644 crate/aarch64/src/regs/sp.rs delete mode 100644 crate/aarch64/src/regs/sp_el0.rs delete mode 100644 crate/aarch64/src/regs/sp_el1.rs delete mode 100644 crate/aarch64/src/regs/spsel.rs delete mode 100644 crate/aarch64/src/regs/spsr_el2.rs delete mode 100644 crate/aarch64/src/regs/tcr_el1.rs delete mode 100644 crate/aarch64/src/regs/ttbr0_el1.rs delete mode 100644 crate/aarch64/src/regs/ttbr1_el1.rs diff --git a/crate/aarch64/Cargo.toml b/crate/aarch64/Cargo.toml deleted file mode 100644 index 7514dd0..0000000 --- a/crate/aarch64/Cargo.toml +++ /dev/null @@ -1,16 +0,0 @@ -[package] -name = "aarch64" -version = "0.1.0" -authors = ["koumingyang <1761674434@qq.com>"] - -[dependencies] -register = "0.2.0" -bit_field = "0.9.0" -bitflags = "1.0.1" -usize_conversions = "0.2.0" -os_bootinfo = "0.2.0" -bare-metal = "0.2.0" - -[dependencies.ux] -default-features = false -version = "0.1.0" \ No newline at end of file diff --git a/crate/aarch64/src/addr.rs b/crate/aarch64/src/addr.rs deleted file mode 100644 index cf3f092..0000000 --- a/crate/aarch64/src/addr.rs +++ /dev/null @@ -1,441 +0,0 @@ -use core::convert::{Into, TryInto}; -use core::fmt; -use core::ops::{Add, AddAssign, Sub, SubAssign}; - -use bit_field::BitField; -use usize_conversions::FromUsize; -use ux::*; - -#[derive(Debug)] -#[repr(u8)] -pub enum VirtAddrRange { - /// 0x0000000000000000 to 0x0000FFFFFFFFFFFF - BottomRange = 0, - /// 0xFFFF000000000000 to 0xFFFFFFFFFFFFFFFF. - TopRange = 1, -} - -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -#[repr(transparent)] -pub struct VirtAddr(u64); - -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -#[repr(transparent)] -pub struct PhysAddr(u64); - -#[derive(Debug)] -pub struct VirtAddrNotValid(u64); - -impl VirtAddr { - /// Creates a new canonical virtual address. - /// - /// This function performs sign extension of bit 47 to make the address canonical. Panics - /// if the bits in the range 48 to 64 contain data (i.e. are not null and no sign extension). - pub fn new(addr: u64) -> VirtAddr { - Self::try_new(addr).expect( - "invalid virtual address", - ) - } - - /// Tries to create a new canonical virtual address. - /// in aarch64, valid virtual address starts with 0x0000 or 0xffff. - pub fn try_new(addr: u64) -> Result { - match addr.get_bits(48..64) { - 0 | 0xffff => Ok(VirtAddr(addr)), // address is canonical - other => Err(VirtAddrNotValid(other)), - } - } - - pub fn new_unchecked(addr: u64) -> VirtAddr { - VirtAddr(addr) - } - - /// Creates a virtual address that points to `0`. - pub const fn zero() -> VirtAddr { - VirtAddr(0) - } - - /// Converts the address to an `u64`. - pub fn as_u64(self) -> u64 { - self.0 - } - - /// Creates a virtual address from the given pointer - pub fn from_ptr(ptr: *const T) -> Self { - use usize_conversions::FromUsize; - - Self::new(u64::from_usize(ptr as usize)) - } - - /// Converts the address to a raw pointer. - #[cfg(target_pointer_width = "64")] - pub fn as_ptr(self) -> *const T { - use usize_conversions::usize_from; - - usize_from(self.as_u64()) as *const T - } - - /// Converts the address to a mutable raw pointer. - #[cfg(target_pointer_width = "64")] - pub fn as_mut_ptr(self) -> *mut T { - self.as_ptr::() as *mut T - } - - /// Aligns the virtual address upwards to the given alignment. - /// - /// See the `align_up` function for more information. - pub fn align_up(self, align: U) -> Self - where - U: Into, - { - VirtAddr(align_up(self.0, align.into())) - } - - /// Aligns the virtual address downwards to the given alignment. - /// - /// See the `align_down` function for more information. - pub fn align_down(self, align: U) -> Self - where - U: Into, - { - VirtAddr(align_down(self.0, align.into())) - } - - /// Checks whether the virtual address has the demanded alignment. - pub fn is_aligned(self, align: U) -> bool - where - U: Into, - { - self.align_down(align) == self - } - - /// Returns the 12-bit page offset of this virtual address. - pub fn page_offset(&self) -> u12 { - u12::new((self.0 & 0xfff).try_into().unwrap()) - } - - /// Returns the VA range - pub fn va_range(&self) -> Result { - match self.va_range_bits() { - 0x0000 => Ok(VirtAddrRange::BottomRange), - 0xffff => Ok(VirtAddrRange::TopRange), - _ => Err(VirtAddrNotValid(self.0)), - } - } - - /// Returns the top 16 bits - pub fn va_range_bits(&self) -> u16 { - ((self.0 >> 48) & 0xffff) as u16 - } - - /// Returns the 9-bit level 1 page table index. - pub fn p1_index(&self) -> u9 { - u9::new(((self.0 >> 12) & 0o777).try_into().unwrap()) - } - - /// Returns the 9-bit level 2 page table index. - pub fn p2_index(&self) -> u9 { - u9::new(((self.0 >> 12 >> 9) & 0o777).try_into().unwrap()) - } - - /// Returns the 9-bit level 3 page table index. - pub fn p3_index(&self) -> u9 { - u9::new(((self.0 >> 12 >> 9 >> 9) & 0o777).try_into().unwrap()) - } - - /// Returns the 9-bit level 4 page table index. - pub fn p4_index(&self) -> u9 { - u9::new(((self.0 >> 12 >> 9 >> 9 >> 9) & 0o777).try_into().unwrap()) - } -} - -impl fmt::Debug for VirtAddr { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - write!(f, "VirtAddr({:#x})", self.0) - } -} - -impl Add for VirtAddr { - type Output = Self; - fn add(self, rhs: u64) -> Self::Output { - VirtAddr::new(self.0 + rhs) - } -} - -impl AddAssign for VirtAddr { - fn add_assign(&mut self, rhs: u64) { - *self = *self + rhs; - } -} - -impl Add for VirtAddr -where - u64: FromUsize, -{ - type Output = Self; - fn add(self, rhs: usize) -> Self::Output { - self + u64::from_usize(rhs) - } -} - -impl AddAssign for VirtAddr -where - u64: FromUsize, -{ - fn add_assign(&mut self, rhs: usize) { - self.add_assign(u64::from_usize(rhs)) - } -} - -impl Sub for VirtAddr { - type Output = Self; - fn sub(self, rhs: u64) -> Self::Output { - VirtAddr::new(self.0.checked_sub(rhs).unwrap()) - } -} - -impl SubAssign for VirtAddr { - fn sub_assign(&mut self, rhs: u64) { - *self = *self - rhs; - } -} - -impl Sub for VirtAddr -where - u64: FromUsize, -{ - type Output = Self; - fn sub(self, rhs: usize) -> Self::Output { - self - u64::from_usize(rhs) - } -} - -impl SubAssign for VirtAddr -where - u64: FromUsize, -{ - fn sub_assign(&mut self, rhs: usize) { - self.sub_assign(u64::from_usize(rhs)) - } -} - -impl Sub for VirtAddr { - type Output = u64; - fn sub(self, rhs: VirtAddr) -> Self::Output { - self.as_u64().checked_sub(rhs.as_u64()).unwrap() - } -} - -/// A passed `u64` was not a valid physical address. -/// -/// This means that bits 52 to 64 are not were not all null. -#[derive(Debug)] -pub struct PhysAddrNotValid(u64); - -impl PhysAddr { - /// Creates a new physical address. - /// - /// Panics if a bit in the range 52 to 64 is set. - pub fn new(addr: u64) -> PhysAddr { - assert_eq!( - addr.get_bits(52..64), - 0, - "physical addresses must not have any bits in the range 52 to 64 set" - ); - PhysAddr(addr) - } - - /// Tries to create a new physical address. - /// - /// Fails if any bits in the range 52 to 64 are set. - pub fn try_new(addr: u64) -> Result { - match addr.get_bits(52..64) { - 0 => Ok(PhysAddr(addr)), // address is valid - other => Err(PhysAddrNotValid(other)), - } - } - - /// Converts the address to an `u64`. - pub fn as_u64(self) -> u64 { - self.0 - } - - /// Convenience method for checking if a physical address is null. - pub fn is_null(&self) -> bool { - self.0 == 0 - } - - /// Aligns the physical address upwards to the given alignment. - /// - /// See the `align_up` function for more information. - pub fn align_up(self, align: U) -> Self - where - U: Into, - { - PhysAddr(align_up(self.0, align.into())) - } - - /// Aligns the physical address downwards to the given alignment. - /// - /// See the `align_down` function for more information. - pub fn align_down(self, align: U) -> Self - where - U: Into, - { - PhysAddr(align_down(self.0, align.into())) - } - - /// Checks whether the physical address has the demanded alignment. - pub fn is_aligned(self, align: U) -> bool - where - U: Into, - { - self.align_down(align) == self - } -} - -impl fmt::Debug for PhysAddr { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - write!(f, "PhysAddr({:#x})", self.0) - } -} - -impl fmt::Binary for PhysAddr { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - self.0.fmt(f) - } -} - -impl fmt::LowerHex for PhysAddr { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - self.0.fmt(f) - } -} - -impl fmt::Octal for PhysAddr { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - self.0.fmt(f) - } -} - -impl fmt::UpperHex for PhysAddr { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - self.0.fmt(f) - } -} - -impl Add for PhysAddr { - type Output = Self; - fn add(self, rhs: u64) -> Self::Output { - PhysAddr::new(self.0 + rhs) - } -} - -impl AddAssign for PhysAddr { - fn add_assign(&mut self, rhs: u64) { - *self = *self + rhs; - } -} - -impl Add for PhysAddr -where - u64: FromUsize, -{ - type Output = Self; - fn add(self, rhs: usize) -> Self::Output { - self + u64::from_usize(rhs) - } -} - -impl AddAssign for PhysAddr -where - u64: FromUsize, -{ - fn add_assign(&mut self, rhs: usize) { - self.add_assign(u64::from_usize(rhs)) - } -} - -impl Sub for PhysAddr { - type Output = Self; - fn sub(self, rhs: u64) -> Self::Output { - PhysAddr::new(self.0.checked_sub(rhs).unwrap()) - } -} - -impl SubAssign for PhysAddr { - fn sub_assign(&mut self, rhs: u64) { - *self = *self - rhs; - } -} - -impl Sub for PhysAddr -where - u64: FromUsize, -{ - type Output = Self; - fn sub(self, rhs: usize) -> Self::Output { - self - u64::from_usize(rhs) - } -} - -impl SubAssign for PhysAddr -where - u64: FromUsize, -{ - fn sub_assign(&mut self, rhs: usize) { - self.sub_assign(u64::from_usize(rhs)) - } -} - -impl Sub for PhysAddr { - type Output = u64; - fn sub(self, rhs: PhysAddr) -> Self::Output { - self.as_u64().checked_sub(rhs.as_u64()).unwrap() - } -} - -/// Align address downwards. -/// -/// Returns the greatest x with alignment `align` so that x <= addr. The alignment must be -/// a power of 2. -pub fn align_down(addr: u64, align: u64) -> u64 { - assert!(align.is_power_of_two(), "`align` must be a power of two"); - addr & !(align - 1) -} - -/// Align address upwards. -/// -/// Returns the smallest x with alignment `align` so that x >= addr. The alignment must be -/// a power of 2. -pub fn align_up(addr: u64, align: u64) -> u64 { - assert!(align.is_power_of_two(), "`align` must be a power of two"); - let align_mask = align - 1; - if addr & align_mask == 0 { - addr // already aligned - } else { - (addr | align_mask) + 1 - } -} - -#[cfg(test)] -mod tests { - use super::*; - - #[test] - pub fn test_align_up() { - // align 1 - assert_eq!(align_up(0, 1), 0); - assert_eq!(align_up(1234, 1), 1234); - assert_eq!(align_up(0xffffffffffffffff, 1), 0xffffffffffffffff); - // align 2 - assert_eq!(align_up(0, 2), 0); - assert_eq!(align_up(1233, 2), 1234); - assert_eq!(align_up(0xfffffffffffffffe, 2), 0xfffffffffffffffe); - // address 0 - assert_eq!(align_up(0, 128), 0); - assert_eq!(align_up(0, 1), 0); - assert_eq!(align_up(0, 2), 0); - assert_eq!(align_up(0, 0x8000000000000000), 0); - } -} diff --git a/crate/aarch64/src/asm.rs b/crate/aarch64/src/asm.rs deleted file mode 100644 index bada049..0000000 --- a/crate/aarch64/src/asm.rs +++ /dev/null @@ -1,158 +0,0 @@ -//! Miscellaneous assembly instructions and functions - -use paging::PhysFrame; -use addr::{PhysAddr, VirtAddr}; -use regs::*; - -/// Returns the current stack pointer. -#[inline(always)] -pub fn sp() -> *const u8 { - let ptr: usize; - unsafe { - asm!("mov $0, sp" : "=r"(ptr)); - } - - ptr as *const u8 -} - -/// Returns the current point counter. -#[inline(always)] -pub unsafe fn get_pc() -> usize { - let pc: usize; - asm!("adr $0, ." : "=r"(pc)); - pc -} - -/// The classic no-op -#[inline] -pub fn nop() { - match () { - #[cfg(target_arch = "aarch64")] - () => unsafe { asm!("nop" :::: "volatile") }, - - #[cfg(not(target_arch = "aarch64"))] - () => unimplemented!(), - } -} - -/// Wait For Interrupt -#[inline] -pub fn wfi() { - match () { - #[cfg(target_arch = "aarch64")] - () => unsafe { asm!("wfi" :::: "volatile") }, - - #[cfg(not(target_arch = "aarch64"))] - () => unimplemented!(), - } -} - -/// Wait For Event -#[inline] -pub fn wfe() { - match () { - #[cfg(target_arch = "aarch64")] - () => unsafe { asm!("wfe" :::: "volatile") }, - - #[cfg(not(target_arch = "aarch64"))] - () => unimplemented!(), - } -} - -/// Exception return -/// -/// Will jump to wherever the corresponding link register points to, and -/// therefore never return. -#[inline] -pub fn eret() -> ! { - use core; - - match () { - #[cfg(target_arch = "aarch64")] - () => unsafe { - asm!("eret" :::: "volatile"); - core::intrinsics::unreachable() - }, - - #[cfg(not(target_arch = "aarch64"))] - () => unimplemented!(), - } -} - -/// Invalidate all TLB entries. -#[inline(always)] -pub fn tlb_invalidate_all() { - unsafe { - asm!( - "dsb ishst - tlbi vmalle1is - dsb ish - isb" - ); - } -} - -/// Invalidate TLB entries that would be used to translate the specified address. -#[inline(always)] -pub fn tlb_invalidate(vaddr: VirtAddr) { - unsafe { - asm!( - "dsb ishst - tlbi vaae1is, $0 - dsb ish - isb" :: "r"(vaddr.as_u64() >> 12) - ); - } -} - -/// Invalidate all instruction caches in Inner Shareable domain to Point of Unification. -#[inline(always)] -pub fn flush_icache_all() { - unsafe { - asm!( - "ic ialluis - dsb ish - isb" - ); - } -} - -/// Address Translate. -#[inline(always)] -pub fn address_translate(vaddr: usize) -> usize { - let paddr: usize; - unsafe { - asm!("at S1E1R, $1; mrs $0, par_el1" : "=r"(paddr) : "r"(vaddr)); - } - paddr -} - -/// Read TTBRx_EL1 as PhysFrame -pub fn ttbr_el1_read(which: u8) -> PhysFrame { - let baddr = match which { - 0 => TTBR0_EL1.get_baddr(), - 1 => TTBR1_EL1.get_baddr(), - _ => 0, - }; - PhysFrame::containing_address(PhysAddr::new(baddr)) -} - -/// Write TTBRx_EL1 from PhysFrame -pub fn ttbr_el1_write(which: u8, frame: PhysFrame) { - let baddr = frame.start_address().as_u64(); - match which { - 0 => TTBR0_EL1.set_baddr(baddr), - 1 => TTBR1_EL1.set_baddr(baddr), - _ => {} - }; -} - -/// write TTBRx_EL1 from PhysFrame and ASID -pub fn ttbr_el1_write_asid(which: u8, asid: u16, frame: PhysFrame) { - let baddr = frame.start_address().as_u64(); - match which { - 0 => TTBR0_EL1.write(TTBR0_EL1::ASID.val(asid as u64) + TTBR0_EL1::BADDR.val(baddr >> 1)), - 1 => TTBR1_EL1.write(TTBR1_EL1::ASID.val(asid as u64) + TTBR1_EL1::BADDR.val(baddr >> 1)), - _ => {} - }; -} diff --git a/crate/aarch64/src/barrier.rs b/crate/aarch64/src/barrier.rs deleted file mode 100644 index 3211480..0000000 --- a/crate/aarch64/src/barrier.rs +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -// Borrow implementations from the pending upstream ACLE implementation until it -// is merged. Afterwards, we'll probably just reexport them, hoping that the API -// doesn't change. -// -// https://github.com/rust-lang-nursery/stdsimd/pull/557 - -mod sealed { - pub trait Dmb { - unsafe fn __dmb(&self); - } - - pub trait Dsb { - unsafe fn __dsb(&self); - } - - pub trait Isb { - unsafe fn __isb(&self); - } -} - -macro_rules! dmb_dsb { - ($A:ident) => { - impl sealed::Dmb for $A { - #[inline(always)] - unsafe fn __dmb(&self) { - asm!(concat!("DMB ", stringify!($A)) : : : "memory" : "volatile") - } - } - impl sealed::Dsb for $A { - #[inline(always)] - unsafe fn __dsb(&self) { - asm!(concat!("DSB ", stringify!($A)) : : : "memory" : "volatile") - } - } - }; -} - -pub struct SY; -pub struct ISH; -pub struct ISHST; - -dmb_dsb!(SY); -dmb_dsb!(ISH); -dmb_dsb!(ISHST); - -impl sealed::Isb for SY { - #[inline(always)] - unsafe fn __isb(&self) { - asm!("ISB SY" : : : "memory" : "volatile") - } -} - -#[inline(always)] -pub unsafe fn dmb(arg: A) -where - A: sealed::Dmb, -{ - arg.__dmb() -} - -#[inline(always)] -pub unsafe fn dsb(arg: A) -where - A: sealed::Dsb, -{ - arg.__dsb() -} - -#[inline(always)] -pub unsafe fn isb(arg: A) -where - A: sealed::Isb, -{ - arg.__isb() -} diff --git a/crate/aarch64/src/lib.rs b/crate/aarch64/src/lib.rs deleted file mode 100644 index bb8bf72..0000000 --- a/crate/aarch64/src/lib.rs +++ /dev/null @@ -1,29 +0,0 @@ -#![no_std] -//#![deny(warnings)] -#![feature(asm)] -#![feature(const_fn)] -#![feature(core_intrinsics)] -#![feature(try_from)] - -extern crate bare_metal; -#[macro_use] -extern crate register; -#[macro_use] -extern crate bitflags; -extern crate bit_field; -extern crate os_bootinfo; -extern crate usize_conversions; - -/// Provides the non-standard-width integer types `u2`–`u63`. -/// -/// We use these integer types in various APIs, for example `u9` for page tables indices. -pub extern crate ux; - -pub use addr::{align_down, align_up, PhysAddr, VirtAddr}; - -pub mod asm; -pub mod addr; -pub mod paging; -pub mod barrier; -pub mod regs; - diff --git a/crate/aarch64/src/paging/frame_alloc.rs b/crate/aarch64/src/paging/frame_alloc.rs deleted file mode 100644 index f3ea4c8..0000000 --- a/crate/aarch64/src/paging/frame_alloc.rs +++ /dev/null @@ -1,15 +0,0 @@ -//! Traits for abstracting away frame allocation and deallocation. - -use paging::{PageSize, PhysFrame}; - -/// A trait for types that can allocate a frame of memory. -pub trait FrameAllocator { - /// Allocate a frame of the appropriate size and return it if possible. - fn alloc(&mut self) -> Option>; -} - -/// A trait for types that can deallocate a frame of memory. -pub trait FrameDeallocator { - /// Deallocate the given frame of memory. - fn dealloc(&mut self, frame: PhysFrame); -} diff --git a/crate/aarch64/src/paging/memory_attribute.rs b/crate/aarch64/src/paging/memory_attribute.rs deleted file mode 100644 index 4a24071..0000000 --- a/crate/aarch64/src/paging/memory_attribute.rs +++ /dev/null @@ -1,64 +0,0 @@ -//!Memory region attributes (D4.5, page 2174) - -use super::{PageTableAttribute, MEMORY_ATTRIBUTE}; -use regs::*; - -pub trait MairType { - const INDEX: u64; - - #[inline] - fn config_value() -> u64; - - #[inline] - fn attr_value() -> PageTableAttribute; -} - -pub enum MairDevice {} -pub enum MairNormal {} -pub enum MairNormalNonCacheable {} - -impl MairType for MairDevice { - const INDEX: u64 = 0; - - #[inline] - fn config_value() -> u64 { - (MAIR_ATTR::Attr_HIGH::Device + MAIR_ATTR::Attr_LOW_DEVICE::Device_nGnRE).value - } - - #[inline] - fn attr_value() -> PageTableAttribute { - MEMORY_ATTRIBUTE::SH::OuterShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) - } -} - -impl MairType for MairNormal { - const INDEX: u64 = 1; - - #[inline] - fn config_value() -> u64 { - (MAIR_ATTR::Attr_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc - + MAIR_ATTR::Attr_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc) - .value - } - - #[inline] - fn attr_value() -> PageTableAttribute { - MEMORY_ATTRIBUTE::SH::InnerShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) - } -} - -impl MairType for MairNormalNonCacheable { - const INDEX: u64 = 2; - - #[inline] - fn config_value() -> u64 { - (MAIR_ATTR::Attr_HIGH::Memory_OuterNonCacheable - + MAIR_ATTR::Attr_LOW_MEMORY::InnerNonCacheable) - .value - } - - #[inline] - fn attr_value() -> PageTableAttribute { - MEMORY_ATTRIBUTE::SH::OuterShareable + MEMORY_ATTRIBUTE::AttrIndx.val(Self::INDEX) - } -} diff --git a/crate/aarch64/src/paging/mod.rs b/crate/aarch64/src/paging/mod.rs deleted file mode 100644 index 552d6f6..0000000 --- a/crate/aarch64/src/paging/mod.rs +++ /dev/null @@ -1,549 +0,0 @@ -//! Abstractions for page tables and other paging related structures. -//! -//! Page tables translate virtual memory “pages” to physical memory “frames”. - -pub use self::frame_alloc::*; -pub use self::page_table::*; -#[cfg(target_arch = "aarch64")] -pub use self::recursive::*; - -use core::fmt; -use core::marker::PhantomData; -use core::ops::{Add, AddAssign, Sub, SubAssign}; -use os_bootinfo; -use ux::*; -use addr::{PhysAddr, VirtAddr}; - -mod frame_alloc; -mod page_table; -mod recursive; - -pub mod memory_attribute; - -/// Trait for abstracting over the three possible block/page sizes on aarch64, 4KiB, 2MiB, 1GiB. -pub trait PageSize: Copy + Eq + PartialOrd + Ord { - /// The page size in bytes. - const SIZE: u64; - - /// A string representation of the page size for debug output. - const SIZE_AS_DEBUG_STR: &'static str; -} - -/// This trait is implemented for 4KiB and 2MiB pages, but not for 1GiB pages. -pub trait NotGiantPageSize: PageSize {} - -/// A standard 4KiB page. -#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -pub enum Size4KiB {} - -/// A “huge” 2MiB page. -#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -pub enum Size2MiB {} - -/// A “giant” 1GiB page. -#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -pub enum Size1GiB {} - -impl PageSize for Size4KiB { - const SIZE: u64 = 4096; - const SIZE_AS_DEBUG_STR: &'static str = "4KiB"; -} - -impl NotGiantPageSize for Size4KiB {} - -impl PageSize for Size2MiB { - const SIZE: u64 = Size4KiB::SIZE * 512; - const SIZE_AS_DEBUG_STR: &'static str = "2MiB"; -} - -impl NotGiantPageSize for Size2MiB {} - -impl PageSize for Size1GiB { - const SIZE: u64 = Size2MiB::SIZE * 512; - const SIZE_AS_DEBUG_STR: &'static str = "1GiB"; -} - -/// A virtual memory page. -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -#[repr(C)] -pub struct Page { - start_address: VirtAddr, - size: PhantomData, -} - -impl Page { - /// Returns the page that starts at the given virtual address. - /// - /// Returns an error if the address is not correctly aligned (i.e. is not a valid page start). - pub fn from_start_address(address: VirtAddr) -> Result { - if !address.is_aligned(S::SIZE) { - return Err(()); - } - Ok(Page::containing_address(address)) - } - - /// Returns the page that contains the given virtual address. - pub fn containing_address(address: VirtAddr) -> Self { - Page { - start_address: address.align_down(S::SIZE), - size: PhantomData, - } - } - - /// Returns the start address of the page. - pub fn start_address(&self) -> VirtAddr { - self.start_address - } - - /// Returns the size the page (4KB, 2MB or 1GB). - pub const fn size(&self) -> u64 { - S::SIZE - } - - /// Returns the level 4 page table index of this page. - pub fn va_range_bits(&self) -> u16 { - self.start_address().va_range_bits() - } - - /// Returns the level 4 page table index of this page. - pub fn p4_index(&self) -> u9 { - self.start_address().p4_index() - } - - /// Returns the level 3 page table index of this page. - pub fn p3_index(&self) -> u9 { - self.start_address().p3_index() - } - - /// Returns a range of pages, exclusive `end`. - pub fn range(start: Self, end: Self) -> PageRange { - PageRange { start, end } - } - - /// Returns a range of pages, inclusive `end`. - pub fn range_inclusive(start: Self, end: Self) -> PageRangeInclusive { - PageRangeInclusive { start, end } - } - - pub fn of_addr(address: usize) -> Self { - Self::containing_address(VirtAddr::new(address as u64)) - } - - pub fn range_of(begin: usize, end: usize) -> PageRange { - Self::range(Page::of_addr(begin), Page::of_addr(end - 1) + 1) - } -} - -impl Page { - /// Returns the level 2 page table index of this page. - pub fn p2_index(&self) -> u9 { - self.start_address().p2_index() - } -} - -impl Page { - /// Returns the 1GiB memory page with the specified page table indices. - pub fn from_page_table_indices_1gib(p4_index: u9, p3_index: u9) -> Self { - use bit_field::BitField; - - let mut addr = 0; - addr.set_bits(39..48, u64::from(p4_index)); - addr.set_bits(30..39, u64::from(p3_index)); - Page::containing_address(VirtAddr::new(addr)) - } -} - -impl Page { - /// Returns the 2MiB memory page with the specified page table indices. - pub fn from_page_table_indices_2mib(p4_index: u9, p3_index: u9, p2_index: u9) -> Self { - use bit_field::BitField; - - let mut addr = 0; - addr.set_bits(39..48, u64::from(p4_index)); - addr.set_bits(30..39, u64::from(p3_index)); - addr.set_bits(21..30, u64::from(p2_index)); - Page::containing_address(VirtAddr::new(addr)) - } -} - -impl Page { - /// Returns the 4KiB memory page with the specified page table indices. - pub fn from_page_table_indices(p4_index: u9, p3_index: u9, p2_index: u9, p1_index: u9) -> Self { - use bit_field::BitField; - - let mut addr = 0; - addr.set_bits(39..48, u64::from(p4_index)); - addr.set_bits(30..39, u64::from(p3_index)); - addr.set_bits(21..30, u64::from(p2_index)); - addr.set_bits(12..21, u64::from(p1_index)); - Page::containing_address(VirtAddr::new(addr)) - } - - /// Returns the level 1 page table index of this page. - pub fn p1_index(&self) -> u9 { - self.start_address().p1_index() - } -} - -impl fmt::Debug for Page { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.write_fmt(format_args!( - "Page[{}]({:#x})", - S::SIZE_AS_DEBUG_STR, - self.start_address().as_u64() - )) - } -} - -impl Add for Page { - type Output = Self; - fn add(self, rhs: u64) -> Self::Output { - Page::containing_address(self.start_address() + rhs * u64::from(S::SIZE)) - } -} - -impl AddAssign for Page { - fn add_assign(&mut self, rhs: u64) { - *self = self.clone() + rhs; - } -} - -impl Sub for Page { - type Output = Self; - fn sub(self, rhs: u64) -> Self::Output { - Page::containing_address(self.start_address() - rhs * u64::from(S::SIZE)) - } -} - -impl SubAssign for Page { - fn sub_assign(&mut self, rhs: u64) { - *self = self.clone() - rhs; - } -} - -impl Sub for Page { - type Output = u64; - fn sub(self, rhs: Self) -> Self::Output { - (self.start_address - rhs.start_address) / S::SIZE - } -} - -/// A range of pages with exclusive upper bound. -#[derive(Clone, Copy, PartialEq, Eq)] -#[repr(C)] -pub struct PageRange { - /// The start of the range, inclusive. - pub start: Page, - /// The end of the range, exclusive. - pub end: Page, -} - -impl PageRange { - /// Returns wether this range contains no pages. - pub fn is_empty(&self) -> bool { - !(self.start < self.end) - } -} - -impl Iterator for PageRange { - type Item = Page; - - fn next(&mut self) -> Option { - if self.start < self.end { - let page = self.start.clone(); - self.start += 1; - Some(page) - } else { - None - } - } -} - -impl PageRange { - /// Converts the range of 2MiB pages to a range of 4KiB pages. - pub fn as_4kib_page_range(self) -> PageRange { - PageRange { - start: Page::containing_address(self.start.start_address()), - end: Page::containing_address(self.end.start_address()), - } - } -} - -impl fmt::Debug for PageRange { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.debug_struct("PageRange") - .field("start", &self.start) - .field("end", &self.end) - .finish() - } -} - -/// A range of pages with inclusive upper bound. -#[derive(Clone, Copy, PartialEq, Eq)] -#[repr(C)] -pub struct PageRangeInclusive { - /// The start of the range, inclusive. - pub start: Page, - /// The end of the range, inclusive. - pub end: Page, -} - -impl PageRangeInclusive { - /// Returns wether this range contains no pages. - pub fn is_empty(&self) -> bool { - !(self.start <= self.end) - } -} - -impl Iterator for PageRangeInclusive { - type Item = Page; - - fn next(&mut self) -> Option { - if self.start <= self.end { - let page = self.start.clone(); - self.start += 1; - Some(page) - } else { - None - } - } -} - -impl fmt::Debug for PageRangeInclusive { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.debug_struct("PageRangeInclusive") - .field("start", &self.start) - .field("end", &self.end) - .finish() - } -} - -/// A physical memory frame. -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -#[repr(C)] -pub struct PhysFrame { - start_address: PhysAddr, - size: PhantomData, -} - -impl PhysFrame { - /// Returns the frame that starts at the given virtual address. - /// - /// Returns an error if the address is not correctly aligned (i.e. is not a valid frame start). - pub fn from_start_address(address: PhysAddr) -> Result { - if !address.is_aligned(S::SIZE) { - return Err(()); - } - Ok(PhysFrame::containing_address(address)) - } - - /// Returns the frame that contains the given physical address. - pub fn containing_address(address: PhysAddr) -> Self { - PhysFrame { - start_address: address.align_down(S::SIZE), - size: PhantomData, - } - } - - /// Returns the start address of the frame. - pub fn start_address(&self) -> PhysAddr { - self.start_address - } - - /// Returns the size the frame (4KB, 2MB or 1GB). - pub fn size(&self) -> u64 { - S::SIZE - } - - /// Returns a range of frames, exclusive `end`. - pub fn range(start: PhysFrame, end: PhysFrame) -> PhysFrameRange { - PhysFrameRange { start, end } - } - - /// Returns a range of frames, inclusive `end`. - pub fn range_inclusive(start: PhysFrame, end: PhysFrame) -> PhysFrameRangeInclusive { - PhysFrameRangeInclusive { start, end } - } - - pub fn of_addr(address: usize) -> Self { - Self::containing_address(PhysAddr::new(address as u64)) - } - - pub fn range_of(begin: usize, end: usize) -> PhysFrameRange { - Self::range(Self::of_addr(begin), Self::of_addr(end - 1) + 1) - } -} - -impl fmt::Debug for PhysFrame { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.write_fmt(format_args!( - "PhysFrame[{}]({:#x})", - S::SIZE_AS_DEBUG_STR, - self.start_address().as_u64() - )) - } -} - -impl Add for PhysFrame { - type Output = Self; - fn add(self, rhs: u64) -> Self::Output { - PhysFrame::containing_address(self.start_address() + rhs * u64::from(S::SIZE)) - } -} - -impl AddAssign for PhysFrame { - fn add_assign(&mut self, rhs: u64) { - *self = self.clone() + rhs; - } -} - -impl Sub for PhysFrame { - type Output = Self; - fn sub(self, rhs: u64) -> Self::Output { - PhysFrame::containing_address(self.start_address() - rhs * u64::from(S::SIZE)) - } -} - -impl SubAssign for PhysFrame { - fn sub_assign(&mut self, rhs: u64) { - *self = self.clone() - rhs; - } -} - -impl Sub> for PhysFrame { - type Output = u64; - fn sub(self, rhs: PhysFrame) -> Self::Output { - (self.start_address - rhs.start_address) / S::SIZE - } -} - -/// An range of physical memory frames, exclusive the upper bound. -#[derive(Clone, Copy, PartialEq, Eq)] -#[repr(C)] -pub struct PhysFrameRange { - /// The start of the range, inclusive. - pub start: PhysFrame, - /// The end of the range, exclusive. - pub end: PhysFrame, -} - -impl PhysFrameRange { - /// Returns whether the range contains no frames. - pub fn is_empty(&self) -> bool { - !(self.start < self.end) - } -} - -impl Iterator for PhysFrameRange { - type Item = PhysFrame; - - fn next(&mut self) -> Option { - if self.start < self.end { - let frame = self.start.clone(); - self.start += 1; - Some(frame) - } else { - None - } - } -} - -impl From for PhysFrameRange { - fn from(range: os_bootinfo::FrameRange) -> Self { - PhysFrameRange { - start: PhysFrame::from_start_address(PhysAddr::new(range.start_addr())).unwrap(), - end: PhysFrame::from_start_address(PhysAddr::new(range.end_addr())).unwrap(), - } - } -} - -impl Into for PhysFrameRange { - fn into(self) -> os_bootinfo::FrameRange { - os_bootinfo::FrameRange::new( - self.start.start_address().as_u64(), - self.end.start_address().as_u64(), - ) - } -} - -impl fmt::Debug for PhysFrameRange { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.debug_struct("PhysFrameRange") - .field("start", &self.start) - .field("end", &self.end) - .finish() - } -} - -/// An range of physical memory frames, inclusive the upper bound. -#[derive(Clone, Copy, PartialEq, Eq)] -#[repr(C)] -pub struct PhysFrameRangeInclusive { - /// The start of the range, inclusive. - pub start: PhysFrame, - /// The start of the range, exclusive. - pub end: PhysFrame, -} - -impl PhysFrameRangeInclusive { - /// Returns whether the range contains no frames. - pub fn is_empty(&self) -> bool { - !(self.start <= self.end) - } -} - -impl Iterator for PhysFrameRangeInclusive { - type Item = PhysFrame; - - fn next(&mut self) -> Option { - if self.start <= self.end { - let frame = self.start.clone(); - self.start += 1; - Some(frame) - } else { - None - } - } -} - -impl fmt::Debug for PhysFrameRangeInclusive { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.debug_struct("PhysFrameRangeInclusive") - .field("start", &self.start) - .field("end", &self.end) - .finish() - } -} - -#[cfg(test)] -mod tests { - use super::*; - - #[test] - pub fn test_page_ranges() { - let page_size = Size4KiB::SIZE; - let number = 1000; - - let start_addr = VirtAddr::new(0xdeadbeaf); - let start: Page = Page::containing_address(start_addr); - let end = start.clone() + number; - - let mut range = Page::range(start.clone(), end.clone()); - for i in 0..number { - assert_eq!( - range.next(), - Some(Page::containing_address(start_addr + page_size * i)) - ); - } - assert_eq!(range.next(), None); - - let mut range_inclusive = Page::range_inclusive(start, end); - for i in 0..=number { - assert_eq!( - range_inclusive.next(), - Some(Page::containing_address(start_addr + page_size * i)) - ); - } - assert_eq!(range_inclusive.next(), None); - } -} diff --git a/crate/aarch64/src/paging/page_table.rs b/crate/aarch64/src/paging/page_table.rs deleted file mode 100644 index 6d33fa6..0000000 --- a/crate/aarch64/src/paging/page_table.rs +++ /dev/null @@ -1,267 +0,0 @@ -use core::fmt; -use core::ops::{Index, IndexMut}; - -use super::{PhysFrame, PageSize}; -use addr::PhysAddr; - -use usize_conversions::usize_from; -use ux::*; - -use register::FieldValue; -use register::cpu::RegisterReadWrite; - -/// Memory attribute fields mask -const MEMORY_ATTR_MASK: u64 = (MEMORY_ATTRIBUTE::SH.mask << MEMORY_ATTRIBUTE::SH.shift) - | (MEMORY_ATTRIBUTE::AttrIndx.mask << MEMORY_ATTRIBUTE::AttrIndx.shift); -/// Output address mask -const ADDR_MASK: u64 = 0x0000_ffff_ffff_f000; -/// Other flags mask -const FLAGS_MASK: u64 = !(MEMORY_ATTR_MASK | ADDR_MASK); - -/// Memory attribute fields -pub type PageTableAttribute = FieldValue; - -/// The error returned by the `PageTableEntry::frame` method. -#[derive(Debug, Clone, Copy, PartialEq)] -pub enum FrameError { - /// The entry does not have the `PRESENT` flag set, so it isn't currently mapped to a frame. - FrameNotPresent, - /// The entry does have the `HUGE_PAGE` flag set. The `frame` method has a standard 4KiB frame - /// as return type, so a huge frame can't be returned. - HugeFrame, -} - -/// A 64-bit page table entry. -#[derive(Clone)] -#[repr(transparent)] -pub struct PageTableEntry { - pub entry: u64, -} - -impl RegisterReadWrite for PageTableEntry { - #[inline] - fn get(&self) -> u64 { - self.entry - } - - #[inline] - fn set(&self, value: u64) { - unsafe { *(&self.entry as *const u64 as *mut u64) = value } - } -} - -impl PageTableEntry { - /// Returns whether this entry is zero. - #[inline] - pub fn is_unused(&self) -> bool { - self.entry == 0 - } - - /// Sets this entry to zero. - #[inline] - pub fn set_unused(&mut self) { - self.entry = 0; - } - - /// Returns the flags of this entry. - #[inline] - pub fn flags(&self) -> PageTableFlags { - PageTableFlags::from_bits_truncate(self.entry) - } - - /// Returns the physical address mapped by this entry, might be zero. - #[inline] - pub fn addr(&self) -> PhysAddr { - PhysAddr::new(self.entry & ADDR_MASK) - } - - /// Returns the memory attribute fields of this entry. - #[inline] - pub fn attr(&self) -> PageTableAttribute { - PageTableAttribute::new(MEMORY_ATTR_MASK, 0, self.entry & MEMORY_ATTR_MASK) - } - - /// Returns the physical frame mapped by this entry. - /// - /// Returns the following errors: - /// - /// - `FrameError::FrameNotPresent` if the entry doesn't have the `PRESENT` flag set. - /// - `FrameError::HugeFrame` if the entry has the `HUGE_PAGE` flag set (for huge pages the - /// `addr` function must be used) - pub fn frame(&self) -> Result { - if !self.flags().contains(PageTableFlags::VALID) { - Err(FrameError::FrameNotPresent) - } else if !self.flags().contains(PageTableFlags::TABLE_OR_PAGE) { - // is a huge page (block) - Err(FrameError::HugeFrame) - } else { - Ok(PhysFrame::containing_address(self.addr())) - } - } - - /// Map the entry to the specified physical frame with the specified flags and memory attribute. - pub fn set_frame(&mut self, frame: PhysFrame, flags: PageTableFlags, attr: PageTableAttribute) { - // is not a block - assert!(flags.contains(PageTableFlags::TABLE_OR_PAGE)); - self.set(frame.start_address().as_u64() | flags.bits() | attr.value); - } - - /// The descriptor gives the base address of a block of memory, and the attributes for that - /// memory region. - pub fn set_block(&mut self, addr: PhysAddr, flags: PageTableFlags, attr: PageTableAttribute) { - // is a block - assert!(!flags.contains(PageTableFlags::TABLE_OR_PAGE)); - self.set(addr.align_down(S::SIZE).as_u64() | flags.bits() | attr.value); - } - - /// Map the entry to the specified physical address with the specified flags. - pub fn modify_addr(&mut self, addr: PhysAddr) { - self.entry = (self.entry & !ADDR_MASK) | addr.as_u64(); - } - - /// Sets the flags of this entry. - pub fn modify_flags(&mut self, flags: PageTableFlags) { - self.entry = (self.entry & !FLAGS_MASK) | flags.bits(); - } - - /// Sets the flags of this entry. - pub fn modify_attr(&mut self, attr: PageTableAttribute) { - self.entry = (self.entry & !MEMORY_ATTR_MASK) | attr.value; - } -} - -impl fmt::Debug for PageTableEntry { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - let mut f = f.debug_struct("PageTableEntry"); - f.field("value", &self.entry); - f.field("addr", &self.addr()); - f.field("flags", &self.flags()); - f.field("attr", &self.attr().value); - f.finish() - } -} - -register_bitfields! {u64, - // Memory attribute fields in the VMSAv8-64 translation table format descriptors (Page 2148~2152) - MEMORY_ATTRIBUTE [ - /// Shareability field - SH OFFSET(8) NUMBITS(2) [ - NonShareable = 0b00, - OuterShareable = 0b10, - InnerShareable = 0b11 - ], - - /// Memory attributes index into the MAIR_EL1 register - AttrIndx OFFSET(2) NUMBITS(3) [] - ] -} - -bitflags! { - /// Possible flags for a page table entry. - pub struct PageTableFlags: u64 { - /// identifies whether the descriptor is valid - const VALID = 1 << 0; - /// the descriptor type - /// 0, Block - /// 1, Table/Page - const TABLE_OR_PAGE = 1 << 1; - /// Access permission: accessable at EL0 - const AP_EL0 = 1 << 6; - /// Access permission: read-only - const AP_RO = 1 << 7; - /// Access flag - const AF = 1 << 10; - /// not global bit - const nG = 1 << 11; - /// Dirty Bit Modifier - const DBM = 1 << 51; - - /// A hint bit indicating that the translation table entry is one of a contiguous set or - /// entries - const Contiguous = 1 << 52; - /// Privileged Execute-never - const PXN = 1 << 53; - /// Execute-never/Unprivileged execute-never - const XN = 1 << 54; - - /// Software Dirty Bit Modifier - const WRITE = 1 << 51; - /// Software dirty bit - const DIRTY = 1 << 55; - /// Software swapped bit - const SWAPPED = 1 << 56; - /// Software writable shared bit for COW - const WRITABLE_SHARED = 1 << 57; - /// Software readonly shared bit for COW - const READONLY_SHARED = 1 << 58; - - /// Privileged Execute-never for table descriptors - const PXNTable = 1 << 59; - /// Execute-never/Unprivileged execute-never for table descriptors - const XNTable = 1 << 60; - } -} - -impl Default for PageTableFlags { - #[inline] - fn default() -> Self { - Self::VALID | Self::TABLE_OR_PAGE | Self::AF | Self::WRITE | Self::PXN | Self::XN - } -} - -/// The number of entries in a page table. -const ENTRY_COUNT: usize = 512; - -/// Represents a page table. -/// -/// Always page-sized. -/// -/// This struct implements the `Index` and `IndexMut` traits, so the entries can be accessed -/// through index operations. For example, `page_table[15]` returns the 15th page table entry. -#[repr(transparent)] -pub struct PageTable { - entries: [PageTableEntry; ENTRY_COUNT], -} - -impl PageTable { - /// Clears all entries. - pub fn zero(&mut self) { - for entry in self.entries.iter_mut() { - entry.set_unused(); - } - } -} - -impl Index for PageTable { - type Output = PageTableEntry; - - fn index(&self, index: usize) -> &Self::Output { - &self.entries[index] - } -} - -impl IndexMut for PageTable { - fn index_mut(&mut self, index: usize) -> &mut Self::Output { - &mut self.entries[index] - } -} - -impl Index for PageTable { - type Output = PageTableEntry; - - fn index(&self, index: u9) -> &Self::Output { - &self.entries[usize_from(u16::from(index))] - } -} - -impl IndexMut for PageTable { - fn index_mut(&mut self, index: u9) -> &mut Self::Output { - &mut self.entries[usize_from(u16::from(index))] - } -} - -impl fmt::Debug for PageTable { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - self.entries[..].fmt(f) - } -} diff --git a/crate/aarch64/src/paging/recursive.rs b/crate/aarch64/src/paging/recursive.rs deleted file mode 100644 index a1633ff..0000000 --- a/crate/aarch64/src/paging/recursive.rs +++ /dev/null @@ -1,425 +0,0 @@ -#![cfg(target_arch = "aarch64")] - -use paging::{ - frame_alloc::FrameAllocator, - page_table::{FrameError, PageTable, PageTableEntry, PageTableFlags}, - NotGiantPageSize, Page, PageSize, PhysFrame, Size4KiB, -}; -use paging::{page_table::PageTableFlags as Flags, PageTableAttribute, memory_attribute::*}; -use asm::{ttbr_el1_read, tlb_invalidate}; -use barrier; -use ux::u9; -use addr::{PhysAddr, VirtAddr}; - -/// This type represents a page whose mapping has changed in the page table. -/// -/// The old mapping might be still cached in the translation lookaside buffer (TLB), so it needs -/// to be flushed from the TLB before it's accessed. This type is returned from function that -/// change the mapping of a page to ensure that the TLB flush is not forgotten. -#[derive(Debug)] -#[must_use = "Page Table changes must be flushed or ignored."] -pub struct MapperFlush(Page); - -impl MapperFlush { - /// Create a new flush promise - fn new(page: Page) -> Self { - MapperFlush(page) - } - - /// Flush the page from the TLB to ensure that the newest mapping is used. - pub fn flush(self) { - tlb_invalidate(self.0.start_address()); - } - - /// Don't flush the TLB and silence the “must be used” warning. - pub fn ignore(self) {} -} - -/// A trait for common page table operations. -pub trait Mapper { - /// Creates a new mapping in the page table. - /// - /// This function might need additional physical frames to create new page tables. These - /// frames are allocated from the `allocator` argument. At most three frames are required. - fn map_to( - &mut self, - page: Page, - frame: PhysFrame, - flags: PageTableFlags, - attr: PageTableAttribute, - allocator: &mut A, - ) -> Result, MapToError> - where - A: FrameAllocator; - - /// Removes a mapping from the page table and returns the frame that used to be mapped. - /// - /// Note that no page tables or pages are deallocated. - fn unmap(&mut self, page: Page) -> Result<(PhysFrame, MapperFlush), UnmapError>; - - /// Updates the flags of an existing mapping. - fn update_flags( - &mut self, - page: Page, - flags: PageTableFlags, - ) -> Result, FlagUpdateError>; - - /// Return the frame that the specified page is mapped to. - fn translate_page(&self, page: Page) -> Option>; - - /// Maps the given frame to the virtual page with the same address. - fn identity_map( - &mut self, - frame: PhysFrame, - flags: PageTableFlags, - attr: PageTableAttribute, - allocator: &mut A, - ) -> Result, MapToError> - where - A: FrameAllocator, - S: PageSize, - Self: Mapper, - { - let page = Page::containing_address(VirtAddr::new(frame.start_address().as_u64())); - self.map_to(page, frame, flags, attr, allocator) - } -} - -/// A recursive page table is a last level page table with an entry mapped to the table itself. -/// -/// This recursive mapping allows accessing all page tables in the hierarchy: -/// -/// - To access the level 4 page table, we “loop“ (i.e. follow the recursively mapped entry) four -/// times. -/// - To access a level 3 page table, we “loop” three times and then use the level 4 index. -/// - To access a level 2 page table, we “loop” two times, then use the level 4 index, then the -/// level 3 index. -/// - To access a level 1 page table, we “loop” once, then use the level 4 index, then the -/// level 3 index, then the level 2 index. -/// -/// This struct implements the `Mapper` trait. -#[derive(Debug)] -pub struct RecursivePageTable<'a> { - p4: &'a mut PageTable, - recursive_index: u9, -} - -/// An error indicating that the given page table is not recursively mapped. -/// -/// Returned from `RecursivePageTable::new`. -#[derive(Debug)] -pub struct NotRecursivelyMapped; - -/// This error is returned from `map_to` and similar methods. -#[derive(Debug)] -pub enum MapToError { - /// An additional frame was needed for the mapping process, but the frame allocator - /// returned `None`. - FrameAllocationFailed, - /// An upper level page table entry has the `HUGE_PAGE` flag set, which means that the - /// given page is part of an already mapped huge page. - ParentEntryHugePage, - /// The given page is already mapped to a physical frame. - PageAlreadyMapped, -} - -/// An error indicating that an `unmap` call failed. -#[derive(Debug)] -pub enum UnmapError { - /// An upper level page table entry has the `HUGE_PAGE` flag set, which means that the - /// given page is part of a huge page and can't be freed individually. - ParentEntryHugePage, - /// The given page is not mapped to a physical frame. - PageNotMapped, - /// The page table entry for the given page points to an invalid physical address. - InvalidFrameAddress(PhysAddr), -} - -/// An error indicating that an `update_flags` call failed. -#[derive(Debug)] -pub enum FlagUpdateError { - /// The given page is not mapped to a physical frame. - PageNotMapped, -} - -impl<'a> RecursivePageTable<'a> { - /// Creates a new RecursivePageTable from the passed level 4 PageTable. - /// - /// The page table must be recursively mapped, that means: - /// - /// - The page table must have one recursive entry, i.e. an entry that points to the table - /// itself. - /// - The reference must use that “loop”, i.e. be of the form `0o_xxx_xxx_xxx_xxx_0000` - /// where `xxx` is the recursive entry. - /// - The page table must be active, i.e. the CR3 register must contain its physical address. - /// - /// Otherwise `Err(NotRecursivelyMapped)` is returned. - pub fn new(table: &'a mut PageTable) -> Result { - let page = Page::containing_address(VirtAddr::new(table as *const _ as u64)); - let recursive_index = page.p4_index(); - - if page.p3_index() != recursive_index - || page.p2_index() != recursive_index - || page.p1_index() != recursive_index - { - return Err(NotRecursivelyMapped); - } - if Ok(ttbr_el1_read(page.start_address().va_range().unwrap() as u8)) != - table[recursive_index].frame() - { - return Err(NotRecursivelyMapped); - } - - Ok(RecursivePageTable { - p4: table, - recursive_index, - }) - } - - /// Creates a new RecursivePageTable without performing any checks. - /// - /// The `recursive_index` parameter must be the index of the recursively mapped entry. - pub unsafe fn new_unchecked(table: &'a mut PageTable, recursive_index: u9) -> Self { - RecursivePageTable { - p4: table, - recursive_index, - } - } - - /// Internal helper function to create the page table of the next level if needed. - /// - /// If the passed entry is unused, a new frame is allocated from the given allocator, zeroed, - /// and the entry is updated to that address. If the passed entry is already mapped, the next - /// table is returned directly. - /// - /// The `next_page_table` page must be the page of the next page table in the hierarchy. - /// - /// Returns `MapToError::FrameAllocationFailed` if the entry is unused and the allocator - /// returned `None`. Returns `MapToError::ParentEntryHugePage` if the `HUGE_PAGE` flag is set - /// in the passed entry. - unsafe fn create_next_table<'b, A>( - entry: &'b mut PageTableEntry, - next_table_page: Page, - allocator: &mut A, - ) -> Result<&'b mut PageTable, MapToError> - where - A: FrameAllocator, - { - /// This inner function is used to limit the scope of `unsafe`. - /// - /// This is a safe function, so we need to use `unsafe` blocks when we do something unsafe. - fn inner<'b, A>( - entry: &'b mut PageTableEntry, - next_table_page: Page, - allocator: &mut A, - ) -> Result<&'b mut PageTable, MapToError> - where - A: FrameAllocator, - { - let created; - - if entry.is_unused() { - if let Some(frame) = allocator.alloc() { - entry.set_frame(frame, Flags::default(), MairNormal::attr_value()); - created = true; - } else { - return Err(MapToError::FrameAllocationFailed); - } - } else { - created = false; - } - // is a huge page (block) - if !entry.flags().contains(Flags::TABLE_OR_PAGE) { - return Err(MapToError::ParentEntryHugePage); - } - - let page_table_ptr = next_table_page.start_address().as_mut_ptr(); - let page_table: &mut PageTable = unsafe { &mut *(page_table_ptr) }; - if created { - unsafe { barrier::dsb(barrier::ISHST); } - page_table.zero(); - } - Ok(page_table) - } - - inner(entry, next_table_page, allocator) - } - - pub fn p3_ptr(&self, page: Page) -> *mut PageTable { - self.p3_page(page).start_address().as_mut_ptr() - } - - pub fn p2_ptr(&self, page: Page) -> *mut PageTable { - self.p2_page(page).start_address().as_mut_ptr() - } - - pub fn p1_ptr(&self, page: Page) -> *mut PageTable { - self.p1_page(page).start_address().as_mut_ptr() - } - - fn p3_page(&self, page: Page) -> Page { - Page::from_page_table_indices( - self.recursive_index, - self.recursive_index, - self.recursive_index, - page.p4_index(), - ) - } - - fn p2_page(&self, page: Page) -> Page { - Page::from_page_table_indices( - self.recursive_index, - self.recursive_index, - page.p4_index(), - page.p3_index(), - ) - } - - fn p1_page(&self, page: Page) -> Page { - Page::from_page_table_indices( - self.recursive_index, - page.p4_index(), - page.p3_index(), - page.p2_index(), - ) - } -} - -impl<'a> Mapper for RecursivePageTable<'a> { - fn map_to( - &mut self, - page: Page, - frame: PhysFrame, - flags: PageTableFlags, - attr: PageTableAttribute, - allocator: &mut A, - ) -> Result, MapToError> - where - A: FrameAllocator, - { - let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; - let p4 = &mut self_mut.p4; - - let p3_page = self.p3_page(page); - let p3 = unsafe { Self::create_next_table(&mut p4[page.p4_index()], p3_page, allocator)? }; - - let p2_page = self.p2_page(page); - let p2 = unsafe { Self::create_next_table(&mut p3[page.p3_index()], p2_page, allocator)? }; - - let p1_page = self.p1_page(page); - let p1 = unsafe { Self::create_next_table(&mut p2[page.p2_index()], p1_page, allocator)? }; - - if !p1[page.p1_index()].is_unused() { - return Err(MapToError::PageAlreadyMapped); - } - p1[page.p1_index()].set_frame(frame, flags, attr); - - Ok(MapperFlush::new(page)) - } - - fn unmap( - &mut self, - page: Page, - ) -> Result<(PhysFrame, MapperFlush), UnmapError> { - let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; - let p4 = &mut self_mut.p4; - - let p4_entry = &p4[page.p4_index()]; - p4_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - let p3 = unsafe { &mut *(self.p3_ptr(page)) }; - let p3_entry = &p3[page.p3_index()]; - p3_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - let p2 = unsafe { &mut *(self.p2_ptr(page)) }; - let p2_entry = &p2[page.p2_index()]; - p2_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - let p1 = unsafe { &mut *(self.p1_ptr(page)) }; - let p1_entry = &mut p1[page.p1_index()]; - - let frame = p1_entry.frame().map_err(|err| match err { - FrameError::FrameNotPresent => UnmapError::PageNotMapped, - FrameError::HugeFrame => UnmapError::ParentEntryHugePage, - })?; - - p1_entry.set_unused(); - Ok((frame, MapperFlush::new(page))) - } - - fn update_flags( - &mut self, - page: Page, - flags: PageTableFlags, - ) -> Result, FlagUpdateError> { - let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; - let p4 = &mut self_mut.p4; - - if p4[page.p4_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - let p3 = unsafe { &mut *(self.p3_ptr(page)) }; - - if p3[page.p3_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - let p2 = unsafe { &mut *(self.p2_ptr(page)) }; - - if p2[page.p2_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - let p1 = unsafe { &mut *(self.p1_ptr(page)) }; - - if p1[page.p1_index()].is_unused() { - return Err(FlagUpdateError::PageNotMapped); - } - - p1[page.p1_index()].modify_flags(flags); - - Ok(MapperFlush::new(page)) - } - - fn translate_page(&self, page: Page) -> Option> { - let self_mut = unsafe { &mut *(self as *const _ as *mut Self) }; - let p4 = &mut self_mut.p4; - - if p4[page.p4_index()].is_unused() { - return None; - } - - let p3 = unsafe { &*(self.p3_ptr(page)) }; - let p3_entry = &p3[page.p3_index()]; - - if p3_entry.is_unused() { - return None; - } - - let p2 = unsafe { &*(self.p2_ptr(page)) }; - let p2_entry = &p2[page.p2_index()]; - - if p2_entry.is_unused() { - return None; - } - - let p1 = unsafe { &*(self.p1_ptr(page)) }; - let p1_entry = &p1[page.p1_index()]; - - if p1_entry.is_unused() { - return None; - } - - PhysFrame::from_start_address(p1_entry.addr()).ok() - } -} diff --git a/crate/aarch64/src/regs/cntfrq_el0.rs b/crate/aarch64/src/regs/cntfrq_el0.rs deleted file mode 100644 index df56ac9..0000000 --- a/crate/aarch64/src/regs/cntfrq_el0.rs +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Counter-timer Frequency register - EL0 -//! -//! This register is provided so that software can discover the frequency of the -//! system counter. It must be programmed with this value as part of system -//! initialization. The value of the register is not interpreted by hardware. - -use register::cpu::RegisterReadOnly; - -pub struct Reg; - -impl RegisterReadOnly for Reg { - sys_coproc_read_raw!(u32, "CNTFRQ_EL0"); -} - -pub static CNTFRQ_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cnthctl_el2.rs b/crate/aarch64/src/regs/cnthctl_el2.rs deleted file mode 100644 index f5e3c2c..0000000 --- a/crate/aarch64/src/regs/cnthctl_el2.rs +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Counter-timer Hypervisor Control register - EL2 -//! -//! Controls the generation of an event stream from the physical counter, and -//! access from Non-secure EL1 to the physical counter and the Non-secure EL1 -//! physical timer. - -use register::cpu::RegisterReadWrite; - -// When HCR_EL2.E2H == 0: -// TODO: Figure out how we can differentiate depending on HCR_EL2.E2H state -// -// For now, implement the HCR_EL2.E2H == 0 version -register_bitfields! {u32, - CNTHCTL_EL2 [ - /// Traps Non-secure EL0 and EL1 accesses to the physical timer - /// registers to EL2. - /// - /// 0 From AArch64 state: Non-secure EL0 and EL1 accesses to the - /// CNTP_CTL_EL0, CNTP_CVAL_EL0, and CNTP_TVAL_EL0 are trapped to EL2, - /// unless it is trapped by CNTKCTL_EL1.EL0PTEN. - /// - /// From AArch32 state: Non-secure EL0 and EL1 accesses to the - /// CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to EL2, unless it - /// is trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN. - /// - /// 1 This control does not cause any instructions to be trapped. - /// - /// If EL3 is implemented and EL2 is not implemented, behavior is as if - /// this bit is 1 other than for the purpose of a direct read. - EL1PCEN OFFSET(1) NUMBITS(1) [], - - /// Traps Non-secure EL0 and EL1 accesses to the physical counter - /// register to EL2. - /// - /// 0 From AArch64 state: Non-secure EL0 and EL1 accesses to the - /// CNTPCT_EL0 are trapped to EL2, unless it is trapped by - /// CNTKCTL_EL1.EL0PCTEN. - /// - /// From AArch32 state: Non-secure EL0 and EL1 accesses to the CNTPCT - /// are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PCTEN - /// or CNTKCTL.PL0PCTEN. - /// - /// 1 This control does not cause any instructions to be trapped. - /// - /// If EL3 is implemented and EL2 is not implemented, behavior is as if - /// this bit is 1 other than for the purpose of a direct read. - EL1PCTEN OFFSET(0) NUMBITS(1) [] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "CNTHCTL_EL2"); - sys_coproc_write_raw!(u32, "CNTHCTL_EL2"); -} - -#[allow(non_upper_case_globals)] -pub static CNTHCTL_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntp_ctl_el0.rs b/crate/aarch64/src/regs/cntp_ctl_el0.rs deleted file mode 100644 index 76991eb..0000000 --- a/crate/aarch64/src/regs/cntp_ctl_el0.rs +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Counter-timer Physical Timer Control register - EL0 -//! -//! Control register for the EL1 physical timer. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u32, - CNTP_CTL_EL0 [ - /// The status of the timer. This bit indicates whether the timer - /// condition is met: - /// - /// 0 Timer condition is not met. - /// 1 Timer condition is met. - /// - /// When the value of the ENABLE bit is 1, ISTATUS indicates whether the - /// timer condition is met. ISTATUS takes no account of the value of the - /// IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 - /// then the timer interrupt is asserted. - /// - /// When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN. - /// - /// This bit is read-only. - ISTATUS OFFSET(2) NUMBITS(1) [], - - /// Timer interrupt mask bit. Permitted values are: - /// - /// 0 Timer interrupt is not masked by the IMASK bit. - /// 1 Timer interrupt is masked by the IMASK bit. - IMASK OFFSET(1) NUMBITS(1) [], - - /// Enables the timer. Permitted values are: - /// - /// 0 Timer disabled. - /// 1 Timer enabled. - ENABLE OFFSET(0) NUMBITS(1) [] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "CNTP_CTL_EL0"); - sys_coproc_write_raw!(u32, "CNTP_CTL_EL0"); -} - -pub static CNTP_CTL_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntp_tval_el0.rs b/crate/aarch64/src/regs/cntp_tval_el0.rs deleted file mode 100644 index bdf5f6a..0000000 --- a/crate/aarch64/src/regs/cntp_tval_el0.rs +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Counter-timer Physical Timer TimerValue register - EL0 -//! -//! Holds the timer value for the EL1 physical timer. - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "CNTP_TVAL_EL0"); - sys_coproc_write_raw!(u32, "CNTP_TVAL_EL0"); -} - -pub static CNTP_TVAL_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntpct_el0.rs b/crate/aarch64/src/regs/cntpct_el0.rs deleted file mode 100644 index b381d99..0000000 --- a/crate/aarch64/src/regs/cntpct_el0.rs +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Counter-timer Physical Count register - EL0 -//! -//! Holds the 64-bit physical count value. - -use register::cpu::RegisterReadOnly; - -pub struct Reg; - -impl RegisterReadOnly for Reg { - sys_coproc_read_raw!(u64, "CNTPCT_EL0"); -} - -pub static CNTPCT_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/cntvoff_el2.rs b/crate/aarch64/src/regs/cntvoff_el2.rs deleted file mode 100644 index aff7074..0000000 --- a/crate/aarch64/src/regs/cntvoff_el2.rs +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Counter-timer Virtual Offset register - EL2 -//! -//! Holds the 64-bit virtual offset. This is the offset between the physical -//! count value visible in CNTPCT_EL0 and the virtual count value visible in -//! CNTVCT_EL0. - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "CNTVOFF_EL2"); - sys_coproc_write_raw!(u64, "CNTVOFF_EL2"); -} - -pub static CNTVOFF_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/currentel.rs b/crate/aarch64/src/regs/currentel.rs deleted file mode 100644 index 91b8e0a..0000000 --- a/crate/aarch64/src/regs/currentel.rs +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Current Exception Level -//! -//! Holds the current Exception level. - -use register::cpu::RegisterReadOnly; - -register_bitfields! {u32, - CurrentEL [ - /// Current Exception level. Possible values of this field are: - /// - /// 00 EL0 - /// 01 EL1 - /// 10 EL2 - /// 11 EL3 - /// - /// When the HCR_EL2.NV bit is 1, Non-secure EL1 read accesses to the - /// CurrentEL register return the value of 0x2 in this field. - /// - /// This field resets to a value that is architecturally UNKNOWN. - EL OFFSET(2) NUMBITS(2) [ - EL0 = 0, - EL1 = 1, - EL2 = 2, - EL3 = 3 - ] - ] -} - -pub struct Reg; - -impl RegisterReadOnly for Reg { - sys_coproc_read_raw!(u32, "CurrentEL"); -} - -#[allow(non_upper_case_globals)] -pub static CurrentEL: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/daif.rs b/crate/aarch64/src/regs/daif.rs deleted file mode 100644 index bf810a2..0000000 --- a/crate/aarch64/src/regs/daif.rs +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Interrupt Mask Bits -//! -//! Allows access to the interrupt mask bits. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u32, - DAIF [ - /// Process state D mask. The possible values of this bit are: - /// - /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at - /// the current Exception level are not masked. - /// - /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at - /// the current Exception level are masked. - /// - /// When the target Exception level of the debug exception is higher - /// than the current Exception level, the exception is not masked by - /// this bit. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 1. - D OFFSET(9) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// SError interrupt mask bit. The possible values of this bit are: - /// - /// 0 Exception not masked. - /// 1 Exception masked. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 1 . - A OFFSET(8) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// IRQ mask bit. The possible values of this bit are: - /// - /// 0 Exception not masked. - /// 1 Exception masked. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 1 . - I OFFSET(7) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// FIQ mask bit. The possible values of this bit are: - /// - /// 0 Exception not masked. - /// 1 Exception masked. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 1 . - F OFFSET(6) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ] - ] -} - - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "DAIF"); - sys_coproc_write_raw!(u32, "DAIF"); -} - -pub static DAIF: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/elr_el2.rs b/crate/aarch64/src/regs/elr_el2.rs deleted file mode 100644 index 0786fbb..0000000 --- a/crate/aarch64/src/regs/elr_el2.rs +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Exception Link Register - EL2 -//! -//! When taking an exception to EL2, holds the address to return to. - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "ELR_EL2"); - sys_coproc_write_raw!(u64, "ELR_EL2"); -} - -pub static ELR_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/far_el1.rs b/crate/aarch64/src/regs/far_el1.rs deleted file mode 100644 index fc809fa..0000000 --- a/crate/aarch64/src/regs/far_el1.rs +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Fault Address Register - EL1 -//! -//! Holds the faulting Virtual Address for all synchronous Instruction or Data -//! Abort, PC alignment fault and Watchpoint exceptions that are taken to EL1. - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "FAR_EL1"); - sys_coproc_write_raw!(u64, "FAR_EL1"); -} - -pub static FAR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/hcr_el2.rs b/crate/aarch64/src/regs/hcr_el2.rs deleted file mode 100644 index 683bbef..0000000 --- a/crate/aarch64/src/regs/hcr_el2.rs +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Hypervisor Configuration Register - EL2 -//! -//! Provides configuration controls for virtualization, including defining -//! whether various Non-secure operations are trapped to EL2. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u64, - HCR_EL2 [ - /// Execution state control for lower Exception levels: - /// - /// 0 Lower levels are all AArch32. - /// 1 The Execution state for EL1 is AArch64. The Execution state for - /// EL0 is determined by the current value of PSTATE.nRW when - /// executing at EL0. - /// - /// If all lower Exception levels cannot use AArch32 then this bit is - /// RAO/WI. - /// - /// In an implementation that includes EL3, when SCR_EL3.NS==0, the PE - /// behaves as if this bit has the same value as the SCR_EL3.RW bit for - /// all purposes other than a direct read or write access of HCR_EL2. - /// - /// The RW bit is permitted to be cached in a TLB. - /// - /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} - /// is {1, 1}, this field behaves as 1 for all purposes other than a - /// direct read of the value of this bit. - RW OFFSET(31) NUMBITS(1) [ - AllLowerELsAreAarch32 = 0, - EL1IsAarch64 = 1 - ], - - /// Default Cacheability. - /// - /// 0 This control has no effect on the Non-secure EL1&0 translation - /// regime. - /// - /// 1 In Non-secure state: - /// - When EL1 is using AArch64, the PE behaves as if the value of - /// the SCTLR_EL1.M field is 0 for all purposes other than - /// returning the value of a direct read of SCTLR_EL1. - /// - /// - When EL1 is using AArch32, the PE behaves as if the value of - /// the SCTLR.M field is 0 for all purposes other than returning - /// the value of a direct read of SCTLR. - /// - /// - The PE behaves as if the value of the HCR_EL2.VM field is 1 - /// for all purposes other than returning the value of a direct - /// read of HCR_EL2. - /// - /// - The memory type produced by stage 1 of the EL1&0 translation - /// regime is Normal Non-Shareable, Inner Write-Back Read-Allocate - /// Write-Allocate, Outer Write-Back Read-Allocate Write-Allocate. - /// - /// This field has no effect on the EL2, EL2&0, and EL3 translation - /// regimes. - /// - /// This field is permitted to be cached in a TLB. - /// - /// In an implementation that includes EL3, when the value of SCR_EL3.NS - /// is 0 the PE behaves as if this field is 0 for all purposes other - /// than a direct read or write access of HCR_EL2. - /// - /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} - /// is {1, 1}, this field behaves as 0 for all purposes other than a - /// direct read of the value of this field. - DC OFFSET(12) NUMBITS(1) [], - - /// Set/Way Invalidation Override. Causes Non-secure EL1 execution of - /// the data cache invalidate by set/way instructions to perform a data - /// cache clean and invalidate by set/way: - /// - /// 0 This control has no effect on the operation of data cache - /// invalidate by set/way instructions. - /// - /// 1 Data cache invalidate by set/way instructions perform a data cache - /// clean and invalidate by set/way. - /// - /// When the value of this bit is 1: - /// - /// AArch32: DCISW performs the same invalidation as a DCCISW - /// instruction. - /// - /// AArch64: DC ISW performs the same invalidation as a DC CISW - /// instruction. - /// - /// This bit can be implemented as RES 1. - /// - /// In an implementation that includes EL3, when the value of SCR_EL3.NS - /// is 0 the PE behaves as if this field is 0 for all purposes other - /// than a direct read or write access of HCR_EL2. - /// - /// When HCR_EL2.TGE is 1, the PE ignores the value of this field for - /// all purposes other than a direct read of this field. - SWIO OFFSET(1) NUMBITS(1) [] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "HCR_EL2"); - sys_coproc_write_raw!(u64, "HCR_EL2"); -} - -pub static HCR_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/id_aa64mmfr0_el1.rs b/crate/aarch64/src/regs/id_aa64mmfr0_el1.rs deleted file mode 100644 index f75813c..0000000 --- a/crate/aarch64/src/regs/id_aa64mmfr0_el1.rs +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! AArch64 Memory Model Feature Register 0 - EL1 -//! -//! Provides information about the implemented memory model and memory -//! management support in AArch64 state. - -use register::cpu::RegisterReadOnly; - -register_bitfields! {u64, - ID_AA64MMFR0_EL1 [ - /// Support for 4KiB memory translation granule size. Defined values - /// are: - /// - /// 0000 4KiB granule supported. - /// 1111 4KiB granule not supported. - /// - /// All other values are reserved. - TGran4 OFFSET(28) NUMBITS(4) [ - Supported = 0b0000, - NotSupported = 0b1111 - ], - - /// Support for 64KiB memory translation granule size. Defined values - /// are: - /// - /// 0000 64KiB granule supported. - /// 1111 64KiB granule not supported. - /// - /// All other values are reserved. - TGran64 OFFSET(24) NUMBITS(4) [ - Supported = 0b0000, - NotSupported = 0b1111 - ], - - /// Physical Address range supported. Defined values are: - /// - /// 0000 32 bits, 4GiB. - /// 0001 36 bits, 64GiB. - /// 0010 40 bits, 1TiB. - /// 0011 42 bits, 4TiB. - /// 0100 44 bits, 16TiB. - /// 0101 48 bits, 256TiB. - /// 0110 52 bits, 4PiB. - /// - /// All other values are reserved. - /// - /// The value 0110 is permitted only if the implementation includes - /// ARMv8.2-LPA, otherwise it is reserved. - PARange OFFSET(0) NUMBITS(4) [ - Bits_32 = 0b0000, - Bits_36 = 0b0001, - Bits_40 = 0b0010, - Bits_42 = 0b0011, - Bits_44 = 0b0100, - Bits_48 = 0b0101, - Bits_52 = 0b0110 - ] - ] -} - -pub struct Reg; - -impl RegisterReadOnly for Reg { - sys_coproc_read_raw!(u64, "ID_AA64MMFR0_EL1"); -} - -pub static ID_AA64MMFR0_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/macros.rs b/crate/aarch64/src/regs/macros.rs deleted file mode 100644 index bd4439c..0000000 --- a/crate/aarch64/src/regs/macros.rs +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -macro_rules! __read_raw { - ($width:ty, $asm_instr:tt, $asm_reg_name:tt) => { - /// Reads the raw bits of the CPU register. - #[inline] - fn get(&self) -> $width { - match () { - #[cfg(target_arch = "aarch64")] - () => { - let reg; - unsafe { - asm!(concat!($asm_instr, " $0, ", $asm_reg_name) : "=r"(reg) ::: "volatile"); - } - reg - } - - #[cfg(not(target_arch = "aarch64"))] - () => unimplemented!(), - } - } - }; -} - -macro_rules! __write_raw { - ($width:ty, $asm_instr:tt, $asm_reg_name:tt) => { - /// Writes raw bits to the CPU register. - #[cfg_attr(not(target_arch = "aarch64"), allow(unused_variables))] - #[inline] - fn set(&self, value: $width) { - match () { - #[cfg(target_arch = "aarch64")] - () => { - unsafe { - asm!(concat!($asm_instr, " ", $asm_reg_name, ", $0") :: "r"(value) :: "volatile") - } - } - - #[cfg(not(target_arch = "aarch64"))] - () => unimplemented!(), - } - } - }; -} - -/// Raw read from system coprocessor registers -macro_rules! sys_coproc_read_raw { - ($width:ty, $asm_reg_name:tt) => { - __read_raw!($width, "mrs", $asm_reg_name); - }; -} - -/// Raw write to system coprocessor registers -macro_rules! sys_coproc_write_raw { - ($width:ty, $asm_reg_name:tt) => { - __write_raw!($width, "msr", $asm_reg_name); - }; -} - -/// Raw read from (ordinary) registers -macro_rules! read_raw { - ($width:ty, $asm_reg_name:tt) => { - __read_raw!($width, "mov", $asm_reg_name); - }; -} -/// Raw write to (ordinary) registers -macro_rules! write_raw { - ($width:ty, $asm_reg_name:tt) => { - __write_raw!($width, "mov", $asm_reg_name); - }; -} diff --git a/crate/aarch64/src/regs/mair_el1.rs b/crate/aarch64/src/regs/mair_el1.rs deleted file mode 100644 index dbd7f9d..0000000 --- a/crate/aarch64/src/regs/mair_el1.rs +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Memory Attribute Indirection Register - EL1 -//! -//! Provides the memory attribute encodings corresponding to the possible -//! AttrIndx values in a Long-descriptor format translation table entry for -//! stage 1 translations at EL1. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u64, - MAIR_EL1 [ - /// Attribute 7 - Attr7 OFFSET(56) NUMBITS(8) [], - - /// Attribute 6 - Attr6 OFFSET(48) NUMBITS(8) [], - - /// Attribute 5 - Attr5 OFFSET(40) NUMBITS(8) [], - - /// Attribute 4 - Attr4 OFFSET(32) NUMBITS(8) [], - - /// Attribute 3 - Attr3 OFFSET(24) NUMBITS(8) [], - - /// Attribute 2 - Attr2 OFFSET(16) NUMBITS(8) [], - - /// Attribute 1 - Attr1 OFFSET(8) NUMBITS(8) [], - - /// Attribute 0 - Attr0 OFFSET(0) NUMBITS(8) [] - ] -} - -register_bitfields! {u64, - MAIR_ATTR [ - Attr_HIGH OFFSET(4) NUMBITS(4) [ - Device = 0b0000, - Memory_OuterNonCacheable = 0b0100, - Memory_OuterWriteThrough_NonTransient_ReadAlloc_WriteAlloc = 0b1011, - Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 - ], - Attr_LOW_DEVICE OFFSET(0) NUMBITS(4) [ - Device_nGnRnE = 0b0000, - Device_nGnRE = 0b0100, - Device_nGRE = 0b1000, - Device_GRE = 0b1100 - ], - Attr_LOW_MEMORY OFFSET(0) NUMBITS(4) [ - InnerNonCacheable = 0b0100, - InnerWriteThrough_NonTransient_ReadAlloc_WriteAlloc = 0b1011, - InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc = 0b1111 - ] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "MAIR_EL1"); - sys_coproc_write_raw!(u64, "MAIR_EL1"); -} - -pub static MAIR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/mod.rs b/crate/aarch64/src/regs/mod.rs deleted file mode 100644 index 11a6d3f..0000000 --- a/crate/aarch64/src/regs/mod.rs +++ /dev/null @@ -1,55 +0,0 @@ -//! Processor core registers - -#[macro_use] -mod macros; - -mod cntfrq_el0; -mod cnthctl_el2; -mod cntp_ctl_el0; -mod cntp_tval_el0; -mod cntpct_el0; -mod cntvoff_el2; -mod currentel; -mod daif; -mod elr_el2; -mod far_el1; -mod hcr_el2; -mod id_aa64mmfr0_el1; -mod mair_el1; -mod mpidr_el1; -mod sctlr_el1; -mod sp; -mod sp_el0; -mod sp_el1; -mod spsel; -mod spsr_el2; -mod tcr_el1; -mod ttbr0_el1; -mod ttbr1_el1; - -// Export only the R/W traits and the static reg definitions -pub use register::cpu::*; - -pub use self::cntfrq_el0::CNTFRQ_EL0; -pub use self::cnthctl_el2::CNTHCTL_EL2; -pub use self::cntp_ctl_el0::CNTP_CTL_EL0; -pub use self::cntp_tval_el0::CNTP_TVAL_EL0; -pub use self::cntpct_el0::CNTPCT_EL0; -pub use self::cntvoff_el2::CNTVOFF_EL2; -pub use self::currentel::CurrentEL; -pub use self::daif::DAIF; -pub use self::elr_el2::ELR_EL2; -pub use self::far_el1::FAR_EL1; -pub use self::hcr_el2::HCR_EL2; -pub use self::id_aa64mmfr0_el1::ID_AA64MMFR0_EL1; -pub use self::mair_el1::{MAIR_EL1, MAIR_ATTR}; -pub use self::mpidr_el1::MPIDR_EL1; -pub use self::sctlr_el1::SCTLR_EL1; -pub use self::sp::SP; -pub use self::sp_el0::SP_EL0; -pub use self::sp_el1::SP_EL1; -pub use self::spsel::SPSel; -pub use self::spsr_el2::SPSR_EL2; -pub use self::tcr_el1::TCR_EL1; -pub use self::ttbr0_el1::TTBR0_EL1; -pub use self::ttbr1_el1::TTBR1_EL1; diff --git a/crate/aarch64/src/regs/mpidr_el1.rs b/crate/aarch64/src/regs/mpidr_el1.rs deleted file mode 100644 index 6fbfea0..0000000 --- a/crate/aarch64/src/regs/mpidr_el1.rs +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Multiprocessor Affinity Register - EL1 -//! -//! In a multiprocessor system, provides an additional PE -//! identification mechanism for scheduling purposes. - -use register::cpu::RegisterReadOnly; - -pub struct Reg; - -impl RegisterReadOnly for Reg { - sys_coproc_read_raw!(u64, "MPIDR_EL1"); -} - -pub static MPIDR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sctlr_el1.rs b/crate/aarch64/src/regs/sctlr_el1.rs deleted file mode 100644 index 1f463b4..0000000 --- a/crate/aarch64/src/regs/sctlr_el1.rs +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! System Control Register - EL1 -//! -//! Provides top level control of the system, including its memory system, at -//! EL1 and EL0. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u32, - SCTLR_EL1 [ - /// Instruction access Cacheability control, for accesses at EL0 and - /// EL1: - /// - /// 0 All instruction access to Normal memory from EL0 and EL1 are - /// Non-cacheable for all levels of instruction and unified cache. - /// - /// If the value of SCTLR_EL1.M is 0, instruction accesses from stage - /// 1 of the EL1&0 translation regime are to Normal, Outer Shareable, - /// Inner Non-cacheable, Outer Non-cacheable memory. - /// - /// 1 This control has no effect on the Cacheability of instruction - /// access to Normal memory from EL0 and EL1. - /// - /// If the value of SCTLR_EL1.M is 0, instruction accesses from stage - /// 1 of the EL1&0 translation regime are to Normal, Outer Shareable, - /// Inner Write-Through, Outer Write-Through memory. - /// - /// When the value of the HCR_EL2.DC bit is 1, then instruction access - /// to Normal memory from EL0 and EL1 are Cacheable regardless of the - /// value of the SCTLR_EL1.I bit. - /// - /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} - /// is {1, 1}, this bit has no effect on the PE. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 0. - I OFFSET(12) NUMBITS(1) [ - NonCacheable = 0, - Cacheable = 1 - ], - - /// Cacheability control, for data accesses. - /// - /// 0 All data access to Normal memory from EL0 and EL1, and all Normal - /// memory accesses to the EL1&0 stage 1 translation tables, are - /// Non-cacheable for all levels of data and unified cache. - /// - /// 1 This control has no effect on the Cacheability of: - /// - Data access to Normal memory from EL0 and EL1. - /// - Normal memory accesses to the EL1&0 stage 1 translation - /// tables. - /// - /// When the value of the HCR_EL2.DC bit is 1, the PE ignores - /// SCLTR.C. This means that Non-secure EL0 and Non-secure EL1 data - /// accesses to Normal memory are Cacheable. - /// - /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} - /// is {1, 1}, this bit has no effect on the PE. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 0. - C OFFSET(2) NUMBITS(1) [ - NonCacheable = 0, - Cacheable = 1 - ], - - /// MMU enable for EL1 and EL0 stage 1 address translation. Possible - /// values of this bit are: - /// - /// 0 EL1 and EL0 stage 1 address translation disabled. - /// See the SCTLR_EL1.I field for the behavior of instruction accesses - /// to Normal memory. - /// 1 EL1 and EL0 stage 1 address translation enabled. - M OFFSET(0) NUMBITS(1) [ - Disable = 0, - Enable = 1 - ] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "SCTLR_EL1"); - sys_coproc_write_raw!(u32, "SCTLR_EL1"); -} - -pub static SCTLR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sp.rs b/crate/aarch64/src/regs/sp.rs deleted file mode 100644 index f9f578b..0000000 --- a/crate/aarch64/src/regs/sp.rs +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! The stack pointer - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - read_raw!(u64, "sp"); - write_raw!(u64, "sp"); -} - -pub static SP: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sp_el0.rs b/crate/aarch64/src/regs/sp_el0.rs deleted file mode 100644 index aa82fdb..0000000 --- a/crate/aarch64/src/regs/sp_el0.rs +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! The stack pointer - EL0 -//! -//! Holds the stack pointer associated with EL0. At higher Exception levels, -//! this is used as the current stack pointer when the value of SPSel.SP is 0. - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "SP_EL0"); - sys_coproc_write_raw!(u64, "SP_EL0"); -} - -pub static SP_EL0: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/sp_el1.rs b/crate/aarch64/src/regs/sp_el1.rs deleted file mode 100644 index 4357412..0000000 --- a/crate/aarch64/src/regs/sp_el1.rs +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! The stack pointer - EL1 -//! -//! Holds the stack pointer associated with EL1. When executing at EL1, the -//! value of SPSel.SP determines the current stack pointer: -//! -//! SPSel.SP | current stack pointer -//! -------------------------------- -//! 0 | SP_EL0 -//! 1 | SP_EL1 - -use register::cpu::RegisterReadWrite; - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "SP_EL1"); - sys_coproc_write_raw!(u64, "SP_EL1"); -} - -pub static SP_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/spsel.rs b/crate/aarch64/src/regs/spsel.rs deleted file mode 100644 index 91e3694..0000000 --- a/crate/aarch64/src/regs/spsel.rs +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Stack Pointer Select -//! -//! Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u32, - SPSel [ - /// Stack pointer to use. Possible values of this bit are: - /// - /// 0 Use SP_EL0 at all Exception levels. - /// 1 Use SP_ELx for Exception level ELx. - /// - /// When this register has an architecturally-defined reset value, this - /// field resets to 1. - SP OFFSET(0) NUMBITS(1) [ - EL0 = 0, - ELx = 1 - ] - ] -} - - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "SPSEL"); - sys_coproc_write_raw!(u32, "SPSEL"); -} - -#[allow(non_upper_case_globals)] -pub static SPSel: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/spsr_el2.rs b/crate/aarch64/src/regs/spsr_el2.rs deleted file mode 100644 index 56078a4..0000000 --- a/crate/aarch64/src/regs/spsr_el2.rs +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Saved Program Status Register - EL2 -//! -//! Holds the saved process state when an exception is taken to EL2. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u32, - SPSR_EL2 [ - /// Process state D mask. The possible values of this bit are: - /// - /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at - /// the current Exception level are not masked. - /// - /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at - /// the current Exception level are masked. - /// - /// When the target Exception level of the debug exception is higher - /// than the current Exception level, the exception is not masked by - /// this bit. - D OFFSET(9) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// SError interrupt mask bit. The possible values of this bit are: - /// - /// 0 Exception not masked. - /// 1 Exception masked. - A OFFSET(8) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// IRQ mask bit. The possible values of this bit are: - /// - /// 0 Exception not masked. - /// 1 Exception masked. - I OFFSET(7) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// FIQ mask bit. The possible values of this bit are: - /// - /// 0 Exception not masked. - /// 1 Exception masked. - F OFFSET(6) NUMBITS(1) [ - Unmasked = 0, - Masked = 1 - ], - - /// AArch64 state (Exception level and selected SP) that an exception - /// was taken from. The possible values are: - /// - /// M[3:0] | State - /// -------------- - /// 0b0000 | EL0t - /// 0b0100 | EL1t - /// 0b0101 | EL1h - /// 0b1000 | EL2t - /// 0b1001 | EL2h - /// - /// Other values are reserved, and returning to an Exception level that - /// is using AArch64 with a reserved value in this field is treated as - /// an illegal exception return. - /// - /// The bits in this field are interpreted as follows: - /// - M[3:2] holds the Exception Level. - /// - M[1] is unused and is RES 0 for all non-reserved values. - /// - M[0] is used to select the SP: - /// - 0 means the SP is always SP0. - /// - 1 means the exception SP is determined by the EL. - M OFFSET(0) NUMBITS(4) [ - EL0t = 0b0000, - EL1t = 0b0100, - EL1h = 0b0101, - EL2t = 0b1000, - EL2h = 0b1001 - ] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u32, "SPSR_EL2"); - sys_coproc_write_raw!(u32, "SPSR_EL2"); -} - -pub static SPSR_EL2: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/tcr_el1.rs b/crate/aarch64/src/regs/tcr_el1.rs deleted file mode 100644 index 9ebb6d7..0000000 --- a/crate/aarch64/src/regs/tcr_el1.rs +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Translation Control Register - EL1 -//! -//! The control register for stage 1 of the EL1&0 translation regime. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u64, - TCR_EL1 [ - /// Top Byte ignored - indicates whether the top byte of an address is - /// used for address match for the TTBR1_EL1 region, or ignored and used - /// for tagged addresses. Defined values are: - /// - /// 0 Top Byte used in the address calculation. - /// 1 Top Byte ignored in the address calculation. - TBI1 OFFSET(38) NUMBITS(1) [ - Used = 0, - Ignored = 1 - ], - - /// Top Byte ignored - indicates whether the top byte of an address is - /// used for address match for the TTBR0_EL1 region, or ignored and used - /// for tagged addresses. Defined values are: - /// - /// 0 Top Byte used in the address calculation. - /// 1 Top Byte ignored in the address calculation. - TBI0 OFFSET(37) NUMBITS(1) [ - Used = 0, - Ignored = 1 - ], - - /// ASID Size. Defined values are: - /// - /// 0 8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by - /// hardware for every purpose except reading back the register, and are - /// treated as if they are all zeros for when used for allocation and matching entries in the TLB. - /// 1 16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for - /// allocation and matching in the TLB. - /// - /// If the implementation has only 8 bits of ASID, this field is RES0. - AS OFFSET(36) NUMBITS(1) [ - Bits_8 = 0, - Bits_16 = 1 - ], - - /// Intermediate Physical Address Size. - /// - /// 000 32 bits, 4GiB. - /// 001 36 bits, 64GiB. - /// 010 40 bits, 1TiB. - /// 011 42 bits, 4TiB. - /// 100 44 bits, 16TiB. - /// 101 48 bits, 256TiB. - /// 110 52 bits, 4PiB - /// - /// Other values are reserved. - /// - /// The reserved values behave in the same way as the 101 or 110 - /// encoding, but software must not rely on this property as the - /// behavior of the reserved values might change in a future revision of - /// the architecture. - /// - /// The value 110 is permitted only if ARMv8.2-LPA is implemented and - /// the translation granule size is 64KiB. - /// - /// In an implementation that supports 52-bit PAs, if the value of this - /// field is not 110 , then bits[51:48] of every translation table base - /// address for the stage of translation controlled by TCR_EL1 are 0000 - /// . - IPS OFFSET(32) NUMBITS(3) [ - Bits_32 = 0b000, - Bits_36 = 0b001, - Bits_40 = 0b010, - Bits_42 = 0b011, - Bits_44 = 0b100, - Bits_48 = 0b101, - Bits_52 = 0b110 - ], - - /// Granule size for the TTBR1_EL1. - /// - /// 01 16KiB - /// 10 4KiB - /// 11 64KiB - /// - /// Other values are reserved. - /// - /// If the value is programmed to either a reserved value, or a size - /// that has not been implemented, then the hardware will treat the - /// field as if it has been programmed to an IMPLEMENTATION DEFINED - /// choice of the sizes that has been implemented for all purposes other - /// than the value read back from this register. - /// - /// It is IMPLEMENTATION DEFINED whether the value read back is the - /// value programmed or the value that corresponds to the size chosen. - TG1 OFFSET(30) NUMBITS(2) [ - KiB_4 = 0b10, - KiB_16 = 0b01, - KiB_64 = 0b11 - ], - - /// Shareability attribute for memory associated with translation table - /// walks using TTBR1_EL1. - /// - /// 00 Non-shareable - /// 10 Outer Shareable - /// 11 Inner Shareable - /// - /// Other values are reserved. - SH1 OFFSET(28) NUMBITS(2) [ - None = 0b00, - Outer = 0b10, - Inner = 0b11 - ], - - /// Outer cacheability attribute for memory associated with translation - /// table walks using TTBR1_EL1. - /// - /// 00 Normal memory, Outer Non-cacheable - /// - /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate - /// Cacheable - /// - /// 10 Normal memory, Outer Write-Through Read-Allocate No - /// Write-Allocate Cacheable - /// - /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate - /// Cacheable - ORGN1 OFFSET(26) NUMBITS(2) [ - NonCacheable = 0b00, - WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, - WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, - WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 - ], - - /// Inner cacheability attribute for memory associated with translation - /// table walks using TTBR1_EL1. - /// - /// 00 Normal memory, Inner Non-cacheable - /// - /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate - /// Cacheable - /// - /// 10 Normal memory, Inner Write-Through Read-Allocate No - /// Write-Allocate Cacheable - /// - /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate - /// Cacheable - IRGN1 OFFSET(24) NUMBITS(2) [ - NonCacheable = 0b00, - WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, - WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, - WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 - ], - - /// Translation table walk disable for translations using - /// TTBR1_EL1. This bit controls whether a translation table walk is - /// performed on a TLB miss, for an address that is translated using - /// TTBR1_EL1. The encoding of this bit is: - /// - /// 0 Perform translation table walks using TTBR1_EL1. - /// - /// 1 A TLB miss on an address that is translated using TTBR1_EL1 - /// generates a Translation fault. No translation table walk is - /// performed. - EPD1 OFFSET(23) NUMBITS(1) [ - EnableTTBR1Walks = 0, - DisableTTBR1Walks = 1 - ], - - /// Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding - /// of this bit is: - /// - /// 0 TTBR0_EL1.ASID defines the ASID. - /// - /// 1 TTBR1_EL1.ASID defines the ASID. - A1 OFFSET(22) NUMBITS(1) [ - UseTTBR0ASID = 0b0, - UseTTBR1ASID = 0b1 - ], - - /// The size offset of the memory region addressed by TTBR1_EL1. The - /// region size is 2^(64-T1SZ) bytes. - /// - /// The maximum and minimum possible values for T1SZ depend on the level - /// of translation table and the memory translation granule size, as - /// described in the AArch64 Virtual Memory System Architecture chapter. - T1SZ OFFSET(16) NUMBITS(6) [], - - /// Granule size for the TTBR0_EL1. - /// - /// 00 4KiB - /// 01 64KiB - /// 10 16KiB - /// - /// Other values are reserved. - /// - /// If the value is programmed to either a reserved value, or a size - /// that has not been implemented, then the hardware will treat the - /// field as if it has been programmed to an IMPLEMENTATION DEFINED - /// choice of the sizes that has been implemented for all purposes other - /// than the value read back from this register. - /// - /// It is IMPLEMENTATION DEFINED whether the value read back is the - /// value programmed or the value that corresponds to the size chosen. - TG0 OFFSET(14) NUMBITS(2) [ - KiB_4 = 0b00, - KiB_16 = 0b10, - KiB_64 = 0b01 - ], - - /// Shareability attribute for memory associated with translation table - /// walks using TTBR0_EL1. - /// - /// 00 Non-shareable - /// 10 Outer Shareable - /// 11 Inner Shareable - /// - /// Other values are reserved. - SH0 OFFSET(12) NUMBITS(2) [ - None = 0b00, - Outer = 0b10, - Inner = 0b11 - ], - - /// Outer cacheability attribute for memory associated with translation - /// table walks using TTBR0_EL1. - /// - /// 00 Normal memory, Outer Non-cacheable - /// - /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate - /// Cacheable - /// - /// 10 Normal memory, Outer Write-Through Read-Allocate No - /// Write-Allocate Cacheable - /// - /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate - /// Cacheable - ORGN0 OFFSET(10) NUMBITS(2) [ - NonCacheable = 0b00, - WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, - WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, - WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 - ], - - /// Inner cacheability attribute for memory associated with translation - /// table walks using TTBR0_EL1. - /// - /// 00 Normal memory, Inner Non-cacheable - /// - /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate - /// Cacheable - /// - /// 10 Normal memory, Inner Write-Through Read-Allocate No - /// Write-Allocate Cacheable - /// - /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate - /// Cacheable - IRGN0 OFFSET(8) NUMBITS(2) [ - NonCacheable = 0b00, - WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01, - WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10, - WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11 - ], - - /// Translation table walk disable for translations using - /// TTBR0_EL1. This bit controls whether a translation table walk is - /// performed on a TLB miss, for an address that is translated using - /// TTBR0_EL1. The encoding of this bit is: - /// - /// 0 Perform translation table walks using TTBR0_EL1. - /// - /// 1 A TLB miss on an address that is translated using TTBR0_EL1 - /// generates a Translation fault. No translation table walk is - /// performed. - EPD0 OFFSET(7) NUMBITS(1) [ - EnableTTBR0Walks = 0, - DisableTTBR0Walks = 1 - ], - - /// The size offset of the memory region addressed by TTBR0_EL1. The - /// region size is 2^(64-T0SZ) bytes. - /// - /// The maximum and minimum possible values for T0SZ depend on the level - /// of translation table and the memory translation granule size, as - /// described in the AArch64 Virtual Memory System Architecture chapter. - T0SZ OFFSET(0) NUMBITS(6) [] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "TCR_EL1"); - sys_coproc_write_raw!(u64, "TCR_EL1"); -} - -pub static TCR_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/ttbr0_el1.rs b/crate/aarch64/src/regs/ttbr0_el1.rs deleted file mode 100644 index a29ff79..0000000 --- a/crate/aarch64/src/regs/ttbr0_el1.rs +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Translation Table Base Register 0 - EL1 -//! -//! Holds the base address of the translation table for the initial lookup for -//! stage 1 of the translation of an address from the lower VA range in the -//! EL1&0 translation regime, and other information for this translation regime. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u64, - TTBR0_EL1 [ - /// An ASID for the translation table base address. The TCR_EL1.A1 field - /// selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID. - /// - /// If the implementation has only 8 bits of ASID, then the upper 8 bits - /// of this field are RES 0. - ASID OFFSET(48) NUMBITS(16) [], - - /// Translation table base address - BADDR OFFSET(1) NUMBITS(47) [], - - /// Common not Private - CnP OFFSET(0) NUMBITS(1) [] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "TTBR0_EL1"); - sys_coproc_write_raw!(u64, "TTBR0_EL1"); -} - -impl Reg { - #[inline] - pub fn get_baddr(&self) -> u64 { - self.read(TTBR0_EL1::BADDR) << 1 - } - - #[inline] - pub fn set_baddr(&self, addr: u64) { - self.write(TTBR0_EL1::BADDR.val(addr >> 1)); - } -} - -pub static TTBR0_EL1: Reg = Reg {}; diff --git a/crate/aarch64/src/regs/ttbr1_el1.rs b/crate/aarch64/src/regs/ttbr1_el1.rs deleted file mode 100644 index 7df383c..0000000 --- a/crate/aarch64/src/regs/ttbr1_el1.rs +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018 by the author(s) - * - * ============================================================================= - * - * Licensed under either of - * - Apache License, Version 2.0 (http://www.apache.org/licenses/LICENSE-2.0) - * - MIT License (http://opensource.org/licenses/MIT) - * at your option. - * - * ============================================================================= - * - * Author(s): - * - Andre Richter - */ - -//! Translation Table Base Register 1 - EL1 -//! -//! Holds the base address of the translation table for the initial lookup for -//! stage 1 of the translation of an address from the upper VA range in the -//! EL1&0 translation regime, and other information for this translation regime. - -use register::cpu::RegisterReadWrite; - -register_bitfields! {u64, - TTBR1_EL1 [ - /// An ASID for the translation table base address. The TCR_EL1.A1 field - /// selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID. - /// - /// If the implementation has only 8 bits of ASID, then the upper 8 bits - /// of this field are RES 0. - ASID OFFSET(48) NUMBITS(16) [], - - /// Translation table base address - BADDR OFFSET(1) NUMBITS(47) [], - - /// Common not Private - CnP OFFSET(0) NUMBITS(1) [] - ] -} - -pub struct Reg; - -impl RegisterReadWrite for Reg { - sys_coproc_read_raw!(u64, "TTBR1_EL1"); - sys_coproc_write_raw!(u64, "TTBR1_EL1"); -} - -impl Reg { - #[inline] - pub fn get_baddr(&self) -> u64 { - self.read(TTBR1_EL1::BADDR) << 1 - } - - #[inline] - pub fn set_baddr(&self, addr: u64) { - self.write(TTBR1_EL1::BADDR.val(addr >> 1)); - } -} - -pub static TTBR1_EL1: Reg = Reg {}; diff --git a/kernel/Cargo.lock b/kernel/Cargo.lock index 4e2b6dc..d3dd0be 100644 --- a/kernel/Cargo.lock +++ b/kernel/Cargo.lock @@ -1,6 +1,7 @@ [[package]] name = "aarch64" -version = "0.1.0" +version = "2.2.2" +source = "git+https://github.com/equation314/aarch64#47bf5439f5a1379f0fef6272853cf684207a4e45" dependencies = [ "bare-metal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)", "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -256,7 +257,7 @@ dependencies = [ name = "ucore" version = "0.1.0" dependencies = [ - "aarch64 0.1.0", + "aarch64 2.2.2 (git+https://github.com/equation314/aarch64)", "atags 0.1.0", "bbl 0.1.0", "bcm2837 0.1.0", @@ -362,6 +363,7 @@ version = "0.1.2" source = "registry+https://github.com/rust-lang/crates.io-index" [metadata] +"checksum aarch64 2.2.2 (git+https://github.com/equation314/aarch64)" = "" "checksum bare-metal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "1bdcf9294ed648c7cd29b11db06ea244005aeef50ae8f605b1a3af2940bf8f92" "checksum bit-vec 0.5.0 (git+https://github.com/AltSysrq/bit-vec.git)" = "" "checksum bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "ed8765909f9009617974ab6b7d332625b320b33c326b1e9321382ef1999b5d56" diff --git a/kernel/Cargo.toml b/kernel/Cargo.toml index 20b696f..316b21c 100644 --- a/kernel/Cargo.toml +++ b/kernel/Cargo.toml @@ -44,7 +44,7 @@ riscv = { path = "../crate/riscv" } bbl = { path = "../crate/bbl" } [target.'cfg(target_arch = "aarch64")'.dependencies] -aarch64 = { path = "../crate/aarch64" } +aarch64 = { git = "https://github.com/equation314/aarch64" } atags = { path = "../crate/atags" } bcm2837 = { path = "../crate/bcm2837", features = ["use_generic_timer"] }