chyyuu
6 years ago
commit
252449a198
@ -0,0 +1,112 @@
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-dev";
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model = "freechips,rocketchip-unknown";
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L14: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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L5: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <16384>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <16384>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L6>;
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reg = <0>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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timebase-frequency = <1000000>;
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tlb-split;
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L3: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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L6: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>;
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};
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L13: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
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ranges;
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L11: blkdev-controller@10015000 {
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compatible = "ucbbar,blkdev";
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interrupt-parent = <&L0>;
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interrupts = <3>;
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reg = <0x10015000 0x1000>;
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reg-names = "control";
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};
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L1: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&L3 3 &L3 7>;
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reg = <0x2000000 0x10000>;
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reg-names = "control";
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};
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L2: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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interrupts-extended = <&L3 65535>;
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reg = <0x0 0x1000>;
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reg-names = "control";
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};
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L8: error-device@3000 {
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compatible = "sifive,error0";
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reg = <0x3000 0x1000>;
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reg-names = "mem";
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};
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L10: external-interrupts {
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interrupt-parent = <&L0>;
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interrupts = <1 2>;
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};
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L0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L3 11 &L3 9>;
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reg = <0xc000000 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <3>;
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};
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L7: mmio-port-axi4@60000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x60000000 0x60000000 0x20000000>;
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serial0: serial@60000000 {
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compatible = "xlnx,xps-uartlite-1.00.a";
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reg = <0x6000000 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <1>;
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};
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axi_intc: axi_intc@61200000 {
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compatible = "xlnx,xps-intc-1.00.a";
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reg = <0x61200000 0x1000>;
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interrupt-parent = <&L10>;
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interrupts = <1>;
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};
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};
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L9: rom@10000 {
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compatible = "sifive,rom0";
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reg = <0x10000 0x10000>;
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reg-names = "mem";
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};
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};
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};
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@ -0,0 +1,50 @@
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/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore */
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/* Simple linker script for the ucore kernel.
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See the GNU ld 'info' manual ("info ld") to learn the syntax. */
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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BASE_ADDRESS = 0xffffffffc0200000;
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SECTIONS
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{
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/* Load the kernel at this address: "." means the current address */
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. = BASE_ADDRESS;
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start = .;
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.text : {
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stext = .;
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*(.text.entry)
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*(.text .text.*)
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. = ALIGN(4K);
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etext = .;
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}
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.rodata : {
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srodata = .;
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*(.rodata .rodata.*)
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*(.dtb)
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. = ALIGN(4K);
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erodata = .;
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}
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.data : {
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sdata = .;
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*(.data .data.*)
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edata = .;
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}
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.stack : {
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*(.bss.stack)
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}
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.bss : {
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sbss = .;
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*(.bss .bss.*)
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ebss = .;
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}
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PROVIDE(end = .);
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}
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@ -0,0 +1,46 @@
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use super::consts::KERNEL_OFFSET;
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/// Mask all external interrupt except serial.
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pub unsafe fn init_external_interrupt() {
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const HART0_S_MODE_INTERRUPT_ENABLES: *mut u64 = (KERNEL_OFFSET + 0x0C00_2080) as *mut u64;
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HART0_S_MODE_INTERRUPT_ENABLES.write_volatile(0xf);
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// mask interrupts first
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const AXI_INTC_IER: *mut u32 = (KERNEL_OFFSET + 0x1900_0008) as *mut u32;
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AXI_INTC_IER.write_volatile(0x0);
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// acknowledge all interrupts
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const AXI_INTC_IAR: *mut u32 = (KERNEL_OFFSET + 0x1900_000C) as *mut u32;
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AXI_INTC_IAR.write_volatile(0xffffffff);
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const AXI_INTC_MER: *mut u32 = (KERNEL_OFFSET + 0x1900_001C) as *mut u32;
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// Hardware Interrupt enable | Enable irq output
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AXI_INTC_MER.write_volatile(0b11);
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// enable all interrupts
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AXI_INTC_IER.write_volatile(0xffffffff);
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}
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/// Claim and complete external interrupt by reading and writing to
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/// PLIC Interrupt Claim/Complete Register.
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pub unsafe fn handle_external_interrupt() {
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const HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE: *mut u32 =
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(KERNEL_OFFSET + 0x0C20_1004) as *mut u32;
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// claim
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let source = HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE.read_volatile();
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// complete
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HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE.write_volatile(source);
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// acknowledge all interrupts
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const AXI_INTC_IAR: *mut u32 = (KERNEL_OFFSET + 0x1900_000C) as *mut u32;
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AXI_INTC_IAR.write_volatile(0xffffffff);
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}
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pub unsafe fn enable_serial_interrupt() {
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const SERIAL_BASE: *mut u32 = (KERNEL_OFFSET + 0x18000000) as *mut u32;
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const UART_CTRL_REG: usize = 3;
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// Intr enable | rx reset | tx reset
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const UART_IE: u32 = 0x13;
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SERIAL_BASE.add(UART_CTRL_REG).write_volatile(UART_IE);
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}
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