From 9001ac1f3d0fb3727658e21ae5d88bac0a354b43 Mon Sep 17 00:00:00 2001
From: WangRunji <wangrunji0408@163.com>
Date: Fri, 13 Jul 2018 00:00:42 +0800
Subject: [PATCH] Fix enter second kernel thread. But page fault now.

---
 src/arch/riscv32/context.rs          | 22 ++++++++--------------
 src/arch/riscv32/interrupt.rs        |  4 +++-
 src/arch/x86_64/interrupt/handler.rs | 12 ++----------
 src/lib.rs                           |  7 +------
 src/process/mod.rs                   | 12 +++++++-----
 src/trap.rs                          | 14 ++++++++++++++
 6 files changed, 35 insertions(+), 36 deletions(-)
 create mode 100644 src/trap.rs

diff --git a/src/arch/riscv32/context.rs b/src/arch/riscv32/context.rs
index b108322..8ac7e58 100644
--- a/src/arch/riscv32/context.rs
+++ b/src/arch/riscv32/context.rs
@@ -44,13 +44,7 @@ impl InitStack {
 }
 
 extern {
-    fn trap_ret();
-}
-
-/// The entry point of new thread
-extern fn forkret() {
-    debug!("forkret");
-    // Will return to `trapret`
+    fn __trapret();
 }
 
 #[derive(Debug, Default)]
@@ -63,7 +57,7 @@ struct ContextData {
 
 impl ContextData {
     fn new(satp: usize) -> Self {
-        ContextData { ra: forkret as usize, satp, ..ContextData::default() }
+        ContextData { ra: __trapret as usize, satp, ..ContextData::default() }
     }
 }
 
@@ -84,8 +78,8 @@ impl Context {
         asm!(
         "
         // save from's registers
-        sub sp, -14*4
-        sw sp, (a0)
+        addi sp, sp, -4*14
+        sw sp, 0(a0)
         sw ra, 0*4(sp)
         sw s0, 2*4(sp)
         sw s1, 3*4(sp)
@@ -103,7 +97,7 @@ impl Context {
         sw s11, 1*4(sp)
 
         // restore to's registers
-        lw sp, (a1)
+        lw sp, 0(a1)
         lw s11, 1*4(sp)
         csrrw x0, 0x180, s11 // satp
         lw ra, 0*4(sp)
@@ -119,11 +113,11 @@ impl Context {
         lw s9, 11*4(sp)
         lw s10, 12*4(sp)
         lw s11, 13*4(sp)
-        add sp, 14*4
+        addi sp, sp, 4*14
 
-        sw zero, (a1)
+        sw zero, 0(a1)
         ret"
-        : : : : "intel" "volatile" )
+        : : : : "volatile" )
     }
 
     pub unsafe fn null() -> Self {
diff --git a/src/arch/riscv32/interrupt.rs b/src/arch/riscv32/interrupt.rs
index 63e2376..248b71a 100644
--- a/src/arch/riscv32/interrupt.rs
+++ b/src/arch/riscv32/interrupt.rs
@@ -32,14 +32,16 @@ pub unsafe fn restore(flags: usize) {
 #[no_mangle]
 pub extern fn rust_trap(tf: &mut TrapFrame) {
     use super::riscv::register::scause::{Trap, Interrupt, Exception};
+    trace!("Interrupt: {:?}", tf.scause.cause());
     match tf.scause.cause() {
         Trap::Interrupt(SupervisorTimer) => timer(),
         _ => panic!("Unhandled interrupt: {:?}\n{:#x?}", tf.scause.cause(), tf),
     }
+    ::trap::before_return();
 }
 
 fn timer() {
-    ::timer_interrupt();
+    ::trap::timer();
     super::timer::set_next();
 }
 
diff --git a/src/arch/x86_64/interrupt/handler.rs b/src/arch/x86_64/interrupt/handler.rs
index 0de47ed..513a925 100644
--- a/src/arch/x86_64/interrupt/handler.rs
+++ b/src/arch/x86_64/interrupt/handler.rs
@@ -78,7 +78,7 @@ pub extern fn rust_trap(tf: &mut TrapFrame) {
         T_IRQ0...63 => {
             let irq = tf.trap_num as u8 - T_IRQ0;
             match irq {
-                IRQ_TIMER => timer(),
+                IRQ_TIMER => ::trap::timer(),
                 IRQ_KBD => keyboard(),
                 IRQ_COM1 => com1(),
                 IRQ_COM2 => com2(),
@@ -97,11 +97,7 @@ pub extern fn rust_trap(tf: &mut TrapFrame) {
         T_DIVIDE | T_GPFLT | T_ILLOP => error(tf),
         _ => panic!("Unhandled interrupt {:x}", tf.trap_num),
     }
-
-    use process::PROCESSOR;
-    if let Some(processor) = PROCESSOR.try() {
-        processor.lock().schedule();
-    }
+    ::trap::before_return();
 }
 
 fn breakpoint() {
@@ -145,10 +141,6 @@ fn com2() {
     COM2.lock().receive();
 }
 
-fn timer() {
-    ::timer_interrupt();
-}
-
 fn to_user(tf: &mut TrapFrame) {
     use arch::gdt;
     info!("\nInterupt: To User");
diff --git a/src/lib.rs b/src/lib.rs
index 96a2ced..03164ab 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -70,6 +70,7 @@ mod syscall;
 mod fs;
 mod thread;
 mod sync;
+mod trap;
 
 #[allow(dead_code)]
 #[cfg(target_arch = "x86_64")]
@@ -80,12 +81,6 @@ mod arch;
 #[path = "arch/riscv32/mod.rs"]
 mod arch;
 
-fn timer_interrupt() {
-    use process::PROCESSOR;
-    let mut processor = PROCESSOR.try().unwrap().lock();
-    processor.tick();
-}
-
 #[no_mangle]
 #[cfg(target_arch = "riscv")]
 pub extern fn rust_main() -> ! {
diff --git a/src/process/mod.rs b/src/process/mod.rs
index 381c22d..ed88e5c 100644
--- a/src/process/mod.rs
+++ b/src/process/mod.rs
@@ -15,16 +15,18 @@ pub fn init() {
         SpinNoIrqLock::new({
             let initproc = Process::new_init();
             let idleproc = Process::new("idle", idle_thread, 0);
-        let mut processor = Processor::new();
-        processor.add(initproc);
-        processor.add(idleproc);
-        processor
-    })});
+            let mut processor = Processor::new();
+            processor.add(initproc);
+            processor.add(idleproc);
+            processor
+        })
+    });
 }
 
 pub static PROCESSOR: Once<SpinNoIrqLock<Processor>> = Once::new();
 
 extern fn idle_thread(_arg: usize) -> ! {
+    println!("Hello, I'm idle.");
     loop {}
 }
 
diff --git a/src/trap.rs b/src/trap.rs
new file mode 100644
index 0000000..be91528
--- /dev/null
+++ b/src/trap.rs
@@ -0,0 +1,14 @@
+use process::PROCESSOR;
+
+
+pub fn timer() {
+    let mut processor = PROCESSOR.try().unwrap().lock();
+    processor.tick();
+}
+
+pub fn before_return() {
+    use process::PROCESSOR;
+    if let Some(processor) = PROCESSOR.try() {
+        processor.lock().schedule();
+    }
+}
\ No newline at end of file