Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel

master
Yuhao Zhou 6 years ago
commit 94d4d01cd5

@ -12,7 +12,6 @@ pub mod driver;
use log::*;
use mips::registers::cp0;
use mips::instructions;
#[cfg(feature = "board_malta")]
#[path = "board/malta/mod.rs"]
@ -40,7 +39,6 @@ pub extern fn rust_main() -> ! {
let ebase = cp0::ebase::read_u32();
let cpu_id = ebase & 0x3ff;
let dtb_start = _dtb_start as usize;
let dtb_end = _dtb_end as usize;
if cpu_id != BOOT_CPU_ID {
// TODO: run others_main on other CPU

@ -1,5 +1,7 @@
//! 16550 serial adapter driver for malta board
#![allow(dead_code)]
use core::fmt::{Write, Result, Arguments};
use core::ptr::{read_volatile, write_volatile};
use spin::Mutex;

@ -216,7 +216,7 @@ impl MutexSupport for Spin {
unsafe {
#[cfg(target_arch = "x86_64")]
asm!("pause" :::: "volatile");
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "mips"))]
asm!("nop" :::: "volatile");
#[cfg(target_arch = "aarch64")]
asm!("yield" :::: "volatile");
@ -254,7 +254,7 @@ impl MutexSupport for SpinNoIrq {
unsafe {
#[cfg(target_arch = "x86_64")]
asm!("pause" :::: "volatile");
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "mips"))]
asm!("nop" :::: "volatile");
#[cfg(target_arch = "aarch64")]
asm!("yield" :::: "volatile");

@ -1 +1 @@
Subproject commit 67890aeb4205083d5a95b1f70de92ae39b549c8c
Subproject commit a460c5b32744292ed50922a159fa22c830aa61b9
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