Add timer for mips.

kernel/Cargo.toml

@@ -69,7 +69,7 @@ riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 aarch64 = { git = "https://github.com/rcore-os/aarch64" }
 bcm2837 = { git = "https://github.com/rcore-os/bcm2837", optional = true }
 
-[target.'cfg(target_arch = "mipsel")'.dependencies]
+[target.'cfg(target_arch = "mips")'.dependencies]
 mips = "^0.1.0"
 
 [package.metadata.bootimage]

kernel/src/arch/mipsel/consts.rs

@@ -39,4 +39,4 @@ pub const USER_STACK_OFFSET: usize = 0x80000000 - USER_STACK_SIZE;
 pub const USER_STACK_SIZE: usize = 0x10000;
 pub const USER32_STACK_OFFSET: usize = 0xC0000000 - USER_STACK_SIZE;
 
-pub const MAX_DTB_SIZE: usize = 0x2000;
+pub const MAX_DTB_SIZE: usize = 0x2000;

kernel/src/arch/mipsel/timer.rs

@@ -1,24 +1,6 @@
-use riscv::register::*;
-use super::sbi;
+use mips::registers::cp0;
 use log::*;
 
-#[cfg(target_pointer_width = "64")]
-pub fn get_cycle() -> u64 {
-    time::read() as u64
-}
-
-#[cfg(target_pointer_width = "32")]
-pub fn get_cycle() -> u64 {
-    loop {
-        let hi = timeh::read();
-        let lo = time::read();
-        let tmp = timeh::read();
-        if hi == tmp {
-            return ((hi as u64) << 32) | (lo as u64);
-        }
-    }
-}
-
 pub fn read_epoch() -> u64 {
     // TODO: support RTC
     0
@@ -27,7 +9,7 @@ pub fn read_epoch() -> u64 {
 /// Enable timer interrupt
 pub fn init() {
     // Enable supervisor timer interrupt
-    unsafe { sie::set_stimer(); }
+    cp0::status::enable_hard_int5();  // IP(7), timer interrupt
     set_next();
     info!("timer: init end");
 }
@@ -36,5 +18,6 @@ pub fn init() {
 pub fn set_next() {
     // 100Hz @ QEMU
     let timebase = 250000;
-    sbi::set_timer(get_cycle() + timebase);
+    cp0::count::write_u32(0);
+    cp0::compare::write_u32(timebase);
 }