From b8460e20d88d2a7876a399a03ef9a10713f8a01b Mon Sep 17 00:00:00 2001 From: WangRunji Date: Fri, 15 Mar 2019 01:58:19 +0800 Subject: [PATCH] fix riscv syscall ABI. fix store user tp and kernel hartid --- kernel/src/arch/riscv32/boot/trap.asm | 32 +++++++++++++++------------ kernel/src/arch/riscv32/context.rs | 5 +++-- kernel/src/arch/riscv32/cpu.rs | 4 ++-- kernel/src/arch/riscv32/interrupt.rs | 6 ++--- user | 2 +- 5 files changed, 27 insertions(+), 22 deletions(-) diff --git a/kernel/src/arch/riscv32/boot/trap.asm b/kernel/src/arch/riscv32/boot/trap.asm index 35f2e44..59d2fc2 100644 --- a/kernel/src/arch/riscv32/boot/trap.asm +++ b/kernel/src/arch/riscv32/boot/trap.asm @@ -15,18 +15,18 @@ # the kernel stack pointer. If we came from the kernel, sscratch # will contain 0, and we should continue on the current stack. csrrw sp, (xscratch), sp - bnez sp, _save_context -_restore_kernel_sp: + bnez sp, trap_from_user +trap_from_kernel: csrr sp, (xscratch) + STORE gp, 0 # sscratch = previous-sp, sp = kernel-sp -_save_context: +trap_from_user: # provide room for trap frame addi sp, sp, -36 * XLENB # save x registers except x2 (sp) STORE x1, 1 STORE x3, 3 - # tp(x4) = hartid. DON'T change. - # STORE x4, 4 + STORE x4, 4 STORE x5, 5 STORE x6, 6 STORE x7, 7 @@ -55,6 +55,9 @@ _save_context: STORE x30, 30 STORE x31, 31 + # load hartid to gp from sp[36] + LOAD gp, 36 + # get sp, sstatus, sepc, stval, scause # set sscratch = 0 csrrw s0, (xscratch), x0 @@ -74,11 +77,12 @@ _save_context: LOAD s1, 32 # s1 = sstatus LOAD s2, 33 # s2 = sepc TEST_BACK_TO_KERNEL - bnez s0, _restore_context # s0 = back to kernel? -_save_kernel_sp: + bnez s0, _to_kernel # s0 = back to kernel? +_to_user: addi s0, sp, 36*XLENB - csrw (xscratch), s0 # sscratch = kernel-sp -_restore_context: + csrw (xscratch), s0 # sscratch = kernel-sp + STORE gp, 36 # store hartid from gp to sp[36] +_to_kernel: # restore sstatus, sepc csrw (xstatus), s1 csrw (xepc), s2 @@ -86,7 +90,7 @@ _restore_context: # restore x registers except x2 (sp) LOAD x1, 1 LOAD x3, 3 - # LOAD x4, 4 + LOAD x4, 4 LOAD x5, 5 LOAD x6, 6 LOAD x7, 7 @@ -119,13 +123,13 @@ _restore_context: .endm .section .text - .globl __alltraps -__alltraps: + .globl trap_entry +trap_entry: SAVE_ALL mv a0, sp jal rust_trap - .globl __trapret -__trapret: + .globl trap_return +trap_return: RESTORE_ALL # return from supervisor call XRET diff --git a/kernel/src/arch/riscv32/context.rs b/kernel/src/arch/riscv32/context.rs index 18499fe..73b9df1 100644 --- a/kernel/src/arch/riscv32/context.rs +++ b/kernel/src/arch/riscv32/context.rs @@ -19,6 +19,7 @@ pub struct TrapFrame { pub sepc: usize, // Supervisor exception program counter, save the trap virtual address (here is used to save the process program entry addr?) pub stval: usize, // Supervisor trap value pub scause: Mcause, // scause register: record the cause of exception/interrupt/trap + pub _hartid: usize, // reserve space } /// Generate the trapframe for building new thread in kernel @@ -123,7 +124,7 @@ impl InitStack { } extern { - fn __trapret(); + fn trap_return(); } #[derive(Debug, Default)] @@ -137,7 +138,7 @@ struct ContextData { impl ContextData { fn new(satp: usize) -> Self { // satp(asid) just like cr3, save the physical address for Page directory? - ContextData { ra: __trapret as usize, satp, ..ContextData::default() } + ContextData { ra: trap_return as usize, satp, ..ContextData::default() } } } diff --git a/kernel/src/arch/riscv32/cpu.rs b/kernel/src/arch/riscv32/cpu.rs index 5b17f54..331a82f 100644 --- a/kernel/src/arch/riscv32/cpu.rs +++ b/kernel/src/arch/riscv32/cpu.rs @@ -4,13 +4,13 @@ use core::ptr::{read_volatile, write_volatile}; static mut STARTED: [bool; MAX_CPU_NUM] = [false; MAX_CPU_NUM]; pub unsafe fn set_cpu_id(cpu_id: usize) { - asm!("mv tp, $0" : : "r"(cpu_id)); + asm!("mv gp, $0" : : "r"(cpu_id)); } pub fn id() -> usize { let cpu_id; #[cfg(not(feature = "m_mode"))] - unsafe { asm!("mv $0, tp" : "=r"(cpu_id)); } + unsafe { asm!("mv $0, gp" : "=r"(cpu_id)); } #[cfg(feature = "m_mode")] unsafe { asm!("csrr $0, mhartid" : "=r"(cpu_id)); } cpu_id diff --git a/kernel/src/arch/riscv32/interrupt.rs b/kernel/src/arch/riscv32/interrupt.rs index bd6f4cf..bb33d85 100644 --- a/kernel/src/arch/riscv32/interrupt.rs +++ b/kernel/src/arch/riscv32/interrupt.rs @@ -24,14 +24,14 @@ mod context; */ pub fn init() { extern { - fn __alltraps(); + fn trap_entry(); } unsafe { // Set sscratch register to 0, indicating to exception vector that we are // presently executing in the kernel xscratch::write(0); // Set the exception vector address - xtvec::write(__alltraps as usize, xtvec::TrapMode::Direct); + xtvec::write(trap_entry as usize, xtvec::TrapMode::Direct); // Enable IPI sie::set_ssoft(); // Enable serial interrupt @@ -168,7 +168,7 @@ fn timer() { */ fn syscall(tf: &mut TrapFrame) { tf.sepc += 4; // Must before syscall, because of fork. - let ret = crate::syscall::syscall(tf.x[10], [tf.x[11], tf.x[12], tf.x[13], tf.x[14], tf.x[15], tf.x[16]], tf); + let ret = crate::syscall::syscall(tf.x[17], [tf.x[10], tf.x[11], tf.x[12], tf.x[13], tf.x[14], tf.x[15]], tf); tf.x[10] = ret as usize; } diff --git a/user b/user index f0441d1..5ce1d2f 160000 --- a/user +++ b/user @@ -1 +1 @@ -Subproject commit f0441d1fe30022acfadced2224b00ed9a29db455 +Subproject commit 5ce1d2f7887b026ab5c5eb60f5aa4fb57390d349