From cd23967f97b4bb4cd007b97c35978dbcf55fc3db Mon Sep 17 00:00:00 2001
From: Jiajie Chen <noc@jiegec.ac.cn>
Date: Fri, 15 Mar 2019 12:39:55 +0800
Subject: [PATCH] Fix riscv32 hartid saving

---
 kernel/src/arch/riscv32/boot/trap.asm | 6 +++---
 user                                  | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/kernel/src/arch/riscv32/boot/trap.asm b/kernel/src/arch/riscv32/boot/trap.asm
index 59d2fc2..3ebd1ed 100644
--- a/kernel/src/arch/riscv32/boot/trap.asm
+++ b/kernel/src/arch/riscv32/boot/trap.asm
@@ -18,11 +18,11 @@
     bnez sp, trap_from_user
 trap_from_kernel:
     csrr sp, (xscratch)
-    STORE gp, 0
+    STORE gp, -1
     # sscratch = previous-sp, sp = kernel-sp
 trap_from_user:
     # provide room for trap frame
-    addi sp, sp, -36 * XLENB
+    addi sp, sp, -37 * XLENB
     # save x registers except x2 (sp)
     STORE x1, 1
     STORE x3, 3
@@ -79,7 +79,7 @@ trap_from_user:
     TEST_BACK_TO_KERNEL
     bnez s0, _to_kernel     # s0 = back to kernel?
 _to_user:
-    addi s0, sp, 36*XLENB
+    addi s0, sp, 37*XLENB
     csrw (xscratch), s0     # sscratch = kernel-sp
     STORE gp, 36            # store hartid from gp to sp[36]
 _to_kernel:
diff --git a/user b/user
index 5ce1d2f..0029070 160000
--- a/user
+++ b/user
@@ -1 +1 @@
-Subproject commit 5ce1d2f7887b026ab5c5eb60f5aa4fb57390d349
+Subproject commit 0029070acbbdb1c51f9ed5defda082a56c3a685b