From daee1e9f94fc6c3e9500897ea6ad0e12926ee579 Mon Sep 17 00:00:00 2001
From: WangRunji <wangrunji0408@163.com>
Date: Thu, 27 Dec 2018 21:33:55 +0800
Subject: [PATCH] fix bugs on K210

---
 kernel/src/arch/riscv32/board/k210/boot.asm | 2 ++
 kernel/src/arch/riscv32/cpu.rs              | 6 ++++--
 kernel/src/arch/riscv32/interrupt.rs        | 5 ++++-
 kernel/src/arch/riscv32/mod.rs              | 7 ++-----
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/kernel/src/arch/riscv32/board/k210/boot.asm b/kernel/src/arch/riscv32/board/k210/boot.asm
index e708ac7..92db963 100644
--- a/kernel/src/arch/riscv32/board/k210/boot.asm
+++ b/kernel/src/arch/riscv32/board/k210/boot.asm
@@ -33,4 +33,6 @@ boot:
     sw t0, 0(x1)
 
     csrr a0, mhartid
+    // FIXME: enable core 1
+    li a2, 0    // hart_mask
     j _start
\ No newline at end of file
diff --git a/kernel/src/arch/riscv32/cpu.rs b/kernel/src/arch/riscv32/cpu.rs
index 0f21646..9fc36c0 100644
--- a/kernel/src/arch/riscv32/cpu.rs
+++ b/kernel/src/arch/riscv32/cpu.rs
@@ -10,7 +10,10 @@ pub unsafe fn set_cpu_id(cpu_id: usize) {
 
 pub fn id() -> usize {
     let cpu_id;
+    #[cfg(not(feature = "m_mode"))]
     unsafe { asm!("mv $0, tp" : "=r"(cpu_id)); }
+    #[cfg(feature = "m_mode")]
+    unsafe { asm!("csrr $0, mhartid" : "=r"(cpu_id)); }
     cpu_id
 }
 
@@ -31,6 +34,5 @@ pub unsafe fn start_others(hart_mask: usize) {
 }
 
 pub fn halt() {
-    use riscv::asm::wfi;
-    unsafe { wfi() }
+    unsafe { riscv::asm::wfi() }
 }
\ No newline at end of file
diff --git a/kernel/src/arch/riscv32/interrupt.rs b/kernel/src/arch/riscv32/interrupt.rs
index 22a3674..dc0d92c 100644
--- a/kernel/src/arch/riscv32/interrupt.rs
+++ b/kernel/src/arch/riscv32/interrupt.rs
@@ -10,7 +10,7 @@ use riscv::register::{
     sscratch as xscratch,
     stvec as xtvec,
 };
-use riscv::register::{mcause, mepc, sie};
+use riscv::register::{mcause, mepc, sie, mie};
 pub use self::context::*;
 use crate::memory::{MemorySet, InactivePageTable0};
 use log::*;
@@ -35,6 +35,9 @@ pub fn init() {
         // Enable IPI
         sie::set_ssoft();
         // Enable serial interrupt
+        #[cfg(feature = "m_mode")]
+        mie::set_mext();
+        #[cfg(not(feature = "m_mode"))]
         sie::set_sext();
         // NOTE: In M-mode: mie.MSIE is set by BBL.
         //                  mie.MEIE can not be set in QEMU v3.0
diff --git a/kernel/src/arch/riscv32/mod.rs b/kernel/src/arch/riscv32/mod.rs
index 0944976..7897c9a 100644
--- a/kernel/src/arch/riscv32/mod.rs
+++ b/kernel/src/arch/riscv32/mod.rs
@@ -15,6 +15,8 @@ pub extern fn rust_main(hartid: usize, dtb: usize, hart_mask: usize, functions:
     unsafe { cpu::set_cpu_id(hartid); }
 
     if hartid != 0 {
+        #[cfg(feature = "board_k210")]
+        loop {} // K210: if not, an assert will fail in spin::RwLock ???
         while unsafe { !cpu::has_started(hartid) }  { }
         println!("Hello RISCV! in hart {}, dtb @ {:#x}, functions @ {:#x}", hartid, dtb, functions);
         others_main();
@@ -28,16 +30,11 @@ pub extern fn rust_main(hartid: usize, dtb: usize, hart_mask: usize, functions:
 
     crate::logging::init();
     interrupt::init();
-    info!("interrupt::init end");
     memory::init();
-    info!("memory::init end");
     timer::init();
-    info!("timer::init end");
     crate::process::init();
-    info!("crate::process::init end");
 
     unsafe { cpu::start_others(hart_mask); }
-    info!("going to crate::kmain");
     crate::kmain();
 }