Timer interrupt

crate/riscv

@@ -1 +1 @@
-Subproject commit a3d2a13c0e656936631c6f420a393c2c0038ecc8
+Subproject commit ef046c88fdb7ed0f416f29e034d4679f0e7a2573

src/arch/riscv32/interrupt.rs

@@ -7,12 +7,27 @@ pub fn init() {
         // Enable interrupt
         sstatus::set_sie();
     }
+    println!("interrupt: init end");
 }
 
 #[no_mangle]
 pub extern fn rust_trap(tf: &mut TrapFrame) {
-    println!("Trap:\n{:#x?}", tf);
-    loop {}
+    use super::riscv::register::scause::{Trap, Interrupt, Exception};
+    match tf.scause.cause() {
+        Trap::Interrupt(SupervisorTimer) => timer(),
+        _ => panic!("Unhandled interrupt: {:?}\n{:#x?}", tf.scause.cause(), tf),
+    }
+}
+
+fn timer() {
+    static mut TICK: usize = 0;
+    unsafe {
+        TICK += 1;
+        if TICK % 100 == 0 {
+            println!("timer");
+        }
+    }
+    super::timer::set_next();
 }
 
 #[derive(Debug, Clone)]

src/arch/riscv32/mod.rs

@@ -3,11 +3,11 @@ extern crate bbl;
 
 pub mod serial;
 pub mod interrupt;
+pub mod timer;
 
 pub fn init() {
     println!("Hello RISCV! {}", 123);
     interrupt::init();
-    // Trigger interrupt
-    unsafe { asm!("mret"); }
+    timer::init();
     loop {}
 }

src/arch/riscv32/timer.rs

@@ -0,0 +1,33 @@
+use super::riscv::register::*;
+use super::bbl::sbi;
+
+#[cfg(target_pointer_width = "64")]
+pub fn get_cycle() -> u64 {
+    time::read() as u64
+}
+
+#[cfg(target_pointer_width = "32")]
+pub fn get_cycle() -> u64 {
+    loop {
+        let hi = timeh::read();
+        let lo = time::read();
+        let tmp = timeh::read();
+        if hi == tmp {
+            return ((hi as u64) << 32) | (lo as u64);
+        }
+    }
+}
+
+pub fn init() {
+    // Enable supervisor timer interrupt
+    unsafe { sie::set_stimer(); }
+
+    set_next();
+    println!("timer: init end");
+}
+
+pub fn set_next() {
+    // 100Hz @ QEMU
+    let timebase = 100000;
+    sbi::set_timer(get_cycle() + timebase);
+}