From f055ba7b23eafa67fe758ce173aee6a4757f4deb Mon Sep 17 00:00:00 2001
From: WangRunji <wangrunji0408@163.com>
Date: Thu, 12 Jul 2018 22:44:34 +0800
Subject: [PATCH] Move kernel base to 0x80020000

---
 riscv-pk/bbl/payload.S          | 2 +-
 src/arch/riscv32/boot/linker.ld | 2 +-
 src/consts.rs                   | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/riscv-pk/bbl/payload.S b/riscv-pk/bbl/payload.S
index 6a175aa..e077f98 100644
--- a/riscv-pk/bbl/payload.S
+++ b/riscv-pk/bbl/payload.S
@@ -1,7 +1,7 @@
 #include "encoding.h"
 
   .section ".payload","a",@progbits
-  .align RISCV_PGSHIFT + RISCV_PGLEVEL_BITS
+  .align 17
 
   .globl _payload_start, _payload_end
 _payload_start:
diff --git a/src/arch/riscv32/boot/linker.ld b/src/arch/riscv32/boot/linker.ld
index 6cba877..288fd94 100644
--- a/src/arch/riscv32/boot/linker.ld
+++ b/src/arch/riscv32/boot/linker.ld
@@ -6,7 +6,7 @@
 OUTPUT_ARCH(riscv)
 ENTRY(kern_entry)
 
-BASE_ADDRESS = 0x80400000;  /* equal to payload address in bbl */
+BASE_ADDRESS = 0x80020000;  /* equal to payload address in bbl */
 
 SECTIONS
 {
diff --git a/src/consts.rs b/src/consts.rs
index ba1e7a9..8fa60e8 100644
--- a/src/consts.rs
+++ b/src/consts.rs
@@ -16,9 +16,9 @@ mod riscv {
     const P2_MASK: usize = 0x3ff << 22;
     pub const RECURSIVE_PAGE_PML4: usize = 0x3fe;
     pub const KERNEL_OFFSET: usize = 0;
-    pub const KERNEL_PML4: usize = 0x8040_0000 >> 22;
-    pub const KERNEL_HEAP_OFFSET: usize = 0x8050_0000;
-    pub const KERNEL_HEAP_SIZE: usize = 1 * 1024 * 1024;
+    pub const KERNEL_PML4: usize = 0x8000_0000 >> 22;
+    pub const KERNEL_HEAP_OFFSET: usize = 0x8010_0000;
+    pub const KERNEL_HEAP_SIZE: usize = 0x0010_0000;
     pub const MEMORY_OFFSET: usize = 0x8000_0000;
     pub const MEMORY_END: usize = 0x8080_0000;
     pub const USER_STACK_OFFSET: usize = 0x70000000;