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Refactored RISC-V page table identity mapping into a function. 		6 years ago
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README.md

RustOS

Build Status

Rust port for uCore OS, supporting x86_64 and riscv32i.

Summary

This is a project of THU Operating System (2018 Spring) && Comprehensive Experiment of Computer System (2018 Summer).

Project wiki (internal access only): OS, CECS

Reports (in Chinese): MidReport, FinalReport, RISCV port note

The initial goal is to write a mini OS in Rust with multi-core support. More specifically, it would start from the post of the Writing an OS in Rust series, then reimplement xv6-x86_64 in Rust style.

In fact, it's more complicated than we expected to write an OS starting from scratch. So by the end of OS course, we only finished rewriting ucore_os_lab, without multi-core support. Then as a part of CECS project, we ported it from x86_64 to RISCV32I, and made it work on our FPGA CPU.

Building

Environment

  • Rust toolchain at nightly-2018-08-03
  • cargo-xbuild
  • QEMU >= 2.12.0
  • riscv32
    • RISCV64 GNU toolchain
  • x86_64
    • nasm
    • grub-mkrescue
    • xorriso

How to run

git clone https://github.com/wangrunji0408/RustOS.git --recursive
cd RustOS/kernel
make run arch=riscv32|x86_64
# For FPGA: 
# make run arch=riscv32 board=1

License

The source code is dual-licensed under MIT or the Apache License (Version 2.0).