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84 lines
2.4 KiB
84 lines
2.4 KiB
extern crate aarch64;
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use aarch64::regs::*;
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use volatile::*;
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/// The base address for the ARM generic timer, IRQs, mailboxes
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const GEN_TIMER_REG_BASE: usize = 0x40000000;
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/// Core interrupt sources (ref: QA7 4.10, page 16)
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#[repr(u8)]
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#[allow(dead_code)]
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#[allow(non_snake_case)]
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#[derive(Copy, Clone, PartialEq, Debug)]
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enum CoreInterrupt {
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CNTPSIRQ = 0,
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CNTPNSIRQ = 1,
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CNTHPIRQ = 2,
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CNTVIRQ = 3,
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Mailbox0 = 4,
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Mailbox1 = 5,
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Mailbox2 = 6,
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Mailbox3 = 7,
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Gpu = 8,
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Pmu = 9,
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AxiOutstanding = 10,
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LocalTimer = 11,
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}
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/// Timer, IRQs, mailboxes registers (ref: QA7 chapter 4, page 7)
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#[allow(non_snake_case)]
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#[repr(C)]
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struct Registers {
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CONTROL: Volatile<u32>,
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_unused1: [Volatile<u32>; 8],
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LOCAL_IRQ: Volatile<u32>,
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_unused2: [Volatile<u32>; 3],
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LOCAL_TIMER_CTL: Volatile<u32>,
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LOCAL_TIMER_FLAGS: Volatile<u32>,
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_unused3: Volatile<u32>,
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CORE_TIMER_IRQCNTL: [Volatile<u32>; 4],
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CORE_MAILBOX_IRQCNTL: [Volatile<u32>; 4],
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CORE_IRQ_SRC: [Volatile<u32>; 4],
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}
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/// The ARM generic timer.
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pub struct Timer {
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registers: &'static mut Registers,
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}
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impl Timer {
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/// Returns a new instance of `Timer`.
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pub fn new() -> Timer {
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Timer {
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registers: unsafe { &mut *(GEN_TIMER_REG_BASE as *mut Registers) },
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}
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}
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/// Reads the generic timer's counter and returns the 64-bit counter value.
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/// The returned value is the number of elapsed microseconds.
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pub fn read(&self) -> u64 {
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let cntfrq = CNTFRQ_EL0.get(); // 62500000
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(CNTPCT_EL0.get() * 1000000 / (cntfrq as u64)) as u64
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}
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/// Sets up a match in timer 1 to occur `us` microseconds from now. If
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/// interrupts for timer 1 are enabled and IRQs are unmasked, then a timer
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/// interrupt will be issued in `us` microseconds.
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pub fn tick_in(&mut self, us: u32) {
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let cntfrq = CNTFRQ_EL0.get(); // 62500000
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CNTP_TVAL_EL0.set(((cntfrq as f64) * (us as f64) / 1000000.0) as u32);
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}
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/// Initialization timer
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pub fn init(&mut self) {
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self.registers.CORE_TIMER_IRQCNTL[0].write(1 << (CoreInterrupt::CNTPNSIRQ as u8));
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CNTP_CTL_EL0.write(CNTP_CTL_EL0::ENABLE::SET);
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}
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/// Returns `true` if timer interruption is pending. Otherwise, returns `false`.
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pub fn is_pending(&self) -> bool {
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self.registers.CORE_IRQ_SRC[0].read() & (1 << (CoreInterrupt::CNTPNSIRQ as u8)) != 0
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}
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}
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