You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 
lcy1996 8c30e9bf05
Modified the report for expr4.
6 years ago
crate merge conflict 6 years ago
docs Modified the report for expr4. 6 years ago
kernel Add comment and report for expr4 6 years ago
riscv-pk Code Transplanting: Blocking getchar 6 years ago
user Finish comment for ristv boot. 6 years ago
.gitignore Add Cargo.lock to gitignore. 6 years ago
.gitmodules Fork crate `riscv` as a submodule 7 years ago
.travis.yml Update README, travis, riscv crate. 6 years ago
README.md Remove root Makefile. Add dev docs link. 6 years ago
status.md Update report 7 years ago

README.md

RustOS

Build Status

Rust port for uCore OS, supporting x86_64 and riscv32i.

Dev docs (in Chinese)

Summary

This is a project of THU Operating System (2018 Spring) && Comprehensive Experiment of Computer System (2018 Summer).

Project wiki (internal access only): OS, CECS

Reports (in Chinese): MidReport, FinalReport, RISCV port note

The initial goal is to write a mini OS in Rust with multi-core support. More specifically, it would start from the post of the Writing an OS in Rust series, then reimplement xv6-x86_64 in Rust style.

In fact, it's more complicated than we expected to write an OS starting from scratch. So by the end of OS course, we only finished rewriting ucore_os_lab, without multi-core support. Then as a part of CECS project, we ported it from x86_64 to RISCV32I, and made it work on our FPGA CPU.

Building

Environment

How to run

rustup component add rust-src
cargo install cargo-xbuild bootimage
git clone https://github.com/wangrunji0408/RustOS.git --recursive
cd RustOS/kernel
rustup override set nightly-2018-09-18
make run arch=riscv32|x86_64
# For FPGA: 
# make run arch=riscv32 board=1

License

The source code is dual-licensed under MIT or the Apache License (Version 2.0).