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WangRunji ba4a24ba3b
Fix RV32 multi-core: Setup page table for other cores.
6 years ago
crate Fix processor. Disable interrupt on switching. 6 years ago
docs Add OSLab/exp3 report 6 years ago
kernel Fix RV32 multi-core: Setup page table for other cores. 6 years ago
riscv-pk Switch to RV64 GNU toolchain. Simplify compiler_rt. 6 years ago
user Use rust-lld for RV32. Remove riscv git submodule. 6 years ago
.gitignore Fix x86_64. Not elegant. 6 years ago
.travis.yml Use Vec to replace array in ProcessManager. 6 years ago
README.md Use rust-lld for RV32. Remove riscv git submodule. 6 years ago
status.md Update report 7 years ago

README.md

RustOS

Build Status

Rust port for uCore OS, supporting x86_64 and riscv32i.

Dev docs (in Chinese)

Summary

This is a project of THU Operating System (2018 Spring) && Comprehensive Experiment of Computer System (2018 Summer).

Project wiki (internal access only): OS, CECS

Reports (in Chinese): MidReport, FinalReport, RISCV port note

The initial goal is to write a mini OS in Rust with multi-core support. More specifically, it would start from the post of the Writing an OS in Rust series, then reimplement xv6-x86_64 in Rust style.

In fact, it's more complicated than we expected to write an OS starting from scratch. So by the end of OS course, we only finished rewriting ucore_os_lab, without multi-core support. Then as a part of CECS project, we ported it from x86_64 to RISCV32I, and made it work on our FPGA CPU.

Building

Environment

How to run

rustup component add rust-src
cargo install cargo-xbuild bootimage
git clone https://github.com/wangrunji0408/RustOS.git
cd RustOS/kernel
rustup override set nightly-2018-09-18
make run arch=riscv32|x86_64
# For FPGA: 
# make run arch=riscv32 board=1

License

The source code is dual-licensed under MIT or the Apache License (Version 2.0).