From 4368027c71ed766584d0f6f103c54a24d44e631e Mon Sep 17 00:00:00 2001 From: e <2751886429@qq.com> Date: Fri, 1 Nov 2019 10:19:23 +0800 Subject: [PATCH] first commit --- .../ASM/程序代码ADS1.2/EUCLIDS/EUCLID02.s | 12 + .../程序代码ADS1.2/EUCLIDS/EUCLIDS.mcp | Bin 0 -> 195756 bytes .../EUCLIDS_Data/CWSettingsWindows.stg | Bin 0 -> 2111 bytes .../EUCLIDS_Data/Debug/TargetDataWindows.tdt | Bin 0 -> 50806 bytes .../EUCLIDS/EUCLIDS_Data/DebugRel/EUCLIDS.axf | Bin 0 -> 1240 bytes .../DebugRel/ObjectCode/EUCLID02.o | Bin 0 -> 1288 bytes .../DebugRel/TargetDataWindows.tdt | Bin 0 -> 56603 bytes .../Release/TargetDataWindows.tdt | Bin 0 -> 49432 bytes .../ASM/程序代码ADS1.2/Euclid/EUCLID01.s | 15 + .../ASM/程序代码ADS1.2/Euclid/Euclid.mcp | Bin 0 -> 195756 bytes .../Euclid/Euclid_Data/CWSettingsWindows.stg | Bin 0 -> 3449 bytes .../Euclid_Data/Debug/TargetDataWindows.tdt | Bin 0 -> 50806 bytes .../Euclid/Euclid_Data/DebugRel/Euclid.axf | Bin 0 -> 1600 bytes .../DebugRel/ObjectCode/EUCLID01.o | Bin 0 -> 1340 bytes .../DebugRel/ObjectCode/EUCLID02.o | Bin 0 -> 1268 bytes .../DebugRel/TargetDataWindows.tdt | Bin 0 -> 55385 bytes .../Euclid_Data/Release/TargetDataWindows.tdt | Bin 0 -> 49432 bytes GreatCommonDivisor/ASM/算法说明.doc | Bin 0 -> 653824 bytes .../Target_1_STM32F107VC_1.0.0.dbgconf | 36 + .../C/Listings/startup_stm32f10x_cl.lst | 1480 +++++++++++++ .../C/Objects/Project.build_log.htm | 65 + .../C/Objects/Project_Target 1.dep | 11 + GreatCommonDivisor/C/Objects/main.d | 5 + .../C/Objects/startup_stm32f10x_cl.d | 1 + .../C/Objects/startup_stm32f10x_cl.o | Bin 0 -> 6912 bytes .../C/Objects/system_stm32f10x.d | 3 + .../C/Project.uvguix.Administrator | 1874 +++++++++++++++++ GreatCommonDivisor/C/Project.uvoptx | 207 ++ GreatCommonDivisor/C/Project.uvprojx | 437 ++++ .../C/RTE/Device/STM32F107VC/RTE_Device.h | 1828 ++++++++++++++++ .../Device/STM32F107VC/startup_stm32f10x_cl.s | 368 ++++ .../RTE/Device/STM32F107VC/system_stm32f10x.c | 1094 ++++++++++ .../C/RTE/_Target_1/RTE_Components.h | 20 + GreatCommonDivisor/C/main.c | 18 + 34 files changed, 7474 insertions(+) create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLID02.s create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS.mcp create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS_Data/CWSettingsWindows.stg create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS_Data/Debug/TargetDataWindows.tdt create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS_Data/DebugRel/EUCLIDS.axf create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS_Data/DebugRel/ObjectCode/EUCLID02.o create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS_Data/DebugRel/TargetDataWindows.tdt create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLIDS_Data/Release/TargetDataWindows.tdt create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/EUCLID01.s create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid.mcp create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/CWSettingsWindows.stg create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/Debug/TargetDataWindows.tdt create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/DebugRel/Euclid.axf create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/DebugRel/ObjectCode/EUCLID01.o create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/DebugRel/ObjectCode/EUCLID02.o create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/DebugRel/TargetDataWindows.tdt create mode 100644 GreatCommonDivisor/ASM/程序代码ADS1.2/Euclid/Euclid_Data/Release/TargetDataWindows.tdt create mode 100644 GreatCommonDivisor/ASM/算法说明.doc create mode 100644 GreatCommonDivisor/C/DebugConfig/Target_1_STM32F107VC_1.0.0.dbgconf create mode 100644 GreatCommonDivisor/C/Listings/startup_stm32f10x_cl.lst create mode 100644 GreatCommonDivisor/C/Objects/Project.build_log.htm create mode 100644 GreatCommonDivisor/C/Objects/Project_Target 1.dep create mode 100644 GreatCommonDivisor/C/Objects/main.d create mode 100644 GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.d create mode 100644 GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.o create mode 100644 GreatCommonDivisor/C/Objects/system_stm32f10x.d create mode 100644 GreatCommonDivisor/C/Project.uvguix.Administrator create mode 100644 GreatCommonDivisor/C/Project.uvoptx create mode 100644 GreatCommonDivisor/C/Project.uvprojx create mode 100644 GreatCommonDivisor/C/RTE/Device/STM32F107VC/RTE_Device.h create mode 100644 GreatCommonDivisor/C/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s create mode 100644 GreatCommonDivisor/C/RTE/Device/STM32F107VC/system_stm32f10x.c create mode 100644 GreatCommonDivisor/C/RTE/_Target_1/RTE_Components.h create mode 100644 GreatCommonDivisor/C/main.c diff --git a/GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLID02.s b/GreatCommonDivisor/ASM/程序代码ADS1.2/EUCLIDS/EUCLID02.s new file mode 100644 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+
Vision Build Log

+
Tool Versions:

+IDE-Version: Vision V5.26.2.0
+Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information:  ,  , LIC=----
+ 
+Tool Versions:
+Toolchain:       MDK-Lite  Version: 5.26.2.0
+Toolchain Path:  E:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.26.2.0
+Dialog DLL:      DCM.DLL V1.17.2.0
+Target DLL:      UL2CM3.DLL V1.161.6.0
+Dialog DLL:      TCM.DLL V1.36.1.0
+ 
+
Project:

+E:\Keil_v5\File\Project01\Project.uvprojx
+Project File Date:  10/13/2019
+
+
Output:

+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'E:\Keil_v5\ARM\ARMCC\Bin'
+Rebuild target 'Target 1'
+assembling startup_stm32f10x_cl.s...
+compiling system_stm32f10x.c...
+E:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h(483): error:  #5: cannot open source input file "core_cm3.h": No such file or directory
+  #include "core_cm3.h"
+RTE\Device\STM32F107VC\system_stm32f10x.c: 0 warnings, 1 error
+compiling main.c...
+E:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h(483): error:  #5: cannot open source input file "core_cm3.h": No such file or directory
+  #include "core_cm3.h"
+main.c: 0 warnings, 1 error
+".\Objects\Project.axf" - 2 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
+                Keil.STM32F1xx_DFP.2.3.0
+                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
+   * Component: Startup Version: 1.0.0
+
+
Collection of Component include folders:

+  .\RTE\Device\STM32F107VC
+  .\RTE\_Target_1
+  E:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include
+
+
Collection of Component Files used:

+
+   * Component: Keil::Device:Startup:1.0.0
+      Source file:   Device\Source\system_stm32f10x.c
+      Include file:  RTE_Driver\Config\RTE_Device.h
+      Source file:   Device\Source\ARM\startup_stm32f10x_cl.s
+      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
+Target not created.
+Build Time Elapsed:  00:00:04
+
+ + diff --git a/GreatCommonDivisor/C/Objects/Project_Target 1.dep b/GreatCommonDivisor/C/Objects/Project_Target 1.dep new file mode 100644 index 0000000..96852f7 --- /dev/null +++ b/GreatCommonDivisor/C/Objects/Project_Target 1.dep @@ -0,0 +1,11 @@ +Dependencies for Project 'Project', Target 'Target 1': (DO NOT MODIFY !) +F (.\main.c)(0x5DA2F400)(--c99 --gnu -c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork --split_sections -I.\RTE\Device\STM32F107VC -I.\RTE\_Target_1 -IE:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include -IE:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="526" -D_RTE_ -DSTM32F10X_CL -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d) +I (E:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599EDB3C) +I (E:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x599EDB3C) +I (E:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x5825386C) +I (.\RTE\_Target_1\RTE_Components.h)(0x5DA2F37B) +F (RTE\Device\STM32F107VC\RTE_Device.h)(0x5927DFA6)() +F (RTE\Device\STM32F107VC\startup_stm32f10x_cl.s)(0x5825386C)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork -I.\RTE\Device\STM32F107VC -I.\RTE\_Target_1 -IE:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include -IE:\Keil_v5\ARM\CMSIS\Include --pd "__UVISION_VERSION SETA 526" --pd "_RTE_ SETA 1" --pd "STM32F10X_CL SETA 1" --list .\listings\startup_stm32f10x_cl.lst --xref -o .\objects\startup_stm32f10x_cl.o --depend .\objects\startup_stm32f10x_cl.d) +F (RTE\Device\STM32F107VC\system_stm32f10x.c)(0x5825386C)(--c99 --gnu -c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork --split_sections -I.\RTE\Device\STM32F107VC -I.\RTE\_Target_1 -IE:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include -IE:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="526" -D_RTE_ -DSTM32F10X_CL -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) +I (E:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x5825386C) +I (.\RTE\_Target_1\RTE_Components.h)(0x5DA2F37B) diff --git a/GreatCommonDivisor/C/Objects/main.d b/GreatCommonDivisor/C/Objects/main.d new file mode 100644 index 0000000..26b0687 --- /dev/null +++ b/GreatCommonDivisor/C/Objects/main.d @@ -0,0 +1,5 @@ +.\objects\main.o: main.c +.\objects\main.o: E:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\main.o: E:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\objects\main.o: E:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h +.\objects\main.o: .\RTE\_Target_1\RTE_Components.h diff --git a/GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.d b/GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.d new file mode 100644 index 0000000..54017af --- /dev/null +++ b/GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.d @@ -0,0 +1 @@ +.\objects\startup_stm32f10x_cl.o: RTE\Device\STM32F107VC\startup_stm32f10x_cl.s diff --git a/GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.o b/GreatCommonDivisor/C/Objects/startup_stm32f10x_cl.o new file mode 100644 index 0000000000000000000000000000000000000000..cd505db0bb203ba9e93c32a48284cf8cd8d4391f GIT binary patch literal 6912 zcmeHMZERat8Gi4zZ{uw3ns%RU)?z$wbZjwkKKjMV>Nrm9C0;$-Ni&vlagv+Xt3M*! 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+ + + + 0 + 1366 + 768 + + + + + + 1 + 0 + + 100 + 0 + + .\main.c + 19 + 1 + 15 + 1 + + 0 + + + + + diff --git a/GreatCommonDivisor/C/Project.uvoptx b/GreatCommonDivisor/C/Project.uvoptx new file mode 100644 index 0000000..7e7db60 --- /dev/null +++ b/GreatCommonDivisor/C/Project.uvoptx @@ -0,0 +1,207 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_CL -FS08000000 -FL080000 -FP0($$Device:STM32F107VC$Flash\STM32F10x_CL.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/GreatCommonDivisor/C/Project.uvprojx b/GreatCommonDivisor/C/Project.uvprojx new file mode 100644 index 0000000..8fcb931 --- /dev/null +++ b/GreatCommonDivisor/C/Project.uvprojx @@ -0,0 +1,437 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F107VC + STMicroelectronics + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00010000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_CL -FS08000000 -FL080000 -FP0($$Device:STM32F107VC$Flash\STM32F10x_CL.FLM)) + 0 + $$Device:STM32F107VC$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F107VC$SVD\STM32F107xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Source Group 1 + + + main.c + 1 + .\main.c + + + + + ::Device + + + + + + + + + + + + + + + + + + RTE\Device\STM32F107VC\RTE_Device.h + + + + + + + + RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + + + + + + + + RTE\Device\STM32F107VC\system_stm32f10x.c + + + + + + + + + + diff --git a/GreatCommonDivisor/C/RTE/Device/STM32F107VC/RTE_Device.h b/GreatCommonDivisor/C/RTE/Device/STM32F107VC/RTE_Device.h new file mode 100644 index 0000000..22d1da2 --- /dev/null +++ b/GreatCommonDivisor/C/RTE/Device/STM32F107VC/RTE_Device.h @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/GreatCommonDivisor/C/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s b/GreatCommonDivisor/C/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s new file mode 100644 index 0000000..833ece4 --- /dev/null +++ b/GreatCommonDivisor/C/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s @@ -0,0 +1,368 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/GreatCommonDivisor/C/RTE/Device/STM32F107VC/system_stm32f10x.c b/GreatCommonDivisor/C/RTE/Device/STM32F107VC/system_stm32f10x.c new file mode 100644 index 0000000..71efc85 --- /dev/null +++ b/GreatCommonDivisor/C/RTE/Device/STM32F107VC/system_stm32f10x.c @@ -0,0 +1,1094 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/GreatCommonDivisor/C/RTE/_Target_1/RTE_Components.h b/GreatCommonDivisor/C/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..960af1c --- /dev/null +++ b/GreatCommonDivisor/C/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'Project' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/GreatCommonDivisor/C/main.c b/GreatCommonDivisor/C/main.c new file mode 100644 index 0000000..d9f0074 --- /dev/null +++ b/GreatCommonDivisor/C/main.c @@ -0,0 +1,18 @@ +#include +#include +#include "stm32f10x.h" // Device header + +int gcd(int a,int b){ + + return b?gcd(b,a%b):a; + +} +int main() +{ + int m,n; + printf(""); + scanf("%d",&m); + scanf("%d",&n); + printf("%d %d ԼΪ:%d\n",m,n,gcd(m,n)); + return 0; +}

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z-VIkv%Z~!9Rt&_6F&D30?&@1TC;vwEnbNk&=`*sOc5$|S^!i_Rhp2|!EbXz5`kLae zG9D|^&v7{NOJ>c@((e6G_T$7YJL6=B2X0#C`}T`BrX_ol>!%{a4rHxo;TQ@AN!gP^ z&sJhjO1%bG8QJI^aBb}5)W$%^(&Yw{(|h3BzAoG_MnG%-7}@H%S=k|zp@-yV+M1qF mu&TTf`U>zG!2K%{kQKnH=>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/GreatCommonDivisor/C/Listings/startup_stm32f10x_cl.lst b/GreatCommonDivisor/C/Listings/startup_stm32f10x_cl.lst new file mode 100644 index 0000000..5915a83 --- /dev/null +++ b/GreatCommonDivisor/C/Listings/startup_stm32f10x_cl.lst @@ -0,0 +1,1480 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f10x_cl.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V3.5.0 + 5 00000000 ;* Date : 11-March-2011 + 6 00000000 ;* Description : STM32F10x Connectivity line devi + ces vector table for MDK-ARM + 7 00000000 ;* toolchain. + 8 00000000 ;* This module performs: + 9 00000000 ;* - Set the initial SP + 10 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 11 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 12 00000000 ;* - Configure the clock system + 13 00000000 ;* - Branches to __main in the C li + brary (which eventually + 14 00000000 ;* calls main()). + 15 00000000 ;* After Reset the CortexM3 process + or is in Thread mode, + 16 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 18 00000000 ;******************************************************* + ************************ + 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A + T PROVIDING CUSTOMERS + 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR + DER FOR THEM TO SAVE TIME. + 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB + LE FOR ANY DIRECT, + 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY + CLAIMS ARISING FROM THE + 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM + ERS OF THE CODING + 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR + PRODUCTS. + 25 00000000 ;******************************************************* + ************************ + 26 00000000 + 27 00000000 ; Amount of memory (in bytes) allocated for Stack + 28 00000000 ; Tailor this value to your application needs + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00000400 + Stack_Size + EQU 0x00000400 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 Stack_Mem + SPACE Stack_Size + 37 00000400 __initial_sp + 38 00000400 + 39 00000400 + 40 00000400 ; Heap Configuration + + + +ARM Macro Assembler Page 2 + + + 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 42 00000400 ; + 43 00000400 + 44 00000400 00000200 + Heap_Size + EQU 0x00000200 + 45 00000400 + 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 47 00000000 __heap_base + 48 00000000 Heap_Mem + SPACE Heap_Size + 49 00000200 __heap_limit + 50 00000200 + 51 00000200 PRESERVE8 + 52 00000200 THUMB + 53 00000200 + 54 00000200 + 55 00000200 ; Vector Table Mapped to Address 0 at Reset + 56 00000200 AREA RESET, DATA, READONLY + 57 00000000 EXPORT __Vectors + 58 00000000 EXPORT __Vectors_End + 59 00000000 EXPORT __Vectors_Size + 60 00000000 + 61 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 62 00000004 00000000 DCD Reset_Handler ; Reset Handler + 63 00000008 00000000 DCD NMI_Handler ; NMI Handler + 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 65 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 66 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 68 0000001C 00000000 DCD 0 ; Reserved + 69 00000020 00000000 DCD 0 ; Reserved + 70 00000024 00000000 DCD 0 ; Reserved + 71 00000028 00000000 DCD 0 ; Reserved + 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 74 00000034 00000000 DCD 0 ; Reserved + 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 76 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 77 00000040 + 78 00000040 ; External Interrupts + 79 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper + 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC + + + +ARM Macro Assembler Page 3 + + + 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash + 84 00000054 00000000 DCD RCC_IRQHandler ; RCC + 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 + 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 + 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 + 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 + 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 + 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler + ; DMA1 Channel 2 + 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler + ; DMA1 Channel 3 + 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler + ; DMA1 Channel 4 + 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler + ; DMA1 Channel 5 + 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler + ; DMA1 Channel 6 + 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler + ; DMA1 Channel 7 + 97 00000088 00000000 DCD ADC1_2_IRQHandler + ; ADC1 and ADC2 + 98 0000008C 00000000 DCD CAN1_TX_IRQHandler ; CAN1 TX + 99 00000090 00000000 DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + 102 0000009C 00000000 DCD EXTI9_5_IRQHandler + ; EXTI Line 9..5 + 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler + ; TIM1 Break + 104 000000A4 00000000 DCD TIM1_UP_IRQHandler + ; TIM1 Update + 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion + 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C1 Error + + 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + 119 000000E0 00000000 DCD EXTI15_10_IRQHandler + ; EXTI Line 15..10 + 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC alarm + through EXTI line + 121 000000E8 00000000 DCD OTG_FS_WKUP_IRQHandler ; USB OT + + + +ARM Macro Assembler Page 4 + + + G FS Wakeup through + EXTI line + 122 000000EC 00000000 DCD 0 ; Reserved + 123 000000F0 00000000 DCD 0 ; Reserved + 124 000000F4 00000000 DCD 0 ; Reserved + 125 000000F8 00000000 DCD 0 ; Reserved + 126 000000FC 00000000 DCD 0 ; Reserved + 127 00000100 00000000 DCD 0 ; Reserved + 128 00000104 00000000 DCD 0 ; Reserved + 129 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + 130 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + 131 00000110 00000000 DCD UART4_IRQHandler ; UART4 + 132 00000114 00000000 DCD UART5_IRQHandler ; UART5 + 133 00000118 00000000 DCD TIM6_IRQHandler ; TIM6 + 134 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 + 135 00000120 00000000 DCD DMA2_Channel1_IRQHandler + ; DMA2 Channel1 + 136 00000124 00000000 DCD DMA2_Channel2_IRQHandler + ; DMA2 Channel2 + 137 00000128 00000000 DCD DMA2_Channel3_IRQHandler + ; DMA2 Channel3 + 138 0000012C 00000000 DCD DMA2_Channel4_IRQHandler + ; DMA2 Channel4 + 139 00000130 00000000 DCD DMA2_Channel5_IRQHandler + ; DMA2 Channel5 + 140 00000134 00000000 DCD ETH_IRQHandler ; Ethernet + 141 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet + Wakeup through EXTI + line + 142 0000013C 00000000 DCD CAN2_TX_IRQHandler ; CAN2 TX + 143 00000140 00000000 DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + 144 00000144 00000000 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + 145 00000148 00000000 DCD CAN2_SCE_IRQHandler ; CAN2 SCE + 146 0000014C 00000000 DCD OTG_FS_IRQHandler ; USB OTG FS + 147 00000150 __Vectors_End + 148 00000150 + 149 00000150 00000150 + __Vectors_Size + EQU __Vectors_End - __Vectors + 150 00000150 + 151 00000150 AREA |.text|, CODE, READONLY + 152 00000000 + 153 00000000 ; Reset handler + 154 00000000 Reset_Handler + PROC + 155 00000000 EXPORT Reset_Handler [WEAK +] + 156 00000000 IMPORT SystemInit + 157 00000000 IMPORT __main + 158 00000000 4809 LDR R0, =SystemInit + 159 00000002 4780 BLX R0 + 160 00000004 4809 LDR R0, =__main + 161 00000006 4700 BX R0 + 162 00000008 ENDP + 163 00000008 + 164 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 165 00000008 + 166 00000008 NMI_Handler + + + +ARM Macro Assembler Page 5 + + + PROC + 167 00000008 EXPORT NMI_Handler [WEA +K] + 168 00000008 E7FE B . + 169 0000000A ENDP + 171 0000000A HardFault_Handler + PROC + 172 0000000A EXPORT HardFault_Handler [WEA +K] + 173 0000000A E7FE B . + 174 0000000C ENDP + 176 0000000C MemManage_Handler + PROC + 177 0000000C EXPORT MemManage_Handler [WEA +K] + 178 0000000C E7FE B . + 179 0000000E ENDP + 181 0000000E BusFault_Handler + PROC + 182 0000000E EXPORT BusFault_Handler [WEA +K] + 183 0000000E E7FE B . + 184 00000010 ENDP + 186 00000010 UsageFault_Handler + PROC + 187 00000010 EXPORT UsageFault_Handler [WEA +K] + 188 00000010 E7FE B . + 189 00000012 ENDP + 190 00000012 SVC_Handler + PROC + 191 00000012 EXPORT SVC_Handler [WEA +K] + 192 00000012 E7FE B . + 193 00000014 ENDP + 195 00000014 DebugMon_Handler + PROC + 196 00000014 EXPORT DebugMon_Handler [WEA +K] + 197 00000014 E7FE B . + 198 00000016 ENDP + 199 00000016 PendSV_Handler + PROC + 200 00000016 EXPORT PendSV_Handler [WEA +K] + 201 00000016 E7FE B . + 202 00000018 ENDP + 203 00000018 SysTick_Handler + PROC + 204 00000018 EXPORT SysTick_Handler [WEA +K] + 205 00000018 E7FE B . + 206 0000001A ENDP + 207 0000001A + 208 0000001A Default_Handler + PROC + 209 0000001A + 210 0000001A EXPORT WWDG_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 6 + + + 211 0000001A EXPORT PVD_IRQHandler [WEA +K] + 212 0000001A EXPORT TAMPER_IRQHandler [WEA +K] + 213 0000001A EXPORT RTC_IRQHandler [WEA +K] + 214 0000001A EXPORT FLASH_IRQHandler [WEA +K] + 215 0000001A EXPORT RCC_IRQHandler [WEA +K] + 216 0000001A EXPORT EXTI0_IRQHandler [WEA +K] + 217 0000001A EXPORT EXTI1_IRQHandler [WEA +K] + 218 0000001A EXPORT EXTI2_IRQHandler [WEA +K] + 219 0000001A EXPORT EXTI3_IRQHandler [WEA +K] + 220 0000001A EXPORT EXTI4_IRQHandler [WEA +K] + 221 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA +K] + 222 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA +K] + 223 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA +K] + 224 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA +K] + 225 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA +K] + 226 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA +K] + 227 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA +K] + 228 0000001A EXPORT ADC1_2_IRQHandler [WEA +K] + 229 0000001A EXPORT CAN1_TX_IRQHandler [WEA +K] + 230 0000001A EXPORT CAN1_RX0_IRQHandler [WEA +K] + 231 0000001A EXPORT CAN1_RX1_IRQHandler [WEA +K] + 232 0000001A EXPORT CAN1_SCE_IRQHandler [WEA +K] + 233 0000001A EXPORT EXTI9_5_IRQHandler [WEA +K] + 234 0000001A EXPORT TIM1_BRK_IRQHandler [WEA +K] + 235 0000001A EXPORT TIM1_UP_IRQHandler [WEA +K] + 236 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA +K] + 237 0000001A EXPORT TIM1_CC_IRQHandler [WEA +K] + 238 0000001A EXPORT TIM2_IRQHandler [WEA +K] + 239 0000001A EXPORT TIM3_IRQHandler [WEA +K] + 240 0000001A EXPORT TIM4_IRQHandler [WEA + + + +ARM Macro Assembler Page 7 + + +K] + 241 0000001A EXPORT I2C1_EV_IRQHandler [WEA +K] + 242 0000001A EXPORT I2C1_ER_IRQHandler [WEA +K] + 243 0000001A EXPORT I2C2_EV_IRQHandler [WEA +K] + 244 0000001A EXPORT I2C2_ER_IRQHandler [WEA +K] + 245 0000001A EXPORT SPI1_IRQHandler [WEA +K] + 246 0000001A EXPORT SPI2_IRQHandler [WEA +K] + 247 0000001A EXPORT USART1_IRQHandler [WEA +K] + 248 0000001A EXPORT USART2_IRQHandler [WEA +K] + 249 0000001A EXPORT USART3_IRQHandler [WEA +K] + 250 0000001A EXPORT EXTI15_10_IRQHandler [WEA +K] + 251 0000001A EXPORT RTCAlarm_IRQHandler [WEA +K] + 252 0000001A EXPORT OTG_FS_WKUP_IRQHandler [WEA +K] + 253 0000001A EXPORT TIM5_IRQHandler [WEA +K] + 254 0000001A EXPORT SPI3_IRQHandler [WEA +K] + 255 0000001A EXPORT UART4_IRQHandler [WEA +K] + 256 0000001A EXPORT UART5_IRQHandler [WEA +K] + 257 0000001A EXPORT TIM6_IRQHandler [WEA +K] + 258 0000001A EXPORT TIM7_IRQHandler [WEA +K] + 259 0000001A EXPORT DMA2_Channel1_IRQHandler [WEA +K] + 260 0000001A EXPORT DMA2_Channel2_IRQHandler [WEA +K] + 261 0000001A EXPORT DMA2_Channel3_IRQHandler [WEA +K] + 262 0000001A EXPORT DMA2_Channel4_IRQHandler [WEA +K] + 263 0000001A EXPORT DMA2_Channel5_IRQHandler [WEA +K] + 264 0000001A EXPORT ETH_IRQHandler [WEA +K] + 265 0000001A EXPORT ETH_WKUP_IRQHandler [WEA +K] + 266 0000001A EXPORT CAN2_TX_IRQHandler [WEA +K] + 267 0000001A EXPORT CAN2_RX0_IRQHandler [WEA +K] + 268 0000001A EXPORT CAN2_RX1_IRQHandler [WEA +K] + 269 0000001A EXPORT CAN2_SCE_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 8 + + + 270 0000001A EXPORT OTG_FS_IRQHandler [WEA +K] + 271 0000001A + 272 0000001A WWDG_IRQHandler + 273 0000001A PVD_IRQHandler + 274 0000001A TAMPER_IRQHandler + 275 0000001A RTC_IRQHandler + 276 0000001A FLASH_IRQHandler + 277 0000001A RCC_IRQHandler + 278 0000001A EXTI0_IRQHandler + 279 0000001A EXTI1_IRQHandler + 280 0000001A EXTI2_IRQHandler + 281 0000001A EXTI3_IRQHandler + 282 0000001A EXTI4_IRQHandler + 283 0000001A DMA1_Channel1_IRQHandler + 284 0000001A DMA1_Channel2_IRQHandler + 285 0000001A DMA1_Channel3_IRQHandler + 286 0000001A DMA1_Channel4_IRQHandler + 287 0000001A DMA1_Channel5_IRQHandler + 288 0000001A DMA1_Channel6_IRQHandler + 289 0000001A DMA1_Channel7_IRQHandler + 290 0000001A ADC1_2_IRQHandler + 291 0000001A CAN1_TX_IRQHandler + 292 0000001A CAN1_RX0_IRQHandler + 293 0000001A CAN1_RX1_IRQHandler + 294 0000001A CAN1_SCE_IRQHandler + 295 0000001A EXTI9_5_IRQHandler + 296 0000001A TIM1_BRK_IRQHandler + 297 0000001A TIM1_UP_IRQHandler + 298 0000001A TIM1_TRG_COM_IRQHandler + 299 0000001A TIM1_CC_IRQHandler + 300 0000001A TIM2_IRQHandler + 301 0000001A TIM3_IRQHandler + 302 0000001A TIM4_IRQHandler + 303 0000001A I2C1_EV_IRQHandler + 304 0000001A I2C1_ER_IRQHandler + 305 0000001A I2C2_EV_IRQHandler + 306 0000001A I2C2_ER_IRQHandler + 307 0000001A SPI1_IRQHandler + 308 0000001A SPI2_IRQHandler + 309 0000001A USART1_IRQHandler + 310 0000001A USART2_IRQHandler + 311 0000001A USART3_IRQHandler + 312 0000001A EXTI15_10_IRQHandler + 313 0000001A RTCAlarm_IRQHandler + 314 0000001A OTG_FS_WKUP_IRQHandler + 315 0000001A TIM5_IRQHandler + 316 0000001A SPI3_IRQHandler + 317 0000001A UART4_IRQHandler + 318 0000001A UART5_IRQHandler + 319 0000001A TIM6_IRQHandler + 320 0000001A TIM7_IRQHandler + 321 0000001A DMA2_Channel1_IRQHandler + 322 0000001A DMA2_Channel2_IRQHandler + 323 0000001A DMA2_Channel3_IRQHandler + 324 0000001A DMA2_Channel4_IRQHandler + 325 0000001A DMA2_Channel5_IRQHandler + 326 0000001A ETH_IRQHandler + 327 0000001A ETH_WKUP_IRQHandler + + + +ARM Macro Assembler Page 9 + + + 328 0000001A CAN2_TX_IRQHandler + 329 0000001A CAN2_RX0_IRQHandler + 330 0000001A CAN2_RX1_IRQHandler + 331 0000001A CAN2_SCE_IRQHandler + 332 0000001A OTG_FS_IRQHandler + 333 0000001A + 334 0000001A E7FE B . + 335 0000001C + 336 0000001C ENDP + 337 0000001C + 338 0000001C ALIGN + 339 0000001C + 340 0000001C ;******************************************************* + ************************ + 341 0000001C ; User Stack and Heap initialization + 342 0000001C ;******************************************************* + ************************ + 343 0000001C IF :DEF:__MICROLIB + 350 0000001C + 351 0000001C IMPORT __use_two_region_memory + 352 0000001C EXPORT __user_initial_stackheap + 353 0000001C + 354 0000001C __user_initial_stackheap + 355 0000001C + 356 0000001C 4804 LDR R0, = Heap_Mem + 357 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size) + 358 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 359 00000022 4B06 LDR R3, = Stack_Mem + 360 00000024 4770 BX LR + 361 00000026 + 362 00000026 00 00 ALIGN + 363 00000028 + 364 00000028 ENDIF + 365 00000028 + 366 00000028 END + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\objects\startup_stm32f10x_cl.d -o.\objects\startup_stm32f10x_cl. +o -I.\RTE\Device\STM32F107VC -I.\RTE\_Target_1 -IE:\Keil_v5\ARM\PACK\Keil\STM32 +F1xx_DFP\2.3.0\Device\Include -IE:\Keil_v5\ARM\CMSIS\Include --predefine="__EVA +L SETA 1" --predefine="__UVISION_VERSION SETA 526" --predefine="_RTE_ SETA 1" - +-predefine="STM32F10X_CL SETA 1" --list=.\listings\startup_stm32f10x_cl.lst RTE +\Device\STM32F107VC\startup_stm32f10x_cl.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 36 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 357 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 359 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 37 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 61 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 46 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 48 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 356 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 358 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 47 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 49 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 56 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 61 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 57 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 149 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +__Vectors_End 00000150 + +Symbol: __Vectors_End + Definitions + At line 147 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 58 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 149 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 151 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: .text unused +ADC1_2_IRQHandler 0000001A + +Symbol: ADC1_2_IRQHandler + Definitions + At line 290 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 97 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 228 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 181 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 66 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 182 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN1_RX0_IRQHandler 0000001A + +Symbol: CAN1_RX0_IRQHandler + Definitions + At line 292 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 99 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 230 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 293 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 100 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 231 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 294 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 101 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 232 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN1_TX_IRQHandler 0000001A + +Symbol: CAN1_TX_IRQHandler + Definitions + At line 291 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 98 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 229 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN2_RX0_IRQHandler 0000001A + +Symbol: CAN2_RX0_IRQHandler + Definitions + At line 329 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 143 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 267 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN2_RX1_IRQHandler 0000001A + +Symbol: CAN2_RX1_IRQHandler + Definitions + At line 330 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 144 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 268 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN2_SCE_IRQHandler 0000001A + +Symbol: CAN2_SCE_IRQHandler + Definitions + At line 331 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 145 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 269 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +CAN2_TX_IRQHandler 0000001A + +Symbol: CAN2_TX_IRQHandler + Definitions + At line 328 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 142 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 266 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 283 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 90 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 221 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 284 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 91 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 222 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel3_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 285 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 92 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 223 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 286 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 93 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 224 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel5_IRQHandler 0000001A + +Symbol: DMA1_Channel5_IRQHandler + Definitions + At line 287 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 94 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 225 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel6_IRQHandler 0000001A + +Symbol: DMA1_Channel6_IRQHandler + Definitions + At line 288 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 95 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 226 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA1_Channel7_IRQHandler 0000001A + +Symbol: DMA1_Channel7_IRQHandler + Definitions + At line 289 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 96 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 227 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA2_Channel1_IRQHandler 0000001A + +Symbol: DMA2_Channel1_IRQHandler + Definitions + At line 321 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 135 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 259 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA2_Channel2_IRQHandler 0000001A + +Symbol: DMA2_Channel2_IRQHandler + Definitions + At line 322 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 136 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + At line 260 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA2_Channel3_IRQHandler 0000001A + +Symbol: DMA2_Channel3_IRQHandler + Definitions + At line 323 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 137 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 261 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA2_Channel4_IRQHandler 0000001A + +Symbol: DMA2_Channel4_IRQHandler + Definitions + At line 324 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 138 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 262 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DMA2_Channel5_IRQHandler 0000001A + +Symbol: DMA2_Channel5_IRQHandler + Definitions + At line 325 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 139 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 263 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 195 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 73 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 196 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 208 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: Default_Handler unused +ETH_IRQHandler 0000001A + +Symbol: ETH_IRQHandler + Definitions + At line 326 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 140 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 264 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +ETH_WKUP_IRQHandler 0000001A + +Symbol: ETH_WKUP_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 327 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 141 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 265 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 278 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 85 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 216 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 312 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 119 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 250 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 279 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 86 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 217 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 280 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 87 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 218 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 281 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 88 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 219 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 282 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 89 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 220 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 295 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 102 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 233 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + At line 276 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 83 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 214 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 171 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 64 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 172 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 304 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 111 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 242 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 303 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 110 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 241 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 306 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 113 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 244 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 305 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 112 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 243 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 176 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 65 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 177 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 166 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 63 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 167 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +OTG_FS_IRQHandler 0000001A + +Symbol: OTG_FS_IRQHandler + Definitions + At line 332 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 146 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 270 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +OTG_FS_WKUP_IRQHandler 0000001A + +Symbol: OTG_FS_WKUP_IRQHandler + Definitions + At line 314 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 121 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 252 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 273 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 80 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 211 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 199 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 75 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 200 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +RCC_IRQHandler 0000001A + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: RCC_IRQHandler + Definitions + At line 277 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 84 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 215 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +RTCAlarm_IRQHandler 0000001A + +Symbol: RTCAlarm_IRQHandler + Definitions + At line 313 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 120 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 251 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 275 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 82 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 213 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 154 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 62 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 155 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 307 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 114 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 245 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 308 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 115 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 246 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +SPI3_IRQHandler 0000001A + +Symbol: SPI3_IRQHandler + Definitions + At line 316 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 130 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 254 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 190 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 72 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 191 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 203 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 76 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 204 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 274 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 81 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 212 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM1_BRK_IRQHandler 0000001A + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 296 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 103 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 234 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 299 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 106 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 237 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM1_TRG_COM_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 298 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 105 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 236 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM1_UP_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 297 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 104 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 235 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 300 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 107 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 238 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 301 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 108 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 239 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM4_IRQHandler 0000001A + +Symbol: TIM4_IRQHandler + Definitions + At line 302 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 109 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 240 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM5_IRQHandler 0000001A + +Symbol: TIM5_IRQHandler + Definitions + At line 315 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 129 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 253 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM6_IRQHandler 0000001A + +Symbol: TIM6_IRQHandler + Definitions + At line 319 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 133 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 257 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +TIM7_IRQHandler 0000001A + +Symbol: TIM7_IRQHandler + Definitions + At line 320 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 134 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 258 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 317 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 131 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 255 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +UART5_IRQHandler 0000001A + +Symbol: UART5_IRQHandler + Definitions + At line 318 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 132 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 256 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 309 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 116 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 247 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 310 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 117 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 248 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 311 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 118 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 249 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 186 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 67 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 187 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 272 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 79 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 210 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +__user_initial_stackheap 0000001C + +Symbol: __user_initial_stackheap + Definitions + At line 354 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 352 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s +Comment: __user_initial_stackheap used once +74 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 44 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 48 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 358 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 33 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 36 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + At line 357 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + +__Vectors_Size 00000150 + +Symbol: __Vectors_Size + Definitions + At line 149 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 59 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 156 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 158 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 157 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + At line 160 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 351 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +428 symbols in table diff --git a/GreatCommonDivisor/C/Objects/Project.build_log.htm b/GreatCommonDivisor/C/Objects/Project.build_log.htm new file mode 100644 index 0000000..61d36e5 --- /dev/null +++ b/GreatCommonDivisor/C/Objects/Project.build_log.htm @@ -0,0 +1,65 @@ + + +