/* @generated */
digraph iCFG {
"foo.acbd18db4cc2f85cedef654fccc4a4d8_1" [label="1: Start foo\nFormals: \nLocals:  0$?%__sil_tmpSIL_temp_conditional___n$0:int 0$?%__sil_tmpSIL_temp_conditional___n$2:int 0$?%__sil_tmpSIL_temp_conditional___n$3:int n:int 0$?%__sil_tmpSIL_temp_conditional___n$6:int y:int x:int \n   DECLARE_LOCALS(&return,&0$?%__sil_tmpSIL_temp_conditional___n$0,&0$?%__sil_tmpSIL_temp_conditional___n$2,&0$?%__sil_tmpSIL_temp_conditional___n$3,&n,&0$?%__sil_tmpSIL_temp_conditional___n$6,&y,&x); [line 10]\n " color=yellow style=filled]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_1" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_37" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_2" [label="2: Exit foo \n  " color=yellow style=filled]
	

"foo.acbd18db4cc2f85cedef654fccc4a4d8_3" [label="3: + \n  " ]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_3" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_8" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_4" [label="4: Prune (true branch) \n   PRUNE(((7 > 9) != 0), true); [line 18]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_4" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_6" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_5" [label="5: Prune (false branch) \n   PRUNE(((7 > 9) == 0), false); [line 18]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_5" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_7" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_6" [label="6:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$0:int=1 [line 18]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_6" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_3" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_7" [label="7:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$0:int=0 [line 18]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_7" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_3" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_8" [label="8:  Return Stmt \n   n$1=*&0$?%__sil_tmpSIL_temp_conditional___n$0:int [line 18]\n  *&return:int=(0 + n$1) [line 18]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_8" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_2" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_9" [label="9: + \n  " ]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_9" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_19" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_10" [label="10: Prune (true branch) \n   PRUNE(((2 < 1) != 0), true); [line 17]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_10" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_12" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_11" [label="11: Prune (false branch) \n   PRUNE(((2 < 1) == 0), false); [line 17]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_11" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_14" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_11" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_15" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_12" [label="12:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$2:int=1 [line 17]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_12" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_9" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_13" [label="13: + \n  " ]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_13" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_18" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_14" [label="14: Prune (true branch) \n   PRUNE(((5 > 4) != 0), true); [line 17]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_14" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_16" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_15" [label="15: Prune (false branch) \n   PRUNE(((5 > 4) == 0), false); [line 17]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_15" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_17" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_16" [label="16:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$3:int=1 [line 17]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_16" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_13" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_17" [label="17:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$3:int=2 [line 17]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_17" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_13" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_18" [label="18:  ConditinalStmt Branch \n   n$4=*&0$?%__sil_tmpSIL_temp_conditional___n$3:int [line 17]\n  *&0$?%__sil_tmpSIL_temp_conditional___n$2:int=n$4 [line 17]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_18" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_9" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_19" [label="19:  BinaryOperatorStmt: Assign \n   n$5=*&0$?%__sil_tmpSIL_temp_conditional___n$2:int [line 17]\n  *&n:int=n$5 [line 17]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_19" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_4" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_19" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_5" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_20" [label="20: + \n  " ]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_20" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_28" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_21" [label="21: Prune (true branch) \n   PRUNE(((3 < 4) != 0), true); [line 16]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_21" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_26" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_22" [label="22: Prune (false branch) \n   PRUNE(((3 < 4) == 0), false); [line 16]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_22" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_23" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_23" [label="23:  BinaryOperatorStmt: LT \n   n$7=*&x:int [line 16]\n  *&x:int=(n$7 + 1) [line 16]\n  n$8=*&y:int [line 16]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_23" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_24" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_23" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_25" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_24" [label="24: Prune (true branch) \n   PRUNE(((7 < (n$7 - n$8)) != 0), true); [line 16]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_24" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_26" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_25" [label="25: Prune (false branch) \n   PRUNE(((7 < (n$7 - n$8)) == 0), false); [line 16]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_25" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_27" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_26" [label="26:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$6:int=1 [line 16]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_26" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_20" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_27" [label="27:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$6:int=2 [line 16]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_27" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_20" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_28" [label="28:  DeclStmt \n   n$9=*&0$?%__sil_tmpSIL_temp_conditional___n$6:int [line 16]\n  *&n:int=n$9 [line 16]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_28" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_10" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_28" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_11" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_29" [label="29:  DeclStmt \n   *&y:int=19 [line 15]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_29" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_21" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_29" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_22" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_30" [label="30: + \n  " ]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_30" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_29" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_31" [label="31: Prune (true branch) \n   PRUNE(((3 < 4) != 0), true); [line 12]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_31" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_36" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_32" [label="32: Prune (false branch) \n   PRUNE(((3 < 4) == 0), false); [line 12]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_32" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_33" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_33" [label="33:  BinaryOperatorStmt: LT \n   n$10=*&x:int [line 12]\n  *&x:int=(n$10 + 1) [line 12]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_33" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_34" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_33" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_35" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_34" [label="34: Prune (true branch) \n   PRUNE(((7 < n$10) != 0), true); [line 12]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_34" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_36" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_35" [label="35: Prune (false branch) \n   PRUNE(((7 < n$10) == 0), false); [line 12]\n " shape="invhouse"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_35" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_30" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_36" [label="36:  BinaryOperatorStmt: Assign \n   *&x:int=0 [line 13]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_36" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_30" ;
"foo.acbd18db4cc2f85cedef654fccc4a4d8_37" [label="37:  DeclStmt \n   *&x:int=5 [line 11]\n " shape="box"]
	

	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_37" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_31" ;
	 "foo.acbd18db4cc2f85cedef654fccc4a4d8_37" -> "foo.acbd18db4cc2f85cedef654fccc4a4d8_32" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_1" [label="1: Start bar\nFormals: \nLocals:  0$?%__sil_tmpSIL_temp_conditional___n$0:int 0$?%__sil_tmpSIL_temp_conditional___n$1:int 0$?%__sil_tmpSIL_temp_conditional___n$5:int y:int x:int \n   DECLARE_LOCALS(&return,&0$?%__sil_tmpSIL_temp_conditional___n$0,&0$?%__sil_tmpSIL_temp_conditional___n$1,&0$?%__sil_tmpSIL_temp_conditional___n$5,&y,&x); [line 21]\n " color=yellow style=filled]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_1" -> "bar.37b51d194a7513e45b56f6524f2d51f2_16" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_2" [label="2: Exit bar \n  " color=yellow style=filled]
	

"bar.37b51d194a7513e45b56f6524f2d51f2_3" [label="3: + \n  " ]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_3" -> "bar.37b51d194a7513e45b56f6524f2d51f2_14" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_4" [label="4: + \n  " ]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_4" -> "bar.37b51d194a7513e45b56f6524f2d51f2_9" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_5" [label="5: Prune (true branch) \n   PRUNE(((3 > 4) != 0), true); [line 24]\n " shape="invhouse"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_5" -> "bar.37b51d194a7513e45b56f6524f2d51f2_7" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_6" [label="6: Prune (false branch) \n   PRUNE(((3 > 4) == 0), false); [line 24]\n " shape="invhouse"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_6" -> "bar.37b51d194a7513e45b56f6524f2d51f2_8" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_7" [label="7:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$1:int=1 [line 24]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_7" -> "bar.37b51d194a7513e45b56f6524f2d51f2_4" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_8" [label="8:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$1:int=2 [line 24]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_8" -> "bar.37b51d194a7513e45b56f6524f2d51f2_4" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_9" [label="9:  BinaryOperatorStmt: GT \n   n$2=*&0$?%__sil_tmpSIL_temp_conditional___n$1:int [line 24]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_9" -> "bar.37b51d194a7513e45b56f6524f2d51f2_10" ;
	 "bar.37b51d194a7513e45b56f6524f2d51f2_9" -> "bar.37b51d194a7513e45b56f6524f2d51f2_11" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_10" [label="10: Prune (true branch) \n   PRUNE(((n$2 > 1) != 0), true); [line 24]\n " shape="invhouse"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_10" -> "bar.37b51d194a7513e45b56f6524f2d51f2_12" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_11" [label="11: Prune (false branch) \n   PRUNE(((n$2 > 1) == 0), false); [line 24]\n " shape="invhouse"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_11" -> "bar.37b51d194a7513e45b56f6524f2d51f2_13" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_12" [label="12:  ConditinalStmt Branch \n   *&x:int=1 [line 24]\n  n$3=*&x:int [line 24]\n  *&0$?%__sil_tmpSIL_temp_conditional___n$0:int=n$3 [line 24]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_12" -> "bar.37b51d194a7513e45b56f6524f2d51f2_3" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_13" [label="13:  ConditinalStmt Branch \n   *&0$?%__sil_tmpSIL_temp_conditional___n$0:int=0 [line 24]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_13" -> "bar.37b51d194a7513e45b56f6524f2d51f2_3" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_14" [label="14:  Return Stmt \n   n$4=*&0$?%__sil_tmpSIL_temp_conditional___n$0:int [line 24]\n  *&return:int=(0 + n$4) [line 24]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_14" -> "bar.37b51d194a7513e45b56f6524f2d51f2_2" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_15" [label="15: + \n  " ]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_15" -> "bar.37b51d194a7513e45b56f6524f2d51f2_21" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_16" [label="16:  BinaryOperatorStmt: GT \n   *&x:int=1 [line 23]\n  n$6=*&x:int [line 23]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_16" -> "bar.37b51d194a7513e45b56f6524f2d51f2_17" ;
	 "bar.37b51d194a7513e45b56f6524f2d51f2_16" -> "bar.37b51d194a7513e45b56f6524f2d51f2_18" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_17" [label="17: Prune (true branch) \n   PRUNE(((n$6 > 1) != 0), true); [line 23]\n " shape="invhouse"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_17" -> "bar.37b51d194a7513e45b56f6524f2d51f2_19" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_18" [label="18: Prune (false branch) \n   PRUNE(((n$6 > 1) == 0), false); [line 23]\n " shape="invhouse"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_18" -> "bar.37b51d194a7513e45b56f6524f2d51f2_20" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_19" [label="19:  ConditinalStmt Branch \n   n$7=*&x:int [line 23]\n  *&x:int=(n$7 + 1) [line 23]\n  *&0$?%__sil_tmpSIL_temp_conditional___n$5:int=(n$7 + 1) [line 23]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_19" -> "bar.37b51d194a7513e45b56f6524f2d51f2_15" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_20" [label="20:  ConditinalStmt Branch \n   n$8=*&x:int [line 23]\n  *&x:int=(n$8 - 1) [line 23]\n  *&0$?%__sil_tmpSIL_temp_conditional___n$5:int=n$8 [line 23]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_20" -> "bar.37b51d194a7513e45b56f6524f2d51f2_15" ;
"bar.37b51d194a7513e45b56f6524f2d51f2_21" [label="21:  BinaryOperatorStmt: Assign \n   n$9=*&0$?%__sil_tmpSIL_temp_conditional___n$5:int [line 23]\n  *&y:int=n$9 [line 23]\n " shape="box"]
	

	 "bar.37b51d194a7513e45b56f6524f2d51f2_21" -> "bar.37b51d194a7513e45b56f6524f2d51f2_5" ;
	 "bar.37b51d194a7513e45b56f6524f2d51f2_21" -> "bar.37b51d194a7513e45b56f6524f2d51f2_6" ;
}
