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(*
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* Copyright (c) 2017 - present Facebook, Inc.
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* All rights reserved.
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*
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* This source code is licensed under the BSD style license found in the
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* LICENSE file in the root directory of this source tree. An additional grant
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* of patent rights can be found in the PATENTS file in the same directory.
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*)
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open! IStd
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module L = Logging
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module type HilConfig = sig
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val include_array_indexes : bool
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end
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module DefaultConfig : HilConfig = struct
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let include_array_indexes = false
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end
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module Make
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(MakeTransferFunctions : TransferFunctions.MakeHIL)
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(HilConfig : HilConfig)
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(CFG : ProcCfg.S) =
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struct
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module TransferFunctions = MakeTransferFunctions (CFG)
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module CFG = TransferFunctions.CFG
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module Domain = AbstractDomain.Pair (TransferFunctions.Domain) (IdAccessPathMapDomain)
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type extras = TransferFunctions.extras
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let pp_session_name = TransferFunctions.pp_session_name
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let pp_pre_post pre post hil_instr node =
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if Config.write_html then (
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let underyling_node = CFG.underlying_node node in
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NodePrinter.start_session ~pp_name:(pp_session_name node) underyling_node ;
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L.d_strln
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(Format.asprintf "PRE: %a@.INSTR: %a@.POST: %a@." TransferFunctions.Domain.pp pre
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HilInstr.pp hil_instr TransferFunctions.Domain.pp post) ;
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NodePrinter.finish_session underyling_node )
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let is_java_unlock pname actuals =
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(* would check is_java, but we want to include builtins too *)
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not (Typ.Procname.is_c_method pname)
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&& match RacerDConfig.Models.get_lock pname actuals with Unlock -> true | _ -> false
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let exec_instr ((actual_state, id_map) as astate) extras node instr =
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let f_resolve_id id = IdAccessPathMapDomain.find_opt id id_map in
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match
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HilInstr.of_sil ~include_array_indexes:HilConfig.include_array_indexes ~f_resolve_id instr
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with
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| Bind (id, access_path) ->
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let id_map' = IdAccessPathMapDomain.add id access_path id_map in
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if phys_equal id_map id_map' then astate else (actual_state, id_map')
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| Unbind ids ->
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let id_map' =
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List.fold ~f:(fun acc id -> IdAccessPathMapDomain.remove id acc) ~init:id_map ids
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in
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if phys_equal id_map id_map' then astate else (actual_state, id_map')
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| Instr (Call (_, Direct callee_pname, actuals, _, loc) as hil_instr)
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when is_java_unlock callee_pname actuals ->
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(* need to be careful not to move reads/writes out of a critical section due to odd
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temporaries introduced in our translation of try/synchronized in Java. to ensure this,
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"dump" all of the temporaries out of the id map, then execute the unlock instruction. *)
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let actual_state' =
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IdAccessPathMapDomain.fold
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(fun id access_expr astate_acc ->
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let lhs_access_path = AccessExpression.Base (id, Typ.mk Typ.Tvoid) in
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let dummy_assign =
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HilInstr.Assign (lhs_access_path, HilExp.AccessExpression access_expr, loc)
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in
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TransferFunctions.exec_instr astate_acc extras node dummy_assign )
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id_map actual_state
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in
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let actual_state'' = TransferFunctions.exec_instr actual_state' extras node hil_instr in
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pp_pre_post actual_state actual_state'' hil_instr node ;
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(actual_state'', IdAccessPathMapDomain.empty)
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| Instr hil_instr ->
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let actual_state' = TransferFunctions.exec_instr actual_state extras node hil_instr in
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pp_pre_post actual_state actual_state' hil_instr node ;
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if phys_equal actual_state actual_state' then astate else (actual_state', id_map)
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| Ignore ->
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astate
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end
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module MakeAbstractInterpreterWithConfig
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(HilConfig : HilConfig)
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(CFG : ProcCfg.S)
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(MakeTransferFunctions : TransferFunctions.MakeHIL) =
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struct
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module Interpreter = AbstractInterpreter.Make (CFG) (Make (MakeTransferFunctions) (HilConfig))
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let compute_post ({ProcData.pdesc; tenv} as proc_data) ~initial =
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Preanal.do_preanalysis pdesc tenv ;
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let initial' = (initial, IdAccessPathMapDomain.empty) in
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Option.map ~f:fst (Interpreter.compute_post ~debug:false proc_data ~initial:initial')
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end
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module MakeAbstractInterpreter = MakeAbstractInterpreterWithConfig (DefaultConfig)
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