Labels Milestones

初始文件同步 #1

Merged

pl5g92irw merged 3 commits from ready into master 3 years ago

Conversation 0 Commits 3 Files Changed 3

pl5g92irw commented 3 years ago

Owner

将源项目的所有初始文件提交到主分支

将源项目的所有初始文件提交到主分支

pl5g92irw added 3 commits 3 years ago

3240e076ea Python描述的神经网络模型

267521f871 以Verilog语言实现FPGA神经网络

48bebc411a FPGA神经网络所重复调动的函数模块，Verilog语言

pl5g92irw referenced this issue from a commit 3 years ago

Merge pull request '初始文件同步' (#1) from ready into master

pl5g92irw merged commit db09feff98 into master 3 years ago

The pull request has been merged as db09feff98.

Sign in to join this conversation.

Reviewers

Request review

No reviewers

Labels

Apply labels

Clear labels

No items

No Label

Milestone

Set milestone

Clear milestone

No items

No Milestone

Assignees

Assign users

Clear assignees

No Assignees

1 Participants

Notifications

Subscribe

Due Date

The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: pl5g92irw/NN2FPGA#1

Write Preview

Loading…

Cancel

Save

There is no content yet.