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# -*- coding: utf-8 -*-
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import sys
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LD = "L.D" # exe steps: 2
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SD = "S.D" # 1
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ADDD = "ADD.D" # 2
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SUBD = "SUB.D" # 2
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MULD = "MUL.D" # 10
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DIVD = "DIV.D" # 40
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class Tomasulo:
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def __init__(self, insts, adder_num, multiplier_num, load_buffer_num,
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store_buffer_num, float_reg_num, int_reg_num, mem_size):
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i = 0
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for inst in insts:
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inst_ = ""
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for term in inst.split(" "):
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inst_ = inst_ + term.split(",")[0] + " "
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insts[i] = inst_.split("\n")[0]
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i += 1
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self.instruction_status = [
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instruction_status(insts[i], i) for i in range(len(insts))
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]
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self.reservation_station = reservation_station(adder_num,
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multiplier_num)
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self.load_buffers = [load_buffer(i) for i in range(load_buffer_num)]
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self.store_buffers = [store_buffer(i) for i in range(store_buffer_num)]
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self.register_result_status = register_result_status(
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float_reg_num, int_reg_num)
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self.mem = [mem(i) for i in range(mem_size)]
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self.clock = 1
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def lbIsFull(self):
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for lb in self.load_buffers:
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if lb.busy == False: return lb.index # return free buffer's index
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return "True" # indicate Full by returning "True"
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def sbIsFull(self):
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for sb in self.store_buffers:
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if sb.busy == False: return sb.index # return free buffer's index
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return "True" # indicate Full by returning "True"
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def print(self):
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print("Cycle " + str(self.clock) + ":")
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print("\nInstruction Status: ")
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print("\t\t\t\t\t\t%s\t%s %s" %
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("Issue", "Complete", "Write_Result"))
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for IS in self.instruction_status:
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IS.print()
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self.reservation_station.print()
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print("-\n")
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# print("Load/Store Buffer:")
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# print("\t\t\tBusy\tAddress\t\tFu")
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# for lb in self.load_buffers:
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# lb.print()
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# for sb in self.store_buffers:
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# sb.print()
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# print("-\n")
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self.register_result_status.print()
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# print("Memory: \n")
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# mem_name = "\t\t "
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# mem_value = "\t\tValue: "
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# for mem in self.mem:
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# if int(mem.name.split("_")[-1]) % 8 == 0:
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# mem_name += ("\tMem_" +
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# str(int(int(mem.name.split("_")[-1]) / 8) + 1))
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# mem_value += ("\t" + str(mem.value))
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# print(mem_name + "\n")
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# print(mem_value)
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# print("-\n")
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def isFinished(self): # check whether the insts are finished
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for IS in self.instruction_status:
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if IS.write == -1: return False
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return True
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def writeResult(self):
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for RS in self.reservation_station.adders:
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self.broadcast(RS)
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for RS in self.reservation_station.multipliers:
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self.broadcast(RS)
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for RS in self.load_buffers:
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self.broadcast(RS)
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for RS in self.store_buffers:
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if RS.busy == True and RS.time == 0:
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if RS.qk != "null":
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if RS.qk.split("_")[0] == "Add":
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fus = self.reservation_station.adders
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elif RS.qk.split("_")[0] == "Mult":
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fus = self.reservation_station.multipliers
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for fu in fus: # store buffer所等待的function unit(reservation station)
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if RS.qk == fu.name and self.clock == self.instruction_status[
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fu.inst_index].write + 1:
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self.mem[RS.address].value = fu.result
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RS.last_time_write = self.clock # 记录instruction最近一次的write_result时间
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self.instruction_status[
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RS.inst_index].write = self.clock
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fu.result = -1 # reset the result
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RS.reset()
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# 对沒有dependence的修改vk
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elif RS.qk == "null": # source register(rt) 未占用
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self.mem[RS.address].value = RS.vk
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self.vk_broadcasted_cycle = self.clock
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RS.last_time_write = self.clock # 记录instruction的write_result时间
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self.instruction_status[RS.inst_index].write = self.clock
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RS.reset()
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def broadcast(self, RS):
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if RS.busy == True and RS.time == 0:
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RS.last_time_write = self.clock
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self.instruction_status[
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RS.inst_index].write = self.clock # write result
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# broadcast to all awaiting reservation stations
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for reg in self.register_result_status.float_regs:
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if reg.qi != "null" and reg.qi == RS.name:
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reg.value = RS.result
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reg.qi = "null"
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for RSs in self.reservation_station.adders: # search for matched Qj or Qk
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if RSs.busy == True and RSs.qj == RS.name:
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RSs.vj = RS.result
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RSs.vj_broadcasted_cycle = self.clock
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RSs.qj = "null"
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if RSs.busy == True and RSs.qk == RS.name:
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RSs.vk = RS.result
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RSs.vk_broadcasted_cycle = self.clock
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RSs.qk = "null"
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for RSs in self.reservation_station.multipliers: # search for matched Qj or Qk
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if RSs.busy == True and RSs.qj == RS.name:
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RSs.vj = RS.result
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RSs.vj_broadcasted_cycle = self.clock
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RSs.qj = "null"
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if RSs.busy == True and RSs.qk == RS.name:
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RSs.vk = RS.result
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RSs.vk_broadcasted_cycle = self.clock
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RSs.qk = "null"
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for RSs in self.load_buffers: # search for matched Qj
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if RSs.busy == True and RSs.qj == RS.name:
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RSs.vj = RS.result
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RSs.vj_broadcasted_cycle = self.clock
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RSs.qj = "null"
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RS.reset()
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def execute(self):
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for RS in self.reservation_station.adders:
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if RS.busy == True and RS.vj != "null" and RS.vk != "null" and RS.qj == "null" and RS.qk == "null":
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if RS.vj_broadcasted_cycle == self.clock or RS.vk_broadcasted_cycle == self.clock:
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continue
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else:
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RS.time = RS.time - 1
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if RS.time == 0:
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if RS.op == ADDD: RS.result = RS.vj + RS.vk
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elif RS.op == SUBD: RS.result = RS.vj - RS.vk
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self.instruction_status[
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RS.inst_index].complete = self.clock
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for RS in self.reservation_station.multipliers:
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if RS.busy == True and RS.vj != "null" and RS.vk != "null" and RS.qj == "null" and RS.qk == "null":
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if RS.vj_broadcasted_cycle == self.clock or RS.vk_broadcasted_cycle == self.clock:
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continue
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else:
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RS.time = RS.time - 1
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if RS.time == 0:
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if RS.op == MULD: RS.result = RS.vj * RS.vk
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elif RS.op == DIVD: RS.result = RS.vj / RS.vk
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self.instruction_status[
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RS.inst_index].complete = self.clock
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for RS in self.load_buffers:
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if RS.busy == True and RS.vj != "null" and RS.qj == "null":
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if RS.vj_broadcasted_cycle == self.clock:
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continue
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else:
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RS.time = RS.time - 1
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if RS.time == 1:
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RS.address = RS.address + RS.vj
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elif RS.time == 0:
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RS.result = self.mem[RS.address].value
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self.instruction_status[
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RS.inst_index].complete = self.clock
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for RS in self.store_buffers:
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#if RS.busy == True and RS.vk != "null" and RS.qk == "null":
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#if RS.busy == True and RS.vk != "null":
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if RS.busy == True:
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#if RS.vk_broadcasted_cycle == self.clock: continue
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#else:
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if RS.time != 0:
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RS.time = RS.time - 1
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if RS.time == 0:
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RS.address = RS.address + RS.vj
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self.instruction_status[
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RS.inst_index].complete = self.clock
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def issue(self):
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for inst in self.instruction_status:
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if inst.issue == -1: # only issue the unissued instructions
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if inst.name == LD:
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index = self.lbIsFull() # index 为 free load_buffer's index
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if index != "True" and self.load_buffers[
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index].last_time_write != self.clock:
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self.load_buffers[index].time = 2
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inst.issue = self.clock
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self.load_buffers[index].inst_index = inst.index
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# load or store
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if self.register_result_status.int_regs[
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inst.rsIndex].qi != "null":
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self.load_buffers[
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index].qj = self.register_result_status.int_regs[
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inst.rsIndex].qi
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else:
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self.load_buffers[
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index].vj = self.register_result_status.int_regs[
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inst.rsIndex].value # base address
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self.load_buffers[index].qj = "null"
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self.load_buffers[
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index].address = inst.offset # save offset(immd. value) to address
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self.load_buffers[index].busy = True
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# load only
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self.register_result_status.float_regs[
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inst.rtIndex].qi = self.load_buffers[index].name
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elif inst.name == SD:
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index = self.sbIsFull()
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if index != "True" and self.store_buffers[
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index].last_time_write != self.clock:
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inst.issue = self.clock
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self.store_buffers[index].time = 1
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self.store_buffers[index].inst_index = inst.index
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# load or store
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if self.register_result_status.int_regs[
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inst.rsIndex].qi != "null":
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self.store_buffers[
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index].qj = self.register_result_status.int_regs[
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inst.rsIndex].qi
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else:
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self.store_buffers[
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index].vj = self.register_result_status.int_regs[
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inst.rsIndex].value # base address
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self.store_buffers[index].qj = "null"
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self.store_buffers[
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index].address = inst.offset # save offset(immd. value) to address
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self.store_buffers[index].busy = True
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# store only
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if self.register_result_status.float_regs[
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inst.rtIndex].qi != "null":
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self.store_buffers[
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index].qk = self.register_result_status.float_regs[
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inst.rtIndex].qi
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else:
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self.store_buffers[
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index].vk = self.register_result_status.float_regs[
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inst.rtIndex].value # source register (rt)
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self.store_buffers[index].qk = "null"
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elif inst.name == ADDD or inst.name == SUBD or inst.name == MULD or inst.name == DIVD:
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if inst.name == ADDD or inst.name == SUBD:
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index = self.reservation_station.isFull(
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self.reservation_station.adders)
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if index != "True" and self.reservation_station.adders[
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index].last_time_write != self.clock:
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inst.issue = self.clock
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self.reservation_station.adders[
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index].inst_index = inst.index
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if inst.name == ADDD:
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self.reservation_station.adders[
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index].op = ADDD
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elif inst.name == SUBD:
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self.reservation_station.adders[
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index].op = SUBD
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self.reservation_station.adders[index].time = 2
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if self.register_result_status.float_regs[
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inst.rsIndex].qi != "null":
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self.reservation_station.adders[
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index].qj = self.register_result_status.float_regs[
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inst.rsIndex].qi
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else:
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self.reservation_station.adders[
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index].vj = self.register_result_status.float_regs[
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inst.rsIndex].value
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self.reservation_station.adders[
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index].qj = "null"
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if self.register_result_status.float_regs[
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inst.rtIndex].qi != "null":
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self.reservation_station.adders[
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index].qk = self.register_result_status.float_regs[
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inst.rtIndex].qi
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else:
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self.reservation_station.adders[
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index].vk = self.register_result_status.float_regs[
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inst.rtIndex].value # base address
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self.reservation_station.adders[
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index].qk = "null"
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self.reservation_station.adders[index].busy = True
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self.register_result_status.float_regs[
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inst.
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rdIndex].qi = self.reservation_station.adders[
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index].name
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elif inst.name == MULD or inst.name == DIVD:
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index = self.reservation_station.isFull(
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self.reservation_station.multipliers)
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if index != "True" and self.reservation_station.multipliers[
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index].last_time_write != self.clock:
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inst.issue = self.clock
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self.reservation_station.multipliers[
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index].inst_index = inst.index
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if inst.name == MULD:
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self.reservation_station.multipliers[
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index].time = 10
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self.reservation_station.multipliers[
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index].op = MULD
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elif inst.name == DIVD:
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self.reservation_station.multipliers[
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index].time = 40
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self.reservation_station.multipliers[
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index].op = DIVD
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if self.register_result_status.float_regs[
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inst.rsIndex].qi != "null":
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self.reservation_station.multipliers[
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index].qj = self.register_result_status.float_regs[
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inst.rsIndex].qi
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else:
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self.reservation_station.multipliers[
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index].vj = self.register_result_status.float_regs[
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inst.rsIndex].value
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self.reservation_station.multipliers[
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index].qj = "null"
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if self.register_result_status.float_regs[
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inst.rtIndex].qi != "null":
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self.reservation_station.multipliers[
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index].qk = self.register_result_status.float_regs[
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inst.rtIndex].qi
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else:
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self.reservation_station.multipliers[
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index].vk = self.register_result_status.float_regs[
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inst.rtIndex].value
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self.reservation_station.multipliers[
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index].qk = "null"
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self.reservation_station.multipliers[
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index].busy = True
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self.register_result_status.float_regs[
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inst.
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rdIndex].qi = self.reservation_station.multipliers[
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index].name
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break # issue one instruction per cycle, so break from for loop anyway
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class instruction_status:
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def __init__(self, inst, i):
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inst = inst.split()
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self.name = inst[0]
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self.issue = self.complete = self.write = self.rs = self.rt = self.rd = self.offset = -1
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self.index = i # instruction index for reservation_station mapping
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if self.name == LD or self.name == SD: # target address: rt = base(rs) + offset
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self.offset = int(inst[-1].split("(")[0])
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self.rs = inst[-1].split("(")[-1].split(")")[0] # base address
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self.rsIndex = int(self.rs.split(
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'R')[-1]) # rs index for register_result_status mapping
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self.rt = inst[1] # destination register
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self.rtIndex = int(int(self.rt.split('F')[-1]) / 2)
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else:
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self.rd = inst[1] # destination register
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self.rdIndex = int(int(self.rd.split('F')[-1]) / 2)
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self.rs = inst[2] # source register 1
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self.rsIndex = int(int(self.rs.split('F')[-1]) / 2)
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self.rt = inst[3] # source register 2
|
|
|
self.rtIndex = int(int(self.rt.split('F')[-1]) / 2)
|
|
|
|
|
|
def print(self):
|
|
|
if self.issue == -1: issue = ""
|
|
|
else: issue = self.issue
|
|
|
if self.complete == -1: complete = ""
|
|
|
else: complete = self.complete
|
|
|
if self.write == -1: write = ""
|
|
|
else: write = self.write
|
|
|
|
|
|
if self.name == LD or self.name == SD:
|
|
|
print("\t\t%s\t%s\t%s\t%s\t %s\t %s\t\t %s" %
|
|
|
(self.name, self.rt, self.offset, self.rs, issue, complete,
|
|
|
write))
|
|
|
else:
|
|
|
print(
|
|
|
"\t\t%s\t%s\t%s\t%s\t %s\t %s\t\t %s" %
|
|
|
(self.name, self.rd, self.rs, self.rt, issue, complete, write))
|
|
|
|
|
|
|
|
|
class reservation_station:
|
|
|
|
|
|
def __init__(self, adder_num, multiplier_num):
|
|
|
self.adders = [adder(i) for i in range(adder_num)]
|
|
|
self.multipliers = [multiplier(i) for i in range(multiplier_num)]
|
|
|
|
|
|
def isFull(self, RS):
|
|
|
for rs in RS:
|
|
|
if rs.busy == False: return rs.index
|
|
|
return "True"
|
|
|
|
|
|
def print(self):
|
|
|
print("-\n\nResevation Station:")
|
|
|
print("\t\tTime\tName\tBusy\tOp\tVj\tVk\tQj\tQk")
|
|
|
for adder in self.adders:
|
|
|
self.print_RS(adder)
|
|
|
for multiplier in self.multipliers:
|
|
|
self.print_RS(multiplier)
|
|
|
|
|
|
def print_RS(self, RS):
|
|
|
if RS.time == -1: time = ""
|
|
|
else: time = RS.time
|
|
|
if RS.busy == False: busy = "No"
|
|
|
else: busy = "Yes"
|
|
|
if RS.op == "null": op = ""
|
|
|
else: op = RS.op
|
|
|
if RS.vj == "null": vj = ""
|
|
|
else: vj = RS.vj
|
|
|
if RS.vk == "null": vk = ""
|
|
|
else: vk = RS.vk
|
|
|
if RS.qj == "null": qj = ""
|
|
|
else:
|
|
|
qj = qj = RS.qj.split("_")[0] + "_" + str(
|
|
|
int(RS.qj.split("_")[-1]) + 1)
|
|
|
if RS.qk == "null": qk = ""
|
|
|
else:
|
|
|
qk = RS.qk.split("_")[0] + "_" + str(int(RS.qk.split("_")[-1]) + 1)
|
|
|
name = RS.name.split("_")[0] + "_" + str(
|
|
|
int(RS.name.split("_")[-1]) + 1)
|
|
|
print("\t\t%4s\t%s\t%s\t%s\t%s\t%s\t%s\t%s" %
|
|
|
(time, name, busy, op, vj, vk, qj, qk))
|
|
|
|
|
|
def adderIsFull(self, RS):
|
|
|
for adder in self.adders:
|
|
|
if adder.busy == False: return False
|
|
|
return True
|
|
|
|
|
|
def multiplierIsFull(self, RS):
|
|
|
for multiplier in self.multipliers:
|
|
|
if multiplier.busy == False: return False
|
|
|
return True
|
|
|
|
|
|
|
|
|
class adder:
|
|
|
|
|
|
def __init__(self, i):
|
|
|
self.index = i
|
|
|
self.name = "Add_" + str(i)
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.op = "null"
|
|
|
self.vj = "null"
|
|
|
self.vk = "null"
|
|
|
self.qj = "null"
|
|
|
self.qk = "null"
|
|
|
self.result = 0
|
|
|
self.inst_index = -1
|
|
|
self.vj_broadcasted_cycle = -1
|
|
|
self.vk_broadcasted_cycle = -1
|
|
|
self.last_time_write = -1
|
|
|
|
|
|
def reset(self):
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.op = "null"
|
|
|
self.vj = "null"
|
|
|
self.vk = "null"
|
|
|
self.qj = "null"
|
|
|
self.qk = "null"
|
|
|
#self.result = 0
|
|
|
#self.inst_index = -1
|
|
|
self.vj_broadcasted_cycle = -1
|
|
|
self.vk_broadcasted_cycle = -1
|
|
|
|
|
|
|
|
|
class multiplier:
|
|
|
|
|
|
def __init__(self, i):
|
|
|
self.index = i
|
|
|
self.name = "Mult_" + str(i)
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.op = "null"
|
|
|
self.vj = "null"
|
|
|
self.vk = "null"
|
|
|
self.qj = "null"
|
|
|
self.qk = "null"
|
|
|
self.result = 0
|
|
|
self.inst_index = -1
|
|
|
self.vj_broadcasted_cycle = -1
|
|
|
self.vk_broadcasted_cycle = -1
|
|
|
self.last_time_write = -1
|
|
|
|
|
|
def reset(self):
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.op = "null"
|
|
|
self.vj = "null"
|
|
|
self.vk = "null"
|
|
|
self.qj = "null"
|
|
|
self.qk = "null"
|
|
|
#self.result = 0
|
|
|
#self.inst_index = -1
|
|
|
self.vj_broadcasted_cycle = -1
|
|
|
self.vk_broadcasted_cycle = -1
|
|
|
|
|
|
|
|
|
class load_buffer:
|
|
|
|
|
|
def __init__(self, i):
|
|
|
self.index = i # index for register_result_status mapping
|
|
|
self.name = "Load_" + str(i)
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.vj = "null" # base address
|
|
|
self.qj = "null" # the function unit which is processing base address
|
|
|
self.address = 0
|
|
|
self.result = 0
|
|
|
self.inst_index = -1
|
|
|
self.vj_broadcasted_cycle = -1
|
|
|
self.last_time_write = -1
|
|
|
|
|
|
def reset(self):
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.vj = "null"
|
|
|
self.qj = "null"
|
|
|
self.address = 0
|
|
|
#self.result = 0
|
|
|
#self.inst_index = -1
|
|
|
self.vj_broadcasted_cycle = -1
|
|
|
|
|
|
def print(self):
|
|
|
if self.busy == False: busy = "No"
|
|
|
else: busy = "Yes"
|
|
|
if self.qj == "null": qj = ""
|
|
|
else:
|
|
|
qj = self.qj.split("_")[0] + "_" + str(
|
|
|
int(self.qj.split("_")[-1]) + 1)
|
|
|
name = self.name.split("_")[0] + "_" + str(
|
|
|
int(self.name.split("_")[-1]) + 1)
|
|
|
print("\t\t%s\t%s\t%s\t\t%s" % (name, busy, self.address, qj))
|
|
|
|
|
|
|
|
|
class store_buffer:
|
|
|
# mem[rs + immd.(offset)] = rt
|
|
|
def __init__(self, i):
|
|
|
self.index = i # index for register_result_status mapping
|
|
|
self.name = "Store_" + str(i)
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.vj = "null" # base address register(rs)
|
|
|
self.vk = "null" # source register (rt)
|
|
|
self.qj = "null"
|
|
|
self.qk = "null" # the function unit which is processing base address
|
|
|
self.address = 0
|
|
|
self.result = 0
|
|
|
self.inst_index = -1 # reservation_station 处理的是哪一个 instruction
|
|
|
self.vk_broadcasted_cycle = -1 # 为了不让RS在broadcast的cycle就开始执行，因此必须在RS记录得到broadcast的时间(cycle)
|
|
|
self.last_time_write = -1 # 为了禁止在write result之后的下个cycle释放station后，马上被新的指令issue并放入station中，
|
|
|
# 因此记录该 station 上个指令的 write result 时间，让下个指令必须2个cycle才能issue。
|
|
|
|
|
|
def reset(self):
|
|
|
self.time = -1
|
|
|
self.busy = False
|
|
|
self.vj = "null"
|
|
|
self.vk = "null"
|
|
|
self.qj = "null"
|
|
|
self.qk = "null"
|
|
|
self.address = 0
|
|
|
#self.result = 0
|
|
|
#self.inst_index = -1
|
|
|
self.vk_broadcasted_cycle = -1
|
|
|
|
|
|
def print(self):
|
|
|
if self.busy == False: busy = "No"
|
|
|
else: busy = "Yes"
|
|
|
if self.qk == "null": qk = ""
|
|
|
else:
|
|
|
qk = self.qk.split("_")[0] + "_" + str(
|
|
|
int(self.qk.split("_")[-1]) + 1)
|
|
|
name = self.name.split("_")[0] + "_" + str(
|
|
|
int(self.name.split("_")[-1]) + 1)
|
|
|
print("\t\t%s\t%s\t%s\t\t%s" % (name, busy, self.address, qk))
|
|
|
|
|
|
|
|
|
class mem: # 内存8个Double(64-bit)的(64-Bytes)，初始值1
|
|
|
|
|
|
def __init__(self, i):
|
|
|
self.name = "Mem_" + str(i)
|
|
|
if i % 8 == 0: self.value = 1
|
|
|
else: self.value = 0
|
|
|
|
|
|
|
|
|
class register_result_status:
|
|
|
|
|
|
def __init__(self, float_reg_num, int_reg_num):
|
|
|
self.float_regs = [float_reg(i) for i in range(float_reg_num)
|
|
|
] # 浮点寄存器F0、F2、F4、…、F30，初始值1；
|
|
|
self.int_regs = [int_reg(i)
|
|
|
for i in range(int_reg_num)] # 整数寄存器R0、R1、…、R31
|
|
|
self.int_regs[1].value = 16
|
|
|
|
|
|
def print(self):
|
|
|
print("Register result status:")
|
|
|
a = ""
|
|
|
for fr in self.float_regs:
|
|
|
a += fr.name + "\t"
|
|
|
print("\t\t\t" + a)
|
|
|
|
|
|
a = ""
|
|
|
for fr in self.float_regs:
|
|
|
if fr.qi == "null": qi = ""
|
|
|
else:
|
|
|
qi = fr.qi.split("_")[0] + "_" + str(
|
|
|
int(fr.qi.split("_")[-1]) + 1)
|
|
|
a += str(qi) + "\t"
|
|
|
print("\t\tQi:\t" + a)
|
|
|
|
|
|
a = ""
|
|
|
for fr in self.float_regs:
|
|
|
a += str(fr.value) + "\t"
|
|
|
print("\t\tvalue:\t" + a)
|
|
|
# print("\n")
|
|
|
|
|
|
# a = ""
|
|
|
# for ir in self.int_regs:
|
|
|
# a += ir.name + "\t"
|
|
|
# print("\t\t\t" + a)
|
|
|
|
|
|
# a = ""
|
|
|
# for ir in self.int_regs:
|
|
|
# if ir.qi == "null": qi = ""
|
|
|
# else:
|
|
|
# qi = ir.qi.split("_")[0] + "_" + str(
|
|
|
# int(ir.qi.split("_")[-1]) + 1)
|
|
|
# a += str(qi) + "\t"
|
|
|
# print("\t\tQi:\t" + a)
|
|
|
|
|
|
# a = ""
|
|
|
# for ir in self.int_regs:
|
|
|
# a += str(ir.value) + "\t"
|
|
|
# print("\t\tvalue:\t" + a)
|
|
|
print("-\n")
|
|
|
|
|
|
|
|
|
class float_reg:
|
|
|
|
|
|
def __init__(self, i):
|
|
|
self.name = "F" + str(i * 2)
|
|
|
self.value = 1
|
|
|
self.qi = "null" # 正在等待的 function unit
|
|
|
|
|
|
def print(self):
|
|
|
print("reg %s, value: %d" % (self.name, self.value))
|
|
|
|
|
|
|
|
|
class int_reg:
|
|
|
|
|
|
def __init__(self, i):
|
|
|
self.name = "R" + str(i)
|
|
|
self.value = 0
|
|
|
self.qi = "null" # 正在等待的 function unit
|
|
|
|
|
|
def print(self):
|
|
|
print("reg %s, value: %d" % (self.name, self.value))
|
|
|
|
|
|
|
|
|
def __main__():
|
|
|
# read argument from command lind
|
|
|
# input_argv = "Computer Architecture\TomasuloAlgorithm-master\sample1.txt"
|
|
|
# f = open(input_argv, 'r')
|
|
|
# insts = f.readlines() # read instructions from text file
|
|
|
insts = [
|
|
|
'L.D F6, 8(R2)',
|
|
|
'L.D F2, 40(R3)',
|
|
|
'MUL.D F0, F2, F4',
|
|
|
'SUB.D F8, F6, F2',
|
|
|
'DIV.D F10, F0, F6',
|
|
|
'ADD.D F6, F8, F2',
|
|
|
]
|
|
|
|
|
|
# f.close()
|
|
|
|
|
|
adder_num = 3
|
|
|
multiplier_num = load_buffer_num = store_buffer_num = 2
|
|
|
float_reg_num = 16 # 浮点寄存器, from F0, F2, F4, …, to F30, 初始值为1；
|
|
|
int_reg_num = 32 # 整数寄存器, from R0, R1, …, to R31
|
|
|
mem_size = 64 # 64-byte memory(8 double-precision space)
|
|
|
tomasulo = Tomasulo(insts, adder_num, multiplier_num, load_buffer_num,
|
|
|
store_buffer_num, float_reg_num, int_reg_num, mem_size)
|
|
|
|
|
|
# original_stdout = sys.stdout
|
|
|
# sys.stdout = open(
|
|
|
# r"Computer Architecture\TomasuloAlgorithm\output.txt", "w")
|
|
|
while (True):
|
|
|
#ipdb.set_trace()
|
|
|
tomasulo.writeResult() # 执行已完成Execution的指令
|
|
|
tomasulo.execute() # 执行已完成Issue的指令，维护指令
|
|
|
tomasulo.issue() # issue指令
|
|
|
|
|
|
tomasulo.print()
|
|
|
tomasulo.clock += 1 # steps one clock cycle
|
|
|
|
|
|
if tomasulo.isFinished(): break
|
|
|
#if tomasulo.clock > 71: break
|
|
|
# sys.stdout = original_stdout
|
|
|
|
|
|
|
|
|
if __name__ == "__main__":
|
|
|
__main__()
|
