From b9fb93b7c40986c85df6c5fa8e1488d9c831fca7 Mon Sep 17 00:00:00 2001
From: pumnflqv2 <ggdxz77@163.com>
Date: Sun, 26 Jun 2022 21:44:14 +0800
Subject: [PATCH] ADD file via upload

---
 include/linux/fdreg.h | 71 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 include/linux/fdreg.h

diff --git a/include/linux/fdreg.h b/include/linux/fdreg.h
new file mode 100644
index 0000000..01355af
--- /dev/null
+++ b/include/linux/fdreg.h
@@ -0,0 +1,71 @@
+/*
+ * This file contains some defines for the floppy disk controller.
+ * Various sources. Mostly "IBM Microcomputers: A Programmers
+ * Handbook", Sanches and Canton.
+ */
+#ifndef _FDREG_H
+#define _FDREG_H
+
+extern int ticks_to_floppy_on(unsigned int nr);
+extern void floppy_on(unsigned int nr);
+extern void floppy_off(unsigned int nr);
+extern void floppy_select(unsigned int nr);
+extern void floppy_deselect(unsigned int nr);
+
+/* Fd controller regs. S&C, about page 340 */
+#define FD_STATUS	0x3f4
+#define FD_DATA		0x3f5
+#define FD_DOR		0x3f2		/* Digital Output Register */
+#define FD_DIR		0x3f7		/* Digital Input Register (read) */
+#define FD_DCR		0x3f7		/* Diskette Control Register (write)*/
+
+/* Bits of main status register */
+#define STATUS_BUSYMASK	0x0F		/* drive busy mask */
+#define STATUS_BUSY	0x10		/* FDC busy */
+#define STATUS_DMA	0x20		/* 0- DMA mode */
+#define STATUS_DIR	0x40		/* 0- cpu->fdc */
+#define STATUS_READY	0x80		/* Data reg ready */
+
+/* Bits of FD_ST0 */
+#define ST0_DS		0x03		/* drive select mask */
+#define ST0_HA		0x04		/* Head (Address) */
+#define ST0_NR		0x08		/* Not Ready */
+#define ST0_ECE		0x10		/* Equipment chech error */
+#define ST0_SE		0x20		/* Seek end */
+#define ST0_INTR	0xC0		/* Interrupt code mask */
+
+/* Bits of FD_ST1 */
+#define ST1_MAM		0x01		/* Missing Address Mark */
+#define ST1_WP		0x02		/* Write Protect */
+#define ST1_ND		0x04		/* No Data - unreadable */
+#define ST1_OR		0x10		/* OverRun */
+#define ST1_CRC		0x20		/* CRC error in data or addr */
+#define ST1_EOC		0x80		/* End Of Cylinder */
+
+/* Bits of FD_ST2 */
+#define ST2_MAM		0x01		/* Missing Addess Mark (again) */
+#define ST2_BC		0x02		/* Bad Cylinder */
+#define ST2_SNS		0x04		/* Scan Not Satisfied */
+#define ST2_SEH		0x08		/* Scan Equal Hit */
+#define ST2_WC		0x10		/* Wrong Cylinder */
+#define ST2_CRC		0x20		/* CRC error in data field */
+#define ST2_CM		0x40		/* Control Mark = deleted */
+
+/* Bits of FD_ST3 */
+#define ST3_HA		0x04		/* Head (Address) */
+#define ST3_TZ		0x10		/* Track Zero signal (1=track 0) */
+#define ST3_WP		0x40		/* Write Protect */
+
+/* Values for FD_COMMAND */
+#define FD_RECALIBRATE	0x07		/* move to track 0 */
+#define FD_SEEK		0x0F		/* seek track */
+#define FD_READ		0xE6		/* read with MT, MFM, SKip deleted */
+#define FD_WRITE	0xC5		/* write with MT, MFM */
+#define FD_SENSEI	0x08		/* Sense Interrupt Status */
+#define FD_SPECIFY	0x03		/* specify HUT etc */
+
+/* DMA commands */
+#define DMA_READ	0x46
+#define DMA_WRITE	0x4A
+
+#endif