From 8e6db9f91237d91bb371990cbec77341d2ac30cf Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Tue, 18 Mar 2025 15:47:54 +0800
Subject: [PATCH] =?UTF-8?q?fix(ARegfile):=20=E4=BF=AE=E6=AD=A3=E5=AF=84?=
 =?UTF-8?q?=E5=AD=98=E5=99=A8=E4=BD=8D=E5=AE=BD=E6=B3=A8=E9=87=8A=E4=B8=BA?=
 =?UTF-8?q?XLEN?=
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---
 chisel/playground/src/pipeline/decode/ARegfile.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/chisel/playground/src/pipeline/decode/ARegfile.scala b/chisel/playground/src/pipeline/decode/ARegfile.scala
index acbb27a..4f1915b 100644
--- a/chisel/playground/src/pipeline/decode/ARegfile.scala
+++ b/chisel/playground/src/pipeline/decode/ARegfile.scala
@@ -28,7 +28,7 @@ class ARegFile extends Module {
     val write = Flipped(new RegWrite())
   })
 
-  // 定义32个32位寄存器
+  // 定义32个XLEN位寄存器
   val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W))))
 
   // 写寄存器堆