Compare commits
1 Commits
| Author | SHA1 | Date |
|---|---|---|
 Felix
|
c8144787b0 | 4 months ago |
@ -0,0 +1,36 @@
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version = 2.6.4
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|
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maxColumn = 120
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align = most
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continuationIndent.defnSite = 2
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assumeStandardLibraryStripMargin = true
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docstrings = ScalaDoc
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lineEndings = preserve
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includeCurlyBraceInSelectChains = false
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danglingParentheses = true
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|
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align.tokens.add = [
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{
|
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code = ":"
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},
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{
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code = ":="
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},
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{
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code = "="
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},
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{
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code = "->"
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}
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|
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]
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newlines.alwaysBeforeCurlyBraceLambdaParams = false
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newlines.alwaysBeforeMultilineDef = false
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newlines.implicitParamListModifierForce = [before]
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verticalMultiline.atDefnSite = true
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optIn.annotationNewlines = true
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rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix]
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@ -0,0 +1,46 @@
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BUILD_DIR = ./build
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DIFF_DIR = ../difftest/core
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DIFF_WORK_DIR = ../difftest
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export PATH := $(PATH):$(abspath ./utils)
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verilog:
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$(call git_commit, "generate verilog") # DO NOT REMOVE THIS LINE!!!
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$(MAKE) clean
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mkdir -p $(BUILD_DIR)
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mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
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test:
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@echo "make test"
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$(call git_commit, "test chisel module") # DO NOT REMOVE THIS LINE!!!
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$(MAKE) clean
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mkdir -p $(BUILD_DIR)
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mill -i __.test.runMain TestMain -td $(BUILD_DIR)
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count:
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find ./playground/ -name "*.scala" | xargs wc -l
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help:
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mill -i __.test.runMain Elaborate --help
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compile:
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mill -i __.compile
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bsp:
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mill -i mill.bsp.BSP/install
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reformat:
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mill -i __.reformat
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checkformat:
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mill -i __.checkFormat
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clean:
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-rm -rf $(BUILD_DIR)
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.PHONY: test verilog help compile bsp reformat checkformat clean
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sim:
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@echo "Write this Makefile by yourself."
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-include ../Makefile
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@ -0,0 +1,38 @@
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# Chisel Project Template
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Another version of the [Chisel template](https://github.com/ucb-bar/chisel-template) supporting mill.
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mill is another Scala/Java build tool without obscure DSL like SBT. It is much faster than SBT.
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Contents at a glance:
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- `.gitignore` - helps Git ignore junk like generated files, build products, and temporary files.
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- `build.sc` - instructs mill to build the Chisel project
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- `Makefile` - rules to call mill
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- `playground/src/GCD.scala` - GCD source file
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- `playground/src/DecoupledGCD.scala` - another GCD source file
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- `playground/src/Elaborate.scala` - wrapper file to call chisel command with the GCD module
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- `playground/test/src/GCDSpec.scala` - GCD tester
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Feel free to rename or delete files under `playground/` or use them as a reference/template.
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## Getting Started
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First, install mill by referring to the documentation [here](https://com-lihaoyi.github.io/mill).
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To run all tests in this design (recommended for test-driven development):
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```bash
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make test
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```
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To generate Verilog:
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```bash
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make verilog
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```
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## Change FIRRTL Compiler
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You can change the FIRRTL compiler between SFC (Scala-based FIRRTL compiler) and
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MFC (MLIR-based FIRRTL compiler) by modifying the `useMFC` variable in `playground/src/Elaborate.scala`.
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The latter one requires `firtool`, which is included under `utils/`.
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@ -0,0 +1,45 @@
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// import Mill dependency
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import mill._
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import mill.scalalib._
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import mill.scalalib.scalafmt.ScalafmtModule
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import mill.scalalib.TestModule.ScalaTest
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// support BSP
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import mill.bsp._
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object playground extends ScalaModule with ScalafmtModule { m =>
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val useChisel5 = false
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val useChisel6 = true
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override def scalaVersion = "2.13.10"
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override def scalacOptions = Seq(
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"-language:reflectiveCalls",
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"-deprecation",
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"-feature",
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"-Xcheckinit"
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)
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override def ivyDeps = Agg(
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if (useChisel5) ivy"org.chipsalliance::chisel:5.0.0"
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else if (useChisel6) ivy"org.chipsalliance::chisel:6.1.0"
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else
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ivy"edu.berkeley.cs::chisel3:3.6.0"
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)
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override def scalacPluginIvyDeps = Agg(
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if (useChisel5) ivy"org.chipsalliance:::chisel-plugin:5.0.0"
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else if (useChisel6) ivy"org.chipsalliance:::chisel-plugin:6.1.0"
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else
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ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"
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)
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object test extends ScalaTests with ScalaTest {
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override def ivyDeps = m.ivyDeps() ++ Agg(
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ivy"com.lihaoyi::utest:0.8.1",
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if (useChisel5 || useChisel6) ivy"edu.berkeley.cs::chiseltest:5.0.0"
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else
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ivy"edu.berkeley.cs::chiseltest:0.6.0"
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)
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}
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def repositoriesTask = T.task {
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Seq(
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coursier.MavenRepository("https://maven.aliyun.com/repository/central"),
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coursier.MavenRepository("https://repo.scala-sbt.org/scalasbt/maven-releases")
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) ++ super.repositoriesTask()
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}
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}
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@ -0,0 +1,54 @@
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module top(
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input clock,
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input reset,
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// Interrupts
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input mei, // to PLIC
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input msi, // to CLINT
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input mti, // to CLINT
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input sei, // to PLIC
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// inst sram interface
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output inst_sram_en,
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output [ 3:0] inst_sram_wen,
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output [31:0] inst_sram_addr,
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output [31:0] inst_sram_wdata,
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input [31:0] inst_sram_rdata,
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// data sram interface
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output data_sram_en,
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output [ 7:0] data_sram_wen,
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output [31:0] data_sram_addr,
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output [63:0] data_sram_wdata,
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input [63:0] data_sram_rdata,
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// trace debug interface
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output debug_commit,
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output [63:0] debug_pc,
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output [4:0 ] debug_rf_wnum,
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output [63:0] debug_rf_wdata
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);
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PuaCpu core(
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.clock (clock),
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.reset (reset),
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// interrupts
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.io_ext_int_mei (mei),
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.io_ext_int_mti (mti),
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.io_ext_int_msi (msi),
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// inst sram interface
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.io_inst_sram_en (inst_sram_en),
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.io_inst_sram_wen (inst_sram_wen),
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.io_inst_sram_addr (inst_sram_addr),
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.io_inst_sram_wdata (inst_sram_wdata),
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.io_inst_sram_rdata (inst_sram_rdata),
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// data sram interface
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.io_data_sram_en (data_sram_en),
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.io_data_sram_wen (data_sram_wen),
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.io_data_sram_addr (data_sram_addr),
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.io_data_sram_wdata (data_sram_wdata),
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.io_data_sram_rdata (data_sram_rdata),
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// debug
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.io_debug_pc (debug_pc),
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.io_debug_commit (debug_commit),
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.io_debug_rf_wnum (debug_rf_wnum),
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.io_debug_rf_wdata (debug_rf_wdata)
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);
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endmodule
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@ -0,0 +1,9 @@
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import cpu._
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import circt.stage._
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object Elaborate extends App {
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implicit val cpuConfig = new CpuConfig()
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def top = new PuaCpu()
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val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
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(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
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}
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@ -0,0 +1,20 @@
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import chisel3._
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import chisel3.util._
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import cpu._
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import cpu.defines._
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class PuaCpu extends Module {
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val inst_sram = new InstSram()
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val data_sram = new DataSram()
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val debug = new DEBUG()
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})
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val core = Module(new Core())
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io.ext_int <> core.io.interrupt
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io.inst_sram <> core.io.instSram
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io.data_sram <> core.io.dataSram
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io.debug <> core.io.debug
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}
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@ -0,0 +1,42 @@
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package cpu.defines
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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trait CoreParameter {
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def cpuConfig = new CpuConfig
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val XLEN = if (cpuConfig.isRV32) 32 else 64
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val VADDR_WID = if (cpuConfig.isRV32) 32 else 39
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val PADDR_WID = 32
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}
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trait Constants extends CoreParameter {
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// 全局
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val PC_INIT = "h80000000".U(XLEN.W)
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val INT_WID = 12
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val EXC_WID = 16
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// inst rom
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val INST_WID = 32
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// GPR RegFile
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val AREG_NUM = 32
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val REG_ADDR_WID = 5
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}
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trait SRAMConst extends Constants {
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val SRAM_ADDR_WID = PADDR_WID // 32
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val DATA_SRAM_DATA_WID = XLEN
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val DATA_SRAM_WEN_WID = XLEN / 8
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val INST_SRAM_DATA_WID = INST_WID
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val INST_SRAM_WEN_WID = INST_WID / 8
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}
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object Const extends Constants with SRAMConst
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|
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object Instructions extends HasInstrType with CoreParameter {
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def NOP = 0x00000013.U
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val DecodeDefault = List(InstrN, FuType.alu, ALUOpType.add)
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def DecodeTable = RVIInstr.table
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}
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@ -0,0 +1,29 @@
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package cpu.defines
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import chisel3._
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import chisel3.util._
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object SignedExtend {
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def apply(a: UInt, len: Int) = {
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val aLen = a.getWidth
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val signBit = a(aLen - 1)
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if (aLen >= len) a(len - 1, 0) else Cat(Fill(len - aLen, signBit), a)
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}
|
||||
}
|
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|
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object ZeroExtend {
|
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def apply(a: UInt, len: Int) = {
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val aLen = a.getWidth
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if (aLen >= len) a(len - 1, 0) else Cat(0.U((len - aLen).W), a)
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}
|
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}
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|
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object LookupTree {
|
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def apply[T <: Data](key: UInt, mapping: Iterable[(UInt, T)]): T =
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Mux1H(mapping.map(p => (p._1 === key, p._2)))
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}
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|
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object LookupTreeDefault {
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def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
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MuxLookup(key, default)(mapping.toSeq)
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}
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@ -0,0 +1,36 @@
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package cpu.defines
|
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|
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import chisel3._
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import chisel3.util._
|
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|
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// 指令类型
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trait HasInstrType {
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def InstrN = "b000".U
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def InstrI = "b100".U
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def InstrR = "b101".U
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def InstrS = "b010".U
|
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def InstrB = "b001".U
|
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def InstrU = "b110".U
|
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def InstrJ = "b111".U
|
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|
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// I、R、U、J类型的指令都需要写寄存器
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def isRegWen(instrType: UInt): Bool = instrType(2)
|
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}
|
||||
|
||||
// 功能单元类型 Function Unit Type
|
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object FuType {
|
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def num = 1
|
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def alu = 0.U // arithmetic logic unit
|
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def apply() = UInt(log2Up(num).W)
|
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}
|
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|
||||
// 功能单元操作类型 Function Unit Operation Type
|
||||
object FuOpType {
|
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def apply() = UInt(5.W) // 宽度与最大的功能单元操作类型宽度一致
|
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}
|
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|
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// 算术逻辑单元操作类型 Arithmetic Logic Unit Operation Type
|
||||
object ALUOpType {
|
||||
def add = "b00000".U
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// TODO: 定义更多的ALU操作类型
|
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}
|
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@ -0,0 +1,30 @@
|
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package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class IfIdData extends Bundle {
|
||||
val inst = UInt(XLEN.W)
|
||||
val valid = Bool()
|
||||
val pc = UInt(XLEN.W)
|
||||
}
|
||||
|
||||
class FetchUnitDecodeUnit extends Bundle {
|
||||
val data = Output(new IfIdData())
|
||||
}
|
||||
|
||||
class DecodeStage extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val fetchUnit = Flipped(new FetchUnitDecodeUnit())
|
||||
val decodeUnit = new FetchUnitDecodeUnit()
|
||||
})
|
||||
|
||||
val data = RegInit(0.U.asTypeOf(new IfIdData()))
|
||||
|
||||
data := io.fetchUnit.data
|
||||
|
||||
io.decodeUnit.data := data
|
||||
}
|
||||
@ -0,0 +1,38 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
|
||||
class DecodeUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
// 输入
|
||||
val decodeStage = Flipped(new FetchUnitDecodeUnit())
|
||||
val regfile = new Src12Read()
|
||||
// 输出
|
||||
val executeStage = Output(new DecodeUnitExecuteUnit())
|
||||
})
|
||||
|
||||
// 译码阶段完成指令的译码操作以及源操作数的准备
|
||||
|
||||
val decoder = Module(new Decoder()).io
|
||||
decoder.in.inst := io.decodeStage.data.inst
|
||||
|
||||
val pc = io.decodeStage.data.pc
|
||||
val info = Wire(new Info())
|
||||
|
||||
info := decoder.out.info
|
||||
info.valid := io.decodeStage.data.valid
|
||||
|
||||
// TODO:完成寄存器堆的读取
|
||||
// io.regfile.src1.raddr :=
|
||||
// io.regfile.src2.raddr :=
|
||||
|
||||
// TODO: 完成DecodeUnit模块的逻辑
|
||||
// io.executeStage.data.pc :=
|
||||
// io.executeStage.data.info :=
|
||||
// io.executeStage.data.src_info.src1_data :=
|
||||
// io.executeStage.data.src_info.src2_data :=
|
||||
|
||||
}
|
||||
@ -0,0 +1,28 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class IdExeData extends Bundle {
|
||||
val pc = UInt(XLEN.W)
|
||||
val info = new Info()
|
||||
val src_info = new SrcInfo()
|
||||
}
|
||||
|
||||
class DecodeUnitExecuteUnit extends Bundle {
|
||||
val data = new IdExeData()
|
||||
}
|
||||
|
||||
class ExecuteStage extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val decodeUnit = Input(new DecodeUnitExecuteUnit())
|
||||
val executeUnit = Output(new DecodeUnitExecuteUnit())
|
||||
})
|
||||
|
||||
val data = RegInit(0.U.asTypeOf(new IdExeData()))
|
||||
|
||||
// TODO: 完成ExecuteStage模块的逻辑
|
||||
}
|
||||
@ -0,0 +1,31 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.CpuConfig
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import chisel3.util.experimental.BoringUtils
|
||||
|
||||
class ExecuteUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val executeStage = Input(new DecodeUnitExecuteUnit())
|
||||
val memoryStage = Output(new ExecuteUnitMemoryUnit())
|
||||
val dataSram = new DataSram()
|
||||
})
|
||||
|
||||
// 执行阶段完成指令的执行操作
|
||||
|
||||
val fu = Module(new Fu()).io
|
||||
fu.data.pc := io.executeStage.data.pc
|
||||
fu.data.info := io.executeStage.data.info
|
||||
fu.data.src_info := io.executeStage.data.src_info
|
||||
|
||||
io.dataSram <> fu.dataSram
|
||||
|
||||
// TODO: 完成ExecuteUnit模块的逻辑
|
||||
// io.memoryStage.data.pc :=
|
||||
// io.memoryStage.data.info :=
|
||||
// io.memoryStage.data.src_info :=
|
||||
// io.memoryStage.data.rd_info :=
|
||||
}
|
||||
@ -0,0 +1,32 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class Fu extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val data = new Bundle {
|
||||
val pc = Input(UInt(XLEN.W))
|
||||
val info = Input(new Info())
|
||||
val src_info = Input(new SrcInfo())
|
||||
val rd_info = Output(new RdInfo())
|
||||
}
|
||||
|
||||
val dataSram = new DataSram()
|
||||
})
|
||||
|
||||
val alu = Module(new Alu()).io
|
||||
|
||||
io.dataSram.en := false.B
|
||||
io.dataSram.addr := DontCare
|
||||
io.dataSram.wdata := DontCare
|
||||
io.dataSram.wen := 0.U
|
||||
|
||||
alu.info := io.data.info
|
||||
alu.src_info := io.data.src_info
|
||||
|
||||
io.data.rd_info.wdata := alu.result
|
||||
}
|
||||
@ -0,0 +1,15 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
|
||||
class Alu extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val info = Input(new Info())
|
||||
val src_info = Input(new SrcInfo())
|
||||
val result = Output(UInt(XLEN.W))
|
||||
})
|
||||
// TODO: 完成ALU模块的逻辑
|
||||
}
|
||||
@ -0,0 +1,41 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
import cpu.defines._
|
||||
|
||||
class FetchUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val decodeStage = new FetchUnitDecodeUnit()
|
||||
val instSram = new InstSram()
|
||||
})
|
||||
|
||||
val boot :: send :: receive :: Nil = Enum(3)
|
||||
val state = RegInit(boot)
|
||||
|
||||
switch(state) {
|
||||
is(boot) {
|
||||
state := send
|
||||
}
|
||||
is(send) {
|
||||
state := receive
|
||||
}
|
||||
is(receive) {}
|
||||
}
|
||||
|
||||
// 取指阶段完成指令的取指操作
|
||||
|
||||
val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), state =/= boot)
|
||||
|
||||
io.instSram.addr := pc + 4.U
|
||||
|
||||
io.decodeStage.data.valid := state === receive
|
||||
io.decodeStage.data.pc := pc
|
||||
io.decodeStage.data.inst := io.instSram.rdata
|
||||
|
||||
io.instSram.en := !reset.asBool
|
||||
io.instSram.wen := 0.U
|
||||
io.instSram.wdata := 0.U
|
||||
}
|
||||
@ -0,0 +1,29 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class ExeMemData extends Bundle {
|
||||
val pc = UInt(XLEN.W)
|
||||
val info = new Info()
|
||||
val rd_info = new RdInfo()
|
||||
val src_info = new SrcInfo()
|
||||
}
|
||||
|
||||
class ExecuteUnitMemoryUnit extends Bundle {
|
||||
val data = new ExeMemData()
|
||||
}
|
||||
|
||||
class MemoryStage extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val executeUnit = Input(new ExecuteUnitMemoryUnit())
|
||||
val memoryUnit = Output(new ExecuteUnitMemoryUnit())
|
||||
})
|
||||
|
||||
val data = RegInit(0.U.asTypeOf(new ExeMemData()))
|
||||
|
||||
// TODO: 完成MemoryStage模块的逻辑
|
||||
}
|
||||
@ -0,0 +1,21 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.util.experimental.BoringUtils
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class MemoryUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val memoryStage = Input(new ExecuteUnitMemoryUnit())
|
||||
val writeBackStage = Output(new MemoryUnitWriteBackUnit())
|
||||
})
|
||||
|
||||
// 访存阶段完成指令的访存操作
|
||||
|
||||
io.writeBackStage.data.pc := io.memoryStage.data.pc
|
||||
io.writeBackStage.data.info := io.memoryStage.data.info
|
||||
io.writeBackStage.data.rd_info.wdata := io.memoryStage.data.rd_info.wdata
|
||||
}
|
||||
@ -0,0 +1,27 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class MemWbData extends Bundle {
|
||||
val pc = UInt(XLEN.W)
|
||||
val info = new Info()
|
||||
val rd_info = new RdInfo()
|
||||
}
|
||||
|
||||
class MemoryUnitWriteBackUnit extends Bundle {
|
||||
val data = new MemWbData()
|
||||
}
|
||||
class WriteBackStage extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val memoryUnit = Input(new MemoryUnitWriteBackUnit())
|
||||
val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
|
||||
})
|
||||
|
||||
val data = RegInit(0.U.asTypeOf(new MemWbData()))
|
||||
|
||||
// TODO: 完成WriteBackStage模块的逻辑
|
||||
}
|
||||
@ -0,0 +1,19 @@
|
||||
package cpu.pipeline
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import cpu.CpuConfig
|
||||
|
||||
class WriteBackUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val writeBackStage = Input(new MemoryUnitWriteBackUnit())
|
||||
val regfile = Output(new RegWrite())
|
||||
val debug = new DEBUG()
|
||||
})
|
||||
|
||||
// 写回阶段完成数据的写回操作
|
||||
// 同时该阶段还负责差分测试的比对工作
|
||||
// TODO: 完成WriteBackUnit模块的逻辑
|
||||
}
|
||||
@ -0,0 +1,9 @@
|
||||
// import cpu._
|
||||
// import circt.stage._
|
||||
|
||||
// object TestMain extends App {
|
||||
// implicit val cpuConfig = new CpuConfig()
|
||||
// def top = new Top()
|
||||
// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
|
||||
// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
|
||||
// }
|
||||
@ -0,0 +1,2 @@
|
||||
#!/usr/bin/env bash
|
||||
firtool.elf.strip --lowering-options=disallowLocalVariables,disallowPackedArrays,locationInfoStyle=wrapInAtSquareBracket $@
|
||||
Binary file not shown.
@ -0,0 +1,54 @@
|
||||
module top(
|
||||
input clock,
|
||||
input reset,
|
||||
// Interrupts
|
||||
input mei, // to PLIC
|
||||
input msi, // to CLINT
|
||||
input mti, // to CLINT
|
||||
input sei, // to PLIC
|
||||
// inst sram interface
|
||||
output inst_sram_en,
|
||||
output [ 3:0] inst_sram_wen,
|
||||
output [31:0] inst_sram_addr,
|
||||
output [31:0] inst_sram_wdata,
|
||||
input [31:0] inst_sram_rdata,
|
||||
// data sram interface
|
||||
output data_sram_en,
|
||||
output [ 7:0] data_sram_wen,
|
||||
output [31:0] data_sram_addr,
|
||||
output [63:0] data_sram_wdata,
|
||||
input [63:0] data_sram_rdata,
|
||||
// trace debug interface
|
||||
output debug_commit,
|
||||
output [63:0] debug_pc,
|
||||
output [4:0 ] debug_rf_wnum,
|
||||
output [63:0] debug_rf_wdata
|
||||
);
|
||||
|
||||
PuaCpu core(
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
// interrupts
|
||||
.io_ext_int_mei (mei),
|
||||
.io_ext_int_mti (mti),
|
||||
.io_ext_int_msi (msi),
|
||||
// inst sram interface
|
||||
.io_inst_sram_en (inst_sram_en),
|
||||
.io_inst_sram_wen (inst_sram_wen),
|
||||
.io_inst_sram_addr (inst_sram_addr),
|
||||
.io_inst_sram_wdata (inst_sram_wdata),
|
||||
.io_inst_sram_rdata (inst_sram_rdata),
|
||||
// data sram interface
|
||||
.io_data_sram_en (data_sram_en),
|
||||
.io_data_sram_wen (data_sram_wen),
|
||||
.io_data_sram_addr (data_sram_addr),
|
||||
.io_data_sram_wdata (data_sram_wdata),
|
||||
.io_data_sram_rdata (data_sram_rdata),
|
||||
// debug
|
||||
.io_debug_pc (debug_pc),
|
||||
.io_debug_commit (debug_commit),
|
||||
.io_debug_rf_wnum (debug_rf_wnum),
|
||||
.io_debug_rf_wdata (debug_rf_wdata)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -1,17 +0,0 @@
|
||||
`ifndef MYCPU_H
|
||||
`define MYCPU_H
|
||||
`define XLEN 64
|
||||
// IF_ID_WID = valid + pc + inst = 1 + 64 + 64 = 129
|
||||
`define IF_ID_WID 129
|
||||
`define FU_OP_TYPE_WID 5
|
||||
// INFO_WID = src1_addr + src2_addr + reg_wen + reg_waddr + op
|
||||
// = 5 + 5 + 1 + 5 + `FU_OP_TYPE_WID = 16 + `FU_OP_TYPE_WID
|
||||
`define INFO_WID (16 +`FU_OP_TYPE_WID)
|
||||
// ID_EXE_WID = valid + pc + op + reg_wen + reg_waddr + src1_rdata + src2_rdata
|
||||
// = 1 + 64 + `FU_OP_TYPE_WID + 1 + 5 + 64 + 64 = 199 + `FU_OP_TYPE_WID
|
||||
`define ID_EXE_WID (199 + `FU_OP_TYPE_WID)
|
||||
// EXE_MEM_WID = valid + pc + reg_wen + reg_waddr + reg_wdata
|
||||
// = 1 + 64 + 1 + 5 + 64 = 135
|
||||
`define EXE_MEM_WID 135
|
||||
`define MEM_WB_WID 135
|
||||
`endif
|
||||
@ -1,41 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module DecodeUnit(
|
||||
// 来自DecodeStage的输入
|
||||
input [`IF_ID_WID - 1: 0] decodeStage,
|
||||
// 与ARegfile的接口
|
||||
output [4: 0] src1_raddr,
|
||||
input [`XLEN - 1: 0] src1_rdata,
|
||||
output [4: 0] src2_raddr,
|
||||
input [`XLEN - 1: 0] src2_rdata,
|
||||
// 输出至ExecuteStage的接口
|
||||
output [`ID_EXE_WID - 1: 0] executeStage
|
||||
);
|
||||
|
||||
wire valid;
|
||||
wire [`XLEN - 1: 0] pc;
|
||||
wire [`XLEN - 1: 0] inst;
|
||||
assign {valid, pc, inst} = decodeStage;
|
||||
|
||||
// outports wire
|
||||
wire [`INFO_WID - 1: 0] info;
|
||||
|
||||
// TODO: 完成译码器的实例化
|
||||
|
||||
wire [`FU_OP_TYPE_WID - 1: 0] op;
|
||||
wire reg_wen;
|
||||
wire [4: 0] reg_waddr;
|
||||
|
||||
assign {src1_raddr, src2_raddr, op, reg_wen, reg_waddr} = info;
|
||||
|
||||
assign executeStage = {
|
||||
valid,
|
||||
pc,
|
||||
op,
|
||||
reg_wen,
|
||||
reg_waddr,
|
||||
src1_rdata,
|
||||
src2_rdata
|
||||
};
|
||||
|
||||
endmodule
|
||||
@ -1,45 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module Decoder(
|
||||
input [`XLEN - 1: 0] inst,
|
||||
output [`INFO_WID - 1: 0] info
|
||||
);
|
||||
|
||||
// TODO: 完成译码器逻辑
|
||||
wire [6: 0] opcode = inst[6: 0];
|
||||
// wire [2: 0] funct3 =
|
||||
// wire [6: 0] funct7 =
|
||||
// wire [4: 0] rs =
|
||||
// wire [4: 0] rt =
|
||||
// wire [4: 0] rd =
|
||||
|
||||
wire inst_add = (opcode == 7'b0110011) && (funct3 == 3'b000) && (funct7 == 7'b0000000);
|
||||
// wire inst_sub =
|
||||
// wire inst_sll =
|
||||
// wire inst_slt =
|
||||
// wire inst_sltu =
|
||||
// wire inst_xor =
|
||||
// wire inst_srl =
|
||||
// wire inst_sra =
|
||||
// wire inst_or =
|
||||
// wire inst_and =
|
||||
// wire inst_addw =
|
||||
// wire inst_subw =
|
||||
// wire inst_sllw =
|
||||
// wire inst_srlw =
|
||||
// wire inst_sraw =
|
||||
|
||||
wire [4: 0] src1_raddr = rs;
|
||||
wire [4: 0] src2_raddr = rt;
|
||||
// wire [`FU_OP_TYPE_WID - 1: 0] op =
|
||||
// wire reg_wen =
|
||||
// wire [4: 0] reg_waddr =
|
||||
|
||||
assign info = {
|
||||
src1_raddr,
|
||||
src2_raddr,
|
||||
op,
|
||||
reg_wen,
|
||||
reg_waddr
|
||||
};
|
||||
endmodule
|
||||
@ -1,26 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module DecoderStage(
|
||||
input clock,
|
||||
input reset,
|
||||
input [`IF_ID_WID - 1: 0] fetchUnit,
|
||||
output [`IF_ID_WID - 1: 0] decodeUnit
|
||||
);
|
||||
|
||||
reg [`IF_ID_WID - 1: 0] data;
|
||||
|
||||
always @(posedge clock)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
data <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
data <= fetchUnit;
|
||||
end
|
||||
end
|
||||
|
||||
assign decodeUnit = data;
|
||||
|
||||
endmodule
|
||||
@ -1,12 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module Alu(
|
||||
input [`FU_OP_TYPE_WID - 1: 0] op,
|
||||
input [`XLEN - 1: 0] src1_data,
|
||||
input [`XLEN - 1: 0] src2_data,
|
||||
output [`XLEN - 1: 0] result
|
||||
);
|
||||
|
||||
// TODO: 完成ALU模块的逻辑
|
||||
|
||||
endmodule
|
||||
@ -1,12 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module ExecuteStage(
|
||||
input clock,
|
||||
input reset,
|
||||
input [`ID_EXE_WID - 1: 0] decodeUnit,
|
||||
output [`ID_EXE_WID - 1: 0] executeUnit
|
||||
);
|
||||
|
||||
// TODO: 完成ExcuteStage逻辑
|
||||
|
||||
endmodule
|
||||
@ -1,41 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module ExecuteUnit(
|
||||
// 来自ExecuteStage的输入
|
||||
input [`ID_EXE_WID - 1: 0] executeStage,
|
||||
// 送往MemoryStage的输出
|
||||
output [`EXE_MEM_WID - 1: 0] memoryStage,
|
||||
// 与memory sram的接口
|
||||
output data_sram_en,
|
||||
output [7: 0] data_sram_wen,
|
||||
output [31: 0] data_sram_addr,
|
||||
output [63: 0] data_sram_wdata
|
||||
);
|
||||
|
||||
wire valid;
|
||||
wire [`XLEN - 1: 0] pc;
|
||||
wire [`FU_OP_TYPE_WID - 1: 0] op;
|
||||
wire reg_wen;
|
||||
wire [4: 0] reg_waddr;
|
||||
wire [`XLEN - 1: 0] src1_data;
|
||||
wire [`XLEN - 1: 0] src2_data;
|
||||
assign {valid, pc, op, reg_wen, reg_waddr, src1_data, src2_data} = executeStage;
|
||||
|
||||
wire [`XLEN - 1: 0] reg_wdata;
|
||||
Alu u_Alu(
|
||||
.op ( op ),
|
||||
.src1_data ( src1_data ),
|
||||
.src2_data ( src2_data ),
|
||||
.result ( reg_wdata )
|
||||
);
|
||||
|
||||
|
||||
assign data_sram_en = 1'b0;
|
||||
assign data_sram_wen = 8'b0;
|
||||
assign data_sram_addr = 32'b0;
|
||||
assign data_sram_wdata = 64'b0;
|
||||
|
||||
// TODO:定义和MemoryStage的连接
|
||||
// assign memoryStage =
|
||||
|
||||
endmodule
|
||||
@ -1,66 +0,0 @@
|
||||
|
||||
`include "mycpu.h"
|
||||
module FetchUnit(
|
||||
input clock,
|
||||
input reset,
|
||||
output [`IF_ID_WID - 1: 0] decodeStage,
|
||||
// inst sram interface
|
||||
output inst_sram_en,
|
||||
output [ 3: 0] inst_sram_wen,
|
||||
output [31: 0] inst_sram_addr,
|
||||
output [31: 0] inst_sram_wdata,
|
||||
input [31: 0] inst_sram_rdata
|
||||
);
|
||||
|
||||
reg [1: 0] state;
|
||||
parameter boot = 0;
|
||||
parameter send = 1;
|
||||
parameter receive = 2;
|
||||
|
||||
always @(posedge clock)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
state <= boot;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case (state)
|
||||
boot:
|
||||
state <= send;
|
||||
send:
|
||||
state <= receive;
|
||||
receive:
|
||||
;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg [`XLEN - 1: 0] pc;
|
||||
wire [`XLEN - 1: 0] pc_next = pc + 4;
|
||||
|
||||
always @(posedge clock)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
pc <= 64'h80000000 - 4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (state != boot)
|
||||
pc <= pc_next;
|
||||
end
|
||||
end
|
||||
|
||||
assign inst_sram_en = !reset;
|
||||
assign inst_sram_wen = 0;
|
||||
assign inst_sram_wdata = 0;
|
||||
assign inst_sram_addr = pc_next[31: 0];
|
||||
|
||||
assign decodeStage = {
|
||||
state == receive, // decodeStage.valid
|
||||
pc, // decodeStage.pc
|
||||
{32'b0, inst_sram_rdata} // decodeStage.inst
|
||||
};
|
||||
|
||||
endmodule
|
||||
@ -1,12 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module MemoryStage(
|
||||
input clock,
|
||||
input reset,
|
||||
input [`EXE_MEM_WID - 1: 0] executeUnit,
|
||||
output [`EXE_MEM_WID - 1: 0] memoryUnit
|
||||
);
|
||||
|
||||
// TODO: 完成MemoryStage逻辑
|
||||
|
||||
endmodule
|
||||
@ -1,14 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module MemoryUnit(
|
||||
// 来自MemoryStage的输入
|
||||
input [`EXE_MEM_WID - 1: 0] memoryStage,
|
||||
// 送往WriteBackStage的输出
|
||||
output [`MEM_WB_WID - 1: 0] writeBackStage,
|
||||
// 与memory sram的接口
|
||||
input [`XLEN - 1: 0] data_sram_rdata
|
||||
);
|
||||
|
||||
// TODO: 完成MemoryUnit逻辑
|
||||
|
||||
endmodule
|
||||
@ -1,12 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module WriteBackStage(
|
||||
input clock,
|
||||
input reset,
|
||||
input [`MEM_WB_WID - 1: 0] memoryUnit,
|
||||
output [`MEM_WB_WID - 1: 0] writeBackUnit
|
||||
);
|
||||
|
||||
// TODO: 完成WriteBackStage逻辑
|
||||
|
||||
endmodule
|
||||
@ -1,20 +0,0 @@
|
||||
`include "mycpu.h"
|
||||
|
||||
module WriteBackUnit(
|
||||
input [`MEM_WB_WID - 1: 0] writeBackStage,
|
||||
// 输出至ARegfile
|
||||
output reg_wen,
|
||||
output [4: 0] reg_waddr,
|
||||
output [`XLEN - 1: 0] reg_wdata,
|
||||
// debug
|
||||
output debug_commit,
|
||||
output [63: 0] debug_pc,
|
||||
output [4: 0] debug_rf_wnum,
|
||||
output [63: 0] debug_rf_wdata
|
||||
);
|
||||
|
||||
// 写回阶段完成数据的写回操作
|
||||
// 同时该阶段还负责差分测试的比对工作
|
||||
// TODO: 完成WriteBackUnit模块的逻辑
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in new issue