diff --git a/30.txt b/30.txt
new file mode 100644
index 0000000..a35f3a8
--- /dev/null
+++ b/30.txt
@@ -0,0 +1,5745 @@
+.text
+.global sum
+.type sum, @function
+sum:
+  addi sp, sp, -1760
+  sd ra, 1744(sp)
+  sd s0, 1752(sp)
+  mv s0, sp
+  sd a0, 0(s0)
+  sd a1, 8(s0)
+  sd a2, 16(s0)
+  sd a3, 24(s0)
+  sd a4, 32(s0)
+  sd a5, 40(s0)
+  sd a6, 48(s0)
+  sd a7, 56(s0)
+  ld t0, 1760(s0)
+  sd t0, 64(s0)
+  ld t0, 1768(s0)
+  sd t0, 72(s0)
+  ld t0, 1776(s0)
+  sd t0, 80(s0)
+  ld t0, 1784(s0)
+  sd t0, 88(s0)
+  ld t0, 1792(s0)
+  sd t0, 96(s0)
+  ld t0, 1800(s0)
+  sd t0, 104(s0)
+  ld t0, 1808(s0)
+  sd t0, 112(s0)
+  ld t0, 1816(s0)
+  sd t0, 120(s0)
+  ld t0, 1824(s0)
+  sd t0, 128(s0)
+  ld t0, 1832(s0)
+  sd t0, 136(s0)
+  ld t0, 1840(s0)
+  sd t0, 144(s0)
+  ld t0, 0(s0)
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 156(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 160(s0)
+  lw t0, 160(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 164(s0)
+  ld t0, 8(s0)
+  lw t1, 164(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 172(s0)
+  lw t0, 156(s0)
+  lw t1, 172(s0)
+  add t0, t0, t1
+  sw t0, 176(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 180(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 184(s0)
+  lw t0, 180(s0)
+  lw t1, 184(s0)
+  add t0, t0, t1
+  sw t0, 188(s0)
+  lw t0, 188(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 192(s0)
+  ld t0, 16(s0)
+  lw t1, 192(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 200(s0)
+  lw t0, 176(s0)
+  lw t1, 200(s0)
+  add t0, t0, t1
+  sw t0, 204(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 208(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 212(s0)
+  lw t0, 208(s0)
+  lw t1, 212(s0)
+  add t0, t0, t1
+  sw t0, 216(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 220(s0)
+  lw t0, 216(s0)
+  lw t1, 220(s0)
+  add t0, t0, t1
+  sw t0, 224(s0)
+  lw t0, 224(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 228(s0)
+  ld t0, 24(s0)
+  lw t1, 228(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 236(s0)
+  lw t0, 204(s0)
+  lw t1, 236(s0)
+  add t0, t0, t1
+  sw t0, 240(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 244(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 248(s0)
+  lw t0, 244(s0)
+  lw t1, 248(s0)
+  add t0, t0, t1
+  sw t0, 252(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 256(s0)
+  lw t0, 252(s0)
+  lw t1, 256(s0)
+  add t0, t0, t1
+  sw t0, 260(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 264(s0)
+  lw t0, 260(s0)
+  lw t1, 264(s0)
+  add t0, t0, t1
+  sw t0, 268(s0)
+  lw t0, 268(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 272(s0)
+  ld t0, 32(s0)
+  lw t1, 272(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 280(s0)
+  lw t0, 240(s0)
+  lw t1, 280(s0)
+  add t0, t0, t1
+  sw t0, 284(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 288(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 292(s0)
+  lw t0, 288(s0)
+  lw t1, 292(s0)
+  add t0, t0, t1
+  sw t0, 296(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 300(s0)
+  lw t0, 296(s0)
+  lw t1, 300(s0)
+  add t0, t0, t1
+  sw t0, 304(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 308(s0)
+  lw t0, 304(s0)
+  lw t1, 308(s0)
+  add t0, t0, t1
+  sw t0, 312(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 316(s0)
+  lw t0, 312(s0)
+  lw t1, 316(s0)
+  add t0, t0, t1
+  sw t0, 320(s0)
+  lw t0, 320(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 324(s0)
+  ld t0, 40(s0)
+  lw t1, 324(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 332(s0)
+  lw t0, 284(s0)
+  lw t1, 332(s0)
+  add t0, t0, t1
+  sw t0, 336(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 340(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 344(s0)
+  lw t0, 340(s0)
+  lw t1, 344(s0)
+  add t0, t0, t1
+  sw t0, 348(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 352(s0)
+  lw t0, 348(s0)
+  lw t1, 352(s0)
+  add t0, t0, t1
+  sw t0, 356(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 360(s0)
+  lw t0, 356(s0)
+  lw t1, 360(s0)
+  add t0, t0, t1
+  sw t0, 364(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 368(s0)
+  lw t0, 364(s0)
+  lw t1, 368(s0)
+  add t0, t0, t1
+  sw t0, 372(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 376(s0)
+  lw t0, 372(s0)
+  lw t1, 376(s0)
+  add t0, t0, t1
+  sw t0, 380(s0)
+  lw t0, 380(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 384(s0)
+  ld t0, 48(s0)
+  lw t1, 384(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 392(s0)
+  lw t0, 336(s0)
+  lw t1, 392(s0)
+  add t0, t0, t1
+  sw t0, 396(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 400(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 404(s0)
+  lw t0, 400(s0)
+  lw t1, 404(s0)
+  add t0, t0, t1
+  sw t0, 408(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 412(s0)
+  lw t0, 408(s0)
+  lw t1, 412(s0)
+  add t0, t0, t1
+  sw t0, 416(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 420(s0)
+  lw t0, 416(s0)
+  lw t1, 420(s0)
+  add t0, t0, t1
+  sw t0, 424(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 428(s0)
+  lw t0, 424(s0)
+  lw t1, 428(s0)
+  add t0, t0, t1
+  sw t0, 432(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 436(s0)
+  lw t0, 432(s0)
+  lw t1, 436(s0)
+  add t0, t0, t1
+  sw t0, 440(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 444(s0)
+  lw t0, 440(s0)
+  lw t1, 444(s0)
+  add t0, t0, t1
+  sw t0, 448(s0)
+  lw t0, 448(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 452(s0)
+  ld t0, 56(s0)
+  lw t1, 452(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 460(s0)
+  lw t0, 396(s0)
+  lw t1, 460(s0)
+  add t0, t0, t1
+  sw t0, 464(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 468(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 472(s0)
+  lw t0, 468(s0)
+  lw t1, 472(s0)
+  add t0, t0, t1
+  sw t0, 476(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 480(s0)
+  lw t0, 476(s0)
+  lw t1, 480(s0)
+  add t0, t0, t1
+  sw t0, 484(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 488(s0)
+  lw t0, 484(s0)
+  lw t1, 488(s0)
+  add t0, t0, t1
+  sw t0, 492(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 496(s0)
+  lw t0, 492(s0)
+  lw t1, 496(s0)
+  add t0, t0, t1
+  sw t0, 500(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 504(s0)
+  lw t0, 500(s0)
+  lw t1, 504(s0)
+  add t0, t0, t1
+  sw t0, 508(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 512(s0)
+  lw t0, 508(s0)
+  lw t1, 512(s0)
+  add t0, t0, t1
+  sw t0, 516(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 520(s0)
+  lw t0, 516(s0)
+  lw t1, 520(s0)
+  add t0, t0, t1
+  sw t0, 524(s0)
+  lw t0, 524(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 528(s0)
+  ld t0, 64(s0)
+  lw t1, 528(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 536(s0)
+  lw t0, 464(s0)
+  lw t1, 536(s0)
+  add t0, t0, t1
+  sw t0, 540(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 544(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 548(s0)
+  lw t0, 544(s0)
+  lw t1, 548(s0)
+  add t0, t0, t1
+  sw t0, 552(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 556(s0)
+  lw t0, 552(s0)
+  lw t1, 556(s0)
+  add t0, t0, t1
+  sw t0, 560(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 564(s0)
+  lw t0, 560(s0)
+  lw t1, 564(s0)
+  add t0, t0, t1
+  sw t0, 568(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 572(s0)
+  lw t0, 568(s0)
+  lw t1, 572(s0)
+  add t0, t0, t1
+  sw t0, 576(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 580(s0)
+  lw t0, 576(s0)
+  lw t1, 580(s0)
+  add t0, t0, t1
+  sw t0, 584(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 588(s0)
+  lw t0, 584(s0)
+  lw t1, 588(s0)
+  add t0, t0, t1
+  sw t0, 592(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 596(s0)
+  lw t0, 592(s0)
+  lw t1, 596(s0)
+  add t0, t0, t1
+  sw t0, 600(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 604(s0)
+  lw t0, 600(s0)
+  lw t1, 604(s0)
+  add t0, t0, t1
+  sw t0, 608(s0)
+  lw t0, 608(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 612(s0)
+  ld t0, 72(s0)
+  lw t1, 612(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 620(s0)
+  lw t0, 540(s0)
+  lw t1, 620(s0)
+  add t0, t0, t1
+  sw t0, 624(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 628(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 632(s0)
+  lw t0, 628(s0)
+  lw t1, 632(s0)
+  add t0, t0, t1
+  sw t0, 636(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 640(s0)
+  lw t0, 636(s0)
+  lw t1, 640(s0)
+  add t0, t0, t1
+  sw t0, 644(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 648(s0)
+  lw t0, 644(s0)
+  lw t1, 648(s0)
+  add t0, t0, t1
+  sw t0, 652(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 656(s0)
+  lw t0, 652(s0)
+  lw t1, 656(s0)
+  add t0, t0, t1
+  sw t0, 660(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 664(s0)
+  lw t0, 660(s0)
+  lw t1, 664(s0)
+  add t0, t0, t1
+  sw t0, 668(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 672(s0)
+  lw t0, 668(s0)
+  lw t1, 672(s0)
+  add t0, t0, t1
+  sw t0, 676(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 680(s0)
+  lw t0, 676(s0)
+  lw t1, 680(s0)
+  add t0, t0, t1
+  sw t0, 684(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 688(s0)
+  lw t0, 684(s0)
+  lw t1, 688(s0)
+  add t0, t0, t1
+  sw t0, 692(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 696(s0)
+  lw t0, 692(s0)
+  lw t1, 696(s0)
+  add t0, t0, t1
+  sw t0, 700(s0)
+  lw t0, 700(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 704(s0)
+  ld t0, 80(s0)
+  lw t1, 704(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 712(s0)
+  lw t0, 624(s0)
+  lw t1, 712(s0)
+  add t0, t0, t1
+  sw t0, 716(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 720(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 724(s0)
+  lw t0, 720(s0)
+  lw t1, 724(s0)
+  add t0, t0, t1
+  sw t0, 728(s0)
+  li t0, 1
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 732(s0)
+  lw t0, 728(s0)
+  lw t1, 732(s0)
+  add t0, t0, t1
+  sw t0, 736(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 740(s0)
+  lw t0, 736(s0)
+  lw t1, 740(s0)
+  add t0, t0, t1
+  sw t0, 744(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 748(s0)
+  lw t0, 744(s0)
+  lw t1, 748(s0)
+  add t0, t0, t1
+  sw t0, 752(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 756(s0)
+  lw t0, 752(s0)
+  lw t1, 756(s0)
+  add t0, t0, t1
+  sw t0, 760(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 764(s0)
+  lw t0, 760(s0)
+  lw t1, 764(s0)
+  add t0, t0, t1
+  sw t0, 768(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 772(s0)
+  lw t0, 768(s0)
+  lw t1, 772(s0)
+  add t0, t0, t1
+  sw t0, 776(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 780(s0)
+  lw t0, 776(s0)
+  lw t1, 780(s0)
+  add t0, t0, t1
+  sw t0, 784(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 788(s0)
+  lw t0, 784(s0)
+  lw t1, 788(s0)
+  add t0, t0, t1
+  sw t0, 792(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 796(s0)
+  lw t0, 792(s0)
+  lw t1, 796(s0)
+  add t0, t0, t1
+  sw t0, 800(s0)
+  lw t0, 800(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 804(s0)
+  ld t0, 88(s0)
+  lw t1, 804(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 812(s0)
+  lw t0, 716(s0)
+  lw t1, 812(s0)
+  add t0, t0, t1
+  sw t0, 816(s0)
+  li t0, 1
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 820(s0)
+  li t0, 1
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 824(s0)
+  lw t0, 820(s0)
+  lw t1, 824(s0)
+  add t0, t0, t1
+  sw t0, 828(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 832(s0)
+  lw t0, 828(s0)
+  lw t1, 832(s0)
+  add t0, t0, t1
+  sw t0, 836(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 840(s0)
+  lw t0, 836(s0)
+  lw t1, 840(s0)
+  add t0, t0, t1
+  sw t0, 844(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 848(s0)
+  lw t0, 844(s0)
+  lw t1, 848(s0)
+  add t0, t0, t1
+  sw t0, 852(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 856(s0)
+  lw t0, 852(s0)
+  lw t1, 856(s0)
+  add t0, t0, t1
+  sw t0, 860(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 864(s0)
+  lw t0, 860(s0)
+  lw t1, 864(s0)
+  add t0, t0, t1
+  sw t0, 868(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 872(s0)
+  lw t0, 868(s0)
+  lw t1, 872(s0)
+  add t0, t0, t1
+  sw t0, 876(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 880(s0)
+  lw t0, 876(s0)
+  lw t1, 880(s0)
+  add t0, t0, t1
+  sw t0, 884(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 888(s0)
+  lw t0, 884(s0)
+  lw t1, 888(s0)
+  add t0, t0, t1
+  sw t0, 892(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 896(s0)
+  lw t0, 892(s0)
+  lw t1, 896(s0)
+  add t0, t0, t1
+  sw t0, 900(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 904(s0)
+  lw t0, 900(s0)
+  lw t1, 904(s0)
+  add t0, t0, t1
+  sw t0, 908(s0)
+  lw t0, 908(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 912(s0)
+  ld t0, 96(s0)
+  lw t1, 912(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 920(s0)
+  lw t0, 816(s0)
+  lw t1, 920(s0)
+  add t0, t0, t1
+  sw t0, 924(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 928(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 932(s0)
+  lw t0, 928(s0)
+  lw t1, 932(s0)
+  add t0, t0, t1
+  sw t0, 936(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 940(s0)
+  lw t0, 936(s0)
+  lw t1, 940(s0)
+  add t0, t0, t1
+  sw t0, 944(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 948(s0)
+  lw t0, 944(s0)
+  lw t1, 948(s0)
+  add t0, t0, t1
+  sw t0, 952(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 956(s0)
+  lw t0, 952(s0)
+  lw t1, 956(s0)
+  add t0, t0, t1
+  sw t0, 960(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 964(s0)
+  lw t0, 960(s0)
+  lw t1, 964(s0)
+  add t0, t0, t1
+  sw t0, 968(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 972(s0)
+  lw t0, 968(s0)
+  lw t1, 972(s0)
+  add t0, t0, t1
+  sw t0, 976(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 980(s0)
+  lw t0, 976(s0)
+  lw t1, 980(s0)
+  add t0, t0, t1
+  sw t0, 984(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 988(s0)
+  lw t0, 984(s0)
+  lw t1, 988(s0)
+  add t0, t0, t1
+  sw t0, 992(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 996(s0)
+  lw t0, 992(s0)
+  lw t1, 996(s0)
+  add t0, t0, t1
+  sw t0, 1000(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1004(s0)
+  lw t0, 1000(s0)
+  lw t1, 1004(s0)
+  add t0, t0, t1
+  sw t0, 1008(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1012(s0)
+  lw t0, 1008(s0)
+  lw t1, 1012(s0)
+  add t0, t0, t1
+  sw t0, 1016(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1020(s0)
+  lw t0, 1016(s0)
+  lw t1, 1020(s0)
+  add t0, t0, t1
+  sw t0, 1024(s0)
+  lw t0, 1024(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1028(s0)
+  ld t0, 104(s0)
+  lw t1, 1028(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1036(s0)
+  lw t0, 924(s0)
+  lw t1, 1036(s0)
+  add t0, t0, t1
+  sw t0, 1040(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1044(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1048(s0)
+  lw t0, 1044(s0)
+  lw t1, 1048(s0)
+  add t0, t0, t1
+  sw t0, 1052(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1056(s0)
+  lw t0, 1052(s0)
+  lw t1, 1056(s0)
+  add t0, t0, t1
+  sw t0, 1060(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1064(s0)
+  lw t0, 1060(s0)
+  lw t1, 1064(s0)
+  add t0, t0, t1
+  sw t0, 1068(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1072(s0)
+  lw t0, 1068(s0)
+  lw t1, 1072(s0)
+  add t0, t0, t1
+  sw t0, 1076(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1080(s0)
+  lw t0, 1076(s0)
+  lw t1, 1080(s0)
+  add t0, t0, t1
+  sw t0, 1084(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1088(s0)
+  lw t0, 1084(s0)
+  lw t1, 1088(s0)
+  add t0, t0, t1
+  sw t0, 1092(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1096(s0)
+  lw t0, 1092(s0)
+  lw t1, 1096(s0)
+  add t0, t0, t1
+  sw t0, 1100(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1104(s0)
+  lw t0, 1100(s0)
+  lw t1, 1104(s0)
+  add t0, t0, t1
+  sw t0, 1108(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1112(s0)
+  lw t0, 1108(s0)
+  lw t1, 1112(s0)
+  add t0, t0, t1
+  sw t0, 1116(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1120(s0)
+  lw t0, 1116(s0)
+  lw t1, 1120(s0)
+  add t0, t0, t1
+  sw t0, 1124(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1128(s0)
+  lw t0, 1124(s0)
+  lw t1, 1128(s0)
+  add t0, t0, t1
+  sw t0, 1132(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1136(s0)
+  lw t0, 1132(s0)
+  lw t1, 1136(s0)
+  add t0, t0, t1
+  sw t0, 1140(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1144(s0)
+  lw t0, 1140(s0)
+  lw t1, 1144(s0)
+  add t0, t0, t1
+  sw t0, 1148(s0)
+  lw t0, 1148(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1152(s0)
+  ld t0, 112(s0)
+  lw t1, 1152(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1160(s0)
+  lw t0, 1040(s0)
+  lw t1, 1160(s0)
+  add t0, t0, t1
+  sw t0, 1164(s0)
+  li t0, 1
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1168(s0)
+  li t0, 1
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1172(s0)
+  lw t0, 1168(s0)
+  lw t1, 1172(s0)
+  add t0, t0, t1
+  sw t0, 1176(s0)
+  li t0, 1
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1180(s0)
+  lw t0, 1176(s0)
+  lw t1, 1180(s0)
+  add t0, t0, t1
+  sw t0, 1184(s0)
+  li t0, 1
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1188(s0)
+  lw t0, 1184(s0)
+  lw t1, 1188(s0)
+  add t0, t0, t1
+  sw t0, 1192(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1196(s0)
+  lw t0, 1192(s0)
+  lw t1, 1196(s0)
+  add t0, t0, t1
+  sw t0, 1200(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1204(s0)
+  lw t0, 1200(s0)
+  lw t1, 1204(s0)
+  add t0, t0, t1
+  sw t0, 1208(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1212(s0)
+  lw t0, 1208(s0)
+  lw t1, 1212(s0)
+  add t0, t0, t1
+  sw t0, 1216(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1220(s0)
+  lw t0, 1216(s0)
+  lw t1, 1220(s0)
+  add t0, t0, t1
+  sw t0, 1224(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1228(s0)
+  lw t0, 1224(s0)
+  lw t1, 1228(s0)
+  add t0, t0, t1
+  sw t0, 1232(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1236(s0)
+  lw t0, 1232(s0)
+  lw t1, 1236(s0)
+  add t0, t0, t1
+  sw t0, 1240(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1244(s0)
+  lw t0, 1240(s0)
+  lw t1, 1244(s0)
+  add t0, t0, t1
+  sw t0, 1248(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1252(s0)
+  lw t0, 1248(s0)
+  lw t1, 1252(s0)
+  add t0, t0, t1
+  sw t0, 1256(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1260(s0)
+  lw t0, 1256(s0)
+  lw t1, 1260(s0)
+  add t0, t0, t1
+  sw t0, 1264(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1268(s0)
+  lw t0, 1264(s0)
+  lw t1, 1268(s0)
+  add t0, t0, t1
+  sw t0, 1272(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1276(s0)
+  lw t0, 1272(s0)
+  lw t1, 1276(s0)
+  add t0, t0, t1
+  sw t0, 1280(s0)
+  lw t0, 1280(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 1284(s0)
+  ld t0, 120(s0)
+  lw t1, 1284(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1292(s0)
+  lw t0, 1164(s0)
+  lw t1, 1292(s0)
+  add t0, t0, t1
+  sw t0, 1296(s0)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  sw t0, 1300(s0)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1304(s0)
+  lw t0, 1300(s0)
+  lw t1, 1304(s0)
+  add t0, t0, t1
+  sw t0, 1308(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1312(s0)
+  lw t0, 1308(s0)
+  lw t1, 1312(s0)
+  add t0, t0, t1
+  sw t0, 1316(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1320(s0)
+  lw t0, 1316(s0)
+  lw t1, 1320(s0)
+  add t0, t0, t1
+  sw t0, 1324(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1328(s0)
+  lw t0, 1324(s0)
+  lw t1, 1328(s0)
+  add t0, t0, t1
+  sw t0, 1332(s0)
+  li t0, 1
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1336(s0)
+  lw t0, 1332(s0)
+  lw t1, 1336(s0)
+  add t0, t0, t1
+  sw t0, 1340(s0)
+  li t0, 1
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1344(s0)
+  lw t0, 1340(s0)
+  lw t1, 1344(s0)
+  add t0, t0, t1
+  sw t0, 1348(s0)
+  li t0, 1
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1352(s0)
+  lw t0, 1348(s0)
+  lw t1, 1352(s0)
+  add t0, t0, t1
+  sw t0, 1356(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1360(s0)
+  lw t0, 1356(s0)
+  lw t1, 1360(s0)
+  add t0, t0, t1
+  sw t0, 1364(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1368(s0)
+  lw t0, 1364(s0)
+  lw t1, 1368(s0)
+  add t0, t0, t1
+  sw t0, 1372(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1376(s0)
+  lw t0, 1372(s0)
+  lw t1, 1376(s0)
+  add t0, t0, t1
+  sw t0, 1380(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1384(s0)
+  lw t0, 1380(s0)
+  lw t1, 1384(s0)
+  add t0, t0, t1
+  sw t0, 1388(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1392(s0)
+  lw t0, 1388(s0)
+  lw t1, 1392(s0)
+  add t0, t0, t1
+  sw t0, 1396(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1400(s0)
+  lw t0, 1396(s0)
+  lw t1, 1400(s0)
+  add t0, t0, t1
+  sw t0, 1404(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1408(s0)
+  lw t0, 1404(s0)
+  lw t1, 1408(s0)
+  add t0, t0, t1
+  sw t0, 1412(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1416(s0)
+  lw t0, 1412(s0)
+  lw t1, 1416(s0)
+  add t0, t0, t1
+  sw t0, 1420(s0)
+  lw t0, 1420(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1424(s0)
+  ld t0, 128(s0)
+  lw t1, 1424(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1432(s0)
+  lw t0, 1296(s0)
+  lw t1, 1432(s0)
+  add t0, t0, t1
+  sw t0, 1436(s0)
+  li t0, 1
+  li t1, 131072
+  mul t0, t0, t1
+  sw t0, 1440(s0)
+  li t0, 1
+  li t1, 65536
+  mul t0, t0, t1
+  sw t0, 1444(s0)
+  lw t0, 1440(s0)
+  lw t1, 1444(s0)
+  add t0, t0, t1
+  sw t0, 1448(s0)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1452(s0)
+  lw t0, 1448(s0)
+  lw t1, 1452(s0)
+  add t0, t0, t1
+  sw t0, 1456(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1460(s0)
+  lw t0, 1456(s0)
+  lw t1, 1460(s0)
+  add t0, t0, t1
+  sw t0, 1464(s0)
+  li t0, 1
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1468(s0)
+  lw t0, 1464(s0)
+  lw t1, 1468(s0)
+  add t0, t0, t1
+  sw t0, 1472(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1476(s0)
+  lw t0, 1472(s0)
+  lw t1, 1476(s0)
+  add t0, t0, t1
+  sw t0, 1480(s0)
+  li t0, 1
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1484(s0)
+  lw t0, 1480(s0)
+  lw t1, 1484(s0)
+  add t0, t0, t1
+  sw t0, 1488(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1492(s0)
+  lw t0, 1488(s0)
+  lw t1, 1492(s0)
+  add t0, t0, t1
+  sw t0, 1496(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1500(s0)
+  lw t0, 1496(s0)
+  lw t1, 1500(s0)
+  add t0, t0, t1
+  sw t0, 1504(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1508(s0)
+  lw t0, 1504(s0)
+  lw t1, 1508(s0)
+  add t0, t0, t1
+  sw t0, 1512(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1516(s0)
+  lw t0, 1512(s0)
+  lw t1, 1516(s0)
+  add t0, t0, t1
+  sw t0, 1520(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1524(s0)
+  lw t0, 1520(s0)
+  lw t1, 1524(s0)
+  add t0, t0, t1
+  sw t0, 1528(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1532(s0)
+  lw t0, 1528(s0)
+  lw t1, 1532(s0)
+  add t0, t0, t1
+  sw t0, 1536(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1540(s0)
+  lw t0, 1536(s0)
+  lw t1, 1540(s0)
+  add t0, t0, t1
+  sw t0, 1544(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1548(s0)
+  lw t0, 1544(s0)
+  lw t1, 1548(s0)
+  add t0, t0, t1
+  sw t0, 1552(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1556(s0)
+  lw t0, 1552(s0)
+  lw t1, 1556(s0)
+  add t0, t0, t1
+  sw t0, 1560(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1564(s0)
+  lw t0, 1560(s0)
+  lw t1, 1564(s0)
+  add t0, t0, t1
+  sw t0, 1568(s0)
+  lw t0, 1568(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1572(s0)
+  ld t0, 136(s0)
+  lw t1, 1572(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1580(s0)
+  lw t0, 1436(s0)
+  lw t1, 1580(s0)
+  add t0, t0, t1
+  sw t0, 1584(s0)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  sw t0, 1588(s0)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  sw t0, 1592(s0)
+  lw t0, 1588(s0)
+  lw t1, 1592(s0)
+  add t0, t0, t1
+  sw t0, 1596(s0)
+  li t0, 1
+  li t1, 65536
+  mul t0, t0, t1
+  sw t0, 1600(s0)
+  lw t0, 1596(s0)
+  lw t1, 1600(s0)
+  add t0, t0, t1
+  sw t0, 1604(s0)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1608(s0)
+  lw t0, 1604(s0)
+  lw t1, 1608(s0)
+  add t0, t0, t1
+  sw t0, 1612(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1616(s0)
+  lw t0, 1612(s0)
+  lw t1, 1616(s0)
+  add t0, t0, t1
+  sw t0, 1620(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1624(s0)
+  lw t0, 1620(s0)
+  lw t1, 1624(s0)
+  add t0, t0, t1
+  sw t0, 1628(s0)
+  li t0, 1
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1632(s0)
+  lw t0, 1628(s0)
+  lw t1, 1632(s0)
+  add t0, t0, t1
+  sw t0, 1636(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1640(s0)
+  lw t0, 1636(s0)
+  lw t1, 1640(s0)
+  add t0, t0, t1
+  sw t0, 1644(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1648(s0)
+  lw t0, 1644(s0)
+  lw t1, 1648(s0)
+  add t0, t0, t1
+  sw t0, 1652(s0)
+  li t0, 1
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1656(s0)
+  lw t0, 1652(s0)
+  lw t1, 1656(s0)
+  add t0, t0, t1
+  sw t0, 1660(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1664(s0)
+  lw t0, 1660(s0)
+  lw t1, 1664(s0)
+  add t0, t0, t1
+  sw t0, 1668(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1672(s0)
+  lw t0, 1668(s0)
+  lw t1, 1672(s0)
+  add t0, t0, t1
+  sw t0, 1676(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1680(s0)
+  lw t0, 1676(s0)
+  lw t1, 1680(s0)
+  add t0, t0, t1
+  sw t0, 1684(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1688(s0)
+  lw t0, 1684(s0)
+  lw t1, 1688(s0)
+  add t0, t0, t1
+  sw t0, 1692(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1696(s0)
+  lw t0, 1692(s0)
+  lw t1, 1696(s0)
+  add t0, t0, t1
+  sw t0, 1700(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1704(s0)
+  lw t0, 1700(s0)
+  lw t1, 1704(s0)
+  add t0, t0, t1
+  sw t0, 1708(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1712(s0)
+  lw t0, 1708(s0)
+  lw t1, 1712(s0)
+  add t0, t0, t1
+  sw t0, 1716(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1720(s0)
+  lw t0, 1716(s0)
+  lw t1, 1720(s0)
+  add t0, t0, t1
+  sw t0, 1724(s0)
+  lw t0, 1724(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 1728(s0)
+  ld t0, 144(s0)
+  lw t1, 1728(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1736(s0)
+  lw t0, 1584(s0)
+  lw t1, 1736(s0)
+  add t0, t0, t1
+  sw t0, 1740(s0)
+  lw a0, 1740(s0)
+  ld ra, 1744(s0)
+  addi sp, s0, 1760
+  ld s0, 1752(s0)
+  ret
+.size sum, .-sum
+
+.global main
+.type main, @function
+main:
+  li t4, -2099184
+  add sp, sp, t4
+  li t4, 2099168
+  add t4, sp, t4
+  sd ra, 0(t4)
+  li t4, 2099176
+  add t4, sp, t4
+  sd s0, 0(t4)
+  mv s0, sp
+  addi a0, s0, 0
+  li a1, 0
+  li a2, 2097152
+  call memset
+  li t0, 0
+  li t4, 2097152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t4, 2097156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L0.while.cond
+L0.while.cond:
+  li t4, 2097156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097160
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097160
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097164
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097164
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L1.while.body
+  j L2.while.end
+L1.while.body:
+  li t0, 0
+  li t4, 2097168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L3.while.cond
+L3.while.cond:
+  li t4, 2097168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097172
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097176
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097176
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L4.while.body
+  j L5.while.end
+L4.while.body:
+  li t0, 0
+  li t4, 2097180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L6.while.cond
+L6.while.cond:
+  li t4, 2097180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097184
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097184
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097188
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L7.while.body
+  j L8.while.end
+L7.while.body:
+  li t0, 0
+  li t4, 2097192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L9.while.cond
+L9.while.cond:
+  li t4, 2097192
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097196
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097196
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097200
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097200
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L10.while.body
+  j L11.while.end
+L10.while.body:
+  li t0, 0
+  li t4, 2097204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L12.while.cond
+L12.while.cond:
+  li t4, 2097204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097208
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097208
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097212
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097212
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L13.while.body
+  j L14.while.end
+L13.while.body:
+  li t0, 0
+  li t4, 2097216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L15.while.cond
+L15.while.cond:
+  li t4, 2097216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097220
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097220
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097224
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097224
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L16.while.body
+  j L17.while.end
+L16.while.body:
+  li t0, 0
+  li t4, 2097228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L18.while.cond
+L18.while.cond:
+  li t4, 2097228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097232
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097232
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097236
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097236
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L19.while.body
+  j L20.while.end
+L19.while.body:
+  li t0, 0
+  li t4, 2097240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L21.while.cond
+L21.while.cond:
+  li t4, 2097240
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097244
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097244
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097248
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097248
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L22.while.body
+  j L23.while.end
+L22.while.body:
+  li t0, 0
+  li t4, 2097252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L24.while.cond
+L24.while.cond:
+  li t4, 2097252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097256
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097256
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097260
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097260
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L25.while.body
+  j L26.while.end
+L25.while.body:
+  li t0, 0
+  li t4, 2097264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L27.while.cond
+L27.while.cond:
+  li t4, 2097264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097268
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097268
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097272
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097272
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L28.while.body
+  j L29.while.end
+L28.while.body:
+  li t0, 0
+  li t4, 2097276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L30.while.cond
+L30.while.cond:
+  li t4, 2097276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097280
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097280
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097284
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097284
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L31.while.body
+  j L32.while.end
+L31.while.body:
+  li t0, 0
+  li t4, 2097288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L33.while.cond
+L33.while.cond:
+  li t4, 2097288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097292
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097296
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097296
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L34.while.body
+  j L35.while.end
+L34.while.body:
+  li t0, 0
+  li t4, 2097300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L36.while.cond
+L36.while.cond:
+  li t4, 2097300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097304
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097304
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097308
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097308
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L37.while.body
+  j L38.while.end
+L37.while.body:
+  li t0, 0
+  li t4, 2097312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L39.while.cond
+L39.while.cond:
+  li t4, 2097312
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097316
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097320
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097320
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L40.while.body
+  j L41.while.end
+L40.while.body:
+  li t0, 0
+  li t4, 2097324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L42.while.cond
+L42.while.cond:
+  li t4, 2097324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097328
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097328
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097332
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097332
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L43.while.body
+  j L44.while.end
+L43.while.body:
+  li t0, 0
+  li t4, 2097336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L45.while.cond
+L45.while.cond:
+  li t4, 2097336
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097340
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097340
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097344
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097344
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L46.while.body
+  j L47.while.end
+L46.while.body:
+  li t0, 0
+  li t4, 2097348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L48.while.cond
+L48.while.cond:
+  li t4, 2097348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097352
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097352
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097356
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097356
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L49.while.body
+  j L50.while.end
+L49.while.body:
+  li t0, 0
+  li t4, 2097360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L51.while.cond
+L51.while.cond:
+  li t4, 2097360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097364
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097364
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097368
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097368
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L52.while.body
+  j L53.while.end
+L52.while.body:
+  li t0, 0
+  li t4, 2097372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L54.while.cond
+L54.while.cond:
+  li t4, 2097372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097376
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097376
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097380
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097380
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L55.while.body
+  j L56.while.end
+L55.while.body:
+  li t4, 2097152
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097384
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097388
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097392
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097392
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  mul t0, t0, t1
+  li t4, 2097396
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097388
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097396
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097400
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097404
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097404
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 4
+  mul t0, t0, t1
+  li t4, 2097408
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097400
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097408
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097412
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097336
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097416
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097416
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2097420
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097412
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097420
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097424
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097428
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097428
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2097432
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097424
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097432
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097436
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097312
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097440
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097440
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2097444
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097436
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097444
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097448
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097452
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097452
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2097456
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097448
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097456
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097460
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097464
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097464
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2097468
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097460
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097468
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097472
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097476
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097476
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2097480
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097472
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097480
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097484
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097488
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097488
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2097492
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097484
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097492
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097496
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097500
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097500
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2097504
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097496
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097504
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097508
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097240
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097512
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097512
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2097516
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097508
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097516
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097520
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097524
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097524
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2097528
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097520
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097528
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097532
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097536
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097536
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2097540
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097532
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097540
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097544
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097548
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097548
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2097552
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097544
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097552
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097556
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097192
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097560
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097560
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2097564
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097556
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097564
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097568
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097572
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097572
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2097576
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097568
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097576
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097580
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097584
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097584
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2097588
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097580
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097588
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097592
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097596
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097596
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2097600
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097592
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097600
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097604
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097384
+  add t4, s0, t4
+  lw t2, 0(t4)
+  addi t0, s0, 0
+  li t4, 2097604
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  li t4, 2097152
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097612
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097612
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097616
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097616
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097620
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097620
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097624
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097624
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L54.while.cond
+L56.while.end:
+  li t4, 2097360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097628
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097628
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097632
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097632
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L51.while.cond
+L53.while.end:
+  li t4, 2097348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097636
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097636
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097640
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097640
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L48.while.cond
+L50.while.end:
+  li t4, 2097336
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097644
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097644
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097648
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097648
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L45.while.cond
+L47.while.end:
+  li t4, 2097324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097652
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097652
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097656
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097656
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L42.while.cond
+L44.while.end:
+  li t4, 2097312
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097660
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097660
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097664
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097664
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L39.while.cond
+L41.while.end:
+  li t4, 2097300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097668
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097668
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097672
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097672
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L36.while.cond
+L38.while.end:
+  li t4, 2097288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097676
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097676
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097680
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097680
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L33.while.cond
+L35.while.end:
+  li t4, 2097276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097684
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097684
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097688
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097688
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L30.while.cond
+L32.while.end:
+  li t4, 2097264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097692
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097692
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097696
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097696
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L27.while.cond
+L29.while.end:
+  li t4, 2097252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097700
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097700
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097704
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097704
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L24.while.cond
+L26.while.end:
+  li t4, 2097240
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097708
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097708
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097712
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097712
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L21.while.cond
+L23.while.end:
+  li t4, 2097228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097716
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097716
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097720
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097720
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L18.while.cond
+L20.while.end:
+  li t4, 2097216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097724
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097724
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097728
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097728
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L15.while.cond
+L17.while.end:
+  li t4, 2097204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097732
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097732
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097736
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097736
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L12.while.cond
+L14.while.end:
+  li t4, 2097192
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097740
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097740
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097744
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097744
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L9.while.cond
+L11.while.end:
+  li t4, 2097180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097748
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097748
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097752
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097752
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L6.while.cond
+L8.while.end:
+  li t4, 2097168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097756
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097756
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097760
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097760
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L3.while.cond
+L5.while.end:
+  li t4, 2097156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097764
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097764
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097768
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097768
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L0.while.cond
+L2.while.end:
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  li t4, 2097772
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  li t4, 2097776
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097772
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097776
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097780
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2097784
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097780
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097784
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097788
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2097792
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097788
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097792
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097796
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2097800
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097796
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097800
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097804
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2097808
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097804
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097808
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097812
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2097816
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097812
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097816
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097820
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2097824
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097820
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097824
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097828
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2097832
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097828
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097832
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097836
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2097840
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097836
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097840
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097844
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2097848
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097844
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097848
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097852
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2097856
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097852
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097856
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097860
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2097864
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097860
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097864
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097868
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2097872
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097868
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097872
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097876
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2097880
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097876
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097880
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097884
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2097888
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097884
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097888
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097892
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2097896
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097892
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097896
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097900
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2097904
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097900
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097904
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097908
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  li t4, 2097916
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2097920
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097916
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097920
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097924
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2097928
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097924
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097928
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097932
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2097936
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097932
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097936
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097940
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2097944
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097940
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097944
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097948
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2097952
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097948
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097952
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097956
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2097960
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097956
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097960
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097964
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2097968
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097964
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097968
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097972
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2097976
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097972
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097976
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097980
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2097984
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097980
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097984
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097988
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2097992
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097988
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097992
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097996
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098000
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097996
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098000
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098004
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098008
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098004
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098008
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098012
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098016
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098012
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098016
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098020
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098024
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098020
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098024
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098028
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098032
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098028
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098032
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098036
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098040
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098036
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098040
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098044
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2098052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2098056
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098052
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098056
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098060
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098064
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098060
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098064
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098072
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098068
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098072
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098080
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098076
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098080
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098084
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098088
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098084
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098088
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098092
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098096
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098092
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098096
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098100
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098104
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098100
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098104
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098108
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098112
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098108
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098112
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098120
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098116
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098120
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098124
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098128
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098124
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098128
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098132
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098136
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098132
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098136
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098140
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098144
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098140
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098144
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098148
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098152
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098160
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098160
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098164
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098164
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098168
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2098180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098184
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098184
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098188
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098192
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098196
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098200
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098196
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098200
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098208
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098208
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098212
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098212
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098216
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098220
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098224
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098220
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098224
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098232
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098232
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098236
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098236
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098240
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098244
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098248
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098244
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098248
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098256
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098256
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098260
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098260
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098264
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098268
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098272
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098268
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098272
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098280
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098280
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098284
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098284
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098288
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098304
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098304
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098308
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098308
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098312
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098320
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098316
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098320
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098328
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098328
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098332
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098332
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098336
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098340
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098344
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098340
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098344
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098352
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098352
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098356
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098356
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098360
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098364
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098368
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098364
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098368
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098376
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098376
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098380
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098384
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098380
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098384
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098388
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098392
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098388
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098392
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098396
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098400
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098396
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098400
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098404
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098412
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098416
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098412
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098416
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098420
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098424
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098420
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098424
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098428
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098432
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098428
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098432
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098436
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098440
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098436
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098440
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098444
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098448
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098444
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098448
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098452
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098456
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098452
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098456
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098460
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098464
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098460
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098464
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098468
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098472
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098468
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098472
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098476
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098480
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098476
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098480
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098484
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098488
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098484
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098488
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098492
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098496
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098492
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098496
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098500
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098504
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098500
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098504
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098508
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098516
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098520
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098516
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098520
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098524
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098528
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098524
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098528
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098532
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098536
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098532
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098536
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098540
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098544
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098540
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098544
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098548
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098552
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098548
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098552
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098556
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098560
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098556
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098560
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098564
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098568
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098564
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098568
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098572
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098576
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098572
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098576
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098580
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098584
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098580
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098584
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098588
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098592
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098588
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098592
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098596
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098600
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098596
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098600
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098604
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098612
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098616
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098612
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098616
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098620
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098624
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098620
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098624
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098628
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098632
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098628
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098632
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098636
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098640
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098636
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098640
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098644
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098648
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098644
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098648
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098652
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098656
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098652
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098656
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098660
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098664
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098660
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098664
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098668
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098672
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098668
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098672
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098676
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098680
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098676
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098680
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098684
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098688
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098684
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098688
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098692
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098700
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098704
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098700
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098704
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098708
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098712
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098708
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098712
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098716
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098720
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098716
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098720
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098724
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098728
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098724
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098728
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098732
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098736
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098732
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098736
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098740
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098744
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098740
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098744
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098748
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098752
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098748
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098752
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098756
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098760
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098756
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098760
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098764
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098768
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098764
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098768
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098772
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098780
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098784
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098780
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098784
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098788
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098792
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098788
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098792
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098796
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098800
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098796
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098800
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098804
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098808
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098804
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098808
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098812
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098816
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098812
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098816
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098820
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098824
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098820
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098824
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098828
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098832
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098828
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098832
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098836
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098840
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098836
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098840
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098844
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098852
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098856
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098852
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098856
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098860
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098864
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098860
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098864
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098868
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098872
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098868
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098872
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098876
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098880
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098876
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098880
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098884
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098888
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098884
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098888
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098892
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098896
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098892
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098896
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098900
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098904
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098900
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098904
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098908
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098916
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098920
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098916
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098920
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098924
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098928
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098924
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098928
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098932
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098936
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098932
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098936
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098940
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098944
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098940
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098944
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098948
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098952
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098948
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098952
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098956
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098960
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098956
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098960
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098964
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098972
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098976
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098972
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098976
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098980
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098984
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098980
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098984
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098988
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098992
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098988
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098992
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098996
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099000
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098996
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099000
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099004
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099008
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099004
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099008
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099012
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2099020
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2099024
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099020
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099024
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099028
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2099032
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099028
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099032
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099036
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099040
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099036
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099040
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099044
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099048
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099044
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099048
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2099060
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2099064
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099060
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099064
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099072
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099068
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099072
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099080
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099076
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099080
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099084
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2099092
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099096
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099092
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099096
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099100
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099104
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099100
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099104
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099108
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099120
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099116
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099120
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099124
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099132
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi sp, sp, -88
+  addi a0, s0, 0
+  li t4, 2097908
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a0, a0, t1
+  addi a1, s0, 0
+  li t4, 2098044
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a1, a1, t1
+  addi a2, s0, 0
+  li t4, 2098172
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a2, a2, t1
+  addi a3, s0, 0
+  li t4, 2098292
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a3, a3, t1
+  addi a4, s0, 0
+  li t4, 2098404
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a4, a4, t1
+  addi a5, s0, 0
+  li t4, 2098508
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a5, a5, t1
+  addi a6, s0, 0
+  li t4, 2098604
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a6, a6, t1
+  addi a7, s0, 0
+  li t4, 2098692
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a7, a7, t1
+  add t4, sp, zero
+  addi t0, s0, 0
+  li t4, 2098772
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 8
+  addi t0, s0, 0
+  li t4, 2098844
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 16
+  addi t0, s0, 0
+  li t4, 2098908
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  addi t0, s0, 0
+  li t4, 2098964
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 32
+  addi t0, s0, 0
+  li t4, 2099012
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 40
+  addi t0, s0, 0
+  li t4, 2099052
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  addi t0, s0, 0
+  li t4, 2099084
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 56
+  addi t0, s0, 0
+  li t4, 2099108
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  addi t0, s0, 0
+  li t4, 2099124
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 72
+  addi t0, s0, 0
+  li t4, 2099132
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 80
+  addi t0, s0, 0
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  call sum
+  addi sp, sp, 88
+  li t4, 2099144
+  add t4, s0, t4
+  sw a0, 0(t4)
+  li t4, 2099144
+  add t4, s0, t4
+  lw a0, 0(t4)
+  call putint
+  li t0, 0
+  li t1, 256
+  rem t0, t0, t1
+  li t4, 2099148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099148
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  add t0, t0, t1
+  li t4, 2099152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099152
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  rem t0, t0, t1
+  li t4, 2099156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099156
+  add t4, s0, t4
+  lw a0, 0(t4)
+  call putint
+  li a0, 10
+  call putch
+  li a0, 0
+  li t3, 2099168
+  add t3, s0, t3
+  ld ra, 0(t3)
+  li t3, 2099184
+  add sp, s0, t3
+  li t3, 2099176
+  add t3, s0, t3
+  ld s0, 0(t3)
+  ret
+.size main, .-main
+
diff --git a/30_many_dimensions.txt b/30_many_dimensions.txt
new file mode 100644
index 0000000..30454e0
--- /dev/null
+++ b/30_many_dimensions.txt
@@ -0,0 +1,5745 @@
+.text
+.global sum
+.type sum, @function
+sum:
+  addi sp, sp, -1760
+  sd ra, 1744(sp)
+  sd s0, 1752(sp)
+  mv s0, sp
+  sd a0, 0(s0)
+  sd a1, 8(s0)
+  sd a2, 16(s0)
+  sd a3, 24(s0)
+  sd a4, 32(s0)
+  sd a5, 40(s0)
+  sd a6, 48(s0)
+  sd a7, 56(s0)
+  ld t0, 1760(s0)
+  sd t0, 64(s0)
+  ld t0, 1768(s0)
+  sd t0, 72(s0)
+  ld t0, 1776(s0)
+  sd t0, 80(s0)
+  ld t0, 1784(s0)
+  sd t0, 88(s0)
+  ld t0, 1792(s0)
+  sd t0, 96(s0)
+  ld t0, 1800(s0)
+  sd t0, 104(s0)
+  ld t0, 1808(s0)
+  sd t0, 112(s0)
+  ld t0, 1816(s0)
+  sd t0, 120(s0)
+  ld t0, 1824(s0)
+  sd t0, 128(s0)
+  ld t0, 1832(s0)
+  sd t0, 136(s0)
+  ld t0, 1840(s0)
+  sd t0, 144(s0)
+  ld t0, 0(s0)
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 156(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 160(s0)
+  lw t0, 160(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 164(s0)
+  ld t0, 8(s0)
+  lw t1, 164(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 172(s0)
+  lw t0, 156(s0)
+  lw t1, 172(s0)
+  add t0, t0, t1
+  sw t0, 176(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 180(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 184(s0)
+  lw t0, 180(s0)
+  lw t1, 184(s0)
+  add t0, t0, t1
+  sw t0, 188(s0)
+  lw t0, 188(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 192(s0)
+  ld t0, 16(s0)
+  lw t1, 192(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 200(s0)
+  lw t0, 176(s0)
+  lw t1, 200(s0)
+  add t0, t0, t1
+  sw t0, 204(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 208(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 212(s0)
+  lw t0, 208(s0)
+  lw t1, 212(s0)
+  add t0, t0, t1
+  sw t0, 216(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 220(s0)
+  lw t0, 216(s0)
+  lw t1, 220(s0)
+  add t0, t0, t1
+  sw t0, 224(s0)
+  lw t0, 224(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 228(s0)
+  ld t0, 24(s0)
+  lw t1, 228(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 236(s0)
+  lw t0, 204(s0)
+  lw t1, 236(s0)
+  add t0, t0, t1
+  sw t0, 240(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 244(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 248(s0)
+  lw t0, 244(s0)
+  lw t1, 248(s0)
+  add t0, t0, t1
+  sw t0, 252(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 256(s0)
+  lw t0, 252(s0)
+  lw t1, 256(s0)
+  add t0, t0, t1
+  sw t0, 260(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 264(s0)
+  lw t0, 260(s0)
+  lw t1, 264(s0)
+  add t0, t0, t1
+  sw t0, 268(s0)
+  lw t0, 268(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 272(s0)
+  ld t0, 32(s0)
+  lw t1, 272(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 280(s0)
+  lw t0, 240(s0)
+  lw t1, 280(s0)
+  add t0, t0, t1
+  sw t0, 284(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 288(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 292(s0)
+  lw t0, 288(s0)
+  lw t1, 292(s0)
+  add t0, t0, t1
+  sw t0, 296(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 300(s0)
+  lw t0, 296(s0)
+  lw t1, 300(s0)
+  add t0, t0, t1
+  sw t0, 304(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 308(s0)
+  lw t0, 304(s0)
+  lw t1, 308(s0)
+  add t0, t0, t1
+  sw t0, 312(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 316(s0)
+  lw t0, 312(s0)
+  lw t1, 316(s0)
+  add t0, t0, t1
+  sw t0, 320(s0)
+  lw t0, 320(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 324(s0)
+  ld t0, 40(s0)
+  lw t1, 324(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 332(s0)
+  lw t0, 284(s0)
+  lw t1, 332(s0)
+  add t0, t0, t1
+  sw t0, 336(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 340(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 344(s0)
+  lw t0, 340(s0)
+  lw t1, 344(s0)
+  add t0, t0, t1
+  sw t0, 348(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 352(s0)
+  lw t0, 348(s0)
+  lw t1, 352(s0)
+  add t0, t0, t1
+  sw t0, 356(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 360(s0)
+  lw t0, 356(s0)
+  lw t1, 360(s0)
+  add t0, t0, t1
+  sw t0, 364(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 368(s0)
+  lw t0, 364(s0)
+  lw t1, 368(s0)
+  add t0, t0, t1
+  sw t0, 372(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 376(s0)
+  lw t0, 372(s0)
+  lw t1, 376(s0)
+  add t0, t0, t1
+  sw t0, 380(s0)
+  lw t0, 380(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 384(s0)
+  ld t0, 48(s0)
+  lw t1, 384(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 392(s0)
+  lw t0, 336(s0)
+  lw t1, 392(s0)
+  add t0, t0, t1
+  sw t0, 396(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 400(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 404(s0)
+  lw t0, 400(s0)
+  lw t1, 404(s0)
+  add t0, t0, t1
+  sw t0, 408(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 412(s0)
+  lw t0, 408(s0)
+  lw t1, 412(s0)
+  add t0, t0, t1
+  sw t0, 416(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 420(s0)
+  lw t0, 416(s0)
+  lw t1, 420(s0)
+  add t0, t0, t1
+  sw t0, 424(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 428(s0)
+  lw t0, 424(s0)
+  lw t1, 428(s0)
+  add t0, t0, t1
+  sw t0, 432(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 436(s0)
+  lw t0, 432(s0)
+  lw t1, 436(s0)
+  add t0, t0, t1
+  sw t0, 440(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 444(s0)
+  lw t0, 440(s0)
+  lw t1, 444(s0)
+  add t0, t0, t1
+  sw t0, 448(s0)
+  lw t0, 448(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 452(s0)
+  ld t0, 56(s0)
+  lw t1, 452(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 460(s0)
+  lw t0, 396(s0)
+  lw t1, 460(s0)
+  add t0, t0, t1
+  sw t0, 464(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 468(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 472(s0)
+  lw t0, 468(s0)
+  lw t1, 472(s0)
+  add t0, t0, t1
+  sw t0, 476(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 480(s0)
+  lw t0, 476(s0)
+  lw t1, 480(s0)
+  add t0, t0, t1
+  sw t0, 484(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 488(s0)
+  lw t0, 484(s0)
+  lw t1, 488(s0)
+  add t0, t0, t1
+  sw t0, 492(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 496(s0)
+  lw t0, 492(s0)
+  lw t1, 496(s0)
+  add t0, t0, t1
+  sw t0, 500(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 504(s0)
+  lw t0, 500(s0)
+  lw t1, 504(s0)
+  add t0, t0, t1
+  sw t0, 508(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 512(s0)
+  lw t0, 508(s0)
+  lw t1, 512(s0)
+  add t0, t0, t1
+  sw t0, 516(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 520(s0)
+  lw t0, 516(s0)
+  lw t1, 520(s0)
+  add t0, t0, t1
+  sw t0, 524(s0)
+  lw t0, 524(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 528(s0)
+  ld t0, 64(s0)
+  lw t1, 528(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 536(s0)
+  lw t0, 464(s0)
+  lw t1, 536(s0)
+  add t0, t0, t1
+  sw t0, 540(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 544(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 548(s0)
+  lw t0, 544(s0)
+  lw t1, 548(s0)
+  add t0, t0, t1
+  sw t0, 552(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 556(s0)
+  lw t0, 552(s0)
+  lw t1, 556(s0)
+  add t0, t0, t1
+  sw t0, 560(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 564(s0)
+  lw t0, 560(s0)
+  lw t1, 564(s0)
+  add t0, t0, t1
+  sw t0, 568(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 572(s0)
+  lw t0, 568(s0)
+  lw t1, 572(s0)
+  add t0, t0, t1
+  sw t0, 576(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 580(s0)
+  lw t0, 576(s0)
+  lw t1, 580(s0)
+  add t0, t0, t1
+  sw t0, 584(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 588(s0)
+  lw t0, 584(s0)
+  lw t1, 588(s0)
+  add t0, t0, t1
+  sw t0, 592(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 596(s0)
+  lw t0, 592(s0)
+  lw t1, 596(s0)
+  add t0, t0, t1
+  sw t0, 600(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 604(s0)
+  lw t0, 600(s0)
+  lw t1, 604(s0)
+  add t0, t0, t1
+  sw t0, 608(s0)
+  lw t0, 608(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 612(s0)
+  ld t0, 72(s0)
+  lw t1, 612(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 620(s0)
+  lw t0, 540(s0)
+  lw t1, 620(s0)
+  add t0, t0, t1
+  sw t0, 624(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 628(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 632(s0)
+  lw t0, 628(s0)
+  lw t1, 632(s0)
+  add t0, t0, t1
+  sw t0, 636(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 640(s0)
+  lw t0, 636(s0)
+  lw t1, 640(s0)
+  add t0, t0, t1
+  sw t0, 644(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 648(s0)
+  lw t0, 644(s0)
+  lw t1, 648(s0)
+  add t0, t0, t1
+  sw t0, 652(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 656(s0)
+  lw t0, 652(s0)
+  lw t1, 656(s0)
+  add t0, t0, t1
+  sw t0, 660(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 664(s0)
+  lw t0, 660(s0)
+  lw t1, 664(s0)
+  add t0, t0, t1
+  sw t0, 668(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 672(s0)
+  lw t0, 668(s0)
+  lw t1, 672(s0)
+  add t0, t0, t1
+  sw t0, 676(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 680(s0)
+  lw t0, 676(s0)
+  lw t1, 680(s0)
+  add t0, t0, t1
+  sw t0, 684(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 688(s0)
+  lw t0, 684(s0)
+  lw t1, 688(s0)
+  add t0, t0, t1
+  sw t0, 692(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 696(s0)
+  lw t0, 692(s0)
+  lw t1, 696(s0)
+  add t0, t0, t1
+  sw t0, 700(s0)
+  lw t0, 700(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 704(s0)
+  ld t0, 80(s0)
+  lw t1, 704(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 712(s0)
+  lw t0, 624(s0)
+  lw t1, 712(s0)
+  add t0, t0, t1
+  sw t0, 716(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 720(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 724(s0)
+  lw t0, 720(s0)
+  lw t1, 724(s0)
+  add t0, t0, t1
+  sw t0, 728(s0)
+  li t0, 1
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 732(s0)
+  lw t0, 728(s0)
+  lw t1, 732(s0)
+  add t0, t0, t1
+  sw t0, 736(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 740(s0)
+  lw t0, 736(s0)
+  lw t1, 740(s0)
+  add t0, t0, t1
+  sw t0, 744(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 748(s0)
+  lw t0, 744(s0)
+  lw t1, 748(s0)
+  add t0, t0, t1
+  sw t0, 752(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 756(s0)
+  lw t0, 752(s0)
+  lw t1, 756(s0)
+  add t0, t0, t1
+  sw t0, 760(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 764(s0)
+  lw t0, 760(s0)
+  lw t1, 764(s0)
+  add t0, t0, t1
+  sw t0, 768(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 772(s0)
+  lw t0, 768(s0)
+  lw t1, 772(s0)
+  add t0, t0, t1
+  sw t0, 776(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 780(s0)
+  lw t0, 776(s0)
+  lw t1, 780(s0)
+  add t0, t0, t1
+  sw t0, 784(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 788(s0)
+  lw t0, 784(s0)
+  lw t1, 788(s0)
+  add t0, t0, t1
+  sw t0, 792(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 796(s0)
+  lw t0, 792(s0)
+  lw t1, 796(s0)
+  add t0, t0, t1
+  sw t0, 800(s0)
+  lw t0, 800(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 804(s0)
+  ld t0, 88(s0)
+  lw t1, 804(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 812(s0)
+  lw t0, 716(s0)
+  lw t1, 812(s0)
+  add t0, t0, t1
+  sw t0, 816(s0)
+  li t0, 1
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 820(s0)
+  li t0, 1
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 824(s0)
+  lw t0, 820(s0)
+  lw t1, 824(s0)
+  add t0, t0, t1
+  sw t0, 828(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 832(s0)
+  lw t0, 828(s0)
+  lw t1, 832(s0)
+  add t0, t0, t1
+  sw t0, 836(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 840(s0)
+  lw t0, 836(s0)
+  lw t1, 840(s0)
+  add t0, t0, t1
+  sw t0, 844(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 848(s0)
+  lw t0, 844(s0)
+  lw t1, 848(s0)
+  add t0, t0, t1
+  sw t0, 852(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 856(s0)
+  lw t0, 852(s0)
+  lw t1, 856(s0)
+  add t0, t0, t1
+  sw t0, 860(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 864(s0)
+  lw t0, 860(s0)
+  lw t1, 864(s0)
+  add t0, t0, t1
+  sw t0, 868(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 872(s0)
+  lw t0, 868(s0)
+  lw t1, 872(s0)
+  add t0, t0, t1
+  sw t0, 876(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 880(s0)
+  lw t0, 876(s0)
+  lw t1, 880(s0)
+  add t0, t0, t1
+  sw t0, 884(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 888(s0)
+  lw t0, 884(s0)
+  lw t1, 888(s0)
+  add t0, t0, t1
+  sw t0, 892(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 896(s0)
+  lw t0, 892(s0)
+  lw t1, 896(s0)
+  add t0, t0, t1
+  sw t0, 900(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 904(s0)
+  lw t0, 900(s0)
+  lw t1, 904(s0)
+  add t0, t0, t1
+  sw t0, 908(s0)
+  lw t0, 908(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 912(s0)
+  ld t0, 96(s0)
+  lw t1, 912(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 920(s0)
+  lw t0, 816(s0)
+  lw t1, 920(s0)
+  add t0, t0, t1
+  sw t0, 924(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 928(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 932(s0)
+  lw t0, 928(s0)
+  lw t1, 932(s0)
+  add t0, t0, t1
+  sw t0, 936(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 940(s0)
+  lw t0, 936(s0)
+  lw t1, 940(s0)
+  add t0, t0, t1
+  sw t0, 944(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 948(s0)
+  lw t0, 944(s0)
+  lw t1, 948(s0)
+  add t0, t0, t1
+  sw t0, 952(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 956(s0)
+  lw t0, 952(s0)
+  lw t1, 956(s0)
+  add t0, t0, t1
+  sw t0, 960(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 964(s0)
+  lw t0, 960(s0)
+  lw t1, 964(s0)
+  add t0, t0, t1
+  sw t0, 968(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 972(s0)
+  lw t0, 968(s0)
+  lw t1, 972(s0)
+  add t0, t0, t1
+  sw t0, 976(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 980(s0)
+  lw t0, 976(s0)
+  lw t1, 980(s0)
+  add t0, t0, t1
+  sw t0, 984(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 988(s0)
+  lw t0, 984(s0)
+  lw t1, 988(s0)
+  add t0, t0, t1
+  sw t0, 992(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 996(s0)
+  lw t0, 992(s0)
+  lw t1, 996(s0)
+  add t0, t0, t1
+  sw t0, 1000(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1004(s0)
+  lw t0, 1000(s0)
+  lw t1, 1004(s0)
+  add t0, t0, t1
+  sw t0, 1008(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1012(s0)
+  lw t0, 1008(s0)
+  lw t1, 1012(s0)
+  add t0, t0, t1
+  sw t0, 1016(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1020(s0)
+  lw t0, 1016(s0)
+  lw t1, 1020(s0)
+  add t0, t0, t1
+  sw t0, 1024(s0)
+  lw t0, 1024(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1028(s0)
+  ld t0, 104(s0)
+  lw t1, 1028(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1036(s0)
+  lw t0, 924(s0)
+  lw t1, 1036(s0)
+  add t0, t0, t1
+  sw t0, 1040(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1044(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1048(s0)
+  lw t0, 1044(s0)
+  lw t1, 1048(s0)
+  add t0, t0, t1
+  sw t0, 1052(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1056(s0)
+  lw t0, 1052(s0)
+  lw t1, 1056(s0)
+  add t0, t0, t1
+  sw t0, 1060(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1064(s0)
+  lw t0, 1060(s0)
+  lw t1, 1064(s0)
+  add t0, t0, t1
+  sw t0, 1068(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1072(s0)
+  lw t0, 1068(s0)
+  lw t1, 1072(s0)
+  add t0, t0, t1
+  sw t0, 1076(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1080(s0)
+  lw t0, 1076(s0)
+  lw t1, 1080(s0)
+  add t0, t0, t1
+  sw t0, 1084(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1088(s0)
+  lw t0, 1084(s0)
+  lw t1, 1088(s0)
+  add t0, t0, t1
+  sw t0, 1092(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1096(s0)
+  lw t0, 1092(s0)
+  lw t1, 1096(s0)
+  add t0, t0, t1
+  sw t0, 1100(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1104(s0)
+  lw t0, 1100(s0)
+  lw t1, 1104(s0)
+  add t0, t0, t1
+  sw t0, 1108(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1112(s0)
+  lw t0, 1108(s0)
+  lw t1, 1112(s0)
+  add t0, t0, t1
+  sw t0, 1116(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1120(s0)
+  lw t0, 1116(s0)
+  lw t1, 1120(s0)
+  add t0, t0, t1
+  sw t0, 1124(s0)
+  li t0, 1
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1128(s0)
+  lw t0, 1124(s0)
+  lw t1, 1128(s0)
+  add t0, t0, t1
+  sw t0, 1132(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1136(s0)
+  lw t0, 1132(s0)
+  lw t1, 1136(s0)
+  add t0, t0, t1
+  sw t0, 1140(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1144(s0)
+  lw t0, 1140(s0)
+  lw t1, 1144(s0)
+  add t0, t0, t1
+  sw t0, 1148(s0)
+  lw t0, 1148(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1152(s0)
+  ld t0, 112(s0)
+  lw t1, 1152(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1160(s0)
+  lw t0, 1040(s0)
+  lw t1, 1160(s0)
+  add t0, t0, t1
+  sw t0, 1164(s0)
+  li t0, 1
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1168(s0)
+  li t0, 1
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1172(s0)
+  lw t0, 1168(s0)
+  lw t1, 1172(s0)
+  add t0, t0, t1
+  sw t0, 1176(s0)
+  li t0, 1
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1180(s0)
+  lw t0, 1176(s0)
+  lw t1, 1180(s0)
+  add t0, t0, t1
+  sw t0, 1184(s0)
+  li t0, 1
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1188(s0)
+  lw t0, 1184(s0)
+  lw t1, 1188(s0)
+  add t0, t0, t1
+  sw t0, 1192(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1196(s0)
+  lw t0, 1192(s0)
+  lw t1, 1196(s0)
+  add t0, t0, t1
+  sw t0, 1200(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1204(s0)
+  lw t0, 1200(s0)
+  lw t1, 1204(s0)
+  add t0, t0, t1
+  sw t0, 1208(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1212(s0)
+  lw t0, 1208(s0)
+  lw t1, 1212(s0)
+  add t0, t0, t1
+  sw t0, 1216(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1220(s0)
+  lw t0, 1216(s0)
+  lw t1, 1220(s0)
+  add t0, t0, t1
+  sw t0, 1224(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1228(s0)
+  lw t0, 1224(s0)
+  lw t1, 1228(s0)
+  add t0, t0, t1
+  sw t0, 1232(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1236(s0)
+  lw t0, 1232(s0)
+  lw t1, 1236(s0)
+  add t0, t0, t1
+  sw t0, 1240(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1244(s0)
+  lw t0, 1240(s0)
+  lw t1, 1244(s0)
+  add t0, t0, t1
+  sw t0, 1248(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1252(s0)
+  lw t0, 1248(s0)
+  lw t1, 1252(s0)
+  add t0, t0, t1
+  sw t0, 1256(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1260(s0)
+  lw t0, 1256(s0)
+  lw t1, 1260(s0)
+  add t0, t0, t1
+  sw t0, 1264(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1268(s0)
+  lw t0, 1264(s0)
+  lw t1, 1268(s0)
+  add t0, t0, t1
+  sw t0, 1272(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1276(s0)
+  lw t0, 1272(s0)
+  lw t1, 1276(s0)
+  add t0, t0, t1
+  sw t0, 1280(s0)
+  lw t0, 1280(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 1284(s0)
+  ld t0, 120(s0)
+  lw t1, 1284(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1292(s0)
+  lw t0, 1164(s0)
+  lw t1, 1292(s0)
+  add t0, t0, t1
+  sw t0, 1296(s0)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  sw t0, 1300(s0)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1304(s0)
+  lw t0, 1300(s0)
+  lw t1, 1304(s0)
+  add t0, t0, t1
+  sw t0, 1308(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1312(s0)
+  lw t0, 1308(s0)
+  lw t1, 1312(s0)
+  add t0, t0, t1
+  sw t0, 1316(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1320(s0)
+  lw t0, 1316(s0)
+  lw t1, 1320(s0)
+  add t0, t0, t1
+  sw t0, 1324(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1328(s0)
+  lw t0, 1324(s0)
+  lw t1, 1328(s0)
+  add t0, t0, t1
+  sw t0, 1332(s0)
+  li t0, 1
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1336(s0)
+  lw t0, 1332(s0)
+  lw t1, 1336(s0)
+  add t0, t0, t1
+  sw t0, 1340(s0)
+  li t0, 1
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1344(s0)
+  lw t0, 1340(s0)
+  lw t1, 1344(s0)
+  add t0, t0, t1
+  sw t0, 1348(s0)
+  li t0, 1
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1352(s0)
+  lw t0, 1348(s0)
+  lw t1, 1352(s0)
+  add t0, t0, t1
+  sw t0, 1356(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1360(s0)
+  lw t0, 1356(s0)
+  lw t1, 1360(s0)
+  add t0, t0, t1
+  sw t0, 1364(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1368(s0)
+  lw t0, 1364(s0)
+  lw t1, 1368(s0)
+  add t0, t0, t1
+  sw t0, 1372(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1376(s0)
+  lw t0, 1372(s0)
+  lw t1, 1376(s0)
+  add t0, t0, t1
+  sw t0, 1380(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1384(s0)
+  lw t0, 1380(s0)
+  lw t1, 1384(s0)
+  add t0, t0, t1
+  sw t0, 1388(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1392(s0)
+  lw t0, 1388(s0)
+  lw t1, 1392(s0)
+  add t0, t0, t1
+  sw t0, 1396(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1400(s0)
+  lw t0, 1396(s0)
+  lw t1, 1400(s0)
+  add t0, t0, t1
+  sw t0, 1404(s0)
+  li t0, 1
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1408(s0)
+  lw t0, 1404(s0)
+  lw t1, 1408(s0)
+  add t0, t0, t1
+  sw t0, 1412(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1416(s0)
+  lw t0, 1412(s0)
+  lw t1, 1416(s0)
+  add t0, t0, t1
+  sw t0, 1420(s0)
+  lw t0, 1420(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1424(s0)
+  ld t0, 128(s0)
+  lw t1, 1424(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1432(s0)
+  lw t0, 1296(s0)
+  lw t1, 1432(s0)
+  add t0, t0, t1
+  sw t0, 1436(s0)
+  li t0, 1
+  li t1, 131072
+  mul t0, t0, t1
+  sw t0, 1440(s0)
+  li t0, 1
+  li t1, 65536
+  mul t0, t0, t1
+  sw t0, 1444(s0)
+  lw t0, 1440(s0)
+  lw t1, 1444(s0)
+  add t0, t0, t1
+  sw t0, 1448(s0)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1452(s0)
+  lw t0, 1448(s0)
+  lw t1, 1452(s0)
+  add t0, t0, t1
+  sw t0, 1456(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1460(s0)
+  lw t0, 1456(s0)
+  lw t1, 1460(s0)
+  add t0, t0, t1
+  sw t0, 1464(s0)
+  li t0, 1
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1468(s0)
+  lw t0, 1464(s0)
+  lw t1, 1468(s0)
+  add t0, t0, t1
+  sw t0, 1472(s0)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1476(s0)
+  lw t0, 1472(s0)
+  lw t1, 1476(s0)
+  add t0, t0, t1
+  sw t0, 1480(s0)
+  li t0, 1
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1484(s0)
+  lw t0, 1480(s0)
+  lw t1, 1484(s0)
+  add t0, t0, t1
+  sw t0, 1488(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1492(s0)
+  lw t0, 1488(s0)
+  lw t1, 1492(s0)
+  add t0, t0, t1
+  sw t0, 1496(s0)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1500(s0)
+  lw t0, 1496(s0)
+  lw t1, 1500(s0)
+  add t0, t0, t1
+  sw t0, 1504(s0)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1508(s0)
+  lw t0, 1504(s0)
+  lw t1, 1508(s0)
+  add t0, t0, t1
+  sw t0, 1512(s0)
+  li t0, 1
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1516(s0)
+  lw t0, 1512(s0)
+  lw t1, 1516(s0)
+  add t0, t0, t1
+  sw t0, 1520(s0)
+  li t0, 1
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1524(s0)
+  lw t0, 1520(s0)
+  lw t1, 1524(s0)
+  add t0, t0, t1
+  sw t0, 1528(s0)
+  li t0, 1
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1532(s0)
+  lw t0, 1528(s0)
+  lw t1, 1532(s0)
+  add t0, t0, t1
+  sw t0, 1536(s0)
+  li t0, 1
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1540(s0)
+  lw t0, 1536(s0)
+  lw t1, 1540(s0)
+  add t0, t0, t1
+  sw t0, 1544(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1548(s0)
+  lw t0, 1544(s0)
+  lw t1, 1548(s0)
+  add t0, t0, t1
+  sw t0, 1552(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1556(s0)
+  lw t0, 1552(s0)
+  lw t1, 1556(s0)
+  add t0, t0, t1
+  sw t0, 1560(s0)
+  li t0, 1
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1564(s0)
+  lw t0, 1560(s0)
+  lw t1, 1564(s0)
+  add t0, t0, t1
+  sw t0, 1568(s0)
+  lw t0, 1568(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1572(s0)
+  ld t0, 136(s0)
+  lw t1, 1572(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1580(s0)
+  lw t0, 1436(s0)
+  lw t1, 1580(s0)
+  add t0, t0, t1
+  sw t0, 1584(s0)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  sw t0, 1588(s0)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  sw t0, 1592(s0)
+  lw t0, 1588(s0)
+  lw t1, 1592(s0)
+  add t0, t0, t1
+  sw t0, 1596(s0)
+  li t0, 1
+  li t1, 65536
+  mul t0, t0, t1
+  sw t0, 1600(s0)
+  lw t0, 1596(s0)
+  lw t1, 1600(s0)
+  add t0, t0, t1
+  sw t0, 1604(s0)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  sw t0, 1608(s0)
+  lw t0, 1604(s0)
+  lw t1, 1608(s0)
+  add t0, t0, t1
+  sw t0, 1612(s0)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  sw t0, 1616(s0)
+  lw t0, 1612(s0)
+  lw t1, 1616(s0)
+  add t0, t0, t1
+  sw t0, 1620(s0)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  sw t0, 1624(s0)
+  lw t0, 1620(s0)
+  lw t1, 1624(s0)
+  add t0, t0, t1
+  sw t0, 1628(s0)
+  li t0, 1
+  li t1, 4096
+  mul t0, t0, t1
+  sw t0, 1632(s0)
+  lw t0, 1628(s0)
+  lw t1, 1632(s0)
+  add t0, t0, t1
+  sw t0, 1636(s0)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  sw t0, 1640(s0)
+  lw t0, 1636(s0)
+  lw t1, 1640(s0)
+  add t0, t0, t1
+  sw t0, 1644(s0)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  sw t0, 1648(s0)
+  lw t0, 1644(s0)
+  lw t1, 1648(s0)
+  add t0, t0, t1
+  sw t0, 1652(s0)
+  li t0, 1
+  li t1, 512
+  mul t0, t0, t1
+  sw t0, 1656(s0)
+  lw t0, 1652(s0)
+  lw t1, 1656(s0)
+  add t0, t0, t1
+  sw t0, 1660(s0)
+  li t0, 1
+  li t1, 256
+  mul t0, t0, t1
+  sw t0, 1664(s0)
+  lw t0, 1660(s0)
+  lw t1, 1664(s0)
+  add t0, t0, t1
+  sw t0, 1668(s0)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  sw t0, 1672(s0)
+  lw t0, 1668(s0)
+  lw t1, 1672(s0)
+  add t0, t0, t1
+  sw t0, 1676(s0)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  sw t0, 1680(s0)
+  lw t0, 1676(s0)
+  lw t1, 1680(s0)
+  add t0, t0, t1
+  sw t0, 1684(s0)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  sw t0, 1688(s0)
+  lw t0, 1684(s0)
+  lw t1, 1688(s0)
+  add t0, t0, t1
+  sw t0, 1692(s0)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  sw t0, 1696(s0)
+  lw t0, 1692(s0)
+  lw t1, 1696(s0)
+  add t0, t0, t1
+  sw t0, 1700(s0)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  sw t0, 1704(s0)
+  lw t0, 1700(s0)
+  lw t1, 1704(s0)
+  add t0, t0, t1
+  sw t0, 1708(s0)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  sw t0, 1712(s0)
+  lw t0, 1708(s0)
+  lw t1, 1712(s0)
+  add t0, t0, t1
+  sw t0, 1716(s0)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  sw t0, 1720(s0)
+  lw t0, 1716(s0)
+  lw t1, 1720(s0)
+  add t0, t0, t1
+  sw t0, 1724(s0)
+  lw t0, 1724(s0)
+  li t1, 0
+  add t0, t0, t1
+  sw t0, 1728(s0)
+  ld t0, 144(s0)
+  lw t1, 1728(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1736(s0)
+  lw t0, 1584(s0)
+  lw t1, 1736(s0)
+  add t0, t0, t1
+  sw t0, 1740(s0)
+  lw a0, 1740(s0)
+  ld ra, 1744(s0)
+  addi sp, s0, 1760
+  ld s0, 1752(s0)
+  ret
+.size sum, .-sum
+
+.global main
+.type main, @function
+main:
+  li t4, -2099184
+  add sp, sp, t4
+  li t4, 2099168
+  add t4, sp, t4
+  sd ra, 0(t4)
+  li t4, 2099176
+  add t4, sp, t4
+  sd s0, 0(t4)
+  mv s0, sp
+  addi a0, s0, 0
+  li a1, 0
+  li a2, 2097152
+  call memset
+  li t0, 0
+  li t4, 2097152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t4, 2097156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L0.while.cond
+L0.while.cond:
+  li t4, 2097156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097160
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097160
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097164
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097164
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L1.while.body
+  j L2.while.end
+L1.while.body:
+  li t0, 0
+  li t4, 2097168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L3.while.cond
+L3.while.cond:
+  li t4, 2097168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097172
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097176
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097176
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L4.while.body
+  j L5.while.end
+L4.while.body:
+  li t0, 0
+  li t4, 2097180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L6.while.cond
+L6.while.cond:
+  li t4, 2097180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097184
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097184
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097188
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L7.while.body
+  j L8.while.end
+L7.while.body:
+  li t0, 0
+  li t4, 2097192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L9.while.cond
+L9.while.cond:
+  li t4, 2097192
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097196
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097196
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097200
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097200
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L10.while.body
+  j L11.while.end
+L10.while.body:
+  li t0, 0
+  li t4, 2097204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L12.while.cond
+L12.while.cond:
+  li t4, 2097204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097208
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097208
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097212
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097212
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L13.while.body
+  j L14.while.end
+L13.while.body:
+  li t0, 0
+  li t4, 2097216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L15.while.cond
+L15.while.cond:
+  li t4, 2097216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097220
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097220
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097224
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097224
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L16.while.body
+  j L17.while.end
+L16.while.body:
+  li t0, 0
+  li t4, 2097228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L18.while.cond
+L18.while.cond:
+  li t4, 2097228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097232
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097232
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097236
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097236
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L19.while.body
+  j L20.while.end
+L19.while.body:
+  li t0, 0
+  li t4, 2097240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L21.while.cond
+L21.while.cond:
+  li t4, 2097240
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097244
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097244
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097248
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097248
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L22.while.body
+  j L23.while.end
+L22.while.body:
+  li t0, 0
+  li t4, 2097252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L24.while.cond
+L24.while.cond:
+  li t4, 2097252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097256
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097256
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097260
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097260
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L25.while.body
+  j L26.while.end
+L25.while.body:
+  li t0, 0
+  li t4, 2097264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L27.while.cond
+L27.while.cond:
+  li t4, 2097264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097268
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097268
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097272
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097272
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L28.while.body
+  j L29.while.end
+L28.while.body:
+  li t0, 0
+  li t4, 2097276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L30.while.cond
+L30.while.cond:
+  li t4, 2097276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097280
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097280
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097284
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097284
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L31.while.body
+  j L32.while.end
+L31.while.body:
+  li t0, 0
+  li t4, 2097288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L33.while.cond
+L33.while.cond:
+  li t4, 2097288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097292
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097296
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097296
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L34.while.body
+  j L35.while.end
+L34.while.body:
+  li t0, 0
+  li t4, 2097300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L36.while.cond
+L36.while.cond:
+  li t4, 2097300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097304
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097304
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097308
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097308
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L37.while.body
+  j L38.while.end
+L37.while.body:
+  li t0, 0
+  li t4, 2097312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L39.while.cond
+L39.while.cond:
+  li t4, 2097312
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097316
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097320
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097320
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L40.while.body
+  j L41.while.end
+L40.while.body:
+  li t0, 0
+  li t4, 2097324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L42.while.cond
+L42.while.cond:
+  li t4, 2097324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097328
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097328
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097332
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097332
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L43.while.body
+  j L44.while.end
+L43.while.body:
+  li t0, 0
+  li t4, 2097336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L45.while.cond
+L45.while.cond:
+  li t4, 2097336
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097340
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097340
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097344
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097344
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L46.while.body
+  j L47.while.end
+L46.while.body:
+  li t0, 0
+  li t4, 2097348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L48.while.cond
+L48.while.cond:
+  li t4, 2097348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097352
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097352
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097356
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097356
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L49.while.body
+  j L50.while.end
+L49.while.body:
+  li t0, 0
+  li t4, 2097360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L51.while.cond
+L51.while.cond:
+  li t4, 2097360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097364
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097364
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097368
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097368
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L52.while.body
+  j L53.while.end
+L52.while.body:
+  li t0, 0
+  li t4, 2097372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L54.while.cond
+L54.while.cond:
+  li t4, 2097372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097376
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097376
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  slt t0, t0, t1
+  li t4, 2097380
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097380
+  add t4, s0, t4
+  lw t0, 0(t4)
+  bnez t0, L55.while.body
+  j L56.while.end
+L55.while.body:
+  li t4, 2097152
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097384
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097388
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097388
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2097392
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097396
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097396
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2097400
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097392
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097400
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097404
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097408
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097408
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2097412
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097404
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097412
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097416
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097192
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097420
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097420
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2097424
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097416
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097424
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097428
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097432
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097432
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2097436
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097428
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097436
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097440
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097444
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097444
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2097448
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097440
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097448
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097452
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097456
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097456
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2097460
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097452
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097460
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097464
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097240
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097468
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097468
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2097472
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097464
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097472
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097476
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097480
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097480
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2097484
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097476
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097484
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097488
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097492
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097492
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2097496
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097488
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097496
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097500
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097504
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097504
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2097508
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097500
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097508
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097512
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097516
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097516
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2097520
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097512
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097520
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097524
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097528
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097528
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2097532
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097524
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097532
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097536
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097312
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097540
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097540
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2097544
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097536
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097544
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097548
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097552
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097552
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2097556
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097548
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097556
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097560
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097336
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097564
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097564
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2097568
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097560
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097568
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097572
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097576
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097576
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 4
+  mul t0, t0, t1
+  li t4, 2097580
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097572
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097580
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097584
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097588
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097588
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 2
+  mul t0, t0, t1
+  li t4, 2097592
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097584
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097592
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097596
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097600
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097596
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097600
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097604
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097384
+  add t4, s0, t4
+  lw t2, 0(t4)
+  addi t0, s0, 0
+  li t4, 2097604
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  li t4, 2097152
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097612
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097612
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097616
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097616
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097620
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097620
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097624
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097624
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L54.while.cond
+L56.while.end:
+  li t4, 2097360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097628
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097628
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097632
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097632
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L51.while.cond
+L53.while.end:
+  li t4, 2097348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097636
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097636
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097640
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097640
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L48.while.cond
+L50.while.end:
+  li t4, 2097336
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097644
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097644
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097648
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097648
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L45.while.cond
+L47.while.end:
+  li t4, 2097324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097652
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097652
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097656
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097656
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L42.while.cond
+L44.while.end:
+  li t4, 2097312
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097660
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097660
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097664
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097664
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L39.while.cond
+L41.while.end:
+  li t4, 2097300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097668
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097668
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097672
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097672
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L36.while.cond
+L38.while.end:
+  li t4, 2097288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097676
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097676
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097680
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097680
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L33.while.cond
+L35.while.end:
+  li t4, 2097276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097684
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097684
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097688
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097688
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L30.while.cond
+L32.while.end:
+  li t4, 2097264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097692
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097692
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097696
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097696
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L27.while.cond
+L29.while.end:
+  li t4, 2097252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097700
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097700
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097704
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097704
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L24.while.cond
+L26.while.end:
+  li t4, 2097240
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097708
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097708
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097712
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097712
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L21.while.cond
+L23.while.end:
+  li t4, 2097228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097716
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097716
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097720
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097720
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L18.while.cond
+L20.while.end:
+  li t4, 2097216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097724
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097724
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097728
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097728
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L15.while.cond
+L17.while.end:
+  li t4, 2097204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097732
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097732
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097736
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097736
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L12.while.cond
+L14.while.end:
+  li t4, 2097192
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097740
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097740
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097744
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097744
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L9.while.cond
+L11.while.end:
+  li t4, 2097180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097748
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097748
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097752
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097752
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L6.while.cond
+L8.while.end:
+  li t4, 2097168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097756
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097756
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097760
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097760
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L3.while.cond
+L5.while.end:
+  li t4, 2097156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097764
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097764
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 1
+  add t0, t0, t1
+  li t4, 2097768
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097768
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  j L0.while.cond
+L2.while.end:
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2097772
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2097776
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097772
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097776
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097780
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2097784
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097780
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097784
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097788
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2097792
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097788
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097792
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097796
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2097800
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097796
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097800
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097804
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2097808
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097804
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097808
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097812
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2097816
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097812
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097816
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097820
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2097824
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097820
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097824
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097828
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2097832
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097828
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097832
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097836
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2097840
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097836
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097840
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097844
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2097848
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097844
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097848
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097852
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2097856
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097852
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097856
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097860
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2097864
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097860
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097864
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097868
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2097872
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097868
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097872
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097876
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2097880
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097876
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097880
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097884
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2097888
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097884
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097888
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097892
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  li t4, 2097896
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097892
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097896
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097900
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2
+  mul t0, t0, t1
+  li t4, 2097904
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097900
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097904
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097908
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2097916
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2097920
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097916
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097920
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097924
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2097928
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097924
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097928
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097932
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2097936
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097932
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097936
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097940
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2097944
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097940
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097944
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097948
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2097952
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097948
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097952
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097956
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2097960
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097956
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097960
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097964
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2097968
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097964
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097968
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097972
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2097976
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097972
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097976
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097980
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2097984
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097980
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097984
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097988
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2097992
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097988
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2097992
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2097996
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098000
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2097996
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098000
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098004
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098008
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098004
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098008
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098012
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098016
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098012
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098016
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098020
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2098024
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098020
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098024
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098028
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2098032
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098028
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098032
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098036
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4
+  mul t0, t0, t1
+  li t4, 2098040
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098036
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098040
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098044
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098056
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098052
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098056
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098060
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098064
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098060
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098064
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098072
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098068
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098072
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098080
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098076
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098080
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098084
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098088
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098084
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098088
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098092
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098096
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098092
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098096
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098100
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098104
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098100
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098104
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098108
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098112
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098108
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098112
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098120
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098116
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098120
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098124
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098128
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098124
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098128
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098132
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098136
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098132
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098136
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098140
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098144
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098140
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098144
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098148
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098152
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2098160
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098156
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098160
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098164
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8
+  mul t0, t0, t1
+  li t4, 2098168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098164
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098168
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098184
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098184
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098188
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098192
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098196
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098200
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098196
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098200
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098208
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098208
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098212
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098212
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098216
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098220
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098224
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098220
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098224
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098232
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098232
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098236
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098236
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098240
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098244
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098248
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098244
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098248
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098256
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098252
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098256
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098260
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098260
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098264
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098268
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098272
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098268
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098272
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098280
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098280
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098284
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16
+  mul t0, t0, t1
+  li t4, 2098288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098284
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098288
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098304
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098300
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098304
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098308
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098308
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098312
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098320
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098316
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098320
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098328
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098324
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098328
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098332
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098332
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098336
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098340
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098344
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098340
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098344
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098352
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098352
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098356
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098356
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098360
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098364
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098368
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098364
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098368
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098376
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098372
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098376
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098380
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098384
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098380
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098384
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098388
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098392
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098388
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098392
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098396
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32
+  mul t0, t0, t1
+  li t4, 2098400
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098396
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098400
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098404
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098412
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098416
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098412
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098416
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098420
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098424
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098420
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098424
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098428
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098432
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098428
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098432
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098436
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098440
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098436
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098440
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098444
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098448
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098444
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098448
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098452
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098456
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098452
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098456
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098460
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098464
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098460
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098464
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098468
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098472
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098468
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098472
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098476
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098480
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098476
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098480
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098484
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098488
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098484
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098488
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098492
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098496
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098492
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098496
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098500
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 64
+  mul t0, t0, t1
+  li t4, 2098504
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098500
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098504
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098508
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098516
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098520
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098516
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098520
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098524
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098528
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098524
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098528
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098532
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098536
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098532
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098536
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098540
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098544
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098540
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098544
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098548
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098552
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098548
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098552
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098556
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098560
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098556
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098560
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098564
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098568
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098564
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098568
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098572
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098576
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098572
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098576
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098580
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098584
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098580
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098584
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098588
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098592
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098588
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098592
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098596
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 128
+  mul t0, t0, t1
+  li t4, 2098600
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098596
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098600
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098604
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098612
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098616
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098612
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098616
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098620
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098624
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098620
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098624
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098628
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098632
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098628
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098632
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098636
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098640
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098636
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098640
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098644
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098648
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098644
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098648
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098652
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098656
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098652
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098656
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098660
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098664
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098660
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098664
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098668
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098672
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098668
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098672
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098676
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098680
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098676
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098680
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098684
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 256
+  mul t0, t0, t1
+  li t4, 2098688
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098684
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098688
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098692
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098700
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098704
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098700
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098704
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098708
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098712
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098708
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098712
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098716
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098720
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098716
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098720
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098724
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098728
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098724
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098728
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098732
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098736
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098732
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098736
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098740
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098744
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098740
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098744
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098748
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098752
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098748
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098752
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098756
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098760
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098756
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098760
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098764
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 512
+  mul t0, t0, t1
+  li t4, 2098768
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098764
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098768
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098772
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098780
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098784
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098780
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098784
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098788
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098792
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098788
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098792
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098796
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098800
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098796
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098800
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098804
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098808
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098804
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098808
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098812
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098816
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098812
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098816
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098820
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098824
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098820
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098824
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098828
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098832
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098828
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098832
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098836
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 1024
+  mul t0, t0, t1
+  li t4, 2098840
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098836
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098840
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098844
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098852
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098856
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098852
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098856
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098860
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098864
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098860
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098864
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098868
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098872
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098868
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098872
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098876
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098880
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098876
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098880
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098884
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098888
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098884
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098888
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098892
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098896
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098892
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098896
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098900
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 2048
+  mul t0, t0, t1
+  li t4, 2098904
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098900
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098904
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098908
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098916
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098920
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098916
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098920
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098924
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098928
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098924
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098928
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098932
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098936
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098932
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098936
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098940
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2098944
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098940
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098944
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098948
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2098952
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098948
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098952
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098956
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 4096
+  mul t0, t0, t1
+  li t4, 2098960
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098956
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098960
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098964
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2098972
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2098976
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098972
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098976
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098980
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2098984
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098980
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098984
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098988
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2098992
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098988
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2098992
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2098996
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2099000
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2098996
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099000
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099004
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 8192
+  mul t0, t0, t1
+  li t4, 2099008
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099004
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099008
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099012
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099020
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099024
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099020
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099024
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099028
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2099032
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099028
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099032
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099036
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2099040
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099036
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099040
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099044
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 16384
+  mul t0, t0, t1
+  li t4, 2099048
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099044
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099048
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099060
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099064
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099060
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099064
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2099072
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099068
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099072
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 32768
+  mul t0, t0, t1
+  li t4, 2099080
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099076
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099080
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099084
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099092
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099096
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099092
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099096
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099100
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 65536
+  mul t0, t0, t1
+  li t4, 2099104
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099100
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099104
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099108
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 131072
+  mul t0, t0, t1
+  li t4, 2099120
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099116
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2099120
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2099124
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 262144
+  mul t0, t0, t1
+  li t4, 2099132
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi sp, sp, -96
+  addi a0, s0, 0
+  li t4, 2097908
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a0, a0, t1
+  addi a1, s0, 0
+  li t4, 2098044
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a1, a1, t1
+  addi a2, s0, 0
+  li t4, 2098172
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a2, a2, t1
+  addi a3, s0, 0
+  li t4, 2098292
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a3, a3, t1
+  addi a4, s0, 0
+  li t4, 2098404
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a4, a4, t1
+  addi a5, s0, 0
+  li t4, 2098508
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a5, a5, t1
+  addi a6, s0, 0
+  li t4, 2098604
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a6, a6, t1
+  addi a7, s0, 0
+  li t4, 2098692
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a7, a7, t1
+  add t4, sp, zero
+  addi t0, s0, 0
+  li t4, 2098772
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 8
+  addi t0, s0, 0
+  li t4, 2098844
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 16
+  addi t0, s0, 0
+  li t4, 2098908
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  addi t0, s0, 0
+  li t4, 2098964
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 32
+  addi t0, s0, 0
+  li t4, 2099012
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 40
+  addi t0, s0, 0
+  li t4, 2099052
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  addi t0, s0, 0
+  li t4, 2099084
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 56
+  addi t0, s0, 0
+  li t4, 2099108
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  addi t0, s0, 0
+  li t4, 2099124
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 72
+  addi t0, s0, 0
+  li t4, 2099132
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 80
+  addi t0, s0, 0
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  call sum
+  addi sp, sp, 96
+  li t4, 2099144
+  add t4, s0, t4
+  sw a0, 0(t4)
+  li t4, 2099144
+  add t4, s0, t4
+  lw a0, 0(t4)
+  call putint
+  li t0, 0
+  li t1, 256
+  rem t0, t0, t1
+  li t4, 2099148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099148
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  add t0, t0, t1
+  li t4, 2099152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099152
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  rem t0, t0, t1
+  li t4, 2099156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2099156
+  add t4, s0, t4
+  lw a0, 0(t4)
+  call putint
+  li a0, 10
+  call putch
+  li a0, 0
+  li t3, 2099168
+  add t3, s0, t3
+  ld ra, 0(t3)
+  li t3, 2099184
+  add sp, s0, t3
+  li t3, 2099176
+  add t3, s0, t3
+  ld s0, 0(t3)
+  ret
+.size main, .-main
+
diff --git a/39_fp_params.txt b/39_fp_params.txt
new file mode 100644
index 0000000..9b6e148
--- /dev/null
+++ b/39_fp_params.txt
@@ -0,0 +1,9102 @@
+.data
+  .global k
+  .type k, @object
+  .size k, 4
+k:
+  .word 0
+.text
+.global params_f40
+.type params_f40, @function
+params_f40:
+  addi sp, sp, -944
+  sd ra, 928(sp)
+  sd s0, 936(sp)
+  mv s0, sp
+  fsw fa0, 0(s0)
+  fsw fa1, 4(s0)
+  fsw fa2, 8(s0)
+  fsw fa3, 12(s0)
+  fsw fa4, 16(s0)
+  fsw fa5, 20(s0)
+  fsw fa6, 24(s0)
+  fsw fa7, 28(s0)
+  flw ft0, 944(s0)
+  fsw ft0, 32(s0)
+  flw ft0, 952(s0)
+  fsw ft0, 36(s0)
+  flw ft0, 960(s0)
+  fsw ft0, 40(s0)
+  flw ft0, 968(s0)
+  fsw ft0, 44(s0)
+  flw ft0, 976(s0)
+  fsw ft0, 48(s0)
+  flw ft0, 984(s0)
+  fsw ft0, 52(s0)
+  flw ft0, 992(s0)
+  fsw ft0, 56(s0)
+  flw ft0, 1000(s0)
+  fsw ft0, 60(s0)
+  flw ft0, 1008(s0)
+  fsw ft0, 64(s0)
+  flw ft0, 1016(s0)
+  fsw ft0, 68(s0)
+  flw ft0, 1024(s0)
+  fsw ft0, 72(s0)
+  flw ft0, 1032(s0)
+  fsw ft0, 76(s0)
+  flw ft0, 1040(s0)
+  fsw ft0, 80(s0)
+  flw ft0, 1048(s0)
+  fsw ft0, 84(s0)
+  flw ft0, 1056(s0)
+  fsw ft0, 88(s0)
+  flw ft0, 1064(s0)
+  fsw ft0, 92(s0)
+  flw ft0, 1072(s0)
+  fsw ft0, 96(s0)
+  flw ft0, 1080(s0)
+  fsw ft0, 100(s0)
+  flw ft0, 1088(s0)
+  fsw ft0, 104(s0)
+  flw ft0, 1096(s0)
+  fsw ft0, 108(s0)
+  flw ft0, 1104(s0)
+  fsw ft0, 112(s0)
+  flw ft0, 1112(s0)
+  fsw ft0, 116(s0)
+  flw ft0, 1120(s0)
+  fsw ft0, 120(s0)
+  flw ft0, 1128(s0)
+  fsw ft0, 124(s0)
+  flw ft0, 1136(s0)
+  fsw ft0, 128(s0)
+  flw ft0, 1144(s0)
+  fsw ft0, 132(s0)
+  flw ft0, 1152(s0)
+  fsw ft0, 136(s0)
+  flw ft0, 1160(s0)
+  fsw ft0, 140(s0)
+  flw ft0, 1168(s0)
+  fsw ft0, 144(s0)
+  flw ft0, 1176(s0)
+  fsw ft0, 148(s0)
+  flw ft0, 1184(s0)
+  fsw ft0, 152(s0)
+  flw ft0, 1192(s0)
+  fsw ft0, 156(s0)
+  flw ft0, 0(s0)
+  fsw ft0, 160(s0)
+  flw ft0, 4(s0)
+  fsw ft0, 164(s0)
+  flw ft0, 8(s0)
+  fsw ft0, 168(s0)
+  flw ft0, 12(s0)
+  fsw ft0, 172(s0)
+  flw ft0, 16(s0)
+  fsw ft0, 176(s0)
+  flw ft0, 20(s0)
+  fsw ft0, 180(s0)
+  flw ft0, 24(s0)
+  fsw ft0, 184(s0)
+  flw ft0, 28(s0)
+  fsw ft0, 188(s0)
+  flw ft0, 32(s0)
+  fsw ft0, 192(s0)
+  flw ft0, 36(s0)
+  fsw ft0, 196(s0)
+  flw ft0, 40(s0)
+  fsw ft0, 200(s0)
+  flw ft0, 44(s0)
+  fsw ft0, 204(s0)
+  flw ft0, 48(s0)
+  fsw ft0, 208(s0)
+  flw ft0, 52(s0)
+  fsw ft0, 212(s0)
+  flw ft0, 56(s0)
+  fsw ft0, 216(s0)
+  flw ft0, 60(s0)
+  fsw ft0, 220(s0)
+  flw ft0, 64(s0)
+  fsw ft0, 224(s0)
+  flw ft0, 68(s0)
+  fsw ft0, 228(s0)
+  flw ft0, 72(s0)
+  fsw ft0, 232(s0)
+  flw ft0, 76(s0)
+  fsw ft0, 236(s0)
+  flw ft0, 80(s0)
+  fsw ft0, 240(s0)
+  flw ft0, 84(s0)
+  fsw ft0, 244(s0)
+  flw ft0, 88(s0)
+  fsw ft0, 248(s0)
+  flw ft0, 92(s0)
+  fsw ft0, 252(s0)
+  flw ft0, 96(s0)
+  fsw ft0, 256(s0)
+  flw ft0, 100(s0)
+  fsw ft0, 260(s0)
+  flw ft0, 104(s0)
+  fsw ft0, 264(s0)
+  flw ft0, 108(s0)
+  fsw ft0, 268(s0)
+  flw ft0, 112(s0)
+  fsw ft0, 272(s0)
+  flw ft0, 116(s0)
+  fsw ft0, 276(s0)
+  flw ft0, 120(s0)
+  fsw ft0, 280(s0)
+  flw ft0, 124(s0)
+  fsw ft0, 284(s0)
+  flw ft0, 128(s0)
+  fsw ft0, 288(s0)
+  flw ft0, 132(s0)
+  fsw ft0, 292(s0)
+  flw ft0, 136(s0)
+  fsw ft0, 296(s0)
+  flw ft0, 140(s0)
+  fsw ft0, 300(s0)
+  flw ft0, 144(s0)
+  fsw ft0, 304(s0)
+  flw ft0, 148(s0)
+  fsw ft0, 308(s0)
+  flw ft0, 152(s0)
+  fsw ft0, 312(s0)
+  flw ft0, 156(s0)
+  fsw ft0, 316(s0)
+  flw ft0, 316(s0)
+  fsw ft0, 320(s0)
+  li t0, 0
+  fcvt.s.w ft0, t0
+  fsw ft0, 324(s0)
+  flw ft0, 320(s0)
+  flw ft1, 324(s0)
+  feq.s t0, ft0, ft1
+  xori t0, t0, 1
+  sw t0, 328(s0)
+  lw t0, 328(s0)
+  bnez t0, L0.if.then
+  j L1.if.else
+L0.if.then:
+  flw ft0, 160(s0)
+  fsw ft0, 400(s0)
+  flw ft0, 164(s0)
+  fsw ft0, 404(s0)
+  flw ft0, 400(s0)
+  flw ft1, 404(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 408(s0)
+  flw ft0, 168(s0)
+  fsw ft0, 412(s0)
+  flw ft0, 408(s0)
+  flw ft1, 412(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 416(s0)
+  flw ft0, 172(s0)
+  fsw ft0, 420(s0)
+  flw ft0, 416(s0)
+  flw ft1, 420(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 424(s0)
+  flw ft0, 176(s0)
+  fsw ft0, 428(s0)
+  flw ft0, 180(s0)
+  fsw ft0, 432(s0)
+  flw ft0, 428(s0)
+  flw ft1, 432(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 436(s0)
+  flw ft0, 184(s0)
+  fsw ft0, 440(s0)
+  flw ft0, 436(s0)
+  flw ft1, 440(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 444(s0)
+  flw ft0, 188(s0)
+  fsw ft0, 448(s0)
+  flw ft0, 444(s0)
+  flw ft1, 448(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 452(s0)
+  flw ft0, 192(s0)
+  fsw ft0, 456(s0)
+  flw ft0, 196(s0)
+  fsw ft0, 460(s0)
+  flw ft0, 456(s0)
+  flw ft1, 460(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 464(s0)
+  flw ft0, 200(s0)
+  fsw ft0, 468(s0)
+  flw ft0, 464(s0)
+  flw ft1, 468(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 472(s0)
+  flw ft0, 204(s0)
+  fsw ft0, 476(s0)
+  flw ft0, 472(s0)
+  flw ft1, 476(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 480(s0)
+  flw ft0, 208(s0)
+  fsw ft0, 484(s0)
+  flw ft0, 212(s0)
+  fsw ft0, 488(s0)
+  flw ft0, 484(s0)
+  flw ft1, 488(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 492(s0)
+  flw ft0, 216(s0)
+  fsw ft0, 496(s0)
+  flw ft0, 492(s0)
+  flw ft1, 496(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 500(s0)
+  flw ft0, 220(s0)
+  fsw ft0, 504(s0)
+  flw ft0, 500(s0)
+  flw ft1, 504(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 508(s0)
+  flw ft0, 224(s0)
+  fsw ft0, 512(s0)
+  flw ft0, 228(s0)
+  fsw ft0, 516(s0)
+  flw ft0, 512(s0)
+  flw ft1, 516(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 520(s0)
+  flw ft0, 232(s0)
+  fsw ft0, 524(s0)
+  flw ft0, 520(s0)
+  flw ft1, 524(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 528(s0)
+  flw ft0, 236(s0)
+  fsw ft0, 532(s0)
+  flw ft0, 528(s0)
+  flw ft1, 532(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 536(s0)
+  flw ft0, 240(s0)
+  fsw ft0, 540(s0)
+  flw ft0, 244(s0)
+  fsw ft0, 544(s0)
+  flw ft0, 540(s0)
+  flw ft1, 544(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 548(s0)
+  flw ft0, 248(s0)
+  fsw ft0, 552(s0)
+  flw ft0, 548(s0)
+  flw ft1, 552(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 556(s0)
+  flw ft0, 252(s0)
+  fsw ft0, 560(s0)
+  flw ft0, 556(s0)
+  flw ft1, 560(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 564(s0)
+  flw ft0, 256(s0)
+  fsw ft0, 568(s0)
+  flw ft0, 260(s0)
+  fsw ft0, 572(s0)
+  flw ft0, 568(s0)
+  flw ft1, 572(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 576(s0)
+  flw ft0, 264(s0)
+  fsw ft0, 580(s0)
+  flw ft0, 576(s0)
+  flw ft1, 580(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 584(s0)
+  flw ft0, 268(s0)
+  fsw ft0, 588(s0)
+  flw ft0, 584(s0)
+  flw ft1, 588(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 592(s0)
+  flw ft0, 272(s0)
+  fsw ft0, 596(s0)
+  flw ft0, 276(s0)
+  fsw ft0, 600(s0)
+  flw ft0, 596(s0)
+  flw ft1, 600(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 604(s0)
+  flw ft0, 280(s0)
+  fsw ft0, 608(s0)
+  flw ft0, 604(s0)
+  flw ft1, 608(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 612(s0)
+  flw ft0, 284(s0)
+  fsw ft0, 616(s0)
+  flw ft0, 612(s0)
+  flw ft1, 616(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 620(s0)
+  flw ft0, 288(s0)
+  fsw ft0, 624(s0)
+  flw ft0, 292(s0)
+  fsw ft0, 628(s0)
+  flw ft0, 624(s0)
+  flw ft1, 628(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 632(s0)
+  flw ft0, 296(s0)
+  fsw ft0, 636(s0)
+  flw ft0, 632(s0)
+  flw ft1, 636(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 640(s0)
+  flw ft0, 300(s0)
+  fsw ft0, 644(s0)
+  flw ft0, 640(s0)
+  flw ft1, 644(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 648(s0)
+  flw ft0, 304(s0)
+  fsw ft0, 652(s0)
+  flw ft0, 308(s0)
+  fsw ft0, 656(s0)
+  flw ft0, 652(s0)
+  flw ft1, 656(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 660(s0)
+  flw ft0, 312(s0)
+  fsw ft0, 664(s0)
+  flw ft0, 660(s0)
+  flw ft1, 664(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 668(s0)
+  flw ft0, 316(s0)
+  fsw ft0, 672(s0)
+  flw ft0, 668(s0)
+  flw ft1, 672(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 676(s0)
+  addi a0, s0, 360
+  li a1, 0
+  li a2, 40
+  call memset
+  flw ft0, 424(s0)
+  addi t0, s0, 360
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 452(s0)
+  addi t0, s0, 360
+  li t1, 1
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 480(s0)
+  addi t0, s0, 360
+  li t1, 2
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 508(s0)
+  addi t0, s0, 360
+  li t1, 3
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 536(s0)
+  addi t0, s0, 360
+  li t1, 4
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 564(s0)
+  addi t0, s0, 360
+  li t1, 5
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 592(s0)
+  addi t0, s0, 360
+  li t1, 6
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 620(s0)
+  addi t0, s0, 360
+  li t1, 7
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 648(s0)
+  addi t0, s0, 360
+  li t1, 8
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 676(s0)
+  addi t0, s0, 360
+  li t1, 9
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  li a0, 10
+  addi a1, s0, 360
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  call putfarray
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 724(s0)
+  addi t0, s0, 360
+  lw t1, 724(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 732(s0)
+  flw fa0, 732(s0)
+  ld ra, 928(s0)
+  addi sp, s0, 944
+  ld s0, 936(s0)
+  ret
+L1.if.else:
+  flw ft0, 164(s0)
+  fsw ft0, 736(s0)
+  flw ft0, 168(s0)
+  fsw ft0, 740(s0)
+  flw ft0, 172(s0)
+  fsw ft0, 744(s0)
+  flw ft0, 176(s0)
+  fsw ft0, 748(s0)
+  flw ft0, 180(s0)
+  fsw ft0, 752(s0)
+  flw ft0, 184(s0)
+  fsw ft0, 756(s0)
+  flw ft0, 188(s0)
+  fsw ft0, 760(s0)
+  flw ft0, 192(s0)
+  fsw ft0, 764(s0)
+  flw ft0, 196(s0)
+  fsw ft0, 768(s0)
+  flw ft0, 200(s0)
+  fsw ft0, 772(s0)
+  flw ft0, 204(s0)
+  fsw ft0, 776(s0)
+  flw ft0, 208(s0)
+  fsw ft0, 780(s0)
+  flw ft0, 212(s0)
+  fsw ft0, 784(s0)
+  flw ft0, 216(s0)
+  fsw ft0, 788(s0)
+  flw ft0, 220(s0)
+  fsw ft0, 792(s0)
+  flw ft0, 224(s0)
+  fsw ft0, 796(s0)
+  flw ft0, 228(s0)
+  fsw ft0, 800(s0)
+  flw ft0, 232(s0)
+  fsw ft0, 804(s0)
+  flw ft0, 236(s0)
+  fsw ft0, 808(s0)
+  flw ft0, 240(s0)
+  fsw ft0, 812(s0)
+  flw ft0, 244(s0)
+  fsw ft0, 816(s0)
+  flw ft0, 248(s0)
+  fsw ft0, 820(s0)
+  flw ft0, 252(s0)
+  fsw ft0, 824(s0)
+  flw ft0, 256(s0)
+  fsw ft0, 828(s0)
+  flw ft0, 260(s0)
+  fsw ft0, 832(s0)
+  flw ft0, 264(s0)
+  fsw ft0, 836(s0)
+  flw ft0, 268(s0)
+  fsw ft0, 840(s0)
+  flw ft0, 272(s0)
+  fsw ft0, 844(s0)
+  flw ft0, 276(s0)
+  fsw ft0, 848(s0)
+  flw ft0, 280(s0)
+  fsw ft0, 852(s0)
+  flw ft0, 284(s0)
+  fsw ft0, 856(s0)
+  flw ft0, 288(s0)
+  fsw ft0, 860(s0)
+  flw ft0, 292(s0)
+  fsw ft0, 864(s0)
+  flw ft0, 296(s0)
+  fsw ft0, 868(s0)
+  flw ft0, 300(s0)
+  fsw ft0, 872(s0)
+  flw ft0, 304(s0)
+  fsw ft0, 876(s0)
+  flw ft0, 308(s0)
+  fsw ft0, 880(s0)
+  flw ft0, 312(s0)
+  fsw ft0, 884(s0)
+  flw ft0, 316(s0)
+  fsw ft0, 888(s0)
+  flw ft0, 160(s0)
+  fsw ft0, 892(s0)
+  flw ft0, 164(s0)
+  fsw ft0, 896(s0)
+  flw ft0, 892(s0)
+  flw ft1, 896(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 900(s0)
+  flw ft0, 168(s0)
+  fsw ft0, 904(s0)
+  flw ft0, 900(s0)
+  flw ft1, 904(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 908(s0)
+  addi sp, sp, -256
+  flw fa0, 736(s0)
+  flw fa1, 740(s0)
+  flw fa2, 744(s0)
+  flw fa3, 748(s0)
+  flw fa4, 752(s0)
+  flw fa5, 756(s0)
+  flw fa6, 760(s0)
+  flw fa7, 764(s0)
+  add t4, sp, zero
+  flw ft0, 768(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 8
+  flw ft0, 772(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 16
+  flw ft0, 776(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 24
+  flw ft0, 780(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 32
+  flw ft0, 784(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 40
+  flw ft0, 788(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 48
+  flw ft0, 792(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 56
+  flw ft0, 796(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 64
+  flw ft0, 800(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 72
+  flw ft0, 804(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 80
+  flw ft0, 808(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 88
+  flw ft0, 812(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 96
+  flw ft0, 816(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 104
+  flw ft0, 820(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 112
+  flw ft0, 824(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 120
+  flw ft0, 828(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 128
+  flw ft0, 832(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 136
+  flw ft0, 836(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 144
+  flw ft0, 840(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 152
+  flw ft0, 844(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 160
+  flw ft0, 848(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 168
+  flw ft0, 852(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 176
+  flw ft0, 856(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 184
+  flw ft0, 860(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 192
+  flw ft0, 864(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 200
+  flw ft0, 868(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 208
+  flw ft0, 872(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 216
+  flw ft0, 876(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 224
+  flw ft0, 880(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 232
+  flw ft0, 884(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 240
+  flw ft0, 888(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 248
+  flw ft0, 908(s0)
+  fsw ft0, 0(t4)
+  call params_f40
+  addi sp, sp, 256
+  fsw fa0, 912(s0)
+  flw fa0, 912(s0)
+  ld ra, 928(s0)
+  addi sp, s0, 944
+  ld s0, 936(s0)
+  ret
+L2.if.end:
+  li t4, 0
+  sw t4, 916(s0)
+  flw fa0, 916(s0)
+  ld ra, 928(s0)
+  addi sp, s0, 944
+  ld s0, 936(s0)
+  ret
+.size params_f40, .-params_f40
+
+.global params_f40_i24
+.type params_f40_i24, @function
+params_f40_i24:
+  addi sp, sp, -1488
+  sd ra, 1472(sp)
+  sd s0, 1480(sp)
+  mv s0, sp
+  sw a0, 0(s0)
+  sw a1, 4(s0)
+  sw a2, 8(s0)
+  fsw fa3, 12(s0)
+  sw a4, 16(s0)
+  sw a5, 20(s0)
+  sw a6, 24(s0)
+  fsw fa7, 28(s0)
+  flw ft0, 1488(s0)
+  fsw ft0, 32(s0)
+  flw ft0, 1496(s0)
+  fsw ft0, 36(s0)
+  ld t0, 1504(s0)
+  sw t0, 40(s0)
+  flw ft0, 1512(s0)
+  fsw ft0, 44(s0)
+  flw ft0, 1520(s0)
+  fsw ft0, 48(s0)
+  ld t0, 1528(s0)
+  sw t0, 52(s0)
+  flw ft0, 1536(s0)
+  fsw ft0, 56(s0)
+  ld t0, 1544(s0)
+  sw t0, 60(s0)
+  flw ft0, 1552(s0)
+  fsw ft0, 64(s0)
+  flw ft0, 1560(s0)
+  fsw ft0, 68(s0)
+  flw ft0, 1568(s0)
+  fsw ft0, 72(s0)
+  flw ft0, 1576(s0)
+  fsw ft0, 76(s0)
+  flw ft0, 1584(s0)
+  fsw ft0, 80(s0)
+  flw ft0, 1592(s0)
+  fsw ft0, 84(s0)
+  ld t0, 1600(s0)
+  sw t0, 88(s0)
+  flw ft0, 1608(s0)
+  fsw ft0, 92(s0)
+  ld t0, 1616(s0)
+  sw t0, 96(s0)
+  ld t0, 1624(s0)
+  sw t0, 100(s0)
+  flw ft0, 1632(s0)
+  fsw ft0, 104(s0)
+  flw ft0, 1640(s0)
+  fsw ft0, 108(s0)
+  flw ft0, 1648(s0)
+  fsw ft0, 112(s0)
+  flw ft0, 1656(s0)
+  fsw ft0, 116(s0)
+  flw ft0, 1664(s0)
+  fsw ft0, 120(s0)
+  ld t0, 1672(s0)
+  sw t0, 124(s0)
+  flw ft0, 1680(s0)
+  fsw ft0, 128(s0)
+  ld t0, 1688(s0)
+  sw t0, 132(s0)
+  flw ft0, 1696(s0)
+  fsw ft0, 136(s0)
+  flw ft0, 1704(s0)
+  fsw ft0, 140(s0)
+  flw ft0, 1712(s0)
+  fsw ft0, 144(s0)
+  flw ft0, 1720(s0)
+  fsw ft0, 148(s0)
+  ld t0, 1728(s0)
+  sw t0, 152(s0)
+  ld t0, 1736(s0)
+  sw t0, 156(s0)
+  flw ft0, 1744(s0)
+  fsw ft0, 160(s0)
+  flw ft0, 1752(s0)
+  fsw ft0, 164(s0)
+  flw ft0, 1760(s0)
+  fsw ft0, 168(s0)
+  ld t0, 1768(s0)
+  sw t0, 172(s0)
+  flw ft0, 1776(s0)
+  fsw ft0, 176(s0)
+  ld t0, 1784(s0)
+  sw t0, 180(s0)
+  ld t0, 1792(s0)
+  sw t0, 184(s0)
+  flw ft0, 1800(s0)
+  fsw ft0, 188(s0)
+  flw ft0, 1808(s0)
+  fsw ft0, 192(s0)
+  flw ft0, 1816(s0)
+  fsw ft0, 196(s0)
+  flw ft0, 1824(s0)
+  fsw ft0, 200(s0)
+  ld t0, 1832(s0)
+  sw t0, 204(s0)
+  ld t0, 1840(s0)
+  sw t0, 208(s0)
+  ld t0, 1848(s0)
+  sw t0, 212(s0)
+  flw ft0, 1856(s0)
+  fsw ft0, 216(s0)
+  flw ft0, 1864(s0)
+  fsw ft0, 220(s0)
+  flw ft0, 1872(s0)
+  fsw ft0, 224(s0)
+  flw ft0, 1880(s0)
+  fsw ft0, 228(s0)
+  flw ft0, 1888(s0)
+  fsw ft0, 232(s0)
+  flw ft0, 1896(s0)
+  fsw ft0, 236(s0)
+  ld t0, 1904(s0)
+  sw t0, 240(s0)
+  flw ft0, 1912(s0)
+  fsw ft0, 244(s0)
+  ld t0, 1920(s0)
+  sw t0, 248(s0)
+  flw ft0, 1928(s0)
+  fsw ft0, 252(s0)
+  lw t0, 0(s0)
+  sw t0, 256(s0)
+  lw t0, 4(s0)
+  sw t0, 260(s0)
+  lw t0, 8(s0)
+  sw t0, 264(s0)
+  flw ft0, 12(s0)
+  fsw ft0, 268(s0)
+  lw t0, 16(s0)
+  sw t0, 272(s0)
+  lw t0, 20(s0)
+  sw t0, 276(s0)
+  lw t0, 24(s0)
+  sw t0, 280(s0)
+  flw ft0, 28(s0)
+  fsw ft0, 284(s0)
+  flw ft0, 32(s0)
+  fsw ft0, 288(s0)
+  flw ft0, 36(s0)
+  fsw ft0, 292(s0)
+  lw t0, 40(s0)
+  sw t0, 296(s0)
+  flw ft0, 44(s0)
+  fsw ft0, 300(s0)
+  flw ft0, 48(s0)
+  fsw ft0, 304(s0)
+  lw t0, 52(s0)
+  sw t0, 308(s0)
+  flw ft0, 56(s0)
+  fsw ft0, 312(s0)
+  lw t0, 60(s0)
+  sw t0, 316(s0)
+  flw ft0, 64(s0)
+  fsw ft0, 320(s0)
+  flw ft0, 68(s0)
+  fsw ft0, 324(s0)
+  flw ft0, 72(s0)
+  fsw ft0, 328(s0)
+  flw ft0, 76(s0)
+  fsw ft0, 332(s0)
+  flw ft0, 80(s0)
+  fsw ft0, 336(s0)
+  flw ft0, 84(s0)
+  fsw ft0, 340(s0)
+  lw t0, 88(s0)
+  sw t0, 344(s0)
+  flw ft0, 92(s0)
+  fsw ft0, 348(s0)
+  lw t0, 96(s0)
+  sw t0, 352(s0)
+  lw t0, 100(s0)
+  sw t0, 356(s0)
+  flw ft0, 104(s0)
+  fsw ft0, 360(s0)
+  flw ft0, 108(s0)
+  fsw ft0, 364(s0)
+  flw ft0, 112(s0)
+  fsw ft0, 368(s0)
+  flw ft0, 116(s0)
+  fsw ft0, 372(s0)
+  flw ft0, 120(s0)
+  fsw ft0, 376(s0)
+  lw t0, 124(s0)
+  sw t0, 380(s0)
+  flw ft0, 128(s0)
+  fsw ft0, 384(s0)
+  lw t0, 132(s0)
+  sw t0, 388(s0)
+  flw ft0, 136(s0)
+  fsw ft0, 392(s0)
+  flw ft0, 140(s0)
+  fsw ft0, 396(s0)
+  flw ft0, 144(s0)
+  fsw ft0, 400(s0)
+  flw ft0, 148(s0)
+  fsw ft0, 404(s0)
+  lw t0, 152(s0)
+  sw t0, 408(s0)
+  lw t0, 156(s0)
+  sw t0, 412(s0)
+  flw ft0, 160(s0)
+  fsw ft0, 416(s0)
+  flw ft0, 164(s0)
+  fsw ft0, 420(s0)
+  flw ft0, 168(s0)
+  fsw ft0, 424(s0)
+  lw t0, 172(s0)
+  sw t0, 428(s0)
+  flw ft0, 176(s0)
+  fsw ft0, 432(s0)
+  lw t0, 180(s0)
+  sw t0, 436(s0)
+  lw t0, 184(s0)
+  sw t0, 440(s0)
+  flw ft0, 188(s0)
+  fsw ft0, 444(s0)
+  flw ft0, 192(s0)
+  fsw ft0, 448(s0)
+  flw ft0, 196(s0)
+  fsw ft0, 452(s0)
+  flw ft0, 200(s0)
+  fsw ft0, 456(s0)
+  lw t0, 204(s0)
+  sw t0, 460(s0)
+  lw t0, 208(s0)
+  sw t0, 464(s0)
+  lw t0, 212(s0)
+  sw t0, 468(s0)
+  flw ft0, 216(s0)
+  fsw ft0, 472(s0)
+  flw ft0, 220(s0)
+  fsw ft0, 476(s0)
+  flw ft0, 224(s0)
+  fsw ft0, 480(s0)
+  flw ft0, 228(s0)
+  fsw ft0, 484(s0)
+  flw ft0, 232(s0)
+  fsw ft0, 488(s0)
+  flw ft0, 236(s0)
+  fsw ft0, 492(s0)
+  lw t0, 240(s0)
+  sw t0, 496(s0)
+  flw ft0, 244(s0)
+  fsw ft0, 500(s0)
+  lw t0, 248(s0)
+  sw t0, 504(s0)
+  flw ft0, 252(s0)
+  fsw ft0, 508(s0)
+  lw t0, 256(s0)
+  sw t0, 512(s0)
+  lw t0, 512(s0)
+  li t1, 0
+  sub t0, t0, t1
+  sltiu t1, t0, 1
+  xori t0, t1, 1
+  sw t0, 516(s0)
+  lw t0, 516(s0)
+  bnez t0, L3.if.then
+  j L4.if.else
+L3.if.then:
+  flw ft0, 424(s0)
+  fsw ft0, 560(s0)
+  flw ft0, 328(s0)
+  fsw ft0, 564(s0)
+  flw ft0, 560(s0)
+  flw ft1, 564(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 568(s0)
+  flw ft0, 500(s0)
+  fsw ft0, 572(s0)
+  flw ft0, 568(s0)
+  flw ft1, 572(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 576(s0)
+  flw ft0, 300(s0)
+  fsw ft0, 580(s0)
+  flw ft0, 576(s0)
+  flw ft1, 580(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 584(s0)
+  flw ft0, 268(s0)
+  fsw ft0, 588(s0)
+  flw ft0, 400(s0)
+  fsw ft0, 592(s0)
+  flw ft0, 588(s0)
+  flw ft1, 592(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 596(s0)
+  flw ft0, 340(s0)
+  fsw ft0, 600(s0)
+  flw ft0, 596(s0)
+  flw ft1, 600(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 604(s0)
+  flw ft0, 292(s0)
+  fsw ft0, 608(s0)
+  flw ft0, 604(s0)
+  flw ft1, 608(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 612(s0)
+  flw ft0, 284(s0)
+  fsw ft0, 616(s0)
+  flw ft0, 372(s0)
+  fsw ft0, 620(s0)
+  flw ft0, 616(s0)
+  flw ft1, 620(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 624(s0)
+  flw ft0, 420(s0)
+  fsw ft0, 628(s0)
+  flw ft0, 624(s0)
+  flw ft1, 628(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 632(s0)
+  flw ft0, 332(s0)
+  fsw ft0, 636(s0)
+  flw ft0, 632(s0)
+  flw ft1, 636(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 640(s0)
+  flw ft0, 324(s0)
+  fsw ft0, 644(s0)
+  flw ft0, 452(s0)
+  fsw ft0, 648(s0)
+  flw ft0, 644(s0)
+  flw ft1, 648(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 652(s0)
+  flw ft0, 416(s0)
+  fsw ft0, 656(s0)
+  flw ft0, 652(s0)
+  flw ft1, 656(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 660(s0)
+  flw ft0, 288(s0)
+  fsw ft0, 664(s0)
+  flw ft0, 660(s0)
+  flw ft1, 664(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 668(s0)
+  flw ft0, 396(s0)
+  fsw ft0, 672(s0)
+  flw ft0, 492(s0)
+  fsw ft0, 676(s0)
+  flw ft0, 672(s0)
+  flw ft1, 676(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 680(s0)
+  flw ft0, 472(s0)
+  fsw ft0, 684(s0)
+  flw ft0, 680(s0)
+  flw ft1, 684(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 688(s0)
+  flw ft0, 476(s0)
+  fsw ft0, 692(s0)
+  flw ft0, 688(s0)
+  flw ft1, 692(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 696(s0)
+  flw ft0, 360(s0)
+  fsw ft0, 700(s0)
+  flw ft0, 392(s0)
+  fsw ft0, 704(s0)
+  flw ft0, 700(s0)
+  flw ft1, 704(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 708(s0)
+  flw ft0, 480(s0)
+  fsw ft0, 712(s0)
+  flw ft0, 708(s0)
+  flw ft1, 712(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 716(s0)
+  flw ft0, 368(s0)
+  fsw ft0, 720(s0)
+  flw ft0, 716(s0)
+  flw ft1, 720(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 724(s0)
+  flw ft0, 448(s0)
+  fsw ft0, 728(s0)
+  flw ft0, 376(s0)
+  fsw ft0, 732(s0)
+  flw ft0, 728(s0)
+  flw ft1, 732(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 736(s0)
+  flw ft0, 484(s0)
+  fsw ft0, 740(s0)
+  flw ft0, 736(s0)
+  flw ft1, 740(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 744(s0)
+  flw ft0, 444(s0)
+  fsw ft0, 748(s0)
+  flw ft0, 744(s0)
+  flw ft1, 748(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 752(s0)
+  flw ft0, 304(s0)
+  fsw ft0, 756(s0)
+  flw ft0, 456(s0)
+  fsw ft0, 760(s0)
+  flw ft0, 756(s0)
+  flw ft1, 760(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 764(s0)
+  flw ft0, 320(s0)
+  fsw ft0, 768(s0)
+  flw ft0, 764(s0)
+  flw ft1, 768(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 772(s0)
+  flw ft0, 432(s0)
+  fsw ft0, 776(s0)
+  flw ft0, 772(s0)
+  flw ft1, 776(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 780(s0)
+  flw ft0, 348(s0)
+  fsw ft0, 784(s0)
+  flw ft0, 364(s0)
+  fsw ft0, 788(s0)
+  flw ft0, 784(s0)
+  flw ft1, 788(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 792(s0)
+  flw ft0, 404(s0)
+  fsw ft0, 796(s0)
+  flw ft0, 792(s0)
+  flw ft1, 796(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 800(s0)
+  flw ft0, 508(s0)
+  fsw ft0, 804(s0)
+  flw ft0, 800(s0)
+  flw ft1, 804(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 808(s0)
+  flw ft0, 488(s0)
+  fsw ft0, 812(s0)
+  flw ft0, 312(s0)
+  fsw ft0, 816(s0)
+  flw ft0, 812(s0)
+  flw ft1, 816(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 820(s0)
+  flw ft0, 336(s0)
+  fsw ft0, 824(s0)
+  flw ft0, 820(s0)
+  flw ft1, 824(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 828(s0)
+  flw ft0, 384(s0)
+  fsw ft0, 832(s0)
+  flw ft0, 828(s0)
+  flw ft1, 832(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 836(s0)
+  addi a0, s0, 520
+  li a1, 0
+  li a2, 40
+  call memset
+  flw ft0, 584(s0)
+  addi t0, s0, 520
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 612(s0)
+  addi t0, s0, 520
+  li t1, 1
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 640(s0)
+  addi t0, s0, 520
+  li t1, 2
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 668(s0)
+  addi t0, s0, 520
+  li t1, 3
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 696(s0)
+  addi t0, s0, 520
+  li t1, 4
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 724(s0)
+  addi t0, s0, 520
+  li t1, 5
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 752(s0)
+  addi t0, s0, 520
+  li t1, 6
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 780(s0)
+  addi t0, s0, 520
+  li t1, 7
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 808(s0)
+  addi t0, s0, 520
+  li t1, 8
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 836(s0)
+  addi t0, s0, 520
+  li t1, 9
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  lw t0, 308(s0)
+  sw t0, 928(s0)
+  lw t0, 272(s0)
+  sw t0, 932(s0)
+  lw t0, 928(s0)
+  lw t1, 932(s0)
+  add t0, t0, t1
+  sw t0, 936(s0)
+  lw t0, 260(s0)
+  sw t0, 940(s0)
+  lw t0, 936(s0)
+  lw t1, 940(s0)
+  add t0, t0, t1
+  sw t0, 944(s0)
+  lw t0, 460(s0)
+  sw t0, 948(s0)
+  lw t0, 276(s0)
+  sw t0, 952(s0)
+  lw t0, 948(s0)
+  lw t1, 952(s0)
+  add t0, t0, t1
+  sw t0, 956(s0)
+  lw t0, 280(s0)
+  sw t0, 960(s0)
+  lw t0, 956(s0)
+  lw t1, 960(s0)
+  add t0, t0, t1
+  sw t0, 964(s0)
+  lw t0, 264(s0)
+  sw t0, 968(s0)
+  lw t0, 344(s0)
+  sw t0, 972(s0)
+  lw t0, 968(s0)
+  lw t1, 972(s0)
+  add t0, t0, t1
+  sw t0, 976(s0)
+  lw t0, 380(s0)
+  sw t0, 980(s0)
+  lw t0, 976(s0)
+  lw t1, 980(s0)
+  add t0, t0, t1
+  sw t0, 984(s0)
+  lw t0, 412(s0)
+  sw t0, 988(s0)
+  lw t0, 352(s0)
+  sw t0, 992(s0)
+  lw t0, 988(s0)
+  lw t1, 992(s0)
+  add t0, t0, t1
+  sw t0, 996(s0)
+  lw t0, 436(s0)
+  sw t0, 1000(s0)
+  lw t0, 996(s0)
+  lw t1, 1000(s0)
+  add t0, t0, t1
+  sw t0, 1004(s0)
+  lw t0, 428(s0)
+  sw t0, 1008(s0)
+  lw t0, 356(s0)
+  sw t0, 1012(s0)
+  lw t0, 1008(s0)
+  lw t1, 1012(s0)
+  add t0, t0, t1
+  sw t0, 1016(s0)
+  lw t0, 504(s0)
+  sw t0, 1020(s0)
+  lw t0, 1016(s0)
+  lw t1, 1020(s0)
+  add t0, t0, t1
+  sw t0, 1024(s0)
+  lw t0, 496(s0)
+  sw t0, 1028(s0)
+  lw t0, 440(s0)
+  sw t0, 1032(s0)
+  lw t0, 1028(s0)
+  lw t1, 1032(s0)
+  add t0, t0, t1
+  sw t0, 1036(s0)
+  lw t0, 388(s0)
+  sw t0, 1040(s0)
+  lw t0, 1036(s0)
+  lw t1, 1040(s0)
+  add t0, t0, t1
+  sw t0, 1044(s0)
+  lw t0, 408(s0)
+  sw t0, 1048(s0)
+  lw t0, 316(s0)
+  sw t0, 1052(s0)
+  lw t0, 1048(s0)
+  lw t1, 1052(s0)
+  add t0, t0, t1
+  sw t0, 1056(s0)
+  lw t0, 468(s0)
+  sw t0, 1060(s0)
+  lw t0, 1056(s0)
+  lw t1, 1060(s0)
+  add t0, t0, t1
+  sw t0, 1064(s0)
+  lw t0, 464(s0)
+  sw t0, 1068(s0)
+  lw t0, 296(s0)
+  sw t0, 1072(s0)
+  lw t0, 1068(s0)
+  lw t1, 1072(s0)
+  add t0, t0, t1
+  sw t0, 1076(s0)
+  lw t0, 256(s0)
+  sw t0, 1080(s0)
+  lw t0, 1076(s0)
+  lw t1, 1080(s0)
+  add t0, t0, t1
+  sw t0, 1084(s0)
+  addi a0, s0, 896
+  li a1, 0
+  li a2, 32
+  call memset
+  lw t2, 944(s0)
+  addi t0, s0, 896
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 964(s0)
+  addi t0, s0, 896
+  li t1, 1
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 984(s0)
+  addi t0, s0, 896
+  li t1, 2
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1004(s0)
+  addi t0, s0, 896
+  li t1, 3
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1024(s0)
+  addi t0, s0, 896
+  li t1, 4
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1044(s0)
+  addi t0, s0, 896
+  li t1, 5
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1064(s0)
+  addi t0, s0, 896
+  li t1, 6
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1084(s0)
+  addi t0, s0, 896
+  li t1, 7
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  li a0, 10
+  addi a1, s0, 520
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  call putfarray
+  li a0, 8
+  addi a1, s0, 896
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  call putarray
+  li t0, 0
+  sw t0, 1128(s0)
+  j L6.while.cond
+L6.while.cond:
+  lw t0, 1128(s0)
+  sw t0, 1132(s0)
+  lw t0, 1132(s0)
+  li t1, 8
+  slt t0, t0, t1
+  sw t0, 1136(s0)
+  lw t0, 1136(s0)
+  bnez t0, L7.while.body
+  j L8.while.end
+L7.while.body:
+  lw t0, 1128(s0)
+  sw t0, 1140(s0)
+  addi t0, s0, 896
+  lw t1, 1140(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1148(s0)
+  lw t0, 1128(s0)
+  sw t0, 1152(s0)
+  addi t0, s0, 520
+  lw t1, 1152(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1160(s0)
+  lw t0, 1148(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1164(s0)
+  flw ft0, 1164(s0)
+  flw ft1, 1160(s0)
+  fsub.s ft0, ft0, ft1
+  fsw ft0, 1168(s0)
+  lw t0, 1128(s0)
+  sw t0, 1172(s0)
+  flw ft0, 1168(s0)
+  fcvt.w.s t0, ft0, rtz
+  sw t0, 1180(s0)
+  lw t2, 1180(s0)
+  addi t0, s0, 896
+  lw t1, 1172(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t0, 1128(s0)
+  sw t0, 1184(s0)
+  lw t0, 1184(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1188(s0)
+  lw t0, 1188(s0)
+  sw t0, 1128(s0)
+  j L6.while.cond
+L8.while.end:
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1192(s0)
+  addi t0, s0, 896
+  lw t1, 1192(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1200(s0)
+  lw t0, 1200(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1204(s0)
+  flw fa0, 1204(s0)
+  ld ra, 1472(s0)
+  addi sp, s0, 1488
+  ld s0, 1480(s0)
+  ret
+L4.if.else:
+  lw t0, 272(s0)
+  sw t0, 1208(s0)
+  lw t0, 260(s0)
+  sw t0, 1212(s0)
+  lw t0, 264(s0)
+  sw t0, 1216(s0)
+  flw ft0, 268(s0)
+  fsw ft0, 1220(s0)
+  lw t0, 272(s0)
+  sw t0, 1224(s0)
+  lw t0, 276(s0)
+  sw t0, 1228(s0)
+  lw t0, 280(s0)
+  sw t0, 1232(s0)
+  flw ft0, 284(s0)
+  fsw ft0, 1236(s0)
+  flw ft0, 288(s0)
+  fsw ft0, 1240(s0)
+  flw ft0, 292(s0)
+  fsw ft0, 1244(s0)
+  lw t0, 296(s0)
+  sw t0, 1248(s0)
+  flw ft0, 300(s0)
+  fsw ft0, 1252(s0)
+  flw ft0, 304(s0)
+  fsw ft0, 1256(s0)
+  lw t0, 308(s0)
+  sw t0, 1260(s0)
+  flw ft0, 312(s0)
+  fsw ft0, 1264(s0)
+  lw t0, 316(s0)
+  sw t0, 1268(s0)
+  flw ft0, 320(s0)
+  fsw ft0, 1272(s0)
+  flw ft0, 324(s0)
+  fsw ft0, 1276(s0)
+  flw ft0, 328(s0)
+  fsw ft0, 1280(s0)
+  flw ft0, 332(s0)
+  fsw ft0, 1284(s0)
+  flw ft0, 336(s0)
+  fsw ft0, 1288(s0)
+  flw ft0, 340(s0)
+  fsw ft0, 1292(s0)
+  lw t0, 344(s0)
+  sw t0, 1296(s0)
+  flw ft0, 348(s0)
+  fsw ft0, 1300(s0)
+  lw t0, 352(s0)
+  sw t0, 1304(s0)
+  lw t0, 356(s0)
+  sw t0, 1308(s0)
+  flw ft0, 360(s0)
+  fsw ft0, 1312(s0)
+  flw ft0, 364(s0)
+  fsw ft0, 1316(s0)
+  flw ft0, 368(s0)
+  fsw ft0, 1320(s0)
+  flw ft0, 372(s0)
+  fsw ft0, 1324(s0)
+  flw ft0, 376(s0)
+  fsw ft0, 1328(s0)
+  lw t0, 380(s0)
+  sw t0, 1332(s0)
+  flw ft0, 384(s0)
+  fsw ft0, 1336(s0)
+  lw t0, 388(s0)
+  sw t0, 1340(s0)
+  flw ft0, 392(s0)
+  fsw ft0, 1344(s0)
+  flw ft0, 396(s0)
+  fsw ft0, 1348(s0)
+  flw ft0, 400(s0)
+  fsw ft0, 1352(s0)
+  flw ft0, 404(s0)
+  fsw ft0, 1356(s0)
+  lw t0, 408(s0)
+  sw t0, 1360(s0)
+  lw t0, 412(s0)
+  sw t0, 1364(s0)
+  flw ft0, 416(s0)
+  fsw ft0, 1368(s0)
+  flw ft0, 420(s0)
+  fsw ft0, 1372(s0)
+  flw ft0, 424(s0)
+  fsw ft0, 1376(s0)
+  lw t0, 428(s0)
+  sw t0, 1380(s0)
+  flw ft0, 432(s0)
+  fsw ft0, 1384(s0)
+  lw t0, 436(s0)
+  sw t0, 1388(s0)
+  lw t0, 440(s0)
+  sw t0, 1392(s0)
+  flw ft0, 444(s0)
+  fsw ft0, 1396(s0)
+  flw ft0, 448(s0)
+  fsw ft0, 1400(s0)
+  flw ft0, 452(s0)
+  fsw ft0, 1404(s0)
+  flw ft0, 456(s0)
+  fsw ft0, 1408(s0)
+  lw t0, 460(s0)
+  sw t0, 1412(s0)
+  lw t0, 464(s0)
+  sw t0, 1416(s0)
+  lw t0, 468(s0)
+  sw t0, 1420(s0)
+  flw ft0, 472(s0)
+  fsw ft0, 1424(s0)
+  flw ft0, 476(s0)
+  fsw ft0, 1428(s0)
+  flw ft0, 480(s0)
+  fsw ft0, 1432(s0)
+  flw ft0, 484(s0)
+  fsw ft0, 1436(s0)
+  flw ft0, 488(s0)
+  fsw ft0, 1440(s0)
+  flw ft0, 492(s0)
+  fsw ft0, 1444(s0)
+  lw t0, 496(s0)
+  sw t0, 1448(s0)
+  flw ft0, 500(s0)
+  fsw ft0, 1452(s0)
+  lw t0, 504(s0)
+  sw t0, 1456(s0)
+  flw ft0, 508(s0)
+  fsw ft0, 1460(s0)
+  addi sp, sp, -448
+  lw a0, 1208(s0)
+  lw a1, 1212(s0)
+  lw a2, 1216(s0)
+  flw fa3, 1220(s0)
+  lw a4, 1224(s0)
+  lw a5, 1228(s0)
+  lw a6, 1232(s0)
+  flw fa7, 1236(s0)
+  add t4, sp, zero
+  flw ft0, 1240(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 8
+  flw ft0, 1244(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 16
+  lw t0, 1248(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  flw ft0, 1252(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 32
+  flw ft0, 1256(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 40
+  lw t0, 1260(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  flw ft0, 1264(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 56
+  lw t0, 1268(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  flw ft0, 1272(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 72
+  flw ft0, 1276(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 80
+  flw ft0, 1280(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 88
+  flw ft0, 1284(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 96
+  flw ft0, 1288(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 104
+  flw ft0, 1292(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 112
+  lw t0, 1296(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 120
+  flw ft0, 1300(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 128
+  lw t0, 1304(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 136
+  lw t0, 1308(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 144
+  flw ft0, 1312(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 152
+  flw ft0, 1316(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 160
+  flw ft0, 1320(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 168
+  flw ft0, 1324(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 176
+  flw ft0, 1328(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 184
+  lw t0, 1332(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 192
+  flw ft0, 1336(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 200
+  lw t0, 1340(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 208
+  flw ft0, 1344(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 216
+  flw ft0, 1348(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 224
+  flw ft0, 1352(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 232
+  flw ft0, 1356(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 240
+  lw t0, 1360(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 248
+  lw t0, 1364(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 256
+  flw ft0, 1368(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 264
+  flw ft0, 1372(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 272
+  flw ft0, 1376(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 280
+  lw t0, 1380(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 288
+  flw ft0, 1384(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 296
+  lw t0, 1388(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 304
+  lw t0, 1392(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 312
+  flw ft0, 1396(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 320
+  flw ft0, 1400(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 328
+  flw ft0, 1404(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 336
+  flw ft0, 1408(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 344
+  lw t0, 1412(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 352
+  lw t0, 1416(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 360
+  lw t0, 1420(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 368
+  flw ft0, 1424(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 376
+  flw ft0, 1428(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 384
+  flw ft0, 1432(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 392
+  flw ft0, 1436(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 400
+  flw ft0, 1440(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 408
+  flw ft0, 1444(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 416
+  lw t0, 1448(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 424
+  flw ft0, 1452(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 432
+  lw t0, 1456(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 440
+  flw ft0, 1460(s0)
+  fsw ft0, 0(t4)
+  call params_f40_i24
+  addi sp, sp, 448
+  fsw fa0, 1464(s0)
+  flw fa0, 1464(s0)
+  ld ra, 1472(s0)
+  addi sp, s0, 1488
+  ld s0, 1480(s0)
+  ret
+L5.if.end:
+  li t4, 0
+  sw t4, 1468(s0)
+  flw fa0, 1468(s0)
+  ld ra, 1472(s0)
+  addi sp, s0, 1488
+  ld s0, 1480(s0)
+  ret
+.size params_f40_i24, .-params_f40_i24
+
+.global params_fa40
+.type params_fa40, @function
+params_fa40:
+  addi sp, sp, -1104
+  sd ra, 1088(sp)
+  sd s0, 1096(sp)
+  mv s0, sp
+  sd a0, 0(s0)
+  sd a1, 8(s0)
+  sd a2, 16(s0)
+  sd a3, 24(s0)
+  sd a4, 32(s0)
+  sd a5, 40(s0)
+  sd a6, 48(s0)
+  sd a7, 56(s0)
+  ld t0, 1104(s0)
+  sd t0, 64(s0)
+  ld t0, 1112(s0)
+  sd t0, 72(s0)
+  ld t0, 1120(s0)
+  sd t0, 80(s0)
+  ld t0, 1128(s0)
+  sd t0, 88(s0)
+  ld t0, 1136(s0)
+  sd t0, 96(s0)
+  ld t0, 1144(s0)
+  sd t0, 104(s0)
+  ld t0, 1152(s0)
+  sd t0, 112(s0)
+  ld t0, 1160(s0)
+  sd t0, 120(s0)
+  ld t0, 1168(s0)
+  sd t0, 128(s0)
+  ld t0, 1176(s0)
+  sd t0, 136(s0)
+  ld t0, 1184(s0)
+  sd t0, 144(s0)
+  ld t0, 1192(s0)
+  sd t0, 152(s0)
+  ld t0, 1200(s0)
+  sd t0, 160(s0)
+  ld t0, 1208(s0)
+  sd t0, 168(s0)
+  ld t0, 1216(s0)
+  sd t0, 176(s0)
+  ld t0, 1224(s0)
+  sd t0, 184(s0)
+  ld t0, 1232(s0)
+  sd t0, 192(s0)
+  ld t0, 1240(s0)
+  sd t0, 200(s0)
+  ld t0, 1248(s0)
+  sd t0, 208(s0)
+  ld t0, 1256(s0)
+  sd t0, 216(s0)
+  ld t0, 1264(s0)
+  sd t0, 224(s0)
+  ld t0, 1272(s0)
+  sd t0, 232(s0)
+  ld t0, 1280(s0)
+  sd t0, 240(s0)
+  ld t0, 1288(s0)
+  sd t0, 248(s0)
+  ld t0, 1296(s0)
+  sd t0, 256(s0)
+  ld t0, 1304(s0)
+  sd t0, 264(s0)
+  ld t0, 1312(s0)
+  sd t0, 272(s0)
+  ld t0, 1320(s0)
+  sd t0, 280(s0)
+  ld t0, 1328(s0)
+  sd t0, 288(s0)
+  ld t0, 1336(s0)
+  sd t0, 296(s0)
+  ld t0, 1344(s0)
+  sd t0, 304(s0)
+  ld t0, 1352(s0)
+  sd t0, 312(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 360(s0)
+  ld t0, 0(s0)
+  lw t1, 360(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 368(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 372(s0)
+  ld t0, 8(s0)
+  lw t1, 372(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 380(s0)
+  flw ft0, 368(s0)
+  flw ft1, 380(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 384(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 388(s0)
+  ld t0, 16(s0)
+  lw t1, 388(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 396(s0)
+  flw ft0, 384(s0)
+  flw ft1, 396(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 400(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 404(s0)
+  ld t0, 24(s0)
+  lw t1, 404(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 412(s0)
+  flw ft0, 400(s0)
+  flw ft1, 412(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 416(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 420(s0)
+  ld t0, 32(s0)
+  lw t1, 420(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 428(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 432(s0)
+  ld t0, 40(s0)
+  lw t1, 432(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 440(s0)
+  flw ft0, 428(s0)
+  flw ft1, 440(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 444(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 448(s0)
+  ld t0, 48(s0)
+  lw t1, 448(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 456(s0)
+  flw ft0, 444(s0)
+  flw ft1, 456(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 460(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 464(s0)
+  ld t0, 56(s0)
+  lw t1, 464(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 472(s0)
+  flw ft0, 460(s0)
+  flw ft1, 472(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 476(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 480(s0)
+  ld t0, 64(s0)
+  lw t1, 480(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 488(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 492(s0)
+  ld t0, 72(s0)
+  lw t1, 492(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 500(s0)
+  flw ft0, 488(s0)
+  flw ft1, 500(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 504(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 508(s0)
+  ld t0, 80(s0)
+  lw t1, 508(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 516(s0)
+  flw ft0, 504(s0)
+  flw ft1, 516(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 520(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 524(s0)
+  ld t0, 88(s0)
+  lw t1, 524(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 532(s0)
+  flw ft0, 520(s0)
+  flw ft1, 532(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 536(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 540(s0)
+  ld t0, 96(s0)
+  lw t1, 540(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 548(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 552(s0)
+  ld t0, 104(s0)
+  lw t1, 552(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 560(s0)
+  flw ft0, 548(s0)
+  flw ft1, 560(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 564(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 568(s0)
+  ld t0, 112(s0)
+  lw t1, 568(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 576(s0)
+  flw ft0, 564(s0)
+  flw ft1, 576(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 580(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 584(s0)
+  ld t0, 120(s0)
+  lw t1, 584(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 592(s0)
+  flw ft0, 580(s0)
+  flw ft1, 592(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 596(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 600(s0)
+  ld t0, 128(s0)
+  lw t1, 600(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 608(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 612(s0)
+  ld t0, 136(s0)
+  lw t1, 612(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 620(s0)
+  flw ft0, 608(s0)
+  flw ft1, 620(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 624(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 628(s0)
+  ld t0, 144(s0)
+  lw t1, 628(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 636(s0)
+  flw ft0, 624(s0)
+  flw ft1, 636(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 640(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 644(s0)
+  ld t0, 152(s0)
+  lw t1, 644(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 652(s0)
+  flw ft0, 640(s0)
+  flw ft1, 652(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 656(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 660(s0)
+  ld t0, 160(s0)
+  lw t1, 660(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 668(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 672(s0)
+  ld t0, 168(s0)
+  lw t1, 672(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 680(s0)
+  flw ft0, 668(s0)
+  flw ft1, 680(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 684(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 688(s0)
+  ld t0, 176(s0)
+  lw t1, 688(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 696(s0)
+  flw ft0, 684(s0)
+  flw ft1, 696(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 700(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 704(s0)
+  ld t0, 184(s0)
+  lw t1, 704(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 712(s0)
+  flw ft0, 700(s0)
+  flw ft1, 712(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 716(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 720(s0)
+  ld t0, 192(s0)
+  lw t1, 720(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 728(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 732(s0)
+  ld t0, 200(s0)
+  lw t1, 732(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 740(s0)
+  flw ft0, 728(s0)
+  flw ft1, 740(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 744(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 748(s0)
+  ld t0, 208(s0)
+  lw t1, 748(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 756(s0)
+  flw ft0, 744(s0)
+  flw ft1, 756(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 760(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 764(s0)
+  ld t0, 216(s0)
+  lw t1, 764(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 772(s0)
+  flw ft0, 760(s0)
+  flw ft1, 772(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 776(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 780(s0)
+  ld t0, 224(s0)
+  lw t1, 780(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 788(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 792(s0)
+  ld t0, 232(s0)
+  lw t1, 792(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 800(s0)
+  flw ft0, 788(s0)
+  flw ft1, 800(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 804(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 808(s0)
+  ld t0, 240(s0)
+  lw t1, 808(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 816(s0)
+  flw ft0, 804(s0)
+  flw ft1, 816(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 820(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 824(s0)
+  ld t0, 248(s0)
+  lw t1, 824(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 832(s0)
+  flw ft0, 820(s0)
+  flw ft1, 832(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 836(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 840(s0)
+  ld t0, 256(s0)
+  lw t1, 840(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 848(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 852(s0)
+  ld t0, 264(s0)
+  lw t1, 852(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 860(s0)
+  flw ft0, 848(s0)
+  flw ft1, 860(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 864(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 868(s0)
+  ld t0, 272(s0)
+  lw t1, 868(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 876(s0)
+  flw ft0, 864(s0)
+  flw ft1, 876(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 880(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 884(s0)
+  ld t0, 280(s0)
+  lw t1, 884(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 892(s0)
+  flw ft0, 880(s0)
+  flw ft1, 892(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 896(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 900(s0)
+  ld t0, 288(s0)
+  lw t1, 900(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 908(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 912(s0)
+  ld t0, 296(s0)
+  lw t1, 912(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 920(s0)
+  flw ft0, 908(s0)
+  flw ft1, 920(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 924(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 928(s0)
+  ld t0, 304(s0)
+  lw t1, 928(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 936(s0)
+  flw ft0, 924(s0)
+  flw ft1, 936(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 940(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 944(s0)
+  ld t0, 312(s0)
+  lw t1, 944(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 952(s0)
+  flw ft0, 940(s0)
+  flw ft1, 952(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 956(s0)
+  addi a0, s0, 320
+  li a1, 0
+  li a2, 40
+  call memset
+  flw ft0, 416(s0)
+  addi t0, s0, 320
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 476(s0)
+  addi t0, s0, 320
+  li t1, 1
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 536(s0)
+  addi t0, s0, 320
+  li t1, 2
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 596(s0)
+  addi t0, s0, 320
+  li t1, 3
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 656(s0)
+  addi t0, s0, 320
+  li t1, 4
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 716(s0)
+  addi t0, s0, 320
+  li t1, 5
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 776(s0)
+  addi t0, s0, 320
+  li t1, 6
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 836(s0)
+  addi t0, s0, 320
+  li t1, 7
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 896(s0)
+  addi t0, s0, 320
+  li t1, 8
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 956(s0)
+  addi t0, s0, 320
+  li t1, 9
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1000(s0)
+  ld t0, 312(s0)
+  lw t1, 1000(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1008(s0)
+  li t0, 0
+  fcvt.s.w ft0, t0
+  fsw ft0, 1012(s0)
+  flw ft0, 1008(s0)
+  flw ft1, 1012(s0)
+  feq.s t0, ft0, ft1
+  xori t0, t0, 1
+  sw t0, 1016(s0)
+  lw t0, 1016(s0)
+  sw t0, 1020(s0)
+  lw t0, 1020(s0)
+  li t1, 0
+  sub t0, t0, t1
+  sltiu t1, t0, 1
+  xori t0, t1, 1
+  sw t0, 1024(s0)
+  lw t0, 1024(s0)
+  sw t0, 1028(s0)
+  lw t0, 1028(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1032(s0)
+  flw ft0, 1032(s0)
+  li t4, 0
+  sw t4, 1040(s0)
+  flw ft1, 1040(s0)
+  feq.s t0, ft0, ft1
+  xori t0, t0, 1
+  sw t0, 1036(s0)
+  lw t0, 1036(s0)
+  sw t0, 1044(s0)
+  lw t0, 1044(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1048(s0)
+  flw ft0, 1048(s0)
+  li t4, 0
+  sw t4, 1056(s0)
+  flw ft1, 1056(s0)
+  feq.s t0, ft0, ft1
+  xori t0, t0, 1
+  sw t0, 1052(s0)
+  lw t0, 1052(s0)
+  bnez t0, L9.if.then
+  j L10.if.else
+L9.if.then:
+  li a0, 10
+  addi a1, s0, 320
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  call putfarray
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1064(s0)
+  addi t0, s0, 320
+  lw t1, 1064(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1072(s0)
+  flw fa0, 1072(s0)
+  ld ra, 1088(s0)
+  addi sp, s0, 1104
+  ld s0, 1096(s0)
+  ret
+L10.if.else:
+  addi sp, sp, -256
+  ld a0, 8(s0)
+  ld a1, 16(s0)
+  ld a2, 24(s0)
+  ld a3, 32(s0)
+  ld a4, 40(s0)
+  ld a5, 48(s0)
+  ld a6, 56(s0)
+  ld a7, 64(s0)
+  add t4, sp, zero
+  ld t0, 72(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 8
+  ld t0, 80(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 16
+  ld t0, 88(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  ld t0, 96(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 32
+  ld t0, 104(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 40
+  ld t0, 112(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  ld t0, 120(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 56
+  ld t0, 128(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  ld t0, 136(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 72
+  ld t0, 144(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 80
+  ld t0, 152(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 88
+  ld t0, 160(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 96
+  ld t0, 168(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 104
+  ld t0, 176(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 112
+  ld t0, 184(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 120
+  ld t0, 192(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 128
+  ld t0, 200(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 136
+  ld t0, 208(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 144
+  ld t0, 216(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 152
+  ld t0, 224(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 160
+  ld t0, 232(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 168
+  ld t0, 240(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 176
+  ld t0, 248(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 184
+  ld t0, 256(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 192
+  ld t0, 264(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 200
+  ld t0, 272(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 208
+  ld t0, 280(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 216
+  ld t0, 288(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 224
+  ld t0, 296(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 232
+  ld t0, 304(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 240
+  ld t0, 312(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 248
+  addi t0, s0, 320
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  call params_fa40
+  addi sp, sp, 256
+  fsw fa0, 1080(s0)
+  flw fa0, 1080(s0)
+  ld ra, 1088(s0)
+  addi sp, s0, 1104
+  ld s0, 1096(s0)
+  ret
+L11.if.end:
+  li t4, 0
+  sw t4, 1084(s0)
+  flw fa0, 1084(s0)
+  ld ra, 1088(s0)
+  addi sp, s0, 1104
+  ld s0, 1096(s0)
+  ret
+.size params_fa40, .-params_fa40
+
+.global params_mix
+.type params_mix, @function
+params_mix:
+  addi sp, sp, -1712
+  sd ra, 1696(sp)
+  sd s0, 1704(sp)
+  mv s0, sp
+  fsw fa0, 0(s0)
+  sd a1, 8(s0)
+  sw a2, 16(s0)
+  sd a3, 24(s0)
+  fsw fa4, 32(s0)
+  sw a5, 36(s0)
+  fsw fa6, 40(s0)
+  fsw fa7, 44(s0)
+  ld t0, 1712(s0)
+  sd t0, 48(s0)
+  ld t0, 1720(s0)
+  sd t0, 56(s0)
+  ld t0, 1728(s0)
+  sw t0, 64(s0)
+  ld t0, 1736(s0)
+  sw t0, 68(s0)
+  ld t0, 1744(s0)
+  sd t0, 72(s0)
+  ld t0, 1752(s0)
+  sd t0, 80(s0)
+  ld t0, 1760(s0)
+  sd t0, 88(s0)
+  ld t0, 1768(s0)
+  sw t0, 96(s0)
+  ld t0, 1776(s0)
+  sd t0, 104(s0)
+  ld t0, 1784(s0)
+  sd t0, 112(s0)
+  flw ft0, 1792(s0)
+  fsw ft0, 120(s0)
+  flw ft0, 1800(s0)
+  fsw ft0, 124(s0)
+  flw ft0, 1808(s0)
+  fsw ft0, 128(s0)
+  ld t0, 1816(s0)
+  sd t0, 136(s0)
+  ld t0, 1824(s0)
+  sw t0, 144(s0)
+  flw ft0, 1832(s0)
+  fsw ft0, 148(s0)
+  flw ft0, 1840(s0)
+  fsw ft0, 152(s0)
+  flw ft0, 1848(s0)
+  fsw ft0, 156(s0)
+  ld t0, 1856(s0)
+  sd t0, 160(s0)
+  ld t0, 1864(s0)
+  sd t0, 168(s0)
+  ld t0, 1872(s0)
+  sd t0, 176(s0)
+  ld t0, 1880(s0)
+  sd t0, 184(s0)
+  ld t0, 1888(s0)
+  sd t0, 192(s0)
+  flw ft0, 1896(s0)
+  fsw ft0, 200(s0)
+  flw ft0, 1904(s0)
+  fsw ft0, 204(s0)
+  ld t0, 1912(s0)
+  sd t0, 208(s0)
+  ld t0, 1920(s0)
+  sw t0, 216(s0)
+  ld t0, 1928(s0)
+  sd t0, 224(s0)
+  ld t0, 1936(s0)
+  sd t0, 232(s0)
+  flw ft0, 1944(s0)
+  fsw ft0, 240(s0)
+  flw ft0, 1952(s0)
+  fsw ft0, 244(s0)
+  ld t0, 1960(s0)
+  sd t0, 248(s0)
+  ld t0, 1968(s0)
+  sd t0, 256(s0)
+  ld t0, 1976(s0)
+  sw t0, 264(s0)
+  ld t0, 1984(s0)
+  sw t0, 268(s0)
+  flw ft0, 1992(s0)
+  fsw ft0, 272(s0)
+  flw ft0, 2000(s0)
+  fsw ft0, 276(s0)
+  ld t0, 2008(s0)
+  sd t0, 280(s0)
+  ld t0, 2016(s0)
+  sw t0, 288(s0)
+  ld t0, 2024(s0)
+  sd t0, 296(s0)
+  ld t0, 2032(s0)
+  sw t0, 304(s0)
+  ld t0, 2040(s0)
+  sd t0, 312(s0)
+  li t4, 2048
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sd t0, 320(s0)
+  li t4, 2056
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 328(s0)
+  li t4, 2064
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 332(s0)
+  li t4, 2072
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sd t0, 336(s0)
+  li t4, 2080
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sw t0, 344(s0)
+  li t4, 2088
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sd t0, 352(s0)
+  li t4, 2096
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sd t0, 360(s0)
+  li t4, 2104
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 368(s0)
+  li t4, 2112
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sw t0, 372(s0)
+  li t4, 2120
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 376(s0)
+  li t4, 2128
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sd t0, 384(s0)
+  li t4, 2136
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sd t0, 392(s0)
+  li t4, 2144
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 400(s0)
+  li t4, 2152
+  add t4, s0, t4
+  ld t0, 0(t4)
+  sw t0, 404(s0)
+  flw ft0, 0(s0)
+  fsw ft0, 408(s0)
+  lw t0, 16(s0)
+  sw t0, 412(s0)
+  flw ft0, 32(s0)
+  fsw ft0, 416(s0)
+  lw t0, 36(s0)
+  sw t0, 420(s0)
+  flw ft0, 40(s0)
+  fsw ft0, 424(s0)
+  flw ft0, 44(s0)
+  fsw ft0, 428(s0)
+  lw t0, 64(s0)
+  sw t0, 432(s0)
+  lw t0, 68(s0)
+  sw t0, 436(s0)
+  lw t0, 96(s0)
+  sw t0, 440(s0)
+  flw ft0, 120(s0)
+  fsw ft0, 444(s0)
+  flw ft0, 124(s0)
+  fsw ft0, 448(s0)
+  flw ft0, 128(s0)
+  fsw ft0, 452(s0)
+  lw t0, 144(s0)
+  sw t0, 456(s0)
+  flw ft0, 148(s0)
+  fsw ft0, 460(s0)
+  flw ft0, 152(s0)
+  fsw ft0, 464(s0)
+  flw ft0, 156(s0)
+  fsw ft0, 468(s0)
+  flw ft0, 200(s0)
+  fsw ft0, 472(s0)
+  flw ft0, 204(s0)
+  fsw ft0, 476(s0)
+  lw t0, 216(s0)
+  sw t0, 480(s0)
+  flw ft0, 240(s0)
+  fsw ft0, 484(s0)
+  flw ft0, 244(s0)
+  fsw ft0, 488(s0)
+  lw t0, 264(s0)
+  sw t0, 492(s0)
+  lw t0, 268(s0)
+  sw t0, 496(s0)
+  flw ft0, 272(s0)
+  fsw ft0, 500(s0)
+  flw ft0, 276(s0)
+  fsw ft0, 504(s0)
+  lw t0, 288(s0)
+  sw t0, 508(s0)
+  lw t0, 304(s0)
+  sw t0, 512(s0)
+  flw ft0, 328(s0)
+  fsw ft0, 516(s0)
+  flw ft0, 332(s0)
+  fsw ft0, 520(s0)
+  lw t0, 344(s0)
+  sw t0, 524(s0)
+  flw ft0, 368(s0)
+  fsw ft0, 528(s0)
+  lw t0, 372(s0)
+  sw t0, 532(s0)
+  flw ft0, 376(s0)
+  fsw ft0, 536(s0)
+  flw ft0, 400(s0)
+  fsw ft0, 540(s0)
+  lw t0, 404(s0)
+  sw t0, 544(s0)
+  flw ft0, 408(s0)
+  fsw ft0, 600(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 604(s0)
+  ld t0, 24(s0)
+  lw t1, 604(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 612(s0)
+  flw ft0, 600(s0)
+  flw ft1, 612(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 616(s0)
+  flw ft0, 416(s0)
+  fsw ft0, 620(s0)
+  flw ft0, 616(s0)
+  flw ft1, 620(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 624(s0)
+  flw ft0, 424(s0)
+  fsw ft0, 628(s0)
+  flw ft0, 624(s0)
+  flw ft1, 628(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 632(s0)
+  flw ft0, 428(s0)
+  fsw ft0, 636(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 640(s0)
+  ld t0, 48(s0)
+  lw t1, 640(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 648(s0)
+  flw ft0, 636(s0)
+  flw ft1, 648(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 652(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 656(s0)
+  ld t0, 72(s0)
+  lw t1, 656(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 664(s0)
+  flw ft0, 652(s0)
+  flw ft1, 664(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 668(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 672(s0)
+  ld t0, 104(s0)
+  lw t1, 672(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 680(s0)
+  flw ft0, 668(s0)
+  flw ft1, 680(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 684(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 688(s0)
+  ld t0, 112(s0)
+  lw t1, 688(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 696(s0)
+  flw ft0, 444(s0)
+  fsw ft0, 700(s0)
+  flw ft0, 696(s0)
+  flw ft1, 700(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 704(s0)
+  flw ft0, 448(s0)
+  fsw ft0, 708(s0)
+  flw ft0, 704(s0)
+  flw ft1, 708(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 712(s0)
+  flw ft0, 452(s0)
+  fsw ft0, 716(s0)
+  flw ft0, 712(s0)
+  flw ft1, 716(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 720(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 724(s0)
+  ld t0, 136(s0)
+  lw t1, 724(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 732(s0)
+  flw ft0, 460(s0)
+  fsw ft0, 736(s0)
+  flw ft0, 732(s0)
+  flw ft1, 736(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 740(s0)
+  flw ft0, 464(s0)
+  fsw ft0, 744(s0)
+  flw ft0, 740(s0)
+  flw ft1, 744(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 748(s0)
+  flw ft0, 468(s0)
+  fsw ft0, 752(s0)
+  flw ft0, 748(s0)
+  flw ft1, 752(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 756(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 760(s0)
+  ld t0, 168(s0)
+  lw t1, 760(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 768(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 772(s0)
+  ld t0, 192(s0)
+  lw t1, 772(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 780(s0)
+  flw ft0, 768(s0)
+  flw ft1, 780(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 784(s0)
+  flw ft0, 472(s0)
+  fsw ft0, 788(s0)
+  flw ft0, 784(s0)
+  flw ft1, 788(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 792(s0)
+  flw ft0, 476(s0)
+  fsw ft0, 796(s0)
+  flw ft0, 792(s0)
+  flw ft1, 796(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 800(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 804(s0)
+  ld t0, 224(s0)
+  lw t1, 804(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 812(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 816(s0)
+  ld t0, 232(s0)
+  lw t1, 816(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 824(s0)
+  flw ft0, 812(s0)
+  flw ft1, 824(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 828(s0)
+  flw ft0, 484(s0)
+  fsw ft0, 832(s0)
+  flw ft0, 828(s0)
+  flw ft1, 832(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 836(s0)
+  flw ft0, 488(s0)
+  fsw ft0, 840(s0)
+  flw ft0, 836(s0)
+  flw ft1, 840(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 844(s0)
+  flw ft0, 500(s0)
+  fsw ft0, 848(s0)
+  flw ft0, 504(s0)
+  fsw ft0, 852(s0)
+  flw ft0, 848(s0)
+  flw ft1, 852(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 856(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 860(s0)
+  ld t0, 296(s0)
+  lw t1, 860(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 868(s0)
+  flw ft0, 856(s0)
+  flw ft1, 868(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 872(s0)
+  flw ft0, 516(s0)
+  fsw ft0, 876(s0)
+  flw ft0, 872(s0)
+  flw ft1, 876(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 880(s0)
+  flw ft0, 520(s0)
+  fsw ft0, 884(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 888(s0)
+  ld t0, 336(s0)
+  lw t1, 888(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 896(s0)
+  flw ft0, 884(s0)
+  flw ft1, 896(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 900(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 904(s0)
+  ld t0, 360(s0)
+  lw t1, 904(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 912(s0)
+  flw ft0, 900(s0)
+  flw ft1, 912(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 916(s0)
+  flw ft0, 528(s0)
+  fsw ft0, 920(s0)
+  flw ft0, 916(s0)
+  flw ft1, 920(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 924(s0)
+  flw ft0, 536(s0)
+  fsw ft0, 928(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 932(s0)
+  ld t0, 384(s0)
+  lw t1, 932(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 940(s0)
+  flw ft0, 928(s0)
+  flw ft1, 940(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 944(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 948(s0)
+  ld t0, 392(s0)
+  lw t1, 948(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 956(s0)
+  flw ft0, 944(s0)
+  flw ft1, 956(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 960(s0)
+  flw ft0, 540(s0)
+  fsw ft0, 964(s0)
+  flw ft0, 960(s0)
+  flw ft1, 964(s0)
+  fadd.s ft0, ft0, ft1
+  fsw ft0, 968(s0)
+  addi a0, s0, 560
+  li a1, 0
+  li a2, 40
+  call memset
+  flw ft0, 632(s0)
+  addi t0, s0, 560
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 684(s0)
+  addi t0, s0, 560
+  li t1, 1
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 720(s0)
+  addi t0, s0, 560
+  li t1, 2
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 756(s0)
+  addi t0, s0, 560
+  li t1, 3
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 800(s0)
+  addi t0, s0, 560
+  li t1, 4
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 844(s0)
+  addi t0, s0, 560
+  li t1, 5
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 880(s0)
+  addi t0, s0, 560
+  li t1, 6
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 924(s0)
+  addi t0, s0, 560
+  li t1, 7
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  flw ft0, 968(s0)
+  addi t0, s0, 560
+  li t1, 8
+  slli t1, t1, 2
+  add t0, t0, t1
+  fsw ft0, 0(t0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1080(s0)
+  ld t0, 8(s0)
+  lw t1, 1080(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1088(s0)
+  lw t0, 412(s0)
+  sw t0, 1092(s0)
+  lw t0, 1088(s0)
+  lw t1, 1092(s0)
+  add t0, t0, t1
+  sw t0, 1096(s0)
+  lw t0, 420(s0)
+  sw t0, 1100(s0)
+  lw t0, 1096(s0)
+  lw t1, 1100(s0)
+  add t0, t0, t1
+  sw t0, 1104(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1108(s0)
+  ld t0, 56(s0)
+  lw t1, 1108(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1116(s0)
+  lw t0, 432(s0)
+  sw t0, 1120(s0)
+  lw t0, 1116(s0)
+  lw t1, 1120(s0)
+  add t0, t0, t1
+  sw t0, 1124(s0)
+  lw t0, 436(s0)
+  sw t0, 1128(s0)
+  lw t0, 1124(s0)
+  lw t1, 1128(s0)
+  add t0, t0, t1
+  sw t0, 1132(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1136(s0)
+  ld t0, 80(s0)
+  lw t1, 1136(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1144(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1148(s0)
+  ld t0, 88(s0)
+  lw t1, 1148(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1156(s0)
+  lw t0, 1144(s0)
+  lw t1, 1156(s0)
+  add t0, t0, t1
+  sw t0, 1160(s0)
+  lw t0, 440(s0)
+  sw t0, 1164(s0)
+  lw t0, 1160(s0)
+  lw t1, 1164(s0)
+  add t0, t0, t1
+  sw t0, 1168(s0)
+  lw t0, 456(s0)
+  sw t0, 1172(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1176(s0)
+  ld t0, 160(s0)
+  lw t1, 1176(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1184(s0)
+  lw t0, 1172(s0)
+  lw t1, 1184(s0)
+  add t0, t0, t1
+  sw t0, 1188(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1192(s0)
+  ld t0, 176(s0)
+  lw t1, 1192(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1200(s0)
+  lw t0, 1188(s0)
+  lw t1, 1200(s0)
+  add t0, t0, t1
+  sw t0, 1204(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1208(s0)
+  ld t0, 184(s0)
+  lw t1, 1208(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1216(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1220(s0)
+  ld t0, 208(s0)
+  lw t1, 1220(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1228(s0)
+  lw t0, 1216(s0)
+  lw t1, 1228(s0)
+  add t0, t0, t1
+  sw t0, 1232(s0)
+  lw t0, 480(s0)
+  sw t0, 1236(s0)
+  lw t0, 1232(s0)
+  lw t1, 1236(s0)
+  add t0, t0, t1
+  sw t0, 1240(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1244(s0)
+  ld t0, 248(s0)
+  lw t1, 1244(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1252(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1256(s0)
+  ld t0, 256(s0)
+  lw t1, 1256(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1264(s0)
+  lw t0, 1252(s0)
+  lw t1, 1264(s0)
+  add t0, t0, t1
+  sw t0, 1268(s0)
+  lw t0, 492(s0)
+  sw t0, 1272(s0)
+  lw t0, 1268(s0)
+  lw t1, 1272(s0)
+  add t0, t0, t1
+  sw t0, 1276(s0)
+  lw t0, 496(s0)
+  sw t0, 1280(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1284(s0)
+  ld t0, 280(s0)
+  lw t1, 1284(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1292(s0)
+  lw t0, 1280(s0)
+  lw t1, 1292(s0)
+  add t0, t0, t1
+  sw t0, 1296(s0)
+  lw t0, 508(s0)
+  sw t0, 1300(s0)
+  lw t0, 1296(s0)
+  lw t1, 1300(s0)
+  add t0, t0, t1
+  sw t0, 1304(s0)
+  lw t0, 512(s0)
+  sw t0, 1308(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1312(s0)
+  ld t0, 312(s0)
+  lw t1, 1312(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1320(s0)
+  lw t0, 1308(s0)
+  lw t1, 1320(s0)
+  add t0, t0, t1
+  sw t0, 1324(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1328(s0)
+  ld t0, 320(s0)
+  lw t1, 1328(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1336(s0)
+  lw t0, 1324(s0)
+  lw t1, 1336(s0)
+  add t0, t0, t1
+  sw t0, 1340(s0)
+  lw t0, 524(s0)
+  sw t0, 1344(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1348(s0)
+  ld t0, 352(s0)
+  lw t1, 1348(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1356(s0)
+  lw t0, 1344(s0)
+  lw t1, 1356(s0)
+  add t0, t0, t1
+  sw t0, 1360(s0)
+  lw t0, 532(s0)
+  sw t0, 1364(s0)
+  lw t0, 1360(s0)
+  lw t1, 1364(s0)
+  add t0, t0, t1
+  sw t0, 1368(s0)
+  lw t0, 544(s0)
+  sw t0, 1372(s0)
+  lw t0, 1368(s0)
+  lw t1, 1372(s0)
+  add t0, t0, t1
+  sw t0, 1376(s0)
+  addi a0, s0, 1040
+  li a1, 0
+  li a2, 40
+  call memset
+  lw t2, 1104(s0)
+  addi t0, s0, 1040
+  li t1, 0
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1132(s0)
+  addi t0, s0, 1040
+  li t1, 1
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1168(s0)
+  addi t0, s0, 1040
+  li t1, 2
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1204(s0)
+  addi t0, s0, 1040
+  li t1, 3
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1240(s0)
+  addi t0, s0, 1040
+  li t1, 4
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1276(s0)
+  addi t0, s0, 1040
+  li t1, 5
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1304(s0)
+  addi t0, s0, 1040
+  li t1, 6
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1340(s0)
+  addi t0, s0, 1040
+  li t1, 7
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t2, 1376(s0)
+  addi t0, s0, 1040
+  li t1, 8
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t0, 544(s0)
+  sw t0, 1416(s0)
+  lw t0, 1416(s0)
+  li t1, 0
+  sub t0, t0, t1
+  sltiu t1, t0, 1
+  xori t0, t1, 1
+  sw t0, 1420(s0)
+  lw t0, 1420(s0)
+  bnez t0, L12.if.then
+  j L13.if.else
+L12.if.then:
+  li a0, 10
+  addi a1, s0, 560
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  call putfarray
+  li a0, 10
+  addi a1, s0, 1040
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  call putarray
+  li t0, 0
+  sw t0, 1432(s0)
+  j L15.while.cond
+L15.while.cond:
+  lw t0, 1432(s0)
+  sw t0, 1436(s0)
+  lw t0, 1436(s0)
+  li t1, 10
+  slt t0, t0, t1
+  sw t0, 1440(s0)
+  lw t0, 1440(s0)
+  bnez t0, L16.while.body
+  j L17.while.end
+L16.while.body:
+  lw t0, 1432(s0)
+  sw t0, 1444(s0)
+  addi t0, s0, 1040
+  lw t1, 1444(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1452(s0)
+  lw t0, 1432(s0)
+  sw t0, 1456(s0)
+  addi t0, s0, 560
+  lw t1, 1456(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1464(s0)
+  lw t0, 1452(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1468(s0)
+  flw ft0, 1468(s0)
+  flw ft1, 1464(s0)
+  fsub.s ft0, ft0, ft1
+  fsw ft0, 1472(s0)
+  lw t0, 1432(s0)
+  sw t0, 1476(s0)
+  flw ft0, 1472(s0)
+  fcvt.w.s t0, ft0, rtz
+  sw t0, 1484(s0)
+  lw t2, 1484(s0)
+  addi t0, s0, 1040
+  lw t1, 1476(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sw t2, 0(t0)
+  lw t0, 1432(s0)
+  sw t0, 1488(s0)
+  lw t0, 1488(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 1492(s0)
+  lw t0, 1492(s0)
+  sw t0, 1432(s0)
+  j L15.while.cond
+L17.while.end:
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1496(s0)
+  addi t0, s0, 1040
+  lw t1, 1496(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1504(s0)
+  addi t0, s0, 560
+  li t1, 8
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1512(s0)
+  lw t0, 1504(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1516(s0)
+  flw ft0, 1516(s0)
+  flw ft1, 1512(s0)
+  fmul.s ft0, ft0, ft1
+  fsw ft0, 1520(s0)
+  flw ft0, 1520(s0)
+  fcvt.w.s t0, ft0, rtz
+  sw t0, 1524(s0)
+  lw a0, 1524(s0)
+  ld ra, 1696(s0)
+  addi sp, s0, 1712
+  ld s0, 1704(s0)
+  ret
+L13.if.else:
+  flw ft0, 408(s0)
+  fsw ft0, 1528(s0)
+  lw t0, 412(s0)
+  sw t0, 1536(s0)
+  flw ft0, 416(s0)
+  fsw ft0, 1544(s0)
+  lw t0, 420(s0)
+  sw t0, 1548(s0)
+  flw ft0, 424(s0)
+  fsw ft0, 1552(s0)
+  flw ft0, 428(s0)
+  fsw ft0, 1556(s0)
+  lw t0, 432(s0)
+  sw t0, 1560(s0)
+  lw t0, 436(s0)
+  sw t0, 1564(s0)
+  lw t0, 440(s0)
+  sw t0, 1568(s0)
+  flw ft0, 444(s0)
+  fsw ft0, 1572(s0)
+  flw ft0, 448(s0)
+  fsw ft0, 1576(s0)
+  flw ft0, 452(s0)
+  fsw ft0, 1580(s0)
+  lw t0, 456(s0)
+  sw t0, 1584(s0)
+  flw ft0, 460(s0)
+  fsw ft0, 1588(s0)
+  flw ft0, 464(s0)
+  fsw ft0, 1592(s0)
+  flw ft0, 468(s0)
+  fsw ft0, 1596(s0)
+  flw ft0, 472(s0)
+  fsw ft0, 1600(s0)
+  flw ft0, 476(s0)
+  fsw ft0, 1604(s0)
+  lw t0, 480(s0)
+  sw t0, 1608(s0)
+  flw ft0, 484(s0)
+  fsw ft0, 1612(s0)
+  flw ft0, 488(s0)
+  fsw ft0, 1616(s0)
+  lw t0, 492(s0)
+  sw t0, 1620(s0)
+  lw t0, 496(s0)
+  sw t0, 1624(s0)
+  flw ft0, 500(s0)
+  fsw ft0, 1628(s0)
+  flw ft0, 504(s0)
+  fsw ft0, 1632(s0)
+  lw t0, 508(s0)
+  sw t0, 1636(s0)
+  lw t0, 512(s0)
+  sw t0, 1640(s0)
+  flw ft0, 516(s0)
+  fsw ft0, 1644(s0)
+  flw ft0, 520(s0)
+  fsw ft0, 1648(s0)
+  lw t0, 524(s0)
+  sw t0, 1652(s0)
+  flw ft0, 528(s0)
+  fsw ft0, 1656(s0)
+  lw t0, 532(s0)
+  sw t0, 1660(s0)
+  flw ft0, 536(s0)
+  fsw ft0, 1664(s0)
+  lw t0, 544(s0)
+  sw t0, 1668(s0)
+  flw ft0, 540(s0)
+  fsw ft0, 1672(s0)
+  lw t0, 1668(s0)
+  fcvt.s.w ft0, t0
+  fsw ft0, 1676(s0)
+  flw ft0, 1672(s0)
+  fcvt.w.s t0, ft0, rtz
+  sw t0, 1680(s0)
+  addi sp, sp, -448
+  flw fa0, 1528(s0)
+  addi a1, s0, 1040
+  li t1, 0
+  slli t1, t1, 2
+  add a1, a1, t1
+  lw a2, 1536(s0)
+  addi a3, s0, 560
+  li t1, 0
+  slli t1, t1, 2
+  add a3, a3, t1
+  flw fa4, 1544(s0)
+  lw a5, 1548(s0)
+  flw fa6, 1552(s0)
+  flw fa7, 1556(s0)
+  add t4, sp, zero
+  ld t0, 48(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 8
+  ld t0, 56(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 16
+  lw t0, 1560(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  lw t0, 1564(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 32
+  ld t0, 72(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 40
+  ld t0, 80(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  ld t0, 88(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 56
+  lw t0, 1568(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  ld t0, 104(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 72
+  ld t0, 112(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 80
+  flw ft0, 1572(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 88
+  flw ft0, 1576(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 96
+  flw ft0, 1580(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 104
+  ld t0, 136(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 112
+  lw t0, 1584(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 120
+  flw ft0, 1588(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 128
+  flw ft0, 1592(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 136
+  flw ft0, 1596(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 144
+  ld t0, 160(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 152
+  ld t0, 168(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 160
+  ld t0, 176(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 168
+  ld t0, 184(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 176
+  ld t0, 192(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 184
+  flw ft0, 1600(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 192
+  flw ft0, 1604(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 200
+  ld t0, 208(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 208
+  lw t0, 1608(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 216
+  ld t0, 224(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 224
+  ld t0, 232(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 232
+  flw ft0, 1612(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 240
+  flw ft0, 1616(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 248
+  ld t0, 248(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 256
+  ld t0, 256(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 264
+  lw t0, 1620(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 272
+  lw t0, 1624(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 280
+  flw ft0, 1628(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 288
+  flw ft0, 1632(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 296
+  ld t0, 280(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 304
+  lw t0, 1636(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 312
+  ld t0, 296(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 320
+  lw t0, 1640(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 328
+  ld t0, 312(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 336
+  ld t0, 320(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 344
+  flw ft0, 1644(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 352
+  flw ft0, 1648(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 360
+  ld t0, 336(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 368
+  lw t0, 1652(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 376
+  ld t0, 352(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 384
+  ld t0, 360(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 392
+  flw ft0, 1656(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 400
+  lw t0, 1660(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 408
+  flw ft0, 1664(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 416
+  ld t0, 384(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 424
+  ld t0, 392(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 432
+  flw ft0, 1676(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 440
+  lw t0, 1680(s0)
+  sd t0, 0(t4)
+  call params_mix
+  addi sp, sp, 448
+  sw a0, 1684(s0)
+  lw a0, 1684(s0)
+  ld ra, 1696(s0)
+  addi sp, s0, 1712
+  ld s0, 1704(s0)
+  ret
+L14.if.end:
+  li a0, 0
+  ld ra, 1696(s0)
+  addi sp, s0, 1712
+  ld s0, 1704(s0)
+  ret
+.size params_mix, .-params_mix
+
+.global main
+.type main, @function
+main:
+  li t4, -4352
+  add sp, sp, t4
+  li t4, 4336
+  add t4, sp, t4
+  sd ra, 0(t4)
+  li t4, 4344
+  add t4, sp, t4
+  sd s0, 0(t4)
+  mv s0, sp
+  addi a0, s0, 0
+  li a1, 0
+  li a2, 480
+  call memset
+  addi a0, s0, 576
+  li a1, 0
+  li a2, 288
+  call memset
+  li t0, 0
+  sw t0, 864(s0)
+  call getint
+  sw a0, 868(s0)
+  lw t0, 868(s0)
+  la t1, k
+  sw t0, 0(t1)
+  li t0, 0
+  sw t0, 864(s0)
+  j L18.while.cond
+L18.while.cond:
+  lw t0, 864(s0)
+  sw t0, 872(s0)
+  lw t0, 872(s0)
+  li t1, 40
+  slt t0, t0, t1
+  sw t0, 876(s0)
+  lw t0, 876(s0)
+  bnez t0, L19.while.body
+  j L20.while.end
+L19.while.body:
+  lw t0, 864(s0)
+  sw t0, 880(s0)
+  lw t0, 880(s0)
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 884(s0)
+  addi a0, s0, 0
+  lw t1, 884(s0)
+  slli t1, t1, 2
+  add a0, a0, t1
+  call getfarray
+  sw a0, 892(s0)
+  lw t0, 864(s0)
+  sw t0, 896(s0)
+  lw t0, 896(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 900(s0)
+  lw t0, 900(s0)
+  sw t0, 864(s0)
+  j L18.while.cond
+L20.while.end:
+  li t0, 0
+  sw t0, 864(s0)
+  j L21.while.cond
+L21.while.cond:
+  lw t0, 864(s0)
+  sw t0, 904(s0)
+  lw t0, 904(s0)
+  li t1, 24
+  slt t0, t0, t1
+  sw t0, 908(s0)
+  lw t0, 908(s0)
+  bnez t0, L22.while.body
+  j L23.while.end
+L22.while.body:
+  lw t0, 864(s0)
+  sw t0, 912(s0)
+  lw t0, 912(s0)
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 916(s0)
+  addi a0, s0, 576
+  lw t1, 916(s0)
+  slli t1, t1, 2
+  add a0, a0, t1
+  call getarray
+  sw a0, 924(s0)
+  lw t0, 864(s0)
+  sw t0, 928(s0)
+  lw t0, 928(s0)
+  li t1, 1
+  add t0, t0, t1
+  sw t0, 932(s0)
+  lw t0, 932(s0)
+  sw t0, 864(s0)
+  j L21.while.cond
+L23.while.end:
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 940(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 944(s0)
+  lw t0, 940(s0)
+  lw t1, 944(s0)
+  add t0, t0, t1
+  sw t0, 948(s0)
+  addi t0, s0, 0
+  lw t1, 948(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 956(s0)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 960(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 964(s0)
+  lw t0, 960(s0)
+  lw t1, 964(s0)
+  add t0, t0, t1
+  sw t0, 968(s0)
+  addi t0, s0, 0
+  lw t1, 968(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 976(s0)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 980(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 984(s0)
+  lw t0, 980(s0)
+  lw t1, 984(s0)
+  add t0, t0, t1
+  sw t0, 988(s0)
+  addi t0, s0, 0
+  lw t1, 988(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 996(s0)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1000(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1004(s0)
+  lw t0, 1000(s0)
+  lw t1, 1004(s0)
+  add t0, t0, t1
+  sw t0, 1008(s0)
+  addi t0, s0, 0
+  lw t1, 1008(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1016(s0)
+  li t0, 4
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1020(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1024(s0)
+  lw t0, 1020(s0)
+  lw t1, 1024(s0)
+  add t0, t0, t1
+  sw t0, 1028(s0)
+  addi t0, s0, 0
+  lw t1, 1028(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1036(s0)
+  li t0, 5
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1040(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1044(s0)
+  lw t0, 1040(s0)
+  lw t1, 1044(s0)
+  add t0, t0, t1
+  sw t0, 1048(s0)
+  addi t0, s0, 0
+  lw t1, 1048(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1056(s0)
+  li t0, 6
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1060(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1064(s0)
+  lw t0, 1060(s0)
+  lw t1, 1064(s0)
+  add t0, t0, t1
+  sw t0, 1068(s0)
+  addi t0, s0, 0
+  lw t1, 1068(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1076(s0)
+  li t0, 7
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1080(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1084(s0)
+  lw t0, 1080(s0)
+  lw t1, 1084(s0)
+  add t0, t0, t1
+  sw t0, 1088(s0)
+  addi t0, s0, 0
+  lw t1, 1088(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1096(s0)
+  li t0, 8
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1100(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1104(s0)
+  lw t0, 1100(s0)
+  lw t1, 1104(s0)
+  add t0, t0, t1
+  sw t0, 1108(s0)
+  addi t0, s0, 0
+  lw t1, 1108(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1116(s0)
+  li t0, 9
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1120(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1124(s0)
+  lw t0, 1120(s0)
+  lw t1, 1124(s0)
+  add t0, t0, t1
+  sw t0, 1128(s0)
+  addi t0, s0, 0
+  lw t1, 1128(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1136(s0)
+  li t0, 10
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1140(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1144(s0)
+  lw t0, 1140(s0)
+  lw t1, 1144(s0)
+  add t0, t0, t1
+  sw t0, 1148(s0)
+  addi t0, s0, 0
+  lw t1, 1148(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1156(s0)
+  li t0, 11
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1160(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1164(s0)
+  lw t0, 1160(s0)
+  lw t1, 1164(s0)
+  add t0, t0, t1
+  sw t0, 1168(s0)
+  addi t0, s0, 0
+  lw t1, 1168(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1176(s0)
+  li t0, 12
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1180(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1184(s0)
+  lw t0, 1180(s0)
+  lw t1, 1184(s0)
+  add t0, t0, t1
+  sw t0, 1188(s0)
+  addi t0, s0, 0
+  lw t1, 1188(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1196(s0)
+  li t0, 13
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1200(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1204(s0)
+  lw t0, 1200(s0)
+  lw t1, 1204(s0)
+  add t0, t0, t1
+  sw t0, 1208(s0)
+  addi t0, s0, 0
+  lw t1, 1208(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1216(s0)
+  li t0, 14
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1220(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1224(s0)
+  lw t0, 1220(s0)
+  lw t1, 1224(s0)
+  add t0, t0, t1
+  sw t0, 1228(s0)
+  addi t0, s0, 0
+  lw t1, 1228(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1236(s0)
+  li t0, 15
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1240(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1244(s0)
+  lw t0, 1240(s0)
+  lw t1, 1244(s0)
+  add t0, t0, t1
+  sw t0, 1248(s0)
+  addi t0, s0, 0
+  lw t1, 1248(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1256(s0)
+  li t0, 16
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1260(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1264(s0)
+  lw t0, 1260(s0)
+  lw t1, 1264(s0)
+  add t0, t0, t1
+  sw t0, 1268(s0)
+  addi t0, s0, 0
+  lw t1, 1268(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1276(s0)
+  li t0, 17
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1280(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1284(s0)
+  lw t0, 1280(s0)
+  lw t1, 1284(s0)
+  add t0, t0, t1
+  sw t0, 1288(s0)
+  addi t0, s0, 0
+  lw t1, 1288(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1296(s0)
+  li t0, 18
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1300(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1304(s0)
+  lw t0, 1300(s0)
+  lw t1, 1304(s0)
+  add t0, t0, t1
+  sw t0, 1308(s0)
+  addi t0, s0, 0
+  lw t1, 1308(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1316(s0)
+  li t0, 19
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1320(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1324(s0)
+  lw t0, 1320(s0)
+  lw t1, 1324(s0)
+  add t0, t0, t1
+  sw t0, 1328(s0)
+  addi t0, s0, 0
+  lw t1, 1328(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1336(s0)
+  li t0, 20
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1340(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1344(s0)
+  lw t0, 1340(s0)
+  lw t1, 1344(s0)
+  add t0, t0, t1
+  sw t0, 1348(s0)
+  addi t0, s0, 0
+  lw t1, 1348(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1356(s0)
+  li t0, 21
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1360(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1364(s0)
+  lw t0, 1360(s0)
+  lw t1, 1364(s0)
+  add t0, t0, t1
+  sw t0, 1368(s0)
+  addi t0, s0, 0
+  lw t1, 1368(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1376(s0)
+  li t0, 22
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1380(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1384(s0)
+  lw t0, 1380(s0)
+  lw t1, 1384(s0)
+  add t0, t0, t1
+  sw t0, 1388(s0)
+  addi t0, s0, 0
+  lw t1, 1388(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1396(s0)
+  li t0, 23
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1400(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1404(s0)
+  lw t0, 1400(s0)
+  lw t1, 1404(s0)
+  add t0, t0, t1
+  sw t0, 1408(s0)
+  addi t0, s0, 0
+  lw t1, 1408(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1416(s0)
+  li t0, 24
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1420(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1424(s0)
+  lw t0, 1420(s0)
+  lw t1, 1424(s0)
+  add t0, t0, t1
+  sw t0, 1428(s0)
+  addi t0, s0, 0
+  lw t1, 1428(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1436(s0)
+  li t0, 25
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1440(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1444(s0)
+  lw t0, 1440(s0)
+  lw t1, 1444(s0)
+  add t0, t0, t1
+  sw t0, 1448(s0)
+  addi t0, s0, 0
+  lw t1, 1448(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1456(s0)
+  li t0, 26
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1460(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1464(s0)
+  lw t0, 1460(s0)
+  lw t1, 1464(s0)
+  add t0, t0, t1
+  sw t0, 1468(s0)
+  addi t0, s0, 0
+  lw t1, 1468(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1476(s0)
+  li t0, 27
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1480(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1484(s0)
+  lw t0, 1480(s0)
+  lw t1, 1484(s0)
+  add t0, t0, t1
+  sw t0, 1488(s0)
+  addi t0, s0, 0
+  lw t1, 1488(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1496(s0)
+  li t0, 28
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1500(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1504(s0)
+  lw t0, 1500(s0)
+  lw t1, 1504(s0)
+  add t0, t0, t1
+  sw t0, 1508(s0)
+  addi t0, s0, 0
+  lw t1, 1508(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1516(s0)
+  li t0, 29
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1520(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1524(s0)
+  lw t0, 1520(s0)
+  lw t1, 1524(s0)
+  add t0, t0, t1
+  sw t0, 1528(s0)
+  addi t0, s0, 0
+  lw t1, 1528(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1536(s0)
+  li t0, 30
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1540(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1544(s0)
+  lw t0, 1540(s0)
+  lw t1, 1544(s0)
+  add t0, t0, t1
+  sw t0, 1548(s0)
+  addi t0, s0, 0
+  lw t1, 1548(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1556(s0)
+  li t0, 31
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1560(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1564(s0)
+  lw t0, 1560(s0)
+  lw t1, 1564(s0)
+  add t0, t0, t1
+  sw t0, 1568(s0)
+  addi t0, s0, 0
+  lw t1, 1568(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1576(s0)
+  li t0, 32
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1580(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1584(s0)
+  lw t0, 1580(s0)
+  lw t1, 1584(s0)
+  add t0, t0, t1
+  sw t0, 1588(s0)
+  addi t0, s0, 0
+  lw t1, 1588(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1596(s0)
+  li t0, 33
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1600(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1604(s0)
+  lw t0, 1600(s0)
+  lw t1, 1604(s0)
+  add t0, t0, t1
+  sw t0, 1608(s0)
+  addi t0, s0, 0
+  lw t1, 1608(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1616(s0)
+  li t0, 34
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1620(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1624(s0)
+  lw t0, 1620(s0)
+  lw t1, 1624(s0)
+  add t0, t0, t1
+  sw t0, 1628(s0)
+  addi t0, s0, 0
+  lw t1, 1628(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1636(s0)
+  li t0, 35
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1640(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1644(s0)
+  lw t0, 1640(s0)
+  lw t1, 1644(s0)
+  add t0, t0, t1
+  sw t0, 1648(s0)
+  addi t0, s0, 0
+  lw t1, 1648(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1656(s0)
+  li t0, 36
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1660(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1664(s0)
+  lw t0, 1660(s0)
+  lw t1, 1664(s0)
+  add t0, t0, t1
+  sw t0, 1668(s0)
+  addi t0, s0, 0
+  lw t1, 1668(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1676(s0)
+  li t0, 37
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1680(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1684(s0)
+  lw t0, 1680(s0)
+  lw t1, 1684(s0)
+  add t0, t0, t1
+  sw t0, 1688(s0)
+  addi t0, s0, 0
+  lw t1, 1688(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1696(s0)
+  li t0, 38
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1700(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1704(s0)
+  lw t0, 1700(s0)
+  lw t1, 1704(s0)
+  add t0, t0, t1
+  sw t0, 1708(s0)
+  addi t0, s0, 0
+  lw t1, 1708(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1716(s0)
+  li t0, 39
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1720(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1724(s0)
+  lw t0, 1720(s0)
+  lw t1, 1724(s0)
+  add t0, t0, t1
+  sw t0, 1728(s0)
+  addi t0, s0, 0
+  lw t1, 1728(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1736(s0)
+  addi sp, sp, -256
+  flw fa0, 956(s0)
+  flw fa1, 976(s0)
+  flw fa2, 996(s0)
+  flw fa3, 1016(s0)
+  flw fa4, 1036(s0)
+  flw fa5, 1056(s0)
+  flw fa6, 1076(s0)
+  flw fa7, 1096(s0)
+  add t4, sp, zero
+  flw ft0, 1116(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 8
+  flw ft0, 1136(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 16
+  flw ft0, 1156(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 24
+  flw ft0, 1176(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 32
+  flw ft0, 1196(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 40
+  flw ft0, 1216(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 48
+  flw ft0, 1236(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 56
+  flw ft0, 1256(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 64
+  flw ft0, 1276(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 72
+  flw ft0, 1296(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 80
+  flw ft0, 1316(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 88
+  flw ft0, 1336(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 96
+  flw ft0, 1356(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 104
+  flw ft0, 1376(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 112
+  flw ft0, 1396(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 120
+  flw ft0, 1416(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 128
+  flw ft0, 1436(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 136
+  flw ft0, 1456(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 144
+  flw ft0, 1476(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 152
+  flw ft0, 1496(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 160
+  flw ft0, 1516(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 168
+  flw ft0, 1536(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 176
+  flw ft0, 1556(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 184
+  flw ft0, 1576(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 192
+  flw ft0, 1596(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 200
+  flw ft0, 1616(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 208
+  flw ft0, 1636(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 216
+  flw ft0, 1656(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 224
+  flw ft0, 1676(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 232
+  flw ft0, 1696(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 240
+  flw ft0, 1716(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 248
+  flw ft0, 1736(s0)
+  fsw ft0, 0(t4)
+  call params_f40
+  addi sp, sp, 256
+  fsw fa0, 1740(s0)
+  flw ft0, 1740(s0)
+  fsw ft0, 936(s0)
+  li t0, 23
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1748(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1752(s0)
+  lw t0, 1748(s0)
+  lw t1, 1752(s0)
+  add t0, t0, t1
+  sw t0, 1756(s0)
+  addi t0, s0, 576
+  lw t1, 1756(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1764(s0)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1768(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1772(s0)
+  lw t0, 1768(s0)
+  lw t1, 1772(s0)
+  add t0, t0, t1
+  sw t0, 1776(s0)
+  addi t0, s0, 576
+  lw t1, 1776(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1784(s0)
+  li t0, 6
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1788(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1792(s0)
+  lw t0, 1788(s0)
+  lw t1, 1792(s0)
+  add t0, t0, t1
+  sw t0, 1796(s0)
+  addi t0, s0, 576
+  lw t1, 1796(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1804(s0)
+  li t0, 4
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1808(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1812(s0)
+  lw t0, 1808(s0)
+  lw t1, 1812(s0)
+  add t0, t0, t1
+  sw t0, 1816(s0)
+  addi t0, s0, 0
+  lw t1, 1816(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1824(s0)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1828(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1832(s0)
+  lw t0, 1828(s0)
+  lw t1, 1832(s0)
+  add t0, t0, t1
+  sw t0, 1836(s0)
+  addi t0, s0, 576
+  lw t1, 1836(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1844(s0)
+  li t0, 4
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1848(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1852(s0)
+  lw t0, 1848(s0)
+  lw t1, 1852(s0)
+  add t0, t0, t1
+  sw t0, 1856(s0)
+  addi t0, s0, 576
+  lw t1, 1856(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1864(s0)
+  li t0, 5
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1868(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1872(s0)
+  lw t0, 1868(s0)
+  lw t1, 1872(s0)
+  add t0, t0, t1
+  sw t0, 1876(s0)
+  addi t0, s0, 576
+  lw t1, 1876(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1884(s0)
+  li t0, 8
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1888(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1892(s0)
+  lw t0, 1888(s0)
+  lw t1, 1892(s0)
+  add t0, t0, t1
+  sw t0, 1896(s0)
+  addi t0, s0, 0
+  lw t1, 1896(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1904(s0)
+  li t0, 15
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1908(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1912(s0)
+  lw t0, 1908(s0)
+  lw t1, 1912(s0)
+  add t0, t0, t1
+  sw t0, 1916(s0)
+  addi t0, s0, 0
+  lw t1, 1916(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1924(s0)
+  li t0, 7
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1928(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1932(s0)
+  lw t0, 1928(s0)
+  lw t1, 1932(s0)
+  add t0, t0, t1
+  sw t0, 1936(s0)
+  addi t0, s0, 0
+  lw t1, 1936(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1944(s0)
+  li t0, 22
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1948(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1952(s0)
+  lw t0, 1948(s0)
+  lw t1, 1952(s0)
+  add t0, t0, t1
+  sw t0, 1956(s0)
+  addi t0, s0, 576
+  lw t1, 1956(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 1964(s0)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1968(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1972(s0)
+  lw t0, 1968(s0)
+  lw t1, 1972(s0)
+  add t0, t0, t1
+  sw t0, 1976(s0)
+  addi t0, s0, 0
+  lw t1, 1976(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 1984(s0)
+  li t0, 28
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 1988(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 1992(s0)
+  lw t0, 1988(s0)
+  lw t1, 1992(s0)
+  add t0, t0, t1
+  sw t0, 1996(s0)
+  addi t0, s0, 0
+  lw t1, 1996(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 2004(s0)
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 2008(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 2012(s0)
+  lw t0, 2008(s0)
+  lw t1, 2012(s0)
+  add t0, t0, t1
+  sw t0, 2016(s0)
+  addi t0, s0, 576
+  lw t1, 2016(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  sw t0, 2024(s0)
+  li t0, 37
+  li t1, 3
+  mul t0, t0, t1
+  sw t0, 2028(s0)
+  la t0, k
+  lw t0, 0(t0)
+  sw t0, 2032(s0)
+  lw t0, 2028(s0)
+  lw t1, 2032(s0)
+  add t0, t0, t1
+  sw t0, 2036(s0)
+  addi t0, s0, 0
+  lw t1, 2036(s0)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  fsw ft0, 2044(s0)
+  li t0, 19
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2048
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2048
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2052
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2056
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2056
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2064
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 30
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2072
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2068
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2072
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2076
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2084
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 12
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2088
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2092
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2088
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2092
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2096
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2096
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2104
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2108
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2112
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2108
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2112
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2116
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2124
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 11
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2128
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2132
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2128
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2132
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2136
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2136
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2144
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 38
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2148
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2152
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2156
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2164
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 6
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2168
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2168
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2172
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2176
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2176
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2184
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 7
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2192
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2188
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2192
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2196
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2196
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 32
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2208
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2212
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2208
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2212
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2216
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2224
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 10
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2232
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2228
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2232
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2236
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2236
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2244
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 13
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2248
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2248
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2252
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2256
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2256
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 20
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2268
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2272
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2268
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2272
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2276
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2284
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 33
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2288
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2288
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2292
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2296
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2296
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2304
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 23
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2308
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2308
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2312
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2316
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2324
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 9
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2328
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2332
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2328
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2332
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2336
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2336
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2344
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 25
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2352
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2348
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2352
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2356
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2356
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2364
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 8
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2368
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2368
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2372
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2376
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2376
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2384
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 39
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2388
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2392
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2388
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2392
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2396
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2396
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2404
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 17
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2408
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2412
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2408
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2412
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2416
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2416
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2424
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 21
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2428
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2432
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2428
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2432
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2436
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2436
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2444
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 16
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2448
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2452
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2448
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2452
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2456
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2456
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2464
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 5
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2468
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2472
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2468
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2472
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2476
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2476
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2484
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 34
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2488
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2492
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2488
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2492
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2496
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2496
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2504
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 18
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2508
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2512
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2508
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2512
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2516
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2516
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2524
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 9
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2528
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2532
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2528
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2532
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2536
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2536
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2544
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 14
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2548
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2552
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2548
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2552
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2556
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2556
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2564
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 10
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2568
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2572
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2568
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2572
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2576
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2576
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2584
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2588
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2592
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2588
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2592
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2596
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2596
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2604
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 12
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2608
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2612
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2608
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2612
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2616
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2616
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2624
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 31
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2628
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2632
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2628
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2632
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2636
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2636
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2644
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 11
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2648
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2652
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2648
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2652
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2656
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2656
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2664
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 16
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2668
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2672
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2668
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2672
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2676
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2676
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2684
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 27
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2688
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2692
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2688
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2692
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2696
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2696
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2704
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 24
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2708
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2712
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2708
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2712
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2716
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2716
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2724
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 13
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2728
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2732
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2728
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2732
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2736
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2736
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2744
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 29
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2748
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2752
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2748
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2752
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2756
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2756
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2764
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2768
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2772
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2768
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2772
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2776
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2776
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2784
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 21
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2788
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2792
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2788
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2792
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2796
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2796
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2804
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 20
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2808
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2812
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2808
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2812
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2816
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2816
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2824
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 18
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2828
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2832
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2828
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2832
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2836
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2836
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2844
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 19
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2848
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2852
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2848
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2852
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2856
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2856
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2864
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 22
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2868
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2872
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2868
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2872
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2876
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2876
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2884
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 26
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2888
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2892
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2888
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2892
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2896
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2896
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2904
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 36
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2908
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2912
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2908
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2912
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2916
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2916
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2924
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 17
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2928
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2932
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2928
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2932
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2936
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2936
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2944
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 15
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2948
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2952
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2948
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2952
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2956
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2956
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 2964
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2968
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2972
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2968
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2972
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2976
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 2976
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 2984
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 14
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 2988
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 2992
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 2988
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 2992
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 2996
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 2996
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3004
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 35
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3008
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3012
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3008
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3012
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3016
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3016
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3024
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  addi sp, sp, -448
+  lw a0, 1764(s0)
+  lw a1, 1784(s0)
+  lw a2, 1804(s0)
+  flw fa3, 1824(s0)
+  lw a4, 1844(s0)
+  lw a5, 1864(s0)
+  lw a6, 1884(s0)
+  flw fa7, 1904(s0)
+  add t4, sp, zero
+  flw ft0, 1924(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 8
+  flw ft0, 1944(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 16
+  lw t0, 1964(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  flw ft0, 1984(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 32
+  flw ft0, 2004(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 40
+  lw t0, 2024(s0)
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  flw ft0, 2044(s0)
+  fsw ft0, 0(t4)
+  addi t4, sp, 56
+  li t4, 2064
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  li t4, 2084
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 72
+  li t4, 2104
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 80
+  li t4, 2124
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 88
+  li t4, 2144
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 96
+  li t4, 2164
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 104
+  li t4, 2184
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 112
+  li t4, 2204
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 120
+  li t4, 2224
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 128
+  li t4, 2244
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 136
+  li t4, 2264
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 144
+  li t4, 2284
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 152
+  li t4, 2304
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 160
+  li t4, 2324
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 168
+  li t4, 2344
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 176
+  li t4, 2364
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 184
+  li t4, 2384
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 192
+  li t4, 2404
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 200
+  li t4, 2424
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 208
+  li t4, 2444
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 216
+  li t4, 2464
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 224
+  li t4, 2484
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 232
+  li t4, 2504
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 240
+  li t4, 2524
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 248
+  li t4, 2544
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 256
+  li t4, 2564
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 264
+  li t4, 2584
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 272
+  li t4, 2604
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 280
+  li t4, 2624
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 288
+  li t4, 2644
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 296
+  li t4, 2664
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 304
+  li t4, 2684
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 312
+  li t4, 2704
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 320
+  li t4, 2724
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 328
+  li t4, 2744
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 336
+  li t4, 2764
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 344
+  li t4, 2784
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 352
+  li t4, 2804
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 360
+  li t4, 2824
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 368
+  li t4, 2844
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 376
+  li t4, 2864
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 384
+  li t4, 2884
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 392
+  li t4, 2904
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 400
+  li t4, 2924
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 408
+  li t4, 2944
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 416
+  li t4, 2964
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 424
+  li t4, 2984
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 432
+  li t4, 3004
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 440
+  li t4, 3024
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  call params_f40_i24
+  addi sp, sp, 448
+  li t4, 3028
+  add t4, s0, t4
+  fsw fa0, 0(t4)
+  li t4, 3028
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 1744(s0)
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3036
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3044
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3060
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 4
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 5
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 6
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3084
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 7
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3092
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 8
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3100
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 9
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3108
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 10
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 11
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3124
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 12
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3132
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 13
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3140
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 14
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 15
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3156
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 16
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3164
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 17
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 18
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 19
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 20
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3196
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 21
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 22
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3212
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 23
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3220
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 24
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 25
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3236
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 26
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3244
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 27
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3252
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 28
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3260
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 29
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3268
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 30
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 31
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3284
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 32
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 33
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3300
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 34
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3308
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 35
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 36
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 37
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3332
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 38
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3340
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 39
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3348
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi sp, sp, -256
+  addi a0, s0, 0
+  li t4, 3036
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a0, a0, t1
+  addi a1, s0, 0
+  li t4, 3044
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a1, a1, t1
+  addi a2, s0, 0
+  li t4, 3052
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a2, a2, t1
+  addi a3, s0, 0
+  li t4, 3060
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a3, a3, t1
+  addi a4, s0, 0
+  li t4, 3068
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a4, a4, t1
+  addi a5, s0, 0
+  li t4, 3076
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a5, a5, t1
+  addi a6, s0, 0
+  li t4, 3084
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a6, a6, t1
+  addi a7, s0, 0
+  li t4, 3092
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a7, a7, t1
+  add t4, sp, zero
+  addi t0, s0, 0
+  li t4, 3100
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 8
+  addi t0, s0, 0
+  li t4, 3108
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 16
+  addi t0, s0, 0
+  li t4, 3116
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  addi t0, s0, 0
+  li t4, 3124
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 32
+  addi t0, s0, 0
+  li t4, 3132
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 40
+  addi t0, s0, 0
+  li t4, 3140
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  addi t0, s0, 0
+  li t4, 3148
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 56
+  addi t0, s0, 0
+  li t4, 3156
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  addi t0, s0, 0
+  li t4, 3164
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 72
+  addi t0, s0, 0
+  li t4, 3172
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 80
+  addi t0, s0, 0
+  li t4, 3180
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 88
+  addi t0, s0, 0
+  li t4, 3188
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 96
+  addi t0, s0, 0
+  li t4, 3196
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 104
+  addi t0, s0, 0
+  li t4, 3204
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 112
+  addi t0, s0, 0
+  li t4, 3212
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 120
+  addi t0, s0, 0
+  li t4, 3220
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 128
+  addi t0, s0, 0
+  li t4, 3228
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 136
+  addi t0, s0, 0
+  li t4, 3236
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 144
+  addi t0, s0, 0
+  li t4, 3244
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 152
+  addi t0, s0, 0
+  li t4, 3252
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 160
+  addi t0, s0, 0
+  li t4, 3260
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 168
+  addi t0, s0, 0
+  li t4, 3268
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 176
+  addi t0, s0, 0
+  li t4, 3276
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 184
+  addi t0, s0, 0
+  li t4, 3284
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 192
+  addi t0, s0, 0
+  li t4, 3292
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 200
+  addi t0, s0, 0
+  li t4, 3300
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 208
+  addi t0, s0, 0
+  li t4, 3308
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 216
+  addi t0, s0, 0
+  li t4, 3316
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 224
+  addi t0, s0, 0
+  li t4, 3324
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 232
+  addi t0, s0, 0
+  li t4, 3332
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 240
+  addi t0, s0, 0
+  li t4, 3340
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 248
+  addi t0, s0, 0
+  li t4, 3348
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  call params_fa40
+  addi sp, sp, 256
+  li t4, 3356
+  add t4, s0, t4
+  fsw fa0, 0(t4)
+  li t4, 3356
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  li t4, 3032
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3364
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3368
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3364
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3368
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3372
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3372
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3380
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3384
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3392
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3396
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3392
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3396
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3400
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3400
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3408
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3412
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3420
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3424
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3420
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3424
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3428
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3428
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3436
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3440
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3444
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3440
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3444
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3448
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3448
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3456
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3460
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3464
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3460
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3464
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3468
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3468
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3476
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 4
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3480
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3484
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3480
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3484
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3488
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3488
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3496
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 5
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3500
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3508
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 4
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3516
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3520
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3516
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3520
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3524
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3524
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3532
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 5
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3536
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3540
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3536
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3540
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3544
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3544
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3552
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 6
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3556
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 6
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3564
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 7
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3572
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 8
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3580
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3584
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3580
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3584
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3588
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3588
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3596
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 7
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3600
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 8
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3608
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 9
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3616
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3620
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3616
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3620
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3624
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3624
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3632
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 10
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3636
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3640
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3636
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3640
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3644
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3644
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3652
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 11
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3656
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3660
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3656
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3660
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3664
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3664
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3672
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 12
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3676
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 9
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3684
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3688
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3684
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3688
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3692
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3692
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3700
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 13
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3704
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3708
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3704
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3708
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3712
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3712
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3720
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 14
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3724
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3728
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3724
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3728
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3732
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3732
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3740
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 15
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3744
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3748
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3744
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3748
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3752
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3752
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3760
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 10
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3764
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 16
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3772
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 11
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3780
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 12
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3788
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 17
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3796
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 18
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3804
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3808
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3804
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3808
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3812
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3812
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3820
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 19
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3824
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3828
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3824
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3828
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3832
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3832
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3840
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 13
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3844
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 14
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3852
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3856
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3852
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3856
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3860
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3860
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3868
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 20
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3872
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 21
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3880
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 22
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3888
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3892
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3888
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3892
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3896
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3896
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3904
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 23
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3908
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3912
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3908
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3912
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3916
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3916
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 3924
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 15
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3928
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 16
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3936
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 17
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3944
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3948
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3944
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3948
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3952
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3952
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3960
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 18
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3964
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3968
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3964
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3968
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3972
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 3972
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 3980
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 24
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 3984
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 3988
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 3984
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3988
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 3992
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 3992
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4000
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 25
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4004
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4008
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4004
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4008
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4012
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 4012
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4020
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 19
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4024
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 20
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4032
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4036
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4032
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4036
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4040
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 4040
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 4048
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 26
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4052
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 21
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4060
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4064
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4060
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4064
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4068
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 4068
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 4076
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 22
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4080
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 23
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4088
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 27
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4096
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4100
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4096
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4100
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4104
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 4104
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4112
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 28
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4116
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4120
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4116
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4120
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4124
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 4124
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4132
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 29
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4136
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 0
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4144
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4148
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4144
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4148
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4152
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 4152
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 4160
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 1
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4164
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 30
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4172
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 31
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4180
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4184
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4180
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4184
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4188
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 4188
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4196
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 2
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4200
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4204
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4200
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4204
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4208
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 4208
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 4216
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 32
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4220
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4224
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4220
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4224
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4228
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 4228
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4236
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 33
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4240
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 34
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4248
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t0, 35
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4256
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4260
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4256
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4260
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4264
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 0
+  li t4, 4264
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  flw ft0, 0(t0)
+  li t4, 4272
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t0, 3
+  li t1, 3
+  mul t0, t0, t1
+  li t4, 4276
+  add t4, s0, t4
+  sw t0, 0(t4)
+  la t0, k
+  lw t0, 0(t0)
+  li t4, 4280
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4276
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4280
+  add t4, s0, t4
+  lw t1, 0(t4)
+  add t0, t0, t1
+  li t4, 4284
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi t0, s0, 576
+  li t4, 4284
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  lw t0, 0(t0)
+  li t4, 4292
+  add t4, s0, t4
+  sw t0, 0(t4)
+  addi sp, sp, -448
+  li t4, 3380
+  add t4, s0, t4
+  flw fa0, 0(t4)
+  addi a1, s0, 576
+  li t4, 3384
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a1, a1, t1
+  li t4, 3408
+  add t4, s0, t4
+  lw a2, 0(t4)
+  addi a3, s0, 0
+  li t4, 3412
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add a3, a3, t1
+  li t4, 3436
+  add t4, s0, t4
+  flw fa4, 0(t4)
+  li t4, 3456
+  add t4, s0, t4
+  lw a5, 0(t4)
+  li t4, 3476
+  add t4, s0, t4
+  flw fa6, 0(t4)
+  li t4, 3496
+  add t4, s0, t4
+  flw fa7, 0(t4)
+  add t4, sp, zero
+  addi t0, s0, 0
+  li t4, 3500
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 8
+  addi t0, s0, 576
+  li t4, 3508
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 16
+  li t4, 3532
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 24
+  li t4, 3552
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 32
+  addi t0, s0, 0
+  li t4, 3556
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 40
+  addi t0, s0, 576
+  li t4, 3564
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 48
+  addi t0, s0, 576
+  li t4, 3572
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 56
+  li t4, 3596
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 64
+  addi t0, s0, 0
+  li t4, 3600
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 72
+  addi t0, s0, 0
+  li t4, 3608
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 80
+  li t4, 3632
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 88
+  li t4, 3652
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 96
+  li t4, 3672
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 104
+  addi t0, s0, 0
+  li t4, 3676
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 112
+  li t4, 3700
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 120
+  li t4, 3720
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 128
+  li t4, 3740
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 136
+  li t4, 3760
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 144
+  addi t0, s0, 576
+  li t4, 3764
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 152
+  addi t0, s0, 0
+  li t4, 3772
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 160
+  addi t0, s0, 576
+  li t4, 3780
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 168
+  addi t0, s0, 576
+  li t4, 3788
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 176
+  addi t0, s0, 0
+  li t4, 3796
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 184
+  li t4, 3820
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 192
+  li t4, 3840
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 200
+  addi t0, s0, 576
+  li t4, 3844
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 208
+  li t4, 3868
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 216
+  addi t0, s0, 0
+  li t4, 3872
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 224
+  addi t0, s0, 0
+  li t4, 3880
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 232
+  li t4, 3904
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 240
+  li t4, 3924
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 248
+  addi t0, s0, 576
+  li t4, 3928
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 256
+  addi t0, s0, 576
+  li t4, 3936
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 264
+  li t4, 3960
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 272
+  li t4, 3980
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 280
+  li t4, 4000
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 288
+  li t4, 4020
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 296
+  addi t0, s0, 576
+  li t4, 4024
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 304
+  li t4, 4048
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 312
+  addi t0, s0, 0
+  li t4, 4052
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 320
+  li t4, 4076
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 328
+  addi t0, s0, 576
+  li t4, 4080
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 336
+  addi t0, s0, 576
+  li t4, 4088
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 344
+  li t4, 4112
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 352
+  li t4, 4132
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 360
+  addi t0, s0, 0
+  li t4, 4136
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 368
+  li t4, 4160
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 376
+  addi t0, s0, 576
+  li t4, 4164
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 384
+  addi t0, s0, 0
+  li t4, 4172
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 392
+  li t4, 4196
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 400
+  li t4, 4216
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  addi t4, sp, 408
+  li t4, 4236
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 416
+  addi t0, s0, 0
+  li t4, 4240
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 424
+  addi t0, s0, 0
+  li t4, 4248
+  add t4, s0, t4
+  lw t1, 0(t4)
+  slli t1, t1, 2
+  add t0, t0, t1
+  sd t0, 0(t4)
+  addi t4, sp, 432
+  li t4, 4272
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  fsw ft0, 0(t4)
+  addi t4, sp, 440
+  li t4, 4292
+  add t4, s0, t4
+  lw t0, 0(t4)
+  sd t0, 0(t4)
+  call params_mix
+  addi sp, sp, 448
+  li t4, 4296
+  add t4, s0, t4
+  sw a0, 0(t4)
+  li t4, 4296
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 3360
+  add t4, s0, t4
+  sw t0, 0(t4)
+  flw ft0, 936(s0)
+  li t4, 4300
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t4, 4300
+  add t4, s0, t4
+  flw fa0, 0(t4)
+  call putfloat
+  li a0, 10
+  call putch
+  flw ft0, 1744(s0)
+  li t4, 4304
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t4, 4304
+  add t4, s0, t4
+  flw fa0, 0(t4)
+  call putfloat
+  li a0, 10
+  call putch
+  li t4, 3032
+  add t4, s0, t4
+  flw ft0, 0(t4)
+  li t4, 4308
+  add t4, s0, t4
+  fsw ft0, 0(t4)
+  li t4, 4308
+  add t4, s0, t4
+  flw fa0, 0(t4)
+  call putfloat
+  li a0, 10
+  call putch
+  li t4, 3360
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t4, 4312
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4312
+  add t4, s0, t4
+  lw a0, 0(t4)
+  call putint
+  li a0, 10
+  call putch
+  li t0, 0
+  li t1, 256
+  rem t0, t0, t1
+  li t4, 4316
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4316
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  add t0, t0, t1
+  li t4, 4320
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4320
+  add t4, s0, t4
+  lw t0, 0(t4)
+  li t1, 256
+  rem t0, t0, t1
+  li t4, 4324
+  add t4, s0, t4
+  sw t0, 0(t4)
+  li t4, 4324
+  add t4, s0, t4
+  lw a0, 0(t4)
+  call putint
+  li a0, 10
+  call putch
+  li a0, 0
+  li t3, 4336
+  add t3, s0, t3
+  ld ra, 0(t3)
+  li t3, 4352
+  add sp, s0, t3
+  li t3, 4344
+  add t3, s0, t3
+  ld s0, 0(t3)
+  ret
+.size main, .-main
+
diff --git a/include/mir/MIR.h b/include/mir/MIR.h
index 4dfe142..0ddabc8 100644
--- a/include/mir/MIR.h
+++ b/include/mir/MIR.h
@@ -100,6 +100,8 @@ enum class Opcode {
   StoreGlobal,
   LoadIndirect,   // lw rd, 0(rs1)  从寄存器地址加载
   StoreIndirect,  // sw rs2, 0(rs1)
+  LoadIndirectFloat,   // flw rd, 0(rs1)
+  StoreIndirectFloat,  // fsw rs2, 0(rs1)
   Call,
   GEP,
   LoadAddr,  
@@ -124,6 +126,8 @@ enum class Opcode {
   Br,
   CondBr,
   Label,
+  LoadCallerStackArg, // 从调用者栈帧加载参数
+  LoadCallerStackArgFloat,  // 从调用者栈帧加载浮点参数
 };
 
 enum class GlobalKind {
@@ -229,13 +233,15 @@ class MachineFunction {
 
   int GetFrameSize() const { return frame_size_; }
   void SetFrameSize(int size) { frame_size_ = size; }
-
+  int GetLocalVarsSize() const { return local_vars_size_; }
+  void SetLocalVarsSize(int s) { local_vars_size_ = s; }
  private:
   std::string name_;
   MachineBasicBlock* entry_ = nullptr;
   std::vector<std::unique_ptr<MachineBasicBlock>> blocks_;
   std::vector<FrameSlot> frame_slots_;
   int frame_size_ = 0;
+  int local_vars_size_ = 0;
 };
 //std::unique_ptr<MachineFunction> LowerToMIR(const ir::Module& module);
 void RunRegAlloc(MachineFunction& function);
diff --git a/ir.txt b/ir.txt
new file mode 100644
index 0000000..da044f3
--- /dev/null
+++ b/ir.txt
@@ -0,0 +1,272 @@
+@MAX = global i32 1000000000
+@TWO = global i32 2
+@THREE = global i32 3
+@FIVE = global i32 5
+
+declare void @putch(i32)
+declare void @memset(i32*, i32, i32)
+declare i32 @getfarray(float*)
+declare float @getfloat()
+declare void @putfloat(float)
+declare void @putint(i32)
+declare void @putfarray(i32, float*)
+
+define float @float_abs(float %x) {
+entry:
+  %0 = alloca float
+  store float %x, float* %0
+  %2 = load float, float* %0
+  %3 = sitofp i32 0 to float
+  %4 = fcmp olt float %2, %3
+  br i1 %4, label %L0.if.then, label %L1.if.end
+L0.if.then:
+  %6 = load float, float* %0
+  %7 = fsub float 0x0, %6
+  ret float %7
+L1.if.end:
+  %9 = load float, float* %0
+  ret float %9
+}
+
+define float @circle_area(i32 %radius) {
+entry:
+  %0 = alloca i32
+  store i32 %radius, i32* %0
+  %2 = load i32, i32* %0
+  %3 = sitofp i32 %2 to float
+  %4 = fmul float 0x400921FB60000000, %3
+  %5 = load i32, i32* %0
+  %6 = sitofp i32 %5 to float
+  %7 = fmul float %4, %6
+  %8 = load i32, i32* %0
+  %9 = load i32, i32* %0
+  %10 = mul i32 %8, %9
+  %11 = sitofp i32 %10 to float
+  %12 = fmul float %11, 0x400921FB60000000
+  %13 = fadd float %7, %12
+  %14 = sitofp i32 2 to float
+  %15 = fdiv float %13, %14
+  ret float %15
+}
+
+define i32 @float_eq(float %a, float %b) {
+entry:
+  %0 = alloca float
+  %1 = alloca float
+  store float %a, float* %0
+  store float %b, float* %1
+  %4 = load float, float* %0
+  %5 = load float, float* %1
+  %6 = fsub float %4, %5
+  %7 = call float @float_abs(float %6)
+  %8 = fcmp olt float %7, 0x3EB0C6F7A0000000
+  br i1 %8, label %L2.if.then, label %L3.if.else
+L2.if.then:
+  %10 = sitofp i32 1 to float
+  %11 = fmul float %10, 0x4000000000000000
+  %12 = sitofp i32 2 to float
+  %13 = fdiv float %11, %12
+  %14 = fptosi float %13 to i32
+  ret i32 %14
+L3.if.else:
+  ret i32 0
+L4.if.end:
+  ret i32 0
+}
+
+define void @error() {
+entry:
+  call void @putch(i32 101)
+  call void @putch(i32 114)
+  call void @putch(i32 114)
+  call void @putch(i32 111)
+  call void @putch(i32 114)
+  call void @putch(i32 10)
+  ret void
+}
+
+define void @ok() {
+entry:
+  call void @putch(i32 111)
+  call void @putch(i32 107)
+  call void @putch(i32 10)
+  ret void
+}
+
+define void @assert(i32 %cond) {
+entry:
+  %0 = alloca i32
+  store i32 %cond, i32* %0
+  %2 = load i32, i32* %0
+  %3 = icmp eq i32 %2, 0
+  %4 = zext i1 %3 to i32
+  %5 = icmp ne i32 %4, 0
+  br i1 %5, label %L5.if.then, label %L6.if.else
+L5.if.then:
+  call void @error()
+  br label %L7.if.end
+L6.if.else:
+  call void @ok()
+  br label %L7.if.end
+L7.if.end:
+  ret void
+}
+
+define void @assert_not(i32 %cond) {
+entry:
+  %0 = alloca i32
+  store i32 %cond, i32* %0
+  %2 = load i32, i32* %0
+  %3 = icmp ne i32 %2, 0
+  br i1 %3, label %L8.if.then, label %L9.if.else
+L8.if.then:
+  call void @error()
+  br label %L10.if.end
+L9.if.else:
+  call void @ok()
+  br label %L10.if.end
+L10.if.end:
+  ret void
+}
+
+define i32 @main() {
+entry:
+  %0 = alloca i32
+  %1 = alloca i32
+  %2 = alloca i32
+  %3 = alloca i32
+  %4 = alloca float, i32 10
+  %5 = alloca i32
+  %6 = alloca float
+  %7 = alloca float
+  %8 = alloca float
+  %9 = call i32 @float_eq(float 0x3FB4000000000000, float 0xC0E01D0000000000)
+  call void @assert_not(i32 %9)
+  %11 = call i32 @float_eq(float 0x4057C21FC0000000, float 0x4041475CE0000000)
+  call void @assert_not(i32 %11)
+  %13 = call i32 @float_eq(float 0x4041475CE0000000, float 0x4041475CE0000000)
+  call void @assert(i32 %13)
+  %15 = fptosi float 0x4016000000000000 to i32
+  %16 = call float @circle_area(i32 %15)
+  %17 = load i32, i32* @FIVE
+  %18 = call float @circle_area(i32 %17)
+  %19 = call i32 @float_eq(float %16, float %18)
+  call void @assert(i32 %19)
+  %21 = call i32 @float_eq(float 0x406D200000000000, float 0x40AFFE0000000000)
+  call void @assert_not(i32 %21)
+  %23 = fcmp one float 0x3FF8000000000000, 0x0
+  br i1 %23, label %L11.if.then, label %L12.if.end
+L11.if.then:
+  call void @ok()
+  br label %L12.if.end
+L12.if.end:
+  %27 = fcmp oeq float 0x400A666660000000, 0x0
+  %28 = zext i1 %27 to i32
+  %29 = icmp eq i32 %28, 0
+  %30 = zext i1 %29 to i32
+  %31 = icmp ne i32 %30, 0
+  br i1 %31, label %L13.if.then, label %L14.if.end
+L13.if.then:
+  call void @ok()
+  br label %L14.if.end
+L14.if.end:
+  %35 = fcmp one float 0x0, 0x0
+  %36 = zext i1 %35 to i32
+  store i32 %36, i32* %0
+  br i1 %35, label %L15.and.rhs, label %L16.and.end
+L15.and.rhs:
+  %39 = icmp ne i32 3, 0
+  %40 = zext i1 %39 to i32
+  store i32 %40, i32* %0
+  br label %L16.and.end
+L16.and.end:
+  %43 = load i32, i32* %0
+  %44 = icmp ne i32 %43, 0
+  br i1 %44, label %L17.if.then, label %L18.if.end
+L17.if.then:
+  call void @error()
+  br label %L18.if.end
+L18.if.end:
+  %48 = icmp ne i32 0, 0
+  %49 = zext i1 %48 to i32
+  store i32 %49, i32* %1
+  br i1 %48, label %L20.or.end, label %L19.or.rhs
+L19.or.rhs:
+  %52 = fcmp one float 0x3FD3333340000000, 0x0
+  %53 = zext i1 %52 to i32
+  store i32 %53, i32* %1
+  br label %L20.or.end
+L20.or.end:
+  %56 = load i32, i32* %1
+  %57 = icmp ne i32 %56, 0
+  br i1 %57, label %L21.if.then, label %L22.if.end
+L21.if.then:
+  call void @ok()
+  br label %L22.if.end
+L22.if.end:
+  store i32 1, i32* %2
+  store i32 0, i32* %3
+  call void @memset(float* %4, i32 0, i32 40)
+  %64 = getelementptr float, float* %4, i32 0
+  store float 0x3FF0000000000000, float* %64
+  %66 = getelementptr float, float* %4, i32 1
+  store i32 2, float* %66
+  %68 = getelementptr float, float* %4, i32 0
+  %69 = call i32 @getfarray(float* %68)
+  store i32 %69, i32* %5
+  br label %L23.while.cond
+L23.while.cond:
+  %72 = load i32, i32* %2
+  %73 = load i32, i32* @MAX
+  %74 = icmp slt i32 %72, %73
+  br i1 %74, label %L24.while.body, label %L25.while.end
+L24.while.body:
+  %76 = call float @getfloat()
+  store float %76, float* %6
+  %78 = load float, float* %6
+  %79 = fmul float 0x400921FB60000000, %78
+  %80 = load float, float* %6
+  %81 = fmul float %79, %80
+  store float %81, float* %7
+  %83 = load float, float* %6
+  %84 = fptosi float %83 to i32
+  %85 = call float @circle_area(i32 %84)
+  store float %85, float* %8
+  %87 = load i32, i32* %3
+  %88 = getelementptr float, float* %4, i32 %87
+  %89 = load float, float* %88
+  %90 = load float, float* %6
+  %91 = fadd float %89, %90
+  %92 = load i32, i32* %3
+  %93 = getelementptr float, float* %4, i32 %92
+  store float %91, float* %93
+  %95 = load float, float* %7
+  call void @putfloat(float %95)
+  call void @putch(i32 32)
+  %98 = load float, float* %8
+  %99 = fptosi float %98 to i32
+  call void @putint(i32 %99)
+  call void @putch(i32 10)
+  %102 = load i32, i32* %2
+  %103 = fsub float 0x0, 0x4024000000000000
+  %104 = fsub float 0x0, %103
+  %105 = sitofp i32 %102 to float
+  %106 = fmul float %105, %104
+  %107 = fptosi float %106 to i32
+  store i32 %107, i32* %2
+  %109 = load i32, i32* %3
+  %110 = add i32 %109, 1
+  store i32 %110, i32* %3
+  br label %L23.while.cond
+L25.while.end:
+  %113 = load i32, i32* %5
+  %114 = getelementptr float, float* %4, i32 0
+  call void @putfarray(i32 %113, float* %114)
+  %116 = srem i32 0, 256
+  %117 = add i32 %116, 256
+  %118 = srem i32 %117, 256
+  call void @putint(i32 %118)
+  call void @putch(i32 10)
+  ret i32 0
+}
+
diff --git a/scripts/mir_test.sh b/scripts/mir_test.sh
deleted file mode 100644
index c16f72d..0000000
--- a/scripts/mir_test.sh
+++ /dev/null
@@ -1,137 +0,0 @@
-#!/bin/bash
-
-PROJECT_ROOT=$(cd "$(dirname "$0")/.." ; pwd)
-COMPILER="$PROJECT_ROOT/build/bin/compiler"
-TEST_CASE_DIR="$PROJECT_ROOT/test/test_case"
-TEST_RESULT_DIR="$PROJECT_ROOT/test/test_result/mir"
-
-RED='\033[0;31m'
-GREEN='\033[0;32m'
-YELLOW='\033[1;33m'
-NC='\033[0m'
-
-if [ ! -x "$COMPILER" ]; then
-    echo "错误：编译器不存在或不可执行: $COMPILER"
-    exit 1
-fi
-
-mkdir -p "$TEST_RESULT_DIR"
-
-echo "=========================================="
-echo "RISC-V 后端测试"
-echo "=========================================="
-echo ""
-
-# 收集测试用例
-mapfile -t test_files < <(find "$TEST_CASE_DIR" -name "*.sy" -not -path '*/*performance*/*' | sort)
-
-total=${#test_files[@]}
-pass_gen=0
-fail_gen=0
-pass_run=0
-fail_run=0
-timeout_cnt=0
-
-echo "=== 阶段1：汇编生成 ==="
-echo ""
-
-for test_file in "${test_files[@]}"; do
-    relative_path=$(realpath --relative-to="$TEST_CASE_DIR" "$test_file")
-    output_file="$TEST_RESULT_DIR/${relative_path%.sy}.s"
-    mkdir -p "$(dirname "$output_file")"
-    
-    "$COMPILER" --emit-asm "$test_file" 2>/dev/null > "$output_file"
-    
-    if [ $? -eq 0 ] && [ -s "$output_file" ]; then
-        echo -e "  ${GREEN}✓${NC} $relative_path"
-        ((pass_gen++))
-    else
-        echo -e "  ${RED}✗${NC} $relative_path"
-        ((fail_gen++))
-    fi
-done
-
-echo ""
-echo "--- 汇编生成: 通过 $pass_gen / 失败 $fail_gen / 总计 $total ---"
-echo ""
-
-echo "=== 阶段2：运行验证 ==="
-echo ""
-
-for test_file in "${test_files[@]}"; do
-    relative_path=$(realpath --relative-to="$TEST_CASE_DIR" "$test_file")
-    stem="${relative_path%.sy}"
-    asm_file="$TEST_RESULT_DIR/${stem}.s"
-    exe_file="$TEST_RESULT_DIR/${stem}"
-    expected_file="${test_file%.sy}.out"
-    
-    if [ ! -s "$asm_file" ]; then
-        echo -e "  ${YELLOW}⚠${NC} $relative_path (跳过)"
-        continue
-    fi
-    
-    riscv64-linux-gnu-gcc -static "$asm_file" -o "$exe_file" -no-pie 2>/dev/null
-    if [ $? -ne 0 ]; then
-        echo -e "  ${RED}✗${NC} $relative_path (链接失败)"
-        ((fail_run++))
-        continue
-    fi
-    
-    # 运行程序，设置超时 5 秒
-    timeout 5 qemu-riscv64 "$exe_file" 2>/dev/null
-    exit_code=$?
-    
-    # 检查是否超时
-    if [ $exit_code -eq 124 ]; then
-        echo -e "  ${YELLOW}⚠${NC} $relative_path (超时)"
-        ((timeout_cnt++))
-        continue
-    fi
-    
-    # 获取程序输出（需要单独捕获，因为 timeout 会改变输出）
-    program_output=$(timeout 5 qemu-riscv64 "$exe_file" 2>/dev/null)
-    if [ $? -eq 124 ]; then
-        echo -e "  ${YELLOW}⚠${NC} $relative_path (超时)"
-        ((timeout_cnt++))
-        continue
-    fi
-    
-    if [ -f "$expected_file" ]; then
-        expected=$(cat "$expected_file" | tr -d '\n')
-        
-        # 判断期望文件是输出内容还是退出码
-        if [ -z "$expected" ] || [[ "$expected" =~ ^[0-9]+$ ]]; then
-            # 期望退出码
-            if [ $exit_code -eq "$expected" ] 2>/dev/null; then
-                echo -e "  ${GREEN}✓${NC} $relative_path (退出码: $exit_code)"
-                ((pass_run++))
-            else
-                echo -e "  ${RED}✗${NC} $relative_path (退出码: 期望 $expected, 实际 $exit_code)"
-                ((fail_run++))
-            fi
-        else
-            # 期望输出内容
-            if [ "$program_output" = "$expected" ]; then
-                echo -e "  ${GREEN}✓${NC} $relative_path (输出匹配)"
-                ((pass_run++))
-            else
-                echo -e "  ${RED}✗${NC} $relative_path (输出不匹配)"
-                ((fail_run++))
-            fi
-        fi
-    else
-        # 没有期望文件，默认通过
-        echo -e "  ${GREEN}✓${NC} $relative_path (退出码: $exit_code)"
-        ((pass_run++))
-    fi
-done
-
-echo ""
-echo "--- 运行验证: 通过 $pass_run / 失败 $fail_run / 超时 $timeout_cnt ---"
-echo ""
-
-echo "=========================================="
-echo "测试完成"
-echo "汇编生成: 通过 $pass_gen / 失败 $fail_gen"
-echo "运行验证: 通过 $pass_run / 失败 $fail_run / 超时 $timeout_cnt"
-echo "=========================================="
\ No newline at end of file
diff --git a/scripts/run_float_tests.sh b/scripts/run_float_tests.sh
deleted file mode 100755
index 594e2f3..0000000
--- a/scripts/run_float_tests.sh
+++ /dev/null
@@ -1,65 +0,0 @@
-
-#!/bin/bash
-
-PROJECT_ROOT=$(cd "$(dirname "$0")/.." ; pwd)
-COMPILER="$PROJECT_ROOT/build/bin/compiler"
-TEST_DIR="$PROJECT_ROOT/test/test_case/basic"
-
-RED='\033[0;31m'
-GREEN='\033[0;32m'
-NC='\033[0m'
-
-if [ ! -f "$COMPILER" ]; then
-    echo "错误: 编译器不存在: $COMPILER"
-    exit 1
-fi
-
-echo "=========================================="
-echo "RISC-V 浮点转换测试"
-echo "=========================================="
-
-TESTS="
-float_conv:3
-float_add:13
-float_mul:30
-"
-
-PASS=0
-FAIL=0
-
-for test in $TESTS; do
-    name=$(echo $test | cut -d: -f1)
-    expected=$(echo $test | cut -d: -f2)
-    
-    echo -n "测试 $name (期望 $expected) ... "
-    
-    "$COMPILER" "$TEST_DIR/$name.sy" --emit-asm > /tmp/test_$name.s 2>&1
-    if [ $? -ne 0 ]; then
-        echo -e "${RED}失败 (汇编错误)${NC}"
-        cat /tmp/test_$name.s | head -3
-        FAIL=$((FAIL + 1))
-        continue
-    fi
-    
-    riscv64-linux-gnu-gcc -static /tmp/test_$name.s -o /tmp/test_$name -no-pie 2>/dev/null
-    if [ $? -ne 0 ]; then
-        echo -e "${RED}失败 (链接错误)${NC}"
-        FAIL=$((FAIL + 1))
-        continue
-    fi
-    
-    qemu-riscv64 /tmp/test_$name > /dev/null 2>&1
-    exit_code=$?
-    
-    if [ $exit_code -eq $expected ]; then
-        echo -e "${GREEN}通过${NC}"
-        PASS=$((PASS + 1))
-    else
-        echo -e "${RED}失败 (实际 $exit_code)${NC}"
-        FAIL=$((FAIL + 1))
-    fi
-done
-
-echo "=========================================="
-echo -e "测试结果: ${GREEN}通过 $PASS${NC} / ${RED}失败 $FAIL${NC}"
-echo "=========================================="
\ No newline at end of file
diff --git a/scripts/test_riscv_basic.sh b/scripts/test_riscv_basic.sh
deleted file mode 100755
index 7112ac7..0000000
--- a/scripts/test_riscv_basic.sh
+++ /dev/null
@@ -1,85 +0,0 @@
-#!/bin/bash
-
-# 获取项目根目录
-PROJECT_ROOT=$(cd "$(dirname "$0")/.." ; pwd)
-COMPILER="$PROJECT_ROOT/build/bin/compiler"
-TEST_DIR="$PROJECT_ROOT/test/test_case/basic"
-
-# 颜色定义
-RED='\033[0;31m'
-GREEN='\033[0;32m'
-NC='\033[0m'
-
-# 检查编译器
-if [ ! -f "$COMPILER" ]; then
-    echo "错误: 编译器不存在: $COMPILER"
-    exit 1
-fi
-
-# 检查工具链
-if ! command -v riscv64-linux-gnu-gcc >/dev/null 2>&1; then
-    echo "错误: 未找到 riscv64-linux-gnu-gcc"
-    exit 1
-fi
-
-if ! command -v qemu-riscv64 >/dev/null 2>&1; then
-    echo "错误: 未找到 qemu-riscv64"
-    exit 1
-fi
-
-echo "=========================================="
-echo "RISC-V 基础功能测试"
-echo "=========================================="
-
-# 定义测试用例
-TESTS="arith:50 add:30 sub:7 mul:50 div:25 mod:2 var:43"
-
-PASS=0
-FAIL=0
-
-for test in $TESTS; do
-    name=$(echo $test | cut -d: -f1)
-    expected=$(echo $test | cut -d: -f2)
-    
-    echo -n "测试 $name (期望 $expected) ... "
-    
-    # 生成汇编
-    "$COMPILER" "$TEST_DIR/$name.sy" --emit-asm > /tmp/test_$name.s 2>&1
-    if [ $? -ne 0 ]; then
-        echo -e "${RED}失败 (汇编错误)${NC}"
-        FAIL=$((FAIL + 1))
-        continue
-    fi
-    
-    # 链接
-    riscv64-linux-gnu-gcc -static /tmp/test_$name.s -o /tmp/test_$name -no-pie 2>/dev/null
-    if [ $? -ne 0 ]; then
-        echo -e "${RED}失败 (链接错误)${NC}"
-        FAIL=$((FAIL + 1))
-        continue
-    fi
-    
-    # 运行
-    qemu-riscv64 /tmp/test_$name > /dev/null 2>&1
-    exit_code=$?
-    
-    if [ $exit_code -eq $expected ]; then
-        echo -e "${GREEN}通过${NC}"
-        PASS=$((PASS + 1))
-    else
-        echo -e "${RED}失败 (实际 $exit_code)${NC}"
-        FAIL=$((FAIL + 1))
-    fi
-done
-
-echo "=========================================="
-echo -e "测试结果: ${GREEN}通过 $PASS${NC} / ${RED}失败 $FAIL${NC}"
-echo "=========================================="
-
-if [ $FAIL -eq 0 ]; then
-    echo -e "${GREEN}✓ 所有基础测试通过！${NC}"
-    exit 0
-else
-    echo -e "${RED}✗ 有 $FAIL 个测试失败${NC}"
-    exit 1
-fi
\ No newline at end of file
diff --git a/src/irgen/IRGenExp.cpp b/src/irgen/IRGenExp.cpp
index 224e606..d1b88bb 100644
--- a/src/irgen/IRGenExp.cpp
+++ b/src/irgen/IRGenExp.cpp
@@ -7,9 +7,57 @@
 #include "ir/IR.h"
 #include "sem/func.h"
 #include "utils/Log.h"
-
+#include <cmath>   // 用于 ldexp
 // ─── 辅助 ─────────────────────────────────────────────────────────────────────
 
+
+// 静态辅助函数：解析十六进制浮点字面量
+static float ParseHexFloat(const std::string& str) {
+    const char* s = str.c_str();
+    // 跳过 "0x" 或 "0X"
+    if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) s += 2;
+
+    double significand = 0.0;
+    bool have_dot = false;
+    double dot_scale = 1.0 / 16.0;
+
+    while (*s && *s != 'p' && *s != 'P') {
+        if (*s == '.') {
+            have_dot = true;
+            ++s;
+            continue;
+        }
+        int digit = -1;
+        if (*s >= '0' && *s <= '9') digit = *s - '0';
+        else if (*s >= 'a' && *s <= 'f') digit = *s - 'a' + 10;
+        else if (*s >= 'A' && *s <= 'F') digit = *s - 'A' + 10;
+        if (digit >= 0) {
+            if (have_dot) {
+                significand += digit * dot_scale;
+                dot_scale /= 16.0;
+            } else {
+                significand = significand * 16 + digit;
+            }
+        }
+        ++s;
+    }
+
+    int exponent = 0;
+    if (*s == 'p' || *s == 'P') {
+        ++s;
+        int sign = 1;
+        if (*s == '-') { sign = -1; ++s; }
+        else if (*s == '+') { ++s; }
+        exponent = 0;
+        while (*s >= '0' && *s <= '9') {
+            exponent = exponent * 10 + (*s - '0');
+            ++s;
+        }
+        exponent *= sign;
+    }
+
+    return static_cast<float>(ldexp(significand, exponent));
+}
 // 把 i32/float 值转成 i1
 ir::Value* IRGenImpl::ToI1(ir::Value* v) {
   if (!v) throw std::runtime_error(FormatError("irgen", "ToI1: null value"));
@@ -571,11 +619,15 @@ std::any IRGenImpl::visitNumber(SysYParser::NumberContext* ctx) {
   if (ctx->FloatConst()) {
     std::string text = ctx->FloatConst()->getText();
     float val = 0.0f;
-    try {
-      val = std::stof(text);
-    } catch (...) {
-      throw std::runtime_error(
-          FormatError("irgen", "浮点字面量解析失败: " + text));
+    if (text.size() >= 2 && (text[1] == 'x' || text[1] == 'X')) {
+        val = ParseHexFloat(text);
+    } else {
+        try {
+            val = std::stof(text);
+        } catch (...) {
+            throw std::runtime_error(
+                FormatError("irgen", "浮点字面量解析失败: " + text));
+        }
     }
     return static_cast<ir::Value*>(builder_.CreateConstFloat(val));
   }
diff --git a/src/mir/AsmPrinter.cpp b/src/mir/AsmPrinter.cpp
index 3f8d776..dad9e72 100644
--- a/src/mir/AsmPrinter.cpp
+++ b/src/mir/AsmPrinter.cpp
@@ -24,7 +24,7 @@ const FrameSlot& GetFrameSlot(const MachineFunction& function,
 }
 
 // 32位整数加载/存储
-void EmitStackLoad(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::SP) {
+void EmitStackLoad(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
     os << "  lw " << PhysRegName(dst) << ", " << offset << "(" << PhysRegName(base) << ")\n";
   } else {
@@ -34,7 +34,7 @@ void EmitStackLoad(std::ostream& os, PhysReg dst, int offset, PhysReg base = Phy
   }
 }
 
-void EmitStackStore(std::ostream& os, PhysReg src, int offset, PhysReg base = PhysReg::SP) {
+void EmitStackStore(std::ostream& os, PhysReg src, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
     os << "  sw " << PhysRegName(src) << ", " << offset << "(" << PhysRegName(base) << ")\n";
   } else {
@@ -45,7 +45,7 @@ void EmitStackStore(std::ostream& os, PhysReg src, int offset, PhysReg base = Ph
 }
 
 // 64位指针加载/存储
-void EmitStackLoad64(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::SP) {
+void EmitStackLoad64(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
     os << "  ld " << PhysRegName(dst) << ", " << offset << "(" << PhysRegName(base) << ")\n";
   } else {
@@ -55,7 +55,7 @@ void EmitStackLoad64(std::ostream& os, PhysReg dst, int offset, PhysReg base = P
   }
 }
 
-void EmitStackStore64(std::ostream& os, PhysReg src, int offset, PhysReg base = PhysReg::SP) {
+void EmitStackStore64(std::ostream& os, PhysReg src, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
     os << "  sd " << PhysRegName(src) << ", " << offset << "(" << PhysRegName(base) << ")\n";
   } else {
@@ -66,7 +66,7 @@ void EmitStackStore64(std::ostream& os, PhysReg src, int offset, PhysReg base =
 }
 
 // 浮点加载/存储（保持32位）
-void EmitStackLoadFloat(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::SP) {
+void EmitStackLoadFloat(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
     os << "  flw " << PhysRegName(dst) << ", " << offset << "(" << PhysRegName(base) << ")\n";
   } else {
@@ -76,7 +76,7 @@ void EmitStackLoadFloat(std::ostream& os, PhysReg dst, int offset, PhysReg base
   }
 }
 
-void EmitStackStoreFloat(std::ostream& os, PhysReg src, int offset, PhysReg base = PhysReg::SP) {
+void EmitStackStoreFloat(std::ostream& os, PhysReg src, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
     os << "  fsw " << PhysRegName(src) << ", " << offset << "(" << PhysRegName(base) << ")\n";
   } else {
@@ -95,7 +95,8 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
   }
 
   int frame_size = function.GetFrameSize();        // 局部变量区大小（正数）
-  int total_frame_size = frame_size + 16;          // +16 用于保存 ra(8) 和 s0(8)
+  int local_vars = function.GetLocalVarsSize();
+  int total_frame = local_vars + 16 ;   
   bool prologue_done = false;
 
   for (const auto& block_ptr : function.GetBlocks()) {
@@ -111,19 +112,19 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
       
       // 在入口块的第一条指令前输出序言
       if (!prologue_done && block.GetName() == "entry") {
-        // 分配栈帧：sp -= total_frame_size
-        if (total_frame_size <= 2047) {
-          os << "  addi sp, sp, -" << total_frame_size << "\n";
+        // 分配栈帧：sp -= total_frame
+        if (total_frame <= 2047) {
+          os << "  addi sp, sp, -" << total_frame << "\n";
         } else {
-          os << "  li t4, -" << total_frame_size << "\n";
+          os << "  li t4, -" << total_frame << "\n";
           os << "  add sp, sp, t4\n";
         }
         
         // 保存 ra 和 s0（在局部变量区之后，即 sp + frame_size 处）
         // ra 保存在 sp + frame_size
         // s0 保存在 sp + frame_size + 8
-        int ra_offset = frame_size;
-        int s0_offset = frame_size + 8;
+        int ra_offset = local_vars;
+        int s0_offset = local_vars + 8;
         
         if (ra_offset <= 2047) {
           os << "  sd ra, " << ra_offset << "(sp)\n";
@@ -140,7 +141,7 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           os << "  add t4, sp, t4\n";
           os << "  sd s0, 0(t4)\n";
         }
-        
+        os << "  mv s0, sp\n";
         prologue_done = true;
       }
       
@@ -155,47 +156,94 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           break;
         
         case Opcode::Load: {
-          if (ops.size() == 2 && ops.at(1).GetKind() == Operand::Kind::Reg) {
-            // 寄存器间接寻址 - 使用 ld（64位）
-            os << "  ld " << PhysRegName(ops.at(0).GetReg()) << ", 0("
-               << PhysRegName(ops.at(1).GetReg()) << ")\n";
-          } else {
-            int frame_idx = ops.at(1).GetFrameIndex();
-            const auto& slot = function.GetFrameSlot(frame_idx);
-            // 根据槽大小决定加载宽度
-            if (slot.size == 8) {
-              EmitStackLoad64(os, ops.at(0).GetReg(), slot.offset);
-            } else {
-              EmitStackLoad(os, ops.at(0).GetReg(), slot.offset);
+            if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Reg) {
+                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", 0(" << PhysRegName(ops[1].GetReg()) << ")\n";
+            } /*else if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Imm) {
+                // 用于调用者 outgoing 存储的占位偏移（将在 Outgoing 中修正）
+                int offset = ops[1].GetImm();  // 实际偏移 = local_vars + 16 + offset
+                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", " << offset << "(sp)\n";*/
+            else {
+                int frame_idx = ops[1].GetFrameIndex();
+                const auto& slot = function.GetFrameSlot(frame_idx);
+                if (slot.size == 8) EmitStackLoad64(os, ops[0].GetReg(), slot.offset);
+                else EmitStackLoad(os, ops[0].GetReg(), slot.offset);
             }
-          }
-          break;
+            break;
         }
-        
+
         case Opcode::Store: {
-          if (ops.size() == 2 && ops.at(1).GetKind() == Operand::Kind::Reg) {
-            // 寄存器间接寻址 - 使用 sd（64位）
-            os << "  sd " << PhysRegName(ops.at(0).GetReg()) << ", 0("
-               << PhysRegName(ops.at(1).GetReg()) << ")\n";
-          } else {
-            int frame_idx = ops.at(1).GetFrameIndex();
-            const auto& slot = function.GetFrameSlot(frame_idx);
-            // 根据槽大小决定存储宽度
+            if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Reg) {
+                os << "  sd " << PhysRegName(ops[0].GetReg()) << ", 0(" << PhysRegName(ops[1].GetReg()) << ")\n";
+            } /*else if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Imm) {
+                int offset = ops[1].GetImm();
+                // 实际偏移需在 AsmPrinter 中加上 local_vars+16，这里简单先直接用 offset（动态修正稍复杂）
+                // 临时方案：直接生成 sw t0, offset(sp)，但 offset 应为 local_vars+16=?
+                // 由于 AsmPrinter 中可访问 function.GetLocalVarsSize()，我们计算：
+                int actual_offset = function.GetLocalVarsSize() + 16 + offset;
+                if (actual_offset <= 2047) os << "  sd " << PhysRegName(ops[0].GetReg()) << ", " << actual_offset << "(sp)\n";
+                else {  }*/
+            else {
+                int frame_idx = ops[1].GetFrameIndex();
+                const auto& slot = function.GetFrameSlot(frame_idx);
+                if (slot.size == 8) EmitStackStore64(os, ops[0].GetReg(), slot.offset);
+                else EmitStackStore(os, ops[0].GetReg(), slot.offset);
+            }
+            break;
+        }
+        
+        case Opcode::LoadCallerStackArg: {
+            // ops: [0] dst (T0), [1] dstFrameIndex, [2] argvIndex (Imm)
+            int argv_index = ops[2].GetImm();
+            int dst_slot = ops[1].GetFrameIndex();
+            int total_frame = function.GetFrameSize();
+            // 调用者栈参数位于 sp + total_frame + argv_index*8
+            int caller_offset = total_frame + argv_index * 8;
+            // 加载到 T0
+            if (caller_offset <= 2047) {
+                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", " << caller_offset << "(s0)\n";
+            } else {
+                os << "  li t4, " << caller_offset << "\n";
+                os << "  add t4, s0, t4\n";
+                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", 0(t4)\n";
+            }
+            // 再存入本地槽
+            const auto& slot = function.GetFrameSlot(dst_slot);
             if (slot.size == 8) {
-              EmitStackStore64(os, ops.at(0).GetReg(), slot.offset);
+                EmitStackStore64(os, ops[0].GetReg(), slot.offset);
             } else {
-              EmitStackStore(os, ops.at(0).GetReg(), slot.offset);
+                EmitStackStore(os, ops[0].GetReg(), slot.offset);
             }
+            break;
+        }
+      
+        case Opcode::LoadCallerStackArgFloat: {
+          int argv_index = ops.at(2).GetImm();
+          int dst_slot = ops.at(1).GetFrameIndex();
+          int total_frame = function.GetFrameSize();
+          int caller_offset = total_frame + argv_index * 8;
+          // 使用 s0 保证稳定
+          if (caller_offset <= 2047) {
+            os << "  flw " << PhysRegName(ops.at(0).GetReg()) << ", " << caller_offset << "(s0)\n";
+          } else {
+            os << "  li t4, " << caller_offset << "\n";
+            os << "  add t4, s0, t4\n";
+            os << "  flw " << PhysRegName(ops.at(0).GetReg()) << ", 0(t4)\n";
           }
+          const auto& slot = function.GetFrameSlot(dst_slot);
+          EmitStackStoreFloat(os, ops.at(0).GetReg(), slot.offset);
           break;
-        } 
-        
+        }
+
         case Opcode::Add:
           os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", "
              << PhysRegName(ops.at(1).GetReg()) << ", "
              << PhysRegName(ops.at(2).GetReg()) << "\n";
           break;
-        
+        case Opcode::Addi:
+          os << "  addi " << PhysRegName(ops[0].GetReg()) << ", "
+            << PhysRegName(ops[1].GetReg()) << ", "
+            << ops[2].GetImm() << "\n";
+          break;
         case Opcode::Sub:
           os << "  sub " << PhysRegName(ops.at(0).GetReg()) << ", "
              << PhysRegName(ops.at(1).GetReg()) << ", "
@@ -284,7 +332,10 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           os << "  lw " << PhysRegName(ops.at(0).GetReg()) << ", 0("
              << PhysRegName(ops.at(1).GetReg()) << ")\n";
           break;
-        
+        case Opcode::LoadIndirectFloat:
+          os << "  flw " << PhysRegName(ops[0].GetReg()) << ", 0("
+             << PhysRegName(ops[1].GetReg()) << ")\n";
+          break;
         case Opcode::Call: {
           std::string func_name = "memset"; // 默认值
           if (!ops.empty() && ops[0].GetKind() == Operand::Kind::Func) {
@@ -299,10 +350,10 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           const auto& slot = function.GetFrameSlot(frame_idx);
           // 计算地址（64 位），offset 是正数
           if (slot.offset <= 2047) {
-            os << "  addi " << PhysRegName(ops.at(0).GetReg()) << ", sp, " << slot.offset << "\n";
+            os << "  addi " << PhysRegName(ops.at(0).GetReg()) << ", s0, " << slot.offset << "\n";
           } else {
             os << "  li " << PhysRegName(ops.at(0).GetReg()) << ", " << slot.offset << "\n";
-            os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", sp, " 
+            os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", s0, " 
               << PhysRegName(ops.at(0).GetReg()) << "\n";
           }
           break;
@@ -319,35 +370,39 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           os << "  sw " << PhysRegName(ops.at(0).GetReg()) << ", 0("
              << PhysRegName(ops.at(1).GetReg()) << ")\n";
           break;
-        
+        case Opcode::StoreIndirectFloat:
+          os << "  fsw " << PhysRegName(ops[0].GetReg()) << ", 0("
+             << PhysRegName(ops[1].GetReg()) << ")\n";
+          break;
         case Opcode::Ret:{
           // 恢复 ra 和 s0
-          int ra_offset = frame_size;
-          int s0_offset = frame_size + 8;
+          int ra_offset = local_vars;
+          int s0_offset = local_vars + 8;
           
           if (ra_offset <= 2047) {
-            os << "  ld ra, " << ra_offset << "(sp)\n";
+            os << "  ld ra, " << ra_offset << "(s0)\n";
           } else {
             os << "  li t3, " << ra_offset << "\n";
-            os << "  add t3, sp, t3\n";
+            os << "  add t3, s0, t3\n";
             os << "  ld ra, 0(t3)\n";
           }
-          
+
+           // 恢复 sp
+          if (total_frame <= 2047) {
+            os << "  addi sp, s0, " << total_frame << "\n";
+          } else {
+            os << "  li t3, " << total_frame << "\n";
+            os << "  add sp, s0, t3\n";
+          }
+
           if (s0_offset <= 2047) {
-            os << "  ld s0, " << s0_offset << "(sp)\n";
+            os << "  ld s0, " << s0_offset << "(s0)\n";
           } else {
             os << "  li t3, " << s0_offset << "\n";
-            os << "  add t3, sp, t3\n";
+            os << "  add t3, s0, t3\n";
             os << "  ld s0, 0(t3)\n";
           }
           
-          // 恢复 sp
-          if (total_frame_size <= 2047) {
-            os << "  addi sp, sp, " << total_frame_size << "\n";
-          } else {
-            os << "  li t3, " << total_frame_size << "\n";
-            os << "  add sp, sp, t3\n";
-          }
           
           os << "  ret\n";
           break;
@@ -360,17 +415,22 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
         }
         
         case Opcode::CondBr: {
-          auto* true_target = reinterpret_cast<MachineBasicBlock*>(ops[1].GetImm64());
-          auto* false_target = reinterpret_cast<MachineBasicBlock*>(ops[2].GetImm64());
-          auto true_it = block_names.find(true_target);
-          auto false_it = block_names.find(false_target);
-          if (true_it == block_names.end() || false_it == block_names.end()) {
-            throw std::runtime_error(FormatError("mir", "CondBr: 找不到基本块名称"));
-          }
-          os << "  bnez " << PhysRegName(ops[0].GetReg()) << ", " 
-             << true_it->second << "\n";
-          os << "  j " << false_it->second << "\n";
-          break;
+            auto* true_target = reinterpret_cast<MachineBasicBlock*>(ops[1].GetImm64());
+            auto* false_target = reinterpret_cast<MachineBasicBlock*>(ops[2].GetImm64());
+            auto true_it = block_names.find(true_target);
+            auto false_it = block_names.find(false_target);
+            if (true_it == block_names.end() || false_it == block_names.end()) {
+                throw std::runtime_error(FormatError("mir", "CondBr: 找不到基本块名称"));
+            }
+
+            // 生成一个唯一的本地标签作为跳板
+            static int condbr_id = 0;
+            std::string temp_label = ".L_condbr_" + std::to_string(condbr_id++);
+            os << "  bnez " << PhysRegName(ops[0].GetReg()) << ", " << temp_label << "\n";
+            os << "  j " << false_it->second << "\n";
+            os << temp_label << ":\n";
+            os << "  j " << true_it->second << "\n";
+            break;
         }
         
         // 浮点运算
@@ -438,7 +498,7 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
         
         case Opcode::FPToSI:
           os << "  fcvt.w.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << "\n";
+            << PhysRegName(ops[1].GetReg()) << ", rtz\n";
           break;
 
         case Opcode::LoadFloat:
@@ -477,73 +537,97 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
 // 输出多个函数的汇编
 void PrintAsm(const std::vector<std::unique_ptr<MachineFunction>>& functions, std::ostream& os) {
   // ========== 输出全局变量 ==========
-  
-  // 输出 .data 段（已初始化的全局变量）
+
+  // .data 段：非常量变量
   bool hasData = false;
   for (const auto& gv : g_globalVars) {
-    if (!gv.isConst) {
-      if (!hasData) {
-        os << ".data\n";
-        hasData = true;
-      }
-      os << "  .global " << gv.name << "\n";
-      os << "  .type " << gv.name << ", @object\n";
-    
-      if (gv.isArray && gv.arraySize > 1) {
-        int totalSize = gv.arraySize * 4;
-        os << "  .size " << gv.name << ", " << totalSize << "\n";
-        os << gv.name << ":\n";
-      
-        if (!gv.arrayValues.empty()) {
-          for (int val : gv.arrayValues) {
-            os << "  .word " << val << "\n";
+    if (gv.isConst) continue;   // 常量到 .rodata
+    if (!hasData) {
+      os << ".data\n";
+      hasData = true;
+    }
+    os << "  .global " << gv.name << "\n";
+    os << "  .type " << gv.name << ", @object\n";
+
+    if (gv.isArray && gv.arraySize > 1) {
+      int totalSize = gv.arraySize * 4;
+      os << "  .size " << gv.name << ", " << totalSize << "\n";
+      os << gv.name << ":\n";
+      if (gv.isFloat) {
+        if (!gv.arrayValuesF.empty()) {
+          for (float val : gv.arrayValuesF) {
+            union { float f; uint32_t i; } u;
+            u.f = val;
+            os << "  .word " << u.i << "\n";
           }
         } else {
-          for (int i = 0; i < gv.arraySize; i++) {
-            os << "  .word 0\n";
-          }
+          for (int i = 0; i < gv.arraySize; i++) os << "  .word 0\n";
+        }
+      } else {
+        if (!gv.arrayValues.empty()) {
+          for (int val : gv.arrayValues) os << "  .word " << val << "\n";
+        } else {
+          for (int i = 0; i < gv.arraySize; i++) os << "  .word 0\n";
         }
+      }
+    } else {
+      os << "  .size " << gv.name << ", 4\n";
+      os << gv.name << ":\n";
+      if (gv.isFloat) {
+        union { float f; uint32_t i; } u;
+        u.f = gv.valueF;
+        os << "  .word " << u.i << "\n";
       } else {
-        os << "  .size " << gv.name << ", 4\n";
-        os << gv.name << ":\n";
         os << "  .word " << gv.value << "\n";
       }
     }
   }
 
-  // 输出 .rodata 段（只读常量）
+  // .rodata 段：只读常量
   bool hasRodata = false;
   for (const auto& gv : g_globalVars) {
-    if (gv.isConst) {
-      if (!hasRodata) {
-        os << ".section .rodata\n";
-        hasRodata = true;
-      }
-      os << "  .global " << gv.name << "\n";
-      os << "  .type " << gv.name << ", @object\n";
-      
-      if (gv.isArray && gv.arraySize > 1) {
-        int totalSize = gv.arraySize * 4;
-        os << "  .size " << gv.name << ", " << totalSize << "\n";
-        os << gv.name << ":\n";
-        
-        if (!gv.arrayValues.empty()) {
-          for (int val : gv.arrayValues) {
-            os << "  .word " << val << "\n";
+    if (!gv.isConst) continue;
+    if (!hasRodata) {
+      os << ".section .rodata\n";
+      hasRodata = true;
+    }
+    os << "  .global " << gv.name << "\n";
+    os << "  .type " << gv.name << ", @object\n";
+
+    if (gv.isArray && gv.arraySize > 1) {
+      int totalSize = gv.arraySize * 4;
+      os << "  .size " << gv.name << ", " << totalSize << "\n";
+      os << gv.name << ":\n";
+      if (gv.isFloat) {
+        if (!gv.arrayValuesF.empty()) {
+          for (float val : gv.arrayValuesF) {
+            union { float f; uint32_t i; } u;
+            u.f = val;
+            os << "  .word " << u.i << "\n";
           }
         } else {
-          for (int i = 0; i < gv.arraySize; i++) {
-            os << "  .word 0\n";
-          }
+          for (int i = 0; i < gv.arraySize; i++) os << "  .word 0\n";
+        }
+      } else {
+        if (!gv.arrayValues.empty()) {
+          for (int val : gv.arrayValues) os << "  .word " << val << "\n";
+        } else {
+          for (int i = 0; i < gv.arraySize; i++) os << "  .word 0\n";
         }
+      }
+    } else {
+      os << "  .size " << gv.name << ", 4\n";
+      os << gv.name << ":\n";
+      if (gv.isFloat) {
+        union { float f; uint32_t i; } u;
+        u.f = gv.valueF;
+        os << "  .word " << u.i << "\n";
       } else {
-        os << "  .size " << gv.name << ", 4\n";
-        os << gv.name << ":\n";
         os << "  .word " << gv.value << "\n";
       }
     }
   }
-  
+
   // ========== 输出代码段 ==========
   os << ".text\n";
   
diff --git a/src/mir/FrameLowering.cpp b/src/mir/FrameLowering.cpp
index 367dbc5..9e04a74 100644
--- a/src/mir/FrameLowering.cpp
+++ b/src/mir/FrameLowering.cpp
@@ -18,19 +18,22 @@ void RunFrameLowering(MachineFunction& function) {
   int cursor = 0;
   const auto& slots = function.GetFrameSlots();
 
-  // 为每个栈槽分配偏移：正偏移，表示相对于 sp 的偏移量
-  // 栈向下增长，sp 减小后，局部变量在 sp 上方（正偏移）
+  // 为每个栈槽分配偏移
   for (const auto& slot : slots) {
-    int align = slot.size;                // 自然对齐（4 或 8 字节）
-    cursor = AlignTo(cursor, align);      // 对齐到所需边界
-    function.GetFrameSlot(slot.index).offset = cursor;  // 正偏移
-    cursor += slot.size;                  // 分配空间
+    int align = slot.size;
+    cursor = AlignTo(cursor, align);
+    function.GetFrameSlot(slot.index).offset = cursor;
+    cursor += slot.size;
   }
 
-  // 栈帧总大小（局部变量区域）按 16 字节对齐
-  function.SetFrameSize(AlignTo(cursor, 16));
+  // 局部变量区按 16 字节对齐
+  int local_vars_size = AlignTo(cursor, 16);
+  function.SetLocalVarsSize(local_vars_size);
 
-  // 在入口块插入 Prologue/Epilogue 占位符
+  // 总帧大小 = 局部变量区 + 16（保存 ra 和 s0）
+  function.SetFrameSize(local_vars_size + 16);
+
+  // 插入 Prologue/Epilogue 占位符（原逻辑）
   auto& insts = function.GetEntry()->GetInstructions();
   std::vector<MachineInstr> lowered;
   lowered.emplace_back(Opcode::Prologue);
diff --git a/src/mir/Lowering.cpp b/src/mir/Lowering.cpp
index 01cefd6..ecadd48 100644
--- a/src/mir/Lowering.cpp
+++ b/src/mir/Lowering.cpp
@@ -27,6 +27,7 @@ static bool IsFloatReg(PhysReg reg) {
 using ValueSlotMap = std::unordered_map<const ir::Value*, int>;
 static std::unordered_map<const ir::BasicBlock*, MachineBasicBlock*> block_map;
 
+
 MachineBasicBlock* GetOrCreateBlock(const ir::BasicBlock* ir_block, 
                                      MachineFunction& function) {
   auto it = block_map.find(ir_block);
@@ -45,14 +46,20 @@ MachineBasicBlock* GetOrCreateBlock(const ir::BasicBlock* ir_block,
 
 void EmitValueToReg(const ir::Value* value, PhysReg target,
                     const ValueSlotMap& slots, MachineBasicBlock& block,
-                    bool for_address = false) {
+                    MachineFunction& function, bool for_address = false){
   // 处理参数（Argument）
   if (auto* arg = dynamic_cast<const ir::Argument*>(value)) {
     auto it = slots.find(arg);
     if (it != slots.end()) {
       bool src_is_float = value->GetType()->IsFloat32();
       bool dst_is_float = IsFloatReg(target);
-      if (src_is_float && !dst_is_float) {
+      if (src_is_float == dst_is_float) {
+        // 同类型 → 直接加载，不转换
+        if (src_is_float)
+          block.Append(Opcode::LoadFloat, {Operand::Reg(target), Operand::FrameIndex(it->second)});
+        else
+          block.Append(Opcode::Load, {Operand::Reg(target), Operand::FrameIndex(it->second)});
+      } else if (src_is_float && !dst_is_float) {
         // 浮点 -> 整数
         block.Append(Opcode::LoadFloat,
                      {Operand::Reg(PhysReg::FT0), Operand::FrameIndex(it->second)});
@@ -62,16 +69,7 @@ void EmitValueToReg(const ir::Value* value, PhysReg target,
         block.Append(Opcode::Load,
                      {Operand::Reg(PhysReg::T0), Operand::FrameIndex(it->second)});
         block.Append(Opcode::SIToFP, {Operand::Reg(target), Operand::Reg(PhysReg::T0)});
-      } else {
-        // 同类型直接加载
-        if (src_is_float) {
-          block.Append(Opcode::LoadFloat,
-                       {Operand::Reg(target), Operand::FrameIndex(it->second)});
-        } else {
-          block.Append(Opcode::Load,
-                       {Operand::Reg(target), Operand::FrameIndex(it->second)});
-        }
-      }
+      } 
       return;
     }
   }
@@ -84,27 +82,32 @@ void EmitValueToReg(const ir::Value* value, PhysReg target,
     return;
   }
 
-  // 处理浮点常量
+    // 处理浮点常量
   if (auto* fconstant = dynamic_cast<const ir::ConstantFloat*>(value)) {
-    float val = fconstant->GetValue();
+    // 直接使用标准的 double -> float 转换，无需特殊分支
+    float fval = static_cast<float>(fconstant->GetValue());
     uint32_t bits;
-    memcpy(&bits, &val, sizeof(val));
-    bool target_is_fp = IsFloatReg(target);
-    if (target_is_fp) {
-      block.Append(Opcode::MovImm,
-                   {Operand::Reg(PhysReg::T0), Operand::Imm(static_cast<int>(bits))});
-      block.Append(Opcode::FMovWX, {Operand::Reg(target), Operand::Reg(PhysReg::T0)});
+    std::memcpy(&bits, &fval, sizeof(fval));
+    int32_t imm = static_cast<int32_t>(bits);
+
+    if (IsFloatReg(target)) {
+        // 通过栈槽加载以保证浮点寄存器符合 NaN‑boxing 要求
+        int tmp_slot = function.CreateFrameIndex(4);
+        block.Append(Opcode::MovImm, {Operand::Reg(PhysReg::T4), Operand::Imm(imm)});
+        block.Append(Opcode::Store, {Operand::Reg(PhysReg::T4),
+                                    Operand::FrameIndex(tmp_slot)});
+        block.Append(Opcode::LoadFloat, {Operand::Reg(target),
+                                        Operand::FrameIndex(tmp_slot)});
     } else {
-      block.Append(Opcode::MovImm,
-                   {Operand::Reg(target), Operand::Imm(static_cast<int>(bits))});
+        block.Append(Opcode::MovImm, {Operand::Reg(target), Operand::Imm(imm)});
     }
     return;
   }
 
   // 处理 GEP 指令
   if (auto* gep = dynamic_cast<const ir::GepInst*>(value)) {
-    EmitValueToReg(gep->GetBasePtr(), target, slots, block, true);
-    EmitValueToReg(gep->GetIndex(), PhysReg::T1, slots, block);
+    EmitValueToReg(gep->GetBasePtr(), target, slots, block,function, true);
+    EmitValueToReg(gep->GetIndex(), PhysReg::T1, slots, block,function);
     block.Append(Opcode::Slli, {Operand::Reg(PhysReg::T1),
                                  Operand::Reg(PhysReg::T1),
                                  Operand::Imm(2)});
@@ -140,7 +143,7 @@ void EmitValueToReg(const ir::Value* value, PhysReg target,
     return;
   }
 
-  // 处理一般栈槽中的值
+    // 处理一般栈槽中的值
   auto it = slots.find(value);
   if (it != slots.end()) {
     bool src_is_float = value->GetType()->IsFloat32();
@@ -202,25 +205,54 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
     
     case ir::Opcode::Store: {
       auto& store = static_cast<const ir::StoreInst&>(inst);
-      if (dynamic_cast<const ir::GepInst*>(store.GetPtr())) {
-        EmitValueToReg(store.GetValue(), PhysReg::T2, slots, block);
-        EmitValueToReg(store.GetPtr(), PhysReg::T0, slots, block, true);
-        block.Append(Opcode::StoreIndirect,
-                 {Operand::Reg(PhysReg::T2), Operand::Reg(PhysReg::T0)});
+      // 如果指针是 GEP，手动生成地址并 store，避免额外计算
+      if (auto* gep = dynamic_cast<const ir::GepInst*>(store.GetPtr())) {
+        // 判断值的类型是否为浮点
+        bool val_is_float = store.GetValue()->GetType()->IsFloat32();
+
+        if (val_is_float) {
+          // 将浮点值加载到 FT0
+          EmitValueToReg(store.GetValue(), PhysReg::FT0, slots, block, function);
+        } else {
+          // 整数值加载到 T2
+          EmitValueToReg(store.GetValue(), PhysReg::T2, slots, block, function);
+        }
+
+        // 计算基址 + 索引*4
+        EmitValueToReg(gep->GetBasePtr(), PhysReg::T0, slots, block, function, true);
+        auto idx_it = slots.find(gep->GetIndex());
+        if (idx_it != slots.end()) {
+          block.Append(Opcode::Load, {Operand::Reg(PhysReg::T1), Operand::FrameIndex(idx_it->second)});
+        } else {
+          EmitValueToReg(gep->GetIndex(), PhysReg::T1, slots, block, function);
+        }
+        block.Append(Opcode::Slli, {Operand::Reg(PhysReg::T1), Operand::Reg(PhysReg::T1), Operand::Imm(2)});
+        block.Append(Opcode::Add, {Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T1)});
+
+        // 使用正确的间接存储操作码
+        if (val_is_float) {
+          block.Append(Opcode::StoreIndirectFloat, {Operand::Reg(PhysReg::FT0), Operand::Reg(PhysReg::T0)});
+        } else {
+          block.Append(Opcode::StoreIndirect, {Operand::Reg(PhysReg::T2), Operand::Reg(PhysReg::T0)});
+        }
         return;
       }
       if (auto* global = dynamic_cast<const ir::GlobalVariable*>(store.GetPtr())) {
-        EmitValueToReg(store.GetValue(), PhysReg::T0, slots, block);
+        EmitValueToReg(store.GetValue(), PhysReg::T0, slots, block, function);
         std::string global_name = global->GetName();
-        block.Append(Opcode::StoreGlobal,
-               {Operand::Reg(PhysReg::T0), Operand::Global(global_name)});
+        block.Append(Opcode::StoreGlobal, {Operand::Reg(PhysReg::T0), Operand::Global(global_name)});
         return;
       }
-      
       auto dst = slots.find(store.GetPtr());
       if (dst != slots.end()) {
-        EmitValueToReg(store.GetValue(), PhysReg::T0, slots, block);
-        StoreRegToSlot(PhysReg::T0, dst->second, block);
+        bool val_is_float = store.GetValue()->GetType()->IsFloat32();
+        if (val_is_float) {
+          EmitValueToReg(store.GetValue(), PhysReg::FT0, slots, block, function);
+          StoreRegToSlot(PhysReg::FT0, dst->second, block, true);
+        } else {
+          EmitValueToReg(store.GetValue(), PhysReg::T0, slots, block, function);
+          StoreRegToSlot(PhysReg::T0, dst->second, block, false);
+        }
         return;
       }
       throw std::runtime_error(FormatError("mir", "Store: 无法处理的指针类型"));
@@ -228,9 +260,36 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
     
     case ir::Opcode::Load: {
       auto& load = static_cast<const ir::LoadInst&>(inst);
-      
+            if (auto* gep = dynamic_cast<const ir::GepInst*>(load.GetPtr())) {
+        // 计算地址到 T0
+        EmitValueToReg(gep->GetBasePtr(), PhysReg::T0, slots, block, function, true);
+        
+        auto idx_it = slots.find(gep->GetIndex());
+        if (idx_it != slots.end()) {
+          block.Append(Opcode::Load, {Operand::Reg(PhysReg::T1), Operand::FrameIndex(idx_it->second)});
+        } else {
+          EmitValueToReg(gep->GetIndex(), PhysReg::T1, slots, block, function);
+        }
+        block.Append(Opcode::Slli, {Operand::Reg(PhysReg::T1), Operand::Reg(PhysReg::T1), Operand::Imm(2)});
+        block.Append(Opcode::Add, {Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T1)});
+
+        bool load_is_float = load.GetType()->IsFloat32();
+        int dst_slot = function.CreateFrameIndex(4);
+
+        if (load_is_float) {
+          // 浮点加载：FT0 = [T0]
+          block.Append(Opcode::LoadIndirectFloat, {Operand::Reg(PhysReg::FT0), Operand::Reg(PhysReg::T0)});
+          StoreRegToSlot(PhysReg::FT0, dst_slot, block, true);
+        } else {
+          // 整数加载
+          block.Append(Opcode::LoadIndirect, {Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T0)});
+          StoreRegToSlot(PhysReg::T0, dst_slot, block, false);
+        }
+        slots.emplace(&inst, dst_slot);
+        return;
+      }
       if (dynamic_cast<const ir::GepInst*>(load.GetPtr())) {
-        EmitValueToReg(load.GetPtr(), PhysReg::T0, slots, block, true);
+        EmitValueToReg(load.GetPtr(), PhysReg::T0, slots, block, function, true);
         block.Append(Opcode::LoadIndirect,
                     {Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T0)});
         int dst_slot = function.CreateFrameIndex(4);
@@ -294,8 +353,8 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       int dst_slot = function.CreateFrameIndex(4);
 
       if (result_is_float) {
-        EmitValueToReg(bin.GetLhs(), PhysReg::FT0, slots, block);
-        EmitValueToReg(bin.GetRhs(), PhysReg::FT1, slots, block);
+        EmitValueToReg(bin.GetLhs(), PhysReg::FT0, slots, block, function);
+        EmitValueToReg(bin.GetRhs(), PhysReg::FT1, slots, block, function);
 
         Opcode op;
         switch (inst.GetOpcode()) {
@@ -310,8 +369,8 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
                           Operand::Reg(PhysReg::FT1)});
         StoreRegToSlot(PhysReg::FT0, dst_slot, block, true);
       } else {
-        EmitValueToReg(bin.GetLhs(), PhysReg::T0, slots, block);
-        EmitValueToReg(bin.GetRhs(), PhysReg::T1, slots, block);
+        EmitValueToReg(bin.GetLhs(), PhysReg::T0, slots, block, function);
+        EmitValueToReg(bin.GetRhs(), PhysReg::T1, slots, block, function);
 
         Opcode op;
         switch (inst.GetOpcode()) {
@@ -338,39 +397,124 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
     }
     
     case ir::Opcode::Call: {
-      auto& call = static_cast<const ir::CallInst&>(inst);
-      for (size_t i = 0; i < call.GetNumArgs() && i < 8; i++) {
-        // 根据参数的实际类型决定使用浮点还是整数寄存器
-        bool arg_is_float = call.GetArg(i)->GetType()->IsFloat32();
-        if (arg_is_float) {
-          PhysReg floatArgReg = static_cast<PhysReg>(static_cast<int>(PhysReg::FA0) + i);
-          EmitValueToReg(call.GetArg(i), floatArgReg, slots, block);
-        } else {
-          PhysReg intArgReg = static_cast<PhysReg>(static_cast<int>(PhysReg::A0) + i);
-          EmitValueToReg(call.GetArg(i), intArgReg, slots, block);
+        auto& call = static_cast<const ir::CallInst&>(inst);
+        int numArgs = static_cast<int>(call.GetNumArgs());
+
+        int ireg = 0, freg = 0;
+        std::vector<std::pair<bool, ir::Value*>> stack_args; // (is_float, value)
+
+        for (int i = 0; i < numArgs; ++i) {
+            bool arg_is_float = call.GetArg(i)->GetType()->IsFloat32();
+            if (arg_is_float) {
+                if (freg < 8) {
+                    PhysReg fregnum = static_cast<PhysReg>(static_cast<int>(PhysReg::FA0) + freg);
+                    EmitValueToReg(call.GetArg(i), fregnum, slots, block, function);
+                    freg++;
+                } else {
+                    stack_args.push_back({true, call.GetArg(i)});
+                }
+            } else { // integer or pointer
+                if (ireg < 8) {
+                    PhysReg iregnum = static_cast<PhysReg>(static_cast<int>(PhysReg::A0) + ireg);
+                    EmitValueToReg(call.GetArg(i), iregnum, slots, block, function);
+                    ireg++;
+                } else {
+                    stack_args.push_back({false, call.GetArg(i)});
+                }
+            }
         }
-      }
-      std::string func_name = call.GetCalleeName();
-      block.Append(Opcode::Call, {Operand::Func(func_name)});
-      if (!call.GetType()->IsVoid()) {
-        int dst_slot = function.CreateFrameIndex();
-        bool ret_is_float = call.GetType()->IsFloat32();
-        if (ret_is_float) {
-          StoreRegToSlot(PhysReg::FA0, dst_slot, block, true);
-        } else {
-          StoreRegToSlot(PhysReg::A0, dst_slot, block, false);
+
+        int stackArgs = static_cast<int>(stack_args.size());
+        if (stackArgs > 0) {
+            int stackSpace = (stackArgs * 8 + 15) & ~15;
+            // sp -= stackSpace
+            if (stackSpace <= 2047) {
+                block.Append(Opcode::Addi, {Operand::Reg(PhysReg::SP),
+                                            Operand::Reg(PhysReg::SP),
+                                            Operand::Imm(-stackSpace)});
+            } else {
+                block.Append(Opcode::MovImm, {Operand::Reg(PhysReg::T4), Operand::Imm(-stackSpace)});
+                block.Append(Opcode::Add, {Operand::Reg(PhysReg::SP),
+                                            Operand::Reg(PhysReg::SP),
+                                            Operand::Reg(PhysReg::T4)});
+            }
+
+            for (int idx = 0; idx < stackArgs; ++idx) {
+                bool is_float = stack_args[idx].first;
+                ir::Value* val = stack_args[idx].second;
+                int offset = idx * 8;
+
+                // 1. 先加载值
+                if (is_float) {
+                    EmitValueToReg(val, PhysReg::FT0, slots, block, function);
+                } else {
+                    EmitValueToReg(val, PhysReg::T0, slots, block, function);
+                }
+
+                // 2. 再计算栈地址到 T4
+                if (offset == 0) {
+                    block.Append(Opcode::Add, {Operand::Reg(PhysReg::T4),
+                                              Operand::Reg(PhysReg::SP),
+                                              Operand::Reg(PhysReg::ZERO)});
+                } else if (offset <= 2047) {
+                    block.Append(Opcode::Addi, {Operand::Reg(PhysReg::T4),
+                                                Operand::Reg(PhysReg::SP),
+                                                Operand::Imm(offset)});
+                } else {
+                    block.Append(Opcode::MovImm, {Operand::Reg(PhysReg::T4), Operand::Imm(offset)});
+                    block.Append(Opcode::Add, {Operand::Reg(PhysReg::T4),
+                                              Operand::Reg(PhysReg::SP),
+                                              Operand::Reg(PhysReg::T4)});
+                }
+
+                // 3. 存储
+                if (is_float) {
+                    block.Append(Opcode::StoreFloat, {Operand::Reg(PhysReg::FT0), Operand::Reg(PhysReg::T4)});
+                } else {
+                    block.Append(Opcode::Store, {Operand::Reg(PhysReg::T0), Operand::Reg(PhysReg::T4)});
+                }
+            }
         }
-        slots.emplace(&inst, dst_slot);
-      }
-      return;
+
+        // 调用目标
+        std::string func_name = call.GetCalleeName();
+        block.Append(Opcode::Call, {Operand::Func(func_name)});
+
+        // 恢复 sp
+        if (stackArgs > 0) {
+            int stackSpace = (stackArgs * 8 + 15) & ~15;
+            if (stackSpace <= 2047) {
+                block.Append(Opcode::Addi, {Operand::Reg(PhysReg::SP),
+                                            Operand::Reg(PhysReg::SP),
+                                            Operand::Imm(stackSpace)});
+            } else {
+                block.Append(Opcode::MovImm, {Operand::Reg(PhysReg::T4), Operand::Imm(stackSpace)});
+                block.Append(Opcode::Add, {Operand::Reg(PhysReg::SP),
+                                            Operand::Reg(PhysReg::SP),
+                                            Operand::Reg(PhysReg::T4)});
+            }
+        }
+
+        // 返回值处理（原有代码保持不变）
+        if (!call.GetType()->IsVoid()) {
+            int dst_slot = function.CreateFrameIndex();
+            bool ret_is_float = call.GetType()->IsFloat32();
+            if (ret_is_float) {
+                StoreRegToSlot(PhysReg::FA0, dst_slot, block, true);
+            } else {
+                StoreRegToSlot(PhysReg::A0, dst_slot, block, false);
+            }
+            slots.emplace(&inst, dst_slot);
+        }
+        return;
     }
-    
+
     case ir::Opcode::ICmp: {
       auto& icmp = static_cast<const ir::ICmpInst&>(inst);
       int dst_slot = function.CreateFrameIndex();
       
-      EmitValueToReg(icmp.GetLhs(), PhysReg::T0, slots, block);
-      EmitValueToReg(icmp.GetRhs(), PhysReg::T1, slots, block);
+      EmitValueToReg(icmp.GetLhs(), PhysReg::T0, slots, block, function);
+      EmitValueToReg(icmp.GetRhs(), PhysReg::T1, slots, block, function);
       
       ir::ICmpPredicate pred = icmp.GetPredicate();
       
@@ -401,26 +545,29 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
                                        Operand::Reg(PhysReg::T0),
                                        Operand::Reg(PhysReg::T1)});
           break;
-        case ir::ICmpPredicate::SLE:
-          block.Append(Opcode::Slt, {Operand::Reg(PhysReg::T1),
-                                       Operand::Reg(PhysReg::T1),
-                                       Operand::Reg(PhysReg::T0)});
-          block.Append(Opcode::Xori, {Operand::Reg(PhysReg::T0),
-                                        Operand::Reg(PhysReg::T1),
-                                        Operand::Imm(1)});
-          break;
         case ir::ICmpPredicate::SGT:
           block.Append(Opcode::Slt, {Operand::Reg(PhysReg::T0),
                                        Operand::Reg(PhysReg::T1),
                                        Operand::Reg(PhysReg::T0)});
           break;
         case ir::ICmpPredicate::SGE:
-          block.Append(Opcode::Slt, {Operand::Reg(PhysReg::T1),
-                                       Operand::Reg(PhysReg::T1),
-                                       Operand::Reg(PhysReg::T0)});
+          // lhs >= rhs 等价于 !(lhs < rhs)
+          block.Append(Opcode::Slt, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::T1)});
           block.Append(Opcode::Xori, {Operand::Reg(PhysReg::T0),
-                                        Operand::Reg(PhysReg::T1),
-                                        Operand::Imm(1)});
+                                      Operand::Reg(PhysReg::T0),
+                                      Operand::Imm(1)});
+          break;
+
+        case ir::ICmpPredicate::SLE:
+          // lhs <= rhs 等价于 !(rhs < lhs)
+          block.Append(Opcode::Slt, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::T1),
+                                      Operand::Reg(PhysReg::T0)}); // 注意操作数顺序：rhs < lhs
+          block.Append(Opcode::Xori, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::T0),
+                                      Operand::Imm(1)});
           break;
       }
       
@@ -432,7 +579,7 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       auto& zext = static_cast<const ir::ZExtInst&>(inst);
       int dst_slot = function.CreateFrameIndex(4);
       
-      EmitValueToReg(zext.GetSrc(), PhysReg::T0, slots, block);
+      EmitValueToReg(zext.GetSrc(), PhysReg::T0, slots, block, function);
       StoreRegToSlot(PhysReg::T0, dst_slot, block);
       slots.emplace(&inst, dst_slot);
       return;
@@ -442,36 +589,51 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       auto& fcmp = static_cast<const ir::FCmpInst&>(inst);
       int dst_slot = function.CreateFrameIndex(4);
       
-      EmitValueToReg(fcmp.GetLhs(), PhysReg::FT0, slots, block);
-      EmitValueToReg(fcmp.GetRhs(), PhysReg::FT1, slots, block);
+      EmitValueToReg(fcmp.GetLhs(), PhysReg::FT0, slots, block, function);
+      EmitValueToReg(fcmp.GetRhs(), PhysReg::FT1, slots, block, function);
       
       ir::FCmpPredicate pred = fcmp.GetPredicate();
       
       switch (pred) {
         case ir::FCmpPredicate::OEQ:
-          block.Append(Opcode::FEq, {Operand::Reg(PhysReg::FT0),
+          block.Append(Opcode::FEq, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::FT0),
+                                      Operand::Reg(PhysReg::FT1)});
+          break;
+        case ir::FCmpPredicate::ONE:
+          block.Append(Opcode::FEq, {Operand::Reg(PhysReg::T0),
                                       Operand::Reg(PhysReg::FT0),
                                       Operand::Reg(PhysReg::FT1)});
+          block.Append(Opcode::Xori, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::T0),
+                                      Operand::Imm(1)});
           break;
         case ir::FCmpPredicate::OLT:
-          block.Append(Opcode::FLt, {Operand::Reg(PhysReg::FT0),
+          block.Append(Opcode::FLt, {Operand::Reg(PhysReg::T0),
                                       Operand::Reg(PhysReg::FT0),
                                       Operand::Reg(PhysReg::FT1)});
           break;
+        case ir::FCmpPredicate::OGT:
+          block.Append(Opcode::FLt, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::FT1),
+                                      Operand::Reg(PhysReg::FT0)});
+          break;
         case ir::FCmpPredicate::OLE:
-          block.Append(Opcode::FLe, {Operand::Reg(PhysReg::FT0),
+          block.Append(Opcode::FLe, {Operand::Reg(PhysReg::T0),
                                       Operand::Reg(PhysReg::FT0),
                                       Operand::Reg(PhysReg::FT1)});
           break;
+        case ir::FCmpPredicate::OGE:
+          block.Append(Opcode::FLe, {Operand::Reg(PhysReg::T0),
+                                      Operand::Reg(PhysReg::FT1),
+                                      Operand::Reg(PhysReg::FT0)});
+          break;
         default:
-          block.Append(Opcode::FEq, {Operand::Reg(PhysReg::FT0),
+          block.Append(Opcode::FEq, {Operand::Reg(PhysReg::T0),
                                       Operand::Reg(PhysReg::FT0),
                                       Operand::Reg(PhysReg::FT1)});
           break;
       }
-      
-      block.Append(Opcode::FMov, {Operand::Reg(PhysReg::T0),
-                                  Operand::Reg(PhysReg::FT0)});
       StoreRegToSlot(PhysReg::T0, dst_slot, block);
       slots.emplace(&inst, dst_slot);
       return;
@@ -481,13 +643,8 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       auto& conv = static_cast<const ir::SIToFPInst&>(inst);
       int dst_slot = function.CreateFrameIndex(4);
       
-      auto src_it = slots.find(conv.GetSrc());
-      if (src_it == slots.end()) {
-        throw std::runtime_error(FormatError("mir", "SIToFP: 找不到源操作数的栈槽"));
-      }
-      
-      block.Append(Opcode::Load,
-                  {Operand::Reg(PhysReg::T0), Operand::FrameIndex(src_it->second)});
+      // 直接加载源操作数到 T0，不依赖 slots 中是否存在
+      EmitValueToReg(conv.GetSrc(), PhysReg::T0, slots, block, function);
       block.Append(Opcode::SIToFP, {Operand::Reg(PhysReg::FT0),
                                     Operand::Reg(PhysReg::T0)});
       StoreRegToSlot(PhysReg::FT0, dst_slot, block, true);
@@ -499,13 +656,8 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       auto& conv = static_cast<const ir::FPToSIInst&>(inst);
       int dst_slot = function.CreateFrameIndex(4);
       
-      auto src_it = slots.find(conv.GetSrc());
-      if (src_it == slots.end()) {
-        throw std::runtime_error(FormatError("mir", "FPToSI: 找不到源操作数的栈槽"));
-      }
-      
-      block.Append(Opcode::LoadFloat,
-                  {Operand::Reg(PhysReg::FT0), Operand::FrameIndex(src_it->second)});
+      // 直接加载源操作数到 FT0，不依赖 slots
+      EmitValueToReg(conv.GetSrc(), PhysReg::FT0, slots, block, function);
       block.Append(Opcode::FPToSI, {Operand::Reg(PhysReg::T0),
                                     Operand::Reg(PhysReg::FT0)});
       StoreRegToSlot(PhysReg::T0, dst_slot, block, false);
@@ -526,7 +678,7 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       auto* true_bb = condbr.GetTrueBB();
       auto* false_bb = condbr.GetFalseBB();
 
-      EmitValueToReg(condbr.GetCond(), PhysReg::T0, slots, block);
+      EmitValueToReg(condbr.GetCond(), PhysReg::T0, slots, block, function);
 
       MachineBasicBlock* true_block = GetOrCreateBlock(true_bb, function);
       MachineBasicBlock* false_block = GetOrCreateBlock(false_bb, function);
@@ -541,9 +693,9 @@ void LowerInstructionToBlock(const ir::Instruction& inst, MachineFunction& funct
       if (ret.GetValue()) {
         auto val = ret.GetValue();
         if (val->GetType()->IsFloat32()) {
-          EmitValueToReg(val, PhysReg::FA0, slots, block);
+          EmitValueToReg(val, PhysReg::FA0, slots, block, function);
         } else {
-          EmitValueToReg(val, PhysReg::A0, slots, block);
+          EmitValueToReg(val, PhysReg::A0, slots, block, function);
         }
       } else {
         block.Append(Opcode::MovImm,
@@ -565,32 +717,41 @@ std::unique_ptr<MachineFunction> LowerFunctionToMIR(const ir::Function& func) {
   
   auto machine_func = std::make_unique<MachineFunction>(func.GetName());
   ValueSlotMap slots;
-
-  // ========== 新增：为函数参数分配栈槽 ==========
+  int ireg = 0, freg = 0, stack_idx = 0;
   for (size_t i = 0; i < func.GetNumArgs(); i++) {
-    ir::Argument* arg = func.GetArgument(i);
-    
-    // 🔑 修改：指针类型分配 8 字节，其他分配 4 字节
-    int size = 4;
-    if (arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat32()) {
-      size = 8;  // 指针在 RV64 上是 8 字节
-    }
-    int slot = machine_func->CreateFrameIndex(size);
-    
-    PhysReg argReg = static_cast<PhysReg>(static_cast<int>(PhysReg::A0) + i);
-    MachineBasicBlock* entry = machine_func->GetEntry();
-    
-    // 存储参数到栈槽
-    if (arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat32()) {
-      // 指针类型：使用 64 位存储（注意：Store 在 MIR 层会根据 slot.size 决定用 sw 还是 sd）
-      entry->Append(Opcode::Store, {Operand::Reg(argReg), Operand::FrameIndex(slot)});
-    } else if (arg->GetType()->IsInt32()) {
-      entry->Append(Opcode::Store, {Operand::Reg(argReg), Operand::FrameIndex(slot)});
-    } else if (arg->GetType()->IsFloat32()) {
-      entry->Append(Opcode::StoreFloat, {Operand::Reg(argReg), Operand::FrameIndex(slot)});
-    }
-    
-    slots[arg] = slot;
+      ir::Argument* arg = func.GetArgument(i);
+      int size = (arg->GetType()->IsPtrInt32() || arg->GetType()->IsPtrFloat32()) ? 8 : 4;
+      int slot = machine_func->CreateFrameIndex(size);
+      MachineBasicBlock* entry = machine_func->GetEntry();
+
+      if (arg->GetType()->IsFloat32()) {
+          if (freg < 8) {
+              PhysReg argReg = static_cast<PhysReg>(static_cast<int>(PhysReg::FA0) + freg);
+              entry->Append(Opcode::StoreFloat, {Operand::Reg(argReg), Operand::FrameIndex(slot)});
+              freg++;
+          } else {
+              entry->Append(Opcode::LoadCallerStackArgFloat, {
+                  Operand::Reg(PhysReg::FT0),
+                  Operand::FrameIndex(slot),
+                  Operand::Imm(stack_idx)
+              });
+              stack_idx++;
+          }
+      } else {
+          if (ireg < 8) {
+              PhysReg argReg = static_cast<PhysReg>(static_cast<int>(PhysReg::A0) + ireg);
+              entry->Append(Opcode::Store, {Operand::Reg(argReg), Operand::FrameIndex(slot)});
+              ireg++;
+          } else {
+              entry->Append(Opcode::LoadCallerStackArg, {
+                  Operand::Reg(PhysReg::T0),
+                  Operand::FrameIndex(slot),
+                  Operand::Imm(stack_idx)
+              });
+              stack_idx++;
+          }
+      }
+      slots[arg] = slot;
   }
 
   // 第一遍：创建所有 IR 基本块对应的 MIR 基本块
diff --git a/src/sem/func.cpp b/src/sem/func.cpp
index 3053065..f9c12c3 100644
--- a/src/sem/func.cpp
+++ b/src/sem/func.cpp
@@ -5,6 +5,58 @@
 #include <string>
 
 #include "utils/Log.h"
+#include <cmath>   // 提供 ldexp
+
+namespace {
+
+// 解析十六进制浮点字面量，支持 0xH.Hp±E 格式
+double ParseHexFloat(const std::string& str) {
+    const char* s = str.c_str();
+    if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) s += 2;
+
+    double significand = 0.0;
+    bool have_dot = false;
+    double dot_scale = 1.0 / 16.0;
+
+    while (*s && *s != 'p' && *s != 'P') {
+        if (*s == '.') {
+            have_dot = true;
+            ++s;
+            continue;
+        }
+        int digit = -1;
+        if (*s >= '0' && *s <= '9') digit = *s - '0';
+        else if (*s >= 'a' && *s <= 'f') digit = *s - 'a' + 10;
+        else if (*s >= 'A' && *s <= 'F') digit = *s - 'A' + 10;
+        if (digit >= 0) {
+            if (have_dot) {
+                significand += digit * dot_scale;
+                dot_scale /= 16.0;
+            } else {
+                significand = significand * 16 + digit;
+            }
+        }
+        ++s;
+    }
+
+    int exponent = 0;
+    if (*s == 'p' || *s == 'P') {
+        ++s;
+        int sign = 1;
+        if (*s == '-') { sign = -1; ++s; }
+        else if (*s == '+') { ++s; }
+        exponent = 0;
+        while (*s >= '0' && *s <= '9') {
+            exponent = exponent * 10 + (*s - '0');
+            ++s;
+        }
+        exponent *= sign;
+    }
+
+    return ldexp(significand, exponent);
+}
+
+} // anonymous namespace
 
 namespace sem {
 
@@ -156,7 +208,12 @@ ConstValue EvaluatePrimaryExp(SysYParser::PrimaryExpContext& ctx) {
       val.float_val = static_cast<double>(val.int_val);
     } else if (float_const) {
       val.is_int = false;
-      val.float_val = ToFloat32(std::stod(float_const->getText()));
+      std::string text = float_const->getText();
+      if (text.size() >= 2 && (text[1] == 'x' || text[1] == 'X')) {
+        val.float_val = ToFloat32(ParseHexFloat(text));
+      } else {
+        val.float_val = ToFloat32(std::stod(text));
+      }
       val.int_val = static_cast<long long>(val.float_val);
     } else {
       throw std::runtime_error(FormatError("sema", "非法数字字面量"));