From 20ab603c469096bedf51410304dcf35f0c526f95 Mon Sep 17 00:00:00 2001
From: cy <766079883@qq.com>
Date: Sat, 16 May 2026 13:47:08 +0800
Subject: [PATCH] =?UTF-8?q?feat(mir):=E5=AE=9E=E7=8E=B0=E5=AF=84=E5=AD=98?=
 =?UTF-8?q?=E5=99=A8=E5=88=86=E9=85=8D=E5=92=8Cspill/reload=E5=8F=8A?=
 =?UTF-8?q?=E9=83=A8=E5=88=86=E4=BC=98=E5=8C=96?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 30.txt                              | 5745 -----------------
 30_many_dimensions.txt              | 5745 -----------------
 39_fp_params.txt                    | 9102 ---------------------------
 include/mir/MIR.h                   |   65 +-
 ir.txt                              |  272 -
 output.s                            |  309 -
 scripts/mir_test.sh:Zone.Identifier |  Bin 25 -> 0 bytes
 src/main.cpp                        |    1 +
 src/mir/AsmPrinter.cpp              |  346 +-
 src/mir/CMakeLists.txt              |    1 +
 src/mir/FrameLowering.cpp           |   67 +-
 src/mir/MIRBasicBlock.cpp           |    7 +
 src/mir/MIRFunction.cpp             |   82 +
 src/mir/MIRInstr.cpp                |   11 +-
 src/mir/Peephole.cpp                |   65 +
 src/mir/RegAlloc.cpp                |  409 +-
 16 files changed, 773 insertions(+), 21454 deletions(-)
 delete mode 100644 30.txt
 delete mode 100644 30_many_dimensions.txt
 delete mode 100644 39_fp_params.txt
 delete mode 100644 ir.txt
 delete mode 100644 output.s
 delete mode 100644 scripts/mir_test.sh:Zone.Identifier
 create mode 100644 src/mir/Peephole.cpp

diff --git a/30.txt b/30.txt
deleted file mode 100644
index a35f3a8..0000000
--- a/30.txt
+++ /dev/null
@@ -1,5745 +0,0 @@
-.text
-.global sum
-.type sum, @function
-sum:
-  addi sp, sp, -1760
-  sd ra, 1744(sp)
-  sd s0, 1752(sp)
-  mv s0, sp
-  sd a0, 0(s0)
-  sd a1, 8(s0)
-  sd a2, 16(s0)
-  sd a3, 24(s0)
-  sd a4, 32(s0)
-  sd a5, 40(s0)
-  sd a6, 48(s0)
-  sd a7, 56(s0)
-  ld t0, 1760(s0)
-  sd t0, 64(s0)
-  ld t0, 1768(s0)
-  sd t0, 72(s0)
-  ld t0, 1776(s0)
-  sd t0, 80(s0)
-  ld t0, 1784(s0)
-  sd t0, 88(s0)
-  ld t0, 1792(s0)
-  sd t0, 96(s0)
-  ld t0, 1800(s0)
-  sd t0, 104(s0)
-  ld t0, 1808(s0)
-  sd t0, 112(s0)
-  ld t0, 1816(s0)
-  sd t0, 120(s0)
-  ld t0, 1824(s0)
-  sd t0, 128(s0)
-  ld t0, 1832(s0)
-  sd t0, 136(s0)
-  ld t0, 1840(s0)
-  sd t0, 144(s0)
-  ld t0, 0(s0)
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 156(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 160(s0)
-  lw t0, 160(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 164(s0)
-  ld t0, 8(s0)
-  lw t1, 164(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 172(s0)
-  lw t0, 156(s0)
-  lw t1, 172(s0)
-  add t0, t0, t1
-  sw t0, 176(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 180(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 184(s0)
-  lw t0, 180(s0)
-  lw t1, 184(s0)
-  add t0, t0, t1
-  sw t0, 188(s0)
-  lw t0, 188(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 192(s0)
-  ld t0, 16(s0)
-  lw t1, 192(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 200(s0)
-  lw t0, 176(s0)
-  lw t1, 200(s0)
-  add t0, t0, t1
-  sw t0, 204(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 208(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 212(s0)
-  lw t0, 208(s0)
-  lw t1, 212(s0)
-  add t0, t0, t1
-  sw t0, 216(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 220(s0)
-  lw t0, 216(s0)
-  lw t1, 220(s0)
-  add t0, t0, t1
-  sw t0, 224(s0)
-  lw t0, 224(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 228(s0)
-  ld t0, 24(s0)
-  lw t1, 228(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 236(s0)
-  lw t0, 204(s0)
-  lw t1, 236(s0)
-  add t0, t0, t1
-  sw t0, 240(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 244(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 248(s0)
-  lw t0, 244(s0)
-  lw t1, 248(s0)
-  add t0, t0, t1
-  sw t0, 252(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 256(s0)
-  lw t0, 252(s0)
-  lw t1, 256(s0)
-  add t0, t0, t1
-  sw t0, 260(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 264(s0)
-  lw t0, 260(s0)
-  lw t1, 264(s0)
-  add t0, t0, t1
-  sw t0, 268(s0)
-  lw t0, 268(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 272(s0)
-  ld t0, 32(s0)
-  lw t1, 272(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 280(s0)
-  lw t0, 240(s0)
-  lw t1, 280(s0)
-  add t0, t0, t1
-  sw t0, 284(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 288(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 292(s0)
-  lw t0, 288(s0)
-  lw t1, 292(s0)
-  add t0, t0, t1
-  sw t0, 296(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 300(s0)
-  lw t0, 296(s0)
-  lw t1, 300(s0)
-  add t0, t0, t1
-  sw t0, 304(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 308(s0)
-  lw t0, 304(s0)
-  lw t1, 308(s0)
-  add t0, t0, t1
-  sw t0, 312(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 316(s0)
-  lw t0, 312(s0)
-  lw t1, 316(s0)
-  add t0, t0, t1
-  sw t0, 320(s0)
-  lw t0, 320(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 324(s0)
-  ld t0, 40(s0)
-  lw t1, 324(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 332(s0)
-  lw t0, 284(s0)
-  lw t1, 332(s0)
-  add t0, t0, t1
-  sw t0, 336(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 340(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 344(s0)
-  lw t0, 340(s0)
-  lw t1, 344(s0)
-  add t0, t0, t1
-  sw t0, 348(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 352(s0)
-  lw t0, 348(s0)
-  lw t1, 352(s0)
-  add t0, t0, t1
-  sw t0, 356(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 360(s0)
-  lw t0, 356(s0)
-  lw t1, 360(s0)
-  add t0, t0, t1
-  sw t0, 364(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 368(s0)
-  lw t0, 364(s0)
-  lw t1, 368(s0)
-  add t0, t0, t1
-  sw t0, 372(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 376(s0)
-  lw t0, 372(s0)
-  lw t1, 376(s0)
-  add t0, t0, t1
-  sw t0, 380(s0)
-  lw t0, 380(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 384(s0)
-  ld t0, 48(s0)
-  lw t1, 384(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 392(s0)
-  lw t0, 336(s0)
-  lw t1, 392(s0)
-  add t0, t0, t1
-  sw t0, 396(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 400(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 404(s0)
-  lw t0, 400(s0)
-  lw t1, 404(s0)
-  add t0, t0, t1
-  sw t0, 408(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 412(s0)
-  lw t0, 408(s0)
-  lw t1, 412(s0)
-  add t0, t0, t1
-  sw t0, 416(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 420(s0)
-  lw t0, 416(s0)
-  lw t1, 420(s0)
-  add t0, t0, t1
-  sw t0, 424(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 428(s0)
-  lw t0, 424(s0)
-  lw t1, 428(s0)
-  add t0, t0, t1
-  sw t0, 432(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 436(s0)
-  lw t0, 432(s0)
-  lw t1, 436(s0)
-  add t0, t0, t1
-  sw t0, 440(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 444(s0)
-  lw t0, 440(s0)
-  lw t1, 444(s0)
-  add t0, t0, t1
-  sw t0, 448(s0)
-  lw t0, 448(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 452(s0)
-  ld t0, 56(s0)
-  lw t1, 452(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 460(s0)
-  lw t0, 396(s0)
-  lw t1, 460(s0)
-  add t0, t0, t1
-  sw t0, 464(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 468(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 472(s0)
-  lw t0, 468(s0)
-  lw t1, 472(s0)
-  add t0, t0, t1
-  sw t0, 476(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 480(s0)
-  lw t0, 476(s0)
-  lw t1, 480(s0)
-  add t0, t0, t1
-  sw t0, 484(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 488(s0)
-  lw t0, 484(s0)
-  lw t1, 488(s0)
-  add t0, t0, t1
-  sw t0, 492(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 496(s0)
-  lw t0, 492(s0)
-  lw t1, 496(s0)
-  add t0, t0, t1
-  sw t0, 500(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 504(s0)
-  lw t0, 500(s0)
-  lw t1, 504(s0)
-  add t0, t0, t1
-  sw t0, 508(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 512(s0)
-  lw t0, 508(s0)
-  lw t1, 512(s0)
-  add t0, t0, t1
-  sw t0, 516(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 520(s0)
-  lw t0, 516(s0)
-  lw t1, 520(s0)
-  add t0, t0, t1
-  sw t0, 524(s0)
-  lw t0, 524(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 528(s0)
-  ld t0, 64(s0)
-  lw t1, 528(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 536(s0)
-  lw t0, 464(s0)
-  lw t1, 536(s0)
-  add t0, t0, t1
-  sw t0, 540(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 544(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 548(s0)
-  lw t0, 544(s0)
-  lw t1, 548(s0)
-  add t0, t0, t1
-  sw t0, 552(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 556(s0)
-  lw t0, 552(s0)
-  lw t1, 556(s0)
-  add t0, t0, t1
-  sw t0, 560(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 564(s0)
-  lw t0, 560(s0)
-  lw t1, 564(s0)
-  add t0, t0, t1
-  sw t0, 568(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 572(s0)
-  lw t0, 568(s0)
-  lw t1, 572(s0)
-  add t0, t0, t1
-  sw t0, 576(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 580(s0)
-  lw t0, 576(s0)
-  lw t1, 580(s0)
-  add t0, t0, t1
-  sw t0, 584(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 588(s0)
-  lw t0, 584(s0)
-  lw t1, 588(s0)
-  add t0, t0, t1
-  sw t0, 592(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 596(s0)
-  lw t0, 592(s0)
-  lw t1, 596(s0)
-  add t0, t0, t1
-  sw t0, 600(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 604(s0)
-  lw t0, 600(s0)
-  lw t1, 604(s0)
-  add t0, t0, t1
-  sw t0, 608(s0)
-  lw t0, 608(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 612(s0)
-  ld t0, 72(s0)
-  lw t1, 612(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 620(s0)
-  lw t0, 540(s0)
-  lw t1, 620(s0)
-  add t0, t0, t1
-  sw t0, 624(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 628(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 632(s0)
-  lw t0, 628(s0)
-  lw t1, 632(s0)
-  add t0, t0, t1
-  sw t0, 636(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 640(s0)
-  lw t0, 636(s0)
-  lw t1, 640(s0)
-  add t0, t0, t1
-  sw t0, 644(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 648(s0)
-  lw t0, 644(s0)
-  lw t1, 648(s0)
-  add t0, t0, t1
-  sw t0, 652(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 656(s0)
-  lw t0, 652(s0)
-  lw t1, 656(s0)
-  add t0, t0, t1
-  sw t0, 660(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 664(s0)
-  lw t0, 660(s0)
-  lw t1, 664(s0)
-  add t0, t0, t1
-  sw t0, 668(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 672(s0)
-  lw t0, 668(s0)
-  lw t1, 672(s0)
-  add t0, t0, t1
-  sw t0, 676(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 680(s0)
-  lw t0, 676(s0)
-  lw t1, 680(s0)
-  add t0, t0, t1
-  sw t0, 684(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 688(s0)
-  lw t0, 684(s0)
-  lw t1, 688(s0)
-  add t0, t0, t1
-  sw t0, 692(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 696(s0)
-  lw t0, 692(s0)
-  lw t1, 696(s0)
-  add t0, t0, t1
-  sw t0, 700(s0)
-  lw t0, 700(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 704(s0)
-  ld t0, 80(s0)
-  lw t1, 704(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 712(s0)
-  lw t0, 624(s0)
-  lw t1, 712(s0)
-  add t0, t0, t1
-  sw t0, 716(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 720(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 724(s0)
-  lw t0, 720(s0)
-  lw t1, 724(s0)
-  add t0, t0, t1
-  sw t0, 728(s0)
-  li t0, 1
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 732(s0)
-  lw t0, 728(s0)
-  lw t1, 732(s0)
-  add t0, t0, t1
-  sw t0, 736(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 740(s0)
-  lw t0, 736(s0)
-  lw t1, 740(s0)
-  add t0, t0, t1
-  sw t0, 744(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 748(s0)
-  lw t0, 744(s0)
-  lw t1, 748(s0)
-  add t0, t0, t1
-  sw t0, 752(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 756(s0)
-  lw t0, 752(s0)
-  lw t1, 756(s0)
-  add t0, t0, t1
-  sw t0, 760(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 764(s0)
-  lw t0, 760(s0)
-  lw t1, 764(s0)
-  add t0, t0, t1
-  sw t0, 768(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 772(s0)
-  lw t0, 768(s0)
-  lw t1, 772(s0)
-  add t0, t0, t1
-  sw t0, 776(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 780(s0)
-  lw t0, 776(s0)
-  lw t1, 780(s0)
-  add t0, t0, t1
-  sw t0, 784(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 788(s0)
-  lw t0, 784(s0)
-  lw t1, 788(s0)
-  add t0, t0, t1
-  sw t0, 792(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 796(s0)
-  lw t0, 792(s0)
-  lw t1, 796(s0)
-  add t0, t0, t1
-  sw t0, 800(s0)
-  lw t0, 800(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 804(s0)
-  ld t0, 88(s0)
-  lw t1, 804(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 812(s0)
-  lw t0, 716(s0)
-  lw t1, 812(s0)
-  add t0, t0, t1
-  sw t0, 816(s0)
-  li t0, 1
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 820(s0)
-  li t0, 1
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 824(s0)
-  lw t0, 820(s0)
-  lw t1, 824(s0)
-  add t0, t0, t1
-  sw t0, 828(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 832(s0)
-  lw t0, 828(s0)
-  lw t1, 832(s0)
-  add t0, t0, t1
-  sw t0, 836(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 840(s0)
-  lw t0, 836(s0)
-  lw t1, 840(s0)
-  add t0, t0, t1
-  sw t0, 844(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 848(s0)
-  lw t0, 844(s0)
-  lw t1, 848(s0)
-  add t0, t0, t1
-  sw t0, 852(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 856(s0)
-  lw t0, 852(s0)
-  lw t1, 856(s0)
-  add t0, t0, t1
-  sw t0, 860(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 864(s0)
-  lw t0, 860(s0)
-  lw t1, 864(s0)
-  add t0, t0, t1
-  sw t0, 868(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 872(s0)
-  lw t0, 868(s0)
-  lw t1, 872(s0)
-  add t0, t0, t1
-  sw t0, 876(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 880(s0)
-  lw t0, 876(s0)
-  lw t1, 880(s0)
-  add t0, t0, t1
-  sw t0, 884(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 888(s0)
-  lw t0, 884(s0)
-  lw t1, 888(s0)
-  add t0, t0, t1
-  sw t0, 892(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 896(s0)
-  lw t0, 892(s0)
-  lw t1, 896(s0)
-  add t0, t0, t1
-  sw t0, 900(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 904(s0)
-  lw t0, 900(s0)
-  lw t1, 904(s0)
-  add t0, t0, t1
-  sw t0, 908(s0)
-  lw t0, 908(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 912(s0)
-  ld t0, 96(s0)
-  lw t1, 912(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 920(s0)
-  lw t0, 816(s0)
-  lw t1, 920(s0)
-  add t0, t0, t1
-  sw t0, 924(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 928(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 932(s0)
-  lw t0, 928(s0)
-  lw t1, 932(s0)
-  add t0, t0, t1
-  sw t0, 936(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 940(s0)
-  lw t0, 936(s0)
-  lw t1, 940(s0)
-  add t0, t0, t1
-  sw t0, 944(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 948(s0)
-  lw t0, 944(s0)
-  lw t1, 948(s0)
-  add t0, t0, t1
-  sw t0, 952(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 956(s0)
-  lw t0, 952(s0)
-  lw t1, 956(s0)
-  add t0, t0, t1
-  sw t0, 960(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 964(s0)
-  lw t0, 960(s0)
-  lw t1, 964(s0)
-  add t0, t0, t1
-  sw t0, 968(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 972(s0)
-  lw t0, 968(s0)
-  lw t1, 972(s0)
-  add t0, t0, t1
-  sw t0, 976(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 980(s0)
-  lw t0, 976(s0)
-  lw t1, 980(s0)
-  add t0, t0, t1
-  sw t0, 984(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 988(s0)
-  lw t0, 984(s0)
-  lw t1, 988(s0)
-  add t0, t0, t1
-  sw t0, 992(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 996(s0)
-  lw t0, 992(s0)
-  lw t1, 996(s0)
-  add t0, t0, t1
-  sw t0, 1000(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1004(s0)
-  lw t0, 1000(s0)
-  lw t1, 1004(s0)
-  add t0, t0, t1
-  sw t0, 1008(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1012(s0)
-  lw t0, 1008(s0)
-  lw t1, 1012(s0)
-  add t0, t0, t1
-  sw t0, 1016(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1020(s0)
-  lw t0, 1016(s0)
-  lw t1, 1020(s0)
-  add t0, t0, t1
-  sw t0, 1024(s0)
-  lw t0, 1024(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1028(s0)
-  ld t0, 104(s0)
-  lw t1, 1028(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1036(s0)
-  lw t0, 924(s0)
-  lw t1, 1036(s0)
-  add t0, t0, t1
-  sw t0, 1040(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1044(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1048(s0)
-  lw t0, 1044(s0)
-  lw t1, 1048(s0)
-  add t0, t0, t1
-  sw t0, 1052(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1056(s0)
-  lw t0, 1052(s0)
-  lw t1, 1056(s0)
-  add t0, t0, t1
-  sw t0, 1060(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1064(s0)
-  lw t0, 1060(s0)
-  lw t1, 1064(s0)
-  add t0, t0, t1
-  sw t0, 1068(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1072(s0)
-  lw t0, 1068(s0)
-  lw t1, 1072(s0)
-  add t0, t0, t1
-  sw t0, 1076(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1080(s0)
-  lw t0, 1076(s0)
-  lw t1, 1080(s0)
-  add t0, t0, t1
-  sw t0, 1084(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1088(s0)
-  lw t0, 1084(s0)
-  lw t1, 1088(s0)
-  add t0, t0, t1
-  sw t0, 1092(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1096(s0)
-  lw t0, 1092(s0)
-  lw t1, 1096(s0)
-  add t0, t0, t1
-  sw t0, 1100(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1104(s0)
-  lw t0, 1100(s0)
-  lw t1, 1104(s0)
-  add t0, t0, t1
-  sw t0, 1108(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1112(s0)
-  lw t0, 1108(s0)
-  lw t1, 1112(s0)
-  add t0, t0, t1
-  sw t0, 1116(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1120(s0)
-  lw t0, 1116(s0)
-  lw t1, 1120(s0)
-  add t0, t0, t1
-  sw t0, 1124(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1128(s0)
-  lw t0, 1124(s0)
-  lw t1, 1128(s0)
-  add t0, t0, t1
-  sw t0, 1132(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1136(s0)
-  lw t0, 1132(s0)
-  lw t1, 1136(s0)
-  add t0, t0, t1
-  sw t0, 1140(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1144(s0)
-  lw t0, 1140(s0)
-  lw t1, 1144(s0)
-  add t0, t0, t1
-  sw t0, 1148(s0)
-  lw t0, 1148(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1152(s0)
-  ld t0, 112(s0)
-  lw t1, 1152(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1160(s0)
-  lw t0, 1040(s0)
-  lw t1, 1160(s0)
-  add t0, t0, t1
-  sw t0, 1164(s0)
-  li t0, 1
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1168(s0)
-  li t0, 1
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1172(s0)
-  lw t0, 1168(s0)
-  lw t1, 1172(s0)
-  add t0, t0, t1
-  sw t0, 1176(s0)
-  li t0, 1
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1180(s0)
-  lw t0, 1176(s0)
-  lw t1, 1180(s0)
-  add t0, t0, t1
-  sw t0, 1184(s0)
-  li t0, 1
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1188(s0)
-  lw t0, 1184(s0)
-  lw t1, 1188(s0)
-  add t0, t0, t1
-  sw t0, 1192(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1196(s0)
-  lw t0, 1192(s0)
-  lw t1, 1196(s0)
-  add t0, t0, t1
-  sw t0, 1200(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1204(s0)
-  lw t0, 1200(s0)
-  lw t1, 1204(s0)
-  add t0, t0, t1
-  sw t0, 1208(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1212(s0)
-  lw t0, 1208(s0)
-  lw t1, 1212(s0)
-  add t0, t0, t1
-  sw t0, 1216(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1220(s0)
-  lw t0, 1216(s0)
-  lw t1, 1220(s0)
-  add t0, t0, t1
-  sw t0, 1224(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1228(s0)
-  lw t0, 1224(s0)
-  lw t1, 1228(s0)
-  add t0, t0, t1
-  sw t0, 1232(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1236(s0)
-  lw t0, 1232(s0)
-  lw t1, 1236(s0)
-  add t0, t0, t1
-  sw t0, 1240(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1244(s0)
-  lw t0, 1240(s0)
-  lw t1, 1244(s0)
-  add t0, t0, t1
-  sw t0, 1248(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1252(s0)
-  lw t0, 1248(s0)
-  lw t1, 1252(s0)
-  add t0, t0, t1
-  sw t0, 1256(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1260(s0)
-  lw t0, 1256(s0)
-  lw t1, 1260(s0)
-  add t0, t0, t1
-  sw t0, 1264(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1268(s0)
-  lw t0, 1264(s0)
-  lw t1, 1268(s0)
-  add t0, t0, t1
-  sw t0, 1272(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1276(s0)
-  lw t0, 1272(s0)
-  lw t1, 1276(s0)
-  add t0, t0, t1
-  sw t0, 1280(s0)
-  lw t0, 1280(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 1284(s0)
-  ld t0, 120(s0)
-  lw t1, 1284(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1292(s0)
-  lw t0, 1164(s0)
-  lw t1, 1292(s0)
-  add t0, t0, t1
-  sw t0, 1296(s0)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  sw t0, 1300(s0)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1304(s0)
-  lw t0, 1300(s0)
-  lw t1, 1304(s0)
-  add t0, t0, t1
-  sw t0, 1308(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1312(s0)
-  lw t0, 1308(s0)
-  lw t1, 1312(s0)
-  add t0, t0, t1
-  sw t0, 1316(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1320(s0)
-  lw t0, 1316(s0)
-  lw t1, 1320(s0)
-  add t0, t0, t1
-  sw t0, 1324(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1328(s0)
-  lw t0, 1324(s0)
-  lw t1, 1328(s0)
-  add t0, t0, t1
-  sw t0, 1332(s0)
-  li t0, 1
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1336(s0)
-  lw t0, 1332(s0)
-  lw t1, 1336(s0)
-  add t0, t0, t1
-  sw t0, 1340(s0)
-  li t0, 1
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1344(s0)
-  lw t0, 1340(s0)
-  lw t1, 1344(s0)
-  add t0, t0, t1
-  sw t0, 1348(s0)
-  li t0, 1
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1352(s0)
-  lw t0, 1348(s0)
-  lw t1, 1352(s0)
-  add t0, t0, t1
-  sw t0, 1356(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1360(s0)
-  lw t0, 1356(s0)
-  lw t1, 1360(s0)
-  add t0, t0, t1
-  sw t0, 1364(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1368(s0)
-  lw t0, 1364(s0)
-  lw t1, 1368(s0)
-  add t0, t0, t1
-  sw t0, 1372(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1376(s0)
-  lw t0, 1372(s0)
-  lw t1, 1376(s0)
-  add t0, t0, t1
-  sw t0, 1380(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1384(s0)
-  lw t0, 1380(s0)
-  lw t1, 1384(s0)
-  add t0, t0, t1
-  sw t0, 1388(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1392(s0)
-  lw t0, 1388(s0)
-  lw t1, 1392(s0)
-  add t0, t0, t1
-  sw t0, 1396(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1400(s0)
-  lw t0, 1396(s0)
-  lw t1, 1400(s0)
-  add t0, t0, t1
-  sw t0, 1404(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1408(s0)
-  lw t0, 1404(s0)
-  lw t1, 1408(s0)
-  add t0, t0, t1
-  sw t0, 1412(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1416(s0)
-  lw t0, 1412(s0)
-  lw t1, 1416(s0)
-  add t0, t0, t1
-  sw t0, 1420(s0)
-  lw t0, 1420(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1424(s0)
-  ld t0, 128(s0)
-  lw t1, 1424(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1432(s0)
-  lw t0, 1296(s0)
-  lw t1, 1432(s0)
-  add t0, t0, t1
-  sw t0, 1436(s0)
-  li t0, 1
-  li t1, 131072
-  mul t0, t0, t1
-  sw t0, 1440(s0)
-  li t0, 1
-  li t1, 65536
-  mul t0, t0, t1
-  sw t0, 1444(s0)
-  lw t0, 1440(s0)
-  lw t1, 1444(s0)
-  add t0, t0, t1
-  sw t0, 1448(s0)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1452(s0)
-  lw t0, 1448(s0)
-  lw t1, 1452(s0)
-  add t0, t0, t1
-  sw t0, 1456(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1460(s0)
-  lw t0, 1456(s0)
-  lw t1, 1460(s0)
-  add t0, t0, t1
-  sw t0, 1464(s0)
-  li t0, 1
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1468(s0)
-  lw t0, 1464(s0)
-  lw t1, 1468(s0)
-  add t0, t0, t1
-  sw t0, 1472(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1476(s0)
-  lw t0, 1472(s0)
-  lw t1, 1476(s0)
-  add t0, t0, t1
-  sw t0, 1480(s0)
-  li t0, 1
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1484(s0)
-  lw t0, 1480(s0)
-  lw t1, 1484(s0)
-  add t0, t0, t1
-  sw t0, 1488(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1492(s0)
-  lw t0, 1488(s0)
-  lw t1, 1492(s0)
-  add t0, t0, t1
-  sw t0, 1496(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1500(s0)
-  lw t0, 1496(s0)
-  lw t1, 1500(s0)
-  add t0, t0, t1
-  sw t0, 1504(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1508(s0)
-  lw t0, 1504(s0)
-  lw t1, 1508(s0)
-  add t0, t0, t1
-  sw t0, 1512(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1516(s0)
-  lw t0, 1512(s0)
-  lw t1, 1516(s0)
-  add t0, t0, t1
-  sw t0, 1520(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1524(s0)
-  lw t0, 1520(s0)
-  lw t1, 1524(s0)
-  add t0, t0, t1
-  sw t0, 1528(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1532(s0)
-  lw t0, 1528(s0)
-  lw t1, 1532(s0)
-  add t0, t0, t1
-  sw t0, 1536(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1540(s0)
-  lw t0, 1536(s0)
-  lw t1, 1540(s0)
-  add t0, t0, t1
-  sw t0, 1544(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1548(s0)
-  lw t0, 1544(s0)
-  lw t1, 1548(s0)
-  add t0, t0, t1
-  sw t0, 1552(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1556(s0)
-  lw t0, 1552(s0)
-  lw t1, 1556(s0)
-  add t0, t0, t1
-  sw t0, 1560(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1564(s0)
-  lw t0, 1560(s0)
-  lw t1, 1564(s0)
-  add t0, t0, t1
-  sw t0, 1568(s0)
-  lw t0, 1568(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1572(s0)
-  ld t0, 136(s0)
-  lw t1, 1572(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1580(s0)
-  lw t0, 1436(s0)
-  lw t1, 1580(s0)
-  add t0, t0, t1
-  sw t0, 1584(s0)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  sw t0, 1588(s0)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  sw t0, 1592(s0)
-  lw t0, 1588(s0)
-  lw t1, 1592(s0)
-  add t0, t0, t1
-  sw t0, 1596(s0)
-  li t0, 1
-  li t1, 65536
-  mul t0, t0, t1
-  sw t0, 1600(s0)
-  lw t0, 1596(s0)
-  lw t1, 1600(s0)
-  add t0, t0, t1
-  sw t0, 1604(s0)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1608(s0)
-  lw t0, 1604(s0)
-  lw t1, 1608(s0)
-  add t0, t0, t1
-  sw t0, 1612(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1616(s0)
-  lw t0, 1612(s0)
-  lw t1, 1616(s0)
-  add t0, t0, t1
-  sw t0, 1620(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1624(s0)
-  lw t0, 1620(s0)
-  lw t1, 1624(s0)
-  add t0, t0, t1
-  sw t0, 1628(s0)
-  li t0, 1
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1632(s0)
-  lw t0, 1628(s0)
-  lw t1, 1632(s0)
-  add t0, t0, t1
-  sw t0, 1636(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1640(s0)
-  lw t0, 1636(s0)
-  lw t1, 1640(s0)
-  add t0, t0, t1
-  sw t0, 1644(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1648(s0)
-  lw t0, 1644(s0)
-  lw t1, 1648(s0)
-  add t0, t0, t1
-  sw t0, 1652(s0)
-  li t0, 1
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1656(s0)
-  lw t0, 1652(s0)
-  lw t1, 1656(s0)
-  add t0, t0, t1
-  sw t0, 1660(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1664(s0)
-  lw t0, 1660(s0)
-  lw t1, 1664(s0)
-  add t0, t0, t1
-  sw t0, 1668(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1672(s0)
-  lw t0, 1668(s0)
-  lw t1, 1672(s0)
-  add t0, t0, t1
-  sw t0, 1676(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1680(s0)
-  lw t0, 1676(s0)
-  lw t1, 1680(s0)
-  add t0, t0, t1
-  sw t0, 1684(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1688(s0)
-  lw t0, 1684(s0)
-  lw t1, 1688(s0)
-  add t0, t0, t1
-  sw t0, 1692(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1696(s0)
-  lw t0, 1692(s0)
-  lw t1, 1696(s0)
-  add t0, t0, t1
-  sw t0, 1700(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1704(s0)
-  lw t0, 1700(s0)
-  lw t1, 1704(s0)
-  add t0, t0, t1
-  sw t0, 1708(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1712(s0)
-  lw t0, 1708(s0)
-  lw t1, 1712(s0)
-  add t0, t0, t1
-  sw t0, 1716(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1720(s0)
-  lw t0, 1716(s0)
-  lw t1, 1720(s0)
-  add t0, t0, t1
-  sw t0, 1724(s0)
-  lw t0, 1724(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 1728(s0)
-  ld t0, 144(s0)
-  lw t1, 1728(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1736(s0)
-  lw t0, 1584(s0)
-  lw t1, 1736(s0)
-  add t0, t0, t1
-  sw t0, 1740(s0)
-  lw a0, 1740(s0)
-  ld ra, 1744(s0)
-  addi sp, s0, 1760
-  ld s0, 1752(s0)
-  ret
-.size sum, .-sum
-
-.global main
-.type main, @function
-main:
-  li t4, -2099184
-  add sp, sp, t4
-  li t4, 2099168
-  add t4, sp, t4
-  sd ra, 0(t4)
-  li t4, 2099176
-  add t4, sp, t4
-  sd s0, 0(t4)
-  mv s0, sp
-  addi a0, s0, 0
-  li a1, 0
-  li a2, 2097152
-  call memset
-  li t0, 0
-  li t4, 2097152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t4, 2097156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L0.while.cond
-L0.while.cond:
-  li t4, 2097156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097160
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097160
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097164
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097164
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L1.while.body
-  j L2.while.end
-L1.while.body:
-  li t0, 0
-  li t4, 2097168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L3.while.cond
-L3.while.cond:
-  li t4, 2097168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097172
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097176
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097176
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L4.while.body
-  j L5.while.end
-L4.while.body:
-  li t0, 0
-  li t4, 2097180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L6.while.cond
-L6.while.cond:
-  li t4, 2097180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097184
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097184
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097188
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L7.while.body
-  j L8.while.end
-L7.while.body:
-  li t0, 0
-  li t4, 2097192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L9.while.cond
-L9.while.cond:
-  li t4, 2097192
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097196
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097196
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097200
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097200
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L10.while.body
-  j L11.while.end
-L10.while.body:
-  li t0, 0
-  li t4, 2097204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L12.while.cond
-L12.while.cond:
-  li t4, 2097204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097208
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097208
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097212
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097212
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L13.while.body
-  j L14.while.end
-L13.while.body:
-  li t0, 0
-  li t4, 2097216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L15.while.cond
-L15.while.cond:
-  li t4, 2097216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097220
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097220
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097224
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097224
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L16.while.body
-  j L17.while.end
-L16.while.body:
-  li t0, 0
-  li t4, 2097228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L18.while.cond
-L18.while.cond:
-  li t4, 2097228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097232
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097232
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097236
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097236
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L19.while.body
-  j L20.while.end
-L19.while.body:
-  li t0, 0
-  li t4, 2097240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L21.while.cond
-L21.while.cond:
-  li t4, 2097240
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097244
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097244
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097248
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097248
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L22.while.body
-  j L23.while.end
-L22.while.body:
-  li t0, 0
-  li t4, 2097252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L24.while.cond
-L24.while.cond:
-  li t4, 2097252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097256
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097256
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097260
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097260
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L25.while.body
-  j L26.while.end
-L25.while.body:
-  li t0, 0
-  li t4, 2097264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L27.while.cond
-L27.while.cond:
-  li t4, 2097264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097268
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097268
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097272
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097272
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L28.while.body
-  j L29.while.end
-L28.while.body:
-  li t0, 0
-  li t4, 2097276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L30.while.cond
-L30.while.cond:
-  li t4, 2097276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097280
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097280
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097284
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097284
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L31.while.body
-  j L32.while.end
-L31.while.body:
-  li t0, 0
-  li t4, 2097288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L33.while.cond
-L33.while.cond:
-  li t4, 2097288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097292
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097296
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097296
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L34.while.body
-  j L35.while.end
-L34.while.body:
-  li t0, 0
-  li t4, 2097300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L36.while.cond
-L36.while.cond:
-  li t4, 2097300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097304
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097304
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097308
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097308
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L37.while.body
-  j L38.while.end
-L37.while.body:
-  li t0, 0
-  li t4, 2097312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L39.while.cond
-L39.while.cond:
-  li t4, 2097312
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097316
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097320
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097320
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L40.while.body
-  j L41.while.end
-L40.while.body:
-  li t0, 0
-  li t4, 2097324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L42.while.cond
-L42.while.cond:
-  li t4, 2097324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097328
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097328
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097332
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097332
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L43.while.body
-  j L44.while.end
-L43.while.body:
-  li t0, 0
-  li t4, 2097336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L45.while.cond
-L45.while.cond:
-  li t4, 2097336
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097340
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097340
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097344
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097344
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L46.while.body
-  j L47.while.end
-L46.while.body:
-  li t0, 0
-  li t4, 2097348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L48.while.cond
-L48.while.cond:
-  li t4, 2097348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097352
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097352
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097356
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097356
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L49.while.body
-  j L50.while.end
-L49.while.body:
-  li t0, 0
-  li t4, 2097360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L51.while.cond
-L51.while.cond:
-  li t4, 2097360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097364
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097364
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097368
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097368
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L52.while.body
-  j L53.while.end
-L52.while.body:
-  li t0, 0
-  li t4, 2097372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L54.while.cond
-L54.while.cond:
-  li t4, 2097372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097376
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097376
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097380
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097380
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L55.while.body
-  j L56.while.end
-L55.while.body:
-  li t4, 2097152
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097384
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097388
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097392
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097392
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  mul t0, t0, t1
-  li t4, 2097396
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097388
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097396
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097400
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097404
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097404
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 4
-  mul t0, t0, t1
-  li t4, 2097408
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097400
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097408
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097412
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097336
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097416
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097416
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2097420
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097412
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097420
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097424
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097428
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097428
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2097432
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097424
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097432
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097436
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097312
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097440
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097440
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2097444
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097436
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097444
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097448
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097452
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097452
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2097456
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097448
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097456
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097460
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097464
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097464
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2097468
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097460
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097468
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097472
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097476
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097476
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2097480
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097472
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097480
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097484
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097488
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097488
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2097492
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097484
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097492
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097496
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097500
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097500
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2097504
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097496
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097504
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097508
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097240
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097512
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097512
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2097516
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097508
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097516
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097520
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097524
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097524
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2097528
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097520
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097528
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097532
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097536
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097536
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2097540
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097532
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097540
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097544
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097548
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097548
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2097552
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097544
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097552
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097556
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097192
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097560
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097560
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2097564
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097556
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097564
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097568
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097572
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097572
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2097576
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097568
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097576
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097580
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097584
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097584
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2097588
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097580
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097588
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097592
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097596
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097596
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2097600
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097592
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097600
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097604
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097384
-  add t4, s0, t4
-  lw t2, 0(t4)
-  addi t0, s0, 0
-  li t4, 2097604
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t4, 2097152
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097612
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097612
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097616
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097616
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097620
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097620
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097624
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097624
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L54.while.cond
-L56.while.end:
-  li t4, 2097360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097628
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097628
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097632
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097632
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L51.while.cond
-L53.while.end:
-  li t4, 2097348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097636
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097636
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097640
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097640
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L48.while.cond
-L50.while.end:
-  li t4, 2097336
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097644
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097644
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097648
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097648
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L45.while.cond
-L47.while.end:
-  li t4, 2097324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097652
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097652
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097656
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097656
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L42.while.cond
-L44.while.end:
-  li t4, 2097312
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097660
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097660
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097664
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097664
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L39.while.cond
-L41.while.end:
-  li t4, 2097300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097668
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097668
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097672
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097672
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L36.while.cond
-L38.while.end:
-  li t4, 2097288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097676
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097676
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097680
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097680
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L33.while.cond
-L35.while.end:
-  li t4, 2097276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097684
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097684
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097688
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097688
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L30.while.cond
-L32.while.end:
-  li t4, 2097264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097692
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097692
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097696
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097696
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L27.while.cond
-L29.while.end:
-  li t4, 2097252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097700
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097700
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097704
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097704
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L24.while.cond
-L26.while.end:
-  li t4, 2097240
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097708
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097708
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097712
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097712
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L21.while.cond
-L23.while.end:
-  li t4, 2097228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097716
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097716
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097720
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097720
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L18.while.cond
-L20.while.end:
-  li t4, 2097216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097724
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097724
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097728
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097728
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L15.while.cond
-L17.while.end:
-  li t4, 2097204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097732
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097732
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097736
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097736
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L12.while.cond
-L14.while.end:
-  li t4, 2097192
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097740
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097740
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097744
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097744
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L9.while.cond
-L11.while.end:
-  li t4, 2097180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097748
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097748
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097752
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097752
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L6.while.cond
-L8.while.end:
-  li t4, 2097168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097756
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097756
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097760
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097760
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L3.while.cond
-L5.while.end:
-  li t4, 2097156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097764
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097764
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097768
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097768
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L0.while.cond
-L2.while.end:
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  li t4, 2097772
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  li t4, 2097776
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097772
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097776
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097780
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2097784
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097780
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097784
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097788
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2097792
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097788
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097792
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097796
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2097800
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097796
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097800
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097804
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2097808
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097804
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097808
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097812
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2097816
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097812
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097816
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097820
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2097824
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097820
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097824
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097828
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2097832
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097828
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097832
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097836
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2097840
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097836
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097840
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097844
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2097848
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097844
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097848
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097852
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2097856
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097852
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097856
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097860
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2097864
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097860
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097864
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097868
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2097872
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097868
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097872
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097876
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2097880
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097876
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097880
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097884
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2097888
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097884
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097888
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097892
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2097896
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097892
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097896
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097900
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2097904
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097900
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097904
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097908
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  li t4, 2097916
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2097920
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097916
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097920
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097924
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2097928
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097924
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097928
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097932
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2097936
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097932
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097936
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097940
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2097944
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097940
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097944
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097948
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2097952
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097948
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097952
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097956
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2097960
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097956
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097960
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097964
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2097968
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097964
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097968
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097972
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2097976
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097972
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097976
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097980
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2097984
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097980
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097984
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097988
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2097992
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097988
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097992
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097996
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098000
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097996
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098000
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098004
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098008
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098004
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098008
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098012
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098016
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098012
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098016
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098020
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098024
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098020
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098024
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098028
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098032
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098028
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098032
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098036
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098040
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098036
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098040
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098044
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2098052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2098056
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098052
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098056
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098060
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098064
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098060
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098064
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098072
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098068
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098072
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098080
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098076
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098080
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098084
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098088
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098084
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098088
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098092
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098096
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098092
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098096
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098100
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098104
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098100
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098104
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098108
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098112
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098108
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098112
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098120
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098116
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098120
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098124
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098128
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098124
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098128
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098132
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098136
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098132
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098136
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098140
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098144
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098140
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098144
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098148
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098152
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098160
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098160
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098164
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098164
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098168
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2098180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098184
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098184
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098188
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098192
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098196
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098200
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098196
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098200
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098208
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098208
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098212
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098212
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098216
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098220
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098224
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098220
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098224
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098232
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098232
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098236
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098236
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098240
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098244
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098248
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098244
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098248
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098256
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098256
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098260
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098260
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098264
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098268
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098272
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098268
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098272
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098280
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098280
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098284
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098284
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098288
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098304
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098304
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098308
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098308
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098312
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098320
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098316
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098320
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098328
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098328
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098332
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098332
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098336
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098340
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098344
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098340
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098344
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098352
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098352
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098356
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098356
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098360
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098364
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098368
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098364
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098368
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098376
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098376
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098380
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098384
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098380
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098384
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098388
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098392
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098388
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098392
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098396
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098400
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098396
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098400
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098404
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098412
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098416
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098412
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098416
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098420
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098424
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098420
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098424
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098428
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098432
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098428
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098432
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098436
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098440
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098436
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098440
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098444
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098448
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098444
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098448
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098452
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098456
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098452
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098456
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098460
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098464
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098460
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098464
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098468
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098472
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098468
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098472
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098476
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098480
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098476
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098480
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098484
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098488
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098484
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098488
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098492
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098496
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098492
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098496
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098500
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098504
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098500
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098504
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098508
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098516
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098520
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098516
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098520
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098524
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098528
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098524
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098528
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098532
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098536
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098532
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098536
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098540
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098544
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098540
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098544
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098548
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098552
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098548
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098552
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098556
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098560
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098556
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098560
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098564
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098568
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098564
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098568
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098572
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098576
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098572
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098576
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098580
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098584
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098580
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098584
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098588
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098592
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098588
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098592
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098596
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098600
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098596
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098600
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098604
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098612
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098616
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098612
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098616
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098620
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098624
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098620
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098624
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098628
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098632
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098628
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098632
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098636
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098640
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098636
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098640
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098644
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098648
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098644
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098648
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098652
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098656
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098652
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098656
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098660
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098664
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098660
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098664
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098668
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098672
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098668
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098672
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098676
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098680
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098676
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098680
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098684
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098688
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098684
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098688
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098692
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098700
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098704
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098700
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098704
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098708
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098712
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098708
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098712
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098716
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098720
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098716
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098720
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098724
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098728
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098724
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098728
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098732
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098736
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098732
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098736
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098740
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098744
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098740
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098744
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098748
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098752
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098748
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098752
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098756
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098760
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098756
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098760
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098764
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098768
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098764
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098768
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098772
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098780
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098784
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098780
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098784
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098788
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098792
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098788
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098792
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098796
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098800
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098796
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098800
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098804
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098808
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098804
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098808
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098812
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098816
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098812
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098816
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098820
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098824
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098820
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098824
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098828
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098832
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098828
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098832
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098836
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098840
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098836
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098840
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098844
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098852
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098856
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098852
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098856
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098860
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098864
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098860
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098864
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098868
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098872
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098868
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098872
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098876
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098880
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098876
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098880
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098884
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098888
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098884
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098888
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098892
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098896
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098892
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098896
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098900
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098904
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098900
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098904
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098908
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098916
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098920
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098916
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098920
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098924
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098928
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098924
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098928
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098932
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098936
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098932
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098936
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098940
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098944
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098940
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098944
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098948
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098952
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098948
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098952
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098956
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098960
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098956
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098960
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098964
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098972
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098976
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098972
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098976
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098980
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098984
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098980
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098984
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098988
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098992
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098988
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098992
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098996
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099000
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098996
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099000
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099004
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099008
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099004
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099008
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099012
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2099020
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2099024
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099020
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099024
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099028
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2099032
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099028
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099032
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099036
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099040
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099036
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099040
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099044
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099048
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099044
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099048
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2099060
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2099064
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099060
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099064
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099072
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099068
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099072
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099080
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099076
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099080
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099084
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2099092
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099096
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099092
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099096
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099100
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099104
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099100
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099104
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099108
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099120
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099116
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099120
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099124
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099132
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi sp, sp, -88
-  addi a0, s0, 0
-  li t4, 2097908
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a0, a0, t1
-  addi a1, s0, 0
-  li t4, 2098044
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a1, a1, t1
-  addi a2, s0, 0
-  li t4, 2098172
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a2, a2, t1
-  addi a3, s0, 0
-  li t4, 2098292
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a3, a3, t1
-  addi a4, s0, 0
-  li t4, 2098404
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a4, a4, t1
-  addi a5, s0, 0
-  li t4, 2098508
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a5, a5, t1
-  addi a6, s0, 0
-  li t4, 2098604
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a6, a6, t1
-  addi a7, s0, 0
-  li t4, 2098692
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a7, a7, t1
-  add t4, sp, zero
-  addi t0, s0, 0
-  li t4, 2098772
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 8
-  addi t0, s0, 0
-  li t4, 2098844
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 16
-  addi t0, s0, 0
-  li t4, 2098908
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  addi t0, s0, 0
-  li t4, 2098964
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 32
-  addi t0, s0, 0
-  li t4, 2099012
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 40
-  addi t0, s0, 0
-  li t4, 2099052
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  addi t0, s0, 0
-  li t4, 2099084
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 56
-  addi t0, s0, 0
-  li t4, 2099108
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  addi t0, s0, 0
-  li t4, 2099124
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 72
-  addi t0, s0, 0
-  li t4, 2099132
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 80
-  addi t0, s0, 0
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  call sum
-  addi sp, sp, 88
-  li t4, 2099144
-  add t4, s0, t4
-  sw a0, 0(t4)
-  li t4, 2099144
-  add t4, s0, t4
-  lw a0, 0(t4)
-  call putint
-  li t0, 0
-  li t1, 256
-  rem t0, t0, t1
-  li t4, 2099148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099148
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  add t0, t0, t1
-  li t4, 2099152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099152
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  rem t0, t0, t1
-  li t4, 2099156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099156
-  add t4, s0, t4
-  lw a0, 0(t4)
-  call putint
-  li a0, 10
-  call putch
-  li a0, 0
-  li t3, 2099168
-  add t3, s0, t3
-  ld ra, 0(t3)
-  li t3, 2099184
-  add sp, s0, t3
-  li t3, 2099176
-  add t3, s0, t3
-  ld s0, 0(t3)
-  ret
-.size main, .-main
-
diff --git a/30_many_dimensions.txt b/30_many_dimensions.txt
deleted file mode 100644
index 30454e0..0000000
--- a/30_many_dimensions.txt
+++ /dev/null
@@ -1,5745 +0,0 @@
-.text
-.global sum
-.type sum, @function
-sum:
-  addi sp, sp, -1760
-  sd ra, 1744(sp)
-  sd s0, 1752(sp)
-  mv s0, sp
-  sd a0, 0(s0)
-  sd a1, 8(s0)
-  sd a2, 16(s0)
-  sd a3, 24(s0)
-  sd a4, 32(s0)
-  sd a5, 40(s0)
-  sd a6, 48(s0)
-  sd a7, 56(s0)
-  ld t0, 1760(s0)
-  sd t0, 64(s0)
-  ld t0, 1768(s0)
-  sd t0, 72(s0)
-  ld t0, 1776(s0)
-  sd t0, 80(s0)
-  ld t0, 1784(s0)
-  sd t0, 88(s0)
-  ld t0, 1792(s0)
-  sd t0, 96(s0)
-  ld t0, 1800(s0)
-  sd t0, 104(s0)
-  ld t0, 1808(s0)
-  sd t0, 112(s0)
-  ld t0, 1816(s0)
-  sd t0, 120(s0)
-  ld t0, 1824(s0)
-  sd t0, 128(s0)
-  ld t0, 1832(s0)
-  sd t0, 136(s0)
-  ld t0, 1840(s0)
-  sd t0, 144(s0)
-  ld t0, 0(s0)
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 156(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 160(s0)
-  lw t0, 160(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 164(s0)
-  ld t0, 8(s0)
-  lw t1, 164(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 172(s0)
-  lw t0, 156(s0)
-  lw t1, 172(s0)
-  add t0, t0, t1
-  sw t0, 176(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 180(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 184(s0)
-  lw t0, 180(s0)
-  lw t1, 184(s0)
-  add t0, t0, t1
-  sw t0, 188(s0)
-  lw t0, 188(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 192(s0)
-  ld t0, 16(s0)
-  lw t1, 192(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 200(s0)
-  lw t0, 176(s0)
-  lw t1, 200(s0)
-  add t0, t0, t1
-  sw t0, 204(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 208(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 212(s0)
-  lw t0, 208(s0)
-  lw t1, 212(s0)
-  add t0, t0, t1
-  sw t0, 216(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 220(s0)
-  lw t0, 216(s0)
-  lw t1, 220(s0)
-  add t0, t0, t1
-  sw t0, 224(s0)
-  lw t0, 224(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 228(s0)
-  ld t0, 24(s0)
-  lw t1, 228(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 236(s0)
-  lw t0, 204(s0)
-  lw t1, 236(s0)
-  add t0, t0, t1
-  sw t0, 240(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 244(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 248(s0)
-  lw t0, 244(s0)
-  lw t1, 248(s0)
-  add t0, t0, t1
-  sw t0, 252(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 256(s0)
-  lw t0, 252(s0)
-  lw t1, 256(s0)
-  add t0, t0, t1
-  sw t0, 260(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 264(s0)
-  lw t0, 260(s0)
-  lw t1, 264(s0)
-  add t0, t0, t1
-  sw t0, 268(s0)
-  lw t0, 268(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 272(s0)
-  ld t0, 32(s0)
-  lw t1, 272(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 280(s0)
-  lw t0, 240(s0)
-  lw t1, 280(s0)
-  add t0, t0, t1
-  sw t0, 284(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 288(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 292(s0)
-  lw t0, 288(s0)
-  lw t1, 292(s0)
-  add t0, t0, t1
-  sw t0, 296(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 300(s0)
-  lw t0, 296(s0)
-  lw t1, 300(s0)
-  add t0, t0, t1
-  sw t0, 304(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 308(s0)
-  lw t0, 304(s0)
-  lw t1, 308(s0)
-  add t0, t0, t1
-  sw t0, 312(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 316(s0)
-  lw t0, 312(s0)
-  lw t1, 316(s0)
-  add t0, t0, t1
-  sw t0, 320(s0)
-  lw t0, 320(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 324(s0)
-  ld t0, 40(s0)
-  lw t1, 324(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 332(s0)
-  lw t0, 284(s0)
-  lw t1, 332(s0)
-  add t0, t0, t1
-  sw t0, 336(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 340(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 344(s0)
-  lw t0, 340(s0)
-  lw t1, 344(s0)
-  add t0, t0, t1
-  sw t0, 348(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 352(s0)
-  lw t0, 348(s0)
-  lw t1, 352(s0)
-  add t0, t0, t1
-  sw t0, 356(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 360(s0)
-  lw t0, 356(s0)
-  lw t1, 360(s0)
-  add t0, t0, t1
-  sw t0, 364(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 368(s0)
-  lw t0, 364(s0)
-  lw t1, 368(s0)
-  add t0, t0, t1
-  sw t0, 372(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 376(s0)
-  lw t0, 372(s0)
-  lw t1, 376(s0)
-  add t0, t0, t1
-  sw t0, 380(s0)
-  lw t0, 380(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 384(s0)
-  ld t0, 48(s0)
-  lw t1, 384(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 392(s0)
-  lw t0, 336(s0)
-  lw t1, 392(s0)
-  add t0, t0, t1
-  sw t0, 396(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 400(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 404(s0)
-  lw t0, 400(s0)
-  lw t1, 404(s0)
-  add t0, t0, t1
-  sw t0, 408(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 412(s0)
-  lw t0, 408(s0)
-  lw t1, 412(s0)
-  add t0, t0, t1
-  sw t0, 416(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 420(s0)
-  lw t0, 416(s0)
-  lw t1, 420(s0)
-  add t0, t0, t1
-  sw t0, 424(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 428(s0)
-  lw t0, 424(s0)
-  lw t1, 428(s0)
-  add t0, t0, t1
-  sw t0, 432(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 436(s0)
-  lw t0, 432(s0)
-  lw t1, 436(s0)
-  add t0, t0, t1
-  sw t0, 440(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 444(s0)
-  lw t0, 440(s0)
-  lw t1, 444(s0)
-  add t0, t0, t1
-  sw t0, 448(s0)
-  lw t0, 448(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 452(s0)
-  ld t0, 56(s0)
-  lw t1, 452(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 460(s0)
-  lw t0, 396(s0)
-  lw t1, 460(s0)
-  add t0, t0, t1
-  sw t0, 464(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 468(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 472(s0)
-  lw t0, 468(s0)
-  lw t1, 472(s0)
-  add t0, t0, t1
-  sw t0, 476(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 480(s0)
-  lw t0, 476(s0)
-  lw t1, 480(s0)
-  add t0, t0, t1
-  sw t0, 484(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 488(s0)
-  lw t0, 484(s0)
-  lw t1, 488(s0)
-  add t0, t0, t1
-  sw t0, 492(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 496(s0)
-  lw t0, 492(s0)
-  lw t1, 496(s0)
-  add t0, t0, t1
-  sw t0, 500(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 504(s0)
-  lw t0, 500(s0)
-  lw t1, 504(s0)
-  add t0, t0, t1
-  sw t0, 508(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 512(s0)
-  lw t0, 508(s0)
-  lw t1, 512(s0)
-  add t0, t0, t1
-  sw t0, 516(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 520(s0)
-  lw t0, 516(s0)
-  lw t1, 520(s0)
-  add t0, t0, t1
-  sw t0, 524(s0)
-  lw t0, 524(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 528(s0)
-  ld t0, 64(s0)
-  lw t1, 528(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 536(s0)
-  lw t0, 464(s0)
-  lw t1, 536(s0)
-  add t0, t0, t1
-  sw t0, 540(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 544(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 548(s0)
-  lw t0, 544(s0)
-  lw t1, 548(s0)
-  add t0, t0, t1
-  sw t0, 552(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 556(s0)
-  lw t0, 552(s0)
-  lw t1, 556(s0)
-  add t0, t0, t1
-  sw t0, 560(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 564(s0)
-  lw t0, 560(s0)
-  lw t1, 564(s0)
-  add t0, t0, t1
-  sw t0, 568(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 572(s0)
-  lw t0, 568(s0)
-  lw t1, 572(s0)
-  add t0, t0, t1
-  sw t0, 576(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 580(s0)
-  lw t0, 576(s0)
-  lw t1, 580(s0)
-  add t0, t0, t1
-  sw t0, 584(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 588(s0)
-  lw t0, 584(s0)
-  lw t1, 588(s0)
-  add t0, t0, t1
-  sw t0, 592(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 596(s0)
-  lw t0, 592(s0)
-  lw t1, 596(s0)
-  add t0, t0, t1
-  sw t0, 600(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 604(s0)
-  lw t0, 600(s0)
-  lw t1, 604(s0)
-  add t0, t0, t1
-  sw t0, 608(s0)
-  lw t0, 608(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 612(s0)
-  ld t0, 72(s0)
-  lw t1, 612(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 620(s0)
-  lw t0, 540(s0)
-  lw t1, 620(s0)
-  add t0, t0, t1
-  sw t0, 624(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 628(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 632(s0)
-  lw t0, 628(s0)
-  lw t1, 632(s0)
-  add t0, t0, t1
-  sw t0, 636(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 640(s0)
-  lw t0, 636(s0)
-  lw t1, 640(s0)
-  add t0, t0, t1
-  sw t0, 644(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 648(s0)
-  lw t0, 644(s0)
-  lw t1, 648(s0)
-  add t0, t0, t1
-  sw t0, 652(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 656(s0)
-  lw t0, 652(s0)
-  lw t1, 656(s0)
-  add t0, t0, t1
-  sw t0, 660(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 664(s0)
-  lw t0, 660(s0)
-  lw t1, 664(s0)
-  add t0, t0, t1
-  sw t0, 668(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 672(s0)
-  lw t0, 668(s0)
-  lw t1, 672(s0)
-  add t0, t0, t1
-  sw t0, 676(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 680(s0)
-  lw t0, 676(s0)
-  lw t1, 680(s0)
-  add t0, t0, t1
-  sw t0, 684(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 688(s0)
-  lw t0, 684(s0)
-  lw t1, 688(s0)
-  add t0, t0, t1
-  sw t0, 692(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 696(s0)
-  lw t0, 692(s0)
-  lw t1, 696(s0)
-  add t0, t0, t1
-  sw t0, 700(s0)
-  lw t0, 700(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 704(s0)
-  ld t0, 80(s0)
-  lw t1, 704(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 712(s0)
-  lw t0, 624(s0)
-  lw t1, 712(s0)
-  add t0, t0, t1
-  sw t0, 716(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 720(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 724(s0)
-  lw t0, 720(s0)
-  lw t1, 724(s0)
-  add t0, t0, t1
-  sw t0, 728(s0)
-  li t0, 1
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 732(s0)
-  lw t0, 728(s0)
-  lw t1, 732(s0)
-  add t0, t0, t1
-  sw t0, 736(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 740(s0)
-  lw t0, 736(s0)
-  lw t1, 740(s0)
-  add t0, t0, t1
-  sw t0, 744(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 748(s0)
-  lw t0, 744(s0)
-  lw t1, 748(s0)
-  add t0, t0, t1
-  sw t0, 752(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 756(s0)
-  lw t0, 752(s0)
-  lw t1, 756(s0)
-  add t0, t0, t1
-  sw t0, 760(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 764(s0)
-  lw t0, 760(s0)
-  lw t1, 764(s0)
-  add t0, t0, t1
-  sw t0, 768(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 772(s0)
-  lw t0, 768(s0)
-  lw t1, 772(s0)
-  add t0, t0, t1
-  sw t0, 776(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 780(s0)
-  lw t0, 776(s0)
-  lw t1, 780(s0)
-  add t0, t0, t1
-  sw t0, 784(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 788(s0)
-  lw t0, 784(s0)
-  lw t1, 788(s0)
-  add t0, t0, t1
-  sw t0, 792(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 796(s0)
-  lw t0, 792(s0)
-  lw t1, 796(s0)
-  add t0, t0, t1
-  sw t0, 800(s0)
-  lw t0, 800(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 804(s0)
-  ld t0, 88(s0)
-  lw t1, 804(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 812(s0)
-  lw t0, 716(s0)
-  lw t1, 812(s0)
-  add t0, t0, t1
-  sw t0, 816(s0)
-  li t0, 1
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 820(s0)
-  li t0, 1
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 824(s0)
-  lw t0, 820(s0)
-  lw t1, 824(s0)
-  add t0, t0, t1
-  sw t0, 828(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 832(s0)
-  lw t0, 828(s0)
-  lw t1, 832(s0)
-  add t0, t0, t1
-  sw t0, 836(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 840(s0)
-  lw t0, 836(s0)
-  lw t1, 840(s0)
-  add t0, t0, t1
-  sw t0, 844(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 848(s0)
-  lw t0, 844(s0)
-  lw t1, 848(s0)
-  add t0, t0, t1
-  sw t0, 852(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 856(s0)
-  lw t0, 852(s0)
-  lw t1, 856(s0)
-  add t0, t0, t1
-  sw t0, 860(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 864(s0)
-  lw t0, 860(s0)
-  lw t1, 864(s0)
-  add t0, t0, t1
-  sw t0, 868(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 872(s0)
-  lw t0, 868(s0)
-  lw t1, 872(s0)
-  add t0, t0, t1
-  sw t0, 876(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 880(s0)
-  lw t0, 876(s0)
-  lw t1, 880(s0)
-  add t0, t0, t1
-  sw t0, 884(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 888(s0)
-  lw t0, 884(s0)
-  lw t1, 888(s0)
-  add t0, t0, t1
-  sw t0, 892(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 896(s0)
-  lw t0, 892(s0)
-  lw t1, 896(s0)
-  add t0, t0, t1
-  sw t0, 900(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 904(s0)
-  lw t0, 900(s0)
-  lw t1, 904(s0)
-  add t0, t0, t1
-  sw t0, 908(s0)
-  lw t0, 908(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 912(s0)
-  ld t0, 96(s0)
-  lw t1, 912(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 920(s0)
-  lw t0, 816(s0)
-  lw t1, 920(s0)
-  add t0, t0, t1
-  sw t0, 924(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 928(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 932(s0)
-  lw t0, 928(s0)
-  lw t1, 932(s0)
-  add t0, t0, t1
-  sw t0, 936(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 940(s0)
-  lw t0, 936(s0)
-  lw t1, 940(s0)
-  add t0, t0, t1
-  sw t0, 944(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 948(s0)
-  lw t0, 944(s0)
-  lw t1, 948(s0)
-  add t0, t0, t1
-  sw t0, 952(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 956(s0)
-  lw t0, 952(s0)
-  lw t1, 956(s0)
-  add t0, t0, t1
-  sw t0, 960(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 964(s0)
-  lw t0, 960(s0)
-  lw t1, 964(s0)
-  add t0, t0, t1
-  sw t0, 968(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 972(s0)
-  lw t0, 968(s0)
-  lw t1, 972(s0)
-  add t0, t0, t1
-  sw t0, 976(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 980(s0)
-  lw t0, 976(s0)
-  lw t1, 980(s0)
-  add t0, t0, t1
-  sw t0, 984(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 988(s0)
-  lw t0, 984(s0)
-  lw t1, 988(s0)
-  add t0, t0, t1
-  sw t0, 992(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 996(s0)
-  lw t0, 992(s0)
-  lw t1, 996(s0)
-  add t0, t0, t1
-  sw t0, 1000(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1004(s0)
-  lw t0, 1000(s0)
-  lw t1, 1004(s0)
-  add t0, t0, t1
-  sw t0, 1008(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1012(s0)
-  lw t0, 1008(s0)
-  lw t1, 1012(s0)
-  add t0, t0, t1
-  sw t0, 1016(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1020(s0)
-  lw t0, 1016(s0)
-  lw t1, 1020(s0)
-  add t0, t0, t1
-  sw t0, 1024(s0)
-  lw t0, 1024(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1028(s0)
-  ld t0, 104(s0)
-  lw t1, 1028(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1036(s0)
-  lw t0, 924(s0)
-  lw t1, 1036(s0)
-  add t0, t0, t1
-  sw t0, 1040(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1044(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1048(s0)
-  lw t0, 1044(s0)
-  lw t1, 1048(s0)
-  add t0, t0, t1
-  sw t0, 1052(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1056(s0)
-  lw t0, 1052(s0)
-  lw t1, 1056(s0)
-  add t0, t0, t1
-  sw t0, 1060(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1064(s0)
-  lw t0, 1060(s0)
-  lw t1, 1064(s0)
-  add t0, t0, t1
-  sw t0, 1068(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1072(s0)
-  lw t0, 1068(s0)
-  lw t1, 1072(s0)
-  add t0, t0, t1
-  sw t0, 1076(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1080(s0)
-  lw t0, 1076(s0)
-  lw t1, 1080(s0)
-  add t0, t0, t1
-  sw t0, 1084(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1088(s0)
-  lw t0, 1084(s0)
-  lw t1, 1088(s0)
-  add t0, t0, t1
-  sw t0, 1092(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1096(s0)
-  lw t0, 1092(s0)
-  lw t1, 1096(s0)
-  add t0, t0, t1
-  sw t0, 1100(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1104(s0)
-  lw t0, 1100(s0)
-  lw t1, 1104(s0)
-  add t0, t0, t1
-  sw t0, 1108(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1112(s0)
-  lw t0, 1108(s0)
-  lw t1, 1112(s0)
-  add t0, t0, t1
-  sw t0, 1116(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1120(s0)
-  lw t0, 1116(s0)
-  lw t1, 1120(s0)
-  add t0, t0, t1
-  sw t0, 1124(s0)
-  li t0, 1
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1128(s0)
-  lw t0, 1124(s0)
-  lw t1, 1128(s0)
-  add t0, t0, t1
-  sw t0, 1132(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1136(s0)
-  lw t0, 1132(s0)
-  lw t1, 1136(s0)
-  add t0, t0, t1
-  sw t0, 1140(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1144(s0)
-  lw t0, 1140(s0)
-  lw t1, 1144(s0)
-  add t0, t0, t1
-  sw t0, 1148(s0)
-  lw t0, 1148(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1152(s0)
-  ld t0, 112(s0)
-  lw t1, 1152(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1160(s0)
-  lw t0, 1040(s0)
-  lw t1, 1160(s0)
-  add t0, t0, t1
-  sw t0, 1164(s0)
-  li t0, 1
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1168(s0)
-  li t0, 1
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1172(s0)
-  lw t0, 1168(s0)
-  lw t1, 1172(s0)
-  add t0, t0, t1
-  sw t0, 1176(s0)
-  li t0, 1
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1180(s0)
-  lw t0, 1176(s0)
-  lw t1, 1180(s0)
-  add t0, t0, t1
-  sw t0, 1184(s0)
-  li t0, 1
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1188(s0)
-  lw t0, 1184(s0)
-  lw t1, 1188(s0)
-  add t0, t0, t1
-  sw t0, 1192(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1196(s0)
-  lw t0, 1192(s0)
-  lw t1, 1196(s0)
-  add t0, t0, t1
-  sw t0, 1200(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1204(s0)
-  lw t0, 1200(s0)
-  lw t1, 1204(s0)
-  add t0, t0, t1
-  sw t0, 1208(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1212(s0)
-  lw t0, 1208(s0)
-  lw t1, 1212(s0)
-  add t0, t0, t1
-  sw t0, 1216(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1220(s0)
-  lw t0, 1216(s0)
-  lw t1, 1220(s0)
-  add t0, t0, t1
-  sw t0, 1224(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1228(s0)
-  lw t0, 1224(s0)
-  lw t1, 1228(s0)
-  add t0, t0, t1
-  sw t0, 1232(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1236(s0)
-  lw t0, 1232(s0)
-  lw t1, 1236(s0)
-  add t0, t0, t1
-  sw t0, 1240(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1244(s0)
-  lw t0, 1240(s0)
-  lw t1, 1244(s0)
-  add t0, t0, t1
-  sw t0, 1248(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1252(s0)
-  lw t0, 1248(s0)
-  lw t1, 1252(s0)
-  add t0, t0, t1
-  sw t0, 1256(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1260(s0)
-  lw t0, 1256(s0)
-  lw t1, 1260(s0)
-  add t0, t0, t1
-  sw t0, 1264(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1268(s0)
-  lw t0, 1264(s0)
-  lw t1, 1268(s0)
-  add t0, t0, t1
-  sw t0, 1272(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1276(s0)
-  lw t0, 1272(s0)
-  lw t1, 1276(s0)
-  add t0, t0, t1
-  sw t0, 1280(s0)
-  lw t0, 1280(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 1284(s0)
-  ld t0, 120(s0)
-  lw t1, 1284(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1292(s0)
-  lw t0, 1164(s0)
-  lw t1, 1292(s0)
-  add t0, t0, t1
-  sw t0, 1296(s0)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  sw t0, 1300(s0)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1304(s0)
-  lw t0, 1300(s0)
-  lw t1, 1304(s0)
-  add t0, t0, t1
-  sw t0, 1308(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1312(s0)
-  lw t0, 1308(s0)
-  lw t1, 1312(s0)
-  add t0, t0, t1
-  sw t0, 1316(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1320(s0)
-  lw t0, 1316(s0)
-  lw t1, 1320(s0)
-  add t0, t0, t1
-  sw t0, 1324(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1328(s0)
-  lw t0, 1324(s0)
-  lw t1, 1328(s0)
-  add t0, t0, t1
-  sw t0, 1332(s0)
-  li t0, 1
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1336(s0)
-  lw t0, 1332(s0)
-  lw t1, 1336(s0)
-  add t0, t0, t1
-  sw t0, 1340(s0)
-  li t0, 1
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1344(s0)
-  lw t0, 1340(s0)
-  lw t1, 1344(s0)
-  add t0, t0, t1
-  sw t0, 1348(s0)
-  li t0, 1
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1352(s0)
-  lw t0, 1348(s0)
-  lw t1, 1352(s0)
-  add t0, t0, t1
-  sw t0, 1356(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1360(s0)
-  lw t0, 1356(s0)
-  lw t1, 1360(s0)
-  add t0, t0, t1
-  sw t0, 1364(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1368(s0)
-  lw t0, 1364(s0)
-  lw t1, 1368(s0)
-  add t0, t0, t1
-  sw t0, 1372(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1376(s0)
-  lw t0, 1372(s0)
-  lw t1, 1376(s0)
-  add t0, t0, t1
-  sw t0, 1380(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1384(s0)
-  lw t0, 1380(s0)
-  lw t1, 1384(s0)
-  add t0, t0, t1
-  sw t0, 1388(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1392(s0)
-  lw t0, 1388(s0)
-  lw t1, 1392(s0)
-  add t0, t0, t1
-  sw t0, 1396(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1400(s0)
-  lw t0, 1396(s0)
-  lw t1, 1400(s0)
-  add t0, t0, t1
-  sw t0, 1404(s0)
-  li t0, 1
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1408(s0)
-  lw t0, 1404(s0)
-  lw t1, 1408(s0)
-  add t0, t0, t1
-  sw t0, 1412(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1416(s0)
-  lw t0, 1412(s0)
-  lw t1, 1416(s0)
-  add t0, t0, t1
-  sw t0, 1420(s0)
-  lw t0, 1420(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1424(s0)
-  ld t0, 128(s0)
-  lw t1, 1424(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1432(s0)
-  lw t0, 1296(s0)
-  lw t1, 1432(s0)
-  add t0, t0, t1
-  sw t0, 1436(s0)
-  li t0, 1
-  li t1, 131072
-  mul t0, t0, t1
-  sw t0, 1440(s0)
-  li t0, 1
-  li t1, 65536
-  mul t0, t0, t1
-  sw t0, 1444(s0)
-  lw t0, 1440(s0)
-  lw t1, 1444(s0)
-  add t0, t0, t1
-  sw t0, 1448(s0)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1452(s0)
-  lw t0, 1448(s0)
-  lw t1, 1452(s0)
-  add t0, t0, t1
-  sw t0, 1456(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1460(s0)
-  lw t0, 1456(s0)
-  lw t1, 1460(s0)
-  add t0, t0, t1
-  sw t0, 1464(s0)
-  li t0, 1
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1468(s0)
-  lw t0, 1464(s0)
-  lw t1, 1468(s0)
-  add t0, t0, t1
-  sw t0, 1472(s0)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1476(s0)
-  lw t0, 1472(s0)
-  lw t1, 1476(s0)
-  add t0, t0, t1
-  sw t0, 1480(s0)
-  li t0, 1
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1484(s0)
-  lw t0, 1480(s0)
-  lw t1, 1484(s0)
-  add t0, t0, t1
-  sw t0, 1488(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1492(s0)
-  lw t0, 1488(s0)
-  lw t1, 1492(s0)
-  add t0, t0, t1
-  sw t0, 1496(s0)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1500(s0)
-  lw t0, 1496(s0)
-  lw t1, 1500(s0)
-  add t0, t0, t1
-  sw t0, 1504(s0)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1508(s0)
-  lw t0, 1504(s0)
-  lw t1, 1508(s0)
-  add t0, t0, t1
-  sw t0, 1512(s0)
-  li t0, 1
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1516(s0)
-  lw t0, 1512(s0)
-  lw t1, 1516(s0)
-  add t0, t0, t1
-  sw t0, 1520(s0)
-  li t0, 1
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1524(s0)
-  lw t0, 1520(s0)
-  lw t1, 1524(s0)
-  add t0, t0, t1
-  sw t0, 1528(s0)
-  li t0, 1
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1532(s0)
-  lw t0, 1528(s0)
-  lw t1, 1532(s0)
-  add t0, t0, t1
-  sw t0, 1536(s0)
-  li t0, 1
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1540(s0)
-  lw t0, 1536(s0)
-  lw t1, 1540(s0)
-  add t0, t0, t1
-  sw t0, 1544(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1548(s0)
-  lw t0, 1544(s0)
-  lw t1, 1548(s0)
-  add t0, t0, t1
-  sw t0, 1552(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1556(s0)
-  lw t0, 1552(s0)
-  lw t1, 1556(s0)
-  add t0, t0, t1
-  sw t0, 1560(s0)
-  li t0, 1
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1564(s0)
-  lw t0, 1560(s0)
-  lw t1, 1564(s0)
-  add t0, t0, t1
-  sw t0, 1568(s0)
-  lw t0, 1568(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1572(s0)
-  ld t0, 136(s0)
-  lw t1, 1572(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1580(s0)
-  lw t0, 1436(s0)
-  lw t1, 1580(s0)
-  add t0, t0, t1
-  sw t0, 1584(s0)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  sw t0, 1588(s0)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  sw t0, 1592(s0)
-  lw t0, 1588(s0)
-  lw t1, 1592(s0)
-  add t0, t0, t1
-  sw t0, 1596(s0)
-  li t0, 1
-  li t1, 65536
-  mul t0, t0, t1
-  sw t0, 1600(s0)
-  lw t0, 1596(s0)
-  lw t1, 1600(s0)
-  add t0, t0, t1
-  sw t0, 1604(s0)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  sw t0, 1608(s0)
-  lw t0, 1604(s0)
-  lw t1, 1608(s0)
-  add t0, t0, t1
-  sw t0, 1612(s0)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  sw t0, 1616(s0)
-  lw t0, 1612(s0)
-  lw t1, 1616(s0)
-  add t0, t0, t1
-  sw t0, 1620(s0)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  sw t0, 1624(s0)
-  lw t0, 1620(s0)
-  lw t1, 1624(s0)
-  add t0, t0, t1
-  sw t0, 1628(s0)
-  li t0, 1
-  li t1, 4096
-  mul t0, t0, t1
-  sw t0, 1632(s0)
-  lw t0, 1628(s0)
-  lw t1, 1632(s0)
-  add t0, t0, t1
-  sw t0, 1636(s0)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  sw t0, 1640(s0)
-  lw t0, 1636(s0)
-  lw t1, 1640(s0)
-  add t0, t0, t1
-  sw t0, 1644(s0)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  sw t0, 1648(s0)
-  lw t0, 1644(s0)
-  lw t1, 1648(s0)
-  add t0, t0, t1
-  sw t0, 1652(s0)
-  li t0, 1
-  li t1, 512
-  mul t0, t0, t1
-  sw t0, 1656(s0)
-  lw t0, 1652(s0)
-  lw t1, 1656(s0)
-  add t0, t0, t1
-  sw t0, 1660(s0)
-  li t0, 1
-  li t1, 256
-  mul t0, t0, t1
-  sw t0, 1664(s0)
-  lw t0, 1660(s0)
-  lw t1, 1664(s0)
-  add t0, t0, t1
-  sw t0, 1668(s0)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  sw t0, 1672(s0)
-  lw t0, 1668(s0)
-  lw t1, 1672(s0)
-  add t0, t0, t1
-  sw t0, 1676(s0)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  sw t0, 1680(s0)
-  lw t0, 1676(s0)
-  lw t1, 1680(s0)
-  add t0, t0, t1
-  sw t0, 1684(s0)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  sw t0, 1688(s0)
-  lw t0, 1684(s0)
-  lw t1, 1688(s0)
-  add t0, t0, t1
-  sw t0, 1692(s0)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  sw t0, 1696(s0)
-  lw t0, 1692(s0)
-  lw t1, 1696(s0)
-  add t0, t0, t1
-  sw t0, 1700(s0)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  sw t0, 1704(s0)
-  lw t0, 1700(s0)
-  lw t1, 1704(s0)
-  add t0, t0, t1
-  sw t0, 1708(s0)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  sw t0, 1712(s0)
-  lw t0, 1708(s0)
-  lw t1, 1712(s0)
-  add t0, t0, t1
-  sw t0, 1716(s0)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, 1720(s0)
-  lw t0, 1716(s0)
-  lw t1, 1720(s0)
-  add t0, t0, t1
-  sw t0, 1724(s0)
-  lw t0, 1724(s0)
-  li t1, 0
-  add t0, t0, t1
-  sw t0, 1728(s0)
-  ld t0, 144(s0)
-  lw t1, 1728(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1736(s0)
-  lw t0, 1584(s0)
-  lw t1, 1736(s0)
-  add t0, t0, t1
-  sw t0, 1740(s0)
-  lw a0, 1740(s0)
-  ld ra, 1744(s0)
-  addi sp, s0, 1760
-  ld s0, 1752(s0)
-  ret
-.size sum, .-sum
-
-.global main
-.type main, @function
-main:
-  li t4, -2099184
-  add sp, sp, t4
-  li t4, 2099168
-  add t4, sp, t4
-  sd ra, 0(t4)
-  li t4, 2099176
-  add t4, sp, t4
-  sd s0, 0(t4)
-  mv s0, sp
-  addi a0, s0, 0
-  li a1, 0
-  li a2, 2097152
-  call memset
-  li t0, 0
-  li t4, 2097152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t4, 2097156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L0.while.cond
-L0.while.cond:
-  li t4, 2097156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097160
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097160
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097164
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097164
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L1.while.body
-  j L2.while.end
-L1.while.body:
-  li t0, 0
-  li t4, 2097168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L3.while.cond
-L3.while.cond:
-  li t4, 2097168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097172
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097176
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097176
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L4.while.body
-  j L5.while.end
-L4.while.body:
-  li t0, 0
-  li t4, 2097180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L6.while.cond
-L6.while.cond:
-  li t4, 2097180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097184
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097184
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097188
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L7.while.body
-  j L8.while.end
-L7.while.body:
-  li t0, 0
-  li t4, 2097192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L9.while.cond
-L9.while.cond:
-  li t4, 2097192
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097196
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097196
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097200
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097200
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L10.while.body
-  j L11.while.end
-L10.while.body:
-  li t0, 0
-  li t4, 2097204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L12.while.cond
-L12.while.cond:
-  li t4, 2097204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097208
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097208
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097212
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097212
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L13.while.body
-  j L14.while.end
-L13.while.body:
-  li t0, 0
-  li t4, 2097216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L15.while.cond
-L15.while.cond:
-  li t4, 2097216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097220
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097220
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097224
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097224
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L16.while.body
-  j L17.while.end
-L16.while.body:
-  li t0, 0
-  li t4, 2097228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L18.while.cond
-L18.while.cond:
-  li t4, 2097228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097232
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097232
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097236
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097236
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L19.while.body
-  j L20.while.end
-L19.while.body:
-  li t0, 0
-  li t4, 2097240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L21.while.cond
-L21.while.cond:
-  li t4, 2097240
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097244
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097244
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097248
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097248
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L22.while.body
-  j L23.while.end
-L22.while.body:
-  li t0, 0
-  li t4, 2097252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L24.while.cond
-L24.while.cond:
-  li t4, 2097252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097256
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097256
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097260
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097260
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L25.while.body
-  j L26.while.end
-L25.while.body:
-  li t0, 0
-  li t4, 2097264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L27.while.cond
-L27.while.cond:
-  li t4, 2097264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097268
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097268
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097272
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097272
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L28.while.body
-  j L29.while.end
-L28.while.body:
-  li t0, 0
-  li t4, 2097276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L30.while.cond
-L30.while.cond:
-  li t4, 2097276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097280
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097280
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097284
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097284
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L31.while.body
-  j L32.while.end
-L31.while.body:
-  li t0, 0
-  li t4, 2097288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L33.while.cond
-L33.while.cond:
-  li t4, 2097288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097292
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097296
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097296
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L34.while.body
-  j L35.while.end
-L34.while.body:
-  li t0, 0
-  li t4, 2097300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L36.while.cond
-L36.while.cond:
-  li t4, 2097300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097304
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097304
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097308
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097308
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L37.while.body
-  j L38.while.end
-L37.while.body:
-  li t0, 0
-  li t4, 2097312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L39.while.cond
-L39.while.cond:
-  li t4, 2097312
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097316
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097320
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097320
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L40.while.body
-  j L41.while.end
-L40.while.body:
-  li t0, 0
-  li t4, 2097324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L42.while.cond
-L42.while.cond:
-  li t4, 2097324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097328
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097328
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097332
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097332
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L43.while.body
-  j L44.while.end
-L43.while.body:
-  li t0, 0
-  li t4, 2097336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L45.while.cond
-L45.while.cond:
-  li t4, 2097336
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097340
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097340
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097344
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097344
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L46.while.body
-  j L47.while.end
-L46.while.body:
-  li t0, 0
-  li t4, 2097348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L48.while.cond
-L48.while.cond:
-  li t4, 2097348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097352
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097352
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097356
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097356
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L49.while.body
-  j L50.while.end
-L49.while.body:
-  li t0, 0
-  li t4, 2097360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L51.while.cond
-L51.while.cond:
-  li t4, 2097360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097364
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097364
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097368
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097368
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L52.while.body
-  j L53.while.end
-L52.while.body:
-  li t0, 0
-  li t4, 2097372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L54.while.cond
-L54.while.cond:
-  li t4, 2097372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097376
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097376
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  slt t0, t0, t1
-  li t4, 2097380
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097380
-  add t4, s0, t4
-  lw t0, 0(t4)
-  bnez t0, L55.while.body
-  j L56.while.end
-L55.while.body:
-  li t4, 2097152
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097384
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097388
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097388
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2097392
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097396
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097396
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2097400
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097392
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097400
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097404
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097408
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097408
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2097412
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097404
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097412
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097416
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097192
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097420
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097420
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2097424
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097416
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097424
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097428
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097432
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097432
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2097436
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097428
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097436
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097440
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097444
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097444
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2097448
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097440
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097448
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097452
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097456
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097456
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2097460
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097452
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097460
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097464
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097240
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097468
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097468
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2097472
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097464
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097472
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097476
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097480
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097480
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2097484
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097476
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097484
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097488
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097492
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097492
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2097496
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097488
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097496
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097500
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097504
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097504
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2097508
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097500
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097508
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097512
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097516
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097516
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2097520
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097512
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097520
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097524
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097528
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097528
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2097532
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097524
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097532
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097536
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097312
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097540
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097540
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2097544
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097536
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097544
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097548
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097552
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097552
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2097556
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097548
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097556
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097560
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097336
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097564
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097564
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2097568
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097560
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097568
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097572
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097576
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097576
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 4
-  mul t0, t0, t1
-  li t4, 2097580
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097572
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097580
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097584
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097588
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097588
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 2
-  mul t0, t0, t1
-  li t4, 2097592
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097584
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097592
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097596
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097600
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097596
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097600
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097604
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097384
-  add t4, s0, t4
-  lw t2, 0(t4)
-  addi t0, s0, 0
-  li t4, 2097604
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t4, 2097152
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097612
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097612
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097616
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097616
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097620
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097620
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097624
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097624
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L54.while.cond
-L56.while.end:
-  li t4, 2097360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097628
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097628
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097632
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097632
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L51.while.cond
-L53.while.end:
-  li t4, 2097348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097636
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097636
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097640
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097640
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L48.while.cond
-L50.while.end:
-  li t4, 2097336
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097644
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097644
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097648
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097648
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L45.while.cond
-L47.while.end:
-  li t4, 2097324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097652
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097652
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097656
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097656
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L42.while.cond
-L44.while.end:
-  li t4, 2097312
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097660
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097660
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097664
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097664
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L39.while.cond
-L41.while.end:
-  li t4, 2097300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097668
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097668
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097672
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097672
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L36.while.cond
-L38.while.end:
-  li t4, 2097288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097676
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097676
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097680
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097680
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L33.while.cond
-L35.while.end:
-  li t4, 2097276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097684
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097684
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097688
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097688
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L30.while.cond
-L32.while.end:
-  li t4, 2097264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097692
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097692
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097696
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097696
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L27.while.cond
-L29.while.end:
-  li t4, 2097252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097700
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097700
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097704
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097704
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L24.while.cond
-L26.while.end:
-  li t4, 2097240
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097708
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097708
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097712
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097712
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L21.while.cond
-L23.while.end:
-  li t4, 2097228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097716
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097716
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097720
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097720
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L18.while.cond
-L20.while.end:
-  li t4, 2097216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097724
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097724
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097728
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097728
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L15.while.cond
-L17.while.end:
-  li t4, 2097204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097732
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097732
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097736
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097736
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L12.while.cond
-L14.while.end:
-  li t4, 2097192
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097740
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097740
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097744
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097744
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L9.while.cond
-L11.while.end:
-  li t4, 2097180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097748
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097748
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097752
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097752
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L6.while.cond
-L8.while.end:
-  li t4, 2097168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097756
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097756
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097760
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097760
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L3.while.cond
-L5.while.end:
-  li t4, 2097156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097764
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097764
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 1
-  add t0, t0, t1
-  li t4, 2097768
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097768
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  j L0.while.cond
-L2.while.end:
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2097772
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2097776
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097772
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097776
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097780
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2097784
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097780
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097784
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097788
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2097792
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097788
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097792
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097796
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2097800
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097796
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097800
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097804
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2097808
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097804
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097808
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097812
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2097816
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097812
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097816
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097820
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2097824
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097820
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097824
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097828
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2097832
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097828
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097832
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097836
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2097840
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097836
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097840
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097844
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2097848
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097844
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097848
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097852
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2097856
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097852
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097856
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097860
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2097864
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097860
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097864
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097868
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2097872
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097868
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097872
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097876
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2097880
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097876
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097880
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097884
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2097888
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097884
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097888
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097892
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  li t4, 2097896
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097892
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097896
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097900
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  li t4, 2097904
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097900
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097904
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097908
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2097916
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2097920
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097916
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097920
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097924
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2097928
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097924
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097928
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097932
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2097936
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097932
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097936
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097940
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2097944
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097940
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097944
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097948
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2097952
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097948
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097952
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097956
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2097960
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097956
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097960
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097964
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2097968
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097964
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097968
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097972
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2097976
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097972
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097976
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097980
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2097984
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097980
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097984
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097988
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2097992
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097988
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2097992
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2097996
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098000
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2097996
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098000
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098004
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098008
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098004
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098008
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098012
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098016
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098012
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098016
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098020
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2098024
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098020
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098024
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098028
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2098032
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098028
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098032
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098036
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4
-  mul t0, t0, t1
-  li t4, 2098040
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098036
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098040
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098044
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098056
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098052
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098056
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098060
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098064
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098060
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098064
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098072
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098068
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098072
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098080
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098076
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098080
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098084
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098088
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098084
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098088
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098092
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098096
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098092
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098096
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098100
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098104
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098100
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098104
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098108
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098112
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098108
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098112
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098120
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098116
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098120
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098124
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098128
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098124
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098128
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098132
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098136
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098132
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098136
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098140
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098144
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098140
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098144
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098148
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098152
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2098160
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098156
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098160
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098164
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8
-  mul t0, t0, t1
-  li t4, 2098168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098164
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098168
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098184
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098184
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098188
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098192
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098196
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098200
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098196
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098200
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098208
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098208
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098212
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098212
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098216
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098220
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098224
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098220
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098224
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098232
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098232
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098236
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098236
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098240
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098244
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098248
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098244
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098248
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098256
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098252
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098256
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098260
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098260
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098264
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098268
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098272
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098268
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098272
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098280
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098280
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098284
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16
-  mul t0, t0, t1
-  li t4, 2098288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098284
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098288
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098304
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098300
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098304
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098308
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098308
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098312
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098320
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098316
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098320
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098328
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098324
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098328
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098332
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098332
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098336
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098340
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098344
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098340
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098344
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098352
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098352
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098356
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098356
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098360
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098364
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098368
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098364
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098368
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098376
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098372
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098376
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098380
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098384
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098380
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098384
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098388
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098392
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098388
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098392
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098396
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32
-  mul t0, t0, t1
-  li t4, 2098400
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098396
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098400
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098404
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098412
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098416
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098412
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098416
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098420
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098424
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098420
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098424
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098428
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098432
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098428
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098432
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098436
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098440
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098436
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098440
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098444
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098448
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098444
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098448
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098452
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098456
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098452
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098456
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098460
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098464
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098460
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098464
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098468
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098472
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098468
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098472
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098476
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098480
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098476
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098480
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098484
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098488
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098484
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098488
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098492
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098496
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098492
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098496
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098500
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 64
-  mul t0, t0, t1
-  li t4, 2098504
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098500
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098504
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098508
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098516
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098520
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098516
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098520
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098524
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098528
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098524
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098528
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098532
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098536
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098532
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098536
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098540
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098544
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098540
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098544
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098548
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098552
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098548
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098552
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098556
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098560
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098556
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098560
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098564
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098568
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098564
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098568
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098572
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098576
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098572
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098576
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098580
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098584
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098580
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098584
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098588
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098592
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098588
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098592
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098596
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 128
-  mul t0, t0, t1
-  li t4, 2098600
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098596
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098600
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098604
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098612
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098616
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098612
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098616
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098620
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098624
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098620
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098624
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098628
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098632
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098628
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098632
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098636
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098640
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098636
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098640
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098644
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098648
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098644
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098648
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098652
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098656
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098652
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098656
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098660
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098664
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098660
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098664
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098668
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098672
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098668
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098672
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098676
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098680
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098676
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098680
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098684
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 256
-  mul t0, t0, t1
-  li t4, 2098688
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098684
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098688
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098692
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098700
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098704
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098700
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098704
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098708
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098712
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098708
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098712
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098716
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098720
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098716
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098720
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098724
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098728
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098724
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098728
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098732
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098736
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098732
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098736
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098740
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098744
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098740
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098744
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098748
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098752
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098748
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098752
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098756
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098760
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098756
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098760
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098764
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 512
-  mul t0, t0, t1
-  li t4, 2098768
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098764
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098768
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098772
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098780
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098784
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098780
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098784
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098788
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098792
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098788
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098792
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098796
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098800
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098796
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098800
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098804
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098808
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098804
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098808
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098812
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098816
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098812
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098816
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098820
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098824
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098820
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098824
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098828
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098832
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098828
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098832
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098836
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 1024
-  mul t0, t0, t1
-  li t4, 2098840
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098836
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098840
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098844
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098852
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098856
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098852
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098856
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098860
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098864
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098860
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098864
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098868
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098872
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098868
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098872
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098876
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098880
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098876
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098880
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098884
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098888
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098884
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098888
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098892
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098896
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098892
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098896
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098900
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 2048
-  mul t0, t0, t1
-  li t4, 2098904
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098900
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098904
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098908
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098916
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098920
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098916
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098920
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098924
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098928
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098924
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098928
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098932
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098936
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098932
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098936
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098940
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2098944
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098940
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098944
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098948
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2098952
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098948
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098952
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098956
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 4096
-  mul t0, t0, t1
-  li t4, 2098960
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098956
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098960
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098964
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2098972
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2098976
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098972
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098976
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098980
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2098984
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098980
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098984
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098988
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2098992
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098988
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2098992
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2098996
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2099000
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2098996
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099000
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099004
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 8192
-  mul t0, t0, t1
-  li t4, 2099008
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099004
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099008
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099012
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099020
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099024
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099020
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099024
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099028
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2099032
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099028
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099032
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099036
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2099040
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099036
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099040
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099044
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 16384
-  mul t0, t0, t1
-  li t4, 2099048
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099044
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099048
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099060
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099064
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099060
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099064
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2099072
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099068
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099072
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 32768
-  mul t0, t0, t1
-  li t4, 2099080
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099076
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099080
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099084
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099092
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099096
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099092
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099096
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099100
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 65536
-  mul t0, t0, t1
-  li t4, 2099104
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099100
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099104
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099108
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 131072
-  mul t0, t0, t1
-  li t4, 2099120
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099116
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2099120
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2099124
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 262144
-  mul t0, t0, t1
-  li t4, 2099132
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi sp, sp, -96
-  addi a0, s0, 0
-  li t4, 2097908
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a0, a0, t1
-  addi a1, s0, 0
-  li t4, 2098044
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a1, a1, t1
-  addi a2, s0, 0
-  li t4, 2098172
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a2, a2, t1
-  addi a3, s0, 0
-  li t4, 2098292
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a3, a3, t1
-  addi a4, s0, 0
-  li t4, 2098404
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a4, a4, t1
-  addi a5, s0, 0
-  li t4, 2098508
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a5, a5, t1
-  addi a6, s0, 0
-  li t4, 2098604
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a6, a6, t1
-  addi a7, s0, 0
-  li t4, 2098692
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a7, a7, t1
-  add t4, sp, zero
-  addi t0, s0, 0
-  li t4, 2098772
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 8
-  addi t0, s0, 0
-  li t4, 2098844
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 16
-  addi t0, s0, 0
-  li t4, 2098908
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  addi t0, s0, 0
-  li t4, 2098964
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 32
-  addi t0, s0, 0
-  li t4, 2099012
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 40
-  addi t0, s0, 0
-  li t4, 2099052
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  addi t0, s0, 0
-  li t4, 2099084
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 56
-  addi t0, s0, 0
-  li t4, 2099108
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  addi t0, s0, 0
-  li t4, 2099124
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 72
-  addi t0, s0, 0
-  li t4, 2099132
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 80
-  addi t0, s0, 0
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  call sum
-  addi sp, sp, 96
-  li t4, 2099144
-  add t4, s0, t4
-  sw a0, 0(t4)
-  li t4, 2099144
-  add t4, s0, t4
-  lw a0, 0(t4)
-  call putint
-  li t0, 0
-  li t1, 256
-  rem t0, t0, t1
-  li t4, 2099148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099148
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  add t0, t0, t1
-  li t4, 2099152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099152
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  rem t0, t0, t1
-  li t4, 2099156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2099156
-  add t4, s0, t4
-  lw a0, 0(t4)
-  call putint
-  li a0, 10
-  call putch
-  li a0, 0
-  li t3, 2099168
-  add t3, s0, t3
-  ld ra, 0(t3)
-  li t3, 2099184
-  add sp, s0, t3
-  li t3, 2099176
-  add t3, s0, t3
-  ld s0, 0(t3)
-  ret
-.size main, .-main
-
diff --git a/39_fp_params.txt b/39_fp_params.txt
deleted file mode 100644
index 9b6e148..0000000
--- a/39_fp_params.txt
+++ /dev/null
@@ -1,9102 +0,0 @@
-.data
-  .global k
-  .type k, @object
-  .size k, 4
-k:
-  .word 0
-.text
-.global params_f40
-.type params_f40, @function
-params_f40:
-  addi sp, sp, -944
-  sd ra, 928(sp)
-  sd s0, 936(sp)
-  mv s0, sp
-  fsw fa0, 0(s0)
-  fsw fa1, 4(s0)
-  fsw fa2, 8(s0)
-  fsw fa3, 12(s0)
-  fsw fa4, 16(s0)
-  fsw fa5, 20(s0)
-  fsw fa6, 24(s0)
-  fsw fa7, 28(s0)
-  flw ft0, 944(s0)
-  fsw ft0, 32(s0)
-  flw ft0, 952(s0)
-  fsw ft0, 36(s0)
-  flw ft0, 960(s0)
-  fsw ft0, 40(s0)
-  flw ft0, 968(s0)
-  fsw ft0, 44(s0)
-  flw ft0, 976(s0)
-  fsw ft0, 48(s0)
-  flw ft0, 984(s0)
-  fsw ft0, 52(s0)
-  flw ft0, 992(s0)
-  fsw ft0, 56(s0)
-  flw ft0, 1000(s0)
-  fsw ft0, 60(s0)
-  flw ft0, 1008(s0)
-  fsw ft0, 64(s0)
-  flw ft0, 1016(s0)
-  fsw ft0, 68(s0)
-  flw ft0, 1024(s0)
-  fsw ft0, 72(s0)
-  flw ft0, 1032(s0)
-  fsw ft0, 76(s0)
-  flw ft0, 1040(s0)
-  fsw ft0, 80(s0)
-  flw ft0, 1048(s0)
-  fsw ft0, 84(s0)
-  flw ft0, 1056(s0)
-  fsw ft0, 88(s0)
-  flw ft0, 1064(s0)
-  fsw ft0, 92(s0)
-  flw ft0, 1072(s0)
-  fsw ft0, 96(s0)
-  flw ft0, 1080(s0)
-  fsw ft0, 100(s0)
-  flw ft0, 1088(s0)
-  fsw ft0, 104(s0)
-  flw ft0, 1096(s0)
-  fsw ft0, 108(s0)
-  flw ft0, 1104(s0)
-  fsw ft0, 112(s0)
-  flw ft0, 1112(s0)
-  fsw ft0, 116(s0)
-  flw ft0, 1120(s0)
-  fsw ft0, 120(s0)
-  flw ft0, 1128(s0)
-  fsw ft0, 124(s0)
-  flw ft0, 1136(s0)
-  fsw ft0, 128(s0)
-  flw ft0, 1144(s0)
-  fsw ft0, 132(s0)
-  flw ft0, 1152(s0)
-  fsw ft0, 136(s0)
-  flw ft0, 1160(s0)
-  fsw ft0, 140(s0)
-  flw ft0, 1168(s0)
-  fsw ft0, 144(s0)
-  flw ft0, 1176(s0)
-  fsw ft0, 148(s0)
-  flw ft0, 1184(s0)
-  fsw ft0, 152(s0)
-  flw ft0, 1192(s0)
-  fsw ft0, 156(s0)
-  flw ft0, 0(s0)
-  fsw ft0, 160(s0)
-  flw ft0, 4(s0)
-  fsw ft0, 164(s0)
-  flw ft0, 8(s0)
-  fsw ft0, 168(s0)
-  flw ft0, 12(s0)
-  fsw ft0, 172(s0)
-  flw ft0, 16(s0)
-  fsw ft0, 176(s0)
-  flw ft0, 20(s0)
-  fsw ft0, 180(s0)
-  flw ft0, 24(s0)
-  fsw ft0, 184(s0)
-  flw ft0, 28(s0)
-  fsw ft0, 188(s0)
-  flw ft0, 32(s0)
-  fsw ft0, 192(s0)
-  flw ft0, 36(s0)
-  fsw ft0, 196(s0)
-  flw ft0, 40(s0)
-  fsw ft0, 200(s0)
-  flw ft0, 44(s0)
-  fsw ft0, 204(s0)
-  flw ft0, 48(s0)
-  fsw ft0, 208(s0)
-  flw ft0, 52(s0)
-  fsw ft0, 212(s0)
-  flw ft0, 56(s0)
-  fsw ft0, 216(s0)
-  flw ft0, 60(s0)
-  fsw ft0, 220(s0)
-  flw ft0, 64(s0)
-  fsw ft0, 224(s0)
-  flw ft0, 68(s0)
-  fsw ft0, 228(s0)
-  flw ft0, 72(s0)
-  fsw ft0, 232(s0)
-  flw ft0, 76(s0)
-  fsw ft0, 236(s0)
-  flw ft0, 80(s0)
-  fsw ft0, 240(s0)
-  flw ft0, 84(s0)
-  fsw ft0, 244(s0)
-  flw ft0, 88(s0)
-  fsw ft0, 248(s0)
-  flw ft0, 92(s0)
-  fsw ft0, 252(s0)
-  flw ft0, 96(s0)
-  fsw ft0, 256(s0)
-  flw ft0, 100(s0)
-  fsw ft0, 260(s0)
-  flw ft0, 104(s0)
-  fsw ft0, 264(s0)
-  flw ft0, 108(s0)
-  fsw ft0, 268(s0)
-  flw ft0, 112(s0)
-  fsw ft0, 272(s0)
-  flw ft0, 116(s0)
-  fsw ft0, 276(s0)
-  flw ft0, 120(s0)
-  fsw ft0, 280(s0)
-  flw ft0, 124(s0)
-  fsw ft0, 284(s0)
-  flw ft0, 128(s0)
-  fsw ft0, 288(s0)
-  flw ft0, 132(s0)
-  fsw ft0, 292(s0)
-  flw ft0, 136(s0)
-  fsw ft0, 296(s0)
-  flw ft0, 140(s0)
-  fsw ft0, 300(s0)
-  flw ft0, 144(s0)
-  fsw ft0, 304(s0)
-  flw ft0, 148(s0)
-  fsw ft0, 308(s0)
-  flw ft0, 152(s0)
-  fsw ft0, 312(s0)
-  flw ft0, 156(s0)
-  fsw ft0, 316(s0)
-  flw ft0, 316(s0)
-  fsw ft0, 320(s0)
-  li t0, 0
-  fcvt.s.w ft0, t0
-  fsw ft0, 324(s0)
-  flw ft0, 320(s0)
-  flw ft1, 324(s0)
-  feq.s t0, ft0, ft1
-  xori t0, t0, 1
-  sw t0, 328(s0)
-  lw t0, 328(s0)
-  bnez t0, L0.if.then
-  j L1.if.else
-L0.if.then:
-  flw ft0, 160(s0)
-  fsw ft0, 400(s0)
-  flw ft0, 164(s0)
-  fsw ft0, 404(s0)
-  flw ft0, 400(s0)
-  flw ft1, 404(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 408(s0)
-  flw ft0, 168(s0)
-  fsw ft0, 412(s0)
-  flw ft0, 408(s0)
-  flw ft1, 412(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 416(s0)
-  flw ft0, 172(s0)
-  fsw ft0, 420(s0)
-  flw ft0, 416(s0)
-  flw ft1, 420(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 424(s0)
-  flw ft0, 176(s0)
-  fsw ft0, 428(s0)
-  flw ft0, 180(s0)
-  fsw ft0, 432(s0)
-  flw ft0, 428(s0)
-  flw ft1, 432(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 436(s0)
-  flw ft0, 184(s0)
-  fsw ft0, 440(s0)
-  flw ft0, 436(s0)
-  flw ft1, 440(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 444(s0)
-  flw ft0, 188(s0)
-  fsw ft0, 448(s0)
-  flw ft0, 444(s0)
-  flw ft1, 448(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 452(s0)
-  flw ft0, 192(s0)
-  fsw ft0, 456(s0)
-  flw ft0, 196(s0)
-  fsw ft0, 460(s0)
-  flw ft0, 456(s0)
-  flw ft1, 460(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 464(s0)
-  flw ft0, 200(s0)
-  fsw ft0, 468(s0)
-  flw ft0, 464(s0)
-  flw ft1, 468(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 472(s0)
-  flw ft0, 204(s0)
-  fsw ft0, 476(s0)
-  flw ft0, 472(s0)
-  flw ft1, 476(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 480(s0)
-  flw ft0, 208(s0)
-  fsw ft0, 484(s0)
-  flw ft0, 212(s0)
-  fsw ft0, 488(s0)
-  flw ft0, 484(s0)
-  flw ft1, 488(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 492(s0)
-  flw ft0, 216(s0)
-  fsw ft0, 496(s0)
-  flw ft0, 492(s0)
-  flw ft1, 496(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 500(s0)
-  flw ft0, 220(s0)
-  fsw ft0, 504(s0)
-  flw ft0, 500(s0)
-  flw ft1, 504(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 508(s0)
-  flw ft0, 224(s0)
-  fsw ft0, 512(s0)
-  flw ft0, 228(s0)
-  fsw ft0, 516(s0)
-  flw ft0, 512(s0)
-  flw ft1, 516(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 520(s0)
-  flw ft0, 232(s0)
-  fsw ft0, 524(s0)
-  flw ft0, 520(s0)
-  flw ft1, 524(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 528(s0)
-  flw ft0, 236(s0)
-  fsw ft0, 532(s0)
-  flw ft0, 528(s0)
-  flw ft1, 532(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 536(s0)
-  flw ft0, 240(s0)
-  fsw ft0, 540(s0)
-  flw ft0, 244(s0)
-  fsw ft0, 544(s0)
-  flw ft0, 540(s0)
-  flw ft1, 544(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 548(s0)
-  flw ft0, 248(s0)
-  fsw ft0, 552(s0)
-  flw ft0, 548(s0)
-  flw ft1, 552(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 556(s0)
-  flw ft0, 252(s0)
-  fsw ft0, 560(s0)
-  flw ft0, 556(s0)
-  flw ft1, 560(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 564(s0)
-  flw ft0, 256(s0)
-  fsw ft0, 568(s0)
-  flw ft0, 260(s0)
-  fsw ft0, 572(s0)
-  flw ft0, 568(s0)
-  flw ft1, 572(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 576(s0)
-  flw ft0, 264(s0)
-  fsw ft0, 580(s0)
-  flw ft0, 576(s0)
-  flw ft1, 580(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 584(s0)
-  flw ft0, 268(s0)
-  fsw ft0, 588(s0)
-  flw ft0, 584(s0)
-  flw ft1, 588(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 592(s0)
-  flw ft0, 272(s0)
-  fsw ft0, 596(s0)
-  flw ft0, 276(s0)
-  fsw ft0, 600(s0)
-  flw ft0, 596(s0)
-  flw ft1, 600(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 604(s0)
-  flw ft0, 280(s0)
-  fsw ft0, 608(s0)
-  flw ft0, 604(s0)
-  flw ft1, 608(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 612(s0)
-  flw ft0, 284(s0)
-  fsw ft0, 616(s0)
-  flw ft0, 612(s0)
-  flw ft1, 616(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 620(s0)
-  flw ft0, 288(s0)
-  fsw ft0, 624(s0)
-  flw ft0, 292(s0)
-  fsw ft0, 628(s0)
-  flw ft0, 624(s0)
-  flw ft1, 628(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 632(s0)
-  flw ft0, 296(s0)
-  fsw ft0, 636(s0)
-  flw ft0, 632(s0)
-  flw ft1, 636(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 640(s0)
-  flw ft0, 300(s0)
-  fsw ft0, 644(s0)
-  flw ft0, 640(s0)
-  flw ft1, 644(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 648(s0)
-  flw ft0, 304(s0)
-  fsw ft0, 652(s0)
-  flw ft0, 308(s0)
-  fsw ft0, 656(s0)
-  flw ft0, 652(s0)
-  flw ft1, 656(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 660(s0)
-  flw ft0, 312(s0)
-  fsw ft0, 664(s0)
-  flw ft0, 660(s0)
-  flw ft1, 664(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 668(s0)
-  flw ft0, 316(s0)
-  fsw ft0, 672(s0)
-  flw ft0, 668(s0)
-  flw ft1, 672(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 676(s0)
-  addi a0, s0, 360
-  li a1, 0
-  li a2, 40
-  call memset
-  flw ft0, 424(s0)
-  addi t0, s0, 360
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 452(s0)
-  addi t0, s0, 360
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 480(s0)
-  addi t0, s0, 360
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 508(s0)
-  addi t0, s0, 360
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 536(s0)
-  addi t0, s0, 360
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 564(s0)
-  addi t0, s0, 360
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 592(s0)
-  addi t0, s0, 360
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 620(s0)
-  addi t0, s0, 360
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 648(s0)
-  addi t0, s0, 360
-  li t1, 8
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 676(s0)
-  addi t0, s0, 360
-  li t1, 9
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  li a0, 10
-  addi a1, s0, 360
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  call putfarray
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 724(s0)
-  addi t0, s0, 360
-  lw t1, 724(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 732(s0)
-  flw fa0, 732(s0)
-  ld ra, 928(s0)
-  addi sp, s0, 944
-  ld s0, 936(s0)
-  ret
-L1.if.else:
-  flw ft0, 164(s0)
-  fsw ft0, 736(s0)
-  flw ft0, 168(s0)
-  fsw ft0, 740(s0)
-  flw ft0, 172(s0)
-  fsw ft0, 744(s0)
-  flw ft0, 176(s0)
-  fsw ft0, 748(s0)
-  flw ft0, 180(s0)
-  fsw ft0, 752(s0)
-  flw ft0, 184(s0)
-  fsw ft0, 756(s0)
-  flw ft0, 188(s0)
-  fsw ft0, 760(s0)
-  flw ft0, 192(s0)
-  fsw ft0, 764(s0)
-  flw ft0, 196(s0)
-  fsw ft0, 768(s0)
-  flw ft0, 200(s0)
-  fsw ft0, 772(s0)
-  flw ft0, 204(s0)
-  fsw ft0, 776(s0)
-  flw ft0, 208(s0)
-  fsw ft0, 780(s0)
-  flw ft0, 212(s0)
-  fsw ft0, 784(s0)
-  flw ft0, 216(s0)
-  fsw ft0, 788(s0)
-  flw ft0, 220(s0)
-  fsw ft0, 792(s0)
-  flw ft0, 224(s0)
-  fsw ft0, 796(s0)
-  flw ft0, 228(s0)
-  fsw ft0, 800(s0)
-  flw ft0, 232(s0)
-  fsw ft0, 804(s0)
-  flw ft0, 236(s0)
-  fsw ft0, 808(s0)
-  flw ft0, 240(s0)
-  fsw ft0, 812(s0)
-  flw ft0, 244(s0)
-  fsw ft0, 816(s0)
-  flw ft0, 248(s0)
-  fsw ft0, 820(s0)
-  flw ft0, 252(s0)
-  fsw ft0, 824(s0)
-  flw ft0, 256(s0)
-  fsw ft0, 828(s0)
-  flw ft0, 260(s0)
-  fsw ft0, 832(s0)
-  flw ft0, 264(s0)
-  fsw ft0, 836(s0)
-  flw ft0, 268(s0)
-  fsw ft0, 840(s0)
-  flw ft0, 272(s0)
-  fsw ft0, 844(s0)
-  flw ft0, 276(s0)
-  fsw ft0, 848(s0)
-  flw ft0, 280(s0)
-  fsw ft0, 852(s0)
-  flw ft0, 284(s0)
-  fsw ft0, 856(s0)
-  flw ft0, 288(s0)
-  fsw ft0, 860(s0)
-  flw ft0, 292(s0)
-  fsw ft0, 864(s0)
-  flw ft0, 296(s0)
-  fsw ft0, 868(s0)
-  flw ft0, 300(s0)
-  fsw ft0, 872(s0)
-  flw ft0, 304(s0)
-  fsw ft0, 876(s0)
-  flw ft0, 308(s0)
-  fsw ft0, 880(s0)
-  flw ft0, 312(s0)
-  fsw ft0, 884(s0)
-  flw ft0, 316(s0)
-  fsw ft0, 888(s0)
-  flw ft0, 160(s0)
-  fsw ft0, 892(s0)
-  flw ft0, 164(s0)
-  fsw ft0, 896(s0)
-  flw ft0, 892(s0)
-  flw ft1, 896(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 900(s0)
-  flw ft0, 168(s0)
-  fsw ft0, 904(s0)
-  flw ft0, 900(s0)
-  flw ft1, 904(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 908(s0)
-  addi sp, sp, -256
-  flw fa0, 736(s0)
-  flw fa1, 740(s0)
-  flw fa2, 744(s0)
-  flw fa3, 748(s0)
-  flw fa4, 752(s0)
-  flw fa5, 756(s0)
-  flw fa6, 760(s0)
-  flw fa7, 764(s0)
-  add t4, sp, zero
-  flw ft0, 768(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 8
-  flw ft0, 772(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 16
-  flw ft0, 776(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 24
-  flw ft0, 780(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 32
-  flw ft0, 784(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 40
-  flw ft0, 788(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 48
-  flw ft0, 792(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 56
-  flw ft0, 796(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 64
-  flw ft0, 800(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 72
-  flw ft0, 804(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 80
-  flw ft0, 808(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 88
-  flw ft0, 812(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 96
-  flw ft0, 816(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 104
-  flw ft0, 820(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 112
-  flw ft0, 824(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 120
-  flw ft0, 828(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 128
-  flw ft0, 832(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 136
-  flw ft0, 836(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 144
-  flw ft0, 840(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 152
-  flw ft0, 844(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 160
-  flw ft0, 848(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 168
-  flw ft0, 852(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 176
-  flw ft0, 856(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 184
-  flw ft0, 860(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 192
-  flw ft0, 864(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 200
-  flw ft0, 868(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 208
-  flw ft0, 872(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 216
-  flw ft0, 876(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 224
-  flw ft0, 880(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 232
-  flw ft0, 884(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 240
-  flw ft0, 888(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 248
-  flw ft0, 908(s0)
-  fsw ft0, 0(t4)
-  call params_f40
-  addi sp, sp, 256
-  fsw fa0, 912(s0)
-  flw fa0, 912(s0)
-  ld ra, 928(s0)
-  addi sp, s0, 944
-  ld s0, 936(s0)
-  ret
-L2.if.end:
-  li t4, 0
-  sw t4, 916(s0)
-  flw fa0, 916(s0)
-  ld ra, 928(s0)
-  addi sp, s0, 944
-  ld s0, 936(s0)
-  ret
-.size params_f40, .-params_f40
-
-.global params_f40_i24
-.type params_f40_i24, @function
-params_f40_i24:
-  addi sp, sp, -1488
-  sd ra, 1472(sp)
-  sd s0, 1480(sp)
-  mv s0, sp
-  sw a0, 0(s0)
-  sw a1, 4(s0)
-  sw a2, 8(s0)
-  fsw fa3, 12(s0)
-  sw a4, 16(s0)
-  sw a5, 20(s0)
-  sw a6, 24(s0)
-  fsw fa7, 28(s0)
-  flw ft0, 1488(s0)
-  fsw ft0, 32(s0)
-  flw ft0, 1496(s0)
-  fsw ft0, 36(s0)
-  ld t0, 1504(s0)
-  sw t0, 40(s0)
-  flw ft0, 1512(s0)
-  fsw ft0, 44(s0)
-  flw ft0, 1520(s0)
-  fsw ft0, 48(s0)
-  ld t0, 1528(s0)
-  sw t0, 52(s0)
-  flw ft0, 1536(s0)
-  fsw ft0, 56(s0)
-  ld t0, 1544(s0)
-  sw t0, 60(s0)
-  flw ft0, 1552(s0)
-  fsw ft0, 64(s0)
-  flw ft0, 1560(s0)
-  fsw ft0, 68(s0)
-  flw ft0, 1568(s0)
-  fsw ft0, 72(s0)
-  flw ft0, 1576(s0)
-  fsw ft0, 76(s0)
-  flw ft0, 1584(s0)
-  fsw ft0, 80(s0)
-  flw ft0, 1592(s0)
-  fsw ft0, 84(s0)
-  ld t0, 1600(s0)
-  sw t0, 88(s0)
-  flw ft0, 1608(s0)
-  fsw ft0, 92(s0)
-  ld t0, 1616(s0)
-  sw t0, 96(s0)
-  ld t0, 1624(s0)
-  sw t0, 100(s0)
-  flw ft0, 1632(s0)
-  fsw ft0, 104(s0)
-  flw ft0, 1640(s0)
-  fsw ft0, 108(s0)
-  flw ft0, 1648(s0)
-  fsw ft0, 112(s0)
-  flw ft0, 1656(s0)
-  fsw ft0, 116(s0)
-  flw ft0, 1664(s0)
-  fsw ft0, 120(s0)
-  ld t0, 1672(s0)
-  sw t0, 124(s0)
-  flw ft0, 1680(s0)
-  fsw ft0, 128(s0)
-  ld t0, 1688(s0)
-  sw t0, 132(s0)
-  flw ft0, 1696(s0)
-  fsw ft0, 136(s0)
-  flw ft0, 1704(s0)
-  fsw ft0, 140(s0)
-  flw ft0, 1712(s0)
-  fsw ft0, 144(s0)
-  flw ft0, 1720(s0)
-  fsw ft0, 148(s0)
-  ld t0, 1728(s0)
-  sw t0, 152(s0)
-  ld t0, 1736(s0)
-  sw t0, 156(s0)
-  flw ft0, 1744(s0)
-  fsw ft0, 160(s0)
-  flw ft0, 1752(s0)
-  fsw ft0, 164(s0)
-  flw ft0, 1760(s0)
-  fsw ft0, 168(s0)
-  ld t0, 1768(s0)
-  sw t0, 172(s0)
-  flw ft0, 1776(s0)
-  fsw ft0, 176(s0)
-  ld t0, 1784(s0)
-  sw t0, 180(s0)
-  ld t0, 1792(s0)
-  sw t0, 184(s0)
-  flw ft0, 1800(s0)
-  fsw ft0, 188(s0)
-  flw ft0, 1808(s0)
-  fsw ft0, 192(s0)
-  flw ft0, 1816(s0)
-  fsw ft0, 196(s0)
-  flw ft0, 1824(s0)
-  fsw ft0, 200(s0)
-  ld t0, 1832(s0)
-  sw t0, 204(s0)
-  ld t0, 1840(s0)
-  sw t0, 208(s0)
-  ld t0, 1848(s0)
-  sw t0, 212(s0)
-  flw ft0, 1856(s0)
-  fsw ft0, 216(s0)
-  flw ft0, 1864(s0)
-  fsw ft0, 220(s0)
-  flw ft0, 1872(s0)
-  fsw ft0, 224(s0)
-  flw ft0, 1880(s0)
-  fsw ft0, 228(s0)
-  flw ft0, 1888(s0)
-  fsw ft0, 232(s0)
-  flw ft0, 1896(s0)
-  fsw ft0, 236(s0)
-  ld t0, 1904(s0)
-  sw t0, 240(s0)
-  flw ft0, 1912(s0)
-  fsw ft0, 244(s0)
-  ld t0, 1920(s0)
-  sw t0, 248(s0)
-  flw ft0, 1928(s0)
-  fsw ft0, 252(s0)
-  lw t0, 0(s0)
-  sw t0, 256(s0)
-  lw t0, 4(s0)
-  sw t0, 260(s0)
-  lw t0, 8(s0)
-  sw t0, 264(s0)
-  flw ft0, 12(s0)
-  fsw ft0, 268(s0)
-  lw t0, 16(s0)
-  sw t0, 272(s0)
-  lw t0, 20(s0)
-  sw t0, 276(s0)
-  lw t0, 24(s0)
-  sw t0, 280(s0)
-  flw ft0, 28(s0)
-  fsw ft0, 284(s0)
-  flw ft0, 32(s0)
-  fsw ft0, 288(s0)
-  flw ft0, 36(s0)
-  fsw ft0, 292(s0)
-  lw t0, 40(s0)
-  sw t0, 296(s0)
-  flw ft0, 44(s0)
-  fsw ft0, 300(s0)
-  flw ft0, 48(s0)
-  fsw ft0, 304(s0)
-  lw t0, 52(s0)
-  sw t0, 308(s0)
-  flw ft0, 56(s0)
-  fsw ft0, 312(s0)
-  lw t0, 60(s0)
-  sw t0, 316(s0)
-  flw ft0, 64(s0)
-  fsw ft0, 320(s0)
-  flw ft0, 68(s0)
-  fsw ft0, 324(s0)
-  flw ft0, 72(s0)
-  fsw ft0, 328(s0)
-  flw ft0, 76(s0)
-  fsw ft0, 332(s0)
-  flw ft0, 80(s0)
-  fsw ft0, 336(s0)
-  flw ft0, 84(s0)
-  fsw ft0, 340(s0)
-  lw t0, 88(s0)
-  sw t0, 344(s0)
-  flw ft0, 92(s0)
-  fsw ft0, 348(s0)
-  lw t0, 96(s0)
-  sw t0, 352(s0)
-  lw t0, 100(s0)
-  sw t0, 356(s0)
-  flw ft0, 104(s0)
-  fsw ft0, 360(s0)
-  flw ft0, 108(s0)
-  fsw ft0, 364(s0)
-  flw ft0, 112(s0)
-  fsw ft0, 368(s0)
-  flw ft0, 116(s0)
-  fsw ft0, 372(s0)
-  flw ft0, 120(s0)
-  fsw ft0, 376(s0)
-  lw t0, 124(s0)
-  sw t0, 380(s0)
-  flw ft0, 128(s0)
-  fsw ft0, 384(s0)
-  lw t0, 132(s0)
-  sw t0, 388(s0)
-  flw ft0, 136(s0)
-  fsw ft0, 392(s0)
-  flw ft0, 140(s0)
-  fsw ft0, 396(s0)
-  flw ft0, 144(s0)
-  fsw ft0, 400(s0)
-  flw ft0, 148(s0)
-  fsw ft0, 404(s0)
-  lw t0, 152(s0)
-  sw t0, 408(s0)
-  lw t0, 156(s0)
-  sw t0, 412(s0)
-  flw ft0, 160(s0)
-  fsw ft0, 416(s0)
-  flw ft0, 164(s0)
-  fsw ft0, 420(s0)
-  flw ft0, 168(s0)
-  fsw ft0, 424(s0)
-  lw t0, 172(s0)
-  sw t0, 428(s0)
-  flw ft0, 176(s0)
-  fsw ft0, 432(s0)
-  lw t0, 180(s0)
-  sw t0, 436(s0)
-  lw t0, 184(s0)
-  sw t0, 440(s0)
-  flw ft0, 188(s0)
-  fsw ft0, 444(s0)
-  flw ft0, 192(s0)
-  fsw ft0, 448(s0)
-  flw ft0, 196(s0)
-  fsw ft0, 452(s0)
-  flw ft0, 200(s0)
-  fsw ft0, 456(s0)
-  lw t0, 204(s0)
-  sw t0, 460(s0)
-  lw t0, 208(s0)
-  sw t0, 464(s0)
-  lw t0, 212(s0)
-  sw t0, 468(s0)
-  flw ft0, 216(s0)
-  fsw ft0, 472(s0)
-  flw ft0, 220(s0)
-  fsw ft0, 476(s0)
-  flw ft0, 224(s0)
-  fsw ft0, 480(s0)
-  flw ft0, 228(s0)
-  fsw ft0, 484(s0)
-  flw ft0, 232(s0)
-  fsw ft0, 488(s0)
-  flw ft0, 236(s0)
-  fsw ft0, 492(s0)
-  lw t0, 240(s0)
-  sw t0, 496(s0)
-  flw ft0, 244(s0)
-  fsw ft0, 500(s0)
-  lw t0, 248(s0)
-  sw t0, 504(s0)
-  flw ft0, 252(s0)
-  fsw ft0, 508(s0)
-  lw t0, 256(s0)
-  sw t0, 512(s0)
-  lw t0, 512(s0)
-  li t1, 0
-  sub t0, t0, t1
-  sltiu t1, t0, 1
-  xori t0, t1, 1
-  sw t0, 516(s0)
-  lw t0, 516(s0)
-  bnez t0, L3.if.then
-  j L4.if.else
-L3.if.then:
-  flw ft0, 424(s0)
-  fsw ft0, 560(s0)
-  flw ft0, 328(s0)
-  fsw ft0, 564(s0)
-  flw ft0, 560(s0)
-  flw ft1, 564(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 568(s0)
-  flw ft0, 500(s0)
-  fsw ft0, 572(s0)
-  flw ft0, 568(s0)
-  flw ft1, 572(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 576(s0)
-  flw ft0, 300(s0)
-  fsw ft0, 580(s0)
-  flw ft0, 576(s0)
-  flw ft1, 580(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 584(s0)
-  flw ft0, 268(s0)
-  fsw ft0, 588(s0)
-  flw ft0, 400(s0)
-  fsw ft0, 592(s0)
-  flw ft0, 588(s0)
-  flw ft1, 592(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 596(s0)
-  flw ft0, 340(s0)
-  fsw ft0, 600(s0)
-  flw ft0, 596(s0)
-  flw ft1, 600(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 604(s0)
-  flw ft0, 292(s0)
-  fsw ft0, 608(s0)
-  flw ft0, 604(s0)
-  flw ft1, 608(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 612(s0)
-  flw ft0, 284(s0)
-  fsw ft0, 616(s0)
-  flw ft0, 372(s0)
-  fsw ft0, 620(s0)
-  flw ft0, 616(s0)
-  flw ft1, 620(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 624(s0)
-  flw ft0, 420(s0)
-  fsw ft0, 628(s0)
-  flw ft0, 624(s0)
-  flw ft1, 628(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 632(s0)
-  flw ft0, 332(s0)
-  fsw ft0, 636(s0)
-  flw ft0, 632(s0)
-  flw ft1, 636(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 640(s0)
-  flw ft0, 324(s0)
-  fsw ft0, 644(s0)
-  flw ft0, 452(s0)
-  fsw ft0, 648(s0)
-  flw ft0, 644(s0)
-  flw ft1, 648(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 652(s0)
-  flw ft0, 416(s0)
-  fsw ft0, 656(s0)
-  flw ft0, 652(s0)
-  flw ft1, 656(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 660(s0)
-  flw ft0, 288(s0)
-  fsw ft0, 664(s0)
-  flw ft0, 660(s0)
-  flw ft1, 664(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 668(s0)
-  flw ft0, 396(s0)
-  fsw ft0, 672(s0)
-  flw ft0, 492(s0)
-  fsw ft0, 676(s0)
-  flw ft0, 672(s0)
-  flw ft1, 676(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 680(s0)
-  flw ft0, 472(s0)
-  fsw ft0, 684(s0)
-  flw ft0, 680(s0)
-  flw ft1, 684(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 688(s0)
-  flw ft0, 476(s0)
-  fsw ft0, 692(s0)
-  flw ft0, 688(s0)
-  flw ft1, 692(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 696(s0)
-  flw ft0, 360(s0)
-  fsw ft0, 700(s0)
-  flw ft0, 392(s0)
-  fsw ft0, 704(s0)
-  flw ft0, 700(s0)
-  flw ft1, 704(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 708(s0)
-  flw ft0, 480(s0)
-  fsw ft0, 712(s0)
-  flw ft0, 708(s0)
-  flw ft1, 712(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 716(s0)
-  flw ft0, 368(s0)
-  fsw ft0, 720(s0)
-  flw ft0, 716(s0)
-  flw ft1, 720(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 724(s0)
-  flw ft0, 448(s0)
-  fsw ft0, 728(s0)
-  flw ft0, 376(s0)
-  fsw ft0, 732(s0)
-  flw ft0, 728(s0)
-  flw ft1, 732(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 736(s0)
-  flw ft0, 484(s0)
-  fsw ft0, 740(s0)
-  flw ft0, 736(s0)
-  flw ft1, 740(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 744(s0)
-  flw ft0, 444(s0)
-  fsw ft0, 748(s0)
-  flw ft0, 744(s0)
-  flw ft1, 748(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 752(s0)
-  flw ft0, 304(s0)
-  fsw ft0, 756(s0)
-  flw ft0, 456(s0)
-  fsw ft0, 760(s0)
-  flw ft0, 756(s0)
-  flw ft1, 760(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 764(s0)
-  flw ft0, 320(s0)
-  fsw ft0, 768(s0)
-  flw ft0, 764(s0)
-  flw ft1, 768(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 772(s0)
-  flw ft0, 432(s0)
-  fsw ft0, 776(s0)
-  flw ft0, 772(s0)
-  flw ft1, 776(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 780(s0)
-  flw ft0, 348(s0)
-  fsw ft0, 784(s0)
-  flw ft0, 364(s0)
-  fsw ft0, 788(s0)
-  flw ft0, 784(s0)
-  flw ft1, 788(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 792(s0)
-  flw ft0, 404(s0)
-  fsw ft0, 796(s0)
-  flw ft0, 792(s0)
-  flw ft1, 796(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 800(s0)
-  flw ft0, 508(s0)
-  fsw ft0, 804(s0)
-  flw ft0, 800(s0)
-  flw ft1, 804(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 808(s0)
-  flw ft0, 488(s0)
-  fsw ft0, 812(s0)
-  flw ft0, 312(s0)
-  fsw ft0, 816(s0)
-  flw ft0, 812(s0)
-  flw ft1, 816(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 820(s0)
-  flw ft0, 336(s0)
-  fsw ft0, 824(s0)
-  flw ft0, 820(s0)
-  flw ft1, 824(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 828(s0)
-  flw ft0, 384(s0)
-  fsw ft0, 832(s0)
-  flw ft0, 828(s0)
-  flw ft1, 832(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 836(s0)
-  addi a0, s0, 520
-  li a1, 0
-  li a2, 40
-  call memset
-  flw ft0, 584(s0)
-  addi t0, s0, 520
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 612(s0)
-  addi t0, s0, 520
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 640(s0)
-  addi t0, s0, 520
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 668(s0)
-  addi t0, s0, 520
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 696(s0)
-  addi t0, s0, 520
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 724(s0)
-  addi t0, s0, 520
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 752(s0)
-  addi t0, s0, 520
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 780(s0)
-  addi t0, s0, 520
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 808(s0)
-  addi t0, s0, 520
-  li t1, 8
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 836(s0)
-  addi t0, s0, 520
-  li t1, 9
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  lw t0, 308(s0)
-  sw t0, 928(s0)
-  lw t0, 272(s0)
-  sw t0, 932(s0)
-  lw t0, 928(s0)
-  lw t1, 932(s0)
-  add t0, t0, t1
-  sw t0, 936(s0)
-  lw t0, 260(s0)
-  sw t0, 940(s0)
-  lw t0, 936(s0)
-  lw t1, 940(s0)
-  add t0, t0, t1
-  sw t0, 944(s0)
-  lw t0, 460(s0)
-  sw t0, 948(s0)
-  lw t0, 276(s0)
-  sw t0, 952(s0)
-  lw t0, 948(s0)
-  lw t1, 952(s0)
-  add t0, t0, t1
-  sw t0, 956(s0)
-  lw t0, 280(s0)
-  sw t0, 960(s0)
-  lw t0, 956(s0)
-  lw t1, 960(s0)
-  add t0, t0, t1
-  sw t0, 964(s0)
-  lw t0, 264(s0)
-  sw t0, 968(s0)
-  lw t0, 344(s0)
-  sw t0, 972(s0)
-  lw t0, 968(s0)
-  lw t1, 972(s0)
-  add t0, t0, t1
-  sw t0, 976(s0)
-  lw t0, 380(s0)
-  sw t0, 980(s0)
-  lw t0, 976(s0)
-  lw t1, 980(s0)
-  add t0, t0, t1
-  sw t0, 984(s0)
-  lw t0, 412(s0)
-  sw t0, 988(s0)
-  lw t0, 352(s0)
-  sw t0, 992(s0)
-  lw t0, 988(s0)
-  lw t1, 992(s0)
-  add t0, t0, t1
-  sw t0, 996(s0)
-  lw t0, 436(s0)
-  sw t0, 1000(s0)
-  lw t0, 996(s0)
-  lw t1, 1000(s0)
-  add t0, t0, t1
-  sw t0, 1004(s0)
-  lw t0, 428(s0)
-  sw t0, 1008(s0)
-  lw t0, 356(s0)
-  sw t0, 1012(s0)
-  lw t0, 1008(s0)
-  lw t1, 1012(s0)
-  add t0, t0, t1
-  sw t0, 1016(s0)
-  lw t0, 504(s0)
-  sw t0, 1020(s0)
-  lw t0, 1016(s0)
-  lw t1, 1020(s0)
-  add t0, t0, t1
-  sw t0, 1024(s0)
-  lw t0, 496(s0)
-  sw t0, 1028(s0)
-  lw t0, 440(s0)
-  sw t0, 1032(s0)
-  lw t0, 1028(s0)
-  lw t1, 1032(s0)
-  add t0, t0, t1
-  sw t0, 1036(s0)
-  lw t0, 388(s0)
-  sw t0, 1040(s0)
-  lw t0, 1036(s0)
-  lw t1, 1040(s0)
-  add t0, t0, t1
-  sw t0, 1044(s0)
-  lw t0, 408(s0)
-  sw t0, 1048(s0)
-  lw t0, 316(s0)
-  sw t0, 1052(s0)
-  lw t0, 1048(s0)
-  lw t1, 1052(s0)
-  add t0, t0, t1
-  sw t0, 1056(s0)
-  lw t0, 468(s0)
-  sw t0, 1060(s0)
-  lw t0, 1056(s0)
-  lw t1, 1060(s0)
-  add t0, t0, t1
-  sw t0, 1064(s0)
-  lw t0, 464(s0)
-  sw t0, 1068(s0)
-  lw t0, 296(s0)
-  sw t0, 1072(s0)
-  lw t0, 1068(s0)
-  lw t1, 1072(s0)
-  add t0, t0, t1
-  sw t0, 1076(s0)
-  lw t0, 256(s0)
-  sw t0, 1080(s0)
-  lw t0, 1076(s0)
-  lw t1, 1080(s0)
-  add t0, t0, t1
-  sw t0, 1084(s0)
-  addi a0, s0, 896
-  li a1, 0
-  li a2, 32
-  call memset
-  lw t2, 944(s0)
-  addi t0, s0, 896
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 964(s0)
-  addi t0, s0, 896
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 984(s0)
-  addi t0, s0, 896
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1004(s0)
-  addi t0, s0, 896
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1024(s0)
-  addi t0, s0, 896
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1044(s0)
-  addi t0, s0, 896
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1064(s0)
-  addi t0, s0, 896
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1084(s0)
-  addi t0, s0, 896
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li a0, 10
-  addi a1, s0, 520
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  call putfarray
-  li a0, 8
-  addi a1, s0, 896
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  call putarray
-  li t0, 0
-  sw t0, 1128(s0)
-  j L6.while.cond
-L6.while.cond:
-  lw t0, 1128(s0)
-  sw t0, 1132(s0)
-  lw t0, 1132(s0)
-  li t1, 8
-  slt t0, t0, t1
-  sw t0, 1136(s0)
-  lw t0, 1136(s0)
-  bnez t0, L7.while.body
-  j L8.while.end
-L7.while.body:
-  lw t0, 1128(s0)
-  sw t0, 1140(s0)
-  addi t0, s0, 896
-  lw t1, 1140(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1148(s0)
-  lw t0, 1128(s0)
-  sw t0, 1152(s0)
-  addi t0, s0, 520
-  lw t1, 1152(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1160(s0)
-  lw t0, 1148(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1164(s0)
-  flw ft0, 1164(s0)
-  flw ft1, 1160(s0)
-  fsub.s ft0, ft0, ft1
-  fsw ft0, 1168(s0)
-  lw t0, 1128(s0)
-  sw t0, 1172(s0)
-  flw ft0, 1168(s0)
-  fcvt.w.s t0, ft0, rtz
-  sw t0, 1180(s0)
-  lw t2, 1180(s0)
-  addi t0, s0, 896
-  lw t1, 1172(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t0, 1128(s0)
-  sw t0, 1184(s0)
-  lw t0, 1184(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1188(s0)
-  lw t0, 1188(s0)
-  sw t0, 1128(s0)
-  j L6.while.cond
-L8.while.end:
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1192(s0)
-  addi t0, s0, 896
-  lw t1, 1192(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1200(s0)
-  lw t0, 1200(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1204(s0)
-  flw fa0, 1204(s0)
-  ld ra, 1472(s0)
-  addi sp, s0, 1488
-  ld s0, 1480(s0)
-  ret
-L4.if.else:
-  lw t0, 272(s0)
-  sw t0, 1208(s0)
-  lw t0, 260(s0)
-  sw t0, 1212(s0)
-  lw t0, 264(s0)
-  sw t0, 1216(s0)
-  flw ft0, 268(s0)
-  fsw ft0, 1220(s0)
-  lw t0, 272(s0)
-  sw t0, 1224(s0)
-  lw t0, 276(s0)
-  sw t0, 1228(s0)
-  lw t0, 280(s0)
-  sw t0, 1232(s0)
-  flw ft0, 284(s0)
-  fsw ft0, 1236(s0)
-  flw ft0, 288(s0)
-  fsw ft0, 1240(s0)
-  flw ft0, 292(s0)
-  fsw ft0, 1244(s0)
-  lw t0, 296(s0)
-  sw t0, 1248(s0)
-  flw ft0, 300(s0)
-  fsw ft0, 1252(s0)
-  flw ft0, 304(s0)
-  fsw ft0, 1256(s0)
-  lw t0, 308(s0)
-  sw t0, 1260(s0)
-  flw ft0, 312(s0)
-  fsw ft0, 1264(s0)
-  lw t0, 316(s0)
-  sw t0, 1268(s0)
-  flw ft0, 320(s0)
-  fsw ft0, 1272(s0)
-  flw ft0, 324(s0)
-  fsw ft0, 1276(s0)
-  flw ft0, 328(s0)
-  fsw ft0, 1280(s0)
-  flw ft0, 332(s0)
-  fsw ft0, 1284(s0)
-  flw ft0, 336(s0)
-  fsw ft0, 1288(s0)
-  flw ft0, 340(s0)
-  fsw ft0, 1292(s0)
-  lw t0, 344(s0)
-  sw t0, 1296(s0)
-  flw ft0, 348(s0)
-  fsw ft0, 1300(s0)
-  lw t0, 352(s0)
-  sw t0, 1304(s0)
-  lw t0, 356(s0)
-  sw t0, 1308(s0)
-  flw ft0, 360(s0)
-  fsw ft0, 1312(s0)
-  flw ft0, 364(s0)
-  fsw ft0, 1316(s0)
-  flw ft0, 368(s0)
-  fsw ft0, 1320(s0)
-  flw ft0, 372(s0)
-  fsw ft0, 1324(s0)
-  flw ft0, 376(s0)
-  fsw ft0, 1328(s0)
-  lw t0, 380(s0)
-  sw t0, 1332(s0)
-  flw ft0, 384(s0)
-  fsw ft0, 1336(s0)
-  lw t0, 388(s0)
-  sw t0, 1340(s0)
-  flw ft0, 392(s0)
-  fsw ft0, 1344(s0)
-  flw ft0, 396(s0)
-  fsw ft0, 1348(s0)
-  flw ft0, 400(s0)
-  fsw ft0, 1352(s0)
-  flw ft0, 404(s0)
-  fsw ft0, 1356(s0)
-  lw t0, 408(s0)
-  sw t0, 1360(s0)
-  lw t0, 412(s0)
-  sw t0, 1364(s0)
-  flw ft0, 416(s0)
-  fsw ft0, 1368(s0)
-  flw ft0, 420(s0)
-  fsw ft0, 1372(s0)
-  flw ft0, 424(s0)
-  fsw ft0, 1376(s0)
-  lw t0, 428(s0)
-  sw t0, 1380(s0)
-  flw ft0, 432(s0)
-  fsw ft0, 1384(s0)
-  lw t0, 436(s0)
-  sw t0, 1388(s0)
-  lw t0, 440(s0)
-  sw t0, 1392(s0)
-  flw ft0, 444(s0)
-  fsw ft0, 1396(s0)
-  flw ft0, 448(s0)
-  fsw ft0, 1400(s0)
-  flw ft0, 452(s0)
-  fsw ft0, 1404(s0)
-  flw ft0, 456(s0)
-  fsw ft0, 1408(s0)
-  lw t0, 460(s0)
-  sw t0, 1412(s0)
-  lw t0, 464(s0)
-  sw t0, 1416(s0)
-  lw t0, 468(s0)
-  sw t0, 1420(s0)
-  flw ft0, 472(s0)
-  fsw ft0, 1424(s0)
-  flw ft0, 476(s0)
-  fsw ft0, 1428(s0)
-  flw ft0, 480(s0)
-  fsw ft0, 1432(s0)
-  flw ft0, 484(s0)
-  fsw ft0, 1436(s0)
-  flw ft0, 488(s0)
-  fsw ft0, 1440(s0)
-  flw ft0, 492(s0)
-  fsw ft0, 1444(s0)
-  lw t0, 496(s0)
-  sw t0, 1448(s0)
-  flw ft0, 500(s0)
-  fsw ft0, 1452(s0)
-  lw t0, 504(s0)
-  sw t0, 1456(s0)
-  flw ft0, 508(s0)
-  fsw ft0, 1460(s0)
-  addi sp, sp, -448
-  lw a0, 1208(s0)
-  lw a1, 1212(s0)
-  lw a2, 1216(s0)
-  flw fa3, 1220(s0)
-  lw a4, 1224(s0)
-  lw a5, 1228(s0)
-  lw a6, 1232(s0)
-  flw fa7, 1236(s0)
-  add t4, sp, zero
-  flw ft0, 1240(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 8
-  flw ft0, 1244(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 16
-  lw t0, 1248(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  flw ft0, 1252(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 32
-  flw ft0, 1256(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 40
-  lw t0, 1260(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  flw ft0, 1264(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 56
-  lw t0, 1268(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  flw ft0, 1272(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 72
-  flw ft0, 1276(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 80
-  flw ft0, 1280(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 88
-  flw ft0, 1284(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 96
-  flw ft0, 1288(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 104
-  flw ft0, 1292(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 112
-  lw t0, 1296(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 120
-  flw ft0, 1300(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 128
-  lw t0, 1304(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 136
-  lw t0, 1308(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 144
-  flw ft0, 1312(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 152
-  flw ft0, 1316(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 160
-  flw ft0, 1320(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 168
-  flw ft0, 1324(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 176
-  flw ft0, 1328(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 184
-  lw t0, 1332(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 192
-  flw ft0, 1336(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 200
-  lw t0, 1340(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 208
-  flw ft0, 1344(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 216
-  flw ft0, 1348(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 224
-  flw ft0, 1352(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 232
-  flw ft0, 1356(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 240
-  lw t0, 1360(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 248
-  lw t0, 1364(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 256
-  flw ft0, 1368(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 264
-  flw ft0, 1372(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 272
-  flw ft0, 1376(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 280
-  lw t0, 1380(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 288
-  flw ft0, 1384(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 296
-  lw t0, 1388(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 304
-  lw t0, 1392(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 312
-  flw ft0, 1396(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 320
-  flw ft0, 1400(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 328
-  flw ft0, 1404(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 336
-  flw ft0, 1408(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 344
-  lw t0, 1412(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 352
-  lw t0, 1416(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 360
-  lw t0, 1420(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 368
-  flw ft0, 1424(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 376
-  flw ft0, 1428(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 384
-  flw ft0, 1432(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 392
-  flw ft0, 1436(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 400
-  flw ft0, 1440(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 408
-  flw ft0, 1444(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 416
-  lw t0, 1448(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 424
-  flw ft0, 1452(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 432
-  lw t0, 1456(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 440
-  flw ft0, 1460(s0)
-  fsw ft0, 0(t4)
-  call params_f40_i24
-  addi sp, sp, 448
-  fsw fa0, 1464(s0)
-  flw fa0, 1464(s0)
-  ld ra, 1472(s0)
-  addi sp, s0, 1488
-  ld s0, 1480(s0)
-  ret
-L5.if.end:
-  li t4, 0
-  sw t4, 1468(s0)
-  flw fa0, 1468(s0)
-  ld ra, 1472(s0)
-  addi sp, s0, 1488
-  ld s0, 1480(s0)
-  ret
-.size params_f40_i24, .-params_f40_i24
-
-.global params_fa40
-.type params_fa40, @function
-params_fa40:
-  addi sp, sp, -1104
-  sd ra, 1088(sp)
-  sd s0, 1096(sp)
-  mv s0, sp
-  sd a0, 0(s0)
-  sd a1, 8(s0)
-  sd a2, 16(s0)
-  sd a3, 24(s0)
-  sd a4, 32(s0)
-  sd a5, 40(s0)
-  sd a6, 48(s0)
-  sd a7, 56(s0)
-  ld t0, 1104(s0)
-  sd t0, 64(s0)
-  ld t0, 1112(s0)
-  sd t0, 72(s0)
-  ld t0, 1120(s0)
-  sd t0, 80(s0)
-  ld t0, 1128(s0)
-  sd t0, 88(s0)
-  ld t0, 1136(s0)
-  sd t0, 96(s0)
-  ld t0, 1144(s0)
-  sd t0, 104(s0)
-  ld t0, 1152(s0)
-  sd t0, 112(s0)
-  ld t0, 1160(s0)
-  sd t0, 120(s0)
-  ld t0, 1168(s0)
-  sd t0, 128(s0)
-  ld t0, 1176(s0)
-  sd t0, 136(s0)
-  ld t0, 1184(s0)
-  sd t0, 144(s0)
-  ld t0, 1192(s0)
-  sd t0, 152(s0)
-  ld t0, 1200(s0)
-  sd t0, 160(s0)
-  ld t0, 1208(s0)
-  sd t0, 168(s0)
-  ld t0, 1216(s0)
-  sd t0, 176(s0)
-  ld t0, 1224(s0)
-  sd t0, 184(s0)
-  ld t0, 1232(s0)
-  sd t0, 192(s0)
-  ld t0, 1240(s0)
-  sd t0, 200(s0)
-  ld t0, 1248(s0)
-  sd t0, 208(s0)
-  ld t0, 1256(s0)
-  sd t0, 216(s0)
-  ld t0, 1264(s0)
-  sd t0, 224(s0)
-  ld t0, 1272(s0)
-  sd t0, 232(s0)
-  ld t0, 1280(s0)
-  sd t0, 240(s0)
-  ld t0, 1288(s0)
-  sd t0, 248(s0)
-  ld t0, 1296(s0)
-  sd t0, 256(s0)
-  ld t0, 1304(s0)
-  sd t0, 264(s0)
-  ld t0, 1312(s0)
-  sd t0, 272(s0)
-  ld t0, 1320(s0)
-  sd t0, 280(s0)
-  ld t0, 1328(s0)
-  sd t0, 288(s0)
-  ld t0, 1336(s0)
-  sd t0, 296(s0)
-  ld t0, 1344(s0)
-  sd t0, 304(s0)
-  ld t0, 1352(s0)
-  sd t0, 312(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 360(s0)
-  ld t0, 0(s0)
-  lw t1, 360(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 368(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 372(s0)
-  ld t0, 8(s0)
-  lw t1, 372(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 380(s0)
-  flw ft0, 368(s0)
-  flw ft1, 380(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 384(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 388(s0)
-  ld t0, 16(s0)
-  lw t1, 388(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 396(s0)
-  flw ft0, 384(s0)
-  flw ft1, 396(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 400(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 404(s0)
-  ld t0, 24(s0)
-  lw t1, 404(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 412(s0)
-  flw ft0, 400(s0)
-  flw ft1, 412(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 416(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 420(s0)
-  ld t0, 32(s0)
-  lw t1, 420(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 428(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 432(s0)
-  ld t0, 40(s0)
-  lw t1, 432(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 440(s0)
-  flw ft0, 428(s0)
-  flw ft1, 440(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 444(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 448(s0)
-  ld t0, 48(s0)
-  lw t1, 448(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 456(s0)
-  flw ft0, 444(s0)
-  flw ft1, 456(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 460(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 464(s0)
-  ld t0, 56(s0)
-  lw t1, 464(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 472(s0)
-  flw ft0, 460(s0)
-  flw ft1, 472(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 476(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 480(s0)
-  ld t0, 64(s0)
-  lw t1, 480(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 488(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 492(s0)
-  ld t0, 72(s0)
-  lw t1, 492(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 500(s0)
-  flw ft0, 488(s0)
-  flw ft1, 500(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 504(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 508(s0)
-  ld t0, 80(s0)
-  lw t1, 508(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 516(s0)
-  flw ft0, 504(s0)
-  flw ft1, 516(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 520(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 524(s0)
-  ld t0, 88(s0)
-  lw t1, 524(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 532(s0)
-  flw ft0, 520(s0)
-  flw ft1, 532(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 536(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 540(s0)
-  ld t0, 96(s0)
-  lw t1, 540(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 548(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 552(s0)
-  ld t0, 104(s0)
-  lw t1, 552(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 560(s0)
-  flw ft0, 548(s0)
-  flw ft1, 560(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 564(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 568(s0)
-  ld t0, 112(s0)
-  lw t1, 568(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 576(s0)
-  flw ft0, 564(s0)
-  flw ft1, 576(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 580(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 584(s0)
-  ld t0, 120(s0)
-  lw t1, 584(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 592(s0)
-  flw ft0, 580(s0)
-  flw ft1, 592(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 596(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 600(s0)
-  ld t0, 128(s0)
-  lw t1, 600(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 608(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 612(s0)
-  ld t0, 136(s0)
-  lw t1, 612(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 620(s0)
-  flw ft0, 608(s0)
-  flw ft1, 620(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 624(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 628(s0)
-  ld t0, 144(s0)
-  lw t1, 628(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 636(s0)
-  flw ft0, 624(s0)
-  flw ft1, 636(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 640(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 644(s0)
-  ld t0, 152(s0)
-  lw t1, 644(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 652(s0)
-  flw ft0, 640(s0)
-  flw ft1, 652(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 656(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 660(s0)
-  ld t0, 160(s0)
-  lw t1, 660(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 668(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 672(s0)
-  ld t0, 168(s0)
-  lw t1, 672(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 680(s0)
-  flw ft0, 668(s0)
-  flw ft1, 680(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 684(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 688(s0)
-  ld t0, 176(s0)
-  lw t1, 688(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 696(s0)
-  flw ft0, 684(s0)
-  flw ft1, 696(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 700(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 704(s0)
-  ld t0, 184(s0)
-  lw t1, 704(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 712(s0)
-  flw ft0, 700(s0)
-  flw ft1, 712(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 716(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 720(s0)
-  ld t0, 192(s0)
-  lw t1, 720(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 728(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 732(s0)
-  ld t0, 200(s0)
-  lw t1, 732(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 740(s0)
-  flw ft0, 728(s0)
-  flw ft1, 740(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 744(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 748(s0)
-  ld t0, 208(s0)
-  lw t1, 748(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 756(s0)
-  flw ft0, 744(s0)
-  flw ft1, 756(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 760(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 764(s0)
-  ld t0, 216(s0)
-  lw t1, 764(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 772(s0)
-  flw ft0, 760(s0)
-  flw ft1, 772(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 776(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 780(s0)
-  ld t0, 224(s0)
-  lw t1, 780(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 788(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 792(s0)
-  ld t0, 232(s0)
-  lw t1, 792(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 800(s0)
-  flw ft0, 788(s0)
-  flw ft1, 800(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 804(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 808(s0)
-  ld t0, 240(s0)
-  lw t1, 808(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 816(s0)
-  flw ft0, 804(s0)
-  flw ft1, 816(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 820(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 824(s0)
-  ld t0, 248(s0)
-  lw t1, 824(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 832(s0)
-  flw ft0, 820(s0)
-  flw ft1, 832(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 836(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 840(s0)
-  ld t0, 256(s0)
-  lw t1, 840(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 848(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 852(s0)
-  ld t0, 264(s0)
-  lw t1, 852(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 860(s0)
-  flw ft0, 848(s0)
-  flw ft1, 860(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 864(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 868(s0)
-  ld t0, 272(s0)
-  lw t1, 868(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 876(s0)
-  flw ft0, 864(s0)
-  flw ft1, 876(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 880(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 884(s0)
-  ld t0, 280(s0)
-  lw t1, 884(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 892(s0)
-  flw ft0, 880(s0)
-  flw ft1, 892(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 896(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 900(s0)
-  ld t0, 288(s0)
-  lw t1, 900(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 908(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 912(s0)
-  ld t0, 296(s0)
-  lw t1, 912(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 920(s0)
-  flw ft0, 908(s0)
-  flw ft1, 920(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 924(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 928(s0)
-  ld t0, 304(s0)
-  lw t1, 928(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 936(s0)
-  flw ft0, 924(s0)
-  flw ft1, 936(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 940(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 944(s0)
-  ld t0, 312(s0)
-  lw t1, 944(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 952(s0)
-  flw ft0, 940(s0)
-  flw ft1, 952(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 956(s0)
-  addi a0, s0, 320
-  li a1, 0
-  li a2, 40
-  call memset
-  flw ft0, 416(s0)
-  addi t0, s0, 320
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 476(s0)
-  addi t0, s0, 320
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 536(s0)
-  addi t0, s0, 320
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 596(s0)
-  addi t0, s0, 320
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 656(s0)
-  addi t0, s0, 320
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 716(s0)
-  addi t0, s0, 320
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 776(s0)
-  addi t0, s0, 320
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 836(s0)
-  addi t0, s0, 320
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 896(s0)
-  addi t0, s0, 320
-  li t1, 8
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 956(s0)
-  addi t0, s0, 320
-  li t1, 9
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1000(s0)
-  ld t0, 312(s0)
-  lw t1, 1000(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1008(s0)
-  li t0, 0
-  fcvt.s.w ft0, t0
-  fsw ft0, 1012(s0)
-  flw ft0, 1008(s0)
-  flw ft1, 1012(s0)
-  feq.s t0, ft0, ft1
-  xori t0, t0, 1
-  sw t0, 1016(s0)
-  lw t0, 1016(s0)
-  sw t0, 1020(s0)
-  lw t0, 1020(s0)
-  li t1, 0
-  sub t0, t0, t1
-  sltiu t1, t0, 1
-  xori t0, t1, 1
-  sw t0, 1024(s0)
-  lw t0, 1024(s0)
-  sw t0, 1028(s0)
-  lw t0, 1028(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1032(s0)
-  flw ft0, 1032(s0)
-  li t4, 0
-  sw t4, 1040(s0)
-  flw ft1, 1040(s0)
-  feq.s t0, ft0, ft1
-  xori t0, t0, 1
-  sw t0, 1036(s0)
-  lw t0, 1036(s0)
-  sw t0, 1044(s0)
-  lw t0, 1044(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1048(s0)
-  flw ft0, 1048(s0)
-  li t4, 0
-  sw t4, 1056(s0)
-  flw ft1, 1056(s0)
-  feq.s t0, ft0, ft1
-  xori t0, t0, 1
-  sw t0, 1052(s0)
-  lw t0, 1052(s0)
-  bnez t0, L9.if.then
-  j L10.if.else
-L9.if.then:
-  li a0, 10
-  addi a1, s0, 320
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  call putfarray
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1064(s0)
-  addi t0, s0, 320
-  lw t1, 1064(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1072(s0)
-  flw fa0, 1072(s0)
-  ld ra, 1088(s0)
-  addi sp, s0, 1104
-  ld s0, 1096(s0)
-  ret
-L10.if.else:
-  addi sp, sp, -256
-  ld a0, 8(s0)
-  ld a1, 16(s0)
-  ld a2, 24(s0)
-  ld a3, 32(s0)
-  ld a4, 40(s0)
-  ld a5, 48(s0)
-  ld a6, 56(s0)
-  ld a7, 64(s0)
-  add t4, sp, zero
-  ld t0, 72(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 8
-  ld t0, 80(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 16
-  ld t0, 88(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  ld t0, 96(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 32
-  ld t0, 104(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 40
-  ld t0, 112(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  ld t0, 120(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 56
-  ld t0, 128(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  ld t0, 136(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 72
-  ld t0, 144(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 80
-  ld t0, 152(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 88
-  ld t0, 160(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 96
-  ld t0, 168(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 104
-  ld t0, 176(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 112
-  ld t0, 184(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 120
-  ld t0, 192(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 128
-  ld t0, 200(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 136
-  ld t0, 208(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 144
-  ld t0, 216(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 152
-  ld t0, 224(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 160
-  ld t0, 232(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 168
-  ld t0, 240(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 176
-  ld t0, 248(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 184
-  ld t0, 256(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 192
-  ld t0, 264(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 200
-  ld t0, 272(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 208
-  ld t0, 280(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 216
-  ld t0, 288(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 224
-  ld t0, 296(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 232
-  ld t0, 304(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 240
-  ld t0, 312(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 248
-  addi t0, s0, 320
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  call params_fa40
-  addi sp, sp, 256
-  fsw fa0, 1080(s0)
-  flw fa0, 1080(s0)
-  ld ra, 1088(s0)
-  addi sp, s0, 1104
-  ld s0, 1096(s0)
-  ret
-L11.if.end:
-  li t4, 0
-  sw t4, 1084(s0)
-  flw fa0, 1084(s0)
-  ld ra, 1088(s0)
-  addi sp, s0, 1104
-  ld s0, 1096(s0)
-  ret
-.size params_fa40, .-params_fa40
-
-.global params_mix
-.type params_mix, @function
-params_mix:
-  addi sp, sp, -1712
-  sd ra, 1696(sp)
-  sd s0, 1704(sp)
-  mv s0, sp
-  fsw fa0, 0(s0)
-  sd a1, 8(s0)
-  sw a2, 16(s0)
-  sd a3, 24(s0)
-  fsw fa4, 32(s0)
-  sw a5, 36(s0)
-  fsw fa6, 40(s0)
-  fsw fa7, 44(s0)
-  ld t0, 1712(s0)
-  sd t0, 48(s0)
-  ld t0, 1720(s0)
-  sd t0, 56(s0)
-  ld t0, 1728(s0)
-  sw t0, 64(s0)
-  ld t0, 1736(s0)
-  sw t0, 68(s0)
-  ld t0, 1744(s0)
-  sd t0, 72(s0)
-  ld t0, 1752(s0)
-  sd t0, 80(s0)
-  ld t0, 1760(s0)
-  sd t0, 88(s0)
-  ld t0, 1768(s0)
-  sw t0, 96(s0)
-  ld t0, 1776(s0)
-  sd t0, 104(s0)
-  ld t0, 1784(s0)
-  sd t0, 112(s0)
-  flw ft0, 1792(s0)
-  fsw ft0, 120(s0)
-  flw ft0, 1800(s0)
-  fsw ft0, 124(s0)
-  flw ft0, 1808(s0)
-  fsw ft0, 128(s0)
-  ld t0, 1816(s0)
-  sd t0, 136(s0)
-  ld t0, 1824(s0)
-  sw t0, 144(s0)
-  flw ft0, 1832(s0)
-  fsw ft0, 148(s0)
-  flw ft0, 1840(s0)
-  fsw ft0, 152(s0)
-  flw ft0, 1848(s0)
-  fsw ft0, 156(s0)
-  ld t0, 1856(s0)
-  sd t0, 160(s0)
-  ld t0, 1864(s0)
-  sd t0, 168(s0)
-  ld t0, 1872(s0)
-  sd t0, 176(s0)
-  ld t0, 1880(s0)
-  sd t0, 184(s0)
-  ld t0, 1888(s0)
-  sd t0, 192(s0)
-  flw ft0, 1896(s0)
-  fsw ft0, 200(s0)
-  flw ft0, 1904(s0)
-  fsw ft0, 204(s0)
-  ld t0, 1912(s0)
-  sd t0, 208(s0)
-  ld t0, 1920(s0)
-  sw t0, 216(s0)
-  ld t0, 1928(s0)
-  sd t0, 224(s0)
-  ld t0, 1936(s0)
-  sd t0, 232(s0)
-  flw ft0, 1944(s0)
-  fsw ft0, 240(s0)
-  flw ft0, 1952(s0)
-  fsw ft0, 244(s0)
-  ld t0, 1960(s0)
-  sd t0, 248(s0)
-  ld t0, 1968(s0)
-  sd t0, 256(s0)
-  ld t0, 1976(s0)
-  sw t0, 264(s0)
-  ld t0, 1984(s0)
-  sw t0, 268(s0)
-  flw ft0, 1992(s0)
-  fsw ft0, 272(s0)
-  flw ft0, 2000(s0)
-  fsw ft0, 276(s0)
-  ld t0, 2008(s0)
-  sd t0, 280(s0)
-  ld t0, 2016(s0)
-  sw t0, 288(s0)
-  ld t0, 2024(s0)
-  sd t0, 296(s0)
-  ld t0, 2032(s0)
-  sw t0, 304(s0)
-  ld t0, 2040(s0)
-  sd t0, 312(s0)
-  li t4, 2048
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sd t0, 320(s0)
-  li t4, 2056
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 328(s0)
-  li t4, 2064
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 332(s0)
-  li t4, 2072
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sd t0, 336(s0)
-  li t4, 2080
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sw t0, 344(s0)
-  li t4, 2088
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sd t0, 352(s0)
-  li t4, 2096
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sd t0, 360(s0)
-  li t4, 2104
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 368(s0)
-  li t4, 2112
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sw t0, 372(s0)
-  li t4, 2120
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 376(s0)
-  li t4, 2128
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sd t0, 384(s0)
-  li t4, 2136
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sd t0, 392(s0)
-  li t4, 2144
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 400(s0)
-  li t4, 2152
-  add t4, s0, t4
-  ld t0, 0(t4)
-  sw t0, 404(s0)
-  flw ft0, 0(s0)
-  fsw ft0, 408(s0)
-  lw t0, 16(s0)
-  sw t0, 412(s0)
-  flw ft0, 32(s0)
-  fsw ft0, 416(s0)
-  lw t0, 36(s0)
-  sw t0, 420(s0)
-  flw ft0, 40(s0)
-  fsw ft0, 424(s0)
-  flw ft0, 44(s0)
-  fsw ft0, 428(s0)
-  lw t0, 64(s0)
-  sw t0, 432(s0)
-  lw t0, 68(s0)
-  sw t0, 436(s0)
-  lw t0, 96(s0)
-  sw t0, 440(s0)
-  flw ft0, 120(s0)
-  fsw ft0, 444(s0)
-  flw ft0, 124(s0)
-  fsw ft0, 448(s0)
-  flw ft0, 128(s0)
-  fsw ft0, 452(s0)
-  lw t0, 144(s0)
-  sw t0, 456(s0)
-  flw ft0, 148(s0)
-  fsw ft0, 460(s0)
-  flw ft0, 152(s0)
-  fsw ft0, 464(s0)
-  flw ft0, 156(s0)
-  fsw ft0, 468(s0)
-  flw ft0, 200(s0)
-  fsw ft0, 472(s0)
-  flw ft0, 204(s0)
-  fsw ft0, 476(s0)
-  lw t0, 216(s0)
-  sw t0, 480(s0)
-  flw ft0, 240(s0)
-  fsw ft0, 484(s0)
-  flw ft0, 244(s0)
-  fsw ft0, 488(s0)
-  lw t0, 264(s0)
-  sw t0, 492(s0)
-  lw t0, 268(s0)
-  sw t0, 496(s0)
-  flw ft0, 272(s0)
-  fsw ft0, 500(s0)
-  flw ft0, 276(s0)
-  fsw ft0, 504(s0)
-  lw t0, 288(s0)
-  sw t0, 508(s0)
-  lw t0, 304(s0)
-  sw t0, 512(s0)
-  flw ft0, 328(s0)
-  fsw ft0, 516(s0)
-  flw ft0, 332(s0)
-  fsw ft0, 520(s0)
-  lw t0, 344(s0)
-  sw t0, 524(s0)
-  flw ft0, 368(s0)
-  fsw ft0, 528(s0)
-  lw t0, 372(s0)
-  sw t0, 532(s0)
-  flw ft0, 376(s0)
-  fsw ft0, 536(s0)
-  flw ft0, 400(s0)
-  fsw ft0, 540(s0)
-  lw t0, 404(s0)
-  sw t0, 544(s0)
-  flw ft0, 408(s0)
-  fsw ft0, 600(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 604(s0)
-  ld t0, 24(s0)
-  lw t1, 604(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 612(s0)
-  flw ft0, 600(s0)
-  flw ft1, 612(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 616(s0)
-  flw ft0, 416(s0)
-  fsw ft0, 620(s0)
-  flw ft0, 616(s0)
-  flw ft1, 620(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 624(s0)
-  flw ft0, 424(s0)
-  fsw ft0, 628(s0)
-  flw ft0, 624(s0)
-  flw ft1, 628(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 632(s0)
-  flw ft0, 428(s0)
-  fsw ft0, 636(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 640(s0)
-  ld t0, 48(s0)
-  lw t1, 640(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 648(s0)
-  flw ft0, 636(s0)
-  flw ft1, 648(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 652(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 656(s0)
-  ld t0, 72(s0)
-  lw t1, 656(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 664(s0)
-  flw ft0, 652(s0)
-  flw ft1, 664(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 668(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 672(s0)
-  ld t0, 104(s0)
-  lw t1, 672(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 680(s0)
-  flw ft0, 668(s0)
-  flw ft1, 680(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 684(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 688(s0)
-  ld t0, 112(s0)
-  lw t1, 688(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 696(s0)
-  flw ft0, 444(s0)
-  fsw ft0, 700(s0)
-  flw ft0, 696(s0)
-  flw ft1, 700(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 704(s0)
-  flw ft0, 448(s0)
-  fsw ft0, 708(s0)
-  flw ft0, 704(s0)
-  flw ft1, 708(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 712(s0)
-  flw ft0, 452(s0)
-  fsw ft0, 716(s0)
-  flw ft0, 712(s0)
-  flw ft1, 716(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 720(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 724(s0)
-  ld t0, 136(s0)
-  lw t1, 724(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 732(s0)
-  flw ft0, 460(s0)
-  fsw ft0, 736(s0)
-  flw ft0, 732(s0)
-  flw ft1, 736(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 740(s0)
-  flw ft0, 464(s0)
-  fsw ft0, 744(s0)
-  flw ft0, 740(s0)
-  flw ft1, 744(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 748(s0)
-  flw ft0, 468(s0)
-  fsw ft0, 752(s0)
-  flw ft0, 748(s0)
-  flw ft1, 752(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 756(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 760(s0)
-  ld t0, 168(s0)
-  lw t1, 760(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 768(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 772(s0)
-  ld t0, 192(s0)
-  lw t1, 772(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 780(s0)
-  flw ft0, 768(s0)
-  flw ft1, 780(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 784(s0)
-  flw ft0, 472(s0)
-  fsw ft0, 788(s0)
-  flw ft0, 784(s0)
-  flw ft1, 788(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 792(s0)
-  flw ft0, 476(s0)
-  fsw ft0, 796(s0)
-  flw ft0, 792(s0)
-  flw ft1, 796(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 800(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 804(s0)
-  ld t0, 224(s0)
-  lw t1, 804(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 812(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 816(s0)
-  ld t0, 232(s0)
-  lw t1, 816(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 824(s0)
-  flw ft0, 812(s0)
-  flw ft1, 824(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 828(s0)
-  flw ft0, 484(s0)
-  fsw ft0, 832(s0)
-  flw ft0, 828(s0)
-  flw ft1, 832(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 836(s0)
-  flw ft0, 488(s0)
-  fsw ft0, 840(s0)
-  flw ft0, 836(s0)
-  flw ft1, 840(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 844(s0)
-  flw ft0, 500(s0)
-  fsw ft0, 848(s0)
-  flw ft0, 504(s0)
-  fsw ft0, 852(s0)
-  flw ft0, 848(s0)
-  flw ft1, 852(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 856(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 860(s0)
-  ld t0, 296(s0)
-  lw t1, 860(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 868(s0)
-  flw ft0, 856(s0)
-  flw ft1, 868(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 872(s0)
-  flw ft0, 516(s0)
-  fsw ft0, 876(s0)
-  flw ft0, 872(s0)
-  flw ft1, 876(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 880(s0)
-  flw ft0, 520(s0)
-  fsw ft0, 884(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 888(s0)
-  ld t0, 336(s0)
-  lw t1, 888(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 896(s0)
-  flw ft0, 884(s0)
-  flw ft1, 896(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 900(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 904(s0)
-  ld t0, 360(s0)
-  lw t1, 904(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 912(s0)
-  flw ft0, 900(s0)
-  flw ft1, 912(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 916(s0)
-  flw ft0, 528(s0)
-  fsw ft0, 920(s0)
-  flw ft0, 916(s0)
-  flw ft1, 920(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 924(s0)
-  flw ft0, 536(s0)
-  fsw ft0, 928(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 932(s0)
-  ld t0, 384(s0)
-  lw t1, 932(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 940(s0)
-  flw ft0, 928(s0)
-  flw ft1, 940(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 944(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 948(s0)
-  ld t0, 392(s0)
-  lw t1, 948(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 956(s0)
-  flw ft0, 944(s0)
-  flw ft1, 956(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 960(s0)
-  flw ft0, 540(s0)
-  fsw ft0, 964(s0)
-  flw ft0, 960(s0)
-  flw ft1, 964(s0)
-  fadd.s ft0, ft0, ft1
-  fsw ft0, 968(s0)
-  addi a0, s0, 560
-  li a1, 0
-  li a2, 40
-  call memset
-  flw ft0, 632(s0)
-  addi t0, s0, 560
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 684(s0)
-  addi t0, s0, 560
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 720(s0)
-  addi t0, s0, 560
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 756(s0)
-  addi t0, s0, 560
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 800(s0)
-  addi t0, s0, 560
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 844(s0)
-  addi t0, s0, 560
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 880(s0)
-  addi t0, s0, 560
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 924(s0)
-  addi t0, s0, 560
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  flw ft0, 968(s0)
-  addi t0, s0, 560
-  li t1, 8
-  slli t1, t1, 2
-  add t0, t0, t1
-  fsw ft0, 0(t0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1080(s0)
-  ld t0, 8(s0)
-  lw t1, 1080(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1088(s0)
-  lw t0, 412(s0)
-  sw t0, 1092(s0)
-  lw t0, 1088(s0)
-  lw t1, 1092(s0)
-  add t0, t0, t1
-  sw t0, 1096(s0)
-  lw t0, 420(s0)
-  sw t0, 1100(s0)
-  lw t0, 1096(s0)
-  lw t1, 1100(s0)
-  add t0, t0, t1
-  sw t0, 1104(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1108(s0)
-  ld t0, 56(s0)
-  lw t1, 1108(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1116(s0)
-  lw t0, 432(s0)
-  sw t0, 1120(s0)
-  lw t0, 1116(s0)
-  lw t1, 1120(s0)
-  add t0, t0, t1
-  sw t0, 1124(s0)
-  lw t0, 436(s0)
-  sw t0, 1128(s0)
-  lw t0, 1124(s0)
-  lw t1, 1128(s0)
-  add t0, t0, t1
-  sw t0, 1132(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1136(s0)
-  ld t0, 80(s0)
-  lw t1, 1136(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1144(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1148(s0)
-  ld t0, 88(s0)
-  lw t1, 1148(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1156(s0)
-  lw t0, 1144(s0)
-  lw t1, 1156(s0)
-  add t0, t0, t1
-  sw t0, 1160(s0)
-  lw t0, 440(s0)
-  sw t0, 1164(s0)
-  lw t0, 1160(s0)
-  lw t1, 1164(s0)
-  add t0, t0, t1
-  sw t0, 1168(s0)
-  lw t0, 456(s0)
-  sw t0, 1172(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1176(s0)
-  ld t0, 160(s0)
-  lw t1, 1176(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1184(s0)
-  lw t0, 1172(s0)
-  lw t1, 1184(s0)
-  add t0, t0, t1
-  sw t0, 1188(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1192(s0)
-  ld t0, 176(s0)
-  lw t1, 1192(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1200(s0)
-  lw t0, 1188(s0)
-  lw t1, 1200(s0)
-  add t0, t0, t1
-  sw t0, 1204(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1208(s0)
-  ld t0, 184(s0)
-  lw t1, 1208(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1216(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1220(s0)
-  ld t0, 208(s0)
-  lw t1, 1220(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1228(s0)
-  lw t0, 1216(s0)
-  lw t1, 1228(s0)
-  add t0, t0, t1
-  sw t0, 1232(s0)
-  lw t0, 480(s0)
-  sw t0, 1236(s0)
-  lw t0, 1232(s0)
-  lw t1, 1236(s0)
-  add t0, t0, t1
-  sw t0, 1240(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1244(s0)
-  ld t0, 248(s0)
-  lw t1, 1244(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1252(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1256(s0)
-  ld t0, 256(s0)
-  lw t1, 1256(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1264(s0)
-  lw t0, 1252(s0)
-  lw t1, 1264(s0)
-  add t0, t0, t1
-  sw t0, 1268(s0)
-  lw t0, 492(s0)
-  sw t0, 1272(s0)
-  lw t0, 1268(s0)
-  lw t1, 1272(s0)
-  add t0, t0, t1
-  sw t0, 1276(s0)
-  lw t0, 496(s0)
-  sw t0, 1280(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1284(s0)
-  ld t0, 280(s0)
-  lw t1, 1284(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1292(s0)
-  lw t0, 1280(s0)
-  lw t1, 1292(s0)
-  add t0, t0, t1
-  sw t0, 1296(s0)
-  lw t0, 508(s0)
-  sw t0, 1300(s0)
-  lw t0, 1296(s0)
-  lw t1, 1300(s0)
-  add t0, t0, t1
-  sw t0, 1304(s0)
-  lw t0, 512(s0)
-  sw t0, 1308(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1312(s0)
-  ld t0, 312(s0)
-  lw t1, 1312(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1320(s0)
-  lw t0, 1308(s0)
-  lw t1, 1320(s0)
-  add t0, t0, t1
-  sw t0, 1324(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1328(s0)
-  ld t0, 320(s0)
-  lw t1, 1328(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1336(s0)
-  lw t0, 1324(s0)
-  lw t1, 1336(s0)
-  add t0, t0, t1
-  sw t0, 1340(s0)
-  lw t0, 524(s0)
-  sw t0, 1344(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1348(s0)
-  ld t0, 352(s0)
-  lw t1, 1348(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1356(s0)
-  lw t0, 1344(s0)
-  lw t1, 1356(s0)
-  add t0, t0, t1
-  sw t0, 1360(s0)
-  lw t0, 532(s0)
-  sw t0, 1364(s0)
-  lw t0, 1360(s0)
-  lw t1, 1364(s0)
-  add t0, t0, t1
-  sw t0, 1368(s0)
-  lw t0, 544(s0)
-  sw t0, 1372(s0)
-  lw t0, 1368(s0)
-  lw t1, 1372(s0)
-  add t0, t0, t1
-  sw t0, 1376(s0)
-  addi a0, s0, 1040
-  li a1, 0
-  li a2, 40
-  call memset
-  lw t2, 1104(s0)
-  addi t0, s0, 1040
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1132(s0)
-  addi t0, s0, 1040
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1168(s0)
-  addi t0, s0, 1040
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1204(s0)
-  addi t0, s0, 1040
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1240(s0)
-  addi t0, s0, 1040
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1276(s0)
-  addi t0, s0, 1040
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1304(s0)
-  addi t0, s0, 1040
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1340(s0)
-  addi t0, s0, 1040
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, 1376(s0)
-  addi t0, s0, 1040
-  li t1, 8
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t0, 544(s0)
-  sw t0, 1416(s0)
-  lw t0, 1416(s0)
-  li t1, 0
-  sub t0, t0, t1
-  sltiu t1, t0, 1
-  xori t0, t1, 1
-  sw t0, 1420(s0)
-  lw t0, 1420(s0)
-  bnez t0, L12.if.then
-  j L13.if.else
-L12.if.then:
-  li a0, 10
-  addi a1, s0, 560
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  call putfarray
-  li a0, 10
-  addi a1, s0, 1040
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  call putarray
-  li t0, 0
-  sw t0, 1432(s0)
-  j L15.while.cond
-L15.while.cond:
-  lw t0, 1432(s0)
-  sw t0, 1436(s0)
-  lw t0, 1436(s0)
-  li t1, 10
-  slt t0, t0, t1
-  sw t0, 1440(s0)
-  lw t0, 1440(s0)
-  bnez t0, L16.while.body
-  j L17.while.end
-L16.while.body:
-  lw t0, 1432(s0)
-  sw t0, 1444(s0)
-  addi t0, s0, 1040
-  lw t1, 1444(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1452(s0)
-  lw t0, 1432(s0)
-  sw t0, 1456(s0)
-  addi t0, s0, 560
-  lw t1, 1456(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1464(s0)
-  lw t0, 1452(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1468(s0)
-  flw ft0, 1468(s0)
-  flw ft1, 1464(s0)
-  fsub.s ft0, ft0, ft1
-  fsw ft0, 1472(s0)
-  lw t0, 1432(s0)
-  sw t0, 1476(s0)
-  flw ft0, 1472(s0)
-  fcvt.w.s t0, ft0, rtz
-  sw t0, 1484(s0)
-  lw t2, 1484(s0)
-  addi t0, s0, 1040
-  lw t1, 1476(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t0, 1432(s0)
-  sw t0, 1488(s0)
-  lw t0, 1488(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 1492(s0)
-  lw t0, 1492(s0)
-  sw t0, 1432(s0)
-  j L15.while.cond
-L17.while.end:
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1496(s0)
-  addi t0, s0, 1040
-  lw t1, 1496(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1504(s0)
-  addi t0, s0, 560
-  li t1, 8
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1512(s0)
-  lw t0, 1504(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1516(s0)
-  flw ft0, 1516(s0)
-  flw ft1, 1512(s0)
-  fmul.s ft0, ft0, ft1
-  fsw ft0, 1520(s0)
-  flw ft0, 1520(s0)
-  fcvt.w.s t0, ft0, rtz
-  sw t0, 1524(s0)
-  lw a0, 1524(s0)
-  ld ra, 1696(s0)
-  addi sp, s0, 1712
-  ld s0, 1704(s0)
-  ret
-L13.if.else:
-  flw ft0, 408(s0)
-  fsw ft0, 1528(s0)
-  lw t0, 412(s0)
-  sw t0, 1536(s0)
-  flw ft0, 416(s0)
-  fsw ft0, 1544(s0)
-  lw t0, 420(s0)
-  sw t0, 1548(s0)
-  flw ft0, 424(s0)
-  fsw ft0, 1552(s0)
-  flw ft0, 428(s0)
-  fsw ft0, 1556(s0)
-  lw t0, 432(s0)
-  sw t0, 1560(s0)
-  lw t0, 436(s0)
-  sw t0, 1564(s0)
-  lw t0, 440(s0)
-  sw t0, 1568(s0)
-  flw ft0, 444(s0)
-  fsw ft0, 1572(s0)
-  flw ft0, 448(s0)
-  fsw ft0, 1576(s0)
-  flw ft0, 452(s0)
-  fsw ft0, 1580(s0)
-  lw t0, 456(s0)
-  sw t0, 1584(s0)
-  flw ft0, 460(s0)
-  fsw ft0, 1588(s0)
-  flw ft0, 464(s0)
-  fsw ft0, 1592(s0)
-  flw ft0, 468(s0)
-  fsw ft0, 1596(s0)
-  flw ft0, 472(s0)
-  fsw ft0, 1600(s0)
-  flw ft0, 476(s0)
-  fsw ft0, 1604(s0)
-  lw t0, 480(s0)
-  sw t0, 1608(s0)
-  flw ft0, 484(s0)
-  fsw ft0, 1612(s0)
-  flw ft0, 488(s0)
-  fsw ft0, 1616(s0)
-  lw t0, 492(s0)
-  sw t0, 1620(s0)
-  lw t0, 496(s0)
-  sw t0, 1624(s0)
-  flw ft0, 500(s0)
-  fsw ft0, 1628(s0)
-  flw ft0, 504(s0)
-  fsw ft0, 1632(s0)
-  lw t0, 508(s0)
-  sw t0, 1636(s0)
-  lw t0, 512(s0)
-  sw t0, 1640(s0)
-  flw ft0, 516(s0)
-  fsw ft0, 1644(s0)
-  flw ft0, 520(s0)
-  fsw ft0, 1648(s0)
-  lw t0, 524(s0)
-  sw t0, 1652(s0)
-  flw ft0, 528(s0)
-  fsw ft0, 1656(s0)
-  lw t0, 532(s0)
-  sw t0, 1660(s0)
-  flw ft0, 536(s0)
-  fsw ft0, 1664(s0)
-  lw t0, 544(s0)
-  sw t0, 1668(s0)
-  flw ft0, 540(s0)
-  fsw ft0, 1672(s0)
-  lw t0, 1668(s0)
-  fcvt.s.w ft0, t0
-  fsw ft0, 1676(s0)
-  flw ft0, 1672(s0)
-  fcvt.w.s t0, ft0, rtz
-  sw t0, 1680(s0)
-  addi sp, sp, -448
-  flw fa0, 1528(s0)
-  addi a1, s0, 1040
-  li t1, 0
-  slli t1, t1, 2
-  add a1, a1, t1
-  lw a2, 1536(s0)
-  addi a3, s0, 560
-  li t1, 0
-  slli t1, t1, 2
-  add a3, a3, t1
-  flw fa4, 1544(s0)
-  lw a5, 1548(s0)
-  flw fa6, 1552(s0)
-  flw fa7, 1556(s0)
-  add t4, sp, zero
-  ld t0, 48(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 8
-  ld t0, 56(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 16
-  lw t0, 1560(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  lw t0, 1564(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 32
-  ld t0, 72(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 40
-  ld t0, 80(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  ld t0, 88(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 56
-  lw t0, 1568(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  ld t0, 104(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 72
-  ld t0, 112(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 80
-  flw ft0, 1572(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 88
-  flw ft0, 1576(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 96
-  flw ft0, 1580(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 104
-  ld t0, 136(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 112
-  lw t0, 1584(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 120
-  flw ft0, 1588(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 128
-  flw ft0, 1592(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 136
-  flw ft0, 1596(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 144
-  ld t0, 160(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 152
-  ld t0, 168(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 160
-  ld t0, 176(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 168
-  ld t0, 184(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 176
-  ld t0, 192(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 184
-  flw ft0, 1600(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 192
-  flw ft0, 1604(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 200
-  ld t0, 208(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 208
-  lw t0, 1608(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 216
-  ld t0, 224(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 224
-  ld t0, 232(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 232
-  flw ft0, 1612(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 240
-  flw ft0, 1616(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 248
-  ld t0, 248(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 256
-  ld t0, 256(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 264
-  lw t0, 1620(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 272
-  lw t0, 1624(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 280
-  flw ft0, 1628(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 288
-  flw ft0, 1632(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 296
-  ld t0, 280(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 304
-  lw t0, 1636(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 312
-  ld t0, 296(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 320
-  lw t0, 1640(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 328
-  ld t0, 312(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 336
-  ld t0, 320(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 344
-  flw ft0, 1644(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 352
-  flw ft0, 1648(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 360
-  ld t0, 336(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 368
-  lw t0, 1652(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 376
-  ld t0, 352(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 384
-  ld t0, 360(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 392
-  flw ft0, 1656(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 400
-  lw t0, 1660(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 408
-  flw ft0, 1664(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 416
-  ld t0, 384(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 424
-  ld t0, 392(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 432
-  flw ft0, 1676(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 440
-  lw t0, 1680(s0)
-  sd t0, 0(t4)
-  call params_mix
-  addi sp, sp, 448
-  sw a0, 1684(s0)
-  lw a0, 1684(s0)
-  ld ra, 1696(s0)
-  addi sp, s0, 1712
-  ld s0, 1704(s0)
-  ret
-L14.if.end:
-  li a0, 0
-  ld ra, 1696(s0)
-  addi sp, s0, 1712
-  ld s0, 1704(s0)
-  ret
-.size params_mix, .-params_mix
-
-.global main
-.type main, @function
-main:
-  li t4, -4352
-  add sp, sp, t4
-  li t4, 4336
-  add t4, sp, t4
-  sd ra, 0(t4)
-  li t4, 4344
-  add t4, sp, t4
-  sd s0, 0(t4)
-  mv s0, sp
-  addi a0, s0, 0
-  li a1, 0
-  li a2, 480
-  call memset
-  addi a0, s0, 576
-  li a1, 0
-  li a2, 288
-  call memset
-  li t0, 0
-  sw t0, 864(s0)
-  call getint
-  sw a0, 868(s0)
-  lw t0, 868(s0)
-  la t1, k
-  sw t0, 0(t1)
-  li t0, 0
-  sw t0, 864(s0)
-  j L18.while.cond
-L18.while.cond:
-  lw t0, 864(s0)
-  sw t0, 872(s0)
-  lw t0, 872(s0)
-  li t1, 40
-  slt t0, t0, t1
-  sw t0, 876(s0)
-  lw t0, 876(s0)
-  bnez t0, L19.while.body
-  j L20.while.end
-L19.while.body:
-  lw t0, 864(s0)
-  sw t0, 880(s0)
-  lw t0, 880(s0)
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 884(s0)
-  addi a0, s0, 0
-  lw t1, 884(s0)
-  slli t1, t1, 2
-  add a0, a0, t1
-  call getfarray
-  sw a0, 892(s0)
-  lw t0, 864(s0)
-  sw t0, 896(s0)
-  lw t0, 896(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 900(s0)
-  lw t0, 900(s0)
-  sw t0, 864(s0)
-  j L18.while.cond
-L20.while.end:
-  li t0, 0
-  sw t0, 864(s0)
-  j L21.while.cond
-L21.while.cond:
-  lw t0, 864(s0)
-  sw t0, 904(s0)
-  lw t0, 904(s0)
-  li t1, 24
-  slt t0, t0, t1
-  sw t0, 908(s0)
-  lw t0, 908(s0)
-  bnez t0, L22.while.body
-  j L23.while.end
-L22.while.body:
-  lw t0, 864(s0)
-  sw t0, 912(s0)
-  lw t0, 912(s0)
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 916(s0)
-  addi a0, s0, 576
-  lw t1, 916(s0)
-  slli t1, t1, 2
-  add a0, a0, t1
-  call getarray
-  sw a0, 924(s0)
-  lw t0, 864(s0)
-  sw t0, 928(s0)
-  lw t0, 928(s0)
-  li t1, 1
-  add t0, t0, t1
-  sw t0, 932(s0)
-  lw t0, 932(s0)
-  sw t0, 864(s0)
-  j L21.while.cond
-L23.while.end:
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 940(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 944(s0)
-  lw t0, 940(s0)
-  lw t1, 944(s0)
-  add t0, t0, t1
-  sw t0, 948(s0)
-  addi t0, s0, 0
-  lw t1, 948(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 956(s0)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 960(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 964(s0)
-  lw t0, 960(s0)
-  lw t1, 964(s0)
-  add t0, t0, t1
-  sw t0, 968(s0)
-  addi t0, s0, 0
-  lw t1, 968(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 976(s0)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 980(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 984(s0)
-  lw t0, 980(s0)
-  lw t1, 984(s0)
-  add t0, t0, t1
-  sw t0, 988(s0)
-  addi t0, s0, 0
-  lw t1, 988(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 996(s0)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1000(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1004(s0)
-  lw t0, 1000(s0)
-  lw t1, 1004(s0)
-  add t0, t0, t1
-  sw t0, 1008(s0)
-  addi t0, s0, 0
-  lw t1, 1008(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1016(s0)
-  li t0, 4
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1020(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1024(s0)
-  lw t0, 1020(s0)
-  lw t1, 1024(s0)
-  add t0, t0, t1
-  sw t0, 1028(s0)
-  addi t0, s0, 0
-  lw t1, 1028(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1036(s0)
-  li t0, 5
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1040(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1044(s0)
-  lw t0, 1040(s0)
-  lw t1, 1044(s0)
-  add t0, t0, t1
-  sw t0, 1048(s0)
-  addi t0, s0, 0
-  lw t1, 1048(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1056(s0)
-  li t0, 6
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1060(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1064(s0)
-  lw t0, 1060(s0)
-  lw t1, 1064(s0)
-  add t0, t0, t1
-  sw t0, 1068(s0)
-  addi t0, s0, 0
-  lw t1, 1068(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1076(s0)
-  li t0, 7
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1080(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1084(s0)
-  lw t0, 1080(s0)
-  lw t1, 1084(s0)
-  add t0, t0, t1
-  sw t0, 1088(s0)
-  addi t0, s0, 0
-  lw t1, 1088(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1096(s0)
-  li t0, 8
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1100(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1104(s0)
-  lw t0, 1100(s0)
-  lw t1, 1104(s0)
-  add t0, t0, t1
-  sw t0, 1108(s0)
-  addi t0, s0, 0
-  lw t1, 1108(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1116(s0)
-  li t0, 9
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1120(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1124(s0)
-  lw t0, 1120(s0)
-  lw t1, 1124(s0)
-  add t0, t0, t1
-  sw t0, 1128(s0)
-  addi t0, s0, 0
-  lw t1, 1128(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1136(s0)
-  li t0, 10
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1140(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1144(s0)
-  lw t0, 1140(s0)
-  lw t1, 1144(s0)
-  add t0, t0, t1
-  sw t0, 1148(s0)
-  addi t0, s0, 0
-  lw t1, 1148(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1156(s0)
-  li t0, 11
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1160(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1164(s0)
-  lw t0, 1160(s0)
-  lw t1, 1164(s0)
-  add t0, t0, t1
-  sw t0, 1168(s0)
-  addi t0, s0, 0
-  lw t1, 1168(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1176(s0)
-  li t0, 12
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1180(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1184(s0)
-  lw t0, 1180(s0)
-  lw t1, 1184(s0)
-  add t0, t0, t1
-  sw t0, 1188(s0)
-  addi t0, s0, 0
-  lw t1, 1188(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1196(s0)
-  li t0, 13
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1200(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1204(s0)
-  lw t0, 1200(s0)
-  lw t1, 1204(s0)
-  add t0, t0, t1
-  sw t0, 1208(s0)
-  addi t0, s0, 0
-  lw t1, 1208(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1216(s0)
-  li t0, 14
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1220(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1224(s0)
-  lw t0, 1220(s0)
-  lw t1, 1224(s0)
-  add t0, t0, t1
-  sw t0, 1228(s0)
-  addi t0, s0, 0
-  lw t1, 1228(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1236(s0)
-  li t0, 15
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1240(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1244(s0)
-  lw t0, 1240(s0)
-  lw t1, 1244(s0)
-  add t0, t0, t1
-  sw t0, 1248(s0)
-  addi t0, s0, 0
-  lw t1, 1248(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1256(s0)
-  li t0, 16
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1260(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1264(s0)
-  lw t0, 1260(s0)
-  lw t1, 1264(s0)
-  add t0, t0, t1
-  sw t0, 1268(s0)
-  addi t0, s0, 0
-  lw t1, 1268(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1276(s0)
-  li t0, 17
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1280(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1284(s0)
-  lw t0, 1280(s0)
-  lw t1, 1284(s0)
-  add t0, t0, t1
-  sw t0, 1288(s0)
-  addi t0, s0, 0
-  lw t1, 1288(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1296(s0)
-  li t0, 18
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1300(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1304(s0)
-  lw t0, 1300(s0)
-  lw t1, 1304(s0)
-  add t0, t0, t1
-  sw t0, 1308(s0)
-  addi t0, s0, 0
-  lw t1, 1308(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1316(s0)
-  li t0, 19
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1320(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1324(s0)
-  lw t0, 1320(s0)
-  lw t1, 1324(s0)
-  add t0, t0, t1
-  sw t0, 1328(s0)
-  addi t0, s0, 0
-  lw t1, 1328(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1336(s0)
-  li t0, 20
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1340(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1344(s0)
-  lw t0, 1340(s0)
-  lw t1, 1344(s0)
-  add t0, t0, t1
-  sw t0, 1348(s0)
-  addi t0, s0, 0
-  lw t1, 1348(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1356(s0)
-  li t0, 21
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1360(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1364(s0)
-  lw t0, 1360(s0)
-  lw t1, 1364(s0)
-  add t0, t0, t1
-  sw t0, 1368(s0)
-  addi t0, s0, 0
-  lw t1, 1368(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1376(s0)
-  li t0, 22
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1380(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1384(s0)
-  lw t0, 1380(s0)
-  lw t1, 1384(s0)
-  add t0, t0, t1
-  sw t0, 1388(s0)
-  addi t0, s0, 0
-  lw t1, 1388(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1396(s0)
-  li t0, 23
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1400(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1404(s0)
-  lw t0, 1400(s0)
-  lw t1, 1404(s0)
-  add t0, t0, t1
-  sw t0, 1408(s0)
-  addi t0, s0, 0
-  lw t1, 1408(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1416(s0)
-  li t0, 24
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1420(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1424(s0)
-  lw t0, 1420(s0)
-  lw t1, 1424(s0)
-  add t0, t0, t1
-  sw t0, 1428(s0)
-  addi t0, s0, 0
-  lw t1, 1428(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1436(s0)
-  li t0, 25
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1440(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1444(s0)
-  lw t0, 1440(s0)
-  lw t1, 1444(s0)
-  add t0, t0, t1
-  sw t0, 1448(s0)
-  addi t0, s0, 0
-  lw t1, 1448(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1456(s0)
-  li t0, 26
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1460(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1464(s0)
-  lw t0, 1460(s0)
-  lw t1, 1464(s0)
-  add t0, t0, t1
-  sw t0, 1468(s0)
-  addi t0, s0, 0
-  lw t1, 1468(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1476(s0)
-  li t0, 27
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1480(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1484(s0)
-  lw t0, 1480(s0)
-  lw t1, 1484(s0)
-  add t0, t0, t1
-  sw t0, 1488(s0)
-  addi t0, s0, 0
-  lw t1, 1488(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1496(s0)
-  li t0, 28
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1500(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1504(s0)
-  lw t0, 1500(s0)
-  lw t1, 1504(s0)
-  add t0, t0, t1
-  sw t0, 1508(s0)
-  addi t0, s0, 0
-  lw t1, 1508(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1516(s0)
-  li t0, 29
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1520(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1524(s0)
-  lw t0, 1520(s0)
-  lw t1, 1524(s0)
-  add t0, t0, t1
-  sw t0, 1528(s0)
-  addi t0, s0, 0
-  lw t1, 1528(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1536(s0)
-  li t0, 30
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1540(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1544(s0)
-  lw t0, 1540(s0)
-  lw t1, 1544(s0)
-  add t0, t0, t1
-  sw t0, 1548(s0)
-  addi t0, s0, 0
-  lw t1, 1548(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1556(s0)
-  li t0, 31
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1560(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1564(s0)
-  lw t0, 1560(s0)
-  lw t1, 1564(s0)
-  add t0, t0, t1
-  sw t0, 1568(s0)
-  addi t0, s0, 0
-  lw t1, 1568(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1576(s0)
-  li t0, 32
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1580(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1584(s0)
-  lw t0, 1580(s0)
-  lw t1, 1584(s0)
-  add t0, t0, t1
-  sw t0, 1588(s0)
-  addi t0, s0, 0
-  lw t1, 1588(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1596(s0)
-  li t0, 33
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1600(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1604(s0)
-  lw t0, 1600(s0)
-  lw t1, 1604(s0)
-  add t0, t0, t1
-  sw t0, 1608(s0)
-  addi t0, s0, 0
-  lw t1, 1608(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1616(s0)
-  li t0, 34
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1620(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1624(s0)
-  lw t0, 1620(s0)
-  lw t1, 1624(s0)
-  add t0, t0, t1
-  sw t0, 1628(s0)
-  addi t0, s0, 0
-  lw t1, 1628(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1636(s0)
-  li t0, 35
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1640(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1644(s0)
-  lw t0, 1640(s0)
-  lw t1, 1644(s0)
-  add t0, t0, t1
-  sw t0, 1648(s0)
-  addi t0, s0, 0
-  lw t1, 1648(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1656(s0)
-  li t0, 36
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1660(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1664(s0)
-  lw t0, 1660(s0)
-  lw t1, 1664(s0)
-  add t0, t0, t1
-  sw t0, 1668(s0)
-  addi t0, s0, 0
-  lw t1, 1668(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1676(s0)
-  li t0, 37
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1680(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1684(s0)
-  lw t0, 1680(s0)
-  lw t1, 1684(s0)
-  add t0, t0, t1
-  sw t0, 1688(s0)
-  addi t0, s0, 0
-  lw t1, 1688(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1696(s0)
-  li t0, 38
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1700(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1704(s0)
-  lw t0, 1700(s0)
-  lw t1, 1704(s0)
-  add t0, t0, t1
-  sw t0, 1708(s0)
-  addi t0, s0, 0
-  lw t1, 1708(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1716(s0)
-  li t0, 39
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1720(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1724(s0)
-  lw t0, 1720(s0)
-  lw t1, 1724(s0)
-  add t0, t0, t1
-  sw t0, 1728(s0)
-  addi t0, s0, 0
-  lw t1, 1728(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1736(s0)
-  addi sp, sp, -256
-  flw fa0, 956(s0)
-  flw fa1, 976(s0)
-  flw fa2, 996(s0)
-  flw fa3, 1016(s0)
-  flw fa4, 1036(s0)
-  flw fa5, 1056(s0)
-  flw fa6, 1076(s0)
-  flw fa7, 1096(s0)
-  add t4, sp, zero
-  flw ft0, 1116(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 8
-  flw ft0, 1136(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 16
-  flw ft0, 1156(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 24
-  flw ft0, 1176(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 32
-  flw ft0, 1196(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 40
-  flw ft0, 1216(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 48
-  flw ft0, 1236(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 56
-  flw ft0, 1256(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 64
-  flw ft0, 1276(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 72
-  flw ft0, 1296(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 80
-  flw ft0, 1316(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 88
-  flw ft0, 1336(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 96
-  flw ft0, 1356(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 104
-  flw ft0, 1376(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 112
-  flw ft0, 1396(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 120
-  flw ft0, 1416(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 128
-  flw ft0, 1436(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 136
-  flw ft0, 1456(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 144
-  flw ft0, 1476(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 152
-  flw ft0, 1496(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 160
-  flw ft0, 1516(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 168
-  flw ft0, 1536(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 176
-  flw ft0, 1556(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 184
-  flw ft0, 1576(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 192
-  flw ft0, 1596(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 200
-  flw ft0, 1616(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 208
-  flw ft0, 1636(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 216
-  flw ft0, 1656(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 224
-  flw ft0, 1676(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 232
-  flw ft0, 1696(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 240
-  flw ft0, 1716(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 248
-  flw ft0, 1736(s0)
-  fsw ft0, 0(t4)
-  call params_f40
-  addi sp, sp, 256
-  fsw fa0, 1740(s0)
-  flw ft0, 1740(s0)
-  fsw ft0, 936(s0)
-  li t0, 23
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1748(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1752(s0)
-  lw t0, 1748(s0)
-  lw t1, 1752(s0)
-  add t0, t0, t1
-  sw t0, 1756(s0)
-  addi t0, s0, 576
-  lw t1, 1756(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1764(s0)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1768(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1772(s0)
-  lw t0, 1768(s0)
-  lw t1, 1772(s0)
-  add t0, t0, t1
-  sw t0, 1776(s0)
-  addi t0, s0, 576
-  lw t1, 1776(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1784(s0)
-  li t0, 6
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1788(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1792(s0)
-  lw t0, 1788(s0)
-  lw t1, 1792(s0)
-  add t0, t0, t1
-  sw t0, 1796(s0)
-  addi t0, s0, 576
-  lw t1, 1796(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1804(s0)
-  li t0, 4
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1808(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1812(s0)
-  lw t0, 1808(s0)
-  lw t1, 1812(s0)
-  add t0, t0, t1
-  sw t0, 1816(s0)
-  addi t0, s0, 0
-  lw t1, 1816(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1824(s0)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1828(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1832(s0)
-  lw t0, 1828(s0)
-  lw t1, 1832(s0)
-  add t0, t0, t1
-  sw t0, 1836(s0)
-  addi t0, s0, 576
-  lw t1, 1836(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1844(s0)
-  li t0, 4
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1848(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1852(s0)
-  lw t0, 1848(s0)
-  lw t1, 1852(s0)
-  add t0, t0, t1
-  sw t0, 1856(s0)
-  addi t0, s0, 576
-  lw t1, 1856(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1864(s0)
-  li t0, 5
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1868(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1872(s0)
-  lw t0, 1868(s0)
-  lw t1, 1872(s0)
-  add t0, t0, t1
-  sw t0, 1876(s0)
-  addi t0, s0, 576
-  lw t1, 1876(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1884(s0)
-  li t0, 8
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1888(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1892(s0)
-  lw t0, 1888(s0)
-  lw t1, 1892(s0)
-  add t0, t0, t1
-  sw t0, 1896(s0)
-  addi t0, s0, 0
-  lw t1, 1896(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1904(s0)
-  li t0, 15
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1908(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1912(s0)
-  lw t0, 1908(s0)
-  lw t1, 1912(s0)
-  add t0, t0, t1
-  sw t0, 1916(s0)
-  addi t0, s0, 0
-  lw t1, 1916(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1924(s0)
-  li t0, 7
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1928(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1932(s0)
-  lw t0, 1928(s0)
-  lw t1, 1932(s0)
-  add t0, t0, t1
-  sw t0, 1936(s0)
-  addi t0, s0, 0
-  lw t1, 1936(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1944(s0)
-  li t0, 22
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1948(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1952(s0)
-  lw t0, 1948(s0)
-  lw t1, 1952(s0)
-  add t0, t0, t1
-  sw t0, 1956(s0)
-  addi t0, s0, 576
-  lw t1, 1956(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 1964(s0)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1968(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1972(s0)
-  lw t0, 1968(s0)
-  lw t1, 1972(s0)
-  add t0, t0, t1
-  sw t0, 1976(s0)
-  addi t0, s0, 0
-  lw t1, 1976(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 1984(s0)
-  li t0, 28
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 1988(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 1992(s0)
-  lw t0, 1988(s0)
-  lw t1, 1992(s0)
-  add t0, t0, t1
-  sw t0, 1996(s0)
-  addi t0, s0, 0
-  lw t1, 1996(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 2004(s0)
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 2008(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 2012(s0)
-  lw t0, 2008(s0)
-  lw t1, 2012(s0)
-  add t0, t0, t1
-  sw t0, 2016(s0)
-  addi t0, s0, 576
-  lw t1, 2016(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, 2024(s0)
-  li t0, 37
-  li t1, 3
-  mul t0, t0, t1
-  sw t0, 2028(s0)
-  la t0, k
-  lw t0, 0(t0)
-  sw t0, 2032(s0)
-  lw t0, 2028(s0)
-  lw t1, 2032(s0)
-  add t0, t0, t1
-  sw t0, 2036(s0)
-  addi t0, s0, 0
-  lw t1, 2036(s0)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  fsw ft0, 2044(s0)
-  li t0, 19
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2048
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2048
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2052
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2056
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2056
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2064
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 30
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2072
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2068
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2072
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2076
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2084
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 12
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2088
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2092
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2088
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2092
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2096
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2096
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2104
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2108
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2112
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2108
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2112
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2116
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2124
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 11
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2128
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2132
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2128
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2132
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2136
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2136
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2144
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 38
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2148
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2152
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2156
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2164
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 6
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2168
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2168
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2172
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2176
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2176
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2184
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 7
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2192
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2188
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2192
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2196
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2196
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 32
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2208
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2212
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2208
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2212
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2216
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2224
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 10
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2232
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2228
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2232
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2236
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2236
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2244
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 13
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2248
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2248
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2252
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2256
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2256
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 20
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2268
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2272
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2268
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2272
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2276
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2284
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 33
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2288
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2288
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2292
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2296
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2296
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2304
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 23
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2308
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2308
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2312
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2316
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2324
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 9
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2328
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2332
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2328
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2332
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2336
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2336
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2344
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 25
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2352
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2348
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2352
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2356
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2356
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2364
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 8
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2368
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2368
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2372
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2376
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2376
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2384
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 39
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2388
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2392
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2388
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2392
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2396
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2396
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2404
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 17
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2408
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2412
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2408
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2412
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2416
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2416
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2424
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 21
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2428
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2432
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2428
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2432
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2436
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2436
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2444
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 16
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2448
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2452
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2448
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2452
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2456
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2456
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2464
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 5
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2468
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2472
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2468
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2472
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2476
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2476
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2484
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 34
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2488
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2492
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2488
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2492
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2496
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2496
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2504
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 18
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2508
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2512
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2508
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2512
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2516
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2516
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2524
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 9
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2528
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2532
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2528
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2532
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2536
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2536
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2544
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 14
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2548
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2552
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2548
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2552
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2556
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2556
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2564
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 10
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2568
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2572
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2568
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2572
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2576
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2576
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2584
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2588
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2592
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2588
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2592
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2596
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2596
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2604
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 12
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2608
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2612
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2608
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2612
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2616
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2616
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2624
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 31
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2628
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2632
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2628
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2632
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2636
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2636
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2644
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 11
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2648
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2652
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2648
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2652
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2656
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2656
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2664
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 16
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2668
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2672
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2668
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2672
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2676
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2676
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2684
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 27
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2688
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2692
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2688
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2692
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2696
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2696
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2704
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 24
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2708
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2712
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2708
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2712
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2716
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2716
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2724
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 13
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2728
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2732
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2728
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2732
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2736
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2736
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2744
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 29
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2748
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2752
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2748
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2752
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2756
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2756
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2764
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2768
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2772
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2768
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2772
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2776
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2776
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2784
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 21
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2788
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2792
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2788
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2792
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2796
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2796
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2804
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 20
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2808
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2812
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2808
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2812
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2816
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2816
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2824
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 18
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2828
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2832
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2828
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2832
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2836
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2836
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2844
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 19
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2848
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2852
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2848
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2852
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2856
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2856
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2864
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 22
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2868
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2872
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2868
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2872
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2876
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2876
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2884
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 26
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2888
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2892
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2888
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2892
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2896
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2896
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2904
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 36
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2908
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2912
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2908
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2912
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2916
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2916
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2924
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 17
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2928
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2932
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2928
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2932
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2936
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2936
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2944
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 15
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2948
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2952
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2948
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2952
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2956
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2956
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 2964
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2968
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2972
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2968
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2972
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2976
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 2976
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 2984
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 14
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 2988
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 2992
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 2988
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 2992
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 2996
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 2996
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3004
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 35
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3008
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3012
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3008
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3012
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3016
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3016
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3024
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  addi sp, sp, -448
-  lw a0, 1764(s0)
-  lw a1, 1784(s0)
-  lw a2, 1804(s0)
-  flw fa3, 1824(s0)
-  lw a4, 1844(s0)
-  lw a5, 1864(s0)
-  lw a6, 1884(s0)
-  flw fa7, 1904(s0)
-  add t4, sp, zero
-  flw ft0, 1924(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 8
-  flw ft0, 1944(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 16
-  lw t0, 1964(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  flw ft0, 1984(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 32
-  flw ft0, 2004(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 40
-  lw t0, 2024(s0)
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  flw ft0, 2044(s0)
-  fsw ft0, 0(t4)
-  addi t4, sp, 56
-  li t4, 2064
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  li t4, 2084
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 72
-  li t4, 2104
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 80
-  li t4, 2124
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 88
-  li t4, 2144
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 96
-  li t4, 2164
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 104
-  li t4, 2184
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 112
-  li t4, 2204
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 120
-  li t4, 2224
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 128
-  li t4, 2244
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 136
-  li t4, 2264
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 144
-  li t4, 2284
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 152
-  li t4, 2304
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 160
-  li t4, 2324
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 168
-  li t4, 2344
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 176
-  li t4, 2364
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 184
-  li t4, 2384
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 192
-  li t4, 2404
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 200
-  li t4, 2424
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 208
-  li t4, 2444
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 216
-  li t4, 2464
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 224
-  li t4, 2484
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 232
-  li t4, 2504
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 240
-  li t4, 2524
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 248
-  li t4, 2544
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 256
-  li t4, 2564
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 264
-  li t4, 2584
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 272
-  li t4, 2604
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 280
-  li t4, 2624
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 288
-  li t4, 2644
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 296
-  li t4, 2664
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 304
-  li t4, 2684
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 312
-  li t4, 2704
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 320
-  li t4, 2724
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 328
-  li t4, 2744
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 336
-  li t4, 2764
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 344
-  li t4, 2784
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 352
-  li t4, 2804
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 360
-  li t4, 2824
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 368
-  li t4, 2844
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 376
-  li t4, 2864
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 384
-  li t4, 2884
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 392
-  li t4, 2904
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 400
-  li t4, 2924
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 408
-  li t4, 2944
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 416
-  li t4, 2964
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 424
-  li t4, 2984
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 432
-  li t4, 3004
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 440
-  li t4, 3024
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  call params_f40_i24
-  addi sp, sp, 448
-  li t4, 3028
-  add t4, s0, t4
-  fsw fa0, 0(t4)
-  li t4, 3028
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 1744(s0)
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3036
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3044
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3060
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 4
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 5
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 6
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3084
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 7
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3092
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 8
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3100
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 9
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3108
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 10
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 11
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3124
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 12
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3132
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 13
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3140
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 14
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 15
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3156
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 16
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3164
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 17
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 18
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 19
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 20
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3196
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 21
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 22
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3212
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 23
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3220
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 24
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 25
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3236
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 26
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3244
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 27
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3252
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 28
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3260
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 29
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3268
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 30
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 31
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3284
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 32
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 33
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3300
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 34
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3308
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 35
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 36
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 37
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3332
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 38
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3340
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 39
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3348
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi sp, sp, -256
-  addi a0, s0, 0
-  li t4, 3036
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a0, a0, t1
-  addi a1, s0, 0
-  li t4, 3044
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a1, a1, t1
-  addi a2, s0, 0
-  li t4, 3052
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a2, a2, t1
-  addi a3, s0, 0
-  li t4, 3060
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a3, a3, t1
-  addi a4, s0, 0
-  li t4, 3068
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a4, a4, t1
-  addi a5, s0, 0
-  li t4, 3076
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a5, a5, t1
-  addi a6, s0, 0
-  li t4, 3084
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a6, a6, t1
-  addi a7, s0, 0
-  li t4, 3092
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a7, a7, t1
-  add t4, sp, zero
-  addi t0, s0, 0
-  li t4, 3100
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 8
-  addi t0, s0, 0
-  li t4, 3108
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 16
-  addi t0, s0, 0
-  li t4, 3116
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  addi t0, s0, 0
-  li t4, 3124
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 32
-  addi t0, s0, 0
-  li t4, 3132
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 40
-  addi t0, s0, 0
-  li t4, 3140
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  addi t0, s0, 0
-  li t4, 3148
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 56
-  addi t0, s0, 0
-  li t4, 3156
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  addi t0, s0, 0
-  li t4, 3164
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 72
-  addi t0, s0, 0
-  li t4, 3172
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 80
-  addi t0, s0, 0
-  li t4, 3180
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 88
-  addi t0, s0, 0
-  li t4, 3188
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 96
-  addi t0, s0, 0
-  li t4, 3196
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 104
-  addi t0, s0, 0
-  li t4, 3204
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 112
-  addi t0, s0, 0
-  li t4, 3212
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 120
-  addi t0, s0, 0
-  li t4, 3220
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 128
-  addi t0, s0, 0
-  li t4, 3228
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 136
-  addi t0, s0, 0
-  li t4, 3236
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 144
-  addi t0, s0, 0
-  li t4, 3244
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 152
-  addi t0, s0, 0
-  li t4, 3252
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 160
-  addi t0, s0, 0
-  li t4, 3260
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 168
-  addi t0, s0, 0
-  li t4, 3268
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 176
-  addi t0, s0, 0
-  li t4, 3276
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 184
-  addi t0, s0, 0
-  li t4, 3284
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 192
-  addi t0, s0, 0
-  li t4, 3292
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 200
-  addi t0, s0, 0
-  li t4, 3300
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 208
-  addi t0, s0, 0
-  li t4, 3308
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 216
-  addi t0, s0, 0
-  li t4, 3316
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 224
-  addi t0, s0, 0
-  li t4, 3324
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 232
-  addi t0, s0, 0
-  li t4, 3332
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 240
-  addi t0, s0, 0
-  li t4, 3340
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 248
-  addi t0, s0, 0
-  li t4, 3348
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  call params_fa40
-  addi sp, sp, 256
-  li t4, 3356
-  add t4, s0, t4
-  fsw fa0, 0(t4)
-  li t4, 3356
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  li t4, 3032
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3364
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3368
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3364
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3368
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3372
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3372
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3380
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3384
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3392
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3396
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3392
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3396
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3400
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3400
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3408
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3412
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3420
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3424
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3420
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3424
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3428
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3428
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3436
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3440
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3444
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3440
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3444
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3448
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3448
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3456
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3460
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3464
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3460
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3464
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3468
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3468
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3476
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 4
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3480
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3484
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3480
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3484
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3488
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3488
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3496
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 5
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3500
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3508
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 4
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3516
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3520
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3516
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3520
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3524
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3524
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3532
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 5
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3536
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3540
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3536
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3540
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3544
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3544
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3552
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 6
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3556
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 6
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3564
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 7
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3572
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 8
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3580
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3584
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3580
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3584
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3588
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3588
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3596
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 7
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3600
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 8
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3608
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 9
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3616
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3620
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3616
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3620
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3624
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3624
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3632
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 10
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3636
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3640
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3636
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3640
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3644
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3644
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3652
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 11
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3656
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3660
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3656
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3660
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3664
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3664
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3672
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 12
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3676
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 9
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3684
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3688
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3684
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3688
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3692
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3692
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3700
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 13
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3704
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3708
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3704
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3708
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3712
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3712
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3720
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 14
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3724
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3728
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3724
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3728
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3732
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3732
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3740
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 15
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3744
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3748
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3744
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3748
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3752
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3752
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3760
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 10
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3764
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 16
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3772
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 11
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3780
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 12
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3788
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 17
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3796
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 18
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3804
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3808
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3804
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3808
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3812
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3812
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3820
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 19
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3824
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3828
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3824
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3828
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3832
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3832
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3840
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 13
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3844
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 14
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3852
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3856
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3852
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3856
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3860
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3860
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3868
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 20
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3872
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 21
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3880
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 22
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3888
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3892
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3888
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3892
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3896
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3896
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3904
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 23
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3908
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3912
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3908
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3912
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3916
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3916
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 3924
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 15
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3928
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 16
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3936
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 17
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3944
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3948
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3944
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3948
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3952
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3952
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3960
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 18
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3964
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3968
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3964
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3968
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3972
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 3972
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 3980
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 24
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 3984
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 3988
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 3984
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3988
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 3992
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 3992
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4000
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 25
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4004
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4008
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4004
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4008
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4012
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 4012
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4020
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 19
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4024
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 20
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4032
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4036
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4032
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4036
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4040
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 4040
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 4048
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 26
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4052
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 21
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4060
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4064
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4060
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4064
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4068
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 4068
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 4076
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 22
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4080
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 23
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4088
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 27
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4096
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4100
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4096
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4100
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4104
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 4104
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4112
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 28
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4116
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4120
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4116
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4120
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4124
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 4124
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4132
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 29
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4136
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 0
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4144
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4148
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4144
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4148
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4152
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 4152
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 4160
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 1
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4164
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 30
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4172
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 31
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4180
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4184
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4180
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4184
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4188
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 4188
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4196
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 2
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4200
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4204
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4200
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4204
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4208
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 4208
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 4216
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 32
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4220
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4224
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4220
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4224
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4228
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 4228
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4236
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 33
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4240
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 34
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4248
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t0, 35
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4256
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4260
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4256
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4260
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4264
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 0
-  li t4, 4264
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  flw ft0, 0(t0)
-  li t4, 4272
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t0, 3
-  li t1, 3
-  mul t0, t0, t1
-  li t4, 4276
-  add t4, s0, t4
-  sw t0, 0(t4)
-  la t0, k
-  lw t0, 0(t0)
-  li t4, 4280
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4276
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4280
-  add t4, s0, t4
-  lw t1, 0(t4)
-  add t0, t0, t1
-  li t4, 4284
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi t0, s0, 576
-  li t4, 4284
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  li t4, 4292
-  add t4, s0, t4
-  sw t0, 0(t4)
-  addi sp, sp, -448
-  li t4, 3380
-  add t4, s0, t4
-  flw fa0, 0(t4)
-  addi a1, s0, 576
-  li t4, 3384
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a1, a1, t1
-  li t4, 3408
-  add t4, s0, t4
-  lw a2, 0(t4)
-  addi a3, s0, 0
-  li t4, 3412
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add a3, a3, t1
-  li t4, 3436
-  add t4, s0, t4
-  flw fa4, 0(t4)
-  li t4, 3456
-  add t4, s0, t4
-  lw a5, 0(t4)
-  li t4, 3476
-  add t4, s0, t4
-  flw fa6, 0(t4)
-  li t4, 3496
-  add t4, s0, t4
-  flw fa7, 0(t4)
-  add t4, sp, zero
-  addi t0, s0, 0
-  li t4, 3500
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 8
-  addi t0, s0, 576
-  li t4, 3508
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 16
-  li t4, 3532
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 24
-  li t4, 3552
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 32
-  addi t0, s0, 0
-  li t4, 3556
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 40
-  addi t0, s0, 576
-  li t4, 3564
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 48
-  addi t0, s0, 576
-  li t4, 3572
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 56
-  li t4, 3596
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 64
-  addi t0, s0, 0
-  li t4, 3600
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 72
-  addi t0, s0, 0
-  li t4, 3608
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 80
-  li t4, 3632
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 88
-  li t4, 3652
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 96
-  li t4, 3672
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 104
-  addi t0, s0, 0
-  li t4, 3676
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 112
-  li t4, 3700
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 120
-  li t4, 3720
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 128
-  li t4, 3740
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 136
-  li t4, 3760
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 144
-  addi t0, s0, 576
-  li t4, 3764
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 152
-  addi t0, s0, 0
-  li t4, 3772
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 160
-  addi t0, s0, 576
-  li t4, 3780
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 168
-  addi t0, s0, 576
-  li t4, 3788
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 176
-  addi t0, s0, 0
-  li t4, 3796
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 184
-  li t4, 3820
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 192
-  li t4, 3840
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 200
-  addi t0, s0, 576
-  li t4, 3844
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 208
-  li t4, 3868
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 216
-  addi t0, s0, 0
-  li t4, 3872
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 224
-  addi t0, s0, 0
-  li t4, 3880
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 232
-  li t4, 3904
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 240
-  li t4, 3924
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 248
-  addi t0, s0, 576
-  li t4, 3928
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 256
-  addi t0, s0, 576
-  li t4, 3936
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 264
-  li t4, 3960
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 272
-  li t4, 3980
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 280
-  li t4, 4000
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 288
-  li t4, 4020
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 296
-  addi t0, s0, 576
-  li t4, 4024
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 304
-  li t4, 4048
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 312
-  addi t0, s0, 0
-  li t4, 4052
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 320
-  li t4, 4076
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 328
-  addi t0, s0, 576
-  li t4, 4080
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 336
-  addi t0, s0, 576
-  li t4, 4088
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 344
-  li t4, 4112
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 352
-  li t4, 4132
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 360
-  addi t0, s0, 0
-  li t4, 4136
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 368
-  li t4, 4160
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 376
-  addi t0, s0, 576
-  li t4, 4164
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 384
-  addi t0, s0, 0
-  li t4, 4172
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 392
-  li t4, 4196
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 400
-  li t4, 4216
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  addi t4, sp, 408
-  li t4, 4236
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 416
-  addi t0, s0, 0
-  li t4, 4240
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 424
-  addi t0, s0, 0
-  li t4, 4248
-  add t4, s0, t4
-  lw t1, 0(t4)
-  slli t1, t1, 2
-  add t0, t0, t1
-  sd t0, 0(t4)
-  addi t4, sp, 432
-  li t4, 4272
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  fsw ft0, 0(t4)
-  addi t4, sp, 440
-  li t4, 4292
-  add t4, s0, t4
-  lw t0, 0(t4)
-  sd t0, 0(t4)
-  call params_mix
-  addi sp, sp, 448
-  li t4, 4296
-  add t4, s0, t4
-  sw a0, 0(t4)
-  li t4, 4296
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 3360
-  add t4, s0, t4
-  sw t0, 0(t4)
-  flw ft0, 936(s0)
-  li t4, 4300
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t4, 4300
-  add t4, s0, t4
-  flw fa0, 0(t4)
-  call putfloat
-  li a0, 10
-  call putch
-  flw ft0, 1744(s0)
-  li t4, 4304
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t4, 4304
-  add t4, s0, t4
-  flw fa0, 0(t4)
-  call putfloat
-  li a0, 10
-  call putch
-  li t4, 3032
-  add t4, s0, t4
-  flw ft0, 0(t4)
-  li t4, 4308
-  add t4, s0, t4
-  fsw ft0, 0(t4)
-  li t4, 4308
-  add t4, s0, t4
-  flw fa0, 0(t4)
-  call putfloat
-  li a0, 10
-  call putch
-  li t4, 3360
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t4, 4312
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4312
-  add t4, s0, t4
-  lw a0, 0(t4)
-  call putint
-  li a0, 10
-  call putch
-  li t0, 0
-  li t1, 256
-  rem t0, t0, t1
-  li t4, 4316
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4316
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  add t0, t0, t1
-  li t4, 4320
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4320
-  add t4, s0, t4
-  lw t0, 0(t4)
-  li t1, 256
-  rem t0, t0, t1
-  li t4, 4324
-  add t4, s0, t4
-  sw t0, 0(t4)
-  li t4, 4324
-  add t4, s0, t4
-  lw a0, 0(t4)
-  call putint
-  li a0, 10
-  call putch
-  li a0, 0
-  li t3, 4336
-  add t3, s0, t3
-  ld ra, 0(t3)
-  li t3, 4352
-  add sp, s0, t3
-  li t3, 4344
-  add t3, s0, t3
-  ld s0, 0(t3)
-  ret
-.size main, .-main
-
diff --git a/include/mir/MIR.h b/include/mir/MIR.h
index 0ddabc8..d0539bc 100644
--- a/include/mir/MIR.h
+++ b/include/mir/MIR.h
@@ -1,5 +1,5 @@
 #pragma once
-
+#include <unordered_map>  
 #include <initializer_list>
 #include <iosfwd>
 #include <memory>
@@ -150,32 +150,37 @@ struct GlobalInfo {
 
 class Operand {
  public:
-  enum class Kind { Reg, Imm, FrameIndex, Global, Func };
+  enum class Kind { PhysReg, VirtReg, Imm, FrameIndex, Global, Func };
   
   static Operand Reg(PhysReg reg);
+  static Operand VirtReg(int index, bool is_float = false);
   static Operand Imm(int value);
-  static Operand Imm64(int64_t value);  // 新增：存储 64 位值
+  static Operand Imm64(int64_t value);
   static Operand FrameIndex(int index);
   static Operand Global(const std::string& name);
   static Operand Func(const std::string& name);
 
   Kind GetKind() const { return kind_; }
-  PhysReg GetReg() const { return reg_; }
+  PhysReg GetPhysReg() const { return reg_; }
+  int GetVirtReg() const { return imm_; }
+  bool IsVirtRegFloat() const { return is_float_; }
   int GetImm() const { return imm_; }
-  int64_t GetImm64() const { return imm64_; }  // 新增
+  int64_t GetImm64() const { return imm64_; }
   int GetFrameIndex() const { return imm_; }
   const std::string& GetGlobalName() const { return global_name_; }
   const std::string& GetFuncName() const { return func_name_; }
 
  private:
   Operand(Kind kind, PhysReg reg, int imm);
-  Operand(Kind kind, PhysReg reg, int64_t imm64);  // 新增构造函数
+  Operand(Kind kind, PhysReg reg, int64_t imm64);
   Operand(Kind kind, PhysReg reg, int imm, const std::string& name);
+  Operand(Kind kind, int virt_reg, bool is_float);
 
   Kind kind_;
   PhysReg reg_;
   int imm_;
-  int64_t imm64_;  // 新增
+  int64_t imm64_;
+  bool is_float_ = false;
   std::string global_name_;
   std::string func_name_;
 };
@@ -186,6 +191,9 @@ class MachineInstr {
 
   Opcode GetOpcode() const { return opcode_; }
   const std::vector<Operand>& GetOperands() const { return operands_; }
+  std::vector<Operand>& GetOperands() { return operands_; }
+  
+  void SetOperands(std::vector<Operand> operands) { operands_ = std::move(operands); }
 
  private:
   Opcode opcode_;
@@ -207,6 +215,9 @@ class MachineBasicBlock {
 
   MachineInstr& Append(Opcode opcode,
                        std::initializer_list<Operand> operands = {});
+  MachineInstr& InsertBefore(std::vector<MachineInstr>::iterator pos,
+                             Opcode opcode,
+                             std::initializer_list<Operand> operands = {});
 
  private:
   std::string name_;
@@ -223,6 +234,7 @@ class MachineFunction {
   MachineBasicBlock* CreateBlock(const std::string& name);
   MachineBasicBlock* GetEntry() { return entry_; }
   const MachineBasicBlock* GetEntry() const { return entry_; }
+  std::vector<std::unique_ptr<MachineBasicBlock>>& GetBlocks() { return blocks_; }
   const std::vector<std::unique_ptr<MachineBasicBlock>>& GetBlocks() const { return blocks_; }
   
   // 栈帧管理
@@ -235,6 +247,31 @@ class MachineFunction {
   void SetFrameSize(int size) { frame_size_ = size; }
   int GetLocalVarsSize() const { return local_vars_size_; }
   void SetLocalVarsSize(int s) { local_vars_size_ = s; }
+  
+  // 虚拟寄存器管理
+  int CreateVirtReg(bool is_float = false);
+  bool IsVirtRegFloat(int reg) const;
+  int GetNumVirtRegs() const { return virt_reg_types_.size(); }
+  const std::vector<bool>& GetVirtRegTypes() const { return virt_reg_types_; }
+  
+  // 物理寄存器分配结果
+  void SetPhysRegForVirt(int virt_reg, PhysReg phys_reg);
+  PhysReg GetPhysRegForVirt(int virt_reg) const;
+  bool HasPhysRegForVirt(int virt_reg) const;
+  
+  // 溢出槽管理
+  int CreateSpillSlot(bool is_float = false);
+  int GetSpillSlot(int virt_reg) const;
+  bool HasSpillSlot(int virt_reg) const;
+  void SetSpillSlot(int virt_reg, int slot);  
+  
+  void SetCalleeSavedOffset(PhysReg reg, int offset);
+  int GetCalleeSavedOffset(PhysReg reg) const;
+
+  // 保存的 callee-saved 寄存器
+  void AddCalleeSavedReg(PhysReg reg);
+  const std::vector<PhysReg>& GetCalleeSavedRegs() const { return callee_saved_regs_; }
+  
  private:
   std::string name_;
   MachineBasicBlock* entry_ = nullptr;
@@ -242,6 +279,19 @@ class MachineFunction {
   std::vector<FrameSlot> frame_slots_;
   int frame_size_ = 0;
   int local_vars_size_ = 0;
+  
+  // 虚拟寄存器
+  int next_virt_reg_ = 0;
+  std::vector<bool> virt_reg_types_;  // true = float, false = int
+  
+  // 寄存器分配结果
+  std::vector<PhysReg> virt_to_phys_;
+  std::vector<int> virt_to_spill_slot_;
+  
+  // callee-saved 寄存器
+  std::vector<PhysReg> callee_saved_regs_;
+
+  std::unordered_map<PhysReg, int> callee_saved_offsets_; 
 };
 //std::unique_ptr<MachineFunction> LowerToMIR(const ir::Module& module);
 void RunRegAlloc(MachineFunction& function);
@@ -249,4 +299,5 @@ void RunFrameLowering(MachineFunction& function);
 //void PrintAsm(const MachineFunction& function, std::ostream& os);
 std::vector<std::unique_ptr<MachineFunction>> LowerToMIR(const ir::Module& module);
 void PrintAsm(const std::vector<std::unique_ptr<MachineFunction>>& functions, std::ostream& os);
+void RunPeepholeOptimization(MachineFunction& function);
 }  // namespace mir
\ No newline at end of file
diff --git a/ir.txt b/ir.txt
deleted file mode 100644
index da044f3..0000000
--- a/ir.txt
+++ /dev/null
@@ -1,272 +0,0 @@
-@MAX = global i32 1000000000
-@TWO = global i32 2
-@THREE = global i32 3
-@FIVE = global i32 5
-
-declare void @putch(i32)
-declare void @memset(i32*, i32, i32)
-declare i32 @getfarray(float*)
-declare float @getfloat()
-declare void @putfloat(float)
-declare void @putint(i32)
-declare void @putfarray(i32, float*)
-
-define float @float_abs(float %x) {
-entry:
-  %0 = alloca float
-  store float %x, float* %0
-  %2 = load float, float* %0
-  %3 = sitofp i32 0 to float
-  %4 = fcmp olt float %2, %3
-  br i1 %4, label %L0.if.then, label %L1.if.end
-L0.if.then:
-  %6 = load float, float* %0
-  %7 = fsub float 0x0, %6
-  ret float %7
-L1.if.end:
-  %9 = load float, float* %0
-  ret float %9
-}
-
-define float @circle_area(i32 %radius) {
-entry:
-  %0 = alloca i32
-  store i32 %radius, i32* %0
-  %2 = load i32, i32* %0
-  %3 = sitofp i32 %2 to float
-  %4 = fmul float 0x400921FB60000000, %3
-  %5 = load i32, i32* %0
-  %6 = sitofp i32 %5 to float
-  %7 = fmul float %4, %6
-  %8 = load i32, i32* %0
-  %9 = load i32, i32* %0
-  %10 = mul i32 %8, %9
-  %11 = sitofp i32 %10 to float
-  %12 = fmul float %11, 0x400921FB60000000
-  %13 = fadd float %7, %12
-  %14 = sitofp i32 2 to float
-  %15 = fdiv float %13, %14
-  ret float %15
-}
-
-define i32 @float_eq(float %a, float %b) {
-entry:
-  %0 = alloca float
-  %1 = alloca float
-  store float %a, float* %0
-  store float %b, float* %1
-  %4 = load float, float* %0
-  %5 = load float, float* %1
-  %6 = fsub float %4, %5
-  %7 = call float @float_abs(float %6)
-  %8 = fcmp olt float %7, 0x3EB0C6F7A0000000
-  br i1 %8, label %L2.if.then, label %L3.if.else
-L2.if.then:
-  %10 = sitofp i32 1 to float
-  %11 = fmul float %10, 0x4000000000000000
-  %12 = sitofp i32 2 to float
-  %13 = fdiv float %11, %12
-  %14 = fptosi float %13 to i32
-  ret i32 %14
-L3.if.else:
-  ret i32 0
-L4.if.end:
-  ret i32 0
-}
-
-define void @error() {
-entry:
-  call void @putch(i32 101)
-  call void @putch(i32 114)
-  call void @putch(i32 114)
-  call void @putch(i32 111)
-  call void @putch(i32 114)
-  call void @putch(i32 10)
-  ret void
-}
-
-define void @ok() {
-entry:
-  call void @putch(i32 111)
-  call void @putch(i32 107)
-  call void @putch(i32 10)
-  ret void
-}
-
-define void @assert(i32 %cond) {
-entry:
-  %0 = alloca i32
-  store i32 %cond, i32* %0
-  %2 = load i32, i32* %0
-  %3 = icmp eq i32 %2, 0
-  %4 = zext i1 %3 to i32
-  %5 = icmp ne i32 %4, 0
-  br i1 %5, label %L5.if.then, label %L6.if.else
-L5.if.then:
-  call void @error()
-  br label %L7.if.end
-L6.if.else:
-  call void @ok()
-  br label %L7.if.end
-L7.if.end:
-  ret void
-}
-
-define void @assert_not(i32 %cond) {
-entry:
-  %0 = alloca i32
-  store i32 %cond, i32* %0
-  %2 = load i32, i32* %0
-  %3 = icmp ne i32 %2, 0
-  br i1 %3, label %L8.if.then, label %L9.if.else
-L8.if.then:
-  call void @error()
-  br label %L10.if.end
-L9.if.else:
-  call void @ok()
-  br label %L10.if.end
-L10.if.end:
-  ret void
-}
-
-define i32 @main() {
-entry:
-  %0 = alloca i32
-  %1 = alloca i32
-  %2 = alloca i32
-  %3 = alloca i32
-  %4 = alloca float, i32 10
-  %5 = alloca i32
-  %6 = alloca float
-  %7 = alloca float
-  %8 = alloca float
-  %9 = call i32 @float_eq(float 0x3FB4000000000000, float 0xC0E01D0000000000)
-  call void @assert_not(i32 %9)
-  %11 = call i32 @float_eq(float 0x4057C21FC0000000, float 0x4041475CE0000000)
-  call void @assert_not(i32 %11)
-  %13 = call i32 @float_eq(float 0x4041475CE0000000, float 0x4041475CE0000000)
-  call void @assert(i32 %13)
-  %15 = fptosi float 0x4016000000000000 to i32
-  %16 = call float @circle_area(i32 %15)
-  %17 = load i32, i32* @FIVE
-  %18 = call float @circle_area(i32 %17)
-  %19 = call i32 @float_eq(float %16, float %18)
-  call void @assert(i32 %19)
-  %21 = call i32 @float_eq(float 0x406D200000000000, float 0x40AFFE0000000000)
-  call void @assert_not(i32 %21)
-  %23 = fcmp one float 0x3FF8000000000000, 0x0
-  br i1 %23, label %L11.if.then, label %L12.if.end
-L11.if.then:
-  call void @ok()
-  br label %L12.if.end
-L12.if.end:
-  %27 = fcmp oeq float 0x400A666660000000, 0x0
-  %28 = zext i1 %27 to i32
-  %29 = icmp eq i32 %28, 0
-  %30 = zext i1 %29 to i32
-  %31 = icmp ne i32 %30, 0
-  br i1 %31, label %L13.if.then, label %L14.if.end
-L13.if.then:
-  call void @ok()
-  br label %L14.if.end
-L14.if.end:
-  %35 = fcmp one float 0x0, 0x0
-  %36 = zext i1 %35 to i32
-  store i32 %36, i32* %0
-  br i1 %35, label %L15.and.rhs, label %L16.and.end
-L15.and.rhs:
-  %39 = icmp ne i32 3, 0
-  %40 = zext i1 %39 to i32
-  store i32 %40, i32* %0
-  br label %L16.and.end
-L16.and.end:
-  %43 = load i32, i32* %0
-  %44 = icmp ne i32 %43, 0
-  br i1 %44, label %L17.if.then, label %L18.if.end
-L17.if.then:
-  call void @error()
-  br label %L18.if.end
-L18.if.end:
-  %48 = icmp ne i32 0, 0
-  %49 = zext i1 %48 to i32
-  store i32 %49, i32* %1
-  br i1 %48, label %L20.or.end, label %L19.or.rhs
-L19.or.rhs:
-  %52 = fcmp one float 0x3FD3333340000000, 0x0
-  %53 = zext i1 %52 to i32
-  store i32 %53, i32* %1
-  br label %L20.or.end
-L20.or.end:
-  %56 = load i32, i32* %1
-  %57 = icmp ne i32 %56, 0
-  br i1 %57, label %L21.if.then, label %L22.if.end
-L21.if.then:
-  call void @ok()
-  br label %L22.if.end
-L22.if.end:
-  store i32 1, i32* %2
-  store i32 0, i32* %3
-  call void @memset(float* %4, i32 0, i32 40)
-  %64 = getelementptr float, float* %4, i32 0
-  store float 0x3FF0000000000000, float* %64
-  %66 = getelementptr float, float* %4, i32 1
-  store i32 2, float* %66
-  %68 = getelementptr float, float* %4, i32 0
-  %69 = call i32 @getfarray(float* %68)
-  store i32 %69, i32* %5
-  br label %L23.while.cond
-L23.while.cond:
-  %72 = load i32, i32* %2
-  %73 = load i32, i32* @MAX
-  %74 = icmp slt i32 %72, %73
-  br i1 %74, label %L24.while.body, label %L25.while.end
-L24.while.body:
-  %76 = call float @getfloat()
-  store float %76, float* %6
-  %78 = load float, float* %6
-  %79 = fmul float 0x400921FB60000000, %78
-  %80 = load float, float* %6
-  %81 = fmul float %79, %80
-  store float %81, float* %7
-  %83 = load float, float* %6
-  %84 = fptosi float %83 to i32
-  %85 = call float @circle_area(i32 %84)
-  store float %85, float* %8
-  %87 = load i32, i32* %3
-  %88 = getelementptr float, float* %4, i32 %87
-  %89 = load float, float* %88
-  %90 = load float, float* %6
-  %91 = fadd float %89, %90
-  %92 = load i32, i32* %3
-  %93 = getelementptr float, float* %4, i32 %92
-  store float %91, float* %93
-  %95 = load float, float* %7
-  call void @putfloat(float %95)
-  call void @putch(i32 32)
-  %98 = load float, float* %8
-  %99 = fptosi float %98 to i32
-  call void @putint(i32 %99)
-  call void @putch(i32 10)
-  %102 = load i32, i32* %2
-  %103 = fsub float 0x0, 0x4024000000000000
-  %104 = fsub float 0x0, %103
-  %105 = sitofp i32 %102 to float
-  %106 = fmul float %105, %104
-  %107 = fptosi float %106 to i32
-  store i32 %107, i32* %2
-  %109 = load i32, i32* %3
-  %110 = add i32 %109, 1
-  store i32 %110, i32* %3
-  br label %L23.while.cond
-L25.while.end:
-  %113 = load i32, i32* %5
-  %114 = getelementptr float, float* %4, i32 0
-  call void @putfarray(i32 %113, float* %114)
-  %116 = srem i32 0, 256
-  %117 = add i32 %116, 256
-  %118 = srem i32 %117, 256
-  call void @putint(i32 %118)
-  call void @putch(i32 10)
-  ret i32 0
-}
-
diff --git a/output.s b/output.s
deleted file mode 100644
index de5870b..0000000
--- a/output.s
+++ /dev/null
@@ -1,309 +0,0 @@
-.text
-.global main
-.type main, @function
-main:
-  addi sp, sp, -272
-  sw ra, 264(sp)
-  sw s0, 256(sp)
-  addi a0, sp, -4
-  li a1, 0
-  li a2, 32
-  call 
-  addi a0, sp, -8
-  li a1, 0
-  li a2, 32
-  call 
-  li t2, 1
-  addi t0, sp, -8
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 2
-  addi t0, sp, -8
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 3
-  addi t0, sp, -8
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 4
-  addi t0, sp, -8
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 5
-  addi t0, sp, -8
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 6
-  addi t0, sp, -8
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 7
-  addi t0, sp, -8
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 8
-  addi t0, sp, -8
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  addi a0, sp, -44
-  li a1, 0
-  li a2, 32
-  call 
-  li t2, 1
-  addi t0, sp, -44
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 2
-  addi t0, sp, -44
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 3
-  addi t0, sp, -44
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 4
-  addi t0, sp, -44
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 5
-  addi t0, sp, -44
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 6
-  addi t0, sp, -44
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 7
-  addi t0, sp, -44
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 8
-  addi t0, sp, -44
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  addi a0, sp, -80
-  li a1, 0
-  li a2, 32
-  call 
-  li t2, 1
-  addi t0, sp, -80
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 2
-  addi t0, sp, -80
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 3
-  addi t0, sp, -80
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 5
-  addi t0, sp, -80
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 7
-  addi t0, sp, -80
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 8
-  addi t0, sp, -80
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t0, 2
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, -112(sp)
-  li t0, 1
-  lw t1, -112(sp)
-  add t0, t0, t1
-  sw t0, -116(sp)
-  addi t0, sp, -80
-  lw t1, -116(sp)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, -124(sp)
-  li t0, 2
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, -128(sp)
-  li t0, 1
-  lw t1, -128(sp)
-  add t0, t0, t1
-  sw t0, -132(sp)
-  addi t0, sp, -44
-  lw t1, -132(sp)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, -140(sp)
-  addi a0, sp, -108
-  li a1, 0
-  li a2, 32
-  call 
-  lw t2, -124(sp)
-  addi t0, sp, -108
-  li t1, 0
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  lw t2, -140(sp)
-  addi t0, sp, -108
-  li t1, 1
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 3
-  addi t0, sp, -108
-  li t1, 2
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 4
-  addi t0, sp, -108
-  li t1, 3
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 5
-  addi t0, sp, -108
-  li t1, 4
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 6
-  addi t0, sp, -108
-  li t1, 5
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 7
-  addi t0, sp, -108
-  li t1, 6
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t2, 8
-  addi t0, sp, -108
-  li t1, 7
-  slli t1, t1, 2
-  add t0, t0, t1
-  sw t2, 0(t0)
-  li t0, 3
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, -176(sp)
-  li t0, 1
-  lw t1, -176(sp)
-  add t0, t0, t1
-  sw t0, -180(sp)
-  addi t0, sp, -108
-  lw t1, -180(sp)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, -188(sp)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, -192(sp)
-  li t0, 0
-  lw t1, -192(sp)
-  add t0, t0, t1
-  sw t0, -196(sp)
-  addi t0, sp, -108
-  lw t1, -196(sp)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, -204(sp)
-  lw t0, -188(sp)
-  lw t1, -204(sp)
-  add t0, t0, t1
-  sw t0, -208(sp)
-  li t0, 0
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, -212(sp)
-  li t0, 1
-  lw t1, -212(sp)
-  add t0, t0, t1
-  sw t0, -216(sp)
-  addi t0, sp, -108
-  lw t1, -216(sp)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, -224(sp)
-  lw t0, -208(sp)
-  lw t1, -224(sp)
-  add t0, t0, t1
-  sw t0, -228(sp)
-  li t0, 2
-  li t1, 2
-  mul t0, t0, t1
-  sw t0, -232(sp)
-  li t0, 0
-  lw t1, -232(sp)
-  add t0, t0, t1
-  sw t0, -236(sp)
-  addi t0, sp, -4
-  lw t1, -236(sp)
-  slli t1, t1, 2
-  add t0, t0, t1
-  lw t0, 0(t0)
-  sw t0, -244(sp)
-  lw t0, -228(sp)
-  lw t1, -244(sp)
-  add t0, t0, t1
-  sw t0, -248(sp)
-  lw a0, -248(sp)
-  lw ra, 264(sp)
-  lw s0, 256(sp)
-  addi sp, sp, 272
-  ret
-.size main, .-main
diff --git a/scripts/mir_test.sh:Zone.Identifier b/scripts/mir_test.sh:Zone.Identifier
deleted file mode 100644
index d6c1ec682968c796b9f5e9e080cc6f674b57c766..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 25
dcma!!%Fjy;DN4*MPD?F{<>dl#JyUFr831@K2x<TT

diff --git a/src/main.cpp b/src/main.cpp
index d9a2127..41989cb 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -59,6 +59,7 @@ int main(int argc, char** argv) {
       for (auto& mf : machine_funcs) {
         mir::RunRegAlloc(*mf);
         mir::RunFrameLowering(*mf);
+        mir::RunPeepholeOptimization(*mf);
       }
       mir::PrintAsm(machine_funcs, *out);
     }
diff --git a/src/mir/AsmPrinter.cpp b/src/mir/AsmPrinter.cpp
index dad9e72..cddaca8 100644
--- a/src/mir/AsmPrinter.cpp
+++ b/src/mir/AsmPrinter.cpp
@@ -14,15 +14,19 @@ extern std::vector<mir::GlobalVarInfo> g_globalVars;
 
 namespace mir {
 namespace {
-
-const FrameSlot& GetFrameSlot(const MachineFunction& function,
-                              const Operand& operand) {
-  if (operand.GetKind() != Operand::Kind::FrameIndex) {
-    throw std::runtime_error(FormatError("mir", "期望 FrameIndex 操作数"));
+bool IsFloatPhysReg(PhysReg reg) {
+  switch (reg) {
+    case PhysReg::FT0: case PhysReg::FT1: case PhysReg::FT2: case PhysReg::FT3:
+    case PhysReg::FT4: case PhysReg::FT5: case PhysReg::FT6: case PhysReg::FT7:
+    case PhysReg::FT8: case PhysReg::FT9: case PhysReg::FT10: case PhysReg::FT11:
+    case PhysReg::FA0: case PhysReg::FA1: case PhysReg::FA2: case PhysReg::FA3:
+    case PhysReg::FA4: case PhysReg::FA5: case PhysReg::FA6: case PhysReg::FA7:
+    case PhysReg::FS0: case PhysReg::FS1:
+      return true;
+    default:
+      return false;
   }
-  return function.GetFrameSlot(operand.GetFrameIndex());
 }
-
 // 32位整数加载/存储
 void EmitStackLoad(std::ostream& os, PhysReg dst, int offset, PhysReg base = PhysReg::S0) {
   if (offset >= -2048 && offset <= 2047) {
@@ -94,9 +98,9 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
     block_names[block_ptr.get()] = block_ptr->GetName();
   }
 
-  int frame_size = function.GetFrameSize();        // 局部变量区大小（正数）
-  int local_vars = function.GetLocalVarsSize();
-  int total_frame = local_vars + 16 ;   
+  //int frame_size = function.GetFrameSize();        // 局部变量区大小（正数）
+  //int local_vars = function.GetLocalVarsSize();
+  int total_frame = function.GetFrameSize();  
   bool prologue_done = false;
 
   for (const auto& block_ptr : function.GetBlocks()) {
@@ -111,36 +115,40 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
       const auto& ops = inst.GetOperands();
       
       // 在入口块的第一条指令前输出序言
+      // 序言（prologue）
       if (!prologue_done && block.GetName() == "entry") {
-        // 分配栈帧：sp -= total_frame
+        // 分配栈帧
         if (total_frame <= 2047) {
           os << "  addi sp, sp, -" << total_frame << "\n";
         } else {
           os << "  li t4, -" << total_frame << "\n";
           os << "  add sp, sp, t4\n";
         }
-        
-        // 保存 ra 和 s0（在局部变量区之后，即 sp + frame_size 处）
-        // ra 保存在 sp + frame_size
-        // s0 保存在 sp + frame_size + 8
-        int ra_offset = local_vars;
-        int s0_offset = local_vars + 8;
-        
-        if (ra_offset <= 2047) {
-          os << "  sd ra, " << ra_offset << "(sp)\n";
-        } else {
-          os << "  li t4, " << ra_offset << "\n";
-          os << "  add t4, sp, t4\n";
-          os << "  sd ra, 0(t4)\n";
-        }
-        
-        if (s0_offset <= 2047) {
-          os << "  sd s0, " << s0_offset << "(sp)\n";
-        } else {
-          os << "  li t4, " << s0_offset << "\n";
-          os << "  add t4, sp, t4\n";
-          os << "  sd s0, 0(t4)\n";
+        // 保存 callee-saved 寄存器（包括 ra 和 s0）
+        for (PhysReg reg : function.GetCalleeSavedRegs()) {
+          int offset = function.GetCalleeSavedOffset(reg);
+          bool isFloat = (reg >= PhysReg::FT0 && reg <= PhysReg::FT11) ||
+                        (reg >= PhysReg::FA0 && reg <= PhysReg::FA7) ||
+                        (reg == PhysReg::FS0 || reg == PhysReg::FS1);
+          if (isFloat) {
+            if (offset <= 2047)
+              os << "  fsw " << PhysRegName(reg) << ", " << offset << "(sp)\n";
+            else {
+              os << "  li t4, " << offset << "\n";
+              os << "  add t4, sp, t4\n";
+              os << "  fsw " << PhysRegName(reg) << ", 0(t4)\n";
+            }
+          } else {
+            if (offset <= 2047)
+              os << "  sd " << PhysRegName(reg) << ", " << offset << "(sp)\n";
+            else {
+              os << "  li t4, " << offset << "\n";
+              os << "  add t4, sp, t4\n";
+              os << "  sd " << PhysRegName(reg) << ", 0(t4)\n";
+            }
+          }
         }
+        // 建立帧指针
         os << "  mv s0, sp\n";
         prologue_done = true;
       }
@@ -151,42 +159,42 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           break;
         
         case Opcode::MovImm:
-          os << "  li " << PhysRegName(ops.at(0).GetReg()) << ", "
+          os << "  li " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
              << ops.at(1).GetImm() << "\n";
           break;
         
         case Opcode::Load: {
-            if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Reg) {
-                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", 0(" << PhysRegName(ops[1].GetReg()) << ")\n";
+            if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::PhysReg) {
+                os << "  ld " << PhysRegName(ops[0].GetPhysReg()) << ", 0(" << PhysRegName(ops[1].GetPhysReg()) << ")\n";
             } /*else if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Imm) {
                 // 用于调用者 outgoing 存储的占位偏移（将在 Outgoing 中修正）
                 int offset = ops[1].GetImm();  // 实际偏移 = local_vars + 16 + offset
-                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", " << offset << "(sp)\n";*/
+                os << "  ld " << PhysRegName(ops[0].GetPhysReg()) << ", " << offset << "(sp)\n";*/
             else {
                 int frame_idx = ops[1].GetFrameIndex();
                 const auto& slot = function.GetFrameSlot(frame_idx);
-                if (slot.size == 8) EmitStackLoad64(os, ops[0].GetReg(), slot.offset);
-                else EmitStackLoad(os, ops[0].GetReg(), slot.offset);
+                if (slot.size == 8) EmitStackLoad64(os, ops[0].GetPhysReg(), slot.offset);
+                else EmitStackLoad(os, ops[0].GetPhysReg(), slot.offset);
             }
             break;
         }
 
         case Opcode::Store: {
-            if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Reg) {
-                os << "  sd " << PhysRegName(ops[0].GetReg()) << ", 0(" << PhysRegName(ops[1].GetReg()) << ")\n";
+            if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::PhysReg) {
+                os << "  sd " << PhysRegName(ops[0].GetPhysReg()) << ", 0(" << PhysRegName(ops[1].GetPhysReg()) << ")\n";
             } /*else if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Imm) {
                 int offset = ops[1].GetImm();
                 // 实际偏移需在 AsmPrinter 中加上 local_vars+16，这里简单先直接用 offset（动态修正稍复杂）
                 // 临时方案：直接生成 sw t0, offset(sp)，但 offset 应为 local_vars+16=?
                 // 由于 AsmPrinter 中可访问 function.GetLocalVarsSize()，我们计算：
                 int actual_offset = function.GetLocalVarsSize() + 16 + offset;
-                if (actual_offset <= 2047) os << "  sd " << PhysRegName(ops[0].GetReg()) << ", " << actual_offset << "(sp)\n";
+                if (actual_offset <= 2047) os << "  sd " << PhysRegName(ops[0].GetPhysReg()) << ", " << actual_offset << "(sp)\n";
                 else {  }*/
             else {
                 int frame_idx = ops[1].GetFrameIndex();
                 const auto& slot = function.GetFrameSlot(frame_idx);
-                if (slot.size == 8) EmitStackStore64(os, ops[0].GetReg(), slot.offset);
-                else EmitStackStore(os, ops[0].GetReg(), slot.offset);
+                if (slot.size == 8) EmitStackStore64(os, ops[0].GetPhysReg(), slot.offset);
+                else EmitStackStore(os, ops[0].GetPhysReg(), slot.offset);
             }
             break;
         }
@@ -200,18 +208,18 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
             int caller_offset = total_frame + argv_index * 8;
             // 加载到 T0
             if (caller_offset <= 2047) {
-                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", " << caller_offset << "(s0)\n";
+                os << "  ld " << PhysRegName(ops[0].GetPhysReg()) << ", " << caller_offset << "(s0)\n";
             } else {
                 os << "  li t4, " << caller_offset << "\n";
                 os << "  add t4, s0, t4\n";
-                os << "  ld " << PhysRegName(ops[0].GetReg()) << ", 0(t4)\n";
+                os << "  ld " << PhysRegName(ops[0].GetPhysReg()) << ", 0(t4)\n";
             }
             // 再存入本地槽
             const auto& slot = function.GetFrameSlot(dst_slot);
             if (slot.size == 8) {
-                EmitStackStore64(os, ops[0].GetReg(), slot.offset);
+                EmitStackStore64(os, ops[0].GetPhysReg(), slot.offset);
             } else {
-                EmitStackStore(os, ops[0].GetReg(), slot.offset);
+                EmitStackStore(os, ops[0].GetPhysReg(), slot.offset);
             }
             break;
         }
@@ -223,104 +231,104 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           int caller_offset = total_frame + argv_index * 8;
           // 使用 s0 保证稳定
           if (caller_offset <= 2047) {
-            os << "  flw " << PhysRegName(ops.at(0).GetReg()) << ", " << caller_offset << "(s0)\n";
+            os << "  flw " << PhysRegName(ops.at(0).GetPhysReg()) << ", " << caller_offset << "(s0)\n";
           } else {
             os << "  li t4, " << caller_offset << "\n";
             os << "  add t4, s0, t4\n";
-            os << "  flw " << PhysRegName(ops.at(0).GetReg()) << ", 0(t4)\n";
+            os << "  flw " << PhysRegName(ops.at(0).GetPhysReg()) << ", 0(t4)\n";
           }
           const auto& slot = function.GetFrameSlot(dst_slot);
-          EmitStackStoreFloat(os, ops.at(0).GetReg(), slot.offset);
+          EmitStackStoreFloat(os, ops.at(0).GetPhysReg(), slot.offset);
           break;
         }
 
         case Opcode::Add:
-          os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
-             << PhysRegName(ops.at(2).GetReg()) << "\n";
+          os << "  add " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           break;
         case Opcode::Addi:
-          os << "  addi " << PhysRegName(ops[0].GetReg()) << ", "
-            << PhysRegName(ops[1].GetReg()) << ", "
+          os << "  addi " << PhysRegName(ops[0].GetPhysReg()) << ", "
+            << PhysRegName(ops[1].GetPhysReg()) << ", "
             << ops[2].GetImm() << "\n";
           break;
         case Opcode::Sub:
-          os << "  sub " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
-             << PhysRegName(ops.at(2).GetReg()) << "\n";
+          os << "  sub " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           break;
         
         case Opcode::Mul: {
           if (ops.size() > 2 && ops.at(2).GetKind() == Operand::Kind::Imm) {
-            os << "  mul " << PhysRegName(ops.at(0).GetReg()) << ", "
-               << PhysRegName(ops.at(1).GetReg()) << ", "
+            os << "  mul " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+               << PhysRegName(ops.at(1).GetPhysReg()) << ", "
                << ops.at(2).GetImm() << "\n";
           } else {
-            os << "  mul " << PhysRegName(ops.at(0).GetReg()) << ", "
-               << PhysRegName(ops.at(1).GetReg()) << ", "
-               << PhysRegName(ops.at(2).GetReg()) << "\n";
+            os << "  mul " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+               << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+               << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           }
           break;
         }
         
         case Opcode::Div:
-          os << "  div " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
-             << PhysRegName(ops.at(2).GetReg()) << "\n";
+          os << "  div " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           break;
         
         case Opcode::Rem:
-          os << "  rem " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
-             << PhysRegName(ops.at(2).GetReg()) << "\n";
+          os << "  rem " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           break;
         
         case Opcode::Slt:
-          os << "  slt " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
-             << PhysRegName(ops.at(2).GetReg()) << "\n";
+          os << "  slt " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           break;
         
         case Opcode::Slti:
-          os << "  slti " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
+          os << "  slti " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
              << ops.at(2).GetImm() << "\n";
           break;
         
         case Opcode::Sltu:
-          os << "  sltu " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
-             << PhysRegName(ops.at(2).GetReg()) << "\n";
+          os << "  sltu " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(2).GetPhysReg()) << "\n";
           break;
         
         case Opcode::Sltiu:
-          os << "  sltiu " << PhysRegName(ops.at(0).GetReg()) << ", "
-            << PhysRegName(ops.at(1).GetReg()) << ", "
+          os << "  sltiu " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+            << PhysRegName(ops.at(1).GetPhysReg()) << ", "
             << ops.at(2).GetImm() << "\n";
           break;
         
         case Opcode::Xori:
-          os << "  xori " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
+          os << "  xori " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
              << ops.at(2).GetImm() << "\n";
           break;
         
         case Opcode::LoadGlobalAddr: {
           std::string global_name = ops.at(1).GetGlobalName();
-          os << "  la " << PhysRegName(ops.at(0).GetReg()) << ", " << global_name << "\n";
+          os << "  la " << PhysRegName(ops.at(0).GetPhysReg()) << ", " << global_name << "\n";
           break;
         }
         
         case Opcode::LoadGlobal:
           // 全局变量加载 - 使用 lw（32位）
-          os << "  lw " << PhysRegName(ops.at(0).GetReg()) << ", 0("
-             << PhysRegName(ops.at(1).GetReg()) << ")\n";
+          os << "  lw " << PhysRegName(ops.at(0).GetPhysReg()) << ", 0("
+             << PhysRegName(ops.at(1).GetPhysReg()) << ")\n";
           break;
         
         case Opcode::StoreGlobal: {
           std::string global_name = ops.at(1).GetGlobalName();
           os << "  la t1, " << global_name << "\n";
-          os << "  sw " << PhysRegName(ops.at(0).GetReg()) << ", 0(t1)\n";
+          os << "  sw " << PhysRegName(ops.at(0).GetPhysReg()) << ", 0(t1)\n";
           break;
         }
         
@@ -329,12 +337,12 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
         
         case Opcode::LoadIndirect:
           // 间接加载 - 使用 lw（32位）
-          os << "  lw " << PhysRegName(ops.at(0).GetReg()) << ", 0("
-             << PhysRegName(ops.at(1).GetReg()) << ")\n";
+          os << "  lw " << PhysRegName(ops.at(0).GetPhysReg()) << ", 0("
+             << PhysRegName(ops.at(1).GetPhysReg()) << ")\n";
           break;
         case Opcode::LoadIndirectFloat:
-          os << "  flw " << PhysRegName(ops[0].GetReg()) << ", 0("
-             << PhysRegName(ops[1].GetReg()) << ")\n";
+          os << "  flw " << PhysRegName(ops[0].GetPhysReg()) << ", 0("
+             << PhysRegName(ops[1].GetPhysReg()) << ")\n";
           break;
         case Opcode::Call: {
           std::string func_name = "memset"; // 默认值
@@ -350,62 +358,58 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
           const auto& slot = function.GetFrameSlot(frame_idx);
           // 计算地址（64 位），offset 是正数
           if (slot.offset <= 2047) {
-            os << "  addi " << PhysRegName(ops.at(0).GetReg()) << ", s0, " << slot.offset << "\n";
+            os << "  addi " << PhysRegName(ops.at(0).GetPhysReg()) << ", s0, " << slot.offset << "\n";
           } else {
-            os << "  li " << PhysRegName(ops.at(0).GetReg()) << ", " << slot.offset << "\n";
-            os << "  add " << PhysRegName(ops.at(0).GetReg()) << ", s0, " 
-              << PhysRegName(ops.at(0).GetReg()) << "\n";
+            os << "  li " << PhysRegName(ops.at(0).GetPhysReg()) << ", " << slot.offset << "\n";
+            os << "  add " << PhysRegName(ops.at(0).GetPhysReg()) << ", s0, " 
+              << PhysRegName(ops.at(0).GetPhysReg()) << "\n";
           }
           break;
         }
         
         case Opcode::Slli:
-          os << "  slli " << PhysRegName(ops.at(0).GetReg()) << ", "
-             << PhysRegName(ops.at(1).GetReg()) << ", "
+          os << "  slli " << PhysRegName(ops.at(0).GetPhysReg()) << ", "
+             << PhysRegName(ops.at(1).GetPhysReg()) << ", "
              << ops.at(2).GetImm() << "\n";
           break;
         
         case Opcode::StoreIndirect:
           // 间接存储 - 使用 sw（32位）
-          os << "  sw " << PhysRegName(ops.at(0).GetReg()) << ", 0("
-             << PhysRegName(ops.at(1).GetReg()) << ")\n";
+          os << "  sw " << PhysRegName(ops.at(0).GetPhysReg()) << ", 0("
+             << PhysRegName(ops.at(1).GetPhysReg()) << ")\n";
           break;
         case Opcode::StoreIndirectFloat:
-          os << "  fsw " << PhysRegName(ops[0].GetReg()) << ", 0("
-             << PhysRegName(ops[1].GetReg()) << ")\n";
-          break;
-        case Opcode::Ret:{
-          // 恢复 ra 和 s0
-          int ra_offset = local_vars;
-          int s0_offset = local_vars + 8;
-          
-          if (ra_offset <= 2047) {
-            os << "  ld ra, " << ra_offset << "(s0)\n";
-          } else {
-            os << "  li t3, " << ra_offset << "\n";
-            os << "  add t3, s0, t3\n";
-            os << "  ld ra, 0(t3)\n";
-          }
-
-           // 恢复 sp
-          if (total_frame <= 2047) {
-            os << "  addi sp, s0, " << total_frame << "\n";
-          } else {
-            os << "  li t3, " << total_frame << "\n";
-            os << "  add sp, s0, t3\n";
-          }
-
-          if (s0_offset <= 2047) {
-            os << "  ld s0, " << s0_offset << "(s0)\n";
-          } else {
-            os << "  li t3, " << s0_offset << "\n";
-            os << "  add t3, s0, t3\n";
-            os << "  ld s0, 0(t3)\n";
-          }
-          
-          
-          os << "  ret\n";
+          os << "  fsw " << PhysRegName(ops[0].GetPhysReg()) << ", 0("
+             << PhysRegName(ops[1].GetPhysReg()) << ")\n";
           break;
+        case Opcode::Ret: {
+            int total_frame = function.GetFrameSize();
+            // 1. 恢复除 ra 和 s0 以外的 callee-saved 寄存器
+            for (PhysReg reg : function.GetCalleeSavedRegs()) {
+                if (reg == PhysReg::RA || reg == PhysReg::S0) continue;
+                int offset = function.GetCalleeSavedOffset(reg);
+                bool isFloat = IsFloatPhysReg(reg);
+                if (isFloat) {
+                    EmitStackLoadFloat(os, reg, offset, PhysReg::S0);
+                } else {
+                    EmitStackLoad64(os, reg, offset, PhysReg::S0);
+                }
+            }
+            // 2. 恢复 ra
+            int ra_offset = function.GetCalleeSavedOffset(PhysReg::RA);
+            EmitStackLoad64(os, PhysReg::RA, ra_offset, PhysReg::S0);
+            // 3. 恢复 sp
+            if (total_frame <= 2047) {
+                os << "  addi sp, s0, " << total_frame << "\n";
+            } else {
+                os << "  li t3, " << total_frame << "\n";
+                os << "  add sp, s0, t3\n";
+            }
+            // 4. 恢复 s0
+            int s0_offset = function.GetCalleeSavedOffset(PhysReg::S0);
+            EmitStackLoad64(os, PhysReg::S0, s0_offset, PhysReg::S0);
+            os << "  ret\n";
+            break;
         }
         
         case Opcode::Br: {
@@ -426,7 +430,7 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
             // 生成一个唯一的本地标签作为跳板
             static int condbr_id = 0;
             std::string temp_label = ".L_condbr_" + std::to_string(condbr_id++);
-            os << "  bnez " << PhysRegName(ops[0].GetReg()) << ", " << temp_label << "\n";
+            os << "  bnez " << PhysRegName(ops[0].GetPhysReg()) << ", " << temp_label << "\n";
             os << "  j " << false_it->second << "\n";
             os << temp_label << ":\n";
             os << "  j " << true_it->second << "\n";
@@ -435,91 +439,91 @@ void PrintAsmFunction(const MachineFunction& function, std::ostream& os) {
         
         // 浮点运算
         case Opcode::FAdd:
-          os << "  fadd.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  fadd.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FSub:
-          os << "  fsub.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  fsub.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FMul:
-          os << "  fmul.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  fmul.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FDiv:
-          os << "  fdiv.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  fdiv.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
 
         case Opcode::FEq:
-          os << "  feq.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  feq.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FLt:
-          os << "  flt.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  flt.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FLe:
-          os << "  fle.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << ", "
-             << PhysRegName(ops[2].GetReg()) << "\n";
+          os << "  fle.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << ", "
+             << PhysRegName(ops[2].GetPhysReg()) << "\n";
           break;
 
         case Opcode::FMov:
-          os << "  fmv.s " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << "\n";
+          os << "  fmv.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FMovWX:
-          os << "  fmv.w.x " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << "\n";
+          os << "  fmv.w.x " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FMovXW:
-          os << "  fmv.x.w " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << "\n";
+          os << "  fmv.x.w " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << "\n";
           break;
 
         case Opcode::SIToFP:
-          os << "  fcvt.s.w " << PhysRegName(ops[0].GetReg()) << ", "
-             << PhysRegName(ops[1].GetReg()) << "\n";
+          os << "  fcvt.s.w " << PhysRegName(ops[0].GetPhysReg()) << ", "
+             << PhysRegName(ops[1].GetPhysReg()) << "\n";
           break;
         
         case Opcode::FPToSI:
-          os << "  fcvt.w.s " << PhysRegName(ops[0].GetReg()) << ", "
-            << PhysRegName(ops[1].GetReg()) << ", rtz\n";
+          os << "  fcvt.w.s " << PhysRegName(ops[0].GetPhysReg()) << ", "
+            << PhysRegName(ops[1].GetPhysReg()) << ", rtz\n";
           break;
 
         case Opcode::LoadFloat:
-          if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Reg) {
-            os << "  flw " << PhysRegName(ops[0].GetReg()) << ", 0("
-              << PhysRegName(ops[1].GetReg()) << ")\n";
+          if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::PhysReg) {
+            os << "  flw " << PhysRegName(ops[0].GetPhysReg()) << ", 0("
+              << PhysRegName(ops[1].GetPhysReg()) << ")\n";
           } else {
             int frame_idx = ops[1].GetFrameIndex();
             const auto& slot = function.GetFrameSlot(frame_idx);
-            EmitStackLoadFloat(os, ops[0].GetReg(), slot.offset);
+            EmitStackLoadFloat(os, ops[0].GetPhysReg(), slot.offset);
           }
           break;
         
         case Opcode::StoreFloat:
-          if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::Reg) {
-            os << "  fsw " << PhysRegName(ops[0].GetReg()) << ", 0("
-              << PhysRegName(ops[1].GetReg()) << ")\n";
+          if (ops.size() == 2 && ops[1].GetKind() == Operand::Kind::PhysReg) {
+            os << "  fsw " << PhysRegName(ops[0].GetPhysReg()) << ", 0("
+              << PhysRegName(ops[1].GetPhysReg()) << ")\n";
           } else {
             int frame_idx = ops[1].GetFrameIndex();
             const auto& slot = function.GetFrameSlot(frame_idx);
-            EmitStackStoreFloat(os, ops[0].GetReg(), slot.offset);
+            EmitStackStoreFloat(os, ops[0].GetPhysReg(), slot.offset);
           }
           break;
         
diff --git a/src/mir/CMakeLists.txt b/src/mir/CMakeLists.txt
index 2535e20..296c567 100644
--- a/src/mir/CMakeLists.txt
+++ b/src/mir/CMakeLists.txt
@@ -8,6 +8,7 @@ add_library(mir_core STATIC
   RegAlloc.cpp
   FrameLowering.cpp
   AsmPrinter.cpp
+  Peephole.cpp  
 )
 
 target_link_libraries(mir_core PUBLIC
diff --git a/src/mir/FrameLowering.cpp b/src/mir/FrameLowering.cpp
index 9e04a74..74db50c 100644
--- a/src/mir/FrameLowering.cpp
+++ b/src/mir/FrameLowering.cpp
@@ -1,5 +1,5 @@
 #include "mir/MIR.h"
-
+#include <algorithm>
 #include <stdexcept>
 #include <vector>
 
@@ -15,35 +15,58 @@ int AlignTo(int value, int align) {
 }  // namespace
 
 void RunFrameLowering(MachineFunction& function) {
+  auto& saved = const_cast<std::vector<PhysReg>&>(function.GetCalleeSavedRegs());
+  auto has_reg = [&](PhysReg r) {
+      return std::find(saved.begin(), saved.end(), r) != saved.end();
+  };
+  if (!has_reg(PhysReg::RA)) saved.push_back(PhysReg::RA);
+  if (!has_reg(PhysReg::S0)) saved.push_back(PhysReg::S0);
   int cursor = 0;
-  const auto& slots = function.GetFrameSlots();
+  std::vector<FrameSlot> newSlots;
 
-  // 为每个栈槽分配偏移
-  for (const auto& slot : slots) {
+  // 1. 为每个现有栈槽分配偏移（包括局部变量、溢出槽）
+  for (const auto& slot : function.GetFrameSlots()) {
     int align = slot.size;
     cursor = AlignTo(cursor, align);
-    function.GetFrameSlot(slot.index).offset = cursor;
+    FrameSlot newSlot = slot;
+    newSlot.offset = cursor;
+    newSlots.push_back(newSlot);
     cursor += slot.size;
   }
 
-  // 局部变量区按 16 字节对齐
-  int local_vars_size = AlignTo(cursor, 16);
-  function.SetLocalVarsSize(local_vars_size);
-
-  // 总帧大小 = 局部变量区 + 16（保存 ra 和 s0）
-  function.SetFrameSize(local_vars_size + 16);
-
-  // 插入 Prologue/Epilogue 占位符（原逻辑）
-  auto& insts = function.GetEntry()->GetInstructions();
-  std::vector<MachineInstr> lowered;
-  lowered.emplace_back(Opcode::Prologue);
-  for (const auto& inst : insts) {
-    if (inst.GetOpcode() == Opcode::Ret) {
-      lowered.emplace_back(Opcode::Epilogue);
-    }
-    lowered.push_back(inst);
+  // 2. 为 callee-saved 寄存器分配空间（先计算需要保存的寄存器）
+  const auto& savedRegs = function.GetCalleeSavedRegs();
+  int savedSize = 0;
+  for (PhysReg reg : savedRegs) {
+    bool isFloat = (reg >= PhysReg::FT0 && reg <= PhysReg::FT11) ||
+                   (reg >= PhysReg::FA0 && reg <= PhysReg::FA7) ||
+                   (reg == PhysReg::FS0 || reg == PhysReg::FS1);
+    savedSize += isFloat ? 4 : 8;
+  }
+  
+  // 3. 总帧大小 = 局部变量区 + callee-saved 区 + 对齐
+  int calleeSavedArea = AlignTo(savedSize, 8);
+  cursor = AlignTo(cursor, 16);       // 局部变量区对齐
+  int localVarsSize = cursor;
+  function.SetLocalVarsSize(localVarsSize);
+  
+  int totalFrame = localVarsSize + calleeSavedArea;
+  function.SetFrameSize(totalFrame);
+
+  // 4. 记录每个 callee-saved 寄存器的偏移（相对于 sp）
+  int offset = localVarsSize;
+  for (PhysReg reg : savedRegs) {
+    bool isFloat = (reg >= PhysReg::FT0 && reg <= PhysReg::FT11) ||
+                   (reg >= PhysReg::FA0 && reg <= PhysReg::FA7) ||
+                   (reg == PhysReg::FS0 || reg == PhysReg::FS1);
+    int size = isFloat ? 4 : 8;
+    function.SetCalleeSavedOffset(reg, offset);
+    offset += size;
+  }
+  const_cast<std::vector<FrameSlot>&>(function.GetFrameSlots()).clear();
+  for (auto& slot : newSlots) {
+    const_cast<std::vector<FrameSlot>&>(function.GetFrameSlots()).push_back(slot);
   }
-  insts = std::move(lowered);
 }
 
 }  // namespace mir
\ No newline at end of file
diff --git a/src/mir/MIRBasicBlock.cpp b/src/mir/MIRBasicBlock.cpp
index d42b4b3..d88dfbb 100644
--- a/src/mir/MIRBasicBlock.cpp
+++ b/src/mir/MIRBasicBlock.cpp
@@ -13,4 +13,11 @@ MachineInstr& MachineBasicBlock::Append(Opcode opcode,
   return instructions_.back();
 }
 
+MachineInstr& MachineBasicBlock::InsertBefore(std::vector<MachineInstr>::iterator pos,
+                                               Opcode opcode,
+                                               std::initializer_list<Operand> operands) {
+  auto it = instructions_.insert(pos, MachineInstr(opcode, std::vector<Operand>(operands)));
+  return *it;
+}
+
 }  // namespace mir
diff --git a/src/mir/MIRFunction.cpp b/src/mir/MIRFunction.cpp
index d506f9a..0155e4c 100644
--- a/src/mir/MIRFunction.cpp
+++ b/src/mir/MIRFunction.cpp
@@ -2,6 +2,7 @@
 
 #include <stdexcept>
 #include <utility>
+#include <algorithm>
 
 #include "utils/Log.h"
 
@@ -39,4 +40,85 @@ const FrameSlot& MachineFunction::GetFrameSlot(int index) const {
   return frame_slots_[index];
 }
 
+// 虚拟寄存器管理
+int MachineFunction::CreateVirtReg(bool is_float) {
+  int reg = next_virt_reg_++;
+  virt_reg_types_.push_back(is_float);
+  virt_to_phys_.push_back(PhysReg::ZERO);
+  virt_to_spill_slot_.push_back(-1);
+  return reg;
+}
+
+bool MachineFunction::IsVirtRegFloat(int reg) const {
+  if (reg < 0 || reg >= static_cast<int>(virt_reg_types_.size())) {
+    throw std::runtime_error(FormatError("mir", "非法 VirtReg"));
+  }
+  return virt_reg_types_[reg];
+}
+
+// 物理寄存器分配结果
+void MachineFunction::SetPhysRegForVirt(int virt_reg, PhysReg phys_reg) {
+  if (virt_reg < 0 || virt_reg >= static_cast<int>(virt_to_phys_.size())) {
+    throw std::runtime_error(FormatError("mir", "非法 VirtReg"));
+  }
+  virt_to_phys_[virt_reg] = phys_reg;
+}
+
+PhysReg MachineFunction::GetPhysRegForVirt(int virt_reg) const {
+  if (virt_reg < 0 || virt_reg >= static_cast<int>(virt_to_phys_.size())) {
+    throw std::runtime_error(FormatError("mir", "非法 VirtReg"));
+  }
+  return virt_to_phys_[virt_reg];
+}
+
+bool MachineFunction::HasPhysRegForVirt(int virt_reg) const {
+  if (virt_reg < 0 || virt_reg >= static_cast<int>(virt_to_phys_.size())) {
+    return false;
+  }
+  return virt_to_phys_[virt_reg] != PhysReg::ZERO;
+}
+
+// 溢出槽管理
+int MachineFunction::CreateSpillSlot(bool is_float) {
+  return CreateFrameIndex(is_float ? 8 : 4);
+}
+
+int MachineFunction::GetSpillSlot(int virt_reg) const {
+  if (virt_reg < 0 || virt_reg >= static_cast<int>(virt_to_spill_slot_.size())) {
+    throw std::runtime_error(FormatError("mir", "非法 VirtReg"));
+  }
+  return virt_to_spill_slot_[virt_reg];
+}
+
+bool MachineFunction::HasSpillSlot(int virt_reg) const {
+  if (virt_reg < 0 || virt_reg >= static_cast<int>(virt_to_spill_slot_.size())) {
+    return false;
+  }
+  return virt_to_spill_slot_[virt_reg] != -1;
+}
+
+void MachineFunction::SetSpillSlot(int virt_reg, int slot) {
+  if (virt_reg < 0 || virt_reg >= static_cast<int>(virt_to_spill_slot_.size())) {
+    throw std::runtime_error(FormatError("mir", "非法 VirtReg"));
+  }
+  virt_to_spill_slot_[virt_reg] = slot;
+}
+
+// callee-saved 寄存器
+void MachineFunction::AddCalleeSavedReg(PhysReg reg) {
+  if (std::find(callee_saved_regs_.begin(), callee_saved_regs_.end(), reg) == callee_saved_regs_.end()) {
+    callee_saved_regs_.push_back(reg);
+  }
+}
+void MachineFunction::SetCalleeSavedOffset(PhysReg reg, int offset) {
+  callee_saved_offsets_[reg] = offset;
+}
+
+int MachineFunction::GetCalleeSavedOffset(PhysReg reg) const {
+  auto it = callee_saved_offsets_.find(reg);
+  if (it == callee_saved_offsets_.end()) {
+    throw std::runtime_error(FormatError("mir", "找不到 callee-saved 寄存器的偏移"));
+  }
+  return it->second;
+}
 }  // namespace mir
\ No newline at end of file
diff --git a/src/mir/MIRInstr.cpp b/src/mir/MIRInstr.cpp
index a4d6e61..e3dfed0 100644
--- a/src/mir/MIRInstr.cpp
+++ b/src/mir/MIRInstr.cpp
@@ -1,6 +1,7 @@
 #include "mir/MIR.h"
 
 #include <utility>
+#include <stdexcept>
 
 namespace mir {
 
@@ -8,11 +9,16 @@ Operand::Operand(Kind kind, PhysReg reg, int imm)
     : kind_(kind), reg_(reg), imm_(imm) {}
 Operand::Operand(Kind kind, PhysReg reg, int64_t imm64)
     : kind_(kind), reg_(PhysReg::ZERO), imm_(0), imm64_(imm64) {}
-// 新增构造函数
 Operand::Operand(Kind kind, PhysReg reg, int imm, const std::string& name)
     : kind_(kind), reg_(reg), imm_(imm), global_name_(name) {}
+Operand::Operand(Kind kind, int virt_reg, bool is_float)
+    : kind_(kind), reg_(PhysReg::ZERO), imm_(virt_reg), is_float_(is_float) {}
 
-Operand Operand::Reg(PhysReg reg) { return Operand(Kind::Reg, reg, 0); }
+Operand Operand::Reg(PhysReg reg) { return Operand(Kind::PhysReg, reg, 0); }
+
+Operand Operand::VirtReg(int index, bool is_float) {
+  return Operand(Kind::VirtReg, index, is_float);
+}
 
 Operand Operand::Imm(int value) {
   return Operand(Kind::Imm, PhysReg::ZERO, value);
@@ -24,7 +30,6 @@ Operand Operand::FrameIndex(int index) {
   return Operand(Kind::FrameIndex, PhysReg::ZERO, index);
 }
 
-// 新增
 Operand Operand::Global(const std::string& name) {
   return Operand(Kind::Global, PhysReg::ZERO, 0, name);
 }
diff --git a/src/mir/Peephole.cpp b/src/mir/Peephole.cpp
new file mode 100644
index 0000000..cb65796
--- /dev/null
+++ b/src/mir/Peephole.cpp
@@ -0,0 +1,65 @@
+// Peephole.cpp - 保守优化版（仅启用安全规则）
+#include "mir/MIR.h"
+#include <algorithm>
+#include <vector>
+#include <cstdint>
+
+namespace mir {
+namespace {
+
+// 判断两个地址操作数是否指向同一内存位置（考虑栈槽和物理寄存器）
+bool SameAddr(const Operand& a, const Operand& b) {
+    if (a.GetKind() != b.GetKind()) return false;
+    if (a.GetKind() == Operand::Kind::PhysReg)
+        return a.GetPhysReg() == b.GetPhysReg();
+    if (a.GetKind() == Operand::Kind::FrameIndex)
+        return a.GetFrameIndex() == b.GetFrameIndex();
+    return false;
+}
+
+// 规则2：消除死存储（连续两次存储到同一地址，删除第一次）
+// 例如: sw t0, addr; sw t1, addr  -> 仅保留第二次存储
+bool EliminateDeadStore(std::vector<MachineInstr>& instrs) {
+    bool changed = false;
+    for (size_t i = 0; i + 1 < instrs.size(); ) {
+        auto& inst1 = instrs[i];
+        auto& inst2 = instrs[i+1];
+        Opcode op1 = inst1.GetOpcode();
+        Opcode op2 = inst2.GetOpcode();
+        bool is_store1 = (op1 == Opcode::Store || op1 == Opcode::StoreFloat);
+        bool is_store2 = (op2 == Opcode::Store || op2 == Opcode::StoreFloat);
+        if (is_store1 && is_store2) {
+            const auto& ops1 = inst1.GetOperands();
+            const auto& ops2 = inst2.GetOperands();
+            // 两个存储操作数至少都有两个操作数 [value, addr]
+            if (ops1.size() >= 2 && ops2.size() >= 2 &&
+                SameAddr(ops1[1], ops2[1])) {
+                // 第一次存储被第二次覆盖，删除第一次
+                instrs.erase(instrs.begin() + i);
+                changed = true;
+                continue;  // 重新检查当前位置
+            }
+        }
+        ++i;
+    }
+    return changed;
+}
+} // anonymous namespace
+
+void RunPeepholeOptimization(MachineFunction& function) {
+    bool overallChanged = true;
+    while (overallChanged) {
+        overallChanged = false;
+        for (auto& blockPtr : function.GetBlocks()) {
+            auto& instrs = blockPtr->GetInstructions();
+            bool changed = false;
+            // 启用死存储消除
+            changed |= EliminateDeadStore(instrs);
+            // changed |= EliminateRedundantStoreLoad(instrs);
+            if (changed)
+                overallChanged = true;
+        }
+    }
+}
+
+} // namespace mir
\ No newline at end of file
diff --git a/src/mir/RegAlloc.cpp b/src/mir/RegAlloc.cpp
index 7bba9a0..9a81282 100644
--- a/src/mir/RegAlloc.cpp
+++ b/src/mir/RegAlloc.cpp
@@ -1,91 +1,344 @@
+// RegAlloc.cpp - 修复版
 #include "mir/MIR.h"
-
+#include <algorithm>
+#include <map>
+#include <set>
+#include <vector>
+#include <queue>
 #include <stdexcept>
-
 #include "utils/Log.h"
 
 namespace mir {
 namespace {
 
-bool IsAllowedReg(PhysReg reg) {
-  switch (reg) {
-    // 临时寄存器
-    case PhysReg::T0:
-    case PhysReg::T1:
-    case PhysReg::T2:
-    case PhysReg::T3:
-    case PhysReg::T4:
-    case PhysReg::T5:
-    case PhysReg::T6:
-    // 参数/返回值寄存器
-    case PhysReg::A0:
-    case PhysReg::A1:
-    case PhysReg::A2:
-    case PhysReg::A3:
-    case PhysReg::A4:
-    case PhysReg::A5:
-    case PhysReg::A6:
-    case PhysReg::A7:
-    // 保存寄存器
-    case PhysReg::S0:
-    case PhysReg::S1:
-    case PhysReg::S2:
-    case PhysReg::S3:
-    case PhysReg::S4:
-    case PhysReg::S5:
-    case PhysReg::S6:
-    case PhysReg::S7:
-    case PhysReg::S8:
-    case PhysReg::S9:
-    case PhysReg::S10:
-    case PhysReg::S11:
-    // 特殊寄存器
-    case PhysReg::ZERO:
-    case PhysReg::RA:
-    case PhysReg::SP:
-    case PhysReg::GP:
-    case PhysReg::TP:
-    case PhysReg::FT0:
-    case PhysReg::FT1:
-    case PhysReg::FT2:
-    case PhysReg::FT3:
-    case PhysReg::FT4:
-    case PhysReg::FT5:
-    case PhysReg::FT6:
-    case PhysReg::FT7:
-    case PhysReg::FT8:
-    case PhysReg::FT9:
-    case PhysReg::FT10:
-    case PhysReg::FT11:
-    // 浮点保存寄存器
-    case PhysReg::FS0:
-    case PhysReg::FS1:
-    // 浮点参数寄存器
-    case PhysReg::FA0:
-    case PhysReg::FA1:
-    case PhysReg::FA2:
-    case PhysReg::FA3:
-    case PhysReg::FA4:
-    case PhysReg::FA5:
-    case PhysReg::FA6:
-    case PhysReg::FA7:
-      return true;
-  }
-  return false;
+// ---------- 物理寄存器集合（排除临时寄存器）----------
+std::vector<PhysReg> GetAllocatableIntRegs() {
+    return {
+        PhysReg::T0, PhysReg::T1, PhysReg::T2, PhysReg::T3,
+        // T4, T5 保留为临时寄存器，不分配
+        PhysReg::T6,
+        PhysReg::A0, PhysReg::A1, PhysReg::A2, PhysReg::A3,
+        PhysReg::A4, PhysReg::A5, PhysReg::A6, PhysReg::A7,
+        PhysReg::S1, PhysReg::S2, PhysReg::S3, PhysReg::S4,
+        PhysReg::S5, PhysReg::S6, PhysReg::S7, PhysReg::S8,
+        PhysReg::S9, PhysReg::S10, PhysReg::S11
+    };
 }
 
-}  // namespace
+std::vector<PhysReg> GetAllocatableFloatRegs() {
+    return {
+        PhysReg::FT0, PhysReg::FT1, PhysReg::FT2, PhysReg::FT3,
+        PhysReg::FT4, PhysReg::FT5, PhysReg::FT6, PhysReg::FT7,
+        // FT8, FT9 保留为临时寄存器
+        PhysReg::FT10, PhysReg::FT11,
+        PhysReg::FA0, PhysReg::FA1, PhysReg::FA2, PhysReg::FA3,
+        PhysReg::FA4, PhysReg::FA5, PhysReg::FA6, PhysReg::FA7,
+        PhysReg::FS0, PhysReg::FS1
+    };
+}
 
-void RunRegAlloc(MachineFunction& function) {
-  // 修复：GetEntry() 返回指针，使用 ->
-  for (const auto& inst : function.GetEntry()->GetInstructions()) {
-    for (const auto& operand : inst.GetOperands()) {
-      if (operand.GetKind() == Operand::Kind::Reg &&
-          !IsAllowedReg(operand.GetReg())) {
-        throw std::runtime_error(FormatError("mir", "寄存器分配失败"));
-      }
+bool IsCallerSaved(PhysReg reg) {
+    if (reg >= PhysReg::T0 && reg <= PhysReg::T6) return true;
+    if (reg >= PhysReg::A0 && reg <= PhysReg::A7) return true;
+    if (reg >= PhysReg::FT0 && reg <= PhysReg::FT11) return true;
+    if (reg >= PhysReg::FA0 && reg <= PhysReg::FA7) return true;
+    return false;
+}
+
+// 临时寄存器（分配时排除）
+const PhysReg kIntTempLoad = PhysReg::T4;   // 整数加载临时
+const PhysReg kIntTempStore = PhysReg::T5;  // 整数存储临时
+const PhysReg kFloatTempLoad = PhysReg::FT8; // 浮点加载临时
+const PhysReg kFloatTempStore = PhysReg::FT9; // 浮点存储临时
+
+// 活跃区间（扩展，预计算跨调用标志）
+struct LiveInterval {
+    int vreg;
+    int start;
+    int end;
+    bool is_float;
+    bool crosses_call;
+
+    LiveInterval(int r, int s, int e, bool f, bool cc = false)
+        : vreg(r), start(s), end(e), is_float(f), crosses_call(cc) {}
+
+    bool operator<(const LiveInterval& other) const { return start < other.start; }
+};
+
+// 收集指令位置及Call信息
+struct InstrInfo {
+    MachineInstr* instr;
+    int pos;
+    bool is_call;
+};
+
+std::vector<InstrInfo> CollectInstructions(MachineFunction& func) {
+    std::vector<InstrInfo> result;
+    int pos = 0;
+    for (auto& block : func.GetBlocks()) {
+        for (auto& instr : block->GetInstructions()) {
+            result.push_back({&instr, pos++, instr.GetOpcode() == Opcode::Call});
+        }
+    }
+    return result;
+}
+
+// 计算活跃区间，同时记录是否跨越Call
+void ComputeLiveIntervals(MachineFunction& func,
+                          std::vector<LiveInterval>& intervals,
+                          std::vector<int>& call_positions) {
+    std::map<int, int> first_def, last_use;
+    auto instrs = CollectInstructions(func);
+    call_positions.clear();
+    for (const auto& info : instrs) {
+        if (info.is_call)
+            call_positions.push_back(info.pos);
+    }
+
+    for (const auto& info : instrs) {
+        const auto& ops = info.instr->GetOperands();
+        // 定义点：通常第一个操作数为写（简化处理）
+        if (!ops.empty() && ops[0].GetKind() == Operand::Kind::VirtReg) {
+            int vreg = ops[0].GetVirtReg();
+            if (first_def.find(vreg) == first_def.end())
+                first_def[vreg] = info.pos;
+        }
+        // 使用点
+        for (size_t i = 0; i < ops.size(); ++i) {
+            if (ops[i].GetKind() == Operand::Kind::VirtReg) {
+                int vreg = ops[i].GetVirtReg();
+                last_use[vreg] = info.pos;
+            }
+        }
+    }
+
+    // 构建区间并判断是否跨越Call
+    for (int vreg = 0; vreg < func.GetNumVirtRegs(); ++vreg) {
+        int s = 0, e = 0;
+        auto def_it = first_def.find(vreg);
+        auto use_it = last_use.find(vreg);
+        if (def_it == first_def.end()) {
+            s = 0;
+            e = (use_it != last_use.end()) ? use_it->second : 0;
+        } else {
+            s = def_it->second;
+            e = (use_it != last_use.end()) ? use_it->second : s;
+        }
+        bool crosses = false;
+        for (int pos : call_positions) {
+            if (pos > s && pos < e) { crosses = true; break; }
+        }
+        intervals.emplace_back(vreg, s, e, func.IsVirtRegFloat(vreg), crosses);
     }
-  }
+    std::sort(intervals.begin(), intervals.end());
+}
+
+// 线性扫描分配（分离整数/浮点活跃列表）
+void LinearScanRegisterAllocation(MachineFunction& func,
+                                  const std::vector<LiveInterval>& intervals,
+                                  const std::vector<int>& call_positions) {
+    auto all_int = GetAllocatableIntRegs();
+    auto all_float = GetAllocatableFloatRegs();
+    std::vector<PhysReg> free_int = all_int;
+    std::vector<PhysReg> free_float = all_float;
+
+    struct ActiveInterval {
+        LiveInterval interval;
+        PhysReg reg;
+        ActiveInterval(LiveInterval i, PhysReg r) : interval(i), reg(r) {}
+    };
+    std::vector<ActiveInterval> active_int, active_float;
+
+    for (const auto& interval : intervals) {
+        auto& active_list = interval.is_float ? active_float : active_int;
+        auto& free_list = interval.is_float ? free_float : free_int;
+
+        // 1. 移除已过期的活跃区间
+        auto it = active_list.begin();
+        while (it != active_list.end()) {
+            if (it->interval.end < interval.start) {
+                free_list.push_back(it->reg);
+                it = active_list.erase(it);
+            } else {
+                ++it;
+            }
+        }
+
+        // 2. 确定可用寄存器（考虑跨调用约束）
+        std::vector<PhysReg> eligible;
+        for (PhysReg r : free_list) {
+            if (interval.crosses_call && IsCallerSaved(r))
+                continue;
+            eligible.push_back(r);
+        }
+
+        if (!eligible.empty()) {
+            // 分配第一个可用寄存器
+            PhysReg reg = eligible.front();
+            free_list.erase(std::find(free_list.begin(), free_list.end(), reg));
+            func.SetPhysRegForVirt(interval.vreg, reg);
+            active_list.emplace_back(interval, reg);
+            // 记录 callee-saved 寄存器
+            if (!interval.is_float && reg >= PhysReg::S1 && reg <= PhysReg::S11)
+                func.AddCalleeSavedReg(reg);
+            if (interval.is_float && (reg == PhysReg::FS0 || reg == PhysReg::FS1))
+                func.AddCalleeSavedReg(reg);
+        } else {
+            // 无可用寄存器，需要溢出：选择结束点最远的活跃区间
+            auto spill_candidate = active_list.end();
+            int farthest_end = -1;
+            for (auto it2 = active_list.begin(); it2 != active_list.end(); ++it2) {
+                if (it2->interval.end > farthest_end) {
+                    farthest_end = it2->interval.end;
+                    spill_candidate = it2;
+                }
+            }
+            if (spill_candidate != active_list.end() && spill_candidate->interval.end > interval.end) {
+                // 溢出旧区间，将其寄存器转给新区间
+                PhysReg reg = spill_candidate->reg;
+                // 清除被溢出区间的物理映射
+                func.SetPhysRegForVirt(spill_candidate->interval.vreg, PhysReg::ZERO);
+                func.SetSpillSlot(spill_candidate->interval.vreg,
+                                  func.CreateSpillSlot(spill_candidate->interval.is_float));
+                active_list.erase(spill_candidate);
+                // 分配寄存器给当前区间
+                func.SetPhysRegForVirt(interval.vreg, reg);
+                active_list.emplace_back(interval, reg);
+                // 记录 callee-saved
+                if (!interval.is_float && reg >= PhysReg::S1 && reg <= PhysReg::S11)
+                    func.AddCalleeSavedReg(reg);
+                if (interval.is_float && (reg == PhysReg::FS0 || reg == PhysReg::FS1))
+                    func.AddCalleeSavedReg(reg);
+            } else {
+                // 溢出当前区间
+                func.SetSpillSlot(interval.vreg,
+                                  func.CreateSpillSlot(interval.is_float));
+                // 不分配物理寄存器，保持 ZERO
+            }
+        }
+    }
+}
+
+// 插入溢出代码（使用两个不同的临时寄存器，避免冲突）
+// RegAlloc.cpp - 修复 InsertSpillReload
+void InsertSpillReload(MachineFunction& func) {
+    for (auto& block : func.GetBlocks()) {
+        auto& instrs = block->GetInstructions();
+        
+        // 使用索引遍历，避免迭代器失效
+        for (size_t idx = 0; idx < instrs.size(); ++idx) {
+            auto& instr = instrs[idx];
+            auto& ops = instr.GetOperands();
+            
+            // 第一遍：替换有物理寄存器的虚拟寄存器
+            for (size_t i = 0; i < ops.size(); ++i) {
+                if (ops[i].GetKind() == Operand::Kind::VirtReg) {
+                    int vreg = ops[i].GetVirtReg();
+                    if (func.HasPhysRegForVirt(vreg)) {
+                        const_cast<Operand&>(ops[i]) = Operand::Reg(func.GetPhysRegForVirt(vreg));
+                    }
+                }
+            }
+        }
+        
+        // 第二遍：处理溢出（使用新的指令列表）
+        std::vector<MachineInstr> new_instrs;
+        
+        for (size_t idx = 0; idx < instrs.size(); ++idx) {
+            auto& instr = instrs[idx];
+            auto& ops = instr.GetOperands();
+            
+            bool is_store = (instr.GetOpcode() == Opcode::Store ||
+                             instr.GetOpcode() == Opcode::StoreFloat);
+            bool is_call = (instr.GetOpcode() == Opcode::Call);
+            bool is_ret = (instr.GetOpcode() == Opcode::Ret);
+            
+            // 收集需要加载的操作数（读操作）
+            std::vector<std::pair<size_t, int>> reads;
+            // 收集需要存储的操作数（写操作）
+            std::vector<std::pair<size_t, int>> writes;
+            
+            for (size_t i = 0; i < ops.size(); ++i) {
+                if (ops[i].GetKind() == Operand::Kind::VirtReg) {
+                    int vreg = ops[i].GetVirtReg();
+                    if (func.HasSpillSlot(vreg)) {
+                        bool is_write = (i == 0 && !is_store && !is_call && !is_ret);
+                        if (is_write) {
+                            writes.push_back({i, vreg});
+                        } else {
+                            reads.push_back({i, vreg});
+                        }
+                    }
+                }
+            }
+            
+            // 为每个读操作插入 load 指令
+            for (auto& read : reads) {
+                int vreg = read.second;
+                int slot = func.GetSpillSlot(vreg);
+                bool is_float = func.IsVirtRegFloat(vreg);
+                PhysReg temp = is_float ? kFloatTempLoad : kIntTempLoad;
+                auto load_op = is_float ? Opcode::LoadFloat : Opcode::Load;
+                
+                new_instrs.emplace_back(load_op, 
+                    std::vector<Operand>{Operand::Reg(temp), Operand::FrameIndex(slot)});
+            }
+            
+            // 复制当前指令，并替换操作数
+            MachineInstr new_instr = instr;
+            auto& new_ops = const_cast<std::vector<Operand>&>(new_instr.GetOperands());
+            
+            for (auto& read : reads) {
+                int vreg = read.second;
+                bool is_float = func.IsVirtRegFloat(vreg);
+                PhysReg temp = is_float ? kFloatTempLoad : kIntTempLoad;
+                new_ops[read.first] = Operand::Reg(temp);
+            }
+            
+            for (auto& write : writes) {
+                int vreg = write.second;
+                bool is_float = func.IsVirtRegFloat(vreg);
+                PhysReg temp = is_float ? kFloatTempStore : kIntTempStore;
+                new_ops[write.first] = Operand::Reg(temp);
+            }
+            
+            new_instrs.push_back(new_instr);
+            
+            // 为每个写操作插入 store 指令
+            for (auto& write : writes) {
+                int vreg = write.second;
+                int slot = func.GetSpillSlot(vreg);
+                bool is_float = func.IsVirtRegFloat(vreg);
+                PhysReg temp = is_float ? kFloatTempStore : kIntTempStore;
+                auto store_op = is_float ? Opcode::StoreFloat : Opcode::Store;
+                
+                new_instrs.emplace_back(store_op,
+                    std::vector<Operand>{Operand::Reg(temp), Operand::FrameIndex(slot)});
+            }
+        }
+        
+        // 替换指令列表
+        instrs = std::move(new_instrs);
+    }
+}
+
+} // namespace
+
+void RunRegAlloc(MachineFunction& function) {
+    if (function.GetNumVirtRegs() == 0)
+        return;
+
+    // 1. 计算活跃区间和 Call 位置
+    std::vector<LiveInterval> intervals;
+    std::vector<int> call_positions;
+    ComputeLiveIntervals(function, intervals, call_positions);
+
+    // 2. 线性扫描分配
+    LinearScanRegisterAllocation(function, intervals, call_positions);
+
+    // 3. 插入溢出代码
+    InsertSpillReload(function);
+    RunPeepholeOptimization(function);
 }
 
-}  // namespace mir
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+} // namespace mir
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